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c090b8e2f0ef2f5408bb8eed2c5010eabd5ee970
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35
36 #include <llvm-c/Core.h>
37 #include <llvm-c/TargetMachine.h>
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "r600d_common.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48
49 void radv_shader_variant_destroy(struct radv_device *device,
50 struct radv_shader_variant *variant);
51
52 static const struct nir_shader_compiler_options nir_options = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp32 = true,
56 .lower_fsat = true,
57 .lower_fdiv = true,
58 .lower_sub = true,
59 .lower_pack_snorm_2x16 = true,
60 .lower_pack_snorm_4x8 = true,
61 .lower_pack_unorm_2x16 = true,
62 .lower_pack_unorm_4x8 = true,
63 .lower_unpack_snorm_2x16 = true,
64 .lower_unpack_snorm_4x8 = true,
65 .lower_unpack_unorm_2x16 = true,
66 .lower_unpack_unorm_4x8 = true,
67 .lower_extract_byte = true,
68 .lower_extract_word = true,
69 .max_unroll_iterations = 32
70 };
71
72 VkResult radv_CreateShaderModule(
73 VkDevice _device,
74 const VkShaderModuleCreateInfo* pCreateInfo,
75 const VkAllocationCallbacks* pAllocator,
76 VkShaderModule* pShaderModule)
77 {
78 RADV_FROM_HANDLE(radv_device, device, _device);
79 struct radv_shader_module *module;
80
81 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
82 assert(pCreateInfo->flags == 0);
83
84 module = vk_alloc2(&device->alloc, pAllocator,
85 sizeof(*module) + pCreateInfo->codeSize, 8,
86 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
87 if (module == NULL)
88 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
89
90 module->nir = NULL;
91 module->size = pCreateInfo->codeSize;
92 memcpy(module->data, pCreateInfo->pCode, module->size);
93
94 _mesa_sha1_compute(module->data, module->size, module->sha1);
95
96 *pShaderModule = radv_shader_module_to_handle(module);
97
98 return VK_SUCCESS;
99 }
100
101 void radv_DestroyShaderModule(
102 VkDevice _device,
103 VkShaderModule _module,
104 const VkAllocationCallbacks* pAllocator)
105 {
106 RADV_FROM_HANDLE(radv_device, device, _device);
107 RADV_FROM_HANDLE(radv_shader_module, module, _module);
108
109 if (!module)
110 return;
111
112 vk_free2(&device->alloc, pAllocator, module);
113 }
114
115
116 static void
117 radv_pipeline_destroy(struct radv_device *device,
118 struct radv_pipeline *pipeline,
119 const VkAllocationCallbacks* allocator)
120 {
121 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
122 if (pipeline->shaders[i])
123 radv_shader_variant_destroy(device, pipeline->shaders[i]);
124
125 if (pipeline->gs_copy_shader)
126 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
127
128 vk_free2(&device->alloc, allocator, pipeline);
129 }
130
131 void radv_DestroyPipeline(
132 VkDevice _device,
133 VkPipeline _pipeline,
134 const VkAllocationCallbacks* pAllocator)
135 {
136 RADV_FROM_HANDLE(radv_device, device, _device);
137 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
138
139 if (!_pipeline)
140 return;
141
142 radv_pipeline_destroy(device, pipeline, pAllocator);
143 }
144
145
146 static void
147 radv_optimize_nir(struct nir_shader *shader)
148 {
149 bool progress;
150
151 do {
152 progress = false;
153
154 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
155 NIR_PASS_V(shader, nir_lower_64bit_pack);
156 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
157 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
158
159 NIR_PASS(progress, shader, nir_copy_prop);
160 NIR_PASS(progress, shader, nir_opt_remove_phis);
161 NIR_PASS(progress, shader, nir_opt_dce);
162 if (nir_opt_trivial_continues(shader)) {
163 progress = true;
164 NIR_PASS(progress, shader, nir_copy_prop);
165 NIR_PASS(progress, shader, nir_opt_dce);
166 }
167 NIR_PASS(progress, shader, nir_opt_if);
168 NIR_PASS(progress, shader, nir_opt_dead_cf);
169 NIR_PASS(progress, shader, nir_opt_cse);
170 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
171 NIR_PASS(progress, shader, nir_opt_algebraic);
172 NIR_PASS(progress, shader, nir_opt_constant_folding);
173 NIR_PASS(progress, shader, nir_opt_undef);
174 NIR_PASS(progress, shader, nir_opt_conditional_discard);
175 if (shader->options->max_unroll_iterations) {
176 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
177 }
178 } while (progress);
179 }
180
181 static nir_shader *
182 radv_shader_compile_to_nir(struct radv_device *device,
183 struct radv_shader_module *module,
184 const char *entrypoint_name,
185 gl_shader_stage stage,
186 const VkSpecializationInfo *spec_info,
187 bool dump)
188 {
189 if (strcmp(entrypoint_name, "main") != 0) {
190 radv_finishme("Multiple shaders per module not really supported");
191 }
192
193 nir_shader *nir;
194 nir_function *entry_point;
195 if (module->nir) {
196 /* Some things such as our meta clear/blit code will give us a NIR
197 * shader directly. In that case, we just ignore the SPIR-V entirely
198 * and just use the NIR shader */
199 nir = module->nir;
200 nir->options = &nir_options;
201 nir_validate_shader(nir);
202
203 assert(exec_list_length(&nir->functions) == 1);
204 struct exec_node *node = exec_list_get_head(&nir->functions);
205 entry_point = exec_node_data(nir_function, node, node);
206 } else {
207 uint32_t *spirv = (uint32_t *) module->data;
208 assert(module->size % 4 == 0);
209
210 if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV)
211 radv_print_spirv(module, stderr);
212
213 uint32_t num_spec_entries = 0;
214 struct nir_spirv_specialization *spec_entries = NULL;
215 if (spec_info && spec_info->mapEntryCount > 0) {
216 num_spec_entries = spec_info->mapEntryCount;
217 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
218 for (uint32_t i = 0; i < num_spec_entries; i++) {
219 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
220 const void *data = spec_info->pData + entry.offset;
221 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
222
223 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
224 if (spec_info->dataSize == 8)
225 spec_entries[i].data64 = *(const uint64_t *)data;
226 else
227 spec_entries[i].data32 = *(const uint32_t *)data;
228 }
229 }
230 const struct nir_spirv_supported_extensions supported_ext = {
231 .draw_parameters = true,
232 .float64 = true,
233 .image_read_without_format = true,
234 .image_write_without_format = true,
235 .tessellation = true,
236 .int64 = true,
237 .multiview = true,
238 .variable_pointers = true,
239 };
240 entry_point = spirv_to_nir(spirv, module->size / 4,
241 spec_entries, num_spec_entries,
242 stage, entrypoint_name, &supported_ext, &nir_options);
243 nir = entry_point->shader;
244 assert(nir->stage == stage);
245 nir_validate_shader(nir);
246
247 free(spec_entries);
248
249 /* We have to lower away local constant initializers right before we
250 * inline functions. That way they get properly initialized at the top
251 * of the function and not at the top of its caller.
252 */
253 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
254 NIR_PASS_V(nir, nir_lower_returns);
255 NIR_PASS_V(nir, nir_inline_functions);
256
257 /* Pick off the single entrypoint that we want */
258 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
259 if (func != entry_point)
260 exec_node_remove(&func->node);
261 }
262 assert(exec_list_length(&nir->functions) == 1);
263 entry_point->name = ralloc_strdup(entry_point, "main");
264
265 NIR_PASS_V(nir, nir_remove_dead_variables,
266 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
267
268 /* Now that we've deleted all but the main function, we can go ahead and
269 * lower the rest of the constant initializers.
270 */
271 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
272 NIR_PASS_V(nir, nir_lower_system_values);
273 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
274 }
275
276 /* Vulkan uses the separate-shader linking model */
277 nir->info.separate_shader = true;
278
279 nir_shader_gather_info(nir, entry_point->impl);
280
281 nir_variable_mode indirect_mask = 0;
282 indirect_mask |= nir_var_shader_in;
283 indirect_mask |= nir_var_local;
284
285 nir_lower_indirect_derefs(nir, indirect_mask);
286
287 static const nir_lower_tex_options tex_options = {
288 .lower_txp = ~0,
289 };
290
291 nir_lower_tex(nir, &tex_options);
292
293 nir_lower_vars_to_ssa(nir);
294 nir_lower_var_copies(nir);
295 nir_lower_global_vars_to_local(nir);
296 nir_remove_dead_variables(nir, nir_var_local);
297 radv_optimize_nir(nir);
298
299 if (dump)
300 nir_print_shader(nir, stderr);
301
302 return nir;
303 }
304
305 static const char *radv_get_shader_name(struct radv_shader_variant *var,
306 gl_shader_stage stage)
307 {
308 switch (stage) {
309 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
310 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
311 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
312 case MESA_SHADER_COMPUTE: return "Compute Shader";
313 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
314 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
315 default:
316 return "Unknown shader";
317 };
318
319 }
320 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
321 {
322 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
323 struct radv_shader_variant *var;
324 struct ac_shader_config *conf;
325 int i;
326 FILE *file = stderr;
327 unsigned max_simd_waves;
328 unsigned lds_per_wave = 0;
329
330 switch (device->physical_device->rad_info.family) {
331 /* These always have 8 waves: */
332 case CHIP_POLARIS10:
333 case CHIP_POLARIS11:
334 case CHIP_POLARIS12:
335 max_simd_waves = 8;
336 break;
337 default:
338 max_simd_waves = 10;
339 }
340
341 for (i = 0; i < MESA_SHADER_STAGES; i++) {
342 if (!pipeline->shaders[i])
343 continue;
344 var = pipeline->shaders[i];
345
346 conf = &var->config;
347
348 if (i == MESA_SHADER_FRAGMENT) {
349 lds_per_wave = conf->lds_size * lds_increment +
350 align(var->info.fs.num_interp * 48, lds_increment);
351 }
352
353 if (conf->num_sgprs) {
354 if (device->physical_device->rad_info.chip_class >= VI)
355 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
356 else
357 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
358 }
359
360 if (conf->num_vgprs)
361 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
362
363 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
364 * that PS can use.
365 */
366 if (lds_per_wave)
367 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
368
369 fprintf(file, "\n%s:\n",
370 radv_get_shader_name(var, i));
371 if (i == MESA_SHADER_FRAGMENT) {
372 fprintf(file, "*** SHADER CONFIG ***\n"
373 "SPI_PS_INPUT_ADDR = 0x%04x\n"
374 "SPI_PS_INPUT_ENA = 0x%04x\n",
375 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
376 }
377 fprintf(file, "*** SHADER STATS ***\n"
378 "SGPRS: %d\n"
379 "VGPRS: %d\n"
380 "Spilled SGPRs: %d\n"
381 "Spilled VGPRs: %d\n"
382 "Code Size: %d bytes\n"
383 "LDS: %d blocks\n"
384 "Scratch: %d bytes per wave\n"
385 "Max Waves: %d\n"
386 "********************\n\n\n",
387 conf->num_sgprs, conf->num_vgprs,
388 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
389 conf->lds_size, conf->scratch_bytes_per_wave,
390 max_simd_waves);
391 }
392 }
393
394 void radv_shader_variant_destroy(struct radv_device *device,
395 struct radv_shader_variant *variant)
396 {
397 if (!p_atomic_dec_zero(&variant->ref_count))
398 return;
399
400 mtx_lock(&device->shader_slab_mutex);
401 list_del(&variant->slab_list);
402 mtx_unlock(&device->shader_slab_mutex);
403
404 free(variant);
405 }
406
407 static void radv_fill_shader_variant(struct radv_device *device,
408 struct radv_shader_variant *variant,
409 struct ac_shader_binary *binary,
410 gl_shader_stage stage)
411 {
412 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
413 unsigned vgpr_comp_cnt = 0;
414
415 if (scratch_enabled && !device->llvm_supports_spill)
416 radv_finishme("shader scratch support only available with LLVM 4.0");
417
418 variant->code_size = binary->code_size;
419 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
420 S_00B12C_SCRATCH_EN(scratch_enabled);
421
422 switch (stage) {
423 case MESA_SHADER_TESS_EVAL:
424 vgpr_comp_cnt = 3;
425 /* fallthrough */
426 case MESA_SHADER_TESS_CTRL:
427 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
428 break;
429 case MESA_SHADER_VERTEX:
430 case MESA_SHADER_GEOMETRY:
431 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
432 break;
433 case MESA_SHADER_FRAGMENT:
434 break;
435 case MESA_SHADER_COMPUTE:
436 variant->rsrc2 |=
437 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
438 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
439 S_00B84C_TG_SIZE_EN(1) |
440 S_00B84C_LDS_SIZE(variant->config.lds_size);
441 break;
442 default:
443 unreachable("unsupported shader type");
444 break;
445 }
446
447 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
448 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
449 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
450 S_00B848_DX10_CLAMP(1) |
451 S_00B848_FLOAT_MODE(variant->config.float_mode);
452
453 void *ptr = radv_alloc_shader_memory(device, variant);
454 memcpy(ptr, binary->code, binary->code_size);
455 }
456
457 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
458 struct nir_shader *shader,
459 struct radv_pipeline_layout *layout,
460 const struct ac_shader_variant_key *key,
461 void** code_out,
462 unsigned *code_size_out,
463 bool dump)
464 {
465 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
466 enum radeon_family chip_family = device->physical_device->rad_info.family;
467 LLVMTargetMachineRef tm;
468 if (!variant)
469 return NULL;
470
471 struct ac_nir_compiler_options options = {0};
472 options.layout = layout;
473 if (key)
474 options.key = *key;
475
476 struct ac_shader_binary binary;
477 enum ac_target_machine_options tm_options = 0;
478 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
479 options.family = chip_family;
480 options.chip_class = device->physical_device->rad_info.chip_class;
481 options.supports_spill = device->llvm_supports_spill;
482 if (options.supports_spill)
483 tm_options |= AC_TM_SUPPORTS_SPILL;
484 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
485 tm_options |= AC_TM_SISCHED;
486 tm = ac_create_target_machine(chip_family, tm_options);
487 ac_compile_nir_shader(tm, &binary, &variant->config,
488 &variant->info, shader, &options, dump);
489 LLVMDisposeTargetMachine(tm);
490
491 radv_fill_shader_variant(device, variant, &binary, shader->stage);
492
493 if (code_out) {
494 *code_out = binary.code;
495 *code_size_out = binary.code_size;
496 } else
497 free(binary.code);
498 free(binary.config);
499 free(binary.rodata);
500 free(binary.global_symbol_offsets);
501 free(binary.relocs);
502 free(binary.disasm_string);
503 variant->ref_count = 1;
504 return variant;
505 }
506
507 static struct radv_shader_variant *
508 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
509 struct nir_shader *nir,
510 void** code_out,
511 unsigned *code_size_out,
512 bool dump_shader,
513 bool multiview)
514 {
515 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
516 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
517 LLVMTargetMachineRef tm;
518 if (!variant)
519 return NULL;
520
521 struct ac_nir_compiler_options options = {0};
522 struct ac_shader_binary binary;
523 enum ac_target_machine_options tm_options = 0;
524 options.family = chip_family;
525 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
526 options.key.has_multiview_view_index = multiview;
527 if (options.supports_spill)
528 tm_options |= AC_TM_SUPPORTS_SPILL;
529 if (pipeline->device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
530 tm_options |= AC_TM_SISCHED;
531 tm = ac_create_target_machine(chip_family, tm_options);
532 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
533 LLVMDisposeTargetMachine(tm);
534
535 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
536
537 if (code_out) {
538 *code_out = binary.code;
539 *code_size_out = binary.code_size;
540 } else
541 free(binary.code);
542 free(binary.config);
543 free(binary.rodata);
544 free(binary.global_symbol_offsets);
545 free(binary.relocs);
546 free(binary.disasm_string);
547 variant->ref_count = 1;
548 return variant;
549 }
550
551 static struct radv_shader_variant *
552 radv_pipeline_compile(struct radv_pipeline *pipeline,
553 struct radv_pipeline_cache *cache,
554 struct radv_shader_module *module,
555 const char *entrypoint,
556 gl_shader_stage stage,
557 const VkSpecializationInfo *spec_info,
558 struct radv_pipeline_layout *layout,
559 const struct ac_shader_variant_key *key)
560 {
561 unsigned char sha1[20];
562 unsigned char gs_copy_sha1[20];
563 struct radv_shader_variant *variant;
564 nir_shader *nir;
565 void *code = NULL;
566 unsigned code_size = 0;
567 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
568
569 if (module->nir)
570 _mesa_sha1_compute(module->nir->info.name,
571 strlen(module->nir->info.name),
572 module->sha1);
573
574 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
575 if (stage == MESA_SHADER_GEOMETRY)
576 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
577 layout, key, 1);
578
579 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
580 cache,
581 sha1);
582
583 if (stage == MESA_SHADER_GEOMETRY) {
584 pipeline->gs_copy_shader =
585 radv_create_shader_variant_from_pipeline_cache(
586 pipeline->device,
587 cache,
588 gs_copy_sha1);
589 }
590
591 if (variant &&
592 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
593 return variant;
594
595 nir = radv_shader_compile_to_nir(pipeline->device,
596 module, entrypoint, stage,
597 spec_info, dump);
598 if (nir == NULL)
599 return NULL;
600
601 if (!variant) {
602 variant = radv_shader_variant_create(pipeline->device, nir,
603 layout, key, &code,
604 &code_size, dump);
605 }
606
607 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
608 void *gs_copy_code = NULL;
609 unsigned gs_copy_code_size = 0;
610 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
611 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump, key->has_multiview_view_index);
612
613 if (pipeline->gs_copy_shader) {
614 pipeline->gs_copy_shader =
615 radv_pipeline_cache_insert_shader(cache,
616 gs_copy_sha1,
617 pipeline->gs_copy_shader,
618 gs_copy_code,
619 gs_copy_code_size);
620 }
621
622 free(gs_copy_code);
623 }
624 if (!module->nir)
625 ralloc_free(nir);
626
627 if (variant)
628 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
629 code, code_size);
630
631 if (code)
632 free(code);
633 return variant;
634 }
635
636 static struct ac_shader_variant_key
637 radv_compute_tes_key(bool as_es, bool export_prim_id)
638 {
639 struct ac_shader_variant_key key;
640 memset(&key, 0, sizeof(key));
641 key.tes.as_es = as_es;
642 /* export prim id only happens when no geom shader */
643 if (!as_es)
644 key.tes.export_prim_id = export_prim_id;
645 return key;
646 }
647
648 static struct ac_shader_variant_key
649 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
650 {
651 struct ac_shader_variant_key key;
652 memset(&key, 0, sizeof(key));
653 key.tcs.primitive_mode = primitive_mode;
654 key.tcs.input_vertices = input_vertices;
655 return key;
656 }
657
658 static void
659 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
660 struct radv_pipeline_cache *cache,
661 struct radv_shader_module *tcs_module,
662 struct radv_shader_module *tes_module,
663 const char *tcs_entrypoint,
664 const char *tes_entrypoint,
665 const VkSpecializationInfo *tcs_spec_info,
666 const VkSpecializationInfo *tes_spec_info,
667 struct radv_pipeline_layout *layout,
668 unsigned input_vertices,
669 bool has_view_index)
670 {
671 unsigned char tcs_sha1[20], tes_sha1[20];
672 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
673 nir_shader *tes_nir, *tcs_nir;
674 void *tes_code = NULL, *tcs_code = NULL;
675 unsigned tes_code_size = 0, tcs_code_size = 0;
676 struct ac_shader_variant_key tes_key;
677 struct ac_shader_variant_key tcs_key;
678 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
679
680 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
681 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
682 tes_key.has_multiview_view_index = has_view_index;
683 if (tes_module->nir)
684 _mesa_sha1_compute(tes_module->nir->info.name,
685 strlen(tes_module->nir->info.name),
686 tes_module->sha1);
687 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
688
689 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
690 cache,
691 tes_sha1);
692
693 if (tes_variant) {
694 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
695
696 if (tcs_module->nir)
697 _mesa_sha1_compute(tcs_module->nir->info.name,
698 strlen(tcs_module->nir->info.name),
699 tcs_module->sha1);
700
701 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
702
703 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
704 cache,
705 tcs_sha1);
706 }
707
708 if (tcs_variant && tes_variant) {
709 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
710 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
711 return;
712 }
713
714 tes_nir = radv_shader_compile_to_nir(pipeline->device,
715 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
716 tes_spec_info, dump);
717 if (tes_nir == NULL)
718 return;
719
720 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
721 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
722 tcs_spec_info, dump);
723 if (tcs_nir == NULL)
724 return;
725
726 nir_lower_tes_patch_vertices(tes_nir,
727 tcs_nir->info.tess.tcs_vertices_out);
728
729 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
730 layout, &tes_key, &tes_code,
731 &tes_code_size, dump);
732
733 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
734 if (tcs_module->nir)
735 _mesa_sha1_compute(tcs_module->nir->info.name,
736 strlen(tcs_module->nir->info.name),
737 tcs_module->sha1);
738
739 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
740
741 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
742 layout, &tcs_key, &tcs_code,
743 &tcs_code_size, dump);
744
745 if (!tes_module->nir)
746 ralloc_free(tes_nir);
747
748 if (!tcs_module->nir)
749 ralloc_free(tcs_nir);
750
751 if (tes_variant)
752 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
753 tes_code, tes_code_size);
754
755 if (tcs_variant)
756 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
757 tcs_code, tcs_code_size);
758
759 if (tes_code)
760 free(tes_code);
761 if (tcs_code)
762 free(tcs_code);
763 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
764 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
765 return;
766 }
767
768 static VkResult
769 radv_pipeline_scratch_init(struct radv_device *device,
770 struct radv_pipeline *pipeline)
771 {
772 unsigned scratch_bytes_per_wave = 0;
773 unsigned max_waves = 0;
774 unsigned min_waves = 1;
775
776 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
777 if (pipeline->shaders[i]) {
778 unsigned max_stage_waves = device->scratch_waves;
779
780 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
781 pipeline->shaders[i]->config.scratch_bytes_per_wave);
782
783 max_stage_waves = MIN2(max_stage_waves,
784 4 * device->physical_device->rad_info.num_good_compute_units *
785 (256 / pipeline->shaders[i]->config.num_vgprs));
786 max_waves = MAX2(max_waves, max_stage_waves);
787 }
788 }
789
790 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
791 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
792 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
793 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
794 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
795 }
796
797 if (scratch_bytes_per_wave)
798 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
799
800 if (scratch_bytes_per_wave && max_waves < min_waves) {
801 /* Not really true at this moment, but will be true on first
802 * execution. Avoid having hanging shaders. */
803 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
804 }
805 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
806 pipeline->max_waves = max_waves;
807 return VK_SUCCESS;
808 }
809
810 static uint32_t si_translate_blend_function(VkBlendOp op)
811 {
812 switch (op) {
813 case VK_BLEND_OP_ADD:
814 return V_028780_COMB_DST_PLUS_SRC;
815 case VK_BLEND_OP_SUBTRACT:
816 return V_028780_COMB_SRC_MINUS_DST;
817 case VK_BLEND_OP_REVERSE_SUBTRACT:
818 return V_028780_COMB_DST_MINUS_SRC;
819 case VK_BLEND_OP_MIN:
820 return V_028780_COMB_MIN_DST_SRC;
821 case VK_BLEND_OP_MAX:
822 return V_028780_COMB_MAX_DST_SRC;
823 default:
824 return 0;
825 }
826 }
827
828 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
829 {
830 switch (factor) {
831 case VK_BLEND_FACTOR_ZERO:
832 return V_028780_BLEND_ZERO;
833 case VK_BLEND_FACTOR_ONE:
834 return V_028780_BLEND_ONE;
835 case VK_BLEND_FACTOR_SRC_COLOR:
836 return V_028780_BLEND_SRC_COLOR;
837 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
838 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
839 case VK_BLEND_FACTOR_DST_COLOR:
840 return V_028780_BLEND_DST_COLOR;
841 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
842 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
843 case VK_BLEND_FACTOR_SRC_ALPHA:
844 return V_028780_BLEND_SRC_ALPHA;
845 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
846 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
847 case VK_BLEND_FACTOR_DST_ALPHA:
848 return V_028780_BLEND_DST_ALPHA;
849 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
850 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
851 case VK_BLEND_FACTOR_CONSTANT_COLOR:
852 return V_028780_BLEND_CONSTANT_COLOR;
853 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
854 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
855 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
856 return V_028780_BLEND_CONSTANT_ALPHA;
857 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
858 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
859 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
860 return V_028780_BLEND_SRC_ALPHA_SATURATE;
861 case VK_BLEND_FACTOR_SRC1_COLOR:
862 return V_028780_BLEND_SRC1_COLOR;
863 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
864 return V_028780_BLEND_INV_SRC1_COLOR;
865 case VK_BLEND_FACTOR_SRC1_ALPHA:
866 return V_028780_BLEND_SRC1_ALPHA;
867 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
868 return V_028780_BLEND_INV_SRC1_ALPHA;
869 default:
870 return 0;
871 }
872 }
873
874 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
875 {
876 switch (op) {
877 case VK_BLEND_OP_ADD:
878 return V_028760_OPT_COMB_ADD;
879 case VK_BLEND_OP_SUBTRACT:
880 return V_028760_OPT_COMB_SUBTRACT;
881 case VK_BLEND_OP_REVERSE_SUBTRACT:
882 return V_028760_OPT_COMB_REVSUBTRACT;
883 case VK_BLEND_OP_MIN:
884 return V_028760_OPT_COMB_MIN;
885 case VK_BLEND_OP_MAX:
886 return V_028760_OPT_COMB_MAX;
887 default:
888 return V_028760_OPT_COMB_BLEND_DISABLED;
889 }
890 }
891
892 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
893 {
894 switch (factor) {
895 case VK_BLEND_FACTOR_ZERO:
896 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
897 case VK_BLEND_FACTOR_ONE:
898 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
899 case VK_BLEND_FACTOR_SRC_COLOR:
900 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
901 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
902 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
903 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
904 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
905 case VK_BLEND_FACTOR_SRC_ALPHA:
906 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
907 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
908 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
909 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
910 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
911 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
912 default:
913 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
914 }
915 }
916
917 /**
918 * Get rid of DST in the blend factors by commuting the operands:
919 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
920 */
921 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
922 unsigned *dst_factor, unsigned expected_dst,
923 unsigned replacement_src)
924 {
925 if (*src_factor == expected_dst &&
926 *dst_factor == VK_BLEND_FACTOR_ZERO) {
927 *src_factor = VK_BLEND_FACTOR_ZERO;
928 *dst_factor = replacement_src;
929
930 /* Commuting the operands requires reversing subtractions. */
931 if (*func == VK_BLEND_OP_SUBTRACT)
932 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
933 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
934 *func = VK_BLEND_OP_SUBTRACT;
935 }
936 }
937
938 static bool si_blend_factor_uses_dst(unsigned factor)
939 {
940 return factor == VK_BLEND_FACTOR_DST_COLOR ||
941 factor == VK_BLEND_FACTOR_DST_ALPHA ||
942 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
943 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
944 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
945 }
946
947 static bool is_dual_src(VkBlendFactor factor)
948 {
949 switch (factor) {
950 case VK_BLEND_FACTOR_SRC1_COLOR:
951 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
952 case VK_BLEND_FACTOR_SRC1_ALPHA:
953 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
954 return true;
955 default:
956 return false;
957 }
958 }
959
960 static unsigned si_choose_spi_color_format(VkFormat vk_format,
961 bool blend_enable,
962 bool blend_need_alpha)
963 {
964 const struct vk_format_description *desc = vk_format_description(vk_format);
965 unsigned format, ntype, swap;
966
967 /* Alpha is needed for alpha-to-coverage.
968 * Blending may be with or without alpha.
969 */
970 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
971 unsigned alpha = 0; /* exports alpha, but may not support blending */
972 unsigned blend = 0; /* supports blending, but may not export alpha */
973 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
974
975 format = radv_translate_colorformat(vk_format);
976 ntype = radv_translate_color_numformat(vk_format, desc,
977 vk_format_get_first_non_void_channel(vk_format));
978 swap = radv_translate_colorswap(vk_format, false);
979
980 /* Choose the SPI color formats. These are required values for Stoney/RB+.
981 * Other chips have multiple choices, though they are not necessarily better.
982 */
983 switch (format) {
984 case V_028C70_COLOR_5_6_5:
985 case V_028C70_COLOR_1_5_5_5:
986 case V_028C70_COLOR_5_5_5_1:
987 case V_028C70_COLOR_4_4_4_4:
988 case V_028C70_COLOR_10_11_11:
989 case V_028C70_COLOR_11_11_10:
990 case V_028C70_COLOR_8:
991 case V_028C70_COLOR_8_8:
992 case V_028C70_COLOR_8_8_8_8:
993 case V_028C70_COLOR_10_10_10_2:
994 case V_028C70_COLOR_2_10_10_10:
995 if (ntype == V_028C70_NUMBER_UINT)
996 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
997 else if (ntype == V_028C70_NUMBER_SINT)
998 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
999 else
1000 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1001 break;
1002
1003 case V_028C70_COLOR_16:
1004 case V_028C70_COLOR_16_16:
1005 case V_028C70_COLOR_16_16_16_16:
1006 if (ntype == V_028C70_NUMBER_UNORM ||
1007 ntype == V_028C70_NUMBER_SNORM) {
1008 /* UNORM16 and SNORM16 don't support blending */
1009 if (ntype == V_028C70_NUMBER_UNORM)
1010 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1011 else
1012 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1013
1014 /* Use 32 bits per channel for blending. */
1015 if (format == V_028C70_COLOR_16) {
1016 if (swap == V_028C70_SWAP_STD) { /* R */
1017 blend = V_028714_SPI_SHADER_32_R;
1018 blend_alpha = V_028714_SPI_SHADER_32_AR;
1019 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1020 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1021 else
1022 assert(0);
1023 } else if (format == V_028C70_COLOR_16_16) {
1024 if (swap == V_028C70_SWAP_STD) { /* RG */
1025 blend = V_028714_SPI_SHADER_32_GR;
1026 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1027 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1028 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1029 else
1030 assert(0);
1031 } else /* 16_16_16_16 */
1032 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1033 } else if (ntype == V_028C70_NUMBER_UINT)
1034 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1035 else if (ntype == V_028C70_NUMBER_SINT)
1036 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1037 else if (ntype == V_028C70_NUMBER_FLOAT)
1038 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1039 else
1040 assert(0);
1041 break;
1042
1043 case V_028C70_COLOR_32:
1044 if (swap == V_028C70_SWAP_STD) { /* R */
1045 blend = normal = V_028714_SPI_SHADER_32_R;
1046 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1047 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1048 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1049 else
1050 assert(0);
1051 break;
1052
1053 case V_028C70_COLOR_32_32:
1054 if (swap == V_028C70_SWAP_STD) { /* RG */
1055 blend = normal = V_028714_SPI_SHADER_32_GR;
1056 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1057 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1058 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1059 else
1060 assert(0);
1061 break;
1062
1063 case V_028C70_COLOR_32_32_32_32:
1064 case V_028C70_COLOR_8_24:
1065 case V_028C70_COLOR_24_8:
1066 case V_028C70_COLOR_X24_8_32_FLOAT:
1067 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1068 break;
1069
1070 default:
1071 unreachable("unhandled blend format");
1072 }
1073
1074 if (blend_enable && blend_need_alpha)
1075 return blend_alpha;
1076 else if(blend_need_alpha)
1077 return alpha;
1078 else if(blend_enable)
1079 return blend;
1080 else
1081 return normal;
1082 }
1083
1084 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
1085 {
1086 unsigned i, cb_shader_mask = 0;
1087
1088 for (i = 0; i < 8; i++) {
1089 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
1090 case V_028714_SPI_SHADER_ZERO:
1091 break;
1092 case V_028714_SPI_SHADER_32_R:
1093 cb_shader_mask |= 0x1 << (i * 4);
1094 break;
1095 case V_028714_SPI_SHADER_32_GR:
1096 cb_shader_mask |= 0x3 << (i * 4);
1097 break;
1098 case V_028714_SPI_SHADER_32_AR:
1099 cb_shader_mask |= 0x9 << (i * 4);
1100 break;
1101 case V_028714_SPI_SHADER_FP16_ABGR:
1102 case V_028714_SPI_SHADER_UNORM16_ABGR:
1103 case V_028714_SPI_SHADER_SNORM16_ABGR:
1104 case V_028714_SPI_SHADER_UINT16_ABGR:
1105 case V_028714_SPI_SHADER_SINT16_ABGR:
1106 case V_028714_SPI_SHADER_32_ABGR:
1107 cb_shader_mask |= 0xf << (i * 4);
1108 break;
1109 default:
1110 assert(0);
1111 }
1112 }
1113 return cb_shader_mask;
1114 }
1115
1116 static void
1117 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1118 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1119 uint32_t blend_enable,
1120 uint32_t blend_need_alpha,
1121 bool single_cb_enable,
1122 bool blend_mrt0_is_dual_src)
1123 {
1124 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1125 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1126 struct radv_blend_state *blend = &pipeline->graphics.blend;
1127 unsigned col_format = 0;
1128
1129 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1130 unsigned cf;
1131
1132 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1133 cf = V_028714_SPI_SHADER_ZERO;
1134 } else {
1135 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
1136
1137 cf = si_choose_spi_color_format(attachment->format,
1138 blend_enable & (1 << i),
1139 blend_need_alpha & (1 << i));
1140 }
1141
1142 col_format |= cf << (4 * i);
1143 }
1144
1145 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1146
1147 if (blend_mrt0_is_dual_src)
1148 col_format |= (col_format & 0xf) << 4;
1149 blend->spi_shader_col_format = col_format;
1150 }
1151
1152 static bool
1153 format_is_int8(VkFormat format)
1154 {
1155 const struct vk_format_description *desc = vk_format_description(format);
1156 int channel = vk_format_get_first_non_void_channel(format);
1157
1158 return channel >= 0 && desc->channel[channel].pure_integer &&
1159 desc->channel[channel].size == 8;
1160 }
1161
1162 static bool
1163 format_is_int10(VkFormat format)
1164 {
1165 const struct vk_format_description *desc = vk_format_description(format);
1166
1167 if (desc->nr_channels != 4)
1168 return false;
1169 for (unsigned i = 0; i < 4; i++) {
1170 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
1171 return true;
1172 }
1173 return false;
1174 }
1175
1176 unsigned radv_format_meta_fs_key(VkFormat format)
1177 {
1178 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1179 bool is_int8 = format_is_int8(format);
1180 bool is_int10 = format_is_int10(format);
1181
1182 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
1183 }
1184
1185 static void
1186 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1187 unsigned *is_int8, unsigned *is_int10)
1188 {
1189 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1190 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1191 *is_int8 = 0;
1192 *is_int10 = 0;
1193
1194 for (unsigned i = 0; i < subpass->color_count; ++i) {
1195 struct radv_render_pass_attachment *attachment;
1196
1197 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
1198 continue;
1199
1200 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1201
1202 if (format_is_int8(attachment->format))
1203 *is_int8 |= 1 << i;
1204 if (format_is_int10(attachment->format))
1205 *is_int10 |= 1 << i;
1206 }
1207 }
1208
1209 static void
1210 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1211 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1212 const struct radv_graphics_pipeline_create_info *extra)
1213 {
1214 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1215 struct radv_blend_state *blend = &pipeline->graphics.blend;
1216 unsigned mode = V_028808_CB_NORMAL;
1217 uint32_t blend_enable = 0, blend_need_alpha = 0;
1218 bool blend_mrt0_is_dual_src = false;
1219 int i;
1220 bool single_cb_enable = false;
1221
1222 if (!vkblend)
1223 return;
1224
1225 if (extra && extra->custom_blend_mode) {
1226 single_cb_enable = true;
1227 mode = extra->custom_blend_mode;
1228 }
1229 blend->cb_color_control = 0;
1230 if (vkblend->logicOpEnable)
1231 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1232 else
1233 blend->cb_color_control |= S_028808_ROP3(0xcc);
1234
1235 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1236 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1237 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1238 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1239
1240 blend->cb_target_mask = 0;
1241 for (i = 0; i < vkblend->attachmentCount; i++) {
1242 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1243 unsigned blend_cntl = 0;
1244 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
1245 VkBlendOp eqRGB = att->colorBlendOp;
1246 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1247 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1248 VkBlendOp eqA = att->alphaBlendOp;
1249 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1250 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1251
1252 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1253
1254 if (!att->colorWriteMask)
1255 continue;
1256
1257 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1258 if (!att->blendEnable) {
1259 blend->cb_blend_control[i] = blend_cntl;
1260 continue;
1261 }
1262
1263 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1264 if (i == 0)
1265 blend_mrt0_is_dual_src = true;
1266
1267 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1268 srcRGB = VK_BLEND_FACTOR_ONE;
1269 dstRGB = VK_BLEND_FACTOR_ONE;
1270 }
1271 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1272 srcA = VK_BLEND_FACTOR_ONE;
1273 dstA = VK_BLEND_FACTOR_ONE;
1274 }
1275
1276 /* Blending optimizations for RB+.
1277 * These transformations don't change the behavior.
1278 *
1279 * First, get rid of DST in the blend factors:
1280 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
1281 */
1282 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
1283 VK_BLEND_FACTOR_DST_COLOR,
1284 VK_BLEND_FACTOR_SRC_COLOR);
1285
1286 si_blend_remove_dst(&eqA, &srcA, &dstA,
1287 VK_BLEND_FACTOR_DST_COLOR,
1288 VK_BLEND_FACTOR_SRC_COLOR);
1289
1290 si_blend_remove_dst(&eqA, &srcA, &dstA,
1291 VK_BLEND_FACTOR_DST_ALPHA,
1292 VK_BLEND_FACTOR_SRC_ALPHA);
1293
1294 /* Look up the ideal settings from tables. */
1295 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
1296 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
1297 srcA_opt = si_translate_blend_opt_factor(srcA, true);
1298 dstA_opt = si_translate_blend_opt_factor(dstA, true);
1299
1300 /* Handle interdependencies. */
1301 if (si_blend_factor_uses_dst(srcRGB))
1302 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1303 if (si_blend_factor_uses_dst(srcA))
1304 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1305
1306 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
1307 (dstRGB == VK_BLEND_FACTOR_ZERO ||
1308 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1309 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
1310 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
1311
1312 /* Set the final value. */
1313 blend->sx_mrt_blend_opt[i] =
1314 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
1315 S_028760_COLOR_DST_OPT(dstRGB_opt) |
1316 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
1317 S_028760_ALPHA_SRC_OPT(srcA_opt) |
1318 S_028760_ALPHA_DST_OPT(dstA_opt) |
1319 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
1320 blend_cntl |= S_028780_ENABLE(1);
1321
1322 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1323 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1324 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1325 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1326 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1327 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1328 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1329 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1330 }
1331 blend->cb_blend_control[i] = blend_cntl;
1332
1333 blend_enable |= 1 << i;
1334
1335 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1336 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1337 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1338 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1339 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1340 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1341 blend_need_alpha |= 1 << i;
1342 }
1343 for (i = vkblend->attachmentCount; i < 8; i++) {
1344 blend->cb_blend_control[i] = 0;
1345 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1346 }
1347
1348 /* disable RB+ for now */
1349 if (pipeline->device->physical_device->has_rbplus)
1350 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
1351
1352 if (blend->cb_target_mask)
1353 blend->cb_color_control |= S_028808_MODE(mode);
1354 else
1355 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1356
1357 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1358 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1359 }
1360
1361 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1362 {
1363 switch (op) {
1364 case VK_STENCIL_OP_KEEP:
1365 return V_02842C_STENCIL_KEEP;
1366 case VK_STENCIL_OP_ZERO:
1367 return V_02842C_STENCIL_ZERO;
1368 case VK_STENCIL_OP_REPLACE:
1369 return V_02842C_STENCIL_REPLACE_TEST;
1370 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1371 return V_02842C_STENCIL_ADD_CLAMP;
1372 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1373 return V_02842C_STENCIL_SUB_CLAMP;
1374 case VK_STENCIL_OP_INVERT:
1375 return V_02842C_STENCIL_INVERT;
1376 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1377 return V_02842C_STENCIL_ADD_WRAP;
1378 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1379 return V_02842C_STENCIL_SUB_WRAP;
1380 default:
1381 return 0;
1382 }
1383 }
1384 static void
1385 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1386 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1387 const struct radv_graphics_pipeline_create_info *extra)
1388 {
1389 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1390 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1391
1392 memset(ds, 0, sizeof(*ds));
1393 if (!vkds)
1394 return;
1395
1396 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1397 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1398 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1399 return;
1400
1401 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
1402 bool has_depth_attachment = vk_format_is_depth(attachment->format);
1403 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
1404
1405 if (has_depth_attachment) {
1406 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1407 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1408 S_028800_ZFUNC(vkds->depthCompareOp) |
1409 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1410 }
1411
1412 if (has_stencil_attachment && vkds->stencilTestEnable) {
1413 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1414 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1415 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1416 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1417 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1418
1419 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1420 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1421 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1422 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1423 }
1424
1425 if (extra) {
1426
1427 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1428 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1429
1430 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1431 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1432 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1433 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1434 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1435 }
1436 }
1437
1438 static uint32_t si_translate_fill(VkPolygonMode func)
1439 {
1440 switch(func) {
1441 case VK_POLYGON_MODE_FILL:
1442 return V_028814_X_DRAW_TRIANGLES;
1443 case VK_POLYGON_MODE_LINE:
1444 return V_028814_X_DRAW_LINES;
1445 case VK_POLYGON_MODE_POINT:
1446 return V_028814_X_DRAW_POINTS;
1447 default:
1448 assert(0);
1449 return V_028814_X_DRAW_POINTS;
1450 }
1451 }
1452 static void
1453 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1454 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1455 {
1456 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1457 struct radv_raster_state *raster = &pipeline->graphics.raster;
1458
1459 memset(raster, 0, sizeof(*raster));
1460
1461 raster->spi_interp_control =
1462 S_0286D4_FLAT_SHADE_ENA(1) |
1463 S_0286D4_PNT_SPRITE_ENA(1) |
1464 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1465 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1466 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1467 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1468 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1469
1470
1471 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1472 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1473 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1474 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1475 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1476 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1477
1478 raster->pa_su_vtx_cntl =
1479 S_028BE4_PIX_CENTER(1) | // TODO verify
1480 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1481 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1482
1483 raster->pa_su_sc_mode_cntl =
1484 S_028814_FACE(vkraster->frontFace) |
1485 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1486 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1487 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1488 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1489 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1490 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1491 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1492 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1493
1494 }
1495
1496 static void
1497 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1498 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1499 {
1500 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1501 struct radv_blend_state *blend = &pipeline->graphics.blend;
1502 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1503 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1504 int ps_iter_samples = 1;
1505 uint32_t mask = 0xffff;
1506
1507 if (vkms)
1508 ms->num_samples = vkms->rasterizationSamples;
1509 else
1510 ms->num_samples = 1;
1511
1512 if (vkms && vkms->sampleShadingEnable) {
1513 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1514 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1515 ps_iter_samples = ms->num_samples;
1516 }
1517
1518 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1519 ms->pa_sc_aa_config = 0;
1520 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1521 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1522 ms->pa_sc_mode_cntl_1 =
1523 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1524 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1525 /* always 1: */
1526 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1527 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1528 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1529 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1530 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1531 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1532 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1533
1534 if (ms->num_samples > 1) {
1535 unsigned log_samples = util_logbase2(ms->num_samples);
1536 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1537 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1538 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1539 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1540 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1541 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1542 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1543 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1544 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1545 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1546 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1547 }
1548
1549 if (vkms) {
1550 if (vkms->alphaToCoverageEnable)
1551 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1552
1553 if (vkms->pSampleMask)
1554 mask = vkms->pSampleMask[0] & 0xffff;
1555 }
1556
1557 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1558 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1559 }
1560
1561 static bool
1562 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1563 {
1564 switch (topology) {
1565 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1566 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1567 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1568 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1569 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1570 return false;
1571 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1572 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1573 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1574 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1575 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1576 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1577 return true;
1578 default:
1579 unreachable("unhandled primitive type");
1580 }
1581 }
1582
1583 static uint32_t
1584 si_translate_prim(enum VkPrimitiveTopology topology)
1585 {
1586 switch (topology) {
1587 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1588 return V_008958_DI_PT_POINTLIST;
1589 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1590 return V_008958_DI_PT_LINELIST;
1591 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1592 return V_008958_DI_PT_LINESTRIP;
1593 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1594 return V_008958_DI_PT_TRILIST;
1595 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1596 return V_008958_DI_PT_TRISTRIP;
1597 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1598 return V_008958_DI_PT_TRIFAN;
1599 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1600 return V_008958_DI_PT_LINELIST_ADJ;
1601 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1602 return V_008958_DI_PT_LINESTRIP_ADJ;
1603 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1604 return V_008958_DI_PT_TRILIST_ADJ;
1605 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1606 return V_008958_DI_PT_TRISTRIP_ADJ;
1607 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1608 return V_008958_DI_PT_PATCH;
1609 default:
1610 assert(0);
1611 return 0;
1612 }
1613 }
1614
1615 static uint32_t
1616 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1617 {
1618 switch (gl_prim) {
1619 case 0: /* GL_POINTS */
1620 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1621 case 1: /* GL_LINES */
1622 case 3: /* GL_LINE_STRIP */
1623 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1624 case 0x8E7A: /* GL_ISOLINES */
1625 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1626
1627 case 4: /* GL_TRIANGLES */
1628 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1629 case 5: /* GL_TRIANGLE_STRIP */
1630 case 7: /* GL_QUADS */
1631 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1632 default:
1633 assert(0);
1634 return 0;
1635 }
1636 }
1637
1638 static uint32_t
1639 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1640 {
1641 switch (topology) {
1642 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1643 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1644 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1645 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1646 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1647 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1648 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1649 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1650 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1651 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1652 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1653 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1654 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1655 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1656 default:
1657 assert(0);
1658 return 0;
1659 }
1660 }
1661
1662 static unsigned si_map_swizzle(unsigned swizzle)
1663 {
1664 switch (swizzle) {
1665 case VK_SWIZZLE_Y:
1666 return V_008F0C_SQ_SEL_Y;
1667 case VK_SWIZZLE_Z:
1668 return V_008F0C_SQ_SEL_Z;
1669 case VK_SWIZZLE_W:
1670 return V_008F0C_SQ_SEL_W;
1671 case VK_SWIZZLE_0:
1672 return V_008F0C_SQ_SEL_0;
1673 case VK_SWIZZLE_1:
1674 return V_008F0C_SQ_SEL_1;
1675 default: /* VK_SWIZZLE_X */
1676 return V_008F0C_SQ_SEL_X;
1677 }
1678 }
1679
1680 static void
1681 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1682 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1683 {
1684 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1685 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1686 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1687
1688 pipeline->dynamic_state = default_dynamic_state;
1689
1690 if (pCreateInfo->pDynamicState) {
1691 /* Remove all of the states that are marked as dynamic */
1692 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1693 for (uint32_t s = 0; s < count; s++)
1694 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1695 }
1696
1697 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1698
1699 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1700 *
1701 * pViewportState is [...] NULL if the pipeline
1702 * has rasterization disabled.
1703 */
1704 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1705 assert(pCreateInfo->pViewportState);
1706
1707 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1708 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1709 typed_memcpy(dynamic->viewport.viewports,
1710 pCreateInfo->pViewportState->pViewports,
1711 pCreateInfo->pViewportState->viewportCount);
1712 }
1713
1714 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1715 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1716 typed_memcpy(dynamic->scissor.scissors,
1717 pCreateInfo->pViewportState->pScissors,
1718 pCreateInfo->pViewportState->scissorCount);
1719 }
1720 }
1721
1722 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1723 assert(pCreateInfo->pRasterizationState);
1724 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1725 }
1726
1727 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1728 assert(pCreateInfo->pRasterizationState);
1729 dynamic->depth_bias.bias =
1730 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1731 dynamic->depth_bias.clamp =
1732 pCreateInfo->pRasterizationState->depthBiasClamp;
1733 dynamic->depth_bias.slope =
1734 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1735 }
1736
1737 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1738 *
1739 * pColorBlendState is [...] NULL if the pipeline has rasterization
1740 * disabled or if the subpass of the render pass the pipeline is
1741 * created against does not use any color attachments.
1742 */
1743 bool uses_color_att = false;
1744 for (unsigned i = 0; i < subpass->color_count; ++i) {
1745 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1746 uses_color_att = true;
1747 break;
1748 }
1749 }
1750
1751 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1752 assert(pCreateInfo->pColorBlendState);
1753 typed_memcpy(dynamic->blend_constants,
1754 pCreateInfo->pColorBlendState->blendConstants, 4);
1755 }
1756
1757 /* If there is no depthstencil attachment, then don't read
1758 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1759 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1760 * no need to override the depthstencil defaults in
1761 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1762 *
1763 * Section 9.2 of the Vulkan 1.0.15 spec says:
1764 *
1765 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1766 * disabled or if the subpass of the render pass the pipeline is created
1767 * against does not use a depth/stencil attachment.
1768 */
1769 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1770 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1771 assert(pCreateInfo->pDepthStencilState);
1772
1773 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1774 dynamic->depth_bounds.min =
1775 pCreateInfo->pDepthStencilState->minDepthBounds;
1776 dynamic->depth_bounds.max =
1777 pCreateInfo->pDepthStencilState->maxDepthBounds;
1778 }
1779
1780 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1781 dynamic->stencil_compare_mask.front =
1782 pCreateInfo->pDepthStencilState->front.compareMask;
1783 dynamic->stencil_compare_mask.back =
1784 pCreateInfo->pDepthStencilState->back.compareMask;
1785 }
1786
1787 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1788 dynamic->stencil_write_mask.front =
1789 pCreateInfo->pDepthStencilState->front.writeMask;
1790 dynamic->stencil_write_mask.back =
1791 pCreateInfo->pDepthStencilState->back.writeMask;
1792 }
1793
1794 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1795 dynamic->stencil_reference.front =
1796 pCreateInfo->pDepthStencilState->front.reference;
1797 dynamic->stencil_reference.back =
1798 pCreateInfo->pDepthStencilState->back.reference;
1799 }
1800 }
1801
1802 pipeline->dynamic_state_mask = states;
1803 }
1804
1805 static struct ac_shader_variant_key
1806 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1807 {
1808 struct ac_shader_variant_key key;
1809 const VkPipelineVertexInputStateCreateInfo *input_state =
1810 pCreateInfo->pVertexInputState;
1811
1812 memset(&key, 0, sizeof(key));
1813 key.vs.instance_rate_inputs = 0;
1814 key.vs.as_es = as_es;
1815 key.vs.as_ls = as_ls;
1816 key.vs.export_prim_id = export_prim_id;
1817
1818 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1819 unsigned binding;
1820 binding = input_state->pVertexAttributeDescriptions[i].binding;
1821 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1822 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1823 }
1824 return key;
1825 }
1826
1827 static void
1828 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1829 {
1830 struct radv_device *device = pipeline->device;
1831 unsigned num_se = device->physical_device->rad_info.max_se;
1832 unsigned wave_size = 64;
1833 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1834 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1835 unsigned alignment = 256 * num_se;
1836 /* The maximum size is 63.999 MB per SE. */
1837 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1838 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1839 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1840 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1841 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1842
1843 /* Calculate the minimum size. */
1844 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1845 wave_size, alignment);
1846 /* These are recommended sizes, not minimum sizes. */
1847 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1848 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1849 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1850 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1851
1852 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1853 esgs_ring_size = align(esgs_ring_size, alignment);
1854 gsvs_ring_size = align(gsvs_ring_size, alignment);
1855
1856 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1857 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1858 }
1859
1860 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1861 unsigned *lds_size)
1862 {
1863 /* SPI barrier management bug:
1864 * Make sure we have at least 4k of LDS in use to avoid the bug.
1865 * It applies to workgroup sizes of more than one wavefront.
1866 */
1867 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1868 device->physical_device->rad_info.family == CHIP_KABINI ||
1869 device->physical_device->rad_info.family == CHIP_MULLINS)
1870 *lds_size = MAX2(*lds_size, 8);
1871 }
1872
1873 static void
1874 calculate_tess_state(struct radv_pipeline *pipeline,
1875 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1876 {
1877 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1878 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1879 unsigned num_tcs_patch_outputs;
1880 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1881 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1882 unsigned lds_size, hardware_lds_size;
1883 unsigned perpatch_output_offset;
1884 unsigned num_patches;
1885 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1886
1887 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1888 * are laid out in LDS. */
1889 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1890
1891 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1892 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1893 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1894
1895 /* Ensure that we only need one wave per SIMD so we don't need to check
1896 * resource usage. Also ensures that the number of tcs in and out
1897 * vertices per threadgroup are at most 256.
1898 */
1899 input_vertex_size = num_tcs_inputs * 16;
1900 output_vertex_size = num_tcs_outputs * 16;
1901
1902 input_patch_size = num_tcs_input_cp * input_vertex_size;
1903
1904 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1905 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1906 /* Ensure that we only need one wave per SIMD so we don't need to check
1907 * resource usage. Also ensures that the number of tcs in and out
1908 * vertices per threadgroup are at most 256.
1909 */
1910 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1911
1912 /* Make sure that the data fits in LDS. This assumes the shaders only
1913 * use LDS for the inputs and outputs.
1914 */
1915 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1916 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1917
1918 /* Make sure the output data fits in the offchip buffer */
1919 num_patches = MIN2(num_patches,
1920 (pipeline->device->tess_offchip_block_dw_size * 4) /
1921 output_patch_size);
1922
1923 /* Not necessary for correctness, but improves performance. The
1924 * specific value is taken from the proprietary driver.
1925 */
1926 num_patches = MIN2(num_patches, 40);
1927
1928 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1929 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1930 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1931 num_patches = MIN2(num_patches, one_wave);
1932 }
1933
1934 output_patch0_offset = input_patch_size * num_patches;
1935 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1936
1937 lds_size = output_patch0_offset + output_patch_size * num_patches;
1938
1939 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1940 assert(lds_size <= 65536);
1941 lds_size = align(lds_size, 512) / 512;
1942 } else {
1943 assert(lds_size <= 32768);
1944 lds_size = align(lds_size, 256) / 256;
1945 }
1946 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1947
1948 tess->lds_size = lds_size;
1949
1950 tess->tcs_in_layout = (input_patch_size / 4) |
1951 ((input_vertex_size / 4) << 13);
1952 tess->tcs_out_layout = (output_patch_size / 4) |
1953 ((output_vertex_size / 4) << 13);
1954 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1955 ((perpatch_output_offset / 16) << 16);
1956 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1957 (num_tcs_output_cp << 9) | num_patches;
1958
1959 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1960 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1961 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1962 tess->num_patches = num_patches;
1963 tess->num_tcs_input_cp = num_tcs_input_cp;
1964
1965 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1966 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1967
1968 switch (tes->info.tes.primitive_mode) {
1969 case GL_TRIANGLES:
1970 type = V_028B6C_TESS_TRIANGLE;
1971 break;
1972 case GL_QUADS:
1973 type = V_028B6C_TESS_QUAD;
1974 break;
1975 case GL_ISOLINES:
1976 type = V_028B6C_TESS_ISOLINE;
1977 break;
1978 }
1979
1980 switch (tes->info.tes.spacing) {
1981 case TESS_SPACING_EQUAL:
1982 partitioning = V_028B6C_PART_INTEGER;
1983 break;
1984 case TESS_SPACING_FRACTIONAL_ODD:
1985 partitioning = V_028B6C_PART_FRAC_ODD;
1986 break;
1987 case TESS_SPACING_FRACTIONAL_EVEN:
1988 partitioning = V_028B6C_PART_FRAC_EVEN;
1989 break;
1990 default:
1991 break;
1992 }
1993
1994 if (tes->info.tes.point_mode)
1995 topology = V_028B6C_OUTPUT_POINT;
1996 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1997 topology = V_028B6C_OUTPUT_LINE;
1998 else if (tes->info.tes.ccw)
1999 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2000 else
2001 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2002
2003 if (pipeline->device->has_distributed_tess) {
2004 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2005 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2006 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2007 else
2008 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2009 } else
2010 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2011
2012 tess->tf_param = S_028B6C_TYPE(type) |
2013 S_028B6C_PARTITIONING(partitioning) |
2014 S_028B6C_TOPOLOGY(topology) |
2015 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2016 }
2017
2018 static const struct radv_prim_vertex_count prim_size_table[] = {
2019 [V_008958_DI_PT_NONE] = {0, 0},
2020 [V_008958_DI_PT_POINTLIST] = {1, 1},
2021 [V_008958_DI_PT_LINELIST] = {2, 2},
2022 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2023 [V_008958_DI_PT_TRILIST] = {3, 3},
2024 [V_008958_DI_PT_TRIFAN] = {3, 1},
2025 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2026 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2027 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2028 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2029 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2030 [V_008958_DI_PT_RECTLIST] = {3, 3},
2031 [V_008958_DI_PT_LINELOOP] = {2, 1},
2032 [V_008958_DI_PT_POLYGON] = {3, 1},
2033 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2034 };
2035
2036 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
2037 {
2038 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
2039 unsigned cut_mode;
2040
2041 if (gs_max_vert_out <= 128) {
2042 cut_mode = V_028A40_GS_CUT_128;
2043 } else if (gs_max_vert_out <= 256) {
2044 cut_mode = V_028A40_GS_CUT_256;
2045 } else if (gs_max_vert_out <= 512) {
2046 cut_mode = V_028A40_GS_CUT_512;
2047 } else {
2048 assert(gs_max_vert_out <= 1024);
2049 cut_mode = V_028A40_GS_CUT_1024;
2050 }
2051
2052 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2053 S_028A40_CUT_MODE(cut_mode)|
2054 S_028A40_ES_WRITE_OPTIMIZE(1) |
2055 S_028A40_GS_WRITE_OPTIMIZE(1);
2056 }
2057
2058 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
2059 {
2060 struct radv_shader_variant *vs;
2061 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2062
2063 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2064
2065 pipeline->graphics.vgt_primitiveid_en = false;
2066 pipeline->graphics.vgt_gs_mode = 0;
2067
2068 if (radv_pipeline_has_gs(pipeline)) {
2069 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2070 } else if (outinfo->export_prim_id) {
2071 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2072 pipeline->graphics.vgt_primitiveid_en = true;
2073 }
2074 }
2075
2076 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
2077 {
2078 struct radv_shader_variant *vs;
2079 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2080
2081 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2082
2083 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2084 clip_dist_mask = outinfo->clip_dist_mask;
2085 cull_dist_mask = outinfo->cull_dist_mask;
2086 total_mask = clip_dist_mask | cull_dist_mask;
2087
2088 bool misc_vec_ena = outinfo->writes_pointsize ||
2089 outinfo->writes_layer ||
2090 outinfo->writes_viewport_index;
2091 pipeline->graphics.pa_cl_vs_out_cntl =
2092 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2093 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2094 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2095 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2096 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2097 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2098 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2099 cull_dist_mask << 8 |
2100 clip_dist_mask;
2101
2102 }
2103
2104 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2105 {
2106 uint32_t ps_input_cntl;
2107 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2108 ps_input_cntl = S_028644_OFFSET(offset);
2109 if (flat_shade)
2110 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2111 } else {
2112 /* The input is a DEFAULT_VAL constant. */
2113 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2114 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2115 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2116 ps_input_cntl = S_028644_OFFSET(0x20) |
2117 S_028644_DEFAULT_VAL(offset);
2118 }
2119 return ps_input_cntl;
2120 }
2121
2122 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
2123 {
2124 struct radv_shader_variant *ps, *vs;
2125 struct ac_vs_output_info *outinfo;
2126
2127 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2128 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2129
2130 outinfo = &vs->info.vs.outinfo;
2131
2132 unsigned ps_offset = 0;
2133
2134 if (ps->info.fs.prim_id_input) {
2135 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2136 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2137 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2138 ++ps_offset;
2139 }
2140 }
2141
2142 if (ps->info.fs.layer_input) {
2143 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2144 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2145 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2146 else
2147 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2148 ++ps_offset;
2149 }
2150
2151 if (ps->info.fs.has_pcoord) {
2152 unsigned val;
2153 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2154 pipeline->graphics.ps_input_cntl[ps_offset] = val;
2155 ps_offset++;
2156 }
2157
2158 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2159 unsigned vs_offset;
2160 bool flat_shade;
2161 if (!(ps->info.fs.input_mask & (1u << i)))
2162 continue;
2163
2164 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2165 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2166 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2167 ++ps_offset;
2168 continue;
2169 }
2170
2171 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2172
2173 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2174 ++ps_offset;
2175 }
2176
2177 pipeline->graphics.ps_input_cntl_num = ps_offset;
2178 }
2179
2180 VkResult
2181 radv_pipeline_init(struct radv_pipeline *pipeline,
2182 struct radv_device *device,
2183 struct radv_pipeline_cache *cache,
2184 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2185 const struct radv_graphics_pipeline_create_info *extra,
2186 const VkAllocationCallbacks *alloc)
2187 {
2188 struct radv_shader_module fs_m = {0};
2189 VkResult result;
2190 bool has_view_index = false;
2191
2192 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2193 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2194 if (subpass->view_mask)
2195 has_view_index = true;
2196 if (alloc == NULL)
2197 alloc = &device->alloc;
2198
2199 pipeline->device = device;
2200 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2201
2202 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2203 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2204 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2205 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2206 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2207 pStages[stage] = &pCreateInfo->pStages[i];
2208 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2209 }
2210
2211 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2212
2213 if (!modules[MESA_SHADER_FRAGMENT]) {
2214 nir_builder fs_b;
2215 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2216 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2217 fs_m.nir = fs_b.shader;
2218 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2219 }
2220
2221 if (modules[MESA_SHADER_FRAGMENT]) {
2222 struct ac_shader_variant_key key = {0};
2223 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2224 if (pCreateInfo->pMultisampleState &&
2225 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
2226 key.fs.multisample = true;
2227
2228 if (pipeline->device->physical_device->rad_info.chip_class < VI)
2229 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
2230
2231 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2232
2233 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2234 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2235 stage ? stage->pName : "main",
2236 MESA_SHADER_FRAGMENT,
2237 stage ? stage->pSpecializationInfo : NULL,
2238 pipeline->layout, &key);
2239 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2240 }
2241
2242 if (fs_m.nir)
2243 ralloc_free(fs_m.nir);
2244
2245 if (modules[MESA_SHADER_VERTEX]) {
2246 bool as_es = false;
2247 bool as_ls = false;
2248 bool export_prim_id = false;
2249 if (modules[MESA_SHADER_TESS_CTRL])
2250 as_ls = true;
2251 else if (modules[MESA_SHADER_GEOMETRY])
2252 as_es = true;
2253 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2254 export_prim_id = true;
2255 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2256 key.has_multiview_view_index = has_view_index;
2257
2258 pipeline->shaders[MESA_SHADER_VERTEX] =
2259 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2260 pStages[MESA_SHADER_VERTEX]->pName,
2261 MESA_SHADER_VERTEX,
2262 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2263 pipeline->layout, &key);
2264
2265 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2266 }
2267
2268 if (modules[MESA_SHADER_GEOMETRY]) {
2269 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2270 key.has_multiview_view_index = has_view_index;
2271
2272 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2273 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2274 pStages[MESA_SHADER_GEOMETRY]->pName,
2275 MESA_SHADER_GEOMETRY,
2276 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2277 pipeline->layout, &key);
2278
2279 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2280 }
2281
2282 if (modules[MESA_SHADER_TESS_EVAL]) {
2283 assert(modules[MESA_SHADER_TESS_CTRL]);
2284
2285 radv_tess_pipeline_compile(pipeline,
2286 cache,
2287 modules[MESA_SHADER_TESS_CTRL],
2288 modules[MESA_SHADER_TESS_EVAL],
2289 pStages[MESA_SHADER_TESS_CTRL]->pName,
2290 pStages[MESA_SHADER_TESS_EVAL]->pName,
2291 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2292 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2293 pipeline->layout,
2294 pCreateInfo->pTessellationState->patchControlPoints,
2295 has_view_index);
2296 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2297 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2298 }
2299
2300 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2301 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2302 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2303 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2304 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2305
2306 if (radv_pipeline_has_gs(pipeline)) {
2307 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2308 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2309 } else {
2310 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2311 }
2312 if (extra && extra->use_rectlist) {
2313 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2314 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2315 pipeline->graphics.can_use_guardband = true;
2316 }
2317 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2318 /* prim vertex count will need TESS changes */
2319 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2320
2321 /* Ensure that some export memory is always allocated, for two reasons:
2322 *
2323 * 1) Correctness: The hardware ignores the EXEC mask if no export
2324 * memory is allocated, so KILL and alpha test do not work correctly
2325 * without this.
2326 * 2) Performance: Every shader needs at least a NULL export, even when
2327 * it writes no color/depth output. The NULL export instruction
2328 * stalls without this setting.
2329 *
2330 * Don't add this to CB_SHADER_MASK.
2331 */
2332 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2333 if (!pipeline->graphics.blend.spi_shader_col_format) {
2334 if (!ps->info.fs.writes_z &&
2335 !ps->info.fs.writes_stencil &&
2336 !ps->info.fs.writes_sample_mask)
2337 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2338 }
2339
2340 unsigned z_order;
2341 pipeline->graphics.db_shader_control = 0;
2342 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2343 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2344 else
2345 z_order = V_02880C_LATE_Z;
2346
2347 pipeline->graphics.db_shader_control =
2348 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2349 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2350 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2351 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2352 S_02880C_Z_ORDER(z_order) |
2353 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2354 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2355 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2356
2357 if (pipeline->device->physical_device->has_rbplus)
2358 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2359
2360 pipeline->graphics.shader_z_format =
2361 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2362 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2363 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2364 V_028710_SPI_SHADER_ZERO;
2365
2366 calculate_vgt_gs_mode(pipeline);
2367 calculate_pa_cl_vs_out_cntl(pipeline);
2368 calculate_ps_inputs(pipeline);
2369
2370 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2371 if (pipeline->shaders[i]) {
2372 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2373 }
2374 }
2375
2376 uint32_t stages = 0;
2377 if (radv_pipeline_has_tess(pipeline)) {
2378 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2379 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2380
2381 if (radv_pipeline_has_gs(pipeline))
2382 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2383 S_028B54_GS_EN(1) |
2384 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2385 else
2386 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2387
2388 } else if (radv_pipeline_has_gs(pipeline))
2389 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2390 S_028B54_GS_EN(1) |
2391 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2392
2393 if (device->physical_device->rad_info.chip_class >= GFX9)
2394 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2395
2396 pipeline->graphics.vgt_shader_stages_en = stages;
2397
2398 if (radv_pipeline_has_gs(pipeline))
2399 calculate_gs_ring_sizes(pipeline);
2400
2401 if (radv_pipeline_has_tess(pipeline)) {
2402 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2403 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2404 pipeline->graphics.prim_vertex_count.incr = 1;
2405 }
2406 calculate_tess_state(pipeline, pCreateInfo);
2407 }
2408
2409 const VkPipelineVertexInputStateCreateInfo *vi_info =
2410 pCreateInfo->pVertexInputState;
2411 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2412 const VkVertexInputAttributeDescription *desc =
2413 &vi_info->pVertexAttributeDescriptions[i];
2414 unsigned loc = desc->location;
2415 const struct vk_format_description *format_desc;
2416 int first_non_void;
2417 uint32_t num_format, data_format;
2418 format_desc = vk_format_description(desc->format);
2419 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2420
2421 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2422 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2423
2424 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2425 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2426 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2427 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2428 S_008F0C_NUM_FORMAT(num_format) |
2429 S_008F0C_DATA_FORMAT(data_format);
2430 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2431 pipeline->va_offset[loc] = desc->offset;
2432 pipeline->va_binding[loc] = desc->binding;
2433 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2434 }
2435
2436 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2437 const VkVertexInputBindingDescription *desc =
2438 &vi_info->pVertexBindingDescriptions[i];
2439
2440 pipeline->binding_stride[desc->binding] = desc->stride;
2441 }
2442
2443 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2444 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2445 if (loc->sgpr_idx != -1) {
2446 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2447 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2448 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2449 pipeline->graphics.vtx_emit_num = 3;
2450 else
2451 pipeline->graphics.vtx_emit_num = 2;
2452 }
2453 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2454 radv_dump_pipeline_stats(device, pipeline);
2455 }
2456
2457 result = radv_pipeline_scratch_init(device, pipeline);
2458 return result;
2459 }
2460
2461 VkResult
2462 radv_graphics_pipeline_create(
2463 VkDevice _device,
2464 VkPipelineCache _cache,
2465 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2466 const struct radv_graphics_pipeline_create_info *extra,
2467 const VkAllocationCallbacks *pAllocator,
2468 VkPipeline *pPipeline)
2469 {
2470 RADV_FROM_HANDLE(radv_device, device, _device);
2471 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2472 struct radv_pipeline *pipeline;
2473 VkResult result;
2474
2475 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2476 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2477 if (pipeline == NULL)
2478 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2479
2480 memset(pipeline, 0, sizeof(*pipeline));
2481 result = radv_pipeline_init(pipeline, device, cache,
2482 pCreateInfo, extra, pAllocator);
2483 if (result != VK_SUCCESS) {
2484 radv_pipeline_destroy(device, pipeline, pAllocator);
2485 return result;
2486 }
2487
2488 *pPipeline = radv_pipeline_to_handle(pipeline);
2489
2490 return VK_SUCCESS;
2491 }
2492
2493 VkResult radv_CreateGraphicsPipelines(
2494 VkDevice _device,
2495 VkPipelineCache pipelineCache,
2496 uint32_t count,
2497 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2498 const VkAllocationCallbacks* pAllocator,
2499 VkPipeline* pPipelines)
2500 {
2501 VkResult result = VK_SUCCESS;
2502 unsigned i = 0;
2503
2504 for (; i < count; i++) {
2505 VkResult r;
2506 r = radv_graphics_pipeline_create(_device,
2507 pipelineCache,
2508 &pCreateInfos[i],
2509 NULL, pAllocator, &pPipelines[i]);
2510 if (r != VK_SUCCESS) {
2511 result = r;
2512 pPipelines[i] = VK_NULL_HANDLE;
2513 }
2514 }
2515
2516 return result;
2517 }
2518
2519 static VkResult radv_compute_pipeline_create(
2520 VkDevice _device,
2521 VkPipelineCache _cache,
2522 const VkComputePipelineCreateInfo* pCreateInfo,
2523 const VkAllocationCallbacks* pAllocator,
2524 VkPipeline* pPipeline)
2525 {
2526 RADV_FROM_HANDLE(radv_device, device, _device);
2527 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2528 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2529 struct radv_pipeline *pipeline;
2530 VkResult result;
2531
2532 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2533 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2534 if (pipeline == NULL)
2535 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2536
2537 memset(pipeline, 0, sizeof(*pipeline));
2538 pipeline->device = device;
2539 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2540
2541 pipeline->shaders[MESA_SHADER_COMPUTE] =
2542 radv_pipeline_compile(pipeline, cache, module,
2543 pCreateInfo->stage.pName,
2544 MESA_SHADER_COMPUTE,
2545 pCreateInfo->stage.pSpecializationInfo,
2546 pipeline->layout, NULL);
2547
2548
2549 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2550 result = radv_pipeline_scratch_init(device, pipeline);
2551 if (result != VK_SUCCESS) {
2552 radv_pipeline_destroy(device, pipeline, pAllocator);
2553 return result;
2554 }
2555
2556 *pPipeline = radv_pipeline_to_handle(pipeline);
2557
2558 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2559 radv_dump_pipeline_stats(device, pipeline);
2560 }
2561 return VK_SUCCESS;
2562 }
2563 VkResult radv_CreateComputePipelines(
2564 VkDevice _device,
2565 VkPipelineCache pipelineCache,
2566 uint32_t count,
2567 const VkComputePipelineCreateInfo* pCreateInfos,
2568 const VkAllocationCallbacks* pAllocator,
2569 VkPipeline* pPipelines)
2570 {
2571 VkResult result = VK_SUCCESS;
2572
2573 unsigned i = 0;
2574 for (; i < count; i++) {
2575 VkResult r;
2576 r = radv_compute_pipeline_create(_device, pipelineCache,
2577 &pCreateInfos[i],
2578 pAllocator, &pPipelines[i]);
2579 if (r != VK_SUCCESS) {
2580 result = r;
2581 pPipelines[i] = VK_NULL_HANDLE;
2582 }
2583 }
2584
2585 return result;
2586 }
2587
2588 void *radv_alloc_shader_memory(struct radv_device *device,
2589 struct radv_shader_variant *shader)
2590 {
2591 mtx_lock(&device->shader_slab_mutex);
2592 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2593 uint64_t offset = 0;
2594 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
2595 if (s->bo_offset - offset >= shader->code_size) {
2596 shader->bo = slab->bo;
2597 shader->bo_offset = offset;
2598 list_addtail(&shader->slab_list, &s->slab_list);
2599 mtx_unlock(&device->shader_slab_mutex);
2600 return slab->ptr + offset;
2601 }
2602 offset = align_u64(s->bo_offset + s->code_size, 256);
2603 }
2604 if (slab->size - offset >= shader->code_size) {
2605 shader->bo = slab->bo;
2606 shader->bo_offset = offset;
2607 list_addtail(&shader->slab_list, &slab->shaders);
2608 mtx_unlock(&device->shader_slab_mutex);
2609 return slab->ptr + offset;
2610 }
2611 }
2612
2613 mtx_unlock(&device->shader_slab_mutex);
2614 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
2615
2616 slab->size = 256 * 1024;
2617 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
2618 RADEON_DOMAIN_VRAM, 0);
2619 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
2620 list_inithead(&slab->shaders);
2621
2622 mtx_lock(&device->shader_slab_mutex);
2623 list_add(&slab->slabs, &device->shader_slabs);
2624
2625 shader->bo = slab->bo;
2626 shader->bo_offset = 0;
2627 list_add(&shader->slab_list, &slab->shaders);
2628 mtx_unlock(&device->shader_slab_mutex);
2629 return slab->ptr;
2630 }
2631
2632 void radv_destroy_shader_slabs(struct radv_device *device)
2633 {
2634 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2635 device->ws->buffer_destroy(slab->bo);
2636 free(slab);
2637 }
2638 mtx_destroy(&device->shader_slab_mutex);
2639 }