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[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107 void radv_DestroyPipeline(
108 VkDevice _device,
109 VkPipeline _pipeline,
110 const VkAllocationCallbacks* pAllocator)
111 {
112 RADV_FROM_HANDLE(radv_device, device, _device);
113 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
114
115 if (!_pipeline)
116 return;
117
118 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
119 if (pipeline->shaders[i])
120 radv_shader_variant_destroy(device, pipeline->shaders[i]);
121
122 vk_free2(&device->alloc, pAllocator, pipeline);
123 }
124
125
126 static void
127 radv_optimize_nir(struct nir_shader *shader)
128 {
129 bool progress;
130
131 do {
132 progress = false;
133
134 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
135 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
136 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
137
138 NIR_PASS(progress, shader, nir_copy_prop);
139 NIR_PASS(progress, shader, nir_opt_remove_phis);
140 NIR_PASS(progress, shader, nir_opt_dce);
141 NIR_PASS(progress, shader, nir_opt_dead_cf);
142 NIR_PASS(progress, shader, nir_opt_cse);
143 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
144 NIR_PASS(progress, shader, nir_opt_algebraic);
145 NIR_PASS(progress, shader, nir_opt_constant_folding);
146 NIR_PASS(progress, shader, nir_opt_undef);
147 NIR_PASS(progress, shader, nir_opt_conditional_discard);
148 } while (progress);
149 }
150
151 static nir_shader *
152 radv_shader_compile_to_nir(struct radv_device *device,
153 struct radv_shader_module *module,
154 const char *entrypoint_name,
155 gl_shader_stage stage,
156 const VkSpecializationInfo *spec_info,
157 bool dump)
158 {
159 if (strcmp(entrypoint_name, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
161 }
162
163 nir_shader *nir;
164 nir_function *entry_point;
165 if (module->nir) {
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
169 nir = module->nir;
170 nir->options = &nir_options;
171 nir_validate_shader(nir);
172
173 assert(exec_list_length(&nir->functions) == 1);
174 struct exec_node *node = exec_list_get_head(&nir->functions);
175 entry_point = exec_node_data(nir_function, node, node);
176 } else {
177 uint32_t *spirv = (uint32_t *) module->data;
178 assert(module->size % 4 == 0);
179
180 uint32_t num_spec_entries = 0;
181 struct nir_spirv_specialization *spec_entries = NULL;
182 if (spec_info && spec_info->mapEntryCount > 0) {
183 num_spec_entries = spec_info->mapEntryCount;
184 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
185 for (uint32_t i = 0; i < num_spec_entries; i++) {
186 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
187 const void *data = spec_info->pData + entry.offset;
188 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
189
190 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
191 if (spec_info->dataSize == 8)
192 spec_entries[i].data64 = *(const uint64_t *)data;
193 else
194 spec_entries[i].data32 = *(const uint32_t *)data;
195 }
196 }
197 const struct nir_spirv_supported_extensions supported_ext = {
198 };
199 entry_point = spirv_to_nir(spirv, module->size / 4,
200 spec_entries, num_spec_entries,
201 stage, entrypoint_name, &supported_ext, &nir_options);
202 nir = entry_point->shader;
203 assert(nir->stage == stage);
204 nir_validate_shader(nir);
205
206 free(spec_entries);
207
208 /* We have to lower away local constant initializers right before we
209 * inline functions. That way they get properly initialized at the top
210 * of the function and not at the top of its caller.
211 */
212 nir_lower_constant_initializers(nir, nir_var_local);
213 nir_validate_shader(nir);
214
215 nir_lower_returns(nir);
216 nir_validate_shader(nir);
217
218 nir_inline_functions(nir);
219 nir_validate_shader(nir);
220
221 /* Pick off the single entrypoint that we want */
222 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
223 if (func != entry_point)
224 exec_node_remove(&func->node);
225 }
226 assert(exec_list_length(&nir->functions) == 1);
227 entry_point->name = ralloc_strdup(entry_point, "main");
228
229 nir_remove_dead_variables(nir, nir_var_shader_in |
230 nir_var_shader_out |
231 nir_var_system_value);
232 nir_validate_shader(nir);
233
234 /* Now that we've deleted all but the main function, we can go ahead and
235 * lower the rest of the constant initializers.
236 */
237 nir_lower_constant_initializers(nir, ~0);
238 nir_validate_shader(nir);
239
240 nir_lower_system_values(nir);
241 nir_validate_shader(nir);
242 }
243
244 /* Vulkan uses the separate-shader linking model */
245 nir->info->separate_shader = true;
246
247 // nir = brw_preprocess_nir(compiler, nir);
248
249 nir_shader_gather_info(nir, entry_point->impl);
250
251 nir_variable_mode indirect_mask = 0;
252 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
253 indirect_mask |= nir_var_shader_in;
254 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
255 indirect_mask |= nir_var_local;
256
257 nir_lower_indirect_derefs(nir, indirect_mask);
258
259 static const nir_lower_tex_options tex_options = {
260 .lower_txp = ~0,
261 };
262
263 nir_lower_tex(nir, &tex_options);
264
265 nir_lower_vars_to_ssa(nir);
266 nir_lower_var_copies(nir);
267 nir_lower_global_vars_to_local(nir);
268 nir_remove_dead_variables(nir, nir_var_local);
269 radv_optimize_nir(nir);
270
271 if (dump)
272 nir_print_shader(nir, stderr);
273
274 return nir;
275 }
276
277 static const char *radv_get_shader_name(struct radv_shader_variant *var,
278 gl_shader_stage stage)
279 {
280 switch (stage) {
281 case MESA_SHADER_VERTEX: return "Vertex Shader as VS";
282 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
283 case MESA_SHADER_COMPUTE: return "Compute Shader";
284 default:
285 return "Unknown shader";
286 };
287
288 }
289 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
290 {
291 unsigned lds_increment = device->instance->physicalDevice.rad_info.chip_class >= CIK ? 512 : 256;
292 struct radv_shader_variant *var;
293 struct ac_shader_config *conf;
294 int i;
295 FILE *file = stderr;
296 unsigned max_simd_waves = 10;
297 unsigned lds_per_wave = 0;
298
299 for (i = 0; i < MESA_SHADER_STAGES; i++) {
300 if (!pipeline->shaders[i])
301 continue;
302 var = pipeline->shaders[i];
303
304 conf = &var->config;
305
306 if (i == MESA_SHADER_FRAGMENT) {
307 lds_per_wave = conf->lds_size * lds_increment +
308 align(var->info.fs.num_interp * 48, lds_increment);
309 }
310
311 if (conf->num_sgprs) {
312 if (device->instance->physicalDevice.rad_info.chip_class >= VI)
313 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
314 else
315 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
316 }
317
318 if (conf->num_vgprs)
319 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
320
321 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
322 * that PS can use.
323 */
324 if (lds_per_wave)
325 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
326
327 fprintf(file, "\n%s:\n",
328 radv_get_shader_name(var, i));
329 if (i == MESA_SHADER_FRAGMENT) {
330 fprintf(file, "*** SHADER CONFIG ***\n"
331 "SPI_PS_INPUT_ADDR = 0x%04x\n"
332 "SPI_PS_INPUT_ENA = 0x%04x\n",
333 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
334 }
335 fprintf(file, "*** SHADER STATS ***\n"
336 "SGPRS: %d\n"
337 "VGPRS: %d\n"
338 "Spilled SGPRs: %d\n"
339 "Spilled VGPRs: %d\n"
340 "Code Size: %d bytes\n"
341 "LDS: %d blocks\n"
342 "Scratch: %d bytes per wave\n"
343 "Max Waves: %d\n"
344 "********************\n\n\n",
345 conf->num_sgprs, conf->num_vgprs,
346 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
347 conf->lds_size, conf->scratch_bytes_per_wave,
348 max_simd_waves);
349 }
350 }
351
352 void radv_shader_variant_destroy(struct radv_device *device,
353 struct radv_shader_variant *variant)
354 {
355 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
356 return;
357
358 device->ws->buffer_destroy(variant->bo);
359 free(variant);
360 }
361
362 static void radv_fill_shader_variant(struct radv_device *device,
363 struct radv_shader_variant *variant,
364 struct ac_shader_binary *binary,
365 gl_shader_stage stage)
366 {
367 variant->code_size = binary->code_size;
368 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
369 unsigned vgpr_comp_cnt = 0;
370
371 if (scratch_enabled)
372 radv_finishme("shader scratch space");
373
374 switch (stage) {
375 case MESA_SHADER_VERTEX:
376 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
377 S_00B12C_SCRATCH_EN(scratch_enabled);
378 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
379 break;
380 case MESA_SHADER_FRAGMENT:
381 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
382 S_00B12C_SCRATCH_EN(scratch_enabled);
383 break;
384 case MESA_SHADER_COMPUTE:
385 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
386 S_00B84C_SCRATCH_EN(scratch_enabled) |
387 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
388 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
389 S_00B84C_TG_SIZE_EN(1) |
390 S_00B84C_LDS_SIZE(variant->config.lds_size);
391 break;
392 default:
393 unreachable("unsupported shader type");
394 break;
395 }
396
397 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
398 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
399 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
400 S_00B848_DX10_CLAMP(1) |
401 S_00B848_FLOAT_MODE(variant->config.float_mode);
402
403 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
404 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
405
406 void *ptr = device->ws->buffer_map(variant->bo);
407 memcpy(ptr, binary->code, binary->code_size);
408 device->ws->buffer_unmap(variant->bo);
409
410
411 }
412
413 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
414 struct nir_shader *shader,
415 struct radv_pipeline_layout *layout,
416 const union ac_shader_variant_key *key,
417 void** code_out,
418 unsigned *code_size_out,
419 bool dump)
420 {
421 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
422 enum radeon_family chip_family = device->instance->physicalDevice.rad_info.family;
423 LLVMTargetMachineRef tm;
424 if (!variant)
425 return NULL;
426
427 struct ac_nir_compiler_options options = {0};
428 options.layout = layout;
429 if (key)
430 options.key = *key;
431
432 struct ac_shader_binary binary;
433
434 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
435 options.family = chip_family;
436 options.chip_class = device->instance->physicalDevice.rad_info.chip_class;
437 tm = ac_create_target_machine(chip_family);
438 ac_compile_nir_shader(tm, &binary, &variant->config,
439 &variant->info, shader, &options, dump);
440 LLVMDisposeTargetMachine(tm);
441
442 radv_fill_shader_variant(device, variant, &binary, shader->stage);
443
444 if (code_out) {
445 *code_out = binary.code;
446 *code_size_out = binary.code_size;
447 } else
448 free(binary.code);
449 free(binary.config);
450 free(binary.rodata);
451 free(binary.global_symbol_offsets);
452 free(binary.relocs);
453 free(binary.disasm_string);
454 variant->ref_count = 1;
455 return variant;
456 }
457
458
459 static struct radv_shader_variant *
460 radv_pipeline_compile(struct radv_pipeline *pipeline,
461 struct radv_pipeline_cache *cache,
462 struct radv_shader_module *module,
463 const char *entrypoint,
464 gl_shader_stage stage,
465 const VkSpecializationInfo *spec_info,
466 struct radv_pipeline_layout *layout,
467 const union ac_shader_variant_key *key)
468 {
469 unsigned char sha1[20];
470 struct radv_shader_variant *variant;
471 nir_shader *nir;
472 void *code = NULL;
473 unsigned code_size = 0;
474 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
475
476 if (module->nir)
477 _mesa_sha1_compute(module->nir->info->name,
478 strlen(module->nir->info->name),
479 module->sha1);
480
481 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key);
482
483 if (cache) {
484 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
485 cache,
486 sha1);
487 if (variant)
488 return variant;
489 }
490
491 nir = radv_shader_compile_to_nir(pipeline->device,
492 module, entrypoint, stage,
493 spec_info, dump);
494 if (nir == NULL)
495 return NULL;
496
497 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
498 &code, &code_size, dump);
499 if (!module->nir)
500 ralloc_free(nir);
501
502 if (variant && cache)
503 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
504 code, code_size);
505
506 if (code)
507 free(code);
508 return variant;
509 }
510
511 static uint32_t si_translate_blend_function(VkBlendOp op)
512 {
513 switch (op) {
514 case VK_BLEND_OP_ADD:
515 return V_028780_COMB_DST_PLUS_SRC;
516 case VK_BLEND_OP_SUBTRACT:
517 return V_028780_COMB_SRC_MINUS_DST;
518 case VK_BLEND_OP_REVERSE_SUBTRACT:
519 return V_028780_COMB_DST_MINUS_SRC;
520 case VK_BLEND_OP_MIN:
521 return V_028780_COMB_MIN_DST_SRC;
522 case VK_BLEND_OP_MAX:
523 return V_028780_COMB_MAX_DST_SRC;
524 default:
525 return 0;
526 }
527 }
528
529 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
530 {
531 switch (factor) {
532 case VK_BLEND_FACTOR_ZERO:
533 return V_028780_BLEND_ZERO;
534 case VK_BLEND_FACTOR_ONE:
535 return V_028780_BLEND_ONE;
536 case VK_BLEND_FACTOR_SRC_COLOR:
537 return V_028780_BLEND_SRC_COLOR;
538 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
539 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
540 case VK_BLEND_FACTOR_DST_COLOR:
541 return V_028780_BLEND_DST_COLOR;
542 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
543 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
544 case VK_BLEND_FACTOR_SRC_ALPHA:
545 return V_028780_BLEND_SRC_ALPHA;
546 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
547 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
548 case VK_BLEND_FACTOR_DST_ALPHA:
549 return V_028780_BLEND_DST_ALPHA;
550 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
551 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
552 case VK_BLEND_FACTOR_CONSTANT_COLOR:
553 return V_028780_BLEND_CONSTANT_COLOR;
554 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
555 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
556 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
557 return V_028780_BLEND_CONSTANT_ALPHA;
558 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
559 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
560 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
561 return V_028780_BLEND_SRC_ALPHA_SATURATE;
562 case VK_BLEND_FACTOR_SRC1_COLOR:
563 return V_028780_BLEND_SRC1_COLOR;
564 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
565 return V_028780_BLEND_INV_SRC1_COLOR;
566 case VK_BLEND_FACTOR_SRC1_ALPHA:
567 return V_028780_BLEND_SRC1_ALPHA;
568 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
569 return V_028780_BLEND_INV_SRC1_ALPHA;
570 default:
571 return 0;
572 }
573 }
574
575 static bool is_dual_src(VkBlendFactor factor)
576 {
577 switch (factor) {
578 case VK_BLEND_FACTOR_SRC1_COLOR:
579 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
580 case VK_BLEND_FACTOR_SRC1_ALPHA:
581 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
582 return true;
583 default:
584 return false;
585 }
586 }
587
588 static unsigned si_choose_spi_color_format(VkFormat vk_format,
589 bool blend_enable,
590 bool blend_need_alpha)
591 {
592 const struct vk_format_description *desc = vk_format_description(vk_format);
593 unsigned format, ntype, swap;
594
595 /* Alpha is needed for alpha-to-coverage.
596 * Blending may be with or without alpha.
597 */
598 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
599 unsigned alpha = 0; /* exports alpha, but may not support blending */
600 unsigned blend = 0; /* supports blending, but may not export alpha */
601 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
602
603 format = radv_translate_colorformat(vk_format);
604 ntype = radv_translate_color_numformat(vk_format, desc,
605 vk_format_get_first_non_void_channel(vk_format));
606 swap = radv_translate_colorswap(vk_format, false);
607
608 /* Choose the SPI color formats. These are required values for Stoney/RB+.
609 * Other chips have multiple choices, though they are not necessarily better.
610 */
611 switch (format) {
612 case V_028C70_COLOR_5_6_5:
613 case V_028C70_COLOR_1_5_5_5:
614 case V_028C70_COLOR_5_5_5_1:
615 case V_028C70_COLOR_4_4_4_4:
616 case V_028C70_COLOR_10_11_11:
617 case V_028C70_COLOR_11_11_10:
618 case V_028C70_COLOR_8:
619 case V_028C70_COLOR_8_8:
620 case V_028C70_COLOR_8_8_8_8:
621 case V_028C70_COLOR_10_10_10_2:
622 case V_028C70_COLOR_2_10_10_10:
623 if (ntype == V_028C70_NUMBER_UINT)
624 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
625 else if (ntype == V_028C70_NUMBER_SINT)
626 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
627 else
628 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
629 break;
630
631 case V_028C70_COLOR_16:
632 case V_028C70_COLOR_16_16:
633 case V_028C70_COLOR_16_16_16_16:
634 if (ntype == V_028C70_NUMBER_UNORM ||
635 ntype == V_028C70_NUMBER_SNORM) {
636 /* UNORM16 and SNORM16 don't support blending */
637 if (ntype == V_028C70_NUMBER_UNORM)
638 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
639 else
640 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
641
642 /* Use 32 bits per channel for blending. */
643 if (format == V_028C70_COLOR_16) {
644 if (swap == V_028C70_SWAP_STD) { /* R */
645 blend = V_028714_SPI_SHADER_32_R;
646 blend_alpha = V_028714_SPI_SHADER_32_AR;
647 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
648 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
649 else
650 assert(0);
651 } else if (format == V_028C70_COLOR_16_16) {
652 if (swap == V_028C70_SWAP_STD) { /* RG */
653 blend = V_028714_SPI_SHADER_32_GR;
654 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
655 } else if (swap == V_028C70_SWAP_ALT) /* RA */
656 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
657 else
658 assert(0);
659 } else /* 16_16_16_16 */
660 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
661 } else if (ntype == V_028C70_NUMBER_UINT)
662 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
663 else if (ntype == V_028C70_NUMBER_SINT)
664 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
665 else if (ntype == V_028C70_NUMBER_FLOAT)
666 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
667 else
668 assert(0);
669 break;
670
671 case V_028C70_COLOR_32:
672 if (swap == V_028C70_SWAP_STD) { /* R */
673 blend = normal = V_028714_SPI_SHADER_32_R;
674 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
675 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
676 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
677 else
678 assert(0);
679 break;
680
681 case V_028C70_COLOR_32_32:
682 if (swap == V_028C70_SWAP_STD) { /* RG */
683 blend = normal = V_028714_SPI_SHADER_32_GR;
684 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
685 } else if (swap == V_028C70_SWAP_ALT) /* RA */
686 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
687 else
688 assert(0);
689 break;
690
691 case V_028C70_COLOR_32_32_32_32:
692 case V_028C70_COLOR_8_24:
693 case V_028C70_COLOR_24_8:
694 case V_028C70_COLOR_X24_8_32_FLOAT:
695 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
696 break;
697
698 default:
699 unreachable("unhandled blend format");
700 }
701
702 if (blend_enable && blend_need_alpha)
703 return blend_alpha;
704 else if(blend_need_alpha)
705 return alpha;
706 else if(blend_enable)
707 return blend;
708 else
709 return normal;
710 }
711
712 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
713 {
714 unsigned i, cb_shader_mask = 0;
715
716 for (i = 0; i < 8; i++) {
717 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
718 case V_028714_SPI_SHADER_ZERO:
719 break;
720 case V_028714_SPI_SHADER_32_R:
721 cb_shader_mask |= 0x1 << (i * 4);
722 break;
723 case V_028714_SPI_SHADER_32_GR:
724 cb_shader_mask |= 0x3 << (i * 4);
725 break;
726 case V_028714_SPI_SHADER_32_AR:
727 cb_shader_mask |= 0x9 << (i * 4);
728 break;
729 case V_028714_SPI_SHADER_FP16_ABGR:
730 case V_028714_SPI_SHADER_UNORM16_ABGR:
731 case V_028714_SPI_SHADER_SNORM16_ABGR:
732 case V_028714_SPI_SHADER_UINT16_ABGR:
733 case V_028714_SPI_SHADER_SINT16_ABGR:
734 case V_028714_SPI_SHADER_32_ABGR:
735 cb_shader_mask |= 0xf << (i * 4);
736 break;
737 default:
738 assert(0);
739 }
740 }
741 return cb_shader_mask;
742 }
743
744 static void
745 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
746 const VkGraphicsPipelineCreateInfo *pCreateInfo,
747 uint32_t blend_enable,
748 uint32_t blend_need_alpha,
749 bool single_cb_enable,
750 bool blend_mrt0_is_dual_src)
751 {
752 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
753 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
754 struct radv_blend_state *blend = &pipeline->graphics.blend;
755 unsigned col_format = 0;
756
757 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
758 struct radv_render_pass_attachment *attachment;
759 unsigned cf;
760
761 attachment = pass->attachments + subpass->color_attachments[i].attachment;
762
763 cf = si_choose_spi_color_format(attachment->format,
764 blend_enable & (1 << i),
765 blend_need_alpha & (1 << i));
766
767 col_format |= cf << (4 * i);
768 }
769
770 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
771
772 if (blend_mrt0_is_dual_src)
773 col_format |= (col_format & 0xf) << 4;
774 if (!col_format)
775 col_format |= V_028714_SPI_SHADER_32_R;
776 blend->spi_shader_col_format = col_format;
777 }
778
779 static bool
780 format_is_int8(VkFormat format)
781 {
782 const struct vk_format_description *desc = vk_format_description(format);
783 int channel = vk_format_get_first_non_void_channel(format);
784
785 return channel >= 0 && desc->channel[channel].pure_integer &&
786 desc->channel[channel].size == 8;
787 }
788
789 unsigned radv_format_meta_fs_key(VkFormat format)
790 {
791 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
792 bool is_int8 = format_is_int8(format);
793
794 return col_format + (is_int8 ? 3 : 0);
795 }
796
797 static unsigned
798 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
799 {
800 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
801 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
802 unsigned is_int8 = 0;
803
804 for (unsigned i = 0; i < subpass->color_count; ++i) {
805 struct radv_render_pass_attachment *attachment;
806
807 attachment = pass->attachments + subpass->color_attachments[i].attachment;
808
809 if (format_is_int8(attachment->format))
810 is_int8 |= 1 << i;
811 }
812
813 return is_int8;
814 }
815
816 static void
817 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
818 const VkGraphicsPipelineCreateInfo *pCreateInfo,
819 const struct radv_graphics_pipeline_create_info *extra)
820 {
821 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
822 struct radv_blend_state *blend = &pipeline->graphics.blend;
823 unsigned mode = V_028808_CB_NORMAL;
824 uint32_t blend_enable = 0, blend_need_alpha = 0;
825 bool blend_mrt0_is_dual_src = false;
826 int i;
827 bool single_cb_enable = false;
828
829 if (!vkblend)
830 return;
831
832 if (extra && extra->custom_blend_mode) {
833 single_cb_enable = true;
834 mode = extra->custom_blend_mode;
835 }
836 blend->cb_color_control = 0;
837 if (vkblend->logicOpEnable)
838 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
839 else
840 blend->cb_color_control |= S_028808_ROP3(0xcc);
841
842 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
843 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
844 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
845 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
846
847 blend->cb_target_mask = 0;
848 for (i = 0; i < vkblend->attachmentCount; i++) {
849 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
850 unsigned blend_cntl = 0;
851 VkBlendOp eqRGB = att->colorBlendOp;
852 VkBlendFactor srcRGB = att->srcColorBlendFactor;
853 VkBlendFactor dstRGB = att->dstColorBlendFactor;
854 VkBlendOp eqA = att->alphaBlendOp;
855 VkBlendFactor srcA = att->srcAlphaBlendFactor;
856 VkBlendFactor dstA = att->dstAlphaBlendFactor;
857
858 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
859
860 if (!att->colorWriteMask)
861 continue;
862
863 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
864 if (!att->blendEnable) {
865 blend->cb_blend_control[i] = blend_cntl;
866 continue;
867 }
868
869 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
870 if (i == 0)
871 blend_mrt0_is_dual_src = true;
872
873 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
874 srcRGB = VK_BLEND_FACTOR_ONE;
875 dstRGB = VK_BLEND_FACTOR_ONE;
876 }
877 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
878 srcA = VK_BLEND_FACTOR_ONE;
879 dstA = VK_BLEND_FACTOR_ONE;
880 }
881
882 blend_cntl |= S_028780_ENABLE(1);
883
884 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
885 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
886 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
887 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
888 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
889 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
890 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
891 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
892 }
893 blend->cb_blend_control[i] = blend_cntl;
894
895 blend_enable |= 1 << i;
896
897 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
898 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
899 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
900 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
901 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
902 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
903 blend_need_alpha |= 1 << i;
904 }
905 for (i = vkblend->attachmentCount; i < 8; i++)
906 blend->cb_blend_control[i] = 0;
907
908 if (blend->cb_target_mask)
909 blend->cb_color_control |= S_028808_MODE(mode);
910 else
911 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
912
913 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
914 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
915 }
916
917 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
918 {
919 switch (op) {
920 case VK_STENCIL_OP_KEEP:
921 return V_02842C_STENCIL_KEEP;
922 case VK_STENCIL_OP_ZERO:
923 return V_02842C_STENCIL_ZERO;
924 case VK_STENCIL_OP_REPLACE:
925 return V_02842C_STENCIL_REPLACE_TEST;
926 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
927 return V_02842C_STENCIL_ADD_CLAMP;
928 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
929 return V_02842C_STENCIL_SUB_CLAMP;
930 case VK_STENCIL_OP_INVERT:
931 return V_02842C_STENCIL_INVERT;
932 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
933 return V_02842C_STENCIL_ADD_WRAP;
934 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
935 return V_02842C_STENCIL_SUB_WRAP;
936 default:
937 return 0;
938 }
939 }
940 static void
941 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
942 const VkGraphicsPipelineCreateInfo *pCreateInfo,
943 const struct radv_graphics_pipeline_create_info *extra)
944 {
945 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
946 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
947
948 memset(ds, 0, sizeof(*ds));
949 if (!vkds)
950 return;
951 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
952 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
953 S_028800_ZFUNC(vkds->depthCompareOp) |
954 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
955
956 if (vkds->stencilTestEnable) {
957 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
958 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
959 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
960 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
961 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
962
963 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
964 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
965 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
966 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
967 }
968
969 if (extra) {
970
971 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
972 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
973
974 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
975 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
976 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
977 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
978 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
979 }
980 }
981
982 static uint32_t si_translate_fill(VkPolygonMode func)
983 {
984 switch(func) {
985 case VK_POLYGON_MODE_FILL:
986 return V_028814_X_DRAW_TRIANGLES;
987 case VK_POLYGON_MODE_LINE:
988 return V_028814_X_DRAW_LINES;
989 case VK_POLYGON_MODE_POINT:
990 return V_028814_X_DRAW_POINTS;
991 default:
992 assert(0);
993 return V_028814_X_DRAW_POINTS;
994 }
995 }
996 static void
997 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
998 const VkGraphicsPipelineCreateInfo *pCreateInfo)
999 {
1000 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1001 struct radv_raster_state *raster = &pipeline->graphics.raster;
1002
1003 memset(raster, 0, sizeof(*raster));
1004
1005 raster->spi_interp_control =
1006 S_0286D4_FLAT_SHADE_ENA(1) |
1007 S_0286D4_PNT_SPRITE_ENA(1) |
1008 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1009 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1010 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1011 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1012 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1013
1014 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
1015 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1016 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1017 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1018 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1019 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1020 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1021
1022 raster->pa_su_vtx_cntl =
1023 S_028BE4_PIX_CENTER(1) | // TODO verify
1024 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1025 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1026
1027 raster->pa_su_sc_mode_cntl =
1028 S_028814_FACE(vkraster->frontFace) |
1029 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1030 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1031 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1032 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1033 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1034 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1035 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1036 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1037
1038 }
1039
1040 static void
1041 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1042 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1043 {
1044 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1045 struct radv_blend_state *blend = &pipeline->graphics.blend;
1046 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1047 unsigned num_tile_pipes = pipeline->device->instance->physicalDevice.rad_info.num_tile_pipes;
1048 int ps_iter_samples = 1;
1049 uint32_t mask = 0xffff;
1050
1051 ms->num_samples = vkms->rasterizationSamples;
1052
1053 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1054 ps_iter_samples = vkms->rasterizationSamples;
1055 }
1056
1057 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1058 ms->pa_sc_aa_config = 0;
1059 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1060 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1061 ms->pa_sc_mode_cntl_1 =
1062 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1063 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1064 /* always 1: */
1065 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1066 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1067 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1068 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1069 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1070 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1071
1072 if (vkms->rasterizationSamples > 1) {
1073 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1074 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1075 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1076 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1077 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1078 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1079 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1080 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1081 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1082 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1083 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1084 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1085 }
1086
1087 if (vkms->alphaToCoverageEnable)
1088 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1089
1090 if (vkms->pSampleMask) {
1091 mask = vkms->pSampleMask[0] & 0xffff;
1092 }
1093
1094 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1095 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1096 }
1097
1098 static uint32_t
1099 si_translate_prim(enum VkPrimitiveTopology topology)
1100 {
1101 switch (topology) {
1102 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1103 return V_008958_DI_PT_POINTLIST;
1104 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1105 return V_008958_DI_PT_LINELIST;
1106 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1107 return V_008958_DI_PT_LINESTRIP;
1108 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1109 return V_008958_DI_PT_TRILIST;
1110 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1111 return V_008958_DI_PT_TRISTRIP;
1112 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1113 return V_008958_DI_PT_TRIFAN;
1114 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1115 return V_008958_DI_PT_LINELIST_ADJ;
1116 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1117 return V_008958_DI_PT_LINESTRIP_ADJ;
1118 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1119 return V_008958_DI_PT_TRILIST_ADJ;
1120 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1121 return V_008958_DI_PT_TRISTRIP_ADJ;
1122 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1123 return V_008958_DI_PT_PATCH;
1124 default:
1125 assert(0);
1126 return 0;
1127 }
1128 }
1129
1130 static uint32_t
1131 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1132 {
1133 switch (topology) {
1134 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1135 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1136 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1137 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1138 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1139 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1140 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1141 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1142 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1143 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1144 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1145 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1146 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1147 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1148 default:
1149 assert(0);
1150 return 0;
1151 }
1152 }
1153
1154 static unsigned si_map_swizzle(unsigned swizzle)
1155 {
1156 switch (swizzle) {
1157 case VK_SWIZZLE_Y:
1158 return V_008F0C_SQ_SEL_Y;
1159 case VK_SWIZZLE_Z:
1160 return V_008F0C_SQ_SEL_Z;
1161 case VK_SWIZZLE_W:
1162 return V_008F0C_SQ_SEL_W;
1163 case VK_SWIZZLE_0:
1164 return V_008F0C_SQ_SEL_0;
1165 case VK_SWIZZLE_1:
1166 return V_008F0C_SQ_SEL_1;
1167 default: /* VK_SWIZZLE_X */
1168 return V_008F0C_SQ_SEL_X;
1169 }
1170 }
1171
1172 static void
1173 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1174 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1175 {
1176 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1177 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1178 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1179
1180 pipeline->dynamic_state = default_dynamic_state;
1181
1182 if (pCreateInfo->pDynamicState) {
1183 /* Remove all of the states that are marked as dynamic */
1184 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1185 for (uint32_t s = 0; s < count; s++)
1186 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1187 }
1188
1189 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1190
1191 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1192 *
1193 * pViewportState is [...] NULL if the pipeline
1194 * has rasterization disabled.
1195 */
1196 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1197 assert(pCreateInfo->pViewportState);
1198
1199 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1200 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1201 typed_memcpy(dynamic->viewport.viewports,
1202 pCreateInfo->pViewportState->pViewports,
1203 pCreateInfo->pViewportState->viewportCount);
1204 }
1205
1206 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1207 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1208 typed_memcpy(dynamic->scissor.scissors,
1209 pCreateInfo->pViewportState->pScissors,
1210 pCreateInfo->pViewportState->scissorCount);
1211 }
1212 }
1213
1214 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1215 assert(pCreateInfo->pRasterizationState);
1216 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1217 }
1218
1219 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1220 assert(pCreateInfo->pRasterizationState);
1221 dynamic->depth_bias.bias =
1222 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1223 dynamic->depth_bias.clamp =
1224 pCreateInfo->pRasterizationState->depthBiasClamp;
1225 dynamic->depth_bias.slope =
1226 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1227 }
1228
1229 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1230 *
1231 * pColorBlendState is [...] NULL if the pipeline has rasterization
1232 * disabled or if the subpass of the render pass the pipeline is
1233 * created against does not use any color attachments.
1234 */
1235 bool uses_color_att = false;
1236 for (unsigned i = 0; i < subpass->color_count; ++i) {
1237 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1238 uses_color_att = true;
1239 break;
1240 }
1241 }
1242
1243 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1244 assert(pCreateInfo->pColorBlendState);
1245 typed_memcpy(dynamic->blend_constants,
1246 pCreateInfo->pColorBlendState->blendConstants, 4);
1247 }
1248
1249 /* If there is no depthstencil attachment, then don't read
1250 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1251 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1252 * no need to override the depthstencil defaults in
1253 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1254 *
1255 * Section 9.2 of the Vulkan 1.0.15 spec says:
1256 *
1257 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1258 * disabled or if the subpass of the render pass the pipeline is created
1259 * against does not use a depth/stencil attachment.
1260 */
1261 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1262 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1263 assert(pCreateInfo->pDepthStencilState);
1264
1265 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1266 dynamic->depth_bounds.min =
1267 pCreateInfo->pDepthStencilState->minDepthBounds;
1268 dynamic->depth_bounds.max =
1269 pCreateInfo->pDepthStencilState->maxDepthBounds;
1270 }
1271
1272 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1273 dynamic->stencil_compare_mask.front =
1274 pCreateInfo->pDepthStencilState->front.compareMask;
1275 dynamic->stencil_compare_mask.back =
1276 pCreateInfo->pDepthStencilState->back.compareMask;
1277 }
1278
1279 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1280 dynamic->stencil_write_mask.front =
1281 pCreateInfo->pDepthStencilState->front.writeMask;
1282 dynamic->stencil_write_mask.back =
1283 pCreateInfo->pDepthStencilState->back.writeMask;
1284 }
1285
1286 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1287 dynamic->stencil_reference.front =
1288 pCreateInfo->pDepthStencilState->front.reference;
1289 dynamic->stencil_reference.back =
1290 pCreateInfo->pDepthStencilState->back.reference;
1291 }
1292 }
1293
1294 pipeline->dynamic_state_mask = states;
1295 }
1296
1297 static union ac_shader_variant_key
1298 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1299 {
1300 union ac_shader_variant_key key;
1301 const VkPipelineVertexInputStateCreateInfo *input_state =
1302 pCreateInfo->pVertexInputState;
1303
1304 memset(&key, 0, sizeof(key));
1305 key.vs.instance_rate_inputs = 0;
1306
1307 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1308 unsigned binding;
1309 binding = input_state->pVertexAttributeDescriptions[i].binding;
1310 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1311 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1312 }
1313 return key;
1314 }
1315
1316 VkResult
1317 radv_pipeline_init(struct radv_pipeline *pipeline,
1318 struct radv_device *device,
1319 struct radv_pipeline_cache *cache,
1320 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1321 const struct radv_graphics_pipeline_create_info *extra,
1322 const VkAllocationCallbacks *alloc)
1323 {
1324 struct radv_shader_module fs_m = {0};
1325
1326 if (alloc == NULL)
1327 alloc = &device->alloc;
1328
1329 pipeline->device = device;
1330 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1331
1332 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1333 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1334 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1335 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1336 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1337 pStages[stage] = &pCreateInfo->pStages[i];
1338 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1339 }
1340
1341 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1342
1343 /* */
1344 if (modules[MESA_SHADER_VERTEX]) {
1345 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
1346
1347 pipeline->shaders[MESA_SHADER_VERTEX] =
1348 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1349 pStages[MESA_SHADER_VERTEX]->pName,
1350 MESA_SHADER_VERTEX,
1351 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1352 pipeline->layout, &key);
1353
1354 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1355 }
1356
1357 if (!modules[MESA_SHADER_FRAGMENT]) {
1358 nir_builder fs_b;
1359 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1360 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1361 fs_m.nir = fs_b.shader;
1362 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1363 }
1364
1365 if (modules[MESA_SHADER_FRAGMENT]) {
1366 union ac_shader_variant_key key;
1367 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1368 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1369
1370 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1371
1372 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1373 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1374 stage ? stage->pName : "main",
1375 MESA_SHADER_FRAGMENT,
1376 stage ? stage->pSpecializationInfo : NULL,
1377 pipeline->layout, &key);
1378 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1379 }
1380
1381 if (fs_m.nir)
1382 ralloc_free(fs_m.nir);
1383
1384 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1385 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1386 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1387 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1388 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1389 if (extra && extra->use_rectlist) {
1390 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1391 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1392 }
1393 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1394
1395 const VkPipelineVertexInputStateCreateInfo *vi_info =
1396 pCreateInfo->pVertexInputState;
1397 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1398 const VkVertexInputAttributeDescription *desc =
1399 &vi_info->pVertexAttributeDescriptions[i];
1400 unsigned loc = desc->location;
1401 const struct vk_format_description *format_desc;
1402 int first_non_void;
1403 uint32_t num_format, data_format;
1404 format_desc = vk_format_description(desc->format);
1405 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1406
1407 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1408 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1409
1410 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1411 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1412 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1413 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1414 S_008F0C_NUM_FORMAT(num_format) |
1415 S_008F0C_DATA_FORMAT(data_format);
1416 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1417 pipeline->va_offset[loc] = desc->offset;
1418 pipeline->va_binding[loc] = desc->binding;
1419 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1420 }
1421
1422 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1423 const VkVertexInputBindingDescription *desc =
1424 &vi_info->pVertexBindingDescriptions[i];
1425
1426 pipeline->binding_stride[desc->binding] = desc->stride;
1427 }
1428
1429 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1430 radv_dump_pipeline_stats(device, pipeline);
1431 }
1432
1433 return VK_SUCCESS;
1434 }
1435
1436 VkResult
1437 radv_graphics_pipeline_create(
1438 VkDevice _device,
1439 VkPipelineCache _cache,
1440 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1441 const struct radv_graphics_pipeline_create_info *extra,
1442 const VkAllocationCallbacks *pAllocator,
1443 VkPipeline *pPipeline)
1444 {
1445 RADV_FROM_HANDLE(radv_device, device, _device);
1446 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1447 struct radv_pipeline *pipeline;
1448 VkResult result;
1449
1450 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1451 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1452 if (pipeline == NULL)
1453 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1454
1455 memset(pipeline, 0, sizeof(*pipeline));
1456 result = radv_pipeline_init(pipeline, device, cache,
1457 pCreateInfo, extra, pAllocator);
1458 if (result != VK_SUCCESS) {
1459 vk_free2(&device->alloc, pAllocator, pipeline);
1460 return result;
1461 }
1462
1463 *pPipeline = radv_pipeline_to_handle(pipeline);
1464
1465 return VK_SUCCESS;
1466 }
1467
1468 VkResult radv_CreateGraphicsPipelines(
1469 VkDevice _device,
1470 VkPipelineCache pipelineCache,
1471 uint32_t count,
1472 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1473 const VkAllocationCallbacks* pAllocator,
1474 VkPipeline* pPipelines)
1475 {
1476 VkResult result = VK_SUCCESS;
1477 unsigned i = 0;
1478
1479 for (; i < count; i++) {
1480 VkResult r;
1481 r = radv_graphics_pipeline_create(_device,
1482 pipelineCache,
1483 &pCreateInfos[i],
1484 NULL, pAllocator, &pPipelines[i]);
1485 if (r != VK_SUCCESS) {
1486 result = r;
1487 pPipelines[i] = VK_NULL_HANDLE;
1488 }
1489 }
1490
1491 return result;
1492 }
1493
1494 static VkResult radv_compute_pipeline_create(
1495 VkDevice _device,
1496 VkPipelineCache _cache,
1497 const VkComputePipelineCreateInfo* pCreateInfo,
1498 const VkAllocationCallbacks* pAllocator,
1499 VkPipeline* pPipeline)
1500 {
1501 RADV_FROM_HANDLE(radv_device, device, _device);
1502 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1503 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1504 struct radv_pipeline *pipeline;
1505
1506 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1507 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1508 if (pipeline == NULL)
1509 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1510
1511 memset(pipeline, 0, sizeof(*pipeline));
1512 pipeline->device = device;
1513 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1514
1515 pipeline->shaders[MESA_SHADER_COMPUTE] =
1516 radv_pipeline_compile(pipeline, cache, module,
1517 pCreateInfo->stage.pName,
1518 MESA_SHADER_COMPUTE,
1519 pCreateInfo->stage.pSpecializationInfo,
1520 pipeline->layout, NULL);
1521
1522 *pPipeline = radv_pipeline_to_handle(pipeline);
1523
1524 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1525 radv_dump_pipeline_stats(device, pipeline);
1526 }
1527 return VK_SUCCESS;
1528 }
1529 VkResult radv_CreateComputePipelines(
1530 VkDevice _device,
1531 VkPipelineCache pipelineCache,
1532 uint32_t count,
1533 const VkComputePipelineCreateInfo* pCreateInfos,
1534 const VkAllocationCallbacks* pAllocator,
1535 VkPipeline* pPipelines)
1536 {
1537 VkResult result = VK_SUCCESS;
1538
1539 unsigned i = 0;
1540 for (; i < count; i++) {
1541 VkResult r;
1542 r = radv_compute_pipeline_create(_device, pipelineCache,
1543 &pCreateInfos[i],
1544 pAllocator, &pPipelines[i]);
1545 if (r != VK_SUCCESS) {
1546 result = r;
1547 pPipelines[i] = VK_NULL_HANDLE;
1548 }
1549 }
1550
1551 return result;
1552 }