2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
39 #include "r600d_common.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "vk_format.h"
44 #include "util/debug.h"
45 #include "ac_exp_param.h"
47 void radv_shader_variant_destroy(struct radv_device
*device
,
48 struct radv_shader_variant
*variant
);
50 static const struct nir_shader_compiler_options nir_options
= {
51 .vertex_id_zero_based
= true,
57 .lower_pack_snorm_2x16
= true,
58 .lower_pack_snorm_4x8
= true,
59 .lower_pack_unorm_2x16
= true,
60 .lower_pack_unorm_4x8
= true,
61 .lower_unpack_snorm_2x16
= true,
62 .lower_unpack_snorm_4x8
= true,
63 .lower_unpack_unorm_2x16
= true,
64 .lower_unpack_unorm_4x8
= true,
65 .lower_extract_byte
= true,
66 .lower_extract_word
= true,
67 .max_unroll_iterations
= 32
70 VkResult
radv_CreateShaderModule(
72 const VkShaderModuleCreateInfo
* pCreateInfo
,
73 const VkAllocationCallbacks
* pAllocator
,
74 VkShaderModule
* pShaderModule
)
76 RADV_FROM_HANDLE(radv_device
, device
, _device
);
77 struct radv_shader_module
*module
;
79 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
80 assert(pCreateInfo
->flags
== 0);
82 module
= vk_alloc2(&device
->alloc
, pAllocator
,
83 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
84 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
86 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
89 module
->size
= pCreateInfo
->codeSize
;
90 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
92 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
94 *pShaderModule
= radv_shader_module_to_handle(module
);
99 void radv_DestroyShaderModule(
101 VkShaderModule _module
,
102 const VkAllocationCallbacks
* pAllocator
)
104 RADV_FROM_HANDLE(radv_device
, device
, _device
);
105 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
110 vk_free2(&device
->alloc
, pAllocator
, module
);
115 radv_pipeline_destroy(struct radv_device
*device
,
116 struct radv_pipeline
*pipeline
,
117 const VkAllocationCallbacks
* allocator
)
119 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
120 if (pipeline
->shaders
[i
])
121 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
123 if (pipeline
->gs_copy_shader
)
124 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
126 vk_free2(&device
->alloc
, allocator
, pipeline
);
129 void radv_DestroyPipeline(
131 VkPipeline _pipeline
,
132 const VkAllocationCallbacks
* pAllocator
)
134 RADV_FROM_HANDLE(radv_device
, device
, _device
);
135 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
140 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
145 radv_optimize_nir(struct nir_shader
*shader
)
152 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
153 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
154 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
156 NIR_PASS(progress
, shader
, nir_copy_prop
);
157 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
158 NIR_PASS(progress
, shader
, nir_opt_dce
);
159 if (nir_opt_trivial_continues(shader
)) {
161 NIR_PASS(progress
, shader
, nir_copy_prop
);
162 NIR_PASS(progress
, shader
, nir_opt_dce
);
164 NIR_PASS(progress
, shader
, nir_opt_if
);
165 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
166 NIR_PASS(progress
, shader
, nir_opt_cse
);
167 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
168 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
169 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
170 NIR_PASS(progress
, shader
, nir_opt_undef
);
171 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
172 if (shader
->options
->max_unroll_iterations
) {
173 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
179 radv_shader_compile_to_nir(struct radv_device
*device
,
180 struct radv_shader_module
*module
,
181 const char *entrypoint_name
,
182 gl_shader_stage stage
,
183 const VkSpecializationInfo
*spec_info
,
186 if (strcmp(entrypoint_name
, "main") != 0) {
187 radv_finishme("Multiple shaders per module not really supported");
191 nir_function
*entry_point
;
193 /* Some things such as our meta clear/blit code will give us a NIR
194 * shader directly. In that case, we just ignore the SPIR-V entirely
195 * and just use the NIR shader */
197 nir
->options
= &nir_options
;
198 nir_validate_shader(nir
);
200 assert(exec_list_length(&nir
->functions
) == 1);
201 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
202 entry_point
= exec_node_data(nir_function
, node
, node
);
204 uint32_t *spirv
= (uint32_t *) module
->data
;
205 assert(module
->size
% 4 == 0);
207 uint32_t num_spec_entries
= 0;
208 struct nir_spirv_specialization
*spec_entries
= NULL
;
209 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
210 num_spec_entries
= spec_info
->mapEntryCount
;
211 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
212 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
213 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
214 const void *data
= spec_info
->pData
+ entry
.offset
;
215 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
217 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
218 if (spec_info
->dataSize
== 8)
219 spec_entries
[i
].data64
= *(const uint64_t *)data
;
221 spec_entries
[i
].data32
= *(const uint32_t *)data
;
224 const struct nir_spirv_supported_extensions supported_ext
= {
225 .draw_parameters
= true,
227 .image_read_without_format
= true,
228 .image_write_without_format
= true,
229 .tessellation
= true,
231 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
232 spec_entries
, num_spec_entries
,
233 stage
, entrypoint_name
, &supported_ext
, &nir_options
);
234 nir
= entry_point
->shader
;
235 assert(nir
->stage
== stage
);
236 nir_validate_shader(nir
);
240 /* We have to lower away local constant initializers right before we
241 * inline functions. That way they get properly initialized at the top
242 * of the function and not at the top of its caller.
244 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
245 NIR_PASS_V(nir
, nir_lower_returns
);
246 NIR_PASS_V(nir
, nir_inline_functions
);
248 /* Pick off the single entrypoint that we want */
249 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
250 if (func
!= entry_point
)
251 exec_node_remove(&func
->node
);
253 assert(exec_list_length(&nir
->functions
) == 1);
254 entry_point
->name
= ralloc_strdup(entry_point
, "main");
256 NIR_PASS_V(nir
, nir_remove_dead_variables
,
257 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
259 /* Now that we've deleted all but the main function, we can go ahead and
260 * lower the rest of the constant initializers.
262 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
263 NIR_PASS_V(nir
, nir_lower_system_values
);
264 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
267 /* Vulkan uses the separate-shader linking model */
268 nir
->info
.separate_shader
= true;
270 nir_shader_gather_info(nir
, entry_point
->impl
);
272 nir_variable_mode indirect_mask
= 0;
273 indirect_mask
|= nir_var_shader_in
;
274 indirect_mask
|= nir_var_local
;
276 nir_lower_indirect_derefs(nir
, indirect_mask
);
278 static const nir_lower_tex_options tex_options
= {
282 nir_lower_tex(nir
, &tex_options
);
284 nir_lower_vars_to_ssa(nir
);
285 nir_lower_var_copies(nir
);
286 nir_lower_global_vars_to_local(nir
);
287 nir_remove_dead_variables(nir
, nir_var_local
);
288 radv_optimize_nir(nir
);
291 nir_print_shader(nir
, stderr
);
296 static const char *radv_get_shader_name(struct radv_shader_variant
*var
,
297 gl_shader_stage stage
)
300 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
301 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
302 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
303 case MESA_SHADER_COMPUTE
: return "Compute Shader";
304 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
305 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
307 return "Unknown shader";
311 static void radv_dump_pipeline_stats(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
313 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
314 struct radv_shader_variant
*var
;
315 struct ac_shader_config
*conf
;
318 unsigned max_simd_waves
= 10;
319 unsigned lds_per_wave
= 0;
321 for (i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
322 if (!pipeline
->shaders
[i
])
324 var
= pipeline
->shaders
[i
];
328 if (i
== MESA_SHADER_FRAGMENT
) {
329 lds_per_wave
= conf
->lds_size
* lds_increment
+
330 align(var
->info
.fs
.num_interp
* 48, lds_increment
);
333 if (conf
->num_sgprs
) {
334 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
335 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
337 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
341 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
343 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
347 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
349 fprintf(file
, "\n%s:\n",
350 radv_get_shader_name(var
, i
));
351 if (i
== MESA_SHADER_FRAGMENT
) {
352 fprintf(file
, "*** SHADER CONFIG ***\n"
353 "SPI_PS_INPUT_ADDR = 0x%04x\n"
354 "SPI_PS_INPUT_ENA = 0x%04x\n",
355 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
357 fprintf(file
, "*** SHADER STATS ***\n"
360 "Spilled SGPRs: %d\n"
361 "Spilled VGPRs: %d\n"
362 "Code Size: %d bytes\n"
364 "Scratch: %d bytes per wave\n"
366 "********************\n\n\n",
367 conf
->num_sgprs
, conf
->num_vgprs
,
368 conf
->spilled_sgprs
, conf
->spilled_vgprs
, var
->code_size
,
369 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
374 void radv_shader_variant_destroy(struct radv_device
*device
,
375 struct radv_shader_variant
*variant
)
377 if (__sync_fetch_and_sub(&variant
->ref_count
, 1) != 1)
380 device
->ws
->buffer_destroy(variant
->bo
);
384 static void radv_fill_shader_variant(struct radv_device
*device
,
385 struct radv_shader_variant
*variant
,
386 struct ac_shader_binary
*binary
,
387 gl_shader_stage stage
)
389 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
390 unsigned vgpr_comp_cnt
= 0;
392 if (scratch_enabled
&& !device
->llvm_supports_spill
)
393 radv_finishme("shader scratch support only available with LLVM 4.0");
395 variant
->code_size
= binary
->code_size
;
396 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
397 S_00B12C_SCRATCH_EN(scratch_enabled
);
400 case MESA_SHADER_TESS_EVAL
:
403 case MESA_SHADER_TESS_CTRL
:
404 variant
->rsrc2
|= S_00B42C_OC_LDS_EN(1);
406 case MESA_SHADER_VERTEX
:
407 case MESA_SHADER_GEOMETRY
:
408 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
410 case MESA_SHADER_FRAGMENT
:
412 case MESA_SHADER_COMPUTE
:
414 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
415 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
416 S_00B84C_TG_SIZE_EN(1) |
417 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
420 unreachable("unsupported shader type");
424 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
425 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
426 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
427 S_00B848_DX10_CLAMP(1) |
428 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
430 variant
->bo
= device
->ws
->buffer_create(device
->ws
, binary
->code_size
, 256,
431 RADEON_DOMAIN_VRAM
, RADEON_FLAG_CPU_ACCESS
);
433 void *ptr
= device
->ws
->buffer_map(variant
->bo
);
434 memcpy(ptr
, binary
->code
, binary
->code_size
);
435 device
->ws
->buffer_unmap(variant
->bo
);
440 static struct radv_shader_variant
*radv_shader_variant_create(struct radv_device
*device
,
441 struct nir_shader
*shader
,
442 struct radv_pipeline_layout
*layout
,
443 const union ac_shader_variant_key
*key
,
445 unsigned *code_size_out
,
448 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
449 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
450 LLVMTargetMachineRef tm
;
454 struct ac_nir_compiler_options options
= {0};
455 options
.layout
= layout
;
459 struct ac_shader_binary binary
;
461 options
.unsafe_math
= !!(device
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
462 options
.family
= chip_family
;
463 options
.chip_class
= device
->physical_device
->rad_info
.chip_class
;
464 options
.supports_spill
= device
->llvm_supports_spill
;
465 tm
= ac_create_target_machine(chip_family
, options
.supports_spill
);
466 ac_compile_nir_shader(tm
, &binary
, &variant
->config
,
467 &variant
->info
, shader
, &options
, dump
);
468 LLVMDisposeTargetMachine(tm
);
470 radv_fill_shader_variant(device
, variant
, &binary
, shader
->stage
);
473 *code_out
= binary
.code
;
474 *code_size_out
= binary
.code_size
;
479 free(binary
.global_symbol_offsets
);
481 free(binary
.disasm_string
);
482 variant
->ref_count
= 1;
486 static struct radv_shader_variant
*
487 radv_pipeline_create_gs_copy_shader(struct radv_pipeline
*pipeline
,
488 struct nir_shader
*nir
,
490 unsigned *code_size_out
,
493 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
494 enum radeon_family chip_family
= pipeline
->device
->physical_device
->rad_info
.family
;
495 LLVMTargetMachineRef tm
;
499 struct ac_nir_compiler_options options
= {0};
500 struct ac_shader_binary binary
;
501 options
.family
= chip_family
;
502 options
.chip_class
= pipeline
->device
->physical_device
->rad_info
.chip_class
;
503 options
.supports_spill
= pipeline
->device
->llvm_supports_spill
;
504 tm
= ac_create_target_machine(chip_family
, options
.supports_spill
);
505 ac_create_gs_copy_shader(tm
, nir
, &binary
, &variant
->config
, &variant
->info
, &options
, dump_shader
);
506 LLVMDisposeTargetMachine(tm
);
508 radv_fill_shader_variant(pipeline
->device
, variant
, &binary
, MESA_SHADER_VERTEX
);
511 *code_out
= binary
.code
;
512 *code_size_out
= binary
.code_size
;
517 free(binary
.global_symbol_offsets
);
519 free(binary
.disasm_string
);
520 variant
->ref_count
= 1;
524 static struct radv_shader_variant
*
525 radv_pipeline_compile(struct radv_pipeline
*pipeline
,
526 struct radv_pipeline_cache
*cache
,
527 struct radv_shader_module
*module
,
528 const char *entrypoint
,
529 gl_shader_stage stage
,
530 const VkSpecializationInfo
*spec_info
,
531 struct radv_pipeline_layout
*layout
,
532 const union ac_shader_variant_key
*key
)
534 unsigned char sha1
[20];
535 unsigned char gs_copy_sha1
[20];
536 struct radv_shader_variant
*variant
;
539 unsigned code_size
= 0;
540 bool dump
= (pipeline
->device
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
);
543 _mesa_sha1_compute(module
->nir
->info
.name
,
544 strlen(module
->nir
->info
.name
),
547 radv_hash_shader(sha1
, module
, entrypoint
, spec_info
, layout
, key
, 0);
548 if (stage
== MESA_SHADER_GEOMETRY
)
549 radv_hash_shader(gs_copy_sha1
, module
, entrypoint
, spec_info
,
552 variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
556 if (stage
== MESA_SHADER_GEOMETRY
) {
557 pipeline
->gs_copy_shader
=
558 radv_create_shader_variant_from_pipeline_cache(
565 (stage
!= MESA_SHADER_GEOMETRY
|| pipeline
->gs_copy_shader
))
568 nir
= radv_shader_compile_to_nir(pipeline
->device
,
569 module
, entrypoint
, stage
,
575 variant
= radv_shader_variant_create(pipeline
->device
, nir
,
580 if (stage
== MESA_SHADER_GEOMETRY
&& !pipeline
->gs_copy_shader
) {
581 void *gs_copy_code
= NULL
;
582 unsigned gs_copy_code_size
= 0;
583 pipeline
->gs_copy_shader
= radv_pipeline_create_gs_copy_shader(
584 pipeline
, nir
, &gs_copy_code
, &gs_copy_code_size
, dump
);
586 if (pipeline
->gs_copy_shader
) {
587 pipeline
->gs_copy_shader
=
588 radv_pipeline_cache_insert_shader(cache
,
590 pipeline
->gs_copy_shader
,
599 variant
= radv_pipeline_cache_insert_shader(cache
, sha1
, variant
,
607 static union ac_shader_variant_key
608 radv_compute_tes_key(bool as_es
)
610 union ac_shader_variant_key key
;
611 memset(&key
, 0, sizeof(key
));
612 key
.tes
.as_es
= as_es
;
616 static union ac_shader_variant_key
617 radv_compute_tcs_key(unsigned primitive_mode
, unsigned input_vertices
)
619 union ac_shader_variant_key key
;
620 memset(&key
, 0, sizeof(key
));
621 key
.tcs
.primitive_mode
= primitive_mode
;
622 key
.tcs
.input_vertices
= input_vertices
;
627 radv_tess_pipeline_compile(struct radv_pipeline
*pipeline
,
628 struct radv_pipeline_cache
*cache
,
629 struct radv_shader_module
*tcs_module
,
630 struct radv_shader_module
*tes_module
,
631 const char *tcs_entrypoint
,
632 const char *tes_entrypoint
,
633 const VkSpecializationInfo
*tcs_spec_info
,
634 const VkSpecializationInfo
*tes_spec_info
,
635 struct radv_pipeline_layout
*layout
,
636 unsigned input_vertices
)
638 unsigned char tcs_sha1
[20], tes_sha1
[20];
639 struct radv_shader_variant
*tes_variant
= NULL
, *tcs_variant
= NULL
;
640 nir_shader
*tes_nir
, *tcs_nir
;
641 void *tes_code
= NULL
, *tcs_code
= NULL
;
642 unsigned tes_code_size
= 0, tcs_code_size
= 0;
643 union ac_shader_variant_key tes_key
= radv_compute_tes_key(radv_pipeline_has_gs(pipeline
));
644 union ac_shader_variant_key tcs_key
;
645 bool dump
= (pipeline
->device
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
);
648 _mesa_sha1_compute(tes_module
->nir
->info
.name
,
649 strlen(tes_module
->nir
->info
.name
),
651 radv_hash_shader(tes_sha1
, tes_module
, tes_entrypoint
, tes_spec_info
, layout
, &tes_key
, 0);
653 tes_variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
658 tcs_key
= radv_compute_tcs_key(tes_variant
->info
.tes
.primitive_mode
, input_vertices
);
661 _mesa_sha1_compute(tcs_module
->nir
->info
.name
,
662 strlen(tcs_module
->nir
->info
.name
),
665 radv_hash_shader(tcs_sha1
, tcs_module
, tcs_entrypoint
, tcs_spec_info
, layout
, &tcs_key
, 0);
667 tcs_variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
672 if (tcs_variant
&& tes_variant
) {
673 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = tcs_variant
;
674 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] = tes_variant
;
678 tes_nir
= radv_shader_compile_to_nir(pipeline
->device
,
679 tes_module
, tes_entrypoint
, MESA_SHADER_TESS_EVAL
,
680 tes_spec_info
, dump
);
684 tcs_nir
= radv_shader_compile_to_nir(pipeline
->device
,
685 tcs_module
, tcs_entrypoint
, MESA_SHADER_TESS_CTRL
,
686 tcs_spec_info
, dump
);
690 nir_lower_tes_patch_vertices(tes_nir
,
691 tcs_nir
->info
.tess
.tcs_vertices_out
);
693 tes_variant
= radv_shader_variant_create(pipeline
->device
, tes_nir
,
694 layout
, &tes_key
, &tes_code
,
695 &tes_code_size
, dump
);
697 tcs_key
= radv_compute_tcs_key(tes_nir
->info
.tess
.primitive_mode
, input_vertices
);
699 _mesa_sha1_compute(tcs_module
->nir
->info
.name
,
700 strlen(tcs_module
->nir
->info
.name
),
703 radv_hash_shader(tcs_sha1
, tcs_module
, tcs_entrypoint
, tcs_spec_info
, layout
, &tcs_key
, 0);
705 tcs_variant
= radv_shader_variant_create(pipeline
->device
, tcs_nir
,
706 layout
, &tcs_key
, &tcs_code
,
707 &tcs_code_size
, dump
);
709 if (!tes_module
->nir
)
710 ralloc_free(tes_nir
);
712 if (!tcs_module
->nir
)
713 ralloc_free(tcs_nir
);
716 tes_variant
= radv_pipeline_cache_insert_shader(cache
, tes_sha1
, tes_variant
,
717 tes_code
, tes_code_size
);
720 tcs_variant
= radv_pipeline_cache_insert_shader(cache
, tcs_sha1
, tcs_variant
,
721 tcs_code
, tcs_code_size
);
727 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = tcs_variant
;
728 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] = tes_variant
;
733 radv_pipeline_scratch_init(struct radv_device
*device
,
734 struct radv_pipeline
*pipeline
)
736 unsigned scratch_bytes_per_wave
= 0;
737 unsigned max_waves
= 0;
738 unsigned min_waves
= 1;
740 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
741 if (pipeline
->shaders
[i
]) {
742 unsigned max_stage_waves
= device
->scratch_waves
;
744 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
745 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
747 max_stage_waves
= MIN2(max_stage_waves
,
748 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
749 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
750 max_waves
= MAX2(max_waves
, max_stage_waves
);
754 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
755 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
756 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
757 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
758 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
761 if (scratch_bytes_per_wave
)
762 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
764 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
765 /* Not really true at this moment, but will be true on first
766 * execution. Avoid having hanging shaders. */
767 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
769 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
770 pipeline
->max_waves
= max_waves
;
774 static uint32_t si_translate_blend_function(VkBlendOp op
)
777 case VK_BLEND_OP_ADD
:
778 return V_028780_COMB_DST_PLUS_SRC
;
779 case VK_BLEND_OP_SUBTRACT
:
780 return V_028780_COMB_SRC_MINUS_DST
;
781 case VK_BLEND_OP_REVERSE_SUBTRACT
:
782 return V_028780_COMB_DST_MINUS_SRC
;
783 case VK_BLEND_OP_MIN
:
784 return V_028780_COMB_MIN_DST_SRC
;
785 case VK_BLEND_OP_MAX
:
786 return V_028780_COMB_MAX_DST_SRC
;
792 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
795 case VK_BLEND_FACTOR_ZERO
:
796 return V_028780_BLEND_ZERO
;
797 case VK_BLEND_FACTOR_ONE
:
798 return V_028780_BLEND_ONE
;
799 case VK_BLEND_FACTOR_SRC_COLOR
:
800 return V_028780_BLEND_SRC_COLOR
;
801 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
802 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
803 case VK_BLEND_FACTOR_DST_COLOR
:
804 return V_028780_BLEND_DST_COLOR
;
805 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
806 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
807 case VK_BLEND_FACTOR_SRC_ALPHA
:
808 return V_028780_BLEND_SRC_ALPHA
;
809 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
810 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
811 case VK_BLEND_FACTOR_DST_ALPHA
:
812 return V_028780_BLEND_DST_ALPHA
;
813 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
814 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
815 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
816 return V_028780_BLEND_CONSTANT_COLOR
;
817 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
818 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
819 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
820 return V_028780_BLEND_CONSTANT_ALPHA
;
821 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
822 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
823 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
824 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
825 case VK_BLEND_FACTOR_SRC1_COLOR
:
826 return V_028780_BLEND_SRC1_COLOR
;
827 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
828 return V_028780_BLEND_INV_SRC1_COLOR
;
829 case VK_BLEND_FACTOR_SRC1_ALPHA
:
830 return V_028780_BLEND_SRC1_ALPHA
;
831 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
832 return V_028780_BLEND_INV_SRC1_ALPHA
;
838 static bool is_dual_src(VkBlendFactor factor
)
841 case VK_BLEND_FACTOR_SRC1_COLOR
:
842 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
843 case VK_BLEND_FACTOR_SRC1_ALPHA
:
844 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
851 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
853 bool blend_need_alpha
)
855 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
856 unsigned format
, ntype
, swap
;
858 /* Alpha is needed for alpha-to-coverage.
859 * Blending may be with or without alpha.
861 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
862 unsigned alpha
= 0; /* exports alpha, but may not support blending */
863 unsigned blend
= 0; /* supports blending, but may not export alpha */
864 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
866 format
= radv_translate_colorformat(vk_format
);
867 ntype
= radv_translate_color_numformat(vk_format
, desc
,
868 vk_format_get_first_non_void_channel(vk_format
));
869 swap
= radv_translate_colorswap(vk_format
, false);
871 /* Choose the SPI color formats. These are required values for Stoney/RB+.
872 * Other chips have multiple choices, though they are not necessarily better.
875 case V_028C70_COLOR_5_6_5
:
876 case V_028C70_COLOR_1_5_5_5
:
877 case V_028C70_COLOR_5_5_5_1
:
878 case V_028C70_COLOR_4_4_4_4
:
879 case V_028C70_COLOR_10_11_11
:
880 case V_028C70_COLOR_11_11_10
:
881 case V_028C70_COLOR_8
:
882 case V_028C70_COLOR_8_8
:
883 case V_028C70_COLOR_8_8_8_8
:
884 case V_028C70_COLOR_10_10_10_2
:
885 case V_028C70_COLOR_2_10_10_10
:
886 if (ntype
== V_028C70_NUMBER_UINT
)
887 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
888 else if (ntype
== V_028C70_NUMBER_SINT
)
889 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
891 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
894 case V_028C70_COLOR_16
:
895 case V_028C70_COLOR_16_16
:
896 case V_028C70_COLOR_16_16_16_16
:
897 if (ntype
== V_028C70_NUMBER_UNORM
||
898 ntype
== V_028C70_NUMBER_SNORM
) {
899 /* UNORM16 and SNORM16 don't support blending */
900 if (ntype
== V_028C70_NUMBER_UNORM
)
901 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
903 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
905 /* Use 32 bits per channel for blending. */
906 if (format
== V_028C70_COLOR_16
) {
907 if (swap
== V_028C70_SWAP_STD
) { /* R */
908 blend
= V_028714_SPI_SHADER_32_R
;
909 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
910 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
911 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
914 } else if (format
== V_028C70_COLOR_16_16
) {
915 if (swap
== V_028C70_SWAP_STD
) { /* RG */
916 blend
= V_028714_SPI_SHADER_32_GR
;
917 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
918 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
919 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
922 } else /* 16_16_16_16 */
923 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
924 } else if (ntype
== V_028C70_NUMBER_UINT
)
925 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
926 else if (ntype
== V_028C70_NUMBER_SINT
)
927 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
928 else if (ntype
== V_028C70_NUMBER_FLOAT
)
929 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
934 case V_028C70_COLOR_32
:
935 if (swap
== V_028C70_SWAP_STD
) { /* R */
936 blend
= normal
= V_028714_SPI_SHADER_32_R
;
937 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
938 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
939 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
944 case V_028C70_COLOR_32_32
:
945 if (swap
== V_028C70_SWAP_STD
) { /* RG */
946 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
947 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
948 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
949 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
954 case V_028C70_COLOR_32_32_32_32
:
955 case V_028C70_COLOR_8_24
:
956 case V_028C70_COLOR_24_8
:
957 case V_028C70_COLOR_X24_8_32_FLOAT
:
958 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
962 unreachable("unhandled blend format");
965 if (blend_enable
&& blend_need_alpha
)
967 else if(blend_need_alpha
)
969 else if(blend_enable
)
975 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
977 unsigned i
, cb_shader_mask
= 0;
979 for (i
= 0; i
< 8; i
++) {
980 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
981 case V_028714_SPI_SHADER_ZERO
:
983 case V_028714_SPI_SHADER_32_R
:
984 cb_shader_mask
|= 0x1 << (i
* 4);
986 case V_028714_SPI_SHADER_32_GR
:
987 cb_shader_mask
|= 0x3 << (i
* 4);
989 case V_028714_SPI_SHADER_32_AR
:
990 cb_shader_mask
|= 0x9 << (i
* 4);
992 case V_028714_SPI_SHADER_FP16_ABGR
:
993 case V_028714_SPI_SHADER_UNORM16_ABGR
:
994 case V_028714_SPI_SHADER_SNORM16_ABGR
:
995 case V_028714_SPI_SHADER_UINT16_ABGR
:
996 case V_028714_SPI_SHADER_SINT16_ABGR
:
997 case V_028714_SPI_SHADER_32_ABGR
:
998 cb_shader_mask
|= 0xf << (i
* 4);
1004 return cb_shader_mask
;
1008 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
1009 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1010 uint32_t blend_enable
,
1011 uint32_t blend_need_alpha
,
1012 bool single_cb_enable
,
1013 bool blend_mrt0_is_dual_src
)
1015 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1016 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1017 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
1018 unsigned col_format
= 0;
1020 for (unsigned i
= 0; i
< (single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
1021 struct radv_render_pass_attachment
*attachment
;
1024 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
1026 cf
= si_choose_spi_color_format(attachment
->format
,
1027 blend_enable
& (1 << i
),
1028 blend_need_alpha
& (1 << i
));
1030 col_format
|= cf
<< (4 * i
);
1033 blend
->cb_shader_mask
= si_get_cb_shader_mask(col_format
);
1035 if (blend_mrt0_is_dual_src
)
1036 col_format
|= (col_format
& 0xf) << 4;
1037 blend
->spi_shader_col_format
= col_format
;
1041 format_is_int8(VkFormat format
)
1043 const struct vk_format_description
*desc
= vk_format_description(format
);
1044 int channel
= vk_format_get_first_non_void_channel(format
);
1046 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
1047 desc
->channel
[channel
].size
== 8;
1050 unsigned radv_format_meta_fs_key(VkFormat format
)
1052 unsigned col_format
= si_choose_spi_color_format(format
, false, false) - 1;
1053 bool is_int8
= format_is_int8(format
);
1055 return col_format
+ (is_int8
? 3 : 0);
1059 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1061 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1062 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1063 unsigned is_int8
= 0;
1065 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1066 struct radv_render_pass_attachment
*attachment
;
1068 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
1070 if (format_is_int8(attachment
->format
))
1078 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
1079 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1080 const struct radv_graphics_pipeline_create_info
*extra
)
1082 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
1083 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
1084 unsigned mode
= V_028808_CB_NORMAL
;
1085 uint32_t blend_enable
= 0, blend_need_alpha
= 0;
1086 bool blend_mrt0_is_dual_src
= false;
1088 bool single_cb_enable
= false;
1093 if (extra
&& extra
->custom_blend_mode
) {
1094 single_cb_enable
= true;
1095 mode
= extra
->custom_blend_mode
;
1097 blend
->cb_color_control
= 0;
1098 if (vkblend
->logicOpEnable
)
1099 blend
->cb_color_control
|= S_028808_ROP3(vkblend
->logicOp
| (vkblend
->logicOp
<< 4));
1101 blend
->cb_color_control
|= S_028808_ROP3(0xcc);
1103 blend
->db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1104 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1105 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1106 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1108 blend
->cb_target_mask
= 0;
1109 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
1110 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
1111 unsigned blend_cntl
= 0;
1112 VkBlendOp eqRGB
= att
->colorBlendOp
;
1113 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
1114 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
1115 VkBlendOp eqA
= att
->alphaBlendOp
;
1116 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
1117 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
1119 blend
->sx_mrt0_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
1121 if (!att
->colorWriteMask
)
1124 blend
->cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
1125 if (!att
->blendEnable
) {
1126 blend
->cb_blend_control
[i
] = blend_cntl
;
1130 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
1132 blend_mrt0_is_dual_src
= true;
1134 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
1135 srcRGB
= VK_BLEND_FACTOR_ONE
;
1136 dstRGB
= VK_BLEND_FACTOR_ONE
;
1138 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
1139 srcA
= VK_BLEND_FACTOR_ONE
;
1140 dstA
= VK_BLEND_FACTOR_ONE
;
1143 blend_cntl
|= S_028780_ENABLE(1);
1145 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
1146 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
1147 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
1148 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
1149 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
1150 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
1151 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
1152 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
1154 blend
->cb_blend_control
[i
] = blend_cntl
;
1156 blend_enable
|= 1 << i
;
1158 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
1159 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
1160 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
1161 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
1162 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
1163 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
1164 blend_need_alpha
|= 1 << i
;
1166 for (i
= vkblend
->attachmentCount
; i
< 8; i
++)
1167 blend
->cb_blend_control
[i
] = 0;
1169 if (blend
->cb_target_mask
)
1170 blend
->cb_color_control
|= S_028808_MODE(mode
);
1172 blend
->cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
1174 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
,
1175 blend_enable
, blend_need_alpha
, single_cb_enable
, blend_mrt0_is_dual_src
);
1178 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
1181 case VK_STENCIL_OP_KEEP
:
1182 return V_02842C_STENCIL_KEEP
;
1183 case VK_STENCIL_OP_ZERO
:
1184 return V_02842C_STENCIL_ZERO
;
1185 case VK_STENCIL_OP_REPLACE
:
1186 return V_02842C_STENCIL_REPLACE_TEST
;
1187 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
1188 return V_02842C_STENCIL_ADD_CLAMP
;
1189 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
1190 return V_02842C_STENCIL_SUB_CLAMP
;
1191 case VK_STENCIL_OP_INVERT
:
1192 return V_02842C_STENCIL_INVERT
;
1193 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
1194 return V_02842C_STENCIL_ADD_WRAP
;
1195 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
1196 return V_02842C_STENCIL_SUB_WRAP
;
1202 radv_pipeline_init_depth_stencil_state(struct radv_pipeline
*pipeline
,
1203 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1204 const struct radv_graphics_pipeline_create_info
*extra
)
1206 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
1207 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
1209 memset(ds
, 0, sizeof(*ds
));
1212 ds
->db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
1213 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
1214 S_028800_ZFUNC(vkds
->depthCompareOp
) |
1215 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
1217 if (vkds
->stencilTestEnable
) {
1218 ds
->db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1219 ds
->db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
1220 ds
->db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
1221 ds
->db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
1222 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
1224 ds
->db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
1225 ds
->db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
1226 ds
->db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
1227 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
1232 ds
->db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
1233 ds
->db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
1235 ds
->db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
1236 ds
->db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
1237 ds
->db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
1238 ds
->db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
1239 ds
->db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
1243 static uint32_t si_translate_fill(VkPolygonMode func
)
1246 case VK_POLYGON_MODE_FILL
:
1247 return V_028814_X_DRAW_TRIANGLES
;
1248 case VK_POLYGON_MODE_LINE
:
1249 return V_028814_X_DRAW_LINES
;
1250 case VK_POLYGON_MODE_POINT
:
1251 return V_028814_X_DRAW_POINTS
;
1254 return V_028814_X_DRAW_POINTS
;
1258 radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline
,
1259 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1261 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
1262 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
1264 memset(raster
, 0, sizeof(*raster
));
1266 raster
->spi_interp_control
=
1267 S_0286D4_FLAT_SHADE_ENA(1) |
1268 S_0286D4_PNT_SPRITE_ENA(1) |
1269 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
1270 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
1271 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
1272 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
1273 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1276 raster
->pa_cl_clip_cntl
= S_028810_PS_UCP_MODE(3) |
1277 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1278 S_028810_ZCLIP_NEAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
1279 S_028810_ZCLIP_FAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
1280 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
1281 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1283 raster
->pa_su_vtx_cntl
=
1284 S_028BE4_PIX_CENTER(1) | // TODO verify
1285 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
1286 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
);
1288 raster
->pa_su_sc_mode_cntl
=
1289 S_028814_FACE(vkraster
->frontFace
) |
1290 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
1291 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
1292 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
1293 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
1294 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
1295 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
1296 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
1297 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
1302 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1303 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1305 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1306 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
1307 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1308 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1309 int ps_iter_samples
= 1;
1310 uint32_t mask
= 0xffff;
1313 ms
->num_samples
= vkms
->rasterizationSamples
;
1315 ms
->num_samples
= 1;
1317 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.force_persample
) {
1318 ps_iter_samples
= ms
->num_samples
;
1321 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1322 ms
->pa_sc_aa_config
= 0;
1323 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1324 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1325 ms
->pa_sc_mode_cntl_1
=
1326 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1327 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1329 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1330 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1331 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1332 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1333 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1334 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1335 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
);
1337 if (ms
->num_samples
> 1) {
1338 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1339 unsigned log_ps_iter_samples
= util_logbase2(util_next_power_of_two(ps_iter_samples
));
1340 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1341 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1342 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1343 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1344 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1345 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1346 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1347 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
1348 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1349 ms
->pa_sc_mode_cntl_1
|= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1353 if (vkms
->alphaToCoverageEnable
)
1354 blend
->db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1356 if (vkms
->pSampleMask
)
1357 mask
= vkms
->pSampleMask
[0] & 0xffff;
1360 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1361 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1365 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1368 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1369 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1370 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1371 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1372 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1374 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1375 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1376 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1377 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1378 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1379 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1382 unreachable("unhandled primitive type");
1387 si_translate_prim(enum VkPrimitiveTopology topology
)
1390 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1391 return V_008958_DI_PT_POINTLIST
;
1392 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1393 return V_008958_DI_PT_LINELIST
;
1394 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1395 return V_008958_DI_PT_LINESTRIP
;
1396 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1397 return V_008958_DI_PT_TRILIST
;
1398 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1399 return V_008958_DI_PT_TRISTRIP
;
1400 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1401 return V_008958_DI_PT_TRIFAN
;
1402 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1403 return V_008958_DI_PT_LINELIST_ADJ
;
1404 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1405 return V_008958_DI_PT_LINESTRIP_ADJ
;
1406 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1407 return V_008958_DI_PT_TRILIST_ADJ
;
1408 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1409 return V_008958_DI_PT_TRISTRIP_ADJ
;
1410 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1411 return V_008958_DI_PT_PATCH
;
1419 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1422 case 0: /* GL_POINTS */
1423 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1424 case 1: /* GL_LINES */
1425 case 3: /* GL_LINE_STRIP */
1426 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1427 case 0x8E7A: /* GL_ISOLINES */
1428 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1430 case 4: /* GL_TRIANGLES */
1431 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1432 case 5: /* GL_TRIANGLE_STRIP */
1433 case 7: /* GL_QUADS */
1434 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1442 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1445 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1446 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1447 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1448 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1449 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1450 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1451 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1452 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1453 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1454 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1455 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1456 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1457 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1458 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1465 static unsigned si_map_swizzle(unsigned swizzle
)
1469 return V_008F0C_SQ_SEL_Y
;
1471 return V_008F0C_SQ_SEL_Z
;
1473 return V_008F0C_SQ_SEL_W
;
1475 return V_008F0C_SQ_SEL_0
;
1477 return V_008F0C_SQ_SEL_1
;
1478 default: /* VK_SWIZZLE_X */
1479 return V_008F0C_SQ_SEL_X
;
1484 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1485 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1487 radv_cmd_dirty_mask_t states
= RADV_CMD_DIRTY_DYNAMIC_ALL
;
1488 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1489 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1491 pipeline
->dynamic_state
= default_dynamic_state
;
1493 if (pCreateInfo
->pDynamicState
) {
1494 /* Remove all of the states that are marked as dynamic */
1495 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1496 for (uint32_t s
= 0; s
< count
; s
++)
1497 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1500 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1502 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1504 * pViewportState is [...] NULL if the pipeline
1505 * has rasterization disabled.
1507 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1508 assert(pCreateInfo
->pViewportState
);
1510 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1511 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1512 typed_memcpy(dynamic
->viewport
.viewports
,
1513 pCreateInfo
->pViewportState
->pViewports
,
1514 pCreateInfo
->pViewportState
->viewportCount
);
1517 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1518 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1519 typed_memcpy(dynamic
->scissor
.scissors
,
1520 pCreateInfo
->pViewportState
->pScissors
,
1521 pCreateInfo
->pViewportState
->scissorCount
);
1525 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1526 assert(pCreateInfo
->pRasterizationState
);
1527 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1530 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1531 assert(pCreateInfo
->pRasterizationState
);
1532 dynamic
->depth_bias
.bias
=
1533 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1534 dynamic
->depth_bias
.clamp
=
1535 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1536 dynamic
->depth_bias
.slope
=
1537 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1540 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1542 * pColorBlendState is [...] NULL if the pipeline has rasterization
1543 * disabled or if the subpass of the render pass the pipeline is
1544 * created against does not use any color attachments.
1546 bool uses_color_att
= false;
1547 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1548 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1549 uses_color_att
= true;
1554 if (uses_color_att
&& states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
1555 assert(pCreateInfo
->pColorBlendState
);
1556 typed_memcpy(dynamic
->blend_constants
,
1557 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1560 /* If there is no depthstencil attachment, then don't read
1561 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1562 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1563 * no need to override the depthstencil defaults in
1564 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1566 * Section 9.2 of the Vulkan 1.0.15 spec says:
1568 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1569 * disabled or if the subpass of the render pass the pipeline is created
1570 * against does not use a depth/stencil attachment.
1572 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1573 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1574 assert(pCreateInfo
->pDepthStencilState
);
1576 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1577 dynamic
->depth_bounds
.min
=
1578 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1579 dynamic
->depth_bounds
.max
=
1580 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1583 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1584 dynamic
->stencil_compare_mask
.front
=
1585 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1586 dynamic
->stencil_compare_mask
.back
=
1587 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1590 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1591 dynamic
->stencil_write_mask
.front
=
1592 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1593 dynamic
->stencil_write_mask
.back
=
1594 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1597 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1598 dynamic
->stencil_reference
.front
=
1599 pCreateInfo
->pDepthStencilState
->front
.reference
;
1600 dynamic
->stencil_reference
.back
=
1601 pCreateInfo
->pDepthStencilState
->back
.reference
;
1605 pipeline
->dynamic_state_mask
= states
;
1608 static union ac_shader_variant_key
1609 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo
*pCreateInfo
, bool as_es
, bool as_ls
)
1611 union ac_shader_variant_key key
;
1612 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1613 pCreateInfo
->pVertexInputState
;
1615 memset(&key
, 0, sizeof(key
));
1616 key
.vs
.instance_rate_inputs
= 0;
1617 key
.vs
.as_es
= as_es
;
1618 key
.vs
.as_ls
= as_ls
;
1620 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1622 binding
= input_state
->pVertexAttributeDescriptions
[i
].binding
;
1623 if (input_state
->pVertexBindingDescriptions
[binding
].inputRate
)
1624 key
.vs
.instance_rate_inputs
|= 1u << input_state
->pVertexAttributeDescriptions
[i
].location
;
1630 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
)
1632 struct radv_device
*device
= pipeline
->device
;
1633 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1634 unsigned wave_size
= 64;
1635 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1636 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1637 unsigned alignment
= 256 * num_se
;
1638 /* The maximum size is 63.999 MB per SE. */
1639 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1640 struct ac_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1641 struct ac_es_output_info
*es_info
= radv_pipeline_has_tess(pipeline
) ?
1642 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1643 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1645 /* Calculate the minimum size. */
1646 unsigned min_esgs_ring_size
= align(es_info
->esgs_itemsize
* gs_vertex_reuse
*
1647 wave_size
, alignment
);
1648 /* These are recommended sizes, not minimum sizes. */
1649 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1650 es_info
->esgs_itemsize
* gs_info
->gs
.vertices_in
;
1651 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1652 gs_info
->gs
.max_gsvs_emit_size
* 1; // no streams in VK (gs->max_gs_stream + 1);
1654 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1655 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1656 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1658 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1659 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1662 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1665 /* SPI barrier management bug:
1666 * Make sure we have at least 4k of LDS in use to avoid the bug.
1667 * It applies to workgroup sizes of more than one wavefront.
1669 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1670 device
->physical_device
->rad_info
.family
== CHIP_KABINI
||
1671 device
->physical_device
->rad_info
.family
== CHIP_MULLINS
)
1672 *lds_size
= MAX2(*lds_size
, 8);
1676 calculate_tess_state(struct radv_pipeline
*pipeline
,
1677 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1679 unsigned num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1680 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
1681 unsigned num_tcs_patch_outputs
;
1682 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
1683 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
1684 unsigned lds_size
, hardware_lds_size
;
1685 unsigned perpatch_output_offset
;
1686 unsigned num_patches
;
1687 struct radv_tessellation_state
*tess
= &pipeline
->graphics
.tess
;
1689 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1690 * are laid out in LDS. */
1691 num_tcs_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outputs_written
);
1693 num_tcs_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
); //tcs->outputs_written
1694 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1695 num_tcs_patch_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.patch_outputs_written
);
1697 /* Ensure that we only need one wave per SIMD so we don't need to check
1698 * resource usage. Also ensures that the number of tcs in and out
1699 * vertices per threadgroup are at most 256.
1701 input_vertex_size
= num_tcs_inputs
* 16;
1702 output_vertex_size
= num_tcs_outputs
* 16;
1704 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
1706 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
1707 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
1708 /* Ensure that we only need one wave per SIMD so we don't need to check
1709 * resource usage. Also ensures that the number of tcs in and out
1710 * vertices per threadgroup are at most 256.
1712 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
1714 /* Make sure that the data fits in LDS. This assumes the shaders only
1715 * use LDS for the inputs and outputs.
1717 hardware_lds_size
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
? 65536 : 32768;
1718 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
1720 /* Make sure the output data fits in the offchip buffer */
1721 num_patches
= MIN2(num_patches
,
1722 (pipeline
->device
->tess_offchip_block_dw_size
* 4) /
1725 /* Not necessary for correctness, but improves performance. The
1726 * specific value is taken from the proprietary driver.
1728 num_patches
= MIN2(num_patches
, 40);
1730 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1731 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== SI
) {
1732 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
1733 num_patches
= MIN2(num_patches
, one_wave
);
1736 output_patch0_offset
= input_patch_size
* num_patches
;
1737 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
1739 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
1741 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1742 assert(lds_size
<= 65536);
1743 lds_size
= align(lds_size
, 512) / 512;
1745 assert(lds_size
<= 32768);
1746 lds_size
= align(lds_size
, 256) / 256;
1748 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1750 tess
->lds_size
= lds_size
;
1752 tess
->tcs_in_layout
= (input_patch_size
/ 4) |
1753 ((input_vertex_size
/ 4) << 13);
1754 tess
->tcs_out_layout
= (output_patch_size
/ 4) |
1755 ((output_vertex_size
/ 4) << 13);
1756 tess
->tcs_out_offsets
= (output_patch0_offset
/ 16) |
1757 ((perpatch_output_offset
/ 16) << 16);
1758 tess
->offchip_layout
= (pervertex_output_patch_size
* num_patches
<< 16) |
1759 (num_tcs_output_cp
<< 9) | num_patches
;
1761 tess
->ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1762 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1763 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1764 tess
->num_patches
= num_patches
;
1765 tess
->num_tcs_input_cp
= num_tcs_input_cp
;
1767 struct radv_shader_variant
*tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1768 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1770 switch (tes
->info
.tes
.primitive_mode
) {
1772 type
= V_028B6C_TESS_TRIANGLE
;
1775 type
= V_028B6C_TESS_QUAD
;
1778 type
= V_028B6C_TESS_ISOLINE
;
1782 switch (tes
->info
.tes
.spacing
) {
1783 case TESS_SPACING_EQUAL
:
1784 partitioning
= V_028B6C_PART_INTEGER
;
1786 case TESS_SPACING_FRACTIONAL_ODD
:
1787 partitioning
= V_028B6C_PART_FRAC_ODD
;
1789 case TESS_SPACING_FRACTIONAL_EVEN
:
1790 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1796 if (tes
->info
.tes
.point_mode
)
1797 topology
= V_028B6C_OUTPUT_POINT
;
1798 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1799 topology
= V_028B6C_OUTPUT_LINE
;
1800 else if (tes
->info
.tes
.ccw
)
1801 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
1803 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1805 if (pipeline
->device
->has_distributed_tess
) {
1806 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1807 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
1808 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
1810 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
1812 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
1814 tess
->tf_param
= S_028B6C_TYPE(type
) |
1815 S_028B6C_PARTITIONING(partitioning
) |
1816 S_028B6C_TOPOLOGY(topology
) |
1817 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
1820 static const struct radv_prim_vertex_count prim_size_table
[] = {
1821 [V_008958_DI_PT_NONE
] = {0, 0},
1822 [V_008958_DI_PT_POINTLIST
] = {1, 1},
1823 [V_008958_DI_PT_LINELIST
] = {2, 2},
1824 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
1825 [V_008958_DI_PT_TRILIST
] = {3, 3},
1826 [V_008958_DI_PT_TRIFAN
] = {3, 1},
1827 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
1828 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
1829 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
1830 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
1831 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
1832 [V_008958_DI_PT_RECTLIST
] = {3, 3},
1833 [V_008958_DI_PT_LINELOOP
] = {2, 1},
1834 [V_008958_DI_PT_POLYGON
] = {3, 1},
1835 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
1838 static uint32_t si_vgt_gs_mode(struct radv_shader_variant
*gs
)
1840 unsigned gs_max_vert_out
= gs
->info
.gs
.vertices_out
;
1843 if (gs_max_vert_out
<= 128) {
1844 cut_mode
= V_028A40_GS_CUT_128
;
1845 } else if (gs_max_vert_out
<= 256) {
1846 cut_mode
= V_028A40_GS_CUT_256
;
1847 } else if (gs_max_vert_out
<= 512) {
1848 cut_mode
= V_028A40_GS_CUT_512
;
1850 assert(gs_max_vert_out
<= 1024);
1851 cut_mode
= V_028A40_GS_CUT_1024
;
1854 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
1855 S_028A40_CUT_MODE(cut_mode
)|
1856 S_028A40_ES_WRITE_OPTIMIZE(1) |
1857 S_028A40_GS_WRITE_OPTIMIZE(1);
1860 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline
*pipeline
)
1862 struct radv_shader_variant
*vs
;
1863 vs
= radv_pipeline_has_gs(pipeline
) ? pipeline
->gs_copy_shader
: (radv_pipeline_has_tess(pipeline
) ? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1865 struct ac_vs_output_info
*outinfo
= &vs
->info
.vs
.outinfo
;
1867 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
1868 clip_dist_mask
= outinfo
->clip_dist_mask
;
1869 cull_dist_mask
= outinfo
->cull_dist_mask
;
1870 total_mask
= clip_dist_mask
| cull_dist_mask
;
1872 bool misc_vec_ena
= outinfo
->writes_pointsize
||
1873 outinfo
->writes_layer
||
1874 outinfo
->writes_viewport_index
;
1875 pipeline
->graphics
.pa_cl_vs_out_cntl
=
1876 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
1877 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
1878 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
1879 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1880 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
1881 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
1882 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
1883 cull_dist_mask
<< 8 |
1888 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
)
1890 uint32_t ps_input_cntl
;
1891 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
1892 ps_input_cntl
= S_028644_OFFSET(offset
);
1894 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1896 /* The input is a DEFAULT_VAL constant. */
1897 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
1898 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
1899 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
1900 ps_input_cntl
= S_028644_OFFSET(0x20) |
1901 S_028644_DEFAULT_VAL(offset
);
1903 return ps_input_cntl
;
1906 static void calculate_ps_inputs(struct radv_pipeline
*pipeline
)
1908 struct radv_shader_variant
*ps
, *vs
;
1909 struct ac_vs_output_info
*outinfo
;
1911 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1912 vs
= radv_pipeline_has_gs(pipeline
) ? pipeline
->gs_copy_shader
: (radv_pipeline_has_tess(pipeline
) ? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1914 outinfo
= &vs
->info
.vs
.outinfo
;
1916 unsigned ps_offset
= 0;
1918 if (ps
->info
.fs
.prim_id_input
) {
1919 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
1920 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
1921 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
1926 if (ps
->info
.fs
.layer_input
) {
1927 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
1928 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
1929 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
1934 if (ps
->info
.fs
.has_pcoord
) {
1936 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1937 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = val
;
1941 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
1944 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
1947 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
1948 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
1949 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
1954 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
1956 pipeline
->graphics
.ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
);
1960 pipeline
->graphics
.ps_input_cntl_num
= ps_offset
;
1964 radv_pipeline_init(struct radv_pipeline
*pipeline
,
1965 struct radv_device
*device
,
1966 struct radv_pipeline_cache
*cache
,
1967 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1968 const struct radv_graphics_pipeline_create_info
*extra
,
1969 const VkAllocationCallbacks
*alloc
)
1971 struct radv_shader_module fs_m
= {0};
1975 alloc
= &device
->alloc
;
1977 pipeline
->device
= device
;
1978 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1980 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
1981 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1982 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1983 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1984 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1985 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1986 modules
[stage
] = radv_shader_module_from_handle(pStages
[stage
]->module
);
1989 radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
1991 if (modules
[MESA_SHADER_VERTEX
]) {
1994 if (modules
[MESA_SHADER_TESS_CTRL
])
1996 else if (modules
[MESA_SHADER_GEOMETRY
])
1998 union ac_shader_variant_key key
= radv_compute_vs_key(pCreateInfo
, as_es
, as_ls
);
2000 pipeline
->shaders
[MESA_SHADER_VERTEX
] =
2001 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_VERTEX
],
2002 pStages
[MESA_SHADER_VERTEX
]->pName
,
2004 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
,
2005 pipeline
->layout
, &key
);
2007 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX
);
2010 if (modules
[MESA_SHADER_GEOMETRY
]) {
2011 union ac_shader_variant_key key
= radv_compute_vs_key(pCreateInfo
, false, false);
2013 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] =
2014 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_GEOMETRY
],
2015 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
2016 MESA_SHADER_GEOMETRY
,
2017 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
,
2018 pipeline
->layout
, &key
);
2020 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY
);
2022 pipeline
->graphics
.vgt_gs_mode
= si_vgt_gs_mode(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
2024 pipeline
->graphics
.vgt_gs_mode
= 0;
2026 if (modules
[MESA_SHADER_TESS_EVAL
]) {
2027 assert(modules
[MESA_SHADER_TESS_CTRL
]);
2029 radv_tess_pipeline_compile(pipeline
,
2031 modules
[MESA_SHADER_TESS_CTRL
],
2032 modules
[MESA_SHADER_TESS_EVAL
],
2033 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
2034 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
2035 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
2036 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
,
2038 pCreateInfo
->pTessellationState
->patchControlPoints
);
2039 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL
) |
2040 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL
);
2043 if (!modules
[MESA_SHADER_FRAGMENT
]) {
2045 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2046 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2047 fs_m
.nir
= fs_b
.shader
;
2048 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2051 if (modules
[MESA_SHADER_FRAGMENT
]) {
2052 union ac_shader_variant_key key
;
2053 key
.fs
.col_format
= pipeline
->graphics
.blend
.spi_shader_col_format
;
2054 key
.fs
.is_int8
= radv_pipeline_compute_is_int8(pCreateInfo
);
2056 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[MESA_SHADER_FRAGMENT
];
2058 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2059 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_FRAGMENT
],
2060 stage
? stage
->pName
: "main",
2061 MESA_SHADER_FRAGMENT
,
2062 stage
? stage
->pSpecializationInfo
: NULL
,
2063 pipeline
->layout
, &key
);
2064 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT
);
2068 ralloc_free(fs_m
.nir
);
2070 radv_pipeline_init_depth_stencil_state(pipeline
, pCreateInfo
, extra
);
2071 radv_pipeline_init_raster_state(pipeline
, pCreateInfo
);
2072 radv_pipeline_init_multisample_state(pipeline
, pCreateInfo
);
2073 pipeline
->graphics
.prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
2074 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
2076 if (radv_pipeline_has_gs(pipeline
)) {
2077 pipeline
->graphics
.gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
2078 pipeline
->graphics
.can_use_guardband
= pipeline
->graphics
.gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2080 pipeline
->graphics
.gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
2082 if (extra
&& extra
->use_rectlist
) {
2083 pipeline
->graphics
.prim
= V_008958_DI_PT_RECTLIST
;
2084 pipeline
->graphics
.gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2085 pipeline
->graphics
.can_use_guardband
= true;
2087 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
2088 /* prim vertex count will need TESS changes */
2089 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[pipeline
->graphics
.prim
];
2091 /* Ensure that some export memory is always allocated, for two reasons:
2093 * 1) Correctness: The hardware ignores the EXEC mask if no export
2094 * memory is allocated, so KILL and alpha test do not work correctly
2096 * 2) Performance: Every shader needs at least a NULL export, even when
2097 * it writes no color/depth output. The NULL export instruction
2098 * stalls without this setting.
2100 * Don't add this to CB_SHADER_MASK.
2102 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
2103 if (!pipeline
->graphics
.blend
.spi_shader_col_format
) {
2104 if (!ps
->info
.fs
.writes_z
&&
2105 !ps
->info
.fs
.writes_stencil
&&
2106 !ps
->info
.fs
.writes_sample_mask
)
2107 pipeline
->graphics
.blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
2111 pipeline
->graphics
.db_shader_control
= 0;
2112 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.fs
.writes_memory
)
2113 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
2115 z_order
= V_02880C_LATE_Z
;
2117 pipeline
->graphics
.db_shader_control
=
2118 S_02880C_Z_EXPORT_ENABLE(ps
->info
.fs
.writes_z
) |
2119 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.fs
.writes_stencil
) |
2120 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
2121 S_02880C_MASK_EXPORT_ENABLE(ps
->info
.fs
.writes_sample_mask
) |
2122 S_02880C_Z_ORDER(z_order
) |
2123 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
2124 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.fs
.writes_memory
) |
2125 S_02880C_EXEC_ON_NOOP(ps
->info
.fs
.writes_memory
);
2127 pipeline
->graphics
.shader_z_format
=
2128 ps
->info
.fs
.writes_sample_mask
? V_028710_SPI_SHADER_32_ABGR
:
2129 ps
->info
.fs
.writes_stencil
? V_028710_SPI_SHADER_32_GR
:
2130 ps
->info
.fs
.writes_z
? V_028710_SPI_SHADER_32_R
:
2131 V_028710_SPI_SHADER_ZERO
;
2133 calculate_pa_cl_vs_out_cntl(pipeline
);
2134 calculate_ps_inputs(pipeline
);
2136 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2137 if (pipeline
->shaders
[i
]) {
2138 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
2142 uint32_t stages
= 0;
2143 if (radv_pipeline_has_tess(pipeline
)) {
2144 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2145 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2147 if (radv_pipeline_has_gs(pipeline
))
2148 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2150 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2152 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2154 } else if (radv_pipeline_has_gs(pipeline
))
2155 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2157 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2159 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
2160 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2162 pipeline
->graphics
.vgt_shader_stages_en
= stages
;
2164 if (radv_pipeline_has_gs(pipeline
))
2165 calculate_gs_ring_sizes(pipeline
);
2167 if (radv_pipeline_has_tess(pipeline
)) {
2168 if (pipeline
->graphics
.prim
== V_008958_DI_PT_PATCH
) {
2169 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2170 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
2172 calculate_tess_state(pipeline
, pCreateInfo
);
2175 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2176 pCreateInfo
->pVertexInputState
;
2177 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
2178 const VkVertexInputAttributeDescription
*desc
=
2179 &vi_info
->pVertexAttributeDescriptions
[i
];
2180 unsigned loc
= desc
->location
;
2181 const struct vk_format_description
*format_desc
;
2183 uint32_t num_format
, data_format
;
2184 format_desc
= vk_format_description(desc
->format
);
2185 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2187 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2188 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2190 pipeline
->va_rsrc_word3
[loc
] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc
->swizzle
[0])) |
2191 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc
->swizzle
[1])) |
2192 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc
->swizzle
[2])) |
2193 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc
->swizzle
[3])) |
2194 S_008F0C_NUM_FORMAT(num_format
) |
2195 S_008F0C_DATA_FORMAT(data_format
);
2196 pipeline
->va_format_size
[loc
] = format_desc
->block
.bits
/ 8;
2197 pipeline
->va_offset
[loc
] = desc
->offset
;
2198 pipeline
->va_binding
[loc
] = desc
->binding
;
2199 pipeline
->num_vertex_attribs
= MAX2(pipeline
->num_vertex_attribs
, loc
+ 1);
2202 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
2203 const VkVertexInputBindingDescription
*desc
=
2204 &vi_info
->pVertexBindingDescriptions
[i
];
2206 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
2209 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
2210 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
2211 if (loc
->sgpr_idx
!= -1) {
2212 pipeline
->graphics
.vtx_base_sgpr
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2213 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
2214 if (pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
)
2215 pipeline
->graphics
.vtx_emit_num
= 3;
2217 pipeline
->graphics
.vtx_emit_num
= 2;
2219 if (device
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
2220 radv_dump_pipeline_stats(device
, pipeline
);
2223 result
= radv_pipeline_scratch_init(device
, pipeline
);
2228 radv_graphics_pipeline_create(
2230 VkPipelineCache _cache
,
2231 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2232 const struct radv_graphics_pipeline_create_info
*extra
,
2233 const VkAllocationCallbacks
*pAllocator
,
2234 VkPipeline
*pPipeline
)
2236 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2237 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
2238 struct radv_pipeline
*pipeline
;
2241 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2242 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2243 if (pipeline
== NULL
)
2244 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2246 memset(pipeline
, 0, sizeof(*pipeline
));
2247 result
= radv_pipeline_init(pipeline
, device
, cache
,
2248 pCreateInfo
, extra
, pAllocator
);
2249 if (result
!= VK_SUCCESS
) {
2250 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
2254 *pPipeline
= radv_pipeline_to_handle(pipeline
);
2259 VkResult
radv_CreateGraphicsPipelines(
2261 VkPipelineCache pipelineCache
,
2263 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
2264 const VkAllocationCallbacks
* pAllocator
,
2265 VkPipeline
* pPipelines
)
2267 VkResult result
= VK_SUCCESS
;
2270 for (; i
< count
; i
++) {
2272 r
= radv_graphics_pipeline_create(_device
,
2275 NULL
, pAllocator
, &pPipelines
[i
]);
2276 if (r
!= VK_SUCCESS
) {
2278 pPipelines
[i
] = VK_NULL_HANDLE
;
2285 static VkResult
radv_compute_pipeline_create(
2287 VkPipelineCache _cache
,
2288 const VkComputePipelineCreateInfo
* pCreateInfo
,
2289 const VkAllocationCallbacks
* pAllocator
,
2290 VkPipeline
* pPipeline
)
2292 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2293 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
2294 RADV_FROM_HANDLE(radv_shader_module
, module
, pCreateInfo
->stage
.module
);
2295 struct radv_pipeline
*pipeline
;
2298 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2299 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2300 if (pipeline
== NULL
)
2301 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2303 memset(pipeline
, 0, sizeof(*pipeline
));
2304 pipeline
->device
= device
;
2305 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
2307 pipeline
->shaders
[MESA_SHADER_COMPUTE
] =
2308 radv_pipeline_compile(pipeline
, cache
, module
,
2309 pCreateInfo
->stage
.pName
,
2310 MESA_SHADER_COMPUTE
,
2311 pCreateInfo
->stage
.pSpecializationInfo
,
2312 pipeline
->layout
, NULL
);
2315 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
2316 result
= radv_pipeline_scratch_init(device
, pipeline
);
2317 if (result
!= VK_SUCCESS
) {
2318 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
2322 *pPipeline
= radv_pipeline_to_handle(pipeline
);
2324 if (device
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
2325 radv_dump_pipeline_stats(device
, pipeline
);
2329 VkResult
radv_CreateComputePipelines(
2331 VkPipelineCache pipelineCache
,
2333 const VkComputePipelineCreateInfo
* pCreateInfos
,
2334 const VkAllocationCallbacks
* pAllocator
,
2335 VkPipeline
* pPipelines
)
2337 VkResult result
= VK_SUCCESS
;
2340 for (; i
< count
; i
++) {
2342 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
2344 pAllocator
, &pPipelines
[i
]);
2345 if (r
!= VK_SUCCESS
) {
2347 pPipelines
[i
] = VK_NULL_HANDLE
;