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radv: move RADV_TRACE_FILE functions to radv_debug.c
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35
36 #include <llvm-c/Core.h>
37 #include <llvm-c/TargetMachine.h>
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "r600d_common.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48
49 void radv_shader_variant_destroy(struct radv_device *device,
50 struct radv_shader_variant *variant);
51
52 static const struct nir_shader_compiler_options nir_options = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp32 = true,
56 .lower_fsat = true,
57 .lower_fdiv = true,
58 .lower_sub = true,
59 .lower_pack_snorm_2x16 = true,
60 .lower_pack_snorm_4x8 = true,
61 .lower_pack_unorm_2x16 = true,
62 .lower_pack_unorm_4x8 = true,
63 .lower_unpack_snorm_2x16 = true,
64 .lower_unpack_snorm_4x8 = true,
65 .lower_unpack_unorm_2x16 = true,
66 .lower_unpack_unorm_4x8 = true,
67 .lower_extract_byte = true,
68 .lower_extract_word = true,
69 .max_unroll_iterations = 32
70 };
71
72 VkResult radv_CreateShaderModule(
73 VkDevice _device,
74 const VkShaderModuleCreateInfo* pCreateInfo,
75 const VkAllocationCallbacks* pAllocator,
76 VkShaderModule* pShaderModule)
77 {
78 RADV_FROM_HANDLE(radv_device, device, _device);
79 struct radv_shader_module *module;
80
81 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
82 assert(pCreateInfo->flags == 0);
83
84 module = vk_alloc2(&device->alloc, pAllocator,
85 sizeof(*module) + pCreateInfo->codeSize, 8,
86 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
87 if (module == NULL)
88 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
89
90 module->nir = NULL;
91 module->size = pCreateInfo->codeSize;
92 memcpy(module->data, pCreateInfo->pCode, module->size);
93
94 _mesa_sha1_compute(module->data, module->size, module->sha1);
95
96 *pShaderModule = radv_shader_module_to_handle(module);
97
98 return VK_SUCCESS;
99 }
100
101 void radv_DestroyShaderModule(
102 VkDevice _device,
103 VkShaderModule _module,
104 const VkAllocationCallbacks* pAllocator)
105 {
106 RADV_FROM_HANDLE(radv_device, device, _device);
107 RADV_FROM_HANDLE(radv_shader_module, module, _module);
108
109 if (!module)
110 return;
111
112 vk_free2(&device->alloc, pAllocator, module);
113 }
114
115
116 static void
117 radv_pipeline_destroy(struct radv_device *device,
118 struct radv_pipeline *pipeline,
119 const VkAllocationCallbacks* allocator)
120 {
121 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
122 if (pipeline->shaders[i])
123 radv_shader_variant_destroy(device, pipeline->shaders[i]);
124
125 if (pipeline->gs_copy_shader)
126 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
127
128 vk_free2(&device->alloc, allocator, pipeline);
129 }
130
131 void radv_DestroyPipeline(
132 VkDevice _device,
133 VkPipeline _pipeline,
134 const VkAllocationCallbacks* pAllocator)
135 {
136 RADV_FROM_HANDLE(radv_device, device, _device);
137 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
138
139 if (!_pipeline)
140 return;
141
142 radv_pipeline_destroy(device, pipeline, pAllocator);
143 }
144
145
146 static void
147 radv_optimize_nir(struct nir_shader *shader)
148 {
149 bool progress;
150
151 do {
152 progress = false;
153
154 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
155 NIR_PASS_V(shader, nir_lower_64bit_pack);
156 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
157 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
158
159 NIR_PASS(progress, shader, nir_copy_prop);
160 NIR_PASS(progress, shader, nir_opt_remove_phis);
161 NIR_PASS(progress, shader, nir_opt_dce);
162 if (nir_opt_trivial_continues(shader)) {
163 progress = true;
164 NIR_PASS(progress, shader, nir_copy_prop);
165 NIR_PASS(progress, shader, nir_opt_dce);
166 }
167 NIR_PASS(progress, shader, nir_opt_if);
168 NIR_PASS(progress, shader, nir_opt_dead_cf);
169 NIR_PASS(progress, shader, nir_opt_cse);
170 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
171 NIR_PASS(progress, shader, nir_opt_algebraic);
172 NIR_PASS(progress, shader, nir_opt_constant_folding);
173 NIR_PASS(progress, shader, nir_opt_undef);
174 NIR_PASS(progress, shader, nir_opt_conditional_discard);
175 if (shader->options->max_unroll_iterations) {
176 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
177 }
178 } while (progress);
179 }
180
181 static nir_shader *
182 radv_shader_compile_to_nir(struct radv_device *device,
183 struct radv_shader_module *module,
184 const char *entrypoint_name,
185 gl_shader_stage stage,
186 const VkSpecializationInfo *spec_info,
187 bool dump)
188 {
189 if (strcmp(entrypoint_name, "main") != 0) {
190 radv_finishme("Multiple shaders per module not really supported");
191 }
192
193 nir_shader *nir;
194 nir_function *entry_point;
195 if (module->nir) {
196 /* Some things such as our meta clear/blit code will give us a NIR
197 * shader directly. In that case, we just ignore the SPIR-V entirely
198 * and just use the NIR shader */
199 nir = module->nir;
200 nir->options = &nir_options;
201 nir_validate_shader(nir);
202
203 assert(exec_list_length(&nir->functions) == 1);
204 struct exec_node *node = exec_list_get_head(&nir->functions);
205 entry_point = exec_node_data(nir_function, node, node);
206 } else {
207 uint32_t *spirv = (uint32_t *) module->data;
208 assert(module->size % 4 == 0);
209
210 uint32_t num_spec_entries = 0;
211 struct nir_spirv_specialization *spec_entries = NULL;
212 if (spec_info && spec_info->mapEntryCount > 0) {
213 num_spec_entries = spec_info->mapEntryCount;
214 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
215 for (uint32_t i = 0; i < num_spec_entries; i++) {
216 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
217 const void *data = spec_info->pData + entry.offset;
218 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
219
220 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
221 if (spec_info->dataSize == 8)
222 spec_entries[i].data64 = *(const uint64_t *)data;
223 else
224 spec_entries[i].data32 = *(const uint32_t *)data;
225 }
226 }
227 const struct nir_spirv_supported_extensions supported_ext = {
228 .draw_parameters = true,
229 .float64 = true,
230 .image_read_without_format = true,
231 .image_write_without_format = true,
232 .tessellation = true,
233 .int64 = true,
234 .multiview = true,
235 .variable_pointers = true,
236 };
237 entry_point = spirv_to_nir(spirv, module->size / 4,
238 spec_entries, num_spec_entries,
239 stage, entrypoint_name, &supported_ext, &nir_options);
240 nir = entry_point->shader;
241 assert(nir->stage == stage);
242 nir_validate_shader(nir);
243
244 free(spec_entries);
245
246 /* We have to lower away local constant initializers right before we
247 * inline functions. That way they get properly initialized at the top
248 * of the function and not at the top of its caller.
249 */
250 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
251 NIR_PASS_V(nir, nir_lower_returns);
252 NIR_PASS_V(nir, nir_inline_functions);
253
254 /* Pick off the single entrypoint that we want */
255 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
256 if (func != entry_point)
257 exec_node_remove(&func->node);
258 }
259 assert(exec_list_length(&nir->functions) == 1);
260 entry_point->name = ralloc_strdup(entry_point, "main");
261
262 NIR_PASS_V(nir, nir_remove_dead_variables,
263 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
264
265 /* Now that we've deleted all but the main function, we can go ahead and
266 * lower the rest of the constant initializers.
267 */
268 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
269 NIR_PASS_V(nir, nir_lower_system_values);
270 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
271 }
272
273 /* Vulkan uses the separate-shader linking model */
274 nir->info.separate_shader = true;
275
276 nir_shader_gather_info(nir, entry_point->impl);
277
278 nir_variable_mode indirect_mask = 0;
279 indirect_mask |= nir_var_shader_in;
280 indirect_mask |= nir_var_local;
281
282 nir_lower_indirect_derefs(nir, indirect_mask);
283
284 static const nir_lower_tex_options tex_options = {
285 .lower_txp = ~0,
286 };
287
288 nir_lower_tex(nir, &tex_options);
289
290 nir_lower_vars_to_ssa(nir);
291 nir_lower_var_copies(nir);
292 nir_lower_global_vars_to_local(nir);
293 nir_remove_dead_variables(nir, nir_var_local);
294 radv_optimize_nir(nir);
295
296 if (dump)
297 nir_print_shader(nir, stderr);
298
299 return nir;
300 }
301
302 static const char *radv_get_shader_name(struct radv_shader_variant *var,
303 gl_shader_stage stage)
304 {
305 switch (stage) {
306 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
307 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
308 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
309 case MESA_SHADER_COMPUTE: return "Compute Shader";
310 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
311 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
312 default:
313 return "Unknown shader";
314 };
315
316 }
317 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
318 {
319 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
320 struct radv_shader_variant *var;
321 struct ac_shader_config *conf;
322 int i;
323 FILE *file = stderr;
324 unsigned max_simd_waves;
325 unsigned lds_per_wave = 0;
326
327 switch (device->physical_device->rad_info.family) {
328 /* These always have 8 waves: */
329 case CHIP_POLARIS10:
330 case CHIP_POLARIS11:
331 case CHIP_POLARIS12:
332 max_simd_waves = 8;
333 break;
334 default:
335 max_simd_waves = 10;
336 }
337
338 for (i = 0; i < MESA_SHADER_STAGES; i++) {
339 if (!pipeline->shaders[i])
340 continue;
341 var = pipeline->shaders[i];
342
343 conf = &var->config;
344
345 if (i == MESA_SHADER_FRAGMENT) {
346 lds_per_wave = conf->lds_size * lds_increment +
347 align(var->info.fs.num_interp * 48, lds_increment);
348 }
349
350 if (conf->num_sgprs) {
351 if (device->physical_device->rad_info.chip_class >= VI)
352 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
353 else
354 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
355 }
356
357 if (conf->num_vgprs)
358 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
359
360 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
361 * that PS can use.
362 */
363 if (lds_per_wave)
364 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
365
366 fprintf(file, "\n%s:\n",
367 radv_get_shader_name(var, i));
368 if (i == MESA_SHADER_FRAGMENT) {
369 fprintf(file, "*** SHADER CONFIG ***\n"
370 "SPI_PS_INPUT_ADDR = 0x%04x\n"
371 "SPI_PS_INPUT_ENA = 0x%04x\n",
372 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
373 }
374 fprintf(file, "*** SHADER STATS ***\n"
375 "SGPRS: %d\n"
376 "VGPRS: %d\n"
377 "Spilled SGPRs: %d\n"
378 "Spilled VGPRs: %d\n"
379 "Code Size: %d bytes\n"
380 "LDS: %d blocks\n"
381 "Scratch: %d bytes per wave\n"
382 "Max Waves: %d\n"
383 "********************\n\n\n",
384 conf->num_sgprs, conf->num_vgprs,
385 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
386 conf->lds_size, conf->scratch_bytes_per_wave,
387 max_simd_waves);
388 }
389 }
390
391 void radv_shader_variant_destroy(struct radv_device *device,
392 struct radv_shader_variant *variant)
393 {
394 if (!p_atomic_dec_zero(&variant->ref_count))
395 return;
396
397 mtx_lock(&device->shader_slab_mutex);
398 list_del(&variant->slab_list);
399 mtx_unlock(&device->shader_slab_mutex);
400
401 free(variant);
402 }
403
404 static void radv_fill_shader_variant(struct radv_device *device,
405 struct radv_shader_variant *variant,
406 struct ac_shader_binary *binary,
407 gl_shader_stage stage)
408 {
409 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
410 unsigned vgpr_comp_cnt = 0;
411
412 if (scratch_enabled && !device->llvm_supports_spill)
413 radv_finishme("shader scratch support only available with LLVM 4.0");
414
415 variant->code_size = binary->code_size;
416 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
417 S_00B12C_SCRATCH_EN(scratch_enabled);
418
419 switch (stage) {
420 case MESA_SHADER_TESS_EVAL:
421 vgpr_comp_cnt = 3;
422 /* fallthrough */
423 case MESA_SHADER_TESS_CTRL:
424 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
425 break;
426 case MESA_SHADER_VERTEX:
427 case MESA_SHADER_GEOMETRY:
428 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
429 break;
430 case MESA_SHADER_FRAGMENT:
431 break;
432 case MESA_SHADER_COMPUTE:
433 variant->rsrc2 |=
434 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
435 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
436 S_00B84C_TG_SIZE_EN(1) |
437 S_00B84C_LDS_SIZE(variant->config.lds_size);
438 break;
439 default:
440 unreachable("unsupported shader type");
441 break;
442 }
443
444 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
445 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
446 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
447 S_00B848_DX10_CLAMP(1) |
448 S_00B848_FLOAT_MODE(variant->config.float_mode);
449
450 void *ptr = radv_alloc_shader_memory(device, variant);
451 memcpy(ptr, binary->code, binary->code_size);
452 }
453
454 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
455 struct nir_shader *shader,
456 struct radv_pipeline_layout *layout,
457 const struct ac_shader_variant_key *key,
458 void** code_out,
459 unsigned *code_size_out,
460 bool dump)
461 {
462 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
463 enum radeon_family chip_family = device->physical_device->rad_info.family;
464 LLVMTargetMachineRef tm;
465 if (!variant)
466 return NULL;
467
468 struct ac_nir_compiler_options options = {0};
469 options.layout = layout;
470 if (key)
471 options.key = *key;
472
473 struct ac_shader_binary binary;
474 enum ac_target_machine_options tm_options = 0;
475 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
476 options.family = chip_family;
477 options.chip_class = device->physical_device->rad_info.chip_class;
478 options.supports_spill = device->llvm_supports_spill;
479 if (options.supports_spill)
480 tm_options |= AC_TM_SUPPORTS_SPILL;
481 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
482 tm_options |= AC_TM_SISCHED;
483 tm = ac_create_target_machine(chip_family, tm_options);
484 ac_compile_nir_shader(tm, &binary, &variant->config,
485 &variant->info, shader, &options, dump);
486 LLVMDisposeTargetMachine(tm);
487
488 radv_fill_shader_variant(device, variant, &binary, shader->stage);
489
490 if (code_out) {
491 *code_out = binary.code;
492 *code_size_out = binary.code_size;
493 } else
494 free(binary.code);
495 free(binary.config);
496 free(binary.rodata);
497 free(binary.global_symbol_offsets);
498 free(binary.relocs);
499 free(binary.disasm_string);
500 variant->ref_count = 1;
501 return variant;
502 }
503
504 static struct radv_shader_variant *
505 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
506 struct nir_shader *nir,
507 void** code_out,
508 unsigned *code_size_out,
509 bool dump_shader,
510 bool multiview)
511 {
512 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
513 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
514 LLVMTargetMachineRef tm;
515 if (!variant)
516 return NULL;
517
518 struct ac_nir_compiler_options options = {0};
519 struct ac_shader_binary binary;
520 enum ac_target_machine_options tm_options = 0;
521 options.family = chip_family;
522 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
523 options.key.has_multiview_view_index = multiview;
524 if (options.supports_spill)
525 tm_options |= AC_TM_SUPPORTS_SPILL;
526 if (pipeline->device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
527 tm_options |= AC_TM_SISCHED;
528 tm = ac_create_target_machine(chip_family, tm_options);
529 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
530 LLVMDisposeTargetMachine(tm);
531
532 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
533
534 if (code_out) {
535 *code_out = binary.code;
536 *code_size_out = binary.code_size;
537 } else
538 free(binary.code);
539 free(binary.config);
540 free(binary.rodata);
541 free(binary.global_symbol_offsets);
542 free(binary.relocs);
543 free(binary.disasm_string);
544 variant->ref_count = 1;
545 return variant;
546 }
547
548 static struct radv_shader_variant *
549 radv_pipeline_compile(struct radv_pipeline *pipeline,
550 struct radv_pipeline_cache *cache,
551 struct radv_shader_module *module,
552 const char *entrypoint,
553 gl_shader_stage stage,
554 const VkSpecializationInfo *spec_info,
555 struct radv_pipeline_layout *layout,
556 const struct ac_shader_variant_key *key)
557 {
558 unsigned char sha1[20];
559 unsigned char gs_copy_sha1[20];
560 struct radv_shader_variant *variant;
561 nir_shader *nir;
562 void *code = NULL;
563 unsigned code_size = 0;
564 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
565
566 if (module->nir)
567 _mesa_sha1_compute(module->nir->info.name,
568 strlen(module->nir->info.name),
569 module->sha1);
570
571 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
572 if (stage == MESA_SHADER_GEOMETRY)
573 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
574 layout, key, 1);
575
576 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
577 cache,
578 sha1);
579
580 if (stage == MESA_SHADER_GEOMETRY) {
581 pipeline->gs_copy_shader =
582 radv_create_shader_variant_from_pipeline_cache(
583 pipeline->device,
584 cache,
585 gs_copy_sha1);
586 }
587
588 if (variant &&
589 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
590 return variant;
591
592 nir = radv_shader_compile_to_nir(pipeline->device,
593 module, entrypoint, stage,
594 spec_info, dump);
595 if (nir == NULL)
596 return NULL;
597
598 if (!variant) {
599 variant = radv_shader_variant_create(pipeline->device, nir,
600 layout, key, &code,
601 &code_size, dump);
602 }
603
604 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
605 void *gs_copy_code = NULL;
606 unsigned gs_copy_code_size = 0;
607 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
608 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump, key->has_multiview_view_index);
609
610 if (pipeline->gs_copy_shader) {
611 pipeline->gs_copy_shader =
612 radv_pipeline_cache_insert_shader(cache,
613 gs_copy_sha1,
614 pipeline->gs_copy_shader,
615 gs_copy_code,
616 gs_copy_code_size);
617 }
618 }
619 if (!module->nir)
620 ralloc_free(nir);
621
622 if (variant)
623 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
624 code, code_size);
625
626 if (code)
627 free(code);
628 return variant;
629 }
630
631 static struct ac_shader_variant_key
632 radv_compute_tes_key(bool as_es, bool export_prim_id)
633 {
634 struct ac_shader_variant_key key;
635 memset(&key, 0, sizeof(key));
636 key.tes.as_es = as_es;
637 /* export prim id only happens when no geom shader */
638 if (!as_es)
639 key.tes.export_prim_id = export_prim_id;
640 return key;
641 }
642
643 static struct ac_shader_variant_key
644 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
645 {
646 struct ac_shader_variant_key key;
647 memset(&key, 0, sizeof(key));
648 key.tcs.primitive_mode = primitive_mode;
649 key.tcs.input_vertices = input_vertices;
650 return key;
651 }
652
653 static void
654 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
655 struct radv_pipeline_cache *cache,
656 struct radv_shader_module *tcs_module,
657 struct radv_shader_module *tes_module,
658 const char *tcs_entrypoint,
659 const char *tes_entrypoint,
660 const VkSpecializationInfo *tcs_spec_info,
661 const VkSpecializationInfo *tes_spec_info,
662 struct radv_pipeline_layout *layout,
663 unsigned input_vertices,
664 bool has_view_index)
665 {
666 unsigned char tcs_sha1[20], tes_sha1[20];
667 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
668 nir_shader *tes_nir, *tcs_nir;
669 void *tes_code = NULL, *tcs_code = NULL;
670 unsigned tes_code_size = 0, tcs_code_size = 0;
671 struct ac_shader_variant_key tes_key;
672 struct ac_shader_variant_key tcs_key;
673 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
674
675 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
676 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
677 tes_key.has_multiview_view_index = has_view_index;
678 if (tes_module->nir)
679 _mesa_sha1_compute(tes_module->nir->info.name,
680 strlen(tes_module->nir->info.name),
681 tes_module->sha1);
682 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
683
684 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
685 cache,
686 tes_sha1);
687
688 if (tes_variant) {
689 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
690
691 if (tcs_module->nir)
692 _mesa_sha1_compute(tcs_module->nir->info.name,
693 strlen(tcs_module->nir->info.name),
694 tcs_module->sha1);
695
696 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
697
698 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
699 cache,
700 tcs_sha1);
701 }
702
703 if (tcs_variant && tes_variant) {
704 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
705 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
706 return;
707 }
708
709 tes_nir = radv_shader_compile_to_nir(pipeline->device,
710 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
711 tes_spec_info, dump);
712 if (tes_nir == NULL)
713 return;
714
715 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
716 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
717 tcs_spec_info, dump);
718 if (tcs_nir == NULL)
719 return;
720
721 nir_lower_tes_patch_vertices(tes_nir,
722 tcs_nir->info.tess.tcs_vertices_out);
723
724 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
725 layout, &tes_key, &tes_code,
726 &tes_code_size, dump);
727
728 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
729 if (tcs_module->nir)
730 _mesa_sha1_compute(tcs_module->nir->info.name,
731 strlen(tcs_module->nir->info.name),
732 tcs_module->sha1);
733
734 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
735
736 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
737 layout, &tcs_key, &tcs_code,
738 &tcs_code_size, dump);
739
740 if (!tes_module->nir)
741 ralloc_free(tes_nir);
742
743 if (!tcs_module->nir)
744 ralloc_free(tcs_nir);
745
746 if (tes_variant)
747 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
748 tes_code, tes_code_size);
749
750 if (tcs_variant)
751 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
752 tcs_code, tcs_code_size);
753
754 if (tes_code)
755 free(tes_code);
756 if (tcs_code)
757 free(tcs_code);
758 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
759 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
760 return;
761 }
762
763 static VkResult
764 radv_pipeline_scratch_init(struct radv_device *device,
765 struct radv_pipeline *pipeline)
766 {
767 unsigned scratch_bytes_per_wave = 0;
768 unsigned max_waves = 0;
769 unsigned min_waves = 1;
770
771 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
772 if (pipeline->shaders[i]) {
773 unsigned max_stage_waves = device->scratch_waves;
774
775 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
776 pipeline->shaders[i]->config.scratch_bytes_per_wave);
777
778 max_stage_waves = MIN2(max_stage_waves,
779 4 * device->physical_device->rad_info.num_good_compute_units *
780 (256 / pipeline->shaders[i]->config.num_vgprs));
781 max_waves = MAX2(max_waves, max_stage_waves);
782 }
783 }
784
785 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
786 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
787 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
788 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
789 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
790 }
791
792 if (scratch_bytes_per_wave)
793 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
794
795 if (scratch_bytes_per_wave && max_waves < min_waves) {
796 /* Not really true at this moment, but will be true on first
797 * execution. Avoid having hanging shaders. */
798 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
799 }
800 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
801 pipeline->max_waves = max_waves;
802 return VK_SUCCESS;
803 }
804
805 static uint32_t si_translate_blend_function(VkBlendOp op)
806 {
807 switch (op) {
808 case VK_BLEND_OP_ADD:
809 return V_028780_COMB_DST_PLUS_SRC;
810 case VK_BLEND_OP_SUBTRACT:
811 return V_028780_COMB_SRC_MINUS_DST;
812 case VK_BLEND_OP_REVERSE_SUBTRACT:
813 return V_028780_COMB_DST_MINUS_SRC;
814 case VK_BLEND_OP_MIN:
815 return V_028780_COMB_MIN_DST_SRC;
816 case VK_BLEND_OP_MAX:
817 return V_028780_COMB_MAX_DST_SRC;
818 default:
819 return 0;
820 }
821 }
822
823 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
824 {
825 switch (factor) {
826 case VK_BLEND_FACTOR_ZERO:
827 return V_028780_BLEND_ZERO;
828 case VK_BLEND_FACTOR_ONE:
829 return V_028780_BLEND_ONE;
830 case VK_BLEND_FACTOR_SRC_COLOR:
831 return V_028780_BLEND_SRC_COLOR;
832 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
833 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
834 case VK_BLEND_FACTOR_DST_COLOR:
835 return V_028780_BLEND_DST_COLOR;
836 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
837 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
838 case VK_BLEND_FACTOR_SRC_ALPHA:
839 return V_028780_BLEND_SRC_ALPHA;
840 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
841 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
842 case VK_BLEND_FACTOR_DST_ALPHA:
843 return V_028780_BLEND_DST_ALPHA;
844 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
845 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
846 case VK_BLEND_FACTOR_CONSTANT_COLOR:
847 return V_028780_BLEND_CONSTANT_COLOR;
848 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
849 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
850 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
851 return V_028780_BLEND_CONSTANT_ALPHA;
852 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
853 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
854 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
855 return V_028780_BLEND_SRC_ALPHA_SATURATE;
856 case VK_BLEND_FACTOR_SRC1_COLOR:
857 return V_028780_BLEND_SRC1_COLOR;
858 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
859 return V_028780_BLEND_INV_SRC1_COLOR;
860 case VK_BLEND_FACTOR_SRC1_ALPHA:
861 return V_028780_BLEND_SRC1_ALPHA;
862 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
863 return V_028780_BLEND_INV_SRC1_ALPHA;
864 default:
865 return 0;
866 }
867 }
868
869 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
870 {
871 switch (op) {
872 case VK_BLEND_OP_ADD:
873 return V_028760_OPT_COMB_ADD;
874 case VK_BLEND_OP_SUBTRACT:
875 return V_028760_OPT_COMB_SUBTRACT;
876 case VK_BLEND_OP_REVERSE_SUBTRACT:
877 return V_028760_OPT_COMB_REVSUBTRACT;
878 case VK_BLEND_OP_MIN:
879 return V_028760_OPT_COMB_MIN;
880 case VK_BLEND_OP_MAX:
881 return V_028760_OPT_COMB_MAX;
882 default:
883 return V_028760_OPT_COMB_BLEND_DISABLED;
884 }
885 }
886
887 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
888 {
889 switch (factor) {
890 case VK_BLEND_FACTOR_ZERO:
891 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
892 case VK_BLEND_FACTOR_ONE:
893 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
894 case VK_BLEND_FACTOR_SRC_COLOR:
895 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
896 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
897 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
898 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
899 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
900 case VK_BLEND_FACTOR_SRC_ALPHA:
901 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
902 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
903 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
904 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
905 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
906 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
907 default:
908 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
909 }
910 }
911
912 /**
913 * Get rid of DST in the blend factors by commuting the operands:
914 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
915 */
916 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
917 unsigned *dst_factor, unsigned expected_dst,
918 unsigned replacement_src)
919 {
920 if (*src_factor == expected_dst &&
921 *dst_factor == VK_BLEND_FACTOR_ZERO) {
922 *src_factor = VK_BLEND_FACTOR_ZERO;
923 *dst_factor = replacement_src;
924
925 /* Commuting the operands requires reversing subtractions. */
926 if (*func == VK_BLEND_OP_SUBTRACT)
927 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
928 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
929 *func = VK_BLEND_OP_SUBTRACT;
930 }
931 }
932
933 static bool si_blend_factor_uses_dst(unsigned factor)
934 {
935 return factor == VK_BLEND_FACTOR_DST_COLOR ||
936 factor == VK_BLEND_FACTOR_DST_ALPHA ||
937 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
938 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
939 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
940 }
941
942 static bool is_dual_src(VkBlendFactor factor)
943 {
944 switch (factor) {
945 case VK_BLEND_FACTOR_SRC1_COLOR:
946 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
947 case VK_BLEND_FACTOR_SRC1_ALPHA:
948 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
949 return true;
950 default:
951 return false;
952 }
953 }
954
955 static unsigned si_choose_spi_color_format(VkFormat vk_format,
956 bool blend_enable,
957 bool blend_need_alpha)
958 {
959 const struct vk_format_description *desc = vk_format_description(vk_format);
960 unsigned format, ntype, swap;
961
962 /* Alpha is needed for alpha-to-coverage.
963 * Blending may be with or without alpha.
964 */
965 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
966 unsigned alpha = 0; /* exports alpha, but may not support blending */
967 unsigned blend = 0; /* supports blending, but may not export alpha */
968 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
969
970 format = radv_translate_colorformat(vk_format);
971 ntype = radv_translate_color_numformat(vk_format, desc,
972 vk_format_get_first_non_void_channel(vk_format));
973 swap = radv_translate_colorswap(vk_format, false);
974
975 /* Choose the SPI color formats. These are required values for Stoney/RB+.
976 * Other chips have multiple choices, though they are not necessarily better.
977 */
978 switch (format) {
979 case V_028C70_COLOR_5_6_5:
980 case V_028C70_COLOR_1_5_5_5:
981 case V_028C70_COLOR_5_5_5_1:
982 case V_028C70_COLOR_4_4_4_4:
983 case V_028C70_COLOR_10_11_11:
984 case V_028C70_COLOR_11_11_10:
985 case V_028C70_COLOR_8:
986 case V_028C70_COLOR_8_8:
987 case V_028C70_COLOR_8_8_8_8:
988 case V_028C70_COLOR_10_10_10_2:
989 case V_028C70_COLOR_2_10_10_10:
990 if (ntype == V_028C70_NUMBER_UINT)
991 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
992 else if (ntype == V_028C70_NUMBER_SINT)
993 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
994 else
995 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
996 break;
997
998 case V_028C70_COLOR_16:
999 case V_028C70_COLOR_16_16:
1000 case V_028C70_COLOR_16_16_16_16:
1001 if (ntype == V_028C70_NUMBER_UNORM ||
1002 ntype == V_028C70_NUMBER_SNORM) {
1003 /* UNORM16 and SNORM16 don't support blending */
1004 if (ntype == V_028C70_NUMBER_UNORM)
1005 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1006 else
1007 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1008
1009 /* Use 32 bits per channel for blending. */
1010 if (format == V_028C70_COLOR_16) {
1011 if (swap == V_028C70_SWAP_STD) { /* R */
1012 blend = V_028714_SPI_SHADER_32_R;
1013 blend_alpha = V_028714_SPI_SHADER_32_AR;
1014 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1015 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1016 else
1017 assert(0);
1018 } else if (format == V_028C70_COLOR_16_16) {
1019 if (swap == V_028C70_SWAP_STD) { /* RG */
1020 blend = V_028714_SPI_SHADER_32_GR;
1021 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1022 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1023 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1024 else
1025 assert(0);
1026 } else /* 16_16_16_16 */
1027 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1028 } else if (ntype == V_028C70_NUMBER_UINT)
1029 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1030 else if (ntype == V_028C70_NUMBER_SINT)
1031 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1032 else if (ntype == V_028C70_NUMBER_FLOAT)
1033 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1034 else
1035 assert(0);
1036 break;
1037
1038 case V_028C70_COLOR_32:
1039 if (swap == V_028C70_SWAP_STD) { /* R */
1040 blend = normal = V_028714_SPI_SHADER_32_R;
1041 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1042 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1043 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1044 else
1045 assert(0);
1046 break;
1047
1048 case V_028C70_COLOR_32_32:
1049 if (swap == V_028C70_SWAP_STD) { /* RG */
1050 blend = normal = V_028714_SPI_SHADER_32_GR;
1051 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1052 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1053 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1054 else
1055 assert(0);
1056 break;
1057
1058 case V_028C70_COLOR_32_32_32_32:
1059 case V_028C70_COLOR_8_24:
1060 case V_028C70_COLOR_24_8:
1061 case V_028C70_COLOR_X24_8_32_FLOAT:
1062 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1063 break;
1064
1065 default:
1066 unreachable("unhandled blend format");
1067 }
1068
1069 if (blend_enable && blend_need_alpha)
1070 return blend_alpha;
1071 else if(blend_need_alpha)
1072 return alpha;
1073 else if(blend_enable)
1074 return blend;
1075 else
1076 return normal;
1077 }
1078
1079 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
1080 {
1081 unsigned i, cb_shader_mask = 0;
1082
1083 for (i = 0; i < 8; i++) {
1084 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
1085 case V_028714_SPI_SHADER_ZERO:
1086 break;
1087 case V_028714_SPI_SHADER_32_R:
1088 cb_shader_mask |= 0x1 << (i * 4);
1089 break;
1090 case V_028714_SPI_SHADER_32_GR:
1091 cb_shader_mask |= 0x3 << (i * 4);
1092 break;
1093 case V_028714_SPI_SHADER_32_AR:
1094 cb_shader_mask |= 0x9 << (i * 4);
1095 break;
1096 case V_028714_SPI_SHADER_FP16_ABGR:
1097 case V_028714_SPI_SHADER_UNORM16_ABGR:
1098 case V_028714_SPI_SHADER_SNORM16_ABGR:
1099 case V_028714_SPI_SHADER_UINT16_ABGR:
1100 case V_028714_SPI_SHADER_SINT16_ABGR:
1101 case V_028714_SPI_SHADER_32_ABGR:
1102 cb_shader_mask |= 0xf << (i * 4);
1103 break;
1104 default:
1105 assert(0);
1106 }
1107 }
1108 return cb_shader_mask;
1109 }
1110
1111 static void
1112 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1113 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1114 uint32_t blend_enable,
1115 uint32_t blend_need_alpha,
1116 bool single_cb_enable,
1117 bool blend_mrt0_is_dual_src)
1118 {
1119 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1120 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1121 struct radv_blend_state *blend = &pipeline->graphics.blend;
1122 unsigned col_format = 0;
1123
1124 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1125 unsigned cf;
1126
1127 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1128 cf = V_028714_SPI_SHADER_ZERO;
1129 } else {
1130 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
1131
1132 cf = si_choose_spi_color_format(attachment->format,
1133 blend_enable & (1 << i),
1134 blend_need_alpha & (1 << i));
1135 }
1136
1137 col_format |= cf << (4 * i);
1138 }
1139
1140 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1141
1142 if (blend_mrt0_is_dual_src)
1143 col_format |= (col_format & 0xf) << 4;
1144 blend->spi_shader_col_format = col_format;
1145 }
1146
1147 static bool
1148 format_is_int8(VkFormat format)
1149 {
1150 const struct vk_format_description *desc = vk_format_description(format);
1151 int channel = vk_format_get_first_non_void_channel(format);
1152
1153 return channel >= 0 && desc->channel[channel].pure_integer &&
1154 desc->channel[channel].size == 8;
1155 }
1156
1157 static bool
1158 format_is_int10(VkFormat format)
1159 {
1160 const struct vk_format_description *desc = vk_format_description(format);
1161
1162 if (desc->nr_channels != 4)
1163 return false;
1164 for (unsigned i = 0; i < 4; i++) {
1165 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
1166 return true;
1167 }
1168 return false;
1169 }
1170
1171 unsigned radv_format_meta_fs_key(VkFormat format)
1172 {
1173 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1174 bool is_int8 = format_is_int8(format);
1175 bool is_int10 = format_is_int10(format);
1176
1177 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
1178 }
1179
1180 static void
1181 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1182 unsigned *is_int8, unsigned *is_int10)
1183 {
1184 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1185 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1186 *is_int8 = 0;
1187 *is_int10 = 0;
1188
1189 for (unsigned i = 0; i < subpass->color_count; ++i) {
1190 struct radv_render_pass_attachment *attachment;
1191
1192 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
1193 continue;
1194
1195 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1196
1197 if (format_is_int8(attachment->format))
1198 *is_int8 |= 1 << i;
1199 if (format_is_int10(attachment->format))
1200 *is_int10 |= 1 << i;
1201 }
1202 }
1203
1204 static void
1205 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1206 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1207 const struct radv_graphics_pipeline_create_info *extra)
1208 {
1209 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1210 struct radv_blend_state *blend = &pipeline->graphics.blend;
1211 unsigned mode = V_028808_CB_NORMAL;
1212 uint32_t blend_enable = 0, blend_need_alpha = 0;
1213 bool blend_mrt0_is_dual_src = false;
1214 int i;
1215 bool single_cb_enable = false;
1216
1217 if (!vkblend)
1218 return;
1219
1220 if (extra && extra->custom_blend_mode) {
1221 single_cb_enable = true;
1222 mode = extra->custom_blend_mode;
1223 }
1224 blend->cb_color_control = 0;
1225 if (vkblend->logicOpEnable)
1226 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1227 else
1228 blend->cb_color_control |= S_028808_ROP3(0xcc);
1229
1230 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1231 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1232 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1233 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1234
1235 blend->cb_target_mask = 0;
1236 for (i = 0; i < vkblend->attachmentCount; i++) {
1237 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1238 unsigned blend_cntl = 0;
1239 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
1240 VkBlendOp eqRGB = att->colorBlendOp;
1241 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1242 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1243 VkBlendOp eqA = att->alphaBlendOp;
1244 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1245 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1246
1247 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1248
1249 if (!att->colorWriteMask)
1250 continue;
1251
1252 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1253 if (!att->blendEnable) {
1254 blend->cb_blend_control[i] = blend_cntl;
1255 continue;
1256 }
1257
1258 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1259 if (i == 0)
1260 blend_mrt0_is_dual_src = true;
1261
1262 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1263 srcRGB = VK_BLEND_FACTOR_ONE;
1264 dstRGB = VK_BLEND_FACTOR_ONE;
1265 }
1266 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1267 srcA = VK_BLEND_FACTOR_ONE;
1268 dstA = VK_BLEND_FACTOR_ONE;
1269 }
1270
1271 /* Blending optimizations for RB+.
1272 * These transformations don't change the behavior.
1273 *
1274 * First, get rid of DST in the blend factors:
1275 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
1276 */
1277 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
1278 VK_BLEND_FACTOR_DST_COLOR,
1279 VK_BLEND_FACTOR_SRC_COLOR);
1280
1281 si_blend_remove_dst(&eqA, &srcA, &dstA,
1282 VK_BLEND_FACTOR_DST_COLOR,
1283 VK_BLEND_FACTOR_SRC_COLOR);
1284
1285 si_blend_remove_dst(&eqA, &srcA, &dstA,
1286 VK_BLEND_FACTOR_DST_ALPHA,
1287 VK_BLEND_FACTOR_SRC_ALPHA);
1288
1289 /* Look up the ideal settings from tables. */
1290 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
1291 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
1292 srcA_opt = si_translate_blend_opt_factor(srcA, true);
1293 dstA_opt = si_translate_blend_opt_factor(dstA, true);
1294
1295 /* Handle interdependencies. */
1296 if (si_blend_factor_uses_dst(srcRGB))
1297 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1298 if (si_blend_factor_uses_dst(srcA))
1299 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1300
1301 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
1302 (dstRGB == VK_BLEND_FACTOR_ZERO ||
1303 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1304 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
1305 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
1306
1307 /* Set the final value. */
1308 blend->sx_mrt_blend_opt[i] =
1309 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
1310 S_028760_COLOR_DST_OPT(dstRGB_opt) |
1311 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
1312 S_028760_ALPHA_SRC_OPT(srcA_opt) |
1313 S_028760_ALPHA_DST_OPT(dstA_opt) |
1314 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
1315 blend_cntl |= S_028780_ENABLE(1);
1316
1317 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1318 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1319 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1320 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1321 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1322 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1323 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1324 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1325 }
1326 blend->cb_blend_control[i] = blend_cntl;
1327
1328 blend_enable |= 1 << i;
1329
1330 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1331 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1332 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1333 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1334 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1335 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1336 blend_need_alpha |= 1 << i;
1337 }
1338 for (i = vkblend->attachmentCount; i < 8; i++) {
1339 blend->cb_blend_control[i] = 0;
1340 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1341 }
1342
1343 /* disable RB+ for now */
1344 if (pipeline->device->physical_device->has_rbplus)
1345 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
1346
1347 if (blend->cb_target_mask)
1348 blend->cb_color_control |= S_028808_MODE(mode);
1349 else
1350 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1351
1352 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1353 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1354 }
1355
1356 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1357 {
1358 switch (op) {
1359 case VK_STENCIL_OP_KEEP:
1360 return V_02842C_STENCIL_KEEP;
1361 case VK_STENCIL_OP_ZERO:
1362 return V_02842C_STENCIL_ZERO;
1363 case VK_STENCIL_OP_REPLACE:
1364 return V_02842C_STENCIL_REPLACE_TEST;
1365 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1366 return V_02842C_STENCIL_ADD_CLAMP;
1367 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1368 return V_02842C_STENCIL_SUB_CLAMP;
1369 case VK_STENCIL_OP_INVERT:
1370 return V_02842C_STENCIL_INVERT;
1371 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1372 return V_02842C_STENCIL_ADD_WRAP;
1373 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1374 return V_02842C_STENCIL_SUB_WRAP;
1375 default:
1376 return 0;
1377 }
1378 }
1379 static void
1380 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1381 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1382 const struct radv_graphics_pipeline_create_info *extra)
1383 {
1384 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1385 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1386
1387 memset(ds, 0, sizeof(*ds));
1388 if (!vkds)
1389 return;
1390
1391 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1392 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1393 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1394 return;
1395
1396 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
1397 bool has_depth_attachment = vk_format_is_depth(attachment->format);
1398 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
1399
1400 if (has_depth_attachment) {
1401 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1402 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1403 S_028800_ZFUNC(vkds->depthCompareOp) |
1404 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1405 }
1406
1407 if (has_stencil_attachment && vkds->stencilTestEnable) {
1408 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1409 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1410 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1411 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1412 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1413
1414 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1415 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1416 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1417 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1418 }
1419
1420 if (extra) {
1421
1422 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1423 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1424
1425 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1426 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1427 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1428 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1429 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1430 }
1431 }
1432
1433 static uint32_t si_translate_fill(VkPolygonMode func)
1434 {
1435 switch(func) {
1436 case VK_POLYGON_MODE_FILL:
1437 return V_028814_X_DRAW_TRIANGLES;
1438 case VK_POLYGON_MODE_LINE:
1439 return V_028814_X_DRAW_LINES;
1440 case VK_POLYGON_MODE_POINT:
1441 return V_028814_X_DRAW_POINTS;
1442 default:
1443 assert(0);
1444 return V_028814_X_DRAW_POINTS;
1445 }
1446 }
1447 static void
1448 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1449 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1450 {
1451 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1452 struct radv_raster_state *raster = &pipeline->graphics.raster;
1453
1454 memset(raster, 0, sizeof(*raster));
1455
1456 raster->spi_interp_control =
1457 S_0286D4_FLAT_SHADE_ENA(1) |
1458 S_0286D4_PNT_SPRITE_ENA(1) |
1459 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1460 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1461 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1462 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1463 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1464
1465
1466 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1467 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1468 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1469 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1470 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1471 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1472
1473 raster->pa_su_vtx_cntl =
1474 S_028BE4_PIX_CENTER(1) | // TODO verify
1475 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1476 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1477
1478 raster->pa_su_sc_mode_cntl =
1479 S_028814_FACE(vkraster->frontFace) |
1480 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1481 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1482 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1483 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1484 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1485 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1486 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1487 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1488
1489 }
1490
1491 static void
1492 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1493 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1494 {
1495 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1496 struct radv_blend_state *blend = &pipeline->graphics.blend;
1497 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1498 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1499 int ps_iter_samples = 1;
1500 uint32_t mask = 0xffff;
1501
1502 if (vkms)
1503 ms->num_samples = vkms->rasterizationSamples;
1504 else
1505 ms->num_samples = 1;
1506
1507 if (vkms && vkms->sampleShadingEnable) {
1508 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1509 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1510 ps_iter_samples = ms->num_samples;
1511 }
1512
1513 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1514 ms->pa_sc_aa_config = 0;
1515 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1516 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1517 ms->pa_sc_mode_cntl_1 =
1518 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1519 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1520 /* always 1: */
1521 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1522 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1523 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1524 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1525 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1526 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1527 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1528
1529 if (ms->num_samples > 1) {
1530 unsigned log_samples = util_logbase2(ms->num_samples);
1531 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1532 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1533 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1534 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1535 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1536 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1537 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1538 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1539 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1540 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1541 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1542 }
1543
1544 if (vkms) {
1545 if (vkms->alphaToCoverageEnable)
1546 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1547
1548 if (vkms->pSampleMask)
1549 mask = vkms->pSampleMask[0] & 0xffff;
1550 }
1551
1552 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1553 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1554 }
1555
1556 static bool
1557 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1558 {
1559 switch (topology) {
1560 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1561 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1562 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1563 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1564 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1565 return false;
1566 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1567 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1568 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1569 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1570 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1571 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1572 return true;
1573 default:
1574 unreachable("unhandled primitive type");
1575 }
1576 }
1577
1578 static uint32_t
1579 si_translate_prim(enum VkPrimitiveTopology topology)
1580 {
1581 switch (topology) {
1582 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1583 return V_008958_DI_PT_POINTLIST;
1584 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1585 return V_008958_DI_PT_LINELIST;
1586 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1587 return V_008958_DI_PT_LINESTRIP;
1588 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1589 return V_008958_DI_PT_TRILIST;
1590 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1591 return V_008958_DI_PT_TRISTRIP;
1592 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1593 return V_008958_DI_PT_TRIFAN;
1594 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1595 return V_008958_DI_PT_LINELIST_ADJ;
1596 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1597 return V_008958_DI_PT_LINESTRIP_ADJ;
1598 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1599 return V_008958_DI_PT_TRILIST_ADJ;
1600 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1601 return V_008958_DI_PT_TRISTRIP_ADJ;
1602 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1603 return V_008958_DI_PT_PATCH;
1604 default:
1605 assert(0);
1606 return 0;
1607 }
1608 }
1609
1610 static uint32_t
1611 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1612 {
1613 switch (gl_prim) {
1614 case 0: /* GL_POINTS */
1615 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1616 case 1: /* GL_LINES */
1617 case 3: /* GL_LINE_STRIP */
1618 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1619 case 0x8E7A: /* GL_ISOLINES */
1620 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1621
1622 case 4: /* GL_TRIANGLES */
1623 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1624 case 5: /* GL_TRIANGLE_STRIP */
1625 case 7: /* GL_QUADS */
1626 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1627 default:
1628 assert(0);
1629 return 0;
1630 }
1631 }
1632
1633 static uint32_t
1634 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1635 {
1636 switch (topology) {
1637 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1638 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1639 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1640 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1641 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1642 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1643 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1644 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1645 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1646 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1647 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1648 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1649 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1650 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1651 default:
1652 assert(0);
1653 return 0;
1654 }
1655 }
1656
1657 static unsigned si_map_swizzle(unsigned swizzle)
1658 {
1659 switch (swizzle) {
1660 case VK_SWIZZLE_Y:
1661 return V_008F0C_SQ_SEL_Y;
1662 case VK_SWIZZLE_Z:
1663 return V_008F0C_SQ_SEL_Z;
1664 case VK_SWIZZLE_W:
1665 return V_008F0C_SQ_SEL_W;
1666 case VK_SWIZZLE_0:
1667 return V_008F0C_SQ_SEL_0;
1668 case VK_SWIZZLE_1:
1669 return V_008F0C_SQ_SEL_1;
1670 default: /* VK_SWIZZLE_X */
1671 return V_008F0C_SQ_SEL_X;
1672 }
1673 }
1674
1675 static void
1676 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1677 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1678 {
1679 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1680 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1681 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1682
1683 pipeline->dynamic_state = default_dynamic_state;
1684
1685 if (pCreateInfo->pDynamicState) {
1686 /* Remove all of the states that are marked as dynamic */
1687 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1688 for (uint32_t s = 0; s < count; s++)
1689 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1690 }
1691
1692 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1693
1694 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1695 *
1696 * pViewportState is [...] NULL if the pipeline
1697 * has rasterization disabled.
1698 */
1699 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1700 assert(pCreateInfo->pViewportState);
1701
1702 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1703 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1704 typed_memcpy(dynamic->viewport.viewports,
1705 pCreateInfo->pViewportState->pViewports,
1706 pCreateInfo->pViewportState->viewportCount);
1707 }
1708
1709 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1710 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1711 typed_memcpy(dynamic->scissor.scissors,
1712 pCreateInfo->pViewportState->pScissors,
1713 pCreateInfo->pViewportState->scissorCount);
1714 }
1715 }
1716
1717 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1718 assert(pCreateInfo->pRasterizationState);
1719 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1720 }
1721
1722 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1723 assert(pCreateInfo->pRasterizationState);
1724 dynamic->depth_bias.bias =
1725 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1726 dynamic->depth_bias.clamp =
1727 pCreateInfo->pRasterizationState->depthBiasClamp;
1728 dynamic->depth_bias.slope =
1729 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1730 }
1731
1732 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1733 *
1734 * pColorBlendState is [...] NULL if the pipeline has rasterization
1735 * disabled or if the subpass of the render pass the pipeline is
1736 * created against does not use any color attachments.
1737 */
1738 bool uses_color_att = false;
1739 for (unsigned i = 0; i < subpass->color_count; ++i) {
1740 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1741 uses_color_att = true;
1742 break;
1743 }
1744 }
1745
1746 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1747 assert(pCreateInfo->pColorBlendState);
1748 typed_memcpy(dynamic->blend_constants,
1749 pCreateInfo->pColorBlendState->blendConstants, 4);
1750 }
1751
1752 /* If there is no depthstencil attachment, then don't read
1753 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1754 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1755 * no need to override the depthstencil defaults in
1756 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1757 *
1758 * Section 9.2 of the Vulkan 1.0.15 spec says:
1759 *
1760 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1761 * disabled or if the subpass of the render pass the pipeline is created
1762 * against does not use a depth/stencil attachment.
1763 */
1764 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1765 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1766 assert(pCreateInfo->pDepthStencilState);
1767
1768 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1769 dynamic->depth_bounds.min =
1770 pCreateInfo->pDepthStencilState->minDepthBounds;
1771 dynamic->depth_bounds.max =
1772 pCreateInfo->pDepthStencilState->maxDepthBounds;
1773 }
1774
1775 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1776 dynamic->stencil_compare_mask.front =
1777 pCreateInfo->pDepthStencilState->front.compareMask;
1778 dynamic->stencil_compare_mask.back =
1779 pCreateInfo->pDepthStencilState->back.compareMask;
1780 }
1781
1782 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1783 dynamic->stencil_write_mask.front =
1784 pCreateInfo->pDepthStencilState->front.writeMask;
1785 dynamic->stencil_write_mask.back =
1786 pCreateInfo->pDepthStencilState->back.writeMask;
1787 }
1788
1789 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1790 dynamic->stencil_reference.front =
1791 pCreateInfo->pDepthStencilState->front.reference;
1792 dynamic->stencil_reference.back =
1793 pCreateInfo->pDepthStencilState->back.reference;
1794 }
1795 }
1796
1797 pipeline->dynamic_state_mask = states;
1798 }
1799
1800 static struct ac_shader_variant_key
1801 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1802 {
1803 struct ac_shader_variant_key key;
1804 const VkPipelineVertexInputStateCreateInfo *input_state =
1805 pCreateInfo->pVertexInputState;
1806
1807 memset(&key, 0, sizeof(key));
1808 key.vs.instance_rate_inputs = 0;
1809 key.vs.as_es = as_es;
1810 key.vs.as_ls = as_ls;
1811 key.vs.export_prim_id = export_prim_id;
1812
1813 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1814 unsigned binding;
1815 binding = input_state->pVertexAttributeDescriptions[i].binding;
1816 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1817 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1818 }
1819 return key;
1820 }
1821
1822 static void
1823 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1824 {
1825 struct radv_device *device = pipeline->device;
1826 unsigned num_se = device->physical_device->rad_info.max_se;
1827 unsigned wave_size = 64;
1828 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1829 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1830 unsigned alignment = 256 * num_se;
1831 /* The maximum size is 63.999 MB per SE. */
1832 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1833 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1834 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1835 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1836 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1837
1838 /* Calculate the minimum size. */
1839 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1840 wave_size, alignment);
1841 /* These are recommended sizes, not minimum sizes. */
1842 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1843 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1844 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1845 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1846
1847 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1848 esgs_ring_size = align(esgs_ring_size, alignment);
1849 gsvs_ring_size = align(gsvs_ring_size, alignment);
1850
1851 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1852 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1853 }
1854
1855 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1856 unsigned *lds_size)
1857 {
1858 /* SPI barrier management bug:
1859 * Make sure we have at least 4k of LDS in use to avoid the bug.
1860 * It applies to workgroup sizes of more than one wavefront.
1861 */
1862 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1863 device->physical_device->rad_info.family == CHIP_KABINI ||
1864 device->physical_device->rad_info.family == CHIP_MULLINS)
1865 *lds_size = MAX2(*lds_size, 8);
1866 }
1867
1868 static void
1869 calculate_tess_state(struct radv_pipeline *pipeline,
1870 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1871 {
1872 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1873 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1874 unsigned num_tcs_patch_outputs;
1875 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1876 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1877 unsigned lds_size, hardware_lds_size;
1878 unsigned perpatch_output_offset;
1879 unsigned num_patches;
1880 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1881
1882 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1883 * are laid out in LDS. */
1884 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1885
1886 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1887 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1888 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1889
1890 /* Ensure that we only need one wave per SIMD so we don't need to check
1891 * resource usage. Also ensures that the number of tcs in and out
1892 * vertices per threadgroup are at most 256.
1893 */
1894 input_vertex_size = num_tcs_inputs * 16;
1895 output_vertex_size = num_tcs_outputs * 16;
1896
1897 input_patch_size = num_tcs_input_cp * input_vertex_size;
1898
1899 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1900 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1901 /* Ensure that we only need one wave per SIMD so we don't need to check
1902 * resource usage. Also ensures that the number of tcs in and out
1903 * vertices per threadgroup are at most 256.
1904 */
1905 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1906
1907 /* Make sure that the data fits in LDS. This assumes the shaders only
1908 * use LDS for the inputs and outputs.
1909 */
1910 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1911 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1912
1913 /* Make sure the output data fits in the offchip buffer */
1914 num_patches = MIN2(num_patches,
1915 (pipeline->device->tess_offchip_block_dw_size * 4) /
1916 output_patch_size);
1917
1918 /* Not necessary for correctness, but improves performance. The
1919 * specific value is taken from the proprietary driver.
1920 */
1921 num_patches = MIN2(num_patches, 40);
1922
1923 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1924 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1925 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1926 num_patches = MIN2(num_patches, one_wave);
1927 }
1928
1929 output_patch0_offset = input_patch_size * num_patches;
1930 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1931
1932 lds_size = output_patch0_offset + output_patch_size * num_patches;
1933
1934 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1935 assert(lds_size <= 65536);
1936 lds_size = align(lds_size, 512) / 512;
1937 } else {
1938 assert(lds_size <= 32768);
1939 lds_size = align(lds_size, 256) / 256;
1940 }
1941 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1942
1943 tess->lds_size = lds_size;
1944
1945 tess->tcs_in_layout = (input_patch_size / 4) |
1946 ((input_vertex_size / 4) << 13);
1947 tess->tcs_out_layout = (output_patch_size / 4) |
1948 ((output_vertex_size / 4) << 13);
1949 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1950 ((perpatch_output_offset / 16) << 16);
1951 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1952 (num_tcs_output_cp << 9) | num_patches;
1953
1954 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1955 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1956 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1957 tess->num_patches = num_patches;
1958 tess->num_tcs_input_cp = num_tcs_input_cp;
1959
1960 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1961 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1962
1963 switch (tes->info.tes.primitive_mode) {
1964 case GL_TRIANGLES:
1965 type = V_028B6C_TESS_TRIANGLE;
1966 break;
1967 case GL_QUADS:
1968 type = V_028B6C_TESS_QUAD;
1969 break;
1970 case GL_ISOLINES:
1971 type = V_028B6C_TESS_ISOLINE;
1972 break;
1973 }
1974
1975 switch (tes->info.tes.spacing) {
1976 case TESS_SPACING_EQUAL:
1977 partitioning = V_028B6C_PART_INTEGER;
1978 break;
1979 case TESS_SPACING_FRACTIONAL_ODD:
1980 partitioning = V_028B6C_PART_FRAC_ODD;
1981 break;
1982 case TESS_SPACING_FRACTIONAL_EVEN:
1983 partitioning = V_028B6C_PART_FRAC_EVEN;
1984 break;
1985 default:
1986 break;
1987 }
1988
1989 if (tes->info.tes.point_mode)
1990 topology = V_028B6C_OUTPUT_POINT;
1991 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1992 topology = V_028B6C_OUTPUT_LINE;
1993 else if (tes->info.tes.ccw)
1994 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1995 else
1996 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1997
1998 if (pipeline->device->has_distributed_tess) {
1999 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2000 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2001 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2002 else
2003 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2004 } else
2005 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2006
2007 tess->tf_param = S_028B6C_TYPE(type) |
2008 S_028B6C_PARTITIONING(partitioning) |
2009 S_028B6C_TOPOLOGY(topology) |
2010 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2011 }
2012
2013 static const struct radv_prim_vertex_count prim_size_table[] = {
2014 [V_008958_DI_PT_NONE] = {0, 0},
2015 [V_008958_DI_PT_POINTLIST] = {1, 1},
2016 [V_008958_DI_PT_LINELIST] = {2, 2},
2017 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2018 [V_008958_DI_PT_TRILIST] = {3, 3},
2019 [V_008958_DI_PT_TRIFAN] = {3, 1},
2020 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2021 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2022 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2023 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2024 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2025 [V_008958_DI_PT_RECTLIST] = {3, 3},
2026 [V_008958_DI_PT_LINELOOP] = {2, 1},
2027 [V_008958_DI_PT_POLYGON] = {3, 1},
2028 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2029 };
2030
2031 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
2032 {
2033 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
2034 unsigned cut_mode;
2035
2036 if (gs_max_vert_out <= 128) {
2037 cut_mode = V_028A40_GS_CUT_128;
2038 } else if (gs_max_vert_out <= 256) {
2039 cut_mode = V_028A40_GS_CUT_256;
2040 } else if (gs_max_vert_out <= 512) {
2041 cut_mode = V_028A40_GS_CUT_512;
2042 } else {
2043 assert(gs_max_vert_out <= 1024);
2044 cut_mode = V_028A40_GS_CUT_1024;
2045 }
2046
2047 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2048 S_028A40_CUT_MODE(cut_mode)|
2049 S_028A40_ES_WRITE_OPTIMIZE(1) |
2050 S_028A40_GS_WRITE_OPTIMIZE(1);
2051 }
2052
2053 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
2054 {
2055 struct radv_shader_variant *vs;
2056 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2057
2058 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2059
2060 pipeline->graphics.vgt_primitiveid_en = false;
2061 pipeline->graphics.vgt_gs_mode = 0;
2062
2063 if (radv_pipeline_has_gs(pipeline)) {
2064 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2065 } else if (outinfo->export_prim_id) {
2066 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2067 pipeline->graphics.vgt_primitiveid_en = true;
2068 }
2069 }
2070
2071 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
2072 {
2073 struct radv_shader_variant *vs;
2074 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2075
2076 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2077
2078 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2079 clip_dist_mask = outinfo->clip_dist_mask;
2080 cull_dist_mask = outinfo->cull_dist_mask;
2081 total_mask = clip_dist_mask | cull_dist_mask;
2082
2083 bool misc_vec_ena = outinfo->writes_pointsize ||
2084 outinfo->writes_layer ||
2085 outinfo->writes_viewport_index;
2086 pipeline->graphics.pa_cl_vs_out_cntl =
2087 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2088 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2089 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2090 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2091 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2092 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2093 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2094 cull_dist_mask << 8 |
2095 clip_dist_mask;
2096
2097 }
2098
2099 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2100 {
2101 uint32_t ps_input_cntl;
2102 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2103 ps_input_cntl = S_028644_OFFSET(offset);
2104 if (flat_shade)
2105 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2106 } else {
2107 /* The input is a DEFAULT_VAL constant. */
2108 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2109 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2110 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2111 ps_input_cntl = S_028644_OFFSET(0x20) |
2112 S_028644_DEFAULT_VAL(offset);
2113 }
2114 return ps_input_cntl;
2115 }
2116
2117 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
2118 {
2119 struct radv_shader_variant *ps, *vs;
2120 struct ac_vs_output_info *outinfo;
2121
2122 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2123 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2124
2125 outinfo = &vs->info.vs.outinfo;
2126
2127 unsigned ps_offset = 0;
2128
2129 if (ps->info.fs.prim_id_input) {
2130 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2131 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2132 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2133 ++ps_offset;
2134 }
2135 }
2136
2137 if (ps->info.fs.layer_input) {
2138 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2139 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2140 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2141 else
2142 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2143 ++ps_offset;
2144 }
2145
2146 if (ps->info.fs.has_pcoord) {
2147 unsigned val;
2148 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2149 pipeline->graphics.ps_input_cntl[ps_offset] = val;
2150 ps_offset++;
2151 }
2152
2153 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2154 unsigned vs_offset;
2155 bool flat_shade;
2156 if (!(ps->info.fs.input_mask & (1u << i)))
2157 continue;
2158
2159 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2160 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2161 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2162 ++ps_offset;
2163 continue;
2164 }
2165
2166 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2167
2168 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2169 ++ps_offset;
2170 }
2171
2172 pipeline->graphics.ps_input_cntl_num = ps_offset;
2173 }
2174
2175 VkResult
2176 radv_pipeline_init(struct radv_pipeline *pipeline,
2177 struct radv_device *device,
2178 struct radv_pipeline_cache *cache,
2179 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2180 const struct radv_graphics_pipeline_create_info *extra,
2181 const VkAllocationCallbacks *alloc)
2182 {
2183 struct radv_shader_module fs_m = {0};
2184 VkResult result;
2185 bool has_view_index = false;
2186
2187 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2188 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2189 if (subpass->view_mask)
2190 has_view_index = true;
2191 if (alloc == NULL)
2192 alloc = &device->alloc;
2193
2194 pipeline->device = device;
2195 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2196
2197 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2198 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2199 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2200 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2201 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2202 pStages[stage] = &pCreateInfo->pStages[i];
2203 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2204 }
2205
2206 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2207
2208 if (!modules[MESA_SHADER_FRAGMENT]) {
2209 nir_builder fs_b;
2210 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2211 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2212 fs_m.nir = fs_b.shader;
2213 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2214 }
2215
2216 if (modules[MESA_SHADER_FRAGMENT]) {
2217 struct ac_shader_variant_key key = {0};
2218 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2219 if (pCreateInfo->pMultisampleState &&
2220 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
2221 key.fs.multisample = true;
2222
2223 if (pipeline->device->physical_device->rad_info.chip_class < VI)
2224 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
2225
2226 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2227
2228 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2229 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2230 stage ? stage->pName : "main",
2231 MESA_SHADER_FRAGMENT,
2232 stage ? stage->pSpecializationInfo : NULL,
2233 pipeline->layout, &key);
2234 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2235 }
2236
2237 if (fs_m.nir)
2238 ralloc_free(fs_m.nir);
2239
2240 if (modules[MESA_SHADER_VERTEX]) {
2241 bool as_es = false;
2242 bool as_ls = false;
2243 bool export_prim_id = false;
2244 if (modules[MESA_SHADER_TESS_CTRL])
2245 as_ls = true;
2246 else if (modules[MESA_SHADER_GEOMETRY])
2247 as_es = true;
2248 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2249 export_prim_id = true;
2250 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2251 key.has_multiview_view_index = has_view_index;
2252
2253 pipeline->shaders[MESA_SHADER_VERTEX] =
2254 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2255 pStages[MESA_SHADER_VERTEX]->pName,
2256 MESA_SHADER_VERTEX,
2257 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2258 pipeline->layout, &key);
2259
2260 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2261 }
2262
2263 if (modules[MESA_SHADER_GEOMETRY]) {
2264 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2265 key.has_multiview_view_index = has_view_index;
2266
2267 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2268 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2269 pStages[MESA_SHADER_GEOMETRY]->pName,
2270 MESA_SHADER_GEOMETRY,
2271 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2272 pipeline->layout, &key);
2273
2274 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2275 }
2276
2277 if (modules[MESA_SHADER_TESS_EVAL]) {
2278 assert(modules[MESA_SHADER_TESS_CTRL]);
2279
2280 radv_tess_pipeline_compile(pipeline,
2281 cache,
2282 modules[MESA_SHADER_TESS_CTRL],
2283 modules[MESA_SHADER_TESS_EVAL],
2284 pStages[MESA_SHADER_TESS_CTRL]->pName,
2285 pStages[MESA_SHADER_TESS_EVAL]->pName,
2286 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2287 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2288 pipeline->layout,
2289 pCreateInfo->pTessellationState->patchControlPoints,
2290 has_view_index);
2291 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2292 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2293 }
2294
2295 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2296 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2297 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2298 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2299 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2300
2301 if (radv_pipeline_has_gs(pipeline)) {
2302 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2303 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2304 } else {
2305 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2306 }
2307 if (extra && extra->use_rectlist) {
2308 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2309 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2310 pipeline->graphics.can_use_guardband = true;
2311 }
2312 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2313 /* prim vertex count will need TESS changes */
2314 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2315
2316 /* Ensure that some export memory is always allocated, for two reasons:
2317 *
2318 * 1) Correctness: The hardware ignores the EXEC mask if no export
2319 * memory is allocated, so KILL and alpha test do not work correctly
2320 * without this.
2321 * 2) Performance: Every shader needs at least a NULL export, even when
2322 * it writes no color/depth output. The NULL export instruction
2323 * stalls without this setting.
2324 *
2325 * Don't add this to CB_SHADER_MASK.
2326 */
2327 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2328 if (!pipeline->graphics.blend.spi_shader_col_format) {
2329 if (!ps->info.fs.writes_z &&
2330 !ps->info.fs.writes_stencil &&
2331 !ps->info.fs.writes_sample_mask)
2332 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2333 }
2334
2335 unsigned z_order;
2336 pipeline->graphics.db_shader_control = 0;
2337 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2338 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2339 else
2340 z_order = V_02880C_LATE_Z;
2341
2342 pipeline->graphics.db_shader_control =
2343 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2344 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2345 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2346 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2347 S_02880C_Z_ORDER(z_order) |
2348 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2349 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2350 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2351
2352 if (pipeline->device->physical_device->has_rbplus)
2353 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2354
2355 pipeline->graphics.shader_z_format =
2356 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2357 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2358 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2359 V_028710_SPI_SHADER_ZERO;
2360
2361 calculate_vgt_gs_mode(pipeline);
2362 calculate_pa_cl_vs_out_cntl(pipeline);
2363 calculate_ps_inputs(pipeline);
2364
2365 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2366 if (pipeline->shaders[i]) {
2367 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2368 }
2369 }
2370
2371 uint32_t stages = 0;
2372 if (radv_pipeline_has_tess(pipeline)) {
2373 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2374 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2375
2376 if (radv_pipeline_has_gs(pipeline))
2377 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2378 S_028B54_GS_EN(1) |
2379 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2380 else
2381 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2382
2383 } else if (radv_pipeline_has_gs(pipeline))
2384 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2385 S_028B54_GS_EN(1) |
2386 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2387
2388 if (device->physical_device->rad_info.chip_class >= GFX9)
2389 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2390
2391 pipeline->graphics.vgt_shader_stages_en = stages;
2392
2393 if (radv_pipeline_has_gs(pipeline))
2394 calculate_gs_ring_sizes(pipeline);
2395
2396 if (radv_pipeline_has_tess(pipeline)) {
2397 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2398 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2399 pipeline->graphics.prim_vertex_count.incr = 1;
2400 }
2401 calculate_tess_state(pipeline, pCreateInfo);
2402 }
2403
2404 const VkPipelineVertexInputStateCreateInfo *vi_info =
2405 pCreateInfo->pVertexInputState;
2406 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2407 const VkVertexInputAttributeDescription *desc =
2408 &vi_info->pVertexAttributeDescriptions[i];
2409 unsigned loc = desc->location;
2410 const struct vk_format_description *format_desc;
2411 int first_non_void;
2412 uint32_t num_format, data_format;
2413 format_desc = vk_format_description(desc->format);
2414 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2415
2416 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2417 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2418
2419 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2420 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2421 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2422 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2423 S_008F0C_NUM_FORMAT(num_format) |
2424 S_008F0C_DATA_FORMAT(data_format);
2425 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2426 pipeline->va_offset[loc] = desc->offset;
2427 pipeline->va_binding[loc] = desc->binding;
2428 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2429 }
2430
2431 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2432 const VkVertexInputBindingDescription *desc =
2433 &vi_info->pVertexBindingDescriptions[i];
2434
2435 pipeline->binding_stride[desc->binding] = desc->stride;
2436 }
2437
2438 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2439 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2440 if (loc->sgpr_idx != -1) {
2441 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2442 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2443 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2444 pipeline->graphics.vtx_emit_num = 3;
2445 else
2446 pipeline->graphics.vtx_emit_num = 2;
2447 }
2448 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2449 radv_dump_pipeline_stats(device, pipeline);
2450 }
2451
2452 result = radv_pipeline_scratch_init(device, pipeline);
2453 return result;
2454 }
2455
2456 VkResult
2457 radv_graphics_pipeline_create(
2458 VkDevice _device,
2459 VkPipelineCache _cache,
2460 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2461 const struct radv_graphics_pipeline_create_info *extra,
2462 const VkAllocationCallbacks *pAllocator,
2463 VkPipeline *pPipeline)
2464 {
2465 RADV_FROM_HANDLE(radv_device, device, _device);
2466 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2467 struct radv_pipeline *pipeline;
2468 VkResult result;
2469
2470 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2471 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2472 if (pipeline == NULL)
2473 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2474
2475 memset(pipeline, 0, sizeof(*pipeline));
2476 result = radv_pipeline_init(pipeline, device, cache,
2477 pCreateInfo, extra, pAllocator);
2478 if (result != VK_SUCCESS) {
2479 radv_pipeline_destroy(device, pipeline, pAllocator);
2480 return result;
2481 }
2482
2483 *pPipeline = radv_pipeline_to_handle(pipeline);
2484
2485 return VK_SUCCESS;
2486 }
2487
2488 VkResult radv_CreateGraphicsPipelines(
2489 VkDevice _device,
2490 VkPipelineCache pipelineCache,
2491 uint32_t count,
2492 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2493 const VkAllocationCallbacks* pAllocator,
2494 VkPipeline* pPipelines)
2495 {
2496 VkResult result = VK_SUCCESS;
2497 unsigned i = 0;
2498
2499 for (; i < count; i++) {
2500 VkResult r;
2501 r = radv_graphics_pipeline_create(_device,
2502 pipelineCache,
2503 &pCreateInfos[i],
2504 NULL, pAllocator, &pPipelines[i]);
2505 if (r != VK_SUCCESS) {
2506 result = r;
2507 pPipelines[i] = VK_NULL_HANDLE;
2508 }
2509 }
2510
2511 return result;
2512 }
2513
2514 static VkResult radv_compute_pipeline_create(
2515 VkDevice _device,
2516 VkPipelineCache _cache,
2517 const VkComputePipelineCreateInfo* pCreateInfo,
2518 const VkAllocationCallbacks* pAllocator,
2519 VkPipeline* pPipeline)
2520 {
2521 RADV_FROM_HANDLE(radv_device, device, _device);
2522 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2523 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2524 struct radv_pipeline *pipeline;
2525 VkResult result;
2526
2527 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2528 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2529 if (pipeline == NULL)
2530 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2531
2532 memset(pipeline, 0, sizeof(*pipeline));
2533 pipeline->device = device;
2534 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2535
2536 pipeline->shaders[MESA_SHADER_COMPUTE] =
2537 radv_pipeline_compile(pipeline, cache, module,
2538 pCreateInfo->stage.pName,
2539 MESA_SHADER_COMPUTE,
2540 pCreateInfo->stage.pSpecializationInfo,
2541 pipeline->layout, NULL);
2542
2543
2544 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2545 result = radv_pipeline_scratch_init(device, pipeline);
2546 if (result != VK_SUCCESS) {
2547 radv_pipeline_destroy(device, pipeline, pAllocator);
2548 return result;
2549 }
2550
2551 *pPipeline = radv_pipeline_to_handle(pipeline);
2552
2553 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2554 radv_dump_pipeline_stats(device, pipeline);
2555 }
2556 return VK_SUCCESS;
2557 }
2558 VkResult radv_CreateComputePipelines(
2559 VkDevice _device,
2560 VkPipelineCache pipelineCache,
2561 uint32_t count,
2562 const VkComputePipelineCreateInfo* pCreateInfos,
2563 const VkAllocationCallbacks* pAllocator,
2564 VkPipeline* pPipelines)
2565 {
2566 VkResult result = VK_SUCCESS;
2567
2568 unsigned i = 0;
2569 for (; i < count; i++) {
2570 VkResult r;
2571 r = radv_compute_pipeline_create(_device, pipelineCache,
2572 &pCreateInfos[i],
2573 pAllocator, &pPipelines[i]);
2574 if (r != VK_SUCCESS) {
2575 result = r;
2576 pPipelines[i] = VK_NULL_HANDLE;
2577 }
2578 }
2579
2580 return result;
2581 }
2582
2583 void *radv_alloc_shader_memory(struct radv_device *device,
2584 struct radv_shader_variant *shader)
2585 {
2586 mtx_lock(&device->shader_slab_mutex);
2587 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2588 uint64_t offset = 0;
2589 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
2590 if (s->bo_offset - offset >= shader->code_size) {
2591 shader->bo = slab->bo;
2592 shader->bo_offset = offset;
2593 list_addtail(&shader->slab_list, &s->slab_list);
2594 mtx_unlock(&device->shader_slab_mutex);
2595 return slab->ptr + offset;
2596 }
2597 offset = align_u64(s->bo_offset + s->code_size, 256);
2598 }
2599 if (slab->size - offset >= shader->code_size) {
2600 shader->bo = slab->bo;
2601 shader->bo_offset = offset;
2602 list_addtail(&shader->slab_list, &slab->shaders);
2603 mtx_unlock(&device->shader_slab_mutex);
2604 return slab->ptr + offset;
2605 }
2606 }
2607
2608 mtx_unlock(&device->shader_slab_mutex);
2609 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
2610
2611 slab->size = 256 * 1024;
2612 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
2613 RADEON_DOMAIN_VRAM, 0);
2614 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
2615 list_inithead(&slab->shaders);
2616
2617 mtx_lock(&device->shader_slab_mutex);
2618 list_add(&slab->slabs, &device->shader_slabs);
2619
2620 shader->bo = slab->bo;
2621 shader->bo_offset = 0;
2622 list_add(&shader->slab_list, &slab->shaders);
2623 mtx_unlock(&device->shader_slab_mutex);
2624 return slab->ptr;
2625 }
2626
2627 void radv_destroy_shader_slabs(struct radv_device *device)
2628 {
2629 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2630 device->ws->buffer_destroy(slab->bo);
2631 free(slab);
2632 }
2633 mtx_destroy(&device->shader_slab_mutex);
2634 }