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f46987fdf6c6985c7e4ce31d07981879837d0424
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107
108 static void
109 radv_pipeline_destroy(struct radv_device *device,
110 struct radv_pipeline *pipeline,
111 const VkAllocationCallbacks* allocator)
112 {
113 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
114 if (pipeline->shaders[i])
115 radv_shader_variant_destroy(device, pipeline->shaders[i]);
116
117 vk_free2(&device->alloc, allocator, pipeline);
118 }
119
120 void radv_DestroyPipeline(
121 VkDevice _device,
122 VkPipeline _pipeline,
123 const VkAllocationCallbacks* pAllocator)
124 {
125 RADV_FROM_HANDLE(radv_device, device, _device);
126 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
127
128 if (!_pipeline)
129 return;
130
131 radv_pipeline_destroy(device, pipeline, pAllocator);
132 }
133
134
135 static void
136 radv_optimize_nir(struct nir_shader *shader)
137 {
138 bool progress;
139
140 do {
141 progress = false;
142
143 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
144 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
145 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
146
147 NIR_PASS(progress, shader, nir_copy_prop);
148 NIR_PASS(progress, shader, nir_opt_remove_phis);
149 NIR_PASS(progress, shader, nir_opt_dce);
150 NIR_PASS(progress, shader, nir_opt_dead_cf);
151 NIR_PASS(progress, shader, nir_opt_cse);
152 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
153 NIR_PASS(progress, shader, nir_opt_algebraic);
154 NIR_PASS(progress, shader, nir_opt_constant_folding);
155 NIR_PASS(progress, shader, nir_opt_undef);
156 NIR_PASS(progress, shader, nir_opt_conditional_discard);
157 } while (progress);
158 }
159
160 static nir_shader *
161 radv_shader_compile_to_nir(struct radv_device *device,
162 struct radv_shader_module *module,
163 const char *entrypoint_name,
164 gl_shader_stage stage,
165 const VkSpecializationInfo *spec_info,
166 bool dump)
167 {
168 if (strcmp(entrypoint_name, "main") != 0) {
169 radv_finishme("Multiple shaders per module not really supported");
170 }
171
172 nir_shader *nir;
173 nir_function *entry_point;
174 if (module->nir) {
175 /* Some things such as our meta clear/blit code will give us a NIR
176 * shader directly. In that case, we just ignore the SPIR-V entirely
177 * and just use the NIR shader */
178 nir = module->nir;
179 nir->options = &nir_options;
180 nir_validate_shader(nir);
181
182 assert(exec_list_length(&nir->functions) == 1);
183 struct exec_node *node = exec_list_get_head(&nir->functions);
184 entry_point = exec_node_data(nir_function, node, node);
185 } else {
186 uint32_t *spirv = (uint32_t *) module->data;
187 assert(module->size % 4 == 0);
188
189 uint32_t num_spec_entries = 0;
190 struct nir_spirv_specialization *spec_entries = NULL;
191 if (spec_info && spec_info->mapEntryCount > 0) {
192 num_spec_entries = spec_info->mapEntryCount;
193 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
194 for (uint32_t i = 0; i < num_spec_entries; i++) {
195 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
196 const void *data = spec_info->pData + entry.offset;
197 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
198
199 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
200 if (spec_info->dataSize == 8)
201 spec_entries[i].data64 = *(const uint64_t *)data;
202 else
203 spec_entries[i].data32 = *(const uint32_t *)data;
204 }
205 }
206 const struct nir_spirv_supported_extensions supported_ext = {
207 };
208 entry_point = spirv_to_nir(spirv, module->size / 4,
209 spec_entries, num_spec_entries,
210 stage, entrypoint_name, &supported_ext, &nir_options);
211 nir = entry_point->shader;
212 assert(nir->stage == stage);
213 nir_validate_shader(nir);
214
215 free(spec_entries);
216
217 /* We have to lower away local constant initializers right before we
218 * inline functions. That way they get properly initialized at the top
219 * of the function and not at the top of its caller.
220 */
221 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
222 NIR_PASS_V(nir, nir_lower_returns);
223 NIR_PASS_V(nir, nir_inline_functions);
224
225 /* Pick off the single entrypoint that we want */
226 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
227 if (func != entry_point)
228 exec_node_remove(&func->node);
229 }
230 assert(exec_list_length(&nir->functions) == 1);
231 entry_point->name = ralloc_strdup(entry_point, "main");
232
233 NIR_PASS_V(nir, nir_remove_dead_variables,
234 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
235
236 /* Now that we've deleted all but the main function, we can go ahead and
237 * lower the rest of the constant initializers.
238 */
239 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
240 NIR_PASS_V(nir, nir_lower_system_values);
241 }
242
243 /* Vulkan uses the separate-shader linking model */
244 nir->info->separate_shader = true;
245
246 // nir = brw_preprocess_nir(compiler, nir);
247
248 nir_shader_gather_info(nir, entry_point->impl);
249
250 nir_variable_mode indirect_mask = 0;
251 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
252 indirect_mask |= nir_var_shader_in;
253 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
254 indirect_mask |= nir_var_local;
255
256 nir_lower_indirect_derefs(nir, indirect_mask);
257
258 static const nir_lower_tex_options tex_options = {
259 .lower_txp = ~0,
260 };
261
262 nir_lower_tex(nir, &tex_options);
263
264 nir_lower_vars_to_ssa(nir);
265 nir_lower_var_copies(nir);
266 nir_lower_global_vars_to_local(nir);
267 nir_remove_dead_variables(nir, nir_var_local);
268 radv_optimize_nir(nir);
269
270 if (dump)
271 nir_print_shader(nir, stderr);
272
273 return nir;
274 }
275
276 static const char *radv_get_shader_name(struct radv_shader_variant *var,
277 gl_shader_stage stage)
278 {
279 switch (stage) {
280 case MESA_SHADER_VERTEX: return "Vertex Shader as VS";
281 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
282 case MESA_SHADER_COMPUTE: return "Compute Shader";
283 default:
284 return "Unknown shader";
285 };
286
287 }
288 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
289 {
290 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
291 struct radv_shader_variant *var;
292 struct ac_shader_config *conf;
293 int i;
294 FILE *file = stderr;
295 unsigned max_simd_waves = 10;
296 unsigned lds_per_wave = 0;
297
298 for (i = 0; i < MESA_SHADER_STAGES; i++) {
299 if (!pipeline->shaders[i])
300 continue;
301 var = pipeline->shaders[i];
302
303 conf = &var->config;
304
305 if (i == MESA_SHADER_FRAGMENT) {
306 lds_per_wave = conf->lds_size * lds_increment +
307 align(var->info.fs.num_interp * 48, lds_increment);
308 }
309
310 if (conf->num_sgprs) {
311 if (device->physical_device->rad_info.chip_class >= VI)
312 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
313 else
314 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
315 }
316
317 if (conf->num_vgprs)
318 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
319
320 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
321 * that PS can use.
322 */
323 if (lds_per_wave)
324 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
325
326 fprintf(file, "\n%s:\n",
327 radv_get_shader_name(var, i));
328 if (i == MESA_SHADER_FRAGMENT) {
329 fprintf(file, "*** SHADER CONFIG ***\n"
330 "SPI_PS_INPUT_ADDR = 0x%04x\n"
331 "SPI_PS_INPUT_ENA = 0x%04x\n",
332 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
333 }
334 fprintf(file, "*** SHADER STATS ***\n"
335 "SGPRS: %d\n"
336 "VGPRS: %d\n"
337 "Spilled SGPRs: %d\n"
338 "Spilled VGPRs: %d\n"
339 "Code Size: %d bytes\n"
340 "LDS: %d blocks\n"
341 "Scratch: %d bytes per wave\n"
342 "Max Waves: %d\n"
343 "********************\n\n\n",
344 conf->num_sgprs, conf->num_vgprs,
345 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
346 conf->lds_size, conf->scratch_bytes_per_wave,
347 max_simd_waves);
348 }
349 }
350
351 void radv_shader_variant_destroy(struct radv_device *device,
352 struct radv_shader_variant *variant)
353 {
354 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
355 return;
356
357 device->ws->buffer_destroy(variant->bo);
358 free(variant);
359 }
360
361 static void radv_fill_shader_variant(struct radv_device *device,
362 struct radv_shader_variant *variant,
363 struct ac_shader_binary *binary,
364 gl_shader_stage stage)
365 {
366 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
367 unsigned vgpr_comp_cnt = 0;
368
369 if (scratch_enabled && !device->llvm_supports_spill)
370 radv_finishme("shader scratch support only available with LLVM 4.0");
371
372 variant->code_size = binary->code_size;
373
374 switch (stage) {
375 case MESA_SHADER_VERTEX:
376 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
377 S_00B12C_SCRATCH_EN(scratch_enabled);
378 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
379 break;
380 case MESA_SHADER_FRAGMENT:
381 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
382 S_00B12C_SCRATCH_EN(scratch_enabled);
383 break;
384 case MESA_SHADER_COMPUTE:
385 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
386 S_00B84C_SCRATCH_EN(scratch_enabled) |
387 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
388 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
389 S_00B84C_TG_SIZE_EN(1) |
390 S_00B84C_LDS_SIZE(variant->config.lds_size);
391 break;
392 default:
393 unreachable("unsupported shader type");
394 break;
395 }
396
397 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
398 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
399 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
400 S_00B848_DX10_CLAMP(1) |
401 S_00B848_FLOAT_MODE(variant->config.float_mode);
402
403 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
404 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
405
406 void *ptr = device->ws->buffer_map(variant->bo);
407 memcpy(ptr, binary->code, binary->code_size);
408 device->ws->buffer_unmap(variant->bo);
409
410
411 }
412
413 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
414 struct nir_shader *shader,
415 struct radv_pipeline_layout *layout,
416 const union ac_shader_variant_key *key,
417 void** code_out,
418 unsigned *code_size_out,
419 bool dump)
420 {
421 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
422 enum radeon_family chip_family = device->physical_device->rad_info.family;
423 LLVMTargetMachineRef tm;
424 if (!variant)
425 return NULL;
426
427 struct ac_nir_compiler_options options = {0};
428 options.layout = layout;
429 if (key)
430 options.key = *key;
431
432 struct ac_shader_binary binary;
433
434 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
435 options.family = chip_family;
436 options.chip_class = device->physical_device->rad_info.chip_class;
437 options.supports_spill = device->llvm_supports_spill;
438 tm = ac_create_target_machine(chip_family, options.supports_spill);
439 ac_compile_nir_shader(tm, &binary, &variant->config,
440 &variant->info, shader, &options, dump);
441 LLVMDisposeTargetMachine(tm);
442
443 radv_fill_shader_variant(device, variant, &binary, shader->stage);
444
445 if (code_out) {
446 *code_out = binary.code;
447 *code_size_out = binary.code_size;
448 } else
449 free(binary.code);
450 free(binary.config);
451 free(binary.rodata);
452 free(binary.global_symbol_offsets);
453 free(binary.relocs);
454 free(binary.disasm_string);
455 variant->ref_count = 1;
456 return variant;
457 }
458
459
460 static struct radv_shader_variant *
461 radv_pipeline_compile(struct radv_pipeline *pipeline,
462 struct radv_pipeline_cache *cache,
463 struct radv_shader_module *module,
464 const char *entrypoint,
465 gl_shader_stage stage,
466 const VkSpecializationInfo *spec_info,
467 struct radv_pipeline_layout *layout,
468 const union ac_shader_variant_key *key)
469 {
470 unsigned char sha1[20];
471 struct radv_shader_variant *variant;
472 nir_shader *nir;
473 void *code = NULL;
474 unsigned code_size = 0;
475 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
476
477 if (module->nir)
478 _mesa_sha1_compute(module->nir->info->name,
479 strlen(module->nir->info->name),
480 module->sha1);
481
482 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key);
483
484 if (cache) {
485 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
486 cache,
487 sha1);
488 if (variant)
489 return variant;
490 }
491
492 nir = radv_shader_compile_to_nir(pipeline->device,
493 module, entrypoint, stage,
494 spec_info, dump);
495 if (nir == NULL)
496 return NULL;
497
498 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
499 &code, &code_size, dump);
500 if (!module->nir)
501 ralloc_free(nir);
502
503 if (variant && cache)
504 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
505 code, code_size);
506
507 if (code)
508 free(code);
509 return variant;
510 }
511
512 static VkResult
513 radv_pipeline_scratch_init(struct radv_device *device,
514 struct radv_pipeline *pipeline)
515 {
516 unsigned scratch_bytes_per_wave = 0;
517 unsigned max_waves = 0;
518 unsigned min_waves = 1;
519
520 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
521 if (pipeline->shaders[i]) {
522 unsigned max_stage_waves = device->scratch_waves;
523
524 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
525 pipeline->shaders[i]->config.scratch_bytes_per_wave);
526
527 max_stage_waves = MIN2(max_stage_waves,
528 4 * device->physical_device->rad_info.num_good_compute_units *
529 (256 / pipeline->shaders[i]->config.num_vgprs));
530 max_waves = MAX2(max_waves, max_stage_waves);
531 }
532 }
533
534 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
535 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
536 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
537 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
538 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
539 }
540
541 if (scratch_bytes_per_wave)
542 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
543
544 if (scratch_bytes_per_wave && max_waves < min_waves) {
545 /* Not really true at this moment, but will be true on first
546 * execution. Avoid having hanging shaders. */
547 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
548 }
549 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
550 pipeline->max_waves = max_waves;
551 return VK_SUCCESS;
552 }
553
554 static uint32_t si_translate_blend_function(VkBlendOp op)
555 {
556 switch (op) {
557 case VK_BLEND_OP_ADD:
558 return V_028780_COMB_DST_PLUS_SRC;
559 case VK_BLEND_OP_SUBTRACT:
560 return V_028780_COMB_SRC_MINUS_DST;
561 case VK_BLEND_OP_REVERSE_SUBTRACT:
562 return V_028780_COMB_DST_MINUS_SRC;
563 case VK_BLEND_OP_MIN:
564 return V_028780_COMB_MIN_DST_SRC;
565 case VK_BLEND_OP_MAX:
566 return V_028780_COMB_MAX_DST_SRC;
567 default:
568 return 0;
569 }
570 }
571
572 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
573 {
574 switch (factor) {
575 case VK_BLEND_FACTOR_ZERO:
576 return V_028780_BLEND_ZERO;
577 case VK_BLEND_FACTOR_ONE:
578 return V_028780_BLEND_ONE;
579 case VK_BLEND_FACTOR_SRC_COLOR:
580 return V_028780_BLEND_SRC_COLOR;
581 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
582 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
583 case VK_BLEND_FACTOR_DST_COLOR:
584 return V_028780_BLEND_DST_COLOR;
585 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
586 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
587 case VK_BLEND_FACTOR_SRC_ALPHA:
588 return V_028780_BLEND_SRC_ALPHA;
589 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
590 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
591 case VK_BLEND_FACTOR_DST_ALPHA:
592 return V_028780_BLEND_DST_ALPHA;
593 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
594 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
595 case VK_BLEND_FACTOR_CONSTANT_COLOR:
596 return V_028780_BLEND_CONSTANT_COLOR;
597 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
598 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
599 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
600 return V_028780_BLEND_CONSTANT_ALPHA;
601 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
602 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
603 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
604 return V_028780_BLEND_SRC_ALPHA_SATURATE;
605 case VK_BLEND_FACTOR_SRC1_COLOR:
606 return V_028780_BLEND_SRC1_COLOR;
607 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
608 return V_028780_BLEND_INV_SRC1_COLOR;
609 case VK_BLEND_FACTOR_SRC1_ALPHA:
610 return V_028780_BLEND_SRC1_ALPHA;
611 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
612 return V_028780_BLEND_INV_SRC1_ALPHA;
613 default:
614 return 0;
615 }
616 }
617
618 static bool is_dual_src(VkBlendFactor factor)
619 {
620 switch (factor) {
621 case VK_BLEND_FACTOR_SRC1_COLOR:
622 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
623 case VK_BLEND_FACTOR_SRC1_ALPHA:
624 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
625 return true;
626 default:
627 return false;
628 }
629 }
630
631 static unsigned si_choose_spi_color_format(VkFormat vk_format,
632 bool blend_enable,
633 bool blend_need_alpha)
634 {
635 const struct vk_format_description *desc = vk_format_description(vk_format);
636 unsigned format, ntype, swap;
637
638 /* Alpha is needed for alpha-to-coverage.
639 * Blending may be with or without alpha.
640 */
641 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
642 unsigned alpha = 0; /* exports alpha, but may not support blending */
643 unsigned blend = 0; /* supports blending, but may not export alpha */
644 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
645
646 format = radv_translate_colorformat(vk_format);
647 ntype = radv_translate_color_numformat(vk_format, desc,
648 vk_format_get_first_non_void_channel(vk_format));
649 swap = radv_translate_colorswap(vk_format, false);
650
651 /* Choose the SPI color formats. These are required values for Stoney/RB+.
652 * Other chips have multiple choices, though they are not necessarily better.
653 */
654 switch (format) {
655 case V_028C70_COLOR_5_6_5:
656 case V_028C70_COLOR_1_5_5_5:
657 case V_028C70_COLOR_5_5_5_1:
658 case V_028C70_COLOR_4_4_4_4:
659 case V_028C70_COLOR_10_11_11:
660 case V_028C70_COLOR_11_11_10:
661 case V_028C70_COLOR_8:
662 case V_028C70_COLOR_8_8:
663 case V_028C70_COLOR_8_8_8_8:
664 case V_028C70_COLOR_10_10_10_2:
665 case V_028C70_COLOR_2_10_10_10:
666 if (ntype == V_028C70_NUMBER_UINT)
667 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
668 else if (ntype == V_028C70_NUMBER_SINT)
669 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
670 else
671 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
672 break;
673
674 case V_028C70_COLOR_16:
675 case V_028C70_COLOR_16_16:
676 case V_028C70_COLOR_16_16_16_16:
677 if (ntype == V_028C70_NUMBER_UNORM ||
678 ntype == V_028C70_NUMBER_SNORM) {
679 /* UNORM16 and SNORM16 don't support blending */
680 if (ntype == V_028C70_NUMBER_UNORM)
681 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
682 else
683 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
684
685 /* Use 32 bits per channel for blending. */
686 if (format == V_028C70_COLOR_16) {
687 if (swap == V_028C70_SWAP_STD) { /* R */
688 blend = V_028714_SPI_SHADER_32_R;
689 blend_alpha = V_028714_SPI_SHADER_32_AR;
690 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
691 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
692 else
693 assert(0);
694 } else if (format == V_028C70_COLOR_16_16) {
695 if (swap == V_028C70_SWAP_STD) { /* RG */
696 blend = V_028714_SPI_SHADER_32_GR;
697 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
698 } else if (swap == V_028C70_SWAP_ALT) /* RA */
699 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
700 else
701 assert(0);
702 } else /* 16_16_16_16 */
703 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
704 } else if (ntype == V_028C70_NUMBER_UINT)
705 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
706 else if (ntype == V_028C70_NUMBER_SINT)
707 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
708 else if (ntype == V_028C70_NUMBER_FLOAT)
709 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
710 else
711 assert(0);
712 break;
713
714 case V_028C70_COLOR_32:
715 if (swap == V_028C70_SWAP_STD) { /* R */
716 blend = normal = V_028714_SPI_SHADER_32_R;
717 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
718 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
719 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
720 else
721 assert(0);
722 break;
723
724 case V_028C70_COLOR_32_32:
725 if (swap == V_028C70_SWAP_STD) { /* RG */
726 blend = normal = V_028714_SPI_SHADER_32_GR;
727 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
728 } else if (swap == V_028C70_SWAP_ALT) /* RA */
729 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
730 else
731 assert(0);
732 break;
733
734 case V_028C70_COLOR_32_32_32_32:
735 case V_028C70_COLOR_8_24:
736 case V_028C70_COLOR_24_8:
737 case V_028C70_COLOR_X24_8_32_FLOAT:
738 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
739 break;
740
741 default:
742 unreachable("unhandled blend format");
743 }
744
745 if (blend_enable && blend_need_alpha)
746 return blend_alpha;
747 else if(blend_need_alpha)
748 return alpha;
749 else if(blend_enable)
750 return blend;
751 else
752 return normal;
753 }
754
755 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
756 {
757 unsigned i, cb_shader_mask = 0;
758
759 for (i = 0; i < 8; i++) {
760 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
761 case V_028714_SPI_SHADER_ZERO:
762 break;
763 case V_028714_SPI_SHADER_32_R:
764 cb_shader_mask |= 0x1 << (i * 4);
765 break;
766 case V_028714_SPI_SHADER_32_GR:
767 cb_shader_mask |= 0x3 << (i * 4);
768 break;
769 case V_028714_SPI_SHADER_32_AR:
770 cb_shader_mask |= 0x9 << (i * 4);
771 break;
772 case V_028714_SPI_SHADER_FP16_ABGR:
773 case V_028714_SPI_SHADER_UNORM16_ABGR:
774 case V_028714_SPI_SHADER_SNORM16_ABGR:
775 case V_028714_SPI_SHADER_UINT16_ABGR:
776 case V_028714_SPI_SHADER_SINT16_ABGR:
777 case V_028714_SPI_SHADER_32_ABGR:
778 cb_shader_mask |= 0xf << (i * 4);
779 break;
780 default:
781 assert(0);
782 }
783 }
784 return cb_shader_mask;
785 }
786
787 static void
788 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
789 const VkGraphicsPipelineCreateInfo *pCreateInfo,
790 uint32_t blend_enable,
791 uint32_t blend_need_alpha,
792 bool single_cb_enable,
793 bool blend_mrt0_is_dual_src)
794 {
795 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
796 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
797 struct radv_blend_state *blend = &pipeline->graphics.blend;
798 unsigned col_format = 0;
799
800 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
801 struct radv_render_pass_attachment *attachment;
802 unsigned cf;
803
804 attachment = pass->attachments + subpass->color_attachments[i].attachment;
805
806 cf = si_choose_spi_color_format(attachment->format,
807 blend_enable & (1 << i),
808 blend_need_alpha & (1 << i));
809
810 col_format |= cf << (4 * i);
811 }
812
813 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
814
815 if (blend_mrt0_is_dual_src)
816 col_format |= (col_format & 0xf) << 4;
817 if (!col_format)
818 col_format |= V_028714_SPI_SHADER_32_R;
819 blend->spi_shader_col_format = col_format;
820 }
821
822 static bool
823 format_is_int8(VkFormat format)
824 {
825 const struct vk_format_description *desc = vk_format_description(format);
826 int channel = vk_format_get_first_non_void_channel(format);
827
828 return channel >= 0 && desc->channel[channel].pure_integer &&
829 desc->channel[channel].size == 8;
830 }
831
832 unsigned radv_format_meta_fs_key(VkFormat format)
833 {
834 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
835 bool is_int8 = format_is_int8(format);
836
837 return col_format + (is_int8 ? 3 : 0);
838 }
839
840 static unsigned
841 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
842 {
843 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
844 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
845 unsigned is_int8 = 0;
846
847 for (unsigned i = 0; i < subpass->color_count; ++i) {
848 struct radv_render_pass_attachment *attachment;
849
850 attachment = pass->attachments + subpass->color_attachments[i].attachment;
851
852 if (format_is_int8(attachment->format))
853 is_int8 |= 1 << i;
854 }
855
856 return is_int8;
857 }
858
859 static void
860 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
861 const VkGraphicsPipelineCreateInfo *pCreateInfo,
862 const struct radv_graphics_pipeline_create_info *extra)
863 {
864 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
865 struct radv_blend_state *blend = &pipeline->graphics.blend;
866 unsigned mode = V_028808_CB_NORMAL;
867 uint32_t blend_enable = 0, blend_need_alpha = 0;
868 bool blend_mrt0_is_dual_src = false;
869 int i;
870 bool single_cb_enable = false;
871
872 if (!vkblend)
873 return;
874
875 if (extra && extra->custom_blend_mode) {
876 single_cb_enable = true;
877 mode = extra->custom_blend_mode;
878 }
879 blend->cb_color_control = 0;
880 if (vkblend->logicOpEnable)
881 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
882 else
883 blend->cb_color_control |= S_028808_ROP3(0xcc);
884
885 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
886 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
887 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
888 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
889
890 blend->cb_target_mask = 0;
891 for (i = 0; i < vkblend->attachmentCount; i++) {
892 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
893 unsigned blend_cntl = 0;
894 VkBlendOp eqRGB = att->colorBlendOp;
895 VkBlendFactor srcRGB = att->srcColorBlendFactor;
896 VkBlendFactor dstRGB = att->dstColorBlendFactor;
897 VkBlendOp eqA = att->alphaBlendOp;
898 VkBlendFactor srcA = att->srcAlphaBlendFactor;
899 VkBlendFactor dstA = att->dstAlphaBlendFactor;
900
901 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
902
903 if (!att->colorWriteMask)
904 continue;
905
906 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
907 if (!att->blendEnable) {
908 blend->cb_blend_control[i] = blend_cntl;
909 continue;
910 }
911
912 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
913 if (i == 0)
914 blend_mrt0_is_dual_src = true;
915
916 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
917 srcRGB = VK_BLEND_FACTOR_ONE;
918 dstRGB = VK_BLEND_FACTOR_ONE;
919 }
920 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
921 srcA = VK_BLEND_FACTOR_ONE;
922 dstA = VK_BLEND_FACTOR_ONE;
923 }
924
925 blend_cntl |= S_028780_ENABLE(1);
926
927 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
928 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
929 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
930 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
931 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
932 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
933 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
934 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
935 }
936 blend->cb_blend_control[i] = blend_cntl;
937
938 blend_enable |= 1 << i;
939
940 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
941 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
942 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
943 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
944 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
945 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
946 blend_need_alpha |= 1 << i;
947 }
948 for (i = vkblend->attachmentCount; i < 8; i++)
949 blend->cb_blend_control[i] = 0;
950
951 if (blend->cb_target_mask)
952 blend->cb_color_control |= S_028808_MODE(mode);
953 else
954 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
955
956 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
957 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
958 }
959
960 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
961 {
962 switch (op) {
963 case VK_STENCIL_OP_KEEP:
964 return V_02842C_STENCIL_KEEP;
965 case VK_STENCIL_OP_ZERO:
966 return V_02842C_STENCIL_ZERO;
967 case VK_STENCIL_OP_REPLACE:
968 return V_02842C_STENCIL_REPLACE_TEST;
969 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
970 return V_02842C_STENCIL_ADD_CLAMP;
971 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
972 return V_02842C_STENCIL_SUB_CLAMP;
973 case VK_STENCIL_OP_INVERT:
974 return V_02842C_STENCIL_INVERT;
975 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
976 return V_02842C_STENCIL_ADD_WRAP;
977 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
978 return V_02842C_STENCIL_SUB_WRAP;
979 default:
980 return 0;
981 }
982 }
983 static void
984 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
985 const VkGraphicsPipelineCreateInfo *pCreateInfo,
986 const struct radv_graphics_pipeline_create_info *extra)
987 {
988 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
989 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
990
991 memset(ds, 0, sizeof(*ds));
992 if (!vkds)
993 return;
994 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
995 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
996 S_028800_ZFUNC(vkds->depthCompareOp) |
997 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
998
999 if (vkds->stencilTestEnable) {
1000 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1001 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1002 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1003 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1004 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1005
1006 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1007 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1008 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1009 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1010 }
1011
1012 if (extra) {
1013
1014 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1015 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1016
1017 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1018 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1019 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1020 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1021 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1022 }
1023 }
1024
1025 static uint32_t si_translate_fill(VkPolygonMode func)
1026 {
1027 switch(func) {
1028 case VK_POLYGON_MODE_FILL:
1029 return V_028814_X_DRAW_TRIANGLES;
1030 case VK_POLYGON_MODE_LINE:
1031 return V_028814_X_DRAW_LINES;
1032 case VK_POLYGON_MODE_POINT:
1033 return V_028814_X_DRAW_POINTS;
1034 default:
1035 assert(0);
1036 return V_028814_X_DRAW_POINTS;
1037 }
1038 }
1039 static void
1040 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1041 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1042 {
1043 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1044 struct radv_raster_state *raster = &pipeline->graphics.raster;
1045
1046 memset(raster, 0, sizeof(*raster));
1047
1048 raster->spi_interp_control =
1049 S_0286D4_FLAT_SHADE_ENA(1) |
1050 S_0286D4_PNT_SPRITE_ENA(1) |
1051 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1052 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1053 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1054 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1055 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1056
1057 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
1058 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1059 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1060 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1061 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1062 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1063 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1064
1065 raster->pa_su_vtx_cntl =
1066 S_028BE4_PIX_CENTER(1) | // TODO verify
1067 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1068 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1069
1070 raster->pa_su_sc_mode_cntl =
1071 S_028814_FACE(vkraster->frontFace) |
1072 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1073 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1074 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1075 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1076 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1077 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1078 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1079 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1080
1081 }
1082
1083 static void
1084 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1085 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1086 {
1087 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1088 struct radv_blend_state *blend = &pipeline->graphics.blend;
1089 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1090 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1091 int ps_iter_samples = 1;
1092 uint32_t mask = 0xffff;
1093
1094 ms->num_samples = vkms->rasterizationSamples;
1095
1096 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1097 ps_iter_samples = vkms->rasterizationSamples;
1098 }
1099
1100 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1101 ms->pa_sc_aa_config = 0;
1102 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1103 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1104 ms->pa_sc_mode_cntl_1 =
1105 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1106 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1107 /* always 1: */
1108 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1109 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1110 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1111 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1112 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1113 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1114
1115 if (vkms->rasterizationSamples > 1) {
1116 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1117 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1118 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1119 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1120 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1121 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1122 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1123 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1124 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1125 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1126 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1127 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1128 }
1129
1130 if (vkms->alphaToCoverageEnable)
1131 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1132
1133 if (vkms->pSampleMask) {
1134 mask = vkms->pSampleMask[0] & 0xffff;
1135 }
1136
1137 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1138 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1139 }
1140
1141 static uint32_t
1142 si_translate_prim(enum VkPrimitiveTopology topology)
1143 {
1144 switch (topology) {
1145 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1146 return V_008958_DI_PT_POINTLIST;
1147 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1148 return V_008958_DI_PT_LINELIST;
1149 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1150 return V_008958_DI_PT_LINESTRIP;
1151 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1152 return V_008958_DI_PT_TRILIST;
1153 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1154 return V_008958_DI_PT_TRISTRIP;
1155 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1156 return V_008958_DI_PT_TRIFAN;
1157 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1158 return V_008958_DI_PT_LINELIST_ADJ;
1159 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1160 return V_008958_DI_PT_LINESTRIP_ADJ;
1161 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1162 return V_008958_DI_PT_TRILIST_ADJ;
1163 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1164 return V_008958_DI_PT_TRISTRIP_ADJ;
1165 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1166 return V_008958_DI_PT_PATCH;
1167 default:
1168 assert(0);
1169 return 0;
1170 }
1171 }
1172
1173 static uint32_t
1174 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1175 {
1176 switch (topology) {
1177 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1178 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1179 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1181 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1182 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1183 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1184 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1190 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1191 default:
1192 assert(0);
1193 return 0;
1194 }
1195 }
1196
1197 static unsigned si_map_swizzle(unsigned swizzle)
1198 {
1199 switch (swizzle) {
1200 case VK_SWIZZLE_Y:
1201 return V_008F0C_SQ_SEL_Y;
1202 case VK_SWIZZLE_Z:
1203 return V_008F0C_SQ_SEL_Z;
1204 case VK_SWIZZLE_W:
1205 return V_008F0C_SQ_SEL_W;
1206 case VK_SWIZZLE_0:
1207 return V_008F0C_SQ_SEL_0;
1208 case VK_SWIZZLE_1:
1209 return V_008F0C_SQ_SEL_1;
1210 default: /* VK_SWIZZLE_X */
1211 return V_008F0C_SQ_SEL_X;
1212 }
1213 }
1214
1215 static void
1216 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1217 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1218 {
1219 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1220 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1221 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1222
1223 pipeline->dynamic_state = default_dynamic_state;
1224
1225 if (pCreateInfo->pDynamicState) {
1226 /* Remove all of the states that are marked as dynamic */
1227 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1228 for (uint32_t s = 0; s < count; s++)
1229 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1230 }
1231
1232 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1233
1234 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1235 *
1236 * pViewportState is [...] NULL if the pipeline
1237 * has rasterization disabled.
1238 */
1239 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1240 assert(pCreateInfo->pViewportState);
1241
1242 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1243 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1244 typed_memcpy(dynamic->viewport.viewports,
1245 pCreateInfo->pViewportState->pViewports,
1246 pCreateInfo->pViewportState->viewportCount);
1247 }
1248
1249 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1250 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1251 typed_memcpy(dynamic->scissor.scissors,
1252 pCreateInfo->pViewportState->pScissors,
1253 pCreateInfo->pViewportState->scissorCount);
1254 }
1255 }
1256
1257 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1258 assert(pCreateInfo->pRasterizationState);
1259 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1260 }
1261
1262 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1263 assert(pCreateInfo->pRasterizationState);
1264 dynamic->depth_bias.bias =
1265 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1266 dynamic->depth_bias.clamp =
1267 pCreateInfo->pRasterizationState->depthBiasClamp;
1268 dynamic->depth_bias.slope =
1269 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1270 }
1271
1272 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1273 *
1274 * pColorBlendState is [...] NULL if the pipeline has rasterization
1275 * disabled or if the subpass of the render pass the pipeline is
1276 * created against does not use any color attachments.
1277 */
1278 bool uses_color_att = false;
1279 for (unsigned i = 0; i < subpass->color_count; ++i) {
1280 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1281 uses_color_att = true;
1282 break;
1283 }
1284 }
1285
1286 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1287 assert(pCreateInfo->pColorBlendState);
1288 typed_memcpy(dynamic->blend_constants,
1289 pCreateInfo->pColorBlendState->blendConstants, 4);
1290 }
1291
1292 /* If there is no depthstencil attachment, then don't read
1293 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1294 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1295 * no need to override the depthstencil defaults in
1296 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1297 *
1298 * Section 9.2 of the Vulkan 1.0.15 spec says:
1299 *
1300 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1301 * disabled or if the subpass of the render pass the pipeline is created
1302 * against does not use a depth/stencil attachment.
1303 */
1304 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1305 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1306 assert(pCreateInfo->pDepthStencilState);
1307
1308 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1309 dynamic->depth_bounds.min =
1310 pCreateInfo->pDepthStencilState->minDepthBounds;
1311 dynamic->depth_bounds.max =
1312 pCreateInfo->pDepthStencilState->maxDepthBounds;
1313 }
1314
1315 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1316 dynamic->stencil_compare_mask.front =
1317 pCreateInfo->pDepthStencilState->front.compareMask;
1318 dynamic->stencil_compare_mask.back =
1319 pCreateInfo->pDepthStencilState->back.compareMask;
1320 }
1321
1322 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1323 dynamic->stencil_write_mask.front =
1324 pCreateInfo->pDepthStencilState->front.writeMask;
1325 dynamic->stencil_write_mask.back =
1326 pCreateInfo->pDepthStencilState->back.writeMask;
1327 }
1328
1329 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1330 dynamic->stencil_reference.front =
1331 pCreateInfo->pDepthStencilState->front.reference;
1332 dynamic->stencil_reference.back =
1333 pCreateInfo->pDepthStencilState->back.reference;
1334 }
1335 }
1336
1337 pipeline->dynamic_state_mask = states;
1338 }
1339
1340 static union ac_shader_variant_key
1341 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1342 {
1343 union ac_shader_variant_key key;
1344 const VkPipelineVertexInputStateCreateInfo *input_state =
1345 pCreateInfo->pVertexInputState;
1346
1347 memset(&key, 0, sizeof(key));
1348 key.vs.instance_rate_inputs = 0;
1349
1350 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1351 unsigned binding;
1352 binding = input_state->pVertexAttributeDescriptions[i].binding;
1353 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1354 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1355 }
1356 return key;
1357 }
1358
1359 VkResult
1360 radv_pipeline_init(struct radv_pipeline *pipeline,
1361 struct radv_device *device,
1362 struct radv_pipeline_cache *cache,
1363 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1364 const struct radv_graphics_pipeline_create_info *extra,
1365 const VkAllocationCallbacks *alloc)
1366 {
1367 struct radv_shader_module fs_m = {0};
1368 VkResult result;
1369
1370 if (alloc == NULL)
1371 alloc = &device->alloc;
1372
1373 pipeline->device = device;
1374 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1375
1376 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1377 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1378 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1379 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1380 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1381 pStages[stage] = &pCreateInfo->pStages[i];
1382 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1383 }
1384
1385 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1386
1387 /* */
1388 if (modules[MESA_SHADER_VERTEX]) {
1389 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
1390
1391 pipeline->shaders[MESA_SHADER_VERTEX] =
1392 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1393 pStages[MESA_SHADER_VERTEX]->pName,
1394 MESA_SHADER_VERTEX,
1395 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1396 pipeline->layout, &key);
1397
1398 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1399 }
1400
1401 if (!modules[MESA_SHADER_FRAGMENT]) {
1402 nir_builder fs_b;
1403 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1404 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1405 fs_m.nir = fs_b.shader;
1406 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1407 }
1408
1409 if (modules[MESA_SHADER_FRAGMENT]) {
1410 union ac_shader_variant_key key;
1411 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1412 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1413
1414 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1415
1416 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1417 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1418 stage ? stage->pName : "main",
1419 MESA_SHADER_FRAGMENT,
1420 stage ? stage->pSpecializationInfo : NULL,
1421 pipeline->layout, &key);
1422 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1423 }
1424
1425 if (fs_m.nir)
1426 ralloc_free(fs_m.nir);
1427
1428 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1429 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1430 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1431 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1432 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1433 if (extra && extra->use_rectlist) {
1434 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1435 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1436 }
1437 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1438
1439 const VkPipelineVertexInputStateCreateInfo *vi_info =
1440 pCreateInfo->pVertexInputState;
1441 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1442 const VkVertexInputAttributeDescription *desc =
1443 &vi_info->pVertexAttributeDescriptions[i];
1444 unsigned loc = desc->location;
1445 const struct vk_format_description *format_desc;
1446 int first_non_void;
1447 uint32_t num_format, data_format;
1448 format_desc = vk_format_description(desc->format);
1449 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1450
1451 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1452 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1453
1454 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1455 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1456 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1457 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1458 S_008F0C_NUM_FORMAT(num_format) |
1459 S_008F0C_DATA_FORMAT(data_format);
1460 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1461 pipeline->va_offset[loc] = desc->offset;
1462 pipeline->va_binding[loc] = desc->binding;
1463 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1464 }
1465
1466 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1467 const VkVertexInputBindingDescription *desc =
1468 &vi_info->pVertexBindingDescriptions[i];
1469
1470 pipeline->binding_stride[desc->binding] = desc->stride;
1471 }
1472
1473 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1474 radv_dump_pipeline_stats(device, pipeline);
1475 }
1476
1477 result = radv_pipeline_scratch_init(device, pipeline);
1478 return result;
1479 }
1480
1481 VkResult
1482 radv_graphics_pipeline_create(
1483 VkDevice _device,
1484 VkPipelineCache _cache,
1485 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1486 const struct radv_graphics_pipeline_create_info *extra,
1487 const VkAllocationCallbacks *pAllocator,
1488 VkPipeline *pPipeline)
1489 {
1490 RADV_FROM_HANDLE(radv_device, device, _device);
1491 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1492 struct radv_pipeline *pipeline;
1493 VkResult result;
1494
1495 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1496 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1497 if (pipeline == NULL)
1498 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1499
1500 memset(pipeline, 0, sizeof(*pipeline));
1501 result = radv_pipeline_init(pipeline, device, cache,
1502 pCreateInfo, extra, pAllocator);
1503 if (result != VK_SUCCESS) {
1504 radv_pipeline_destroy(device, pipeline, pAllocator);
1505 return result;
1506 }
1507
1508 *pPipeline = radv_pipeline_to_handle(pipeline);
1509
1510 return VK_SUCCESS;
1511 }
1512
1513 VkResult radv_CreateGraphicsPipelines(
1514 VkDevice _device,
1515 VkPipelineCache pipelineCache,
1516 uint32_t count,
1517 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1518 const VkAllocationCallbacks* pAllocator,
1519 VkPipeline* pPipelines)
1520 {
1521 VkResult result = VK_SUCCESS;
1522 unsigned i = 0;
1523
1524 for (; i < count; i++) {
1525 VkResult r;
1526 r = radv_graphics_pipeline_create(_device,
1527 pipelineCache,
1528 &pCreateInfos[i],
1529 NULL, pAllocator, &pPipelines[i]);
1530 if (r != VK_SUCCESS) {
1531 result = r;
1532 pPipelines[i] = VK_NULL_HANDLE;
1533 }
1534 }
1535
1536 return result;
1537 }
1538
1539 static VkResult radv_compute_pipeline_create(
1540 VkDevice _device,
1541 VkPipelineCache _cache,
1542 const VkComputePipelineCreateInfo* pCreateInfo,
1543 const VkAllocationCallbacks* pAllocator,
1544 VkPipeline* pPipeline)
1545 {
1546 RADV_FROM_HANDLE(radv_device, device, _device);
1547 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1548 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1549 struct radv_pipeline *pipeline;
1550 VkResult result;
1551
1552 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1553 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1554 if (pipeline == NULL)
1555 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1556
1557 memset(pipeline, 0, sizeof(*pipeline));
1558 pipeline->device = device;
1559 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1560
1561 pipeline->shaders[MESA_SHADER_COMPUTE] =
1562 radv_pipeline_compile(pipeline, cache, module,
1563 pCreateInfo->stage.pName,
1564 MESA_SHADER_COMPUTE,
1565 pCreateInfo->stage.pSpecializationInfo,
1566 pipeline->layout, NULL);
1567
1568
1569 result = radv_pipeline_scratch_init(device, pipeline);
1570 if (result != VK_SUCCESS) {
1571 radv_pipeline_destroy(device, pipeline, pAllocator);
1572 return result;
1573 }
1574
1575 *pPipeline = radv_pipeline_to_handle(pipeline);
1576
1577 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1578 radv_dump_pipeline_stats(device, pipeline);
1579 }
1580 return VK_SUCCESS;
1581 }
1582 VkResult radv_CreateComputePipelines(
1583 VkDevice _device,
1584 VkPipelineCache pipelineCache,
1585 uint32_t count,
1586 const VkComputePipelineCreateInfo* pCreateInfos,
1587 const VkAllocationCallbacks* pAllocator,
1588 VkPipeline* pPipelines)
1589 {
1590 VkResult result = VK_SUCCESS;
1591
1592 unsigned i = 0;
1593 for (; i < count; i++) {
1594 VkResult r;
1595 r = radv_compute_pipeline_create(_device, pipelineCache,
1596 &pCreateInfos[i],
1597 pAllocator, &pPipelines[i]);
1598 if (r != VK_SUCCESS) {
1599 result = r;
1600 pPipelines[i] = VK_NULL_HANDLE;
1601 }
1602 }
1603
1604 return result;
1605 }