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radv: disable CPU caching for IBS to reduce fetch latency
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 static const VkPipelineMultisampleStateCreateInfo *
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
94 {
95 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
96 return pCreateInfo->pMultisampleState;
97 return NULL;
98 }
99
100 static const VkPipelineTessellationStateCreateInfo *
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
102 {
103 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
104 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
105 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
106 return pCreateInfo->pTessellationState;
107 }
108 }
109 return NULL;
110 }
111
112 static const VkPipelineDepthStencilStateCreateInfo *
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
114 {
115 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
116 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
117
118 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
119 subpass->depth_stencil_attachment)
120 return pCreateInfo->pDepthStencilState;
121 return NULL;
122 }
123
124 static const VkPipelineColorBlendStateCreateInfo *
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
126 {
127 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
128 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
129
130 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
131 subpass->has_color_att)
132 return pCreateInfo->pColorBlendState;
133 return NULL;
134 }
135
136 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
137 {
138 struct radv_shader_variant *variant = NULL;
139 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
140 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
141 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
142 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
143 else if (pipeline->shaders[MESA_SHADER_VERTEX])
144 variant = pipeline->shaders[MESA_SHADER_VERTEX];
145 else
146 return false;
147 return variant->info.is_ngg;
148 }
149
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
151 {
152 assert(radv_pipeline_has_ngg(pipeline));
153
154 struct radv_shader_variant *variant = NULL;
155 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
156 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
157 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
158 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
159 else if (pipeline->shaders[MESA_SHADER_VERTEX])
160 variant = pipeline->shaders[MESA_SHADER_VERTEX];
161 else
162 return false;
163 return variant->info.is_ngg_passthrough;
164 }
165
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
167 {
168 if (!radv_pipeline_has_gs(pipeline))
169 return false;
170
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
173 * enable NGG.
174 */
175 if (radv_pipeline_has_ngg(pipeline))
176 return false;
177
178 assert(pipeline->gs_copy_shader);
179 return true;
180 }
181
182 static void
183 radv_pipeline_destroy(struct radv_device *device,
184 struct radv_pipeline *pipeline,
185 const VkAllocationCallbacks* allocator)
186 {
187 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
188 if (pipeline->shaders[i])
189 radv_shader_variant_destroy(device, pipeline->shaders[i]);
190
191 if (pipeline->gs_copy_shader)
192 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
193
194 if(pipeline->cs.buf)
195 free(pipeline->cs.buf);
196
197 vk_object_base_finish(&pipeline->base);
198 vk_free2(&device->vk.alloc, allocator, pipeline);
199 }
200
201 void radv_DestroyPipeline(
202 VkDevice _device,
203 VkPipeline _pipeline,
204 const VkAllocationCallbacks* pAllocator)
205 {
206 RADV_FROM_HANDLE(radv_device, device, _device);
207 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
208
209 if (!_pipeline)
210 return;
211
212 radv_pipeline_destroy(device, pipeline, pAllocator);
213 }
214
215 static uint32_t get_hash_flags(struct radv_device *device)
216 {
217 uint32_t hash_flags = 0;
218
219 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
220 hash_flags |= RADV_HASH_SHADER_NO_NGG;
221 if (device->physical_device->cs_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
223 if (device->physical_device->ps_wave_size == 32)
224 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
225 if (device->physical_device->ge_wave_size == 32)
226 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
227 if (device->physical_device->use_llvm)
228 hash_flags |= RADV_HASH_SHADER_LLVM;
229 return hash_flags;
230 }
231
232 static VkResult
233 radv_pipeline_scratch_init(struct radv_device *device,
234 struct radv_pipeline *pipeline)
235 {
236 unsigned scratch_bytes_per_wave = 0;
237 unsigned max_waves = 0;
238 unsigned min_waves = 1;
239
240 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
241 if (pipeline->shaders[i] &&
242 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
243 unsigned max_stage_waves = device->scratch_waves;
244
245 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
246 pipeline->shaders[i]->config.scratch_bytes_per_wave);
247
248 max_stage_waves = MIN2(max_stage_waves,
249 4 * device->physical_device->rad_info.num_good_compute_units *
250 (256 / pipeline->shaders[i]->config.num_vgprs));
251 max_waves = MAX2(max_waves, max_stage_waves);
252 }
253 }
254
255 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
256 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
258 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
259 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
260 }
261
262 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
263 pipeline->max_waves = max_waves;
264 return VK_SUCCESS;
265 }
266
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
268 {
269 switch (op) {
270 case VK_LOGIC_OP_CLEAR:
271 return V_028808_ROP3_CLEAR;
272 case VK_LOGIC_OP_AND:
273 return V_028808_ROP3_AND;
274 case VK_LOGIC_OP_AND_REVERSE:
275 return V_028808_ROP3_AND_REVERSE;
276 case VK_LOGIC_OP_COPY:
277 return V_028808_ROP3_COPY;
278 case VK_LOGIC_OP_AND_INVERTED:
279 return V_028808_ROP3_AND_INVERTED;
280 case VK_LOGIC_OP_NO_OP:
281 return V_028808_ROP3_NO_OP;
282 case VK_LOGIC_OP_XOR:
283 return V_028808_ROP3_XOR;
284 case VK_LOGIC_OP_OR:
285 return V_028808_ROP3_OR;
286 case VK_LOGIC_OP_NOR:
287 return V_028808_ROP3_NOR;
288 case VK_LOGIC_OP_EQUIVALENT:
289 return V_028808_ROP3_EQUIVALENT;
290 case VK_LOGIC_OP_INVERT:
291 return V_028808_ROP3_INVERT;
292 case VK_LOGIC_OP_OR_REVERSE:
293 return V_028808_ROP3_OR_REVERSE;
294 case VK_LOGIC_OP_COPY_INVERTED:
295 return V_028808_ROP3_COPY_INVERTED;
296 case VK_LOGIC_OP_OR_INVERTED:
297 return V_028808_ROP3_OR_INVERTED;
298 case VK_LOGIC_OP_NAND:
299 return V_028808_ROP3_NAND;
300 case VK_LOGIC_OP_SET:
301 return V_028808_ROP3_SET;
302 default:
303 unreachable("Unhandled logic op");
304 }
305 }
306
307
308 static uint32_t si_translate_blend_function(VkBlendOp op)
309 {
310 switch (op) {
311 case VK_BLEND_OP_ADD:
312 return V_028780_COMB_DST_PLUS_SRC;
313 case VK_BLEND_OP_SUBTRACT:
314 return V_028780_COMB_SRC_MINUS_DST;
315 case VK_BLEND_OP_REVERSE_SUBTRACT:
316 return V_028780_COMB_DST_MINUS_SRC;
317 case VK_BLEND_OP_MIN:
318 return V_028780_COMB_MIN_DST_SRC;
319 case VK_BLEND_OP_MAX:
320 return V_028780_COMB_MAX_DST_SRC;
321 default:
322 return 0;
323 }
324 }
325
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
327 {
328 switch (factor) {
329 case VK_BLEND_FACTOR_ZERO:
330 return V_028780_BLEND_ZERO;
331 case VK_BLEND_FACTOR_ONE:
332 return V_028780_BLEND_ONE;
333 case VK_BLEND_FACTOR_SRC_COLOR:
334 return V_028780_BLEND_SRC_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
337 case VK_BLEND_FACTOR_DST_COLOR:
338 return V_028780_BLEND_DST_COLOR;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
341 case VK_BLEND_FACTOR_SRC_ALPHA:
342 return V_028780_BLEND_SRC_ALPHA;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
345 case VK_BLEND_FACTOR_DST_ALPHA:
346 return V_028780_BLEND_DST_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR:
350 return V_028780_BLEND_CONSTANT_COLOR;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
354 return V_028780_BLEND_CONSTANT_ALPHA;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE;
359 case VK_BLEND_FACTOR_SRC1_COLOR:
360 return V_028780_BLEND_SRC1_COLOR;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
362 return V_028780_BLEND_INV_SRC1_COLOR;
363 case VK_BLEND_FACTOR_SRC1_ALPHA:
364 return V_028780_BLEND_SRC1_ALPHA;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
366 return V_028780_BLEND_INV_SRC1_ALPHA;
367 default:
368 return 0;
369 }
370 }
371
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
373 {
374 switch (op) {
375 case VK_BLEND_OP_ADD:
376 return V_028760_OPT_COMB_ADD;
377 case VK_BLEND_OP_SUBTRACT:
378 return V_028760_OPT_COMB_SUBTRACT;
379 case VK_BLEND_OP_REVERSE_SUBTRACT:
380 return V_028760_OPT_COMB_REVSUBTRACT;
381 case VK_BLEND_OP_MIN:
382 return V_028760_OPT_COMB_MIN;
383 case VK_BLEND_OP_MAX:
384 return V_028760_OPT_COMB_MAX;
385 default:
386 return V_028760_OPT_COMB_BLEND_DISABLED;
387 }
388 }
389
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
391 {
392 switch (factor) {
393 case VK_BLEND_FACTOR_ZERO:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
395 case VK_BLEND_FACTOR_ONE:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
397 case VK_BLEND_FACTOR_SRC_COLOR:
398 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
401 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
403 case VK_BLEND_FACTOR_SRC_ALPHA:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
408 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
410 default:
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == VK_BLEND_FACTOR_ZERO) {
425 *src_factor = VK_BLEND_FACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == VK_BLEND_OP_SUBTRACT)
430 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
431 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
432 *func = VK_BLEND_OP_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == VK_BLEND_FACTOR_DST_COLOR ||
439 factor == VK_BLEND_FACTOR_DST_ALPHA ||
440 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
441 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
442 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
443 }
444
445 static bool is_dual_src(VkBlendFactor factor)
446 {
447 switch (factor) {
448 case VK_BLEND_FACTOR_SRC1_COLOR:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
450 case VK_BLEND_FACTOR_SRC1_ALPHA:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
452 return true;
453 default:
454 return false;
455 }
456 }
457
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
459 bool blend_enable,
460 bool blend_need_alpha)
461 {
462 const struct vk_format_description *desc = vk_format_description(vk_format);
463 struct ac_spi_color_formats formats = {};
464 unsigned format, ntype, swap;
465
466 format = radv_translate_colorformat(vk_format);
467 ntype = radv_translate_color_numformat(vk_format, desc,
468 vk_format_get_first_non_void_channel(vk_format));
469 swap = radv_translate_colorswap(vk_format, false);
470
471 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
472
473 if (blend_enable && blend_need_alpha)
474 return formats.blend_alpha;
475 else if(blend_need_alpha)
476 return formats.alpha;
477 else if(blend_enable)
478 return formats.blend;
479 else
480 return formats.normal;
481 }
482
483 static bool
484 format_is_int8(VkFormat format)
485 {
486 const struct vk_format_description *desc = vk_format_description(format);
487 int channel = vk_format_get_first_non_void_channel(format);
488
489 return channel >= 0 && desc->channel[channel].pure_integer &&
490 desc->channel[channel].size == 8;
491 }
492
493 static bool
494 format_is_int10(VkFormat format)
495 {
496 const struct vk_format_description *desc = vk_format_description(format);
497
498 if (desc->nr_channels != 4)
499 return false;
500 for (unsigned i = 0; i < 4; i++) {
501 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
502 return true;
503 }
504 return false;
505 }
506
507 static void
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
509 const VkGraphicsPipelineCreateInfo *pCreateInfo,
510 struct radv_blend_state *blend)
511 {
512 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
513 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
514 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
515 unsigned num_targets;
516
517 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
518 unsigned cf;
519
520 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
521 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
522 cf = V_028714_SPI_SHADER_ZERO;
523 } else {
524 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
525 bool blend_enable =
526 blend->blend_enable_4bit & (0xfu << (i * 4));
527
528 cf = radv_choose_spi_color_format(attachment->format,
529 blend_enable,
530 blend->need_src_alpha & (1 << i));
531
532 if (format_is_int8(attachment->format))
533 is_int8 |= 1 << i;
534 if (format_is_int10(attachment->format))
535 is_int10 |= 1 << i;
536 }
537
538 col_format |= cf << (4 * i);
539 }
540
541 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
545 */
546 col_format |= V_028714_SPI_SHADER_32_AR;
547 }
548
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
551 */
552 num_targets = (util_last_bit(col_format) + 3) / 4;
553 for (unsigned i = 0; i < num_targets; i++) {
554 if (!(col_format & (0xf << (i * 4)))) {
555 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
556 }
557 }
558
559 /* The output for dual source blending should have the same format as
560 * the first output.
561 */
562 if (blend->mrt0_is_dual_src)
563 col_format |= (col_format & 0xf) << 4;
564
565 blend->spi_shader_col_format = col_format;
566 blend->col_format_is_int8 = is_int8;
567 blend->col_format_is_int10 = is_int10;
568 }
569
570 /*
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
573 */
574 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
575 VK_FORMAT_R32_SFLOAT,
576 VK_FORMAT_R32G32_SFLOAT,
577 VK_FORMAT_R8G8B8A8_UNORM,
578 VK_FORMAT_R16G16B16A16_UNORM,
579 VK_FORMAT_R16G16B16A16_SNORM,
580 VK_FORMAT_R16G16B16A16_UINT,
581 VK_FORMAT_R16G16B16A16_SINT,
582 VK_FORMAT_R32G32B32A32_SFLOAT,
583 VK_FORMAT_R8G8B8A8_UINT,
584 VK_FORMAT_R8G8B8A8_SINT,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32,
587 };
588
589 unsigned radv_format_meta_fs_key(VkFormat format)
590 {
591 unsigned col_format = radv_choose_spi_color_format(format, false, false);
592
593 assert(col_format != V_028714_SPI_SHADER_32_AR);
594 if (col_format >= V_028714_SPI_SHADER_32_AR)
595 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
596
597 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8 = format_is_int8(format);
599 bool is_int10 = format_is_int10(format);
600
601 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
602 }
603
604 static void
605 radv_blend_check_commutativity(struct radv_blend_state *blend,
606 VkBlendOp op, VkBlendFactor src,
607 VkBlendFactor dst, unsigned chanmask)
608 {
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed =
611 (1u << VK_BLEND_FACTOR_ONE) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
619 (1u << VK_BLEND_FACTOR_ZERO) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
626
627 if (dst == VK_BLEND_FACTOR_ONE &&
628 (src_allowed & (1u << src))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
632 */
633 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
634 blend->commutative_4bit |= chanmask;
635 }
636 }
637
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
640 const VkGraphicsPipelineCreateInfo *pCreateInfo,
641 const struct radv_graphics_pipeline_create_info *extra)
642 {
643 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
644 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
645 struct radv_blend_state blend = {0};
646 unsigned mode = V_028808_CB_NORMAL;
647 int i;
648
649 if (extra && extra->custom_blend_mode) {
650 blend.single_cb_enable = true;
651 mode = extra->custom_blend_mode;
652 }
653
654 blend.cb_color_control = 0;
655 if (vkblend) {
656 if (vkblend->logicOpEnable)
657 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
658 else
659 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
660 }
661
662 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
667
668 if (vkms && vkms->alphaToCoverageEnable) {
669 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend.need_src_alpha |= 0x1;
671 }
672
673 blend.cb_target_mask = 0;
674 if (vkblend) {
675 for (i = 0; i < vkblend->attachmentCount; i++) {
676 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
677 unsigned blend_cntl = 0;
678 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
679 VkBlendOp eqRGB = att->colorBlendOp;
680 VkBlendFactor srcRGB = att->srcColorBlendFactor;
681 VkBlendFactor dstRGB = att->dstColorBlendFactor;
682 VkBlendOp eqA = att->alphaBlendOp;
683 VkBlendFactor srcA = att->srcAlphaBlendFactor;
684 VkBlendFactor dstA = att->dstAlphaBlendFactor;
685
686 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
687
688 if (!att->colorWriteMask)
689 continue;
690
691 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
692 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
693 if (!att->blendEnable) {
694 blend.cb_blend_control[i] = blend_cntl;
695 continue;
696 }
697
698 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
699 if (i == 0)
700 blend.mrt0_is_dual_src = true;
701
702 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
703 srcRGB = VK_BLEND_FACTOR_ONE;
704 dstRGB = VK_BLEND_FACTOR_ONE;
705 }
706 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
707 srcA = VK_BLEND_FACTOR_ONE;
708 dstA = VK_BLEND_FACTOR_ONE;
709 }
710
711 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
712 0x7 << (4 * i));
713 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
714 0x8 << (4 * i));
715
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
718 *
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
721 */
722 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
723 VK_BLEND_FACTOR_DST_COLOR,
724 VK_BLEND_FACTOR_SRC_COLOR);
725
726 si_blend_remove_dst(&eqA, &srcA, &dstA,
727 VK_BLEND_FACTOR_DST_COLOR,
728 VK_BLEND_FACTOR_SRC_COLOR);
729
730 si_blend_remove_dst(&eqA, &srcA, &dstA,
731 VK_BLEND_FACTOR_DST_ALPHA,
732 VK_BLEND_FACTOR_SRC_ALPHA);
733
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
736 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
737 srcA_opt = si_translate_blend_opt_factor(srcA, true);
738 dstA_opt = si_translate_blend_opt_factor(dstA, true);
739
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
743 if (si_blend_factor_uses_dst(srcA))
744 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
745
746 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
747 (dstRGB == VK_BLEND_FACTOR_ZERO ||
748 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
749 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
750 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
751
752 /* Set the final value. */
753 blend.sx_mrt_blend_opt[i] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt) |
758 S_028760_ALPHA_DST_OPT(dstA_opt) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
760 blend_cntl |= S_028780_ENABLE(1);
761
762 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
763 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
764 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
765 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
766 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
768 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
769 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
770 }
771 blend.cb_blend_control[i] = blend_cntl;
772
773 blend.blend_enable_4bit |= 0xfu << (i * 4);
774
775 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
776 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
777 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
778 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
779 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
780 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
781 blend.need_src_alpha |= 1 << i;
782 }
783 for (i = vkblend->attachmentCount; i < 8; i++) {
784 blend.cb_blend_control[i] = 0;
785 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
786 }
787 }
788
789 if (pipeline->device->physical_device->rad_info.has_rbplus) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend.mrt0_is_dual_src) {
792 for (i = 0; i < 8; i++) {
793 blend.sx_mrt_blend_opt[i] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
796 }
797 }
798
799 /* RB+ doesn't work with dual source blending, logic op and
800 * RESOLVE.
801 */
802 if (blend.mrt0_is_dual_src ||
803 (vkblend && vkblend->logicOpEnable) ||
804 mode == V_028808_CB_RESOLVE)
805 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
806 }
807
808 if (blend.cb_target_mask)
809 blend.cb_color_control |= S_028808_MODE(mode);
810 else
811 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
812
813 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
814 return blend;
815 }
816
817 static uint32_t si_translate_fill(VkPolygonMode func)
818 {
819 switch(func) {
820 case VK_POLYGON_MODE_FILL:
821 return V_028814_X_DRAW_TRIANGLES;
822 case VK_POLYGON_MODE_LINE:
823 return V_028814_X_DRAW_LINES;
824 case VK_POLYGON_MODE_POINT:
825 return V_028814_X_DRAW_POINTS;
826 default:
827 assert(0);
828 return V_028814_X_DRAW_POINTS;
829 }
830 }
831
832 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
833 {
834 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
835 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
836 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
837 uint32_t ps_iter_samples = 1;
838 uint32_t num_samples;
839
840 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
841 *
842 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
843 * subpass uses color attachments, totalSamples is the number of
844 * samples of the color attachments. Otherwise, totalSamples is the
845 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
846 * specified at pipeline creation time."
847 */
848 if (subpass->has_color_att) {
849 num_samples = subpass->color_sample_count;
850 } else {
851 num_samples = vkms->rasterizationSamples;
852 }
853
854 if (vkms->sampleShadingEnable) {
855 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
856 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
857 }
858 return ps_iter_samples;
859 }
860
861 static bool
862 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
863 {
864 return pCreateInfo->depthTestEnable &&
865 pCreateInfo->depthWriteEnable &&
866 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
867 }
868
869 static bool
870 radv_writes_stencil(const VkStencilOpState *state)
871 {
872 return state->writeMask &&
873 (state->failOp != VK_STENCIL_OP_KEEP ||
874 state->passOp != VK_STENCIL_OP_KEEP ||
875 state->depthFailOp != VK_STENCIL_OP_KEEP);
876 }
877
878 static bool
879 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
880 {
881 return pCreateInfo->stencilTestEnable &&
882 (radv_writes_stencil(&pCreateInfo->front) ||
883 radv_writes_stencil(&pCreateInfo->back));
884 }
885
886 static bool
887 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
888 {
889 return radv_is_depth_write_enabled(pCreateInfo) ||
890 radv_is_stencil_write_enabled(pCreateInfo);
891 }
892
893 static bool
894 radv_order_invariant_stencil_op(VkStencilOp op)
895 {
896 /* REPLACE is normally order invariant, except when the stencil
897 * reference value is written by the fragment shader. Tracking this
898 * interaction does not seem worth the effort, so be conservative.
899 */
900 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
901 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
902 op != VK_STENCIL_OP_REPLACE;
903 }
904
905 static bool
906 radv_order_invariant_stencil_state(const VkStencilOpState *state)
907 {
908 /* Compute whether, assuming Z writes are disabled, this stencil state
909 * is order invariant in the sense that the set of passing fragments as
910 * well as the final stencil buffer result does not depend on the order
911 * of fragments.
912 */
913 return !state->writeMask ||
914 /* The following assumes that Z writes are disabled. */
915 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
916 radv_order_invariant_stencil_op(state->passOp) &&
917 radv_order_invariant_stencil_op(state->depthFailOp)) ||
918 (state->compareOp == VK_COMPARE_OP_NEVER &&
919 radv_order_invariant_stencil_op(state->failOp));
920 }
921
922 static bool
923 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
924 {
925 VkDynamicState ds_states[] = {
926 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
927 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
928 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
929 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
930 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
931 };
932
933 if (pCreateInfo->pDynamicState) {
934 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
935 for (uint32_t i = 0; i < count; i++) {
936 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
937 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
938 return true;
939 }
940 }
941 }
942
943 return false;
944 }
945
946 static bool
947 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
948 struct radv_blend_state *blend,
949 const VkGraphicsPipelineCreateInfo *pCreateInfo)
950 {
951 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
952 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
953 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
954 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
955 unsigned colormask = blend->cb_target_enabled_4bit;
956
957 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
958 return false;
959
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask && vkblend && vkblend->logicOpEnable)
962 return false;
963
964 /* Be conservative if an extended dynamic depth/stencil state is
965 * enabled because the driver can't update out-of-order rasterization
966 * dynamically.
967 */
968 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
969 return false;
970
971 /* Default depth/stencil invariance when no attachment is bound. */
972 struct radv_dsa_order_invariance dsa_order_invariant = {
973 .zs = true, .pass_set = true
974 };
975
976 if (vkds) {
977 struct radv_render_pass_attachment *attachment =
978 pass->attachments + subpass->depth_stencil_attachment->attachment;
979 bool has_stencil = vk_format_is_stencil(attachment->format);
980 struct radv_dsa_order_invariance order_invariance[2];
981 struct radv_shader_variant *ps =
982 pipeline->shaders[MESA_SHADER_FRAGMENT];
983
984 /* Compute depth/stencil order invariance in order to know if
985 * it's safe to enable out-of-order.
986 */
987 bool zfunc_is_ordered =
988 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
989 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
990 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
991 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
992 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
993
994 bool nozwrite_and_order_invariant_stencil =
995 !radv_is_ds_write_enabled(vkds) ||
996 (!radv_is_depth_write_enabled(vkds) &&
997 radv_order_invariant_stencil_state(&vkds->front) &&
998 radv_order_invariant_stencil_state(&vkds->back));
999
1000 order_invariance[1].zs =
1001 nozwrite_and_order_invariant_stencil ||
1002 (!radv_is_stencil_write_enabled(vkds) &&
1003 zfunc_is_ordered);
1004 order_invariance[0].zs =
1005 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1006
1007 order_invariance[1].pass_set =
1008 nozwrite_and_order_invariant_stencil ||
1009 (!radv_is_stencil_write_enabled(vkds) &&
1010 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1011 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1012 order_invariance[0].pass_set =
1013 !radv_is_depth_write_enabled(vkds) ||
1014 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1015 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1016
1017 dsa_order_invariant = order_invariance[has_stencil];
1018 if (!dsa_order_invariant.zs)
1019 return false;
1020
1021 /* The set of PS invocations is always order invariant,
1022 * except when early Z/S tests are requested.
1023 */
1024 if (ps &&
1025 ps->info.ps.writes_memory &&
1026 ps->info.ps.early_fragment_test &&
1027 !dsa_order_invariant.pass_set)
1028 return false;
1029
1030 /* Determine if out-of-order rasterization should be disabled
1031 * when occlusion queries are used.
1032 */
1033 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1034 !dsa_order_invariant.pass_set;
1035 }
1036
1037 /* No color buffers are enabled for writing. */
1038 if (!colormask)
1039 return true;
1040
1041 unsigned blendmask = colormask & blend->blend_enable_4bit;
1042
1043 if (blendmask) {
1044 /* Only commutative blending. */
1045 if (blendmask & ~blend->commutative_4bit)
1046 return false;
1047
1048 if (!dsa_order_invariant.pass_set)
1049 return false;
1050 }
1051
1052 if (colormask & ~blendmask)
1053 return false;
1054
1055 return true;
1056 }
1057
1058 static void
1059 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1060 struct radv_blend_state *blend,
1061 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1062 {
1063 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1064 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1065 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1066 bool out_of_order_rast = false;
1067 int ps_iter_samples = 1;
1068 uint32_t mask = 0xffff;
1069
1070 if (vkms) {
1071 ms->num_samples = vkms->rasterizationSamples;
1072
1073 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1074 *
1075 * "Sample shading is enabled for a graphics pipeline:
1076 *
1077 * - If the interface of the fragment shader entry point of the
1078 * graphics pipeline includes an input variable decorated
1079 * with SampleId or SamplePosition. In this case
1080 * minSampleShadingFactor takes the value 1.0.
1081 * - Else if the sampleShadingEnable member of the
1082 * VkPipelineMultisampleStateCreateInfo structure specified
1083 * when creating the graphics pipeline is set to VK_TRUE. In
1084 * this case minSampleShadingFactor takes the value of
1085 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1086 *
1087 * Otherwise, sample shading is considered disabled."
1088 */
1089 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1090 ps_iter_samples = ms->num_samples;
1091 } else {
1092 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1093 }
1094 } else {
1095 ms->num_samples = 1;
1096 }
1097
1098 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1099 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1100 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1101 /* Out-of-order rasterization is explicitly enabled by the
1102 * application.
1103 */
1104 out_of_order_rast = true;
1105 } else {
1106 /* Determine if the driver can enable out-of-order
1107 * rasterization internally.
1108 */
1109 out_of_order_rast =
1110 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1111 }
1112
1113 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1114 ms->pa_sc_aa_config = 0;
1115 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1116 S_028804_INCOHERENT_EQAA_READS(1) |
1117 S_028804_INTERPOLATE_COMP_Z(1) |
1118 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1119 ms->pa_sc_mode_cntl_1 =
1120 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1121 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1122 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1123 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1124 /* always 1: */
1125 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1126 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1127 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1128 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1129 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1130 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1131 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1132 S_028A48_VPORT_SCISSOR_ENABLE(1);
1133
1134 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1135 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1136 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1137 if (rast_line) {
1138 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1139 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1140 /* From the Vulkan spec 1.1.129:
1141 *
1142 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1143 * are being rasterized, sample locations may all be
1144 * treated as being at the pixel center (this may
1145 * affect attribute and depth interpolation)."
1146 */
1147 ms->num_samples = 1;
1148 }
1149 }
1150
1151 if (ms->num_samples > 1) {
1152 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1153 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1154 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1155 unsigned log_samples = util_logbase2(ms->num_samples);
1156 unsigned log_z_samples = util_logbase2(z_samples);
1157 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1158 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1159 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1160 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1161 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1162 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1163 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1164 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1165 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1166 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1167 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1168 if (ps_iter_samples > 1)
1169 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1170 }
1171
1172 if (vkms && vkms->pSampleMask) {
1173 mask = vkms->pSampleMask[0] & 0xffff;
1174 }
1175
1176 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1177 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1178 }
1179
1180 static bool
1181 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1182 {
1183 switch (topology) {
1184 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1189 return false;
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1195 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1196 return true;
1197 default:
1198 unreachable("unhandled primitive type");
1199 }
1200 }
1201
1202 static uint32_t
1203 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1204 {
1205 switch (gl_prim) {
1206 case 0: /* GL_POINTS */
1207 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1208 case 1: /* GL_LINES */
1209 case 3: /* GL_LINE_STRIP */
1210 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1211 case 0x8E7A: /* GL_ISOLINES */
1212 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1213
1214 case 4: /* GL_TRIANGLES */
1215 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1216 case 5: /* GL_TRIANGLE_STRIP */
1217 case 7: /* GL_QUADS */
1218 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1219 default:
1220 assert(0);
1221 return 0;
1222 }
1223 }
1224
1225 static uint32_t
1226 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1227 {
1228 switch (topology) {
1229 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1230 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1231 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1234 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1235 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1236 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1240 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1241 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1242 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1243 default:
1244 assert(0);
1245 return 0;
1246 }
1247 }
1248
1249 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1250 {
1251 switch(state) {
1252 case VK_DYNAMIC_STATE_VIEWPORT:
1253 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1254 return RADV_DYNAMIC_VIEWPORT;
1255 case VK_DYNAMIC_STATE_SCISSOR:
1256 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1257 return RADV_DYNAMIC_SCISSOR;
1258 case VK_DYNAMIC_STATE_LINE_WIDTH:
1259 return RADV_DYNAMIC_LINE_WIDTH;
1260 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1261 return RADV_DYNAMIC_DEPTH_BIAS;
1262 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1263 return RADV_DYNAMIC_BLEND_CONSTANTS;
1264 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1265 return RADV_DYNAMIC_DEPTH_BOUNDS;
1266 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1267 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1268 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1269 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1270 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1271 return RADV_DYNAMIC_STENCIL_REFERENCE;
1272 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1273 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1274 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1275 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1276 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1277 return RADV_DYNAMIC_LINE_STIPPLE;
1278 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1279 return RADV_DYNAMIC_CULL_MODE;
1280 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1281 return RADV_DYNAMIC_FRONT_FACE;
1282 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1283 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1284 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1285 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1286 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1287 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1288 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1289 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1290 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1291 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1292 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1293 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1294 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1295 return RADV_DYNAMIC_STENCIL_OP;
1296 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1297 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1298 default:
1299 unreachable("Unhandled dynamic state");
1300 }
1301 }
1302
1303 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1304 {
1305 uint32_t states = RADV_DYNAMIC_ALL;
1306
1307 /* If rasterization is disabled we do not care about any of the
1308 * dynamic states, since they are all rasterization related only,
1309 * except primitive topology and vertex binding stride.
1310 */
1311 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1312 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1313 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1314
1315 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1316 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1317
1318 if (!pCreateInfo->pDepthStencilState ||
1319 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1320 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1321
1322 if (!pCreateInfo->pDepthStencilState ||
1323 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1324 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1325 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1326 RADV_DYNAMIC_STENCIL_REFERENCE);
1327
1328 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1329 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1330
1331 if (!pCreateInfo->pMultisampleState ||
1332 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1333 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1334 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1335
1336 if (!pCreateInfo->pRasterizationState ||
1337 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1338 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1339 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1340
1341 /* TODO: blend constants & line width. */
1342
1343 return states;
1344 }
1345
1346
1347 static void
1348 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1349 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1350 const struct radv_graphics_pipeline_create_info *extra)
1351 {
1352 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1353 uint32_t states = needed_states;
1354 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1355 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1356
1357 pipeline->dynamic_state = default_dynamic_state;
1358 pipeline->graphics.needed_dynamic_state = needed_states;
1359
1360 if (pCreateInfo->pDynamicState) {
1361 /* Remove all of the states that are marked as dynamic */
1362 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1363 for (uint32_t s = 0; s < count; s++)
1364 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1365 }
1366
1367 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1368
1369 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1370 assert(pCreateInfo->pViewportState);
1371
1372 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1373 if (states & RADV_DYNAMIC_VIEWPORT) {
1374 typed_memcpy(dynamic->viewport.viewports,
1375 pCreateInfo->pViewportState->pViewports,
1376 pCreateInfo->pViewportState->viewportCount);
1377 }
1378 }
1379
1380 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1381 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1382 if (states & RADV_DYNAMIC_SCISSOR) {
1383 typed_memcpy(dynamic->scissor.scissors,
1384 pCreateInfo->pViewportState->pScissors,
1385 pCreateInfo->pViewportState->scissorCount);
1386 }
1387 }
1388
1389 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1390 assert(pCreateInfo->pRasterizationState);
1391 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1392 }
1393
1394 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1395 assert(pCreateInfo->pRasterizationState);
1396 dynamic->depth_bias.bias =
1397 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1398 dynamic->depth_bias.clamp =
1399 pCreateInfo->pRasterizationState->depthBiasClamp;
1400 dynamic->depth_bias.slope =
1401 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1402 }
1403
1404 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1405 *
1406 * pColorBlendState is [...] NULL if the pipeline has rasterization
1407 * disabled or if the subpass of the render pass the pipeline is
1408 * created against does not use any color attachments.
1409 */
1410 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1411 assert(pCreateInfo->pColorBlendState);
1412 typed_memcpy(dynamic->blend_constants,
1413 pCreateInfo->pColorBlendState->blendConstants, 4);
1414 }
1415
1416 if (states & RADV_DYNAMIC_CULL_MODE) {
1417 dynamic->cull_mode =
1418 pCreateInfo->pRasterizationState->cullMode;
1419 }
1420
1421 if (states & RADV_DYNAMIC_FRONT_FACE) {
1422 dynamic->front_face =
1423 pCreateInfo->pRasterizationState->frontFace;
1424 }
1425
1426 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1427 dynamic->primitive_topology =
1428 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1429 if (extra && extra->use_rectlist) {
1430 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1431 }
1432 }
1433
1434 /* If there is no depthstencil attachment, then don't read
1435 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1436 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1437 * no need to override the depthstencil defaults in
1438 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1439 *
1440 * Section 9.2 of the Vulkan 1.0.15 spec says:
1441 *
1442 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1443 * disabled or if the subpass of the render pass the pipeline is created
1444 * against does not use a depth/stencil attachment.
1445 */
1446 if (needed_states && subpass->depth_stencil_attachment) {
1447 assert(pCreateInfo->pDepthStencilState);
1448
1449 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1450 dynamic->depth_bounds.min =
1451 pCreateInfo->pDepthStencilState->minDepthBounds;
1452 dynamic->depth_bounds.max =
1453 pCreateInfo->pDepthStencilState->maxDepthBounds;
1454 }
1455
1456 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1457 dynamic->stencil_compare_mask.front =
1458 pCreateInfo->pDepthStencilState->front.compareMask;
1459 dynamic->stencil_compare_mask.back =
1460 pCreateInfo->pDepthStencilState->back.compareMask;
1461 }
1462
1463 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1464 dynamic->stencil_write_mask.front =
1465 pCreateInfo->pDepthStencilState->front.writeMask;
1466 dynamic->stencil_write_mask.back =
1467 pCreateInfo->pDepthStencilState->back.writeMask;
1468 }
1469
1470 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1471 dynamic->stencil_reference.front =
1472 pCreateInfo->pDepthStencilState->front.reference;
1473 dynamic->stencil_reference.back =
1474 pCreateInfo->pDepthStencilState->back.reference;
1475 }
1476
1477 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1478 dynamic->depth_test_enable =
1479 pCreateInfo->pDepthStencilState->depthTestEnable;
1480 }
1481
1482 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1483 dynamic->depth_write_enable =
1484 pCreateInfo->pDepthStencilState->depthWriteEnable;
1485 }
1486
1487 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1488 dynamic->depth_compare_op =
1489 pCreateInfo->pDepthStencilState->depthCompareOp;
1490 }
1491
1492 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1493 dynamic->depth_bounds_test_enable =
1494 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1495 }
1496
1497 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1498 dynamic->stencil_test_enable =
1499 pCreateInfo->pDepthStencilState->stencilTestEnable;
1500 }
1501
1502 if (states & RADV_DYNAMIC_STENCIL_OP) {
1503 dynamic->stencil_op.front.compare_op =
1504 pCreateInfo->pDepthStencilState->front.compareOp;
1505 dynamic->stencil_op.front.fail_op =
1506 pCreateInfo->pDepthStencilState->front.failOp;
1507 dynamic->stencil_op.front.pass_op =
1508 pCreateInfo->pDepthStencilState->front.passOp;
1509 dynamic->stencil_op.front.depth_fail_op =
1510 pCreateInfo->pDepthStencilState->front.depthFailOp;
1511
1512 dynamic->stencil_op.back.compare_op =
1513 pCreateInfo->pDepthStencilState->back.compareOp;
1514 dynamic->stencil_op.back.fail_op =
1515 pCreateInfo->pDepthStencilState->back.failOp;
1516 dynamic->stencil_op.back.pass_op =
1517 pCreateInfo->pDepthStencilState->back.passOp;
1518 dynamic->stencil_op.back.depth_fail_op =
1519 pCreateInfo->pDepthStencilState->back.depthFailOp;
1520 }
1521 }
1522
1523 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1524 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1525 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1526 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1527 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1528 typed_memcpy(dynamic->discard_rectangle.rectangles,
1529 discard_rectangle_info->pDiscardRectangles,
1530 discard_rectangle_info->discardRectangleCount);
1531 }
1532 }
1533
1534 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1535 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1536 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1537 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1538 /* If sampleLocationsEnable is VK_FALSE, the default sample
1539 * locations are used and the values specified in
1540 * sampleLocationsInfo are ignored.
1541 */
1542 if (sample_location_info->sampleLocationsEnable) {
1543 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1544 &sample_location_info->sampleLocationsInfo;
1545
1546 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1547
1548 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1549 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1550 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1551 typed_memcpy(&dynamic->sample_location.locations[0],
1552 pSampleLocationsInfo->pSampleLocations,
1553 pSampleLocationsInfo->sampleLocationsCount);
1554 }
1555 }
1556
1557 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1558 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1559 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1560 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1561 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1562 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1563 }
1564
1565 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1566 pipeline->graphics.uses_dynamic_stride = true;
1567
1568 pipeline->dynamic_state.mask = states;
1569 }
1570
1571 static void
1572 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1573 const struct radv_pipeline *pipeline,
1574 nir_shader **nir,
1575 struct radv_shader_info *infos,
1576 struct gfx9_gs_info *out)
1577 {
1578 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1579 struct radv_es_output_info *es_info;
1580 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1581 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1582 else
1583 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1584 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1585 &infos[MESA_SHADER_VERTEX].vs.es_info;
1586
1587 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1588 bool uses_adjacency;
1589 switch(key->topology) {
1590 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1591 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1592 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1593 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1594 uses_adjacency = true;
1595 break;
1596 default:
1597 uses_adjacency = false;
1598 break;
1599 }
1600
1601 /* All these are in dwords: */
1602 /* We can't allow using the whole LDS, because GS waves compete with
1603 * other shader stages for LDS space. */
1604 const unsigned max_lds_size = 8 * 1024;
1605 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1606 unsigned esgs_lds_size;
1607
1608 /* All these are per subgroup: */
1609 const unsigned max_out_prims = 32 * 1024;
1610 const unsigned max_es_verts = 255;
1611 const unsigned ideal_gs_prims = 64;
1612 unsigned max_gs_prims, gs_prims;
1613 unsigned min_es_verts, es_verts, worst_case_es_verts;
1614
1615 if (uses_adjacency || gs_num_invocations > 1)
1616 max_gs_prims = 127 / gs_num_invocations;
1617 else
1618 max_gs_prims = 255;
1619
1620 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1621 * Make sure we don't go over the maximum value.
1622 */
1623 if (gs_info->gs.vertices_out > 0) {
1624 max_gs_prims = MIN2(max_gs_prims,
1625 max_out_prims /
1626 (gs_info->gs.vertices_out * gs_num_invocations));
1627 }
1628 assert(max_gs_prims > 0);
1629
1630 /* If the primitive has adjacency, halve the number of vertices
1631 * that will be reused in multiple primitives.
1632 */
1633 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1634
1635 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1636 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1637
1638 /* Compute ESGS LDS size based on the worst case number of ES vertices
1639 * needed to create the target number of GS prims per subgroup.
1640 */
1641 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1642
1643 /* If total LDS usage is too big, refactor partitions based on ratio
1644 * of ESGS item sizes.
1645 */
1646 if (esgs_lds_size > max_lds_size) {
1647 /* Our target GS Prims Per Subgroup was too large. Calculate
1648 * the maximum number of GS Prims Per Subgroup that will fit
1649 * into LDS, capped by the maximum that the hardware can support.
1650 */
1651 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1652 max_gs_prims);
1653 assert(gs_prims > 0);
1654 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1655 max_es_verts);
1656
1657 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1658 assert(esgs_lds_size <= max_lds_size);
1659 }
1660
1661 /* Now calculate remaining ESGS information. */
1662 if (esgs_lds_size)
1663 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1664 else
1665 es_verts = max_es_verts;
1666
1667 /* Vertices for adjacency primitives are not always reused, so restore
1668 * it for ES_VERTS_PER_SUBGRP.
1669 */
1670 min_es_verts = gs_info->gs.vertices_in;
1671
1672 /* For normal primitives, the VGT only checks if they are past the ES
1673 * verts per subgroup after allocating a full GS primitive and if they
1674 * are, kick off a new subgroup. But if those additional ES verts are
1675 * unique (e.g. not reused) we need to make sure there is enough LDS
1676 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1677 */
1678 es_verts -= min_es_verts - 1;
1679
1680 uint32_t es_verts_per_subgroup = es_verts;
1681 uint32_t gs_prims_per_subgroup = gs_prims;
1682 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1683 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1684 out->lds_size = align(esgs_lds_size, 128) / 128;
1685 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1686 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1687 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1688 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1689 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1690 assert(max_prims_per_subgroup <= max_out_prims);
1691 }
1692
1693 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1694 unsigned min_verts_per_prim, bool use_adjacency)
1695 {
1696 unsigned max_reuse = max_esverts - min_verts_per_prim;
1697 if (use_adjacency)
1698 max_reuse /= 2;
1699 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1700 }
1701
1702 static unsigned
1703 radv_get_num_input_vertices(nir_shader **nir)
1704 {
1705 if (nir[MESA_SHADER_GEOMETRY]) {
1706 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1707
1708 return gs->info.gs.vertices_in;
1709 }
1710
1711 if (nir[MESA_SHADER_TESS_CTRL]) {
1712 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1713
1714 if (tes->info.tess.point_mode)
1715 return 1;
1716 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1717 return 2;
1718 return 3;
1719 }
1720
1721 return 3;
1722 }
1723
1724 static void
1725 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1726 struct radv_pipeline *pipeline,
1727 nir_shader **nir,
1728 struct radv_shader_info *infos,
1729 struct gfx10_ngg_info *ngg)
1730 {
1731 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1732 struct radv_es_output_info *es_info =
1733 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1734 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1735 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1736 unsigned min_verts_per_prim =
1737 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1738 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1739 bool uses_adjacency;
1740 switch(key->topology) {
1741 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1742 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1743 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1744 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1745 uses_adjacency = true;
1746 break;
1747 default:
1748 uses_adjacency = false;
1749 break;
1750 }
1751
1752 /* All these are in dwords: */
1753 /* We can't allow using the whole LDS, because GS waves compete with
1754 * other shader stages for LDS space.
1755 *
1756 * TODO: We should really take the shader's internal LDS use into
1757 * account. The linker will fail if the size is greater than
1758 * 8K dwords.
1759 */
1760 const unsigned max_lds_size = 8 * 1024 - 768;
1761 const unsigned target_lds_size = max_lds_size;
1762 unsigned esvert_lds_size = 0;
1763 unsigned gsprim_lds_size = 0;
1764
1765 /* All these are per subgroup: */
1766 bool max_vert_out_per_gs_instance = false;
1767 unsigned max_esverts_base = 256;
1768 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1769
1770 /* Hardware has the following non-natural restrictions on the value
1771 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1772 * the draw:
1773 * - at most 252 for any line input primitive type
1774 * - at most 251 for any quad input primitive type
1775 * - at most 251 for triangle strips with adjacency (this happens to
1776 * be the natural limit for triangle *lists* with adjacency)
1777 */
1778 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1779
1780 if (gs_type == MESA_SHADER_GEOMETRY) {
1781 unsigned max_out_verts_per_gsprim =
1782 gs_info->gs.vertices_out * gs_num_invocations;
1783
1784 if (max_out_verts_per_gsprim <= 256) {
1785 if (max_out_verts_per_gsprim) {
1786 max_gsprims_base = MIN2(max_gsprims_base,
1787 256 / max_out_verts_per_gsprim);
1788 }
1789 } else {
1790 /* Use special multi-cycling mode in which each GS
1791 * instance gets its own subgroup. Does not work with
1792 * tessellation. */
1793 max_vert_out_per_gs_instance = true;
1794 max_gsprims_base = 1;
1795 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1796 }
1797
1798 esvert_lds_size = es_info->esgs_itemsize / 4;
1799 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1800 } else {
1801 /* VS and TES. */
1802 /* LDS size for passing data from GS to ES. */
1803 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1804 ? &infos[MESA_SHADER_TESS_EVAL].so
1805 : &infos[MESA_SHADER_VERTEX].so;
1806
1807 if (so_info->num_outputs)
1808 esvert_lds_size = 4 * so_info->num_outputs + 1;
1809
1810 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1811 * corresponding to the ES thread of the provoking vertex. All
1812 * ES threads load and export PrimitiveID for their thread.
1813 */
1814 if (!nir[MESA_SHADER_TESS_CTRL] &&
1815 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1816 esvert_lds_size = MAX2(esvert_lds_size, 1);
1817 }
1818
1819 unsigned max_gsprims = max_gsprims_base;
1820 unsigned max_esverts = max_esverts_base;
1821
1822 if (esvert_lds_size)
1823 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1824 if (gsprim_lds_size)
1825 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1826
1827 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1828 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1829 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1830
1831 if (esvert_lds_size || gsprim_lds_size) {
1832 /* Now that we have a rough proportionality between esverts
1833 * and gsprims based on the primitive type, scale both of them
1834 * down simultaneously based on required LDS space.
1835 *
1836 * We could be smarter about this if we knew how much vertex
1837 * reuse to expect.
1838 */
1839 unsigned lds_total = max_esverts * esvert_lds_size +
1840 max_gsprims * gsprim_lds_size;
1841 if (lds_total > target_lds_size) {
1842 max_esverts = max_esverts * target_lds_size / lds_total;
1843 max_gsprims = max_gsprims * target_lds_size / lds_total;
1844
1845 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1846 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1847 min_verts_per_prim, uses_adjacency);
1848 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1849 }
1850 }
1851
1852 /* Round up towards full wave sizes for better ALU utilization. */
1853 if (!max_vert_out_per_gs_instance) {
1854 unsigned orig_max_esverts;
1855 unsigned orig_max_gsprims;
1856 unsigned wavesize;
1857
1858 if (gs_type == MESA_SHADER_GEOMETRY) {
1859 wavesize = gs_info->wave_size;
1860 } else {
1861 wavesize = nir[MESA_SHADER_TESS_CTRL]
1862 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1863 : infos[MESA_SHADER_VERTEX].wave_size;
1864 }
1865
1866 do {
1867 orig_max_esverts = max_esverts;
1868 orig_max_gsprims = max_gsprims;
1869
1870 max_esverts = align(max_esverts, wavesize);
1871 max_esverts = MIN2(max_esverts, max_esverts_base);
1872 if (esvert_lds_size)
1873 max_esverts = MIN2(max_esverts,
1874 (max_lds_size - max_gsprims * gsprim_lds_size) /
1875 esvert_lds_size);
1876 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1877
1878 max_gsprims = align(max_gsprims, wavesize);
1879 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1880 if (gsprim_lds_size)
1881 max_gsprims = MIN2(max_gsprims,
1882 (max_lds_size - max_esverts * esvert_lds_size) /
1883 gsprim_lds_size);
1884 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1885 min_verts_per_prim, uses_adjacency);
1886 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1887 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1888 }
1889
1890 /* Hardware restriction: minimum value of max_esverts */
1891 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1892
1893 unsigned max_out_vertices =
1894 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1895 gs_type == MESA_SHADER_GEOMETRY ?
1896 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1897 max_esverts;
1898 assert(max_out_vertices <= 256);
1899
1900 unsigned prim_amp_factor = 1;
1901 if (gs_type == MESA_SHADER_GEOMETRY) {
1902 /* Number of output primitives per GS input primitive after
1903 * GS instancing. */
1904 prim_amp_factor = gs_info->gs.vertices_out;
1905 }
1906
1907 /* The GE only checks against the maximum number of ES verts after
1908 * allocating a full GS primitive. So we need to ensure that whenever
1909 * this check passes, there is enough space for a full primitive without
1910 * vertex reuse.
1911 */
1912 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1913 ngg->max_gsprims = max_gsprims;
1914 ngg->max_out_verts = max_out_vertices;
1915 ngg->prim_amp_factor = prim_amp_factor;
1916 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1917 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1918 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1919
1920 if (gs_type == MESA_SHADER_GEOMETRY) {
1921 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1922 } else {
1923 ngg->vgt_esgs_ring_itemsize = 1;
1924 }
1925
1926 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1927
1928 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1929 }
1930
1931 static void
1932 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1933 const struct gfx9_gs_info *gs)
1934 {
1935 struct radv_device *device = pipeline->device;
1936 unsigned num_se = device->physical_device->rad_info.max_se;
1937 unsigned wave_size = 64;
1938 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1939 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1940 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1941 */
1942 unsigned gs_vertex_reuse =
1943 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1944 unsigned alignment = 256 * num_se;
1945 /* The maximum size is 63.999 MB per SE. */
1946 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1947 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1948
1949 /* Calculate the minimum size. */
1950 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1951 wave_size, alignment);
1952 /* These are recommended sizes, not minimum sizes. */
1953 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1954 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1955 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1956 gs_info->gs.max_gsvs_emit_size;
1957
1958 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1959 esgs_ring_size = align(esgs_ring_size, alignment);
1960 gsvs_ring_size = align(gsvs_ring_size, alignment);
1961
1962 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1963 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1964
1965 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1966 }
1967
1968 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1969 unsigned *lds_size)
1970 {
1971 /* If tessellation is all offchip and on-chip GS isn't used, this
1972 * workaround is not needed.
1973 */
1974 return;
1975
1976 /* SPI barrier management bug:
1977 * Make sure we have at least 4k of LDS in use to avoid the bug.
1978 * It applies to workgroup sizes of more than one wavefront.
1979 */
1980 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1981 device->physical_device->rad_info.family == CHIP_KABINI)
1982 *lds_size = MAX2(*lds_size, 8);
1983 }
1984
1985 struct radv_shader_variant *
1986 radv_get_shader(struct radv_pipeline *pipeline,
1987 gl_shader_stage stage)
1988 {
1989 if (stage == MESA_SHADER_VERTEX) {
1990 if (pipeline->shaders[MESA_SHADER_VERTEX])
1991 return pipeline->shaders[MESA_SHADER_VERTEX];
1992 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1993 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1994 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1995 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1996 } else if (stage == MESA_SHADER_TESS_EVAL) {
1997 if (!radv_pipeline_has_tess(pipeline))
1998 return NULL;
1999 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2000 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2001 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2002 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2003 }
2004 return pipeline->shaders[stage];
2005 }
2006
2007 static struct radv_tessellation_state
2008 calculate_tess_state(struct radv_pipeline *pipeline,
2009 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2010 {
2011 unsigned num_tcs_input_cp;
2012 unsigned num_tcs_output_cp;
2013 unsigned lds_size;
2014 unsigned num_patches;
2015 struct radv_tessellation_state tess = {0};
2016
2017 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
2018 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
2019 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2020
2021 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
2022
2023 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
2024 assert(lds_size <= 65536);
2025 lds_size = align(lds_size, 512) / 512;
2026 } else {
2027 assert(lds_size <= 32768);
2028 lds_size = align(lds_size, 256) / 256;
2029 }
2030 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
2031
2032 tess.lds_size = lds_size;
2033
2034 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
2035 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
2036 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
2037 tess.num_patches = num_patches;
2038
2039 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
2040 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
2041
2042 switch (tes->info.tes.primitive_mode) {
2043 case GL_TRIANGLES:
2044 type = V_028B6C_TESS_TRIANGLE;
2045 break;
2046 case GL_QUADS:
2047 type = V_028B6C_TESS_QUAD;
2048 break;
2049 case GL_ISOLINES:
2050 type = V_028B6C_TESS_ISOLINE;
2051 break;
2052 }
2053
2054 switch (tes->info.tes.spacing) {
2055 case TESS_SPACING_EQUAL:
2056 partitioning = V_028B6C_PART_INTEGER;
2057 break;
2058 case TESS_SPACING_FRACTIONAL_ODD:
2059 partitioning = V_028B6C_PART_FRAC_ODD;
2060 break;
2061 case TESS_SPACING_FRACTIONAL_EVEN:
2062 partitioning = V_028B6C_PART_FRAC_EVEN;
2063 break;
2064 default:
2065 break;
2066 }
2067
2068 bool ccw = tes->info.tes.ccw;
2069 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2070 vk_find_struct_const(pCreateInfo->pTessellationState,
2071 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2072
2073 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2074 ccw = !ccw;
2075
2076 if (tes->info.tes.point_mode)
2077 topology = V_028B6C_OUTPUT_POINT;
2078 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2079 topology = V_028B6C_OUTPUT_LINE;
2080 else if (ccw)
2081 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2082 else
2083 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2084
2085 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2086 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2087 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2088 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2089 else
2090 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2091 } else
2092 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2093
2094 tess.tf_param = S_028B6C_TYPE(type) |
2095 S_028B6C_PARTITIONING(partitioning) |
2096 S_028B6C_TOPOLOGY(topology) |
2097 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2098
2099 return tess;
2100 }
2101
2102 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2103 {
2104 if (radv_pipeline_has_gs(pipeline))
2105 if (radv_pipeline_has_ngg(pipeline))
2106 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2107 else
2108 return &pipeline->gs_copy_shader->info.vs.outinfo;
2109 else if (radv_pipeline_has_tess(pipeline))
2110 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2111 else
2112 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2113 }
2114
2115 static void
2116 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2117 {
2118 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2119 int shader_count = 0;
2120
2121 if(shaders[MESA_SHADER_FRAGMENT]) {
2122 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2123 }
2124 if(shaders[MESA_SHADER_GEOMETRY]) {
2125 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2126 }
2127 if(shaders[MESA_SHADER_TESS_EVAL]) {
2128 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2129 }
2130 if(shaders[MESA_SHADER_TESS_CTRL]) {
2131 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2132 }
2133 if(shaders[MESA_SHADER_VERTEX]) {
2134 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2135 }
2136
2137 if (shader_count > 1) {
2138 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2139 unsigned last = ordered_shaders[0]->info.stage;
2140
2141 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2142 ordered_shaders[1]->info.has_transform_feedback_varyings)
2143 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2144
2145 for (int i = 0; i < shader_count; ++i) {
2146 nir_variable_mode mask = 0;
2147
2148 if (ordered_shaders[i]->info.stage != first)
2149 mask = mask | nir_var_shader_in;
2150
2151 if (ordered_shaders[i]->info.stage != last)
2152 mask = mask | nir_var_shader_out;
2153
2154 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2155 radv_optimize_nir(ordered_shaders[i], false, false);
2156 }
2157 }
2158
2159 for (int i = 1; i < shader_count; ++i) {
2160 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2161 ordered_shaders[i - 1]);
2162
2163 if (nir_link_opt_varyings(ordered_shaders[i],
2164 ordered_shaders[i - 1]))
2165 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2166
2167 nir_remove_dead_variables(ordered_shaders[i],
2168 nir_var_shader_out, NULL);
2169 nir_remove_dead_variables(ordered_shaders[i - 1],
2170 nir_var_shader_in, NULL);
2171
2172 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2173 ordered_shaders[i - 1]);
2174
2175 nir_compact_varyings(ordered_shaders[i],
2176 ordered_shaders[i - 1], true);
2177
2178 if (progress) {
2179 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2180 ac_lower_indirect_derefs(ordered_shaders[i],
2181 pipeline->device->physical_device->rad_info.chip_class);
2182 }
2183 radv_optimize_nir(ordered_shaders[i], false, false);
2184
2185 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2186 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2187 pipeline->device->physical_device->rad_info.chip_class);
2188 }
2189 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2190 }
2191 }
2192 }
2193
2194 static void
2195 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2196 struct radv_shader_info infos[MESA_SHADER_STAGES])
2197 {
2198 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2199 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2200
2201 if (!has_tess && !has_gs)
2202 return;
2203
2204 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2205 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2206
2207 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2208 /* These are merged into the next stage */
2209 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2210 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2211 }
2212
2213 if (has_tess) {
2214 nir_linked_io_var_info vs2tcs =
2215 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2216 nir_linked_io_var_info tcs2tes =
2217 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2218
2219 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2220 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2221 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2222 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2223 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2224 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2225
2226 if (has_gs) {
2227 nir_linked_io_var_info tes2gs =
2228 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2229
2230 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2231 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2232 }
2233 } else if (has_gs) {
2234 nir_linked_io_var_info vs2gs =
2235 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2236
2237 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2238 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2239 }
2240 }
2241
2242 static uint32_t
2243 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2244 uint32_t attrib_binding)
2245 {
2246 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2247 const VkVertexInputBindingDescription *input_binding =
2248 &input_state->pVertexBindingDescriptions[i];
2249
2250 if (input_binding->binding == attrib_binding)
2251 return input_binding->stride;
2252 }
2253
2254 return 0;
2255 }
2256
2257 static struct radv_pipeline_key
2258 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2259 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2260 const struct radv_blend_state *blend,
2261 bool has_view_index)
2262 {
2263 const VkPipelineVertexInputStateCreateInfo *input_state =
2264 pCreateInfo->pVertexInputState;
2265 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2266 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2267
2268 struct radv_pipeline_key key;
2269 memset(&key, 0, sizeof(key));
2270
2271 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2272 key.optimisations_disabled = 1;
2273
2274 key.has_multiview_view_index = has_view_index;
2275
2276 uint32_t binding_input_rate = 0;
2277 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2278 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2279 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2280 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2281 binding_input_rate |= 1u << binding;
2282 instance_rate_divisors[binding] = 1;
2283 }
2284 }
2285 if (divisor_state) {
2286 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2287 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2288 divisor_state->pVertexBindingDivisors[i].divisor;
2289 }
2290 }
2291
2292 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2293 const VkVertexInputAttributeDescription *desc =
2294 &input_state->pVertexAttributeDescriptions[i];
2295 const struct vk_format_description *format_desc;
2296 unsigned location = desc->location;
2297 unsigned binding = desc->binding;
2298 unsigned num_format, data_format;
2299 int first_non_void;
2300
2301 if (binding_input_rate & (1u << binding)) {
2302 key.instance_rate_inputs |= 1u << location;
2303 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2304 }
2305
2306 format_desc = vk_format_description(desc->format);
2307 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2308
2309 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2310 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2311
2312 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2313 key.vertex_attribute_bindings[location] = desc->binding;
2314 key.vertex_attribute_offsets[location] = desc->offset;
2315 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2316
2317 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2318 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2319 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2320 uint64_t adjust;
2321 switch(format) {
2322 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2323 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2324 adjust = RADV_ALPHA_ADJUST_SNORM;
2325 break;
2326 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2327 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2328 adjust = RADV_ALPHA_ADJUST_SSCALED;
2329 break;
2330 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2331 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2332 adjust = RADV_ALPHA_ADJUST_SINT;
2333 break;
2334 default:
2335 adjust = 0;
2336 break;
2337 }
2338 key.vertex_alpha_adjust |= adjust << (2 * location);
2339 }
2340
2341 switch (desc->format) {
2342 case VK_FORMAT_B8G8R8A8_UNORM:
2343 case VK_FORMAT_B8G8R8A8_SNORM:
2344 case VK_FORMAT_B8G8R8A8_USCALED:
2345 case VK_FORMAT_B8G8R8A8_SSCALED:
2346 case VK_FORMAT_B8G8R8A8_UINT:
2347 case VK_FORMAT_B8G8R8A8_SINT:
2348 case VK_FORMAT_B8G8R8A8_SRGB:
2349 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2350 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2351 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2352 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2353 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2354 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2355 key.vertex_post_shuffle |= 1 << location;
2356 break;
2357 default:
2358 break;
2359 }
2360 }
2361
2362 const VkPipelineTessellationStateCreateInfo *tess =
2363 radv_pipeline_get_tessellation_state(pCreateInfo);
2364 if (tess)
2365 key.tess_input_vertices = tess->patchControlPoints;
2366
2367 const VkPipelineMultisampleStateCreateInfo *vkms =
2368 radv_pipeline_get_multisample_state(pCreateInfo);
2369 if (vkms && vkms->rasterizationSamples > 1) {
2370 uint32_t num_samples = vkms->rasterizationSamples;
2371 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2372 key.num_samples = num_samples;
2373 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2374 }
2375
2376 key.col_format = blend->spi_shader_col_format;
2377 key.is_dual_src = blend->mrt0_is_dual_src;
2378 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2379 key.is_int8 = blend->col_format_is_int8;
2380 key.is_int10 = blend->col_format_is_int10;
2381 }
2382
2383 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2384 key.topology = pCreateInfo->pInputAssemblyState->topology;
2385
2386 return key;
2387 }
2388
2389 static bool
2390 radv_nir_stage_uses_xfb(const nir_shader *nir)
2391 {
2392 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2393 bool uses_xfb = !!xfb;
2394
2395 ralloc_free(xfb);
2396 return uses_xfb;
2397 }
2398
2399 static void
2400 radv_fill_shader_keys(struct radv_device *device,
2401 struct radv_shader_variant_key *keys,
2402 const struct radv_pipeline_key *key,
2403 nir_shader **nir)
2404 {
2405 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2406 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2407 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2408 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2409 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2410 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2411 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2412 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2413 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2414 }
2415 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2416
2417 if (nir[MESA_SHADER_TESS_CTRL]) {
2418 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2419 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2420 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2421 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2422
2423 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2424 }
2425
2426 if (nir[MESA_SHADER_GEOMETRY]) {
2427 if (nir[MESA_SHADER_TESS_CTRL])
2428 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2429 else
2430 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2431 }
2432
2433 if (device->physical_device->use_ngg) {
2434 if (nir[MESA_SHADER_TESS_CTRL]) {
2435 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2436 } else {
2437 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2438 }
2439
2440 if (nir[MESA_SHADER_TESS_CTRL] &&
2441 nir[MESA_SHADER_GEOMETRY] &&
2442 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2443 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2444 /* Fallback to the legacy path if tessellation is
2445 * enabled with extreme geometry because
2446 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2447 * might hang.
2448 */
2449 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2450 }
2451
2452 if (!device->physical_device->use_ngg_gs) {
2453 if (nir[MESA_SHADER_GEOMETRY]) {
2454 if (nir[MESA_SHADER_TESS_CTRL])
2455 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2456 else
2457 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2458 }
2459 }
2460
2461 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2462
2463 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2464 if (nir[i])
2465 last_xfb_stage = i;
2466 }
2467
2468 bool uses_xfb = nir[last_xfb_stage] &&
2469 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2470
2471 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2472 if (nir[MESA_SHADER_TESS_CTRL])
2473 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2474 else
2475 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2476 }
2477
2478 /* Determine if the pipeline is eligible for the NGG passthrough
2479 * mode. It can't be enabled for geometry shaders, for NGG
2480 * streamout or for vertex shaders that export the primitive ID
2481 * (this is checked later because we don't have the info here.)
2482 */
2483 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2484 if (nir[MESA_SHADER_TESS_CTRL] &&
2485 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2486 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2487 } else if (nir[MESA_SHADER_VERTEX] &&
2488 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2489 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2490 }
2491 }
2492 }
2493
2494 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2495 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2496
2497 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2498 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2499 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2500 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2501 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2502 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2503
2504 if (nir[MESA_SHADER_COMPUTE]) {
2505 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2506 }
2507 }
2508
2509 static uint8_t
2510 radv_get_wave_size(struct radv_device *device,
2511 const VkPipelineShaderStageCreateInfo *pStage,
2512 gl_shader_stage stage,
2513 const struct radv_shader_variant_key *key)
2514 {
2515 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2516 return 64;
2517 else if (stage == MESA_SHADER_COMPUTE) {
2518 if (key->cs.subgroup_size) {
2519 /* Return the required subgroup size if specified. */
2520 return key->cs.subgroup_size;
2521 }
2522 return device->physical_device->cs_wave_size;
2523 }
2524 else if (stage == MESA_SHADER_FRAGMENT)
2525 return device->physical_device->ps_wave_size;
2526 else
2527 return device->physical_device->ge_wave_size;
2528 }
2529
2530 static uint8_t
2531 radv_get_ballot_bit_size(struct radv_device *device,
2532 const VkPipelineShaderStageCreateInfo *pStage,
2533 gl_shader_stage stage,
2534 const struct radv_shader_variant_key *key)
2535 {
2536 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2537 return key->cs.subgroup_size;
2538 return 64;
2539 }
2540
2541 static void
2542 radv_fill_shader_info(struct radv_pipeline *pipeline,
2543 const VkPipelineShaderStageCreateInfo **pStages,
2544 struct radv_shader_variant_key *keys,
2545 struct radv_shader_info *infos,
2546 nir_shader **nir)
2547 {
2548 unsigned active_stages = 0;
2549 unsigned filled_stages = 0;
2550
2551 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2552 if (nir[i])
2553 active_stages |= (1 << i);
2554 }
2555
2556 if (nir[MESA_SHADER_FRAGMENT]) {
2557 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2558 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2559 pipeline->layout,
2560 &keys[MESA_SHADER_FRAGMENT],
2561 &infos[MESA_SHADER_FRAGMENT],
2562 pipeline->device->physical_device->use_llvm);
2563
2564 /* TODO: These are no longer used as keys we should refactor this */
2565 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2566 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2567 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2568 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2569 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2570 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2571 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2572 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2573 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2574 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2575 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2576 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2577 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2578 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2579 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2580 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2581
2582 /* NGG passthrough mode can't be enabled for vertex shaders
2583 * that export the primitive ID.
2584 *
2585 * TODO: I should really refactor the keys logic.
2586 */
2587 if (nir[MESA_SHADER_VERTEX] &&
2588 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2589 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2590 }
2591
2592 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2593 }
2594
2595 if (nir[MESA_SHADER_TESS_CTRL]) {
2596 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2597 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2598 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2599 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2600 }
2601
2602 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2603 nir[MESA_SHADER_TESS_CTRL]) {
2604 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2605 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2606 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2607
2608 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2609
2610 for (int i = 0; i < 2; i++) {
2611 radv_nir_shader_info_pass(combined_nir[i],
2612 pipeline->layout, &key,
2613 &infos[MESA_SHADER_TESS_CTRL],
2614 pipeline->device->physical_device->use_llvm);
2615 }
2616
2617 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2618 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2619 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2620 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2621
2622 filled_stages |= (1 << MESA_SHADER_VERTEX);
2623 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2624 }
2625
2626 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2627 nir[MESA_SHADER_GEOMETRY]) {
2628 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2629 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2630
2631 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2632
2633 for (int i = 0; i < 2; i++) {
2634 radv_nir_shader_info_pass(combined_nir[i],
2635 pipeline->layout,
2636 &keys[pre_stage],
2637 &infos[MESA_SHADER_GEOMETRY],
2638 pipeline->device->physical_device->use_llvm);
2639 }
2640
2641 filled_stages |= (1 << pre_stage);
2642 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2643 }
2644
2645 active_stages ^= filled_stages;
2646 while (active_stages) {
2647 int i = u_bit_scan(&active_stages);
2648
2649 if (i == MESA_SHADER_TESS_CTRL) {
2650 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2651 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2652 }
2653
2654 if (i == MESA_SHADER_TESS_EVAL) {
2655 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2656 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2657 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2658 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2659 }
2660
2661 radv_nir_shader_info_init(&infos[i]);
2662 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2663 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2664 }
2665
2666 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2667 if (nir[i]) {
2668 infos[i].wave_size =
2669 radv_get_wave_size(pipeline->device, pStages[i],
2670 i, &keys[i]);
2671 infos[i].ballot_bit_size =
2672 radv_get_ballot_bit_size(pipeline->device,
2673 pStages[i], i,
2674 &keys[i]);
2675 }
2676 }
2677 }
2678
2679 static void
2680 merge_tess_info(struct shader_info *tes_info,
2681 const struct shader_info *tcs_info)
2682 {
2683 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2684 *
2685 * "PointMode. Controls generation of points rather than triangles
2686 * or lines. This functionality defaults to disabled, and is
2687 * enabled if either shader stage includes the execution mode.
2688 *
2689 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2690 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2691 * and OutputVertices, it says:
2692 *
2693 * "One mode must be set in at least one of the tessellation
2694 * shader stages."
2695 *
2696 * So, the fields can be set in either the TCS or TES, but they must
2697 * agree if set in both. Our backend looks at TES, so bitwise-or in
2698 * the values from the TCS.
2699 */
2700 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2701 tes_info->tess.tcs_vertices_out == 0 ||
2702 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2703 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2704
2705 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2706 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2707 tcs_info->tess.spacing == tes_info->tess.spacing);
2708 tes_info->tess.spacing |= tcs_info->tess.spacing;
2709
2710 assert(tcs_info->tess.primitive_mode == 0 ||
2711 tes_info->tess.primitive_mode == 0 ||
2712 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2713 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2714 tes_info->tess.ccw |= tcs_info->tess.ccw;
2715 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2716 }
2717
2718 static
2719 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2720 {
2721 if (!ext)
2722 return;
2723
2724 if (ext->pPipelineCreationFeedback) {
2725 ext->pPipelineCreationFeedback->flags = 0;
2726 ext->pPipelineCreationFeedback->duration = 0;
2727 }
2728
2729 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2730 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2731 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2732 }
2733 }
2734
2735 static
2736 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2737 {
2738 if (!feedback)
2739 return;
2740
2741 feedback->duration -= radv_get_current_time();
2742 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2743 }
2744
2745 static
2746 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2747 {
2748 if (!feedback)
2749 return;
2750
2751 feedback->duration += radv_get_current_time();
2752 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2753 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2754 }
2755
2756 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2757 struct radv_device *device,
2758 struct radv_pipeline_cache *cache,
2759 const struct radv_pipeline_key *key,
2760 const VkPipelineShaderStageCreateInfo **pStages,
2761 const VkPipelineCreateFlags flags,
2762 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2763 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2764 {
2765 struct radv_shader_module fs_m = {0};
2766 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2767 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2768 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2769 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2770 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2771 unsigned char hash[20], gs_copy_hash[20];
2772 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2773 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2774 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2775 device->keep_shader_info;
2776
2777 radv_start_feedback(pipeline_feedback);
2778
2779 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2780 if (pStages[i]) {
2781 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2782 if (modules[i]->nir)
2783 _mesa_sha1_compute(modules[i]->nir->info.name,
2784 strlen(modules[i]->nir->info.name),
2785 modules[i]->sha1);
2786
2787 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2788 }
2789 }
2790
2791 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2792 memcpy(gs_copy_hash, hash, 20);
2793 gs_copy_hash[0] ^= 1;
2794
2795 bool found_in_application_cache = true;
2796 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2797 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2798 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2799 &found_in_application_cache);
2800 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2801 }
2802
2803 if (!keep_executable_info && !keep_statistic_info &&
2804 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2805 &found_in_application_cache) &&
2806 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2807 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2808 return VK_SUCCESS;
2809 }
2810
2811 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2812 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2813 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2814 }
2815
2816 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2817 nir_builder fs_b;
2818 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2819 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2820 fs_m.nir = fs_b.shader;
2821 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2822 }
2823
2824 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2825 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2826 unsigned subgroup_size = 64, ballot_bit_size = 64;
2827
2828 if (!modules[i])
2829 continue;
2830
2831 radv_start_feedback(stage_feedbacks[i]);
2832
2833 if (key->compute_subgroup_size) {
2834 /* Only compute shaders currently support requiring a
2835 * specific subgroup size.
2836 */
2837 assert(i == MESA_SHADER_COMPUTE);
2838 subgroup_size = key->compute_subgroup_size;
2839 ballot_bit_size = key->compute_subgroup_size;
2840 }
2841
2842 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2843 stage ? stage->pName : "main", i,
2844 stage ? stage->pSpecializationInfo : NULL,
2845 flags, pipeline->layout,
2846 subgroup_size, ballot_bit_size);
2847
2848 /* We don't want to alter meta shaders IR directly so clone it
2849 * first.
2850 */
2851 if (nir[i]->info.name) {
2852 nir[i] = nir_shader_clone(NULL, nir[i]);
2853 }
2854
2855 radv_stop_feedback(stage_feedbacks[i], false);
2856 }
2857
2858 if (nir[MESA_SHADER_TESS_CTRL]) {
2859 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2860 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2861 }
2862
2863 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2864 radv_link_shaders(pipeline, nir);
2865
2866 radv_set_linked_driver_locations(pipeline, nir, infos);
2867
2868 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2869 if (nir[i]) {
2870 /* do this again since information such as outputs_read can be out-of-date */
2871 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2872
2873 if (device->physical_device->use_llvm) {
2874 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2875 } else {
2876 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2877 nir_lower_non_uniform_ubo_access |
2878 nir_lower_non_uniform_ssbo_access |
2879 nir_lower_non_uniform_texture_access |
2880 nir_lower_non_uniform_image_access);
2881 }
2882 }
2883 }
2884
2885 if (nir[MESA_SHADER_FRAGMENT])
2886 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2887
2888 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2889 if (radv_can_dump_shader(device, modules[i], false))
2890 nir_print_shader(nir[i], stderr);
2891 }
2892
2893 radv_fill_shader_keys(device, keys, key, nir);
2894
2895 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2896
2897 if ((nir[MESA_SHADER_VERTEX] &&
2898 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2899 (nir[MESA_SHADER_TESS_EVAL] &&
2900 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2901 struct gfx10_ngg_info *ngg_info;
2902
2903 if (nir[MESA_SHADER_GEOMETRY])
2904 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2905 else if (nir[MESA_SHADER_TESS_CTRL])
2906 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2907 else
2908 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2909
2910 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2911 } else if (nir[MESA_SHADER_GEOMETRY]) {
2912 struct gfx9_gs_info *gs_info =
2913 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2914
2915 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2916 }
2917
2918 if(modules[MESA_SHADER_GEOMETRY]) {
2919 struct radv_shader_binary *gs_copy_binary = NULL;
2920 if (!pipeline->gs_copy_shader &&
2921 !radv_pipeline_has_ngg(pipeline)) {
2922 struct radv_shader_info info = {};
2923 struct radv_shader_variant_key key = {};
2924
2925 key.has_multiview_view_index =
2926 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2927
2928 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2929 pipeline->layout, &key,
2930 &info, pipeline->device->physical_device->use_llvm);
2931 info.wave_size = 64; /* Wave32 not supported. */
2932 info.ballot_bit_size = 64;
2933
2934 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2935 device, nir[MESA_SHADER_GEOMETRY], &info,
2936 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2937 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2938 }
2939
2940 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2941 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2942 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2943
2944 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2945 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2946
2947 radv_pipeline_cache_insert_shaders(device, cache,
2948 gs_copy_hash,
2949 variants,
2950 binaries);
2951 }
2952 free(gs_copy_binary);
2953 }
2954
2955 if (nir[MESA_SHADER_FRAGMENT]) {
2956 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2957 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2958
2959 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2960 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2961 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2962 infos + MESA_SHADER_FRAGMENT,
2963 keep_executable_info, keep_statistic_info,
2964 &binaries[MESA_SHADER_FRAGMENT]);
2965
2966 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2967 }
2968 }
2969
2970 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2971 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2972 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2973 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2974 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2975
2976 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2977
2978 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2979 pipeline->layout,
2980 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2981 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2982
2983 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2984 }
2985 modules[MESA_SHADER_VERTEX] = NULL;
2986 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2987 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2988 }
2989
2990 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2991 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2992 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2993 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2994
2995 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2996
2997 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2998 pipeline->layout,
2999 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
3000 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
3001
3002 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
3003 }
3004 modules[pre_stage] = NULL;
3005 }
3006
3007 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3008 if(modules[i] && !pipeline->shaders[i]) {
3009 if (i == MESA_SHADER_TESS_CTRL) {
3010 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
3011 }
3012 if (i == MESA_SHADER_TESS_EVAL) {
3013 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
3014 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
3015 }
3016
3017 radv_start_feedback(stage_feedbacks[i]);
3018
3019 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
3020 pipeline->layout,
3021 keys + i, infos + i, keep_executable_info,
3022 keep_statistic_info, &binaries[i]);
3023
3024 radv_stop_feedback(stage_feedbacks[i], false);
3025 }
3026 }
3027
3028 if (!keep_executable_info && !keep_statistic_info) {
3029 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3030 binaries);
3031 }
3032
3033 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3034 free(binaries[i]);
3035 if (nir[i]) {
3036 ralloc_free(nir[i]);
3037
3038 if (radv_can_dump_shader_stats(device, modules[i]))
3039 radv_shader_dump_stats(device,
3040 pipeline->shaders[i],
3041 i, stderr);
3042 }
3043 }
3044
3045 if (fs_m.nir)
3046 ralloc_free(fs_m.nir);
3047
3048 radv_stop_feedback(pipeline_feedback, false);
3049 return VK_SUCCESS;
3050 }
3051
3052 static uint32_t
3053 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3054 gl_shader_stage stage, enum chip_class chip_class)
3055 {
3056 bool has_gs = radv_pipeline_has_gs(pipeline);
3057 bool has_tess = radv_pipeline_has_tess(pipeline);
3058 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3059
3060 switch (stage) {
3061 case MESA_SHADER_FRAGMENT:
3062 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3063 case MESA_SHADER_VERTEX:
3064 if (has_tess) {
3065 if (chip_class >= GFX10) {
3066 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3067 } else if (chip_class == GFX9) {
3068 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3069 } else {
3070 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3071 }
3072
3073 }
3074
3075 if (has_gs) {
3076 if (chip_class >= GFX10) {
3077 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3078 } else {
3079 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3080 }
3081 }
3082
3083 if (has_ngg)
3084 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3085
3086 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3087 case MESA_SHADER_GEOMETRY:
3088 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3089 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3090 case MESA_SHADER_COMPUTE:
3091 return R_00B900_COMPUTE_USER_DATA_0;
3092 case MESA_SHADER_TESS_CTRL:
3093 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3094 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3095 case MESA_SHADER_TESS_EVAL:
3096 if (has_gs) {
3097 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3098 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3099 } else if (has_ngg) {
3100 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3101 } else {
3102 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3103 }
3104 default:
3105 unreachable("unknown shader");
3106 }
3107 }
3108
3109 struct radv_bin_size_entry {
3110 unsigned bpp;
3111 VkExtent2D extent;
3112 };
3113
3114 static VkExtent2D
3115 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3116 {
3117 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3118 {
3119 /* One RB / SE */
3120 {
3121 /* One shader engine */
3122 { 0, {128, 128}},
3123 { 1, { 64, 128}},
3124 { 2, { 32, 128}},
3125 { 3, { 16, 128}},
3126 { 17, { 0, 0}},
3127 { UINT_MAX, { 0, 0}},
3128 },
3129 {
3130 /* Two shader engines */
3131 { 0, {128, 128}},
3132 { 2, { 64, 128}},
3133 { 3, { 32, 128}},
3134 { 5, { 16, 128}},
3135 { 17, { 0, 0}},
3136 { UINT_MAX, { 0, 0}},
3137 },
3138 {
3139 /* Four shader engines */
3140 { 0, {128, 128}},
3141 { 3, { 64, 128}},
3142 { 5, { 16, 128}},
3143 { 17, { 0, 0}},
3144 { UINT_MAX, { 0, 0}},
3145 },
3146 },
3147 {
3148 /* Two RB / SE */
3149 {
3150 /* One shader engine */
3151 { 0, {128, 128}},
3152 { 2, { 64, 128}},
3153 { 3, { 32, 128}},
3154 { 5, { 16, 128}},
3155 { 33, { 0, 0}},
3156 { UINT_MAX, { 0, 0}},
3157 },
3158 {
3159 /* Two shader engines */
3160 { 0, {128, 128}},
3161 { 3, { 64, 128}},
3162 { 5, { 32, 128}},
3163 { 9, { 16, 128}},
3164 { 33, { 0, 0}},
3165 { UINT_MAX, { 0, 0}},
3166 },
3167 {
3168 /* Four shader engines */
3169 { 0, {256, 256}},
3170 { 2, {128, 256}},
3171 { 3, {128, 128}},
3172 { 5, { 64, 128}},
3173 { 9, { 16, 128}},
3174 { 33, { 0, 0}},
3175 { UINT_MAX, { 0, 0}},
3176 },
3177 },
3178 {
3179 /* Four RB / SE */
3180 {
3181 /* One shader engine */
3182 { 0, {128, 256}},
3183 { 2, {128, 128}},
3184 { 3, { 64, 128}},
3185 { 5, { 32, 128}},
3186 { 9, { 16, 128}},
3187 { 33, { 0, 0}},
3188 { UINT_MAX, { 0, 0}},
3189 },
3190 {
3191 /* Two shader engines */
3192 { 0, {256, 256}},
3193 { 2, {128, 256}},
3194 { 3, {128, 128}},
3195 { 5, { 64, 128}},
3196 { 9, { 32, 128}},
3197 { 17, { 16, 128}},
3198 { 33, { 0, 0}},
3199 { UINT_MAX, { 0, 0}},
3200 },
3201 {
3202 /* Four shader engines */
3203 { 0, {256, 512}},
3204 { 2, {256, 256}},
3205 { 3, {128, 256}},
3206 { 5, {128, 128}},
3207 { 9, { 64, 128}},
3208 { 17, { 16, 128}},
3209 { 33, { 0, 0}},
3210 { UINT_MAX, { 0, 0}},
3211 },
3212 },
3213 };
3214 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3215 {
3216 // One RB / SE
3217 {
3218 // One shader engine
3219 { 0, {128, 256}},
3220 { 2, {128, 128}},
3221 { 4, { 64, 128}},
3222 { 7, { 32, 128}},
3223 { 13, { 16, 128}},
3224 { 49, { 0, 0}},
3225 { UINT_MAX, { 0, 0}},
3226 },
3227 {
3228 // Two shader engines
3229 { 0, {256, 256}},
3230 { 2, {128, 256}},
3231 { 4, {128, 128}},
3232 { 7, { 64, 128}},
3233 { 13, { 32, 128}},
3234 { 25, { 16, 128}},
3235 { 49, { 0, 0}},
3236 { UINT_MAX, { 0, 0}},
3237 },
3238 {
3239 // Four shader engines
3240 { 0, {256, 512}},
3241 { 2, {256, 256}},
3242 { 4, {128, 256}},
3243 { 7, {128, 128}},
3244 { 13, { 64, 128}},
3245 { 25, { 16, 128}},
3246 { 49, { 0, 0}},
3247 { UINT_MAX, { 0, 0}},
3248 },
3249 },
3250 {
3251 // Two RB / SE
3252 {
3253 // One shader engine
3254 { 0, {256, 256}},
3255 { 2, {128, 256}},
3256 { 4, {128, 128}},
3257 { 7, { 64, 128}},
3258 { 13, { 32, 128}},
3259 { 25, { 16, 128}},
3260 { 97, { 0, 0}},
3261 { UINT_MAX, { 0, 0}},
3262 },
3263 {
3264 // Two shader engines
3265 { 0, {256, 512}},
3266 { 2, {256, 256}},
3267 { 4, {128, 256}},
3268 { 7, {128, 128}},
3269 { 13, { 64, 128}},
3270 { 25, { 32, 128}},
3271 { 49, { 16, 128}},
3272 { 97, { 0, 0}},
3273 { UINT_MAX, { 0, 0}},
3274 },
3275 {
3276 // Four shader engines
3277 { 0, {512, 512}},
3278 { 2, {256, 512}},
3279 { 4, {256, 256}},
3280 { 7, {128, 256}},
3281 { 13, {128, 128}},
3282 { 25, { 64, 128}},
3283 { 49, { 16, 128}},
3284 { 97, { 0, 0}},
3285 { UINT_MAX, { 0, 0}},
3286 },
3287 },
3288 {
3289 // Four RB / SE
3290 {
3291 // One shader engine
3292 { 0, {256, 512}},
3293 { 2, {256, 256}},
3294 { 4, {128, 256}},
3295 { 7, {128, 128}},
3296 { 13, { 64, 128}},
3297 { 25, { 32, 128}},
3298 { 49, { 16, 128}},
3299 { UINT_MAX, { 0, 0}},
3300 },
3301 {
3302 // Two shader engines
3303 { 0, {512, 512}},
3304 { 2, {256, 512}},
3305 { 4, {256, 256}},
3306 { 7, {128, 256}},
3307 { 13, {128, 128}},
3308 { 25, { 64, 128}},
3309 { 49, { 32, 128}},
3310 { 97, { 16, 128}},
3311 { UINT_MAX, { 0, 0}},
3312 },
3313 {
3314 // Four shader engines
3315 { 0, {512, 512}},
3316 { 4, {256, 512}},
3317 { 7, {256, 256}},
3318 { 13, {128, 256}},
3319 { 25, {128, 128}},
3320 { 49, { 64, 128}},
3321 { 97, { 16, 128}},
3322 { UINT_MAX, { 0, 0}},
3323 },
3324 },
3325 };
3326
3327 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3328 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3329 VkExtent2D extent = {512, 512};
3330
3331 unsigned log_num_rb_per_se =
3332 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3333 pipeline->device->physical_device->rad_info.max_se);
3334 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3335
3336 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3337 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3338 unsigned effective_samples = total_samples;
3339 unsigned color_bytes_per_pixel = 0;
3340
3341 const VkPipelineColorBlendStateCreateInfo *vkblend =
3342 radv_pipeline_get_color_blend_state(pCreateInfo);
3343 if (vkblend) {
3344 for (unsigned i = 0; i < subpass->color_count; i++) {
3345 if (!vkblend->pAttachments[i].colorWriteMask)
3346 continue;
3347
3348 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3349 continue;
3350
3351 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3352 color_bytes_per_pixel += vk_format_get_blocksize(format);
3353 }
3354
3355 /* MSAA images typically don't use all samples all the time. */
3356 if (effective_samples >= 2 && ps_iter_samples <= 1)
3357 effective_samples = 2;
3358 color_bytes_per_pixel *= effective_samples;
3359 }
3360
3361 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3362 while(color_entry[1].bpp <= color_bytes_per_pixel)
3363 ++color_entry;
3364
3365 extent = color_entry->extent;
3366
3367 if (subpass->depth_stencil_attachment) {
3368 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3369
3370 /* Coefficients taken from AMDVLK */
3371 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3372 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3373 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3374
3375 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3376 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3377 ++ds_entry;
3378
3379 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3380 extent = ds_entry->extent;
3381 }
3382
3383 return extent;
3384 }
3385
3386 static VkExtent2D
3387 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3388 {
3389 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3390 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3391 VkExtent2D extent = {512, 512};
3392
3393 const unsigned db_tag_size = 64;
3394 const unsigned db_tag_count = 312;
3395 const unsigned color_tag_size = 1024;
3396 const unsigned color_tag_count = 31;
3397 const unsigned fmask_tag_size = 256;
3398 const unsigned fmask_tag_count = 44;
3399
3400 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3401 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3402
3403 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3404 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3405 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3406
3407 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3408 const unsigned samples_log = util_logbase2_ceil(total_samples);
3409
3410 unsigned color_bytes_per_pixel = 0;
3411 unsigned fmask_bytes_per_pixel = 0;
3412
3413 const VkPipelineColorBlendStateCreateInfo *vkblend =
3414 radv_pipeline_get_color_blend_state(pCreateInfo);
3415 if (vkblend) {
3416 for (unsigned i = 0; i < subpass->color_count; i++) {
3417 if (!vkblend->pAttachments[i].colorWriteMask)
3418 continue;
3419
3420 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3421 continue;
3422
3423 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3424 color_bytes_per_pixel += vk_format_get_blocksize(format);
3425
3426 if (total_samples > 1) {
3427 assert(samples_log <= 3);
3428 const unsigned fmask_array[] = {0, 1, 1, 4};
3429 fmask_bytes_per_pixel += fmask_array[samples_log];
3430 }
3431 }
3432
3433 color_bytes_per_pixel *= total_samples;
3434 }
3435 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3436
3437 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3438 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3439 extent.height = 1ull << (color_pixel_count_log / 2);
3440
3441 if (fmask_bytes_per_pixel) {
3442 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3443
3444 const VkExtent2D fmask_extent = (VkExtent2D){
3445 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3446 .height = 1ull << (color_pixel_count_log / 2)
3447 };
3448
3449 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3450 extent = fmask_extent;
3451 }
3452
3453 if (subpass->depth_stencil_attachment) {
3454 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3455
3456 /* Coefficients taken from AMDVLK */
3457 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3458 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3459 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3460
3461 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3462
3463 const VkExtent2D db_extent = (VkExtent2D){
3464 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3465 .height = 1ull << (color_pixel_count_log / 2)
3466 };
3467
3468 if (db_extent.width * db_extent.height < extent.width * extent.height)
3469 extent = db_extent;
3470 }
3471
3472 extent.width = MAX2(extent.width, 128);
3473 extent.height = MAX2(extent.width, 64);
3474
3475 return extent;
3476 }
3477
3478 static void
3479 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3480 struct radv_pipeline *pipeline,
3481 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3482 {
3483 uint32_t pa_sc_binner_cntl_0 =
3484 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3485 S_028C44_DISABLE_START_OF_PRIM(1);
3486 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3487
3488 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3489 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3490 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3491 const VkPipelineColorBlendStateCreateInfo *vkblend =
3492 radv_pipeline_get_color_blend_state(pCreateInfo);
3493 unsigned min_bytes_per_pixel = 0;
3494
3495 if (vkblend) {
3496 for (unsigned i = 0; i < subpass->color_count; i++) {
3497 if (!vkblend->pAttachments[i].colorWriteMask)
3498 continue;
3499
3500 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3501 continue;
3502
3503 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3504 unsigned bytes = vk_format_get_blocksize(format);
3505 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3506 min_bytes_per_pixel = bytes;
3507 }
3508 }
3509
3510 pa_sc_binner_cntl_0 =
3511 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3512 S_028C44_BIN_SIZE_X(0) |
3513 S_028C44_BIN_SIZE_Y(0) |
3514 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3515 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3516 S_028C44_DISABLE_START_OF_PRIM(1);
3517 }
3518
3519 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3520 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3521 }
3522
3523 struct radv_binning_settings
3524 radv_get_binning_settings(const struct radv_physical_device *pdev)
3525 {
3526 struct radv_binning_settings settings;
3527 if (pdev->rad_info.has_dedicated_vram) {
3528 if (pdev->rad_info.num_render_backends > 4) {
3529 settings.context_states_per_bin = 1;
3530 settings.persistent_states_per_bin = 1;
3531 } else {
3532 settings.context_states_per_bin = 3;
3533 settings.persistent_states_per_bin = 8;
3534 }
3535 settings.fpovs_per_batch = 63;
3536 } else {
3537 /* The context states are affected by the scissor bug. */
3538 settings.context_states_per_bin = 6;
3539 /* 32 causes hangs for RAVEN. */
3540 settings.persistent_states_per_bin = 16;
3541 settings.fpovs_per_batch = 63;
3542 }
3543
3544 if (pdev->rad_info.has_gfx9_scissor_bug)
3545 settings.context_states_per_bin = 1;
3546
3547 return settings;
3548 }
3549
3550 static void
3551 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3552 struct radv_pipeline *pipeline,
3553 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3554 const struct radv_blend_state *blend)
3555 {
3556 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3557 return;
3558
3559 VkExtent2D bin_size;
3560 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3561 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3562 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3563 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3564 } else
3565 unreachable("Unhandled generation for binning bin size calculation");
3566
3567 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3568 struct radv_binning_settings settings =
3569 radv_get_binning_settings(pipeline->device->physical_device);
3570
3571 bool disable_start_of_prim = true;
3572 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3573
3574 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3575
3576 if (pipeline->device->dfsm_allowed && ps &&
3577 !ps->info.ps.can_discard &&
3578 !ps->info.ps.writes_memory &&
3579 blend->cb_target_enabled_4bit) {
3580 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3581 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3582 }
3583
3584 const uint32_t pa_sc_binner_cntl_0 =
3585 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3586 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3587 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3588 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3589 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3590 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3591 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3592 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3593 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3594 S_028C44_OPTIMAL_BIN_SELECTION(1);
3595
3596 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3597 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3598 } else
3599 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3600 }
3601
3602
3603 static void
3604 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3605 struct radv_pipeline *pipeline,
3606 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3607 const struct radv_graphics_pipeline_create_info *extra)
3608 {
3609 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3610 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3611 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3612 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3613 struct radv_render_pass_attachment *attachment = NULL;
3614 uint32_t db_depth_control = 0;
3615 uint32_t db_render_control = 0, db_render_override2 = 0;
3616 uint32_t db_render_override = 0;
3617
3618 if (subpass->depth_stencil_attachment)
3619 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3620
3621 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3622 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3623
3624 if (vkds && has_depth_attachment) {
3625 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3626 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3627 S_028800_ZFUNC(vkds->depthCompareOp) |
3628 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3629
3630 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3631 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3632
3633 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3634 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3635 }
3636
3637 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3638 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3639 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3640
3641 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3642 }
3643
3644 if (attachment && extra) {
3645 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3646 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3647
3648 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3649 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3650 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3651 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3652 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3653 }
3654
3655 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3656 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3657
3658 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3659 ps->info.ps.writes_z) {
3660 /* From VK_EXT_depth_range_unrestricted spec:
3661 *
3662 * "The behavior described in Primitive Clipping still applies.
3663 * If depth clamping is disabled the depth values are still
3664 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3665 * depth clamping is enabled the above equation is ignored and
3666 * the depth values are instead clamped to the VkViewport
3667 * minDepth and maxDepth values, which in the case of this
3668 * extension can be outside of the 0.0 to 1.0 range."
3669 */
3670 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3671 }
3672
3673 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3674 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3675 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3676
3677 pipeline->graphics.db_depth_control = db_depth_control;
3678 }
3679
3680 static void
3681 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3682 struct radv_pipeline *pipeline,
3683 const struct radv_blend_state *blend)
3684 {
3685 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3686 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3687 8);
3688 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3689 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3690
3691 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3692
3693 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3694 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3695 }
3696
3697 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3698
3699 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3700 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3701
3702 pipeline->graphics.col_format = blend->spi_shader_col_format;
3703 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3704 }
3705
3706 static const VkConservativeRasterizationModeEXT
3707 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3708 {
3709 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3710 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3711
3712 if (!conservative_raster)
3713 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3714 return conservative_raster->conservativeRasterizationMode;
3715 }
3716
3717 static void
3718 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3719 struct radv_pipeline *pipeline,
3720 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3721 {
3722 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3723 const VkConservativeRasterizationModeEXT mode =
3724 radv_get_conservative_raster_mode(vkraster);
3725 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3726 bool depth_clip_disable = vkraster->depthClampEnable;
3727
3728 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3729 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3730 if (depth_clip_state) {
3731 depth_clip_disable = !depth_clip_state->depthClipEnable;
3732 }
3733
3734 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3735 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3736 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3737 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3738 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3739 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3740
3741 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3742 S_0286D4_FLAT_SHADE_ENA(1) |
3743 S_0286D4_PNT_SPRITE_ENA(1) |
3744 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3745 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3746 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3747 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3748 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3749
3750 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3751 S_028BE4_PIX_CENTER(1) | // TODO verify
3752 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3753 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3754
3755 pipeline->graphics.pa_su_sc_mode_cntl =
3756 S_028814_FACE(vkraster->frontFace) |
3757 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3758 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3759 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3760 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3761 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3762 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3763 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3764 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
3765
3766 /* Conservative rasterization. */
3767 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3768 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3769
3770 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3771 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3772 S_028804_OVERRASTERIZATION_AMOUNT(4);
3773
3774 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3775 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3776 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3777
3778 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3779 pa_sc_conservative_rast |=
3780 S_028C4C_OVER_RAST_ENABLE(1) |
3781 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3782 S_028C4C_UNDER_RAST_ENABLE(0) |
3783 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3784 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3785 } else {
3786 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3787 pa_sc_conservative_rast |=
3788 S_028C4C_OVER_RAST_ENABLE(0) |
3789 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3790 S_028C4C_UNDER_RAST_ENABLE(1) |
3791 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3792 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3793 }
3794 }
3795
3796 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3797 pa_sc_conservative_rast);
3798 }
3799
3800
3801 static void
3802 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3803 struct radv_pipeline *pipeline)
3804 {
3805 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3806
3807 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3808 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3809 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3810
3811 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3812 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3813 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3814 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3815 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3816
3817 /* The exclusion bits can be set to improve rasterization efficiency
3818 * if no sample lies on the pixel boundary (-8 sample offset). It's
3819 * currently always TRUE because the driver doesn't support 16 samples.
3820 */
3821 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3822 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3823 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3824 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3825
3826 /* GFX9: Flush DFSM when the AA mode changes. */
3827 if (pipeline->device->dfsm_allowed) {
3828 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3829 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3830 }
3831 }
3832
3833 static void
3834 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3835 struct radv_pipeline *pipeline)
3836 {
3837 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3838 const struct radv_shader_variant *vs =
3839 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3840 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3841 pipeline->shaders[MESA_SHADER_VERTEX];
3842 unsigned vgt_primitiveid_en = 0;
3843 uint32_t vgt_gs_mode = 0;
3844
3845 if (radv_pipeline_has_ngg(pipeline))
3846 return;
3847
3848 if (radv_pipeline_has_gs(pipeline)) {
3849 const struct radv_shader_variant *gs =
3850 pipeline->shaders[MESA_SHADER_GEOMETRY];
3851
3852 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3853 pipeline->device->physical_device->rad_info.chip_class);
3854 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3855 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3856 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3857 }
3858
3859 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3860 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3861 }
3862
3863 static void
3864 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3865 struct radeon_cmdbuf *cs,
3866 struct radv_pipeline *pipeline,
3867 struct radv_shader_variant *shader)
3868 {
3869 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3870
3871 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3872 radeon_emit(cs, va >> 8);
3873 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3874 radeon_emit(cs, shader->config.rsrc1);
3875 radeon_emit(cs, shader->config.rsrc2);
3876
3877 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3878 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3879 clip_dist_mask = outinfo->clip_dist_mask;
3880 cull_dist_mask = outinfo->cull_dist_mask;
3881 total_mask = clip_dist_mask | cull_dist_mask;
3882 bool misc_vec_ena = outinfo->writes_pointsize ||
3883 outinfo->writes_layer ||
3884 outinfo->writes_viewport_index;
3885 unsigned spi_vs_out_config, nparams;
3886
3887 /* VS is required to export at least one param. */
3888 nparams = MAX2(outinfo->param_exports, 1);
3889 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3890
3891 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3892 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3893 }
3894
3895 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3896
3897 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3898 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3899 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3900 V_02870C_SPI_SHADER_4COMP :
3901 V_02870C_SPI_SHADER_NONE) |
3902 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3903 V_02870C_SPI_SHADER_4COMP :
3904 V_02870C_SPI_SHADER_NONE) |
3905 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3906 V_02870C_SPI_SHADER_4COMP :
3907 V_02870C_SPI_SHADER_NONE));
3908
3909 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3910 S_028818_VTX_W0_FMT(1) |
3911 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3912 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3913 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3914
3915 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3916 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3917 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3918 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3919 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3920 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3921 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3922 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3923 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3924 cull_dist_mask << 8 |
3925 clip_dist_mask);
3926
3927 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3928 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3929 outinfo->writes_viewport_index);
3930 }
3931
3932 static void
3933 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3934 struct radv_pipeline *pipeline,
3935 struct radv_shader_variant *shader)
3936 {
3937 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3938
3939 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3940 radeon_emit(cs, va >> 8);
3941 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3942 radeon_emit(cs, shader->config.rsrc1);
3943 radeon_emit(cs, shader->config.rsrc2);
3944 }
3945
3946 static void
3947 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3948 struct radv_pipeline *pipeline,
3949 struct radv_shader_variant *shader,
3950 const struct radv_tessellation_state *tess)
3951 {
3952 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3953 uint32_t rsrc2 = shader->config.rsrc2;
3954
3955 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3956 radeon_emit(cs, va >> 8);
3957 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3958
3959 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3960 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3961 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3962 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3963
3964 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3965 radeon_emit(cs, shader->config.rsrc1);
3966 radeon_emit(cs, rsrc2);
3967 }
3968
3969 static void
3970 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3971 struct radeon_cmdbuf *cs,
3972 struct radv_pipeline *pipeline,
3973 struct radv_shader_variant *shader)
3974 {
3975 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3976 gl_shader_stage es_type =
3977 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3978 struct radv_shader_variant *es =
3979 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3980 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3981
3982 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3983 radeon_emit(cs, va >> 8);
3984 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3985 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3986 radeon_emit(cs, shader->config.rsrc1);
3987 radeon_emit(cs, shader->config.rsrc2);
3988
3989 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3990 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3991 clip_dist_mask = outinfo->clip_dist_mask;
3992 cull_dist_mask = outinfo->cull_dist_mask;
3993 total_mask = clip_dist_mask | cull_dist_mask;
3994 bool misc_vec_ena = outinfo->writes_pointsize ||
3995 outinfo->writes_layer ||
3996 outinfo->writes_viewport_index;
3997 bool es_enable_prim_id = outinfo->export_prim_id ||
3998 (es && es->info.uses_prim_id);
3999 bool break_wave_at_eoi = false;
4000 unsigned ge_cntl;
4001 unsigned nparams;
4002
4003 if (es_type == MESA_SHADER_TESS_EVAL) {
4004 struct radv_shader_variant *gs =
4005 pipeline->shaders[MESA_SHADER_GEOMETRY];
4006
4007 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
4008 break_wave_at_eoi = true;
4009 }
4010
4011 nparams = MAX2(outinfo->param_exports, 1);
4012 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
4013 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
4014 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
4015
4016 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
4017 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
4018 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
4019 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
4020 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
4021 V_02870C_SPI_SHADER_4COMP :
4022 V_02870C_SPI_SHADER_NONE) |
4023 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
4024 V_02870C_SPI_SHADER_4COMP :
4025 V_02870C_SPI_SHADER_NONE) |
4026 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
4027 V_02870C_SPI_SHADER_4COMP :
4028 V_02870C_SPI_SHADER_NONE));
4029
4030 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
4031 S_028818_VTX_W0_FMT(1) |
4032 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
4033 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
4034 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
4035 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
4036 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4037 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4038 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4039 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4040 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4041 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4042 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4043 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4044 cull_dist_mask << 8 |
4045 clip_dist_mask);
4046
4047 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4048 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4049 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4050
4051 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4052 ngg_state->vgt_esgs_ring_itemsize);
4053
4054 /* NGG specific registers. */
4055 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4056 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4057
4058 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4059 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4060 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4061 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4062 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4063 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4064 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4065 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4066 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4067 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4068 S_028B90_CNT(gs_num_invocations) |
4069 S_028B90_ENABLE(gs_num_invocations > 1) |
4070 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4071
4072 /* User edge flags are set by the pos exports. If user edge flags are
4073 * not used, we must use hw-generated edge flags and pass them via
4074 * the prim export to prevent drawing lines on internal edges of
4075 * decomposed primitives (such as quads) with polygon mode = lines.
4076 *
4077 * TODO: We should combine hw-generated edge flags with user edge
4078 * flags in the shader.
4079 */
4080 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4081 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4082 !radv_pipeline_has_gs(pipeline)) |
4083 /* Reuse for NGG. */
4084 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4085
4086 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4087 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4088 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4089
4090 /* Bug workaround for a possible hang with non-tessellation cases.
4091 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4092 *
4093 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4094 */
4095 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4096 !radv_pipeline_has_tess(pipeline) &&
4097 ngg_state->hw_max_esverts != 256) {
4098 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4099
4100 if (ngg_state->hw_max_esverts > 5) {
4101 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4102 }
4103 }
4104
4105 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4106 }
4107
4108 static void
4109 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4110 struct radv_pipeline *pipeline,
4111 struct radv_shader_variant *shader,
4112 const struct radv_tessellation_state *tess)
4113 {
4114 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4115
4116 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4117 unsigned hs_rsrc2 = shader->config.rsrc2;
4118
4119 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4120 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4121 } else {
4122 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4123 }
4124
4125 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4126 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4127 radeon_emit(cs, va >> 8);
4128 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4129 } else {
4130 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4131 radeon_emit(cs, va >> 8);
4132 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4133 }
4134
4135 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4136 radeon_emit(cs, shader->config.rsrc1);
4137 radeon_emit(cs, hs_rsrc2);
4138 } else {
4139 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4140 radeon_emit(cs, va >> 8);
4141 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4142 radeon_emit(cs, shader->config.rsrc1);
4143 radeon_emit(cs, shader->config.rsrc2);
4144 }
4145 }
4146
4147 static void
4148 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4149 struct radeon_cmdbuf *cs,
4150 struct radv_pipeline *pipeline,
4151 const struct radv_tessellation_state *tess)
4152 {
4153 struct radv_shader_variant *vs;
4154
4155 /* Skip shaders merged into HS/GS */
4156 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4157 if (!vs)
4158 return;
4159
4160 if (vs->info.vs.as_ls)
4161 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4162 else if (vs->info.vs.as_es)
4163 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4164 else if (vs->info.is_ngg)
4165 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4166 else
4167 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4168 }
4169
4170 static void
4171 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4172 struct radeon_cmdbuf *cs,
4173 struct radv_pipeline *pipeline,
4174 const struct radv_tessellation_state *tess)
4175 {
4176 if (!radv_pipeline_has_tess(pipeline))
4177 return;
4178
4179 struct radv_shader_variant *tes, *tcs;
4180
4181 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4182 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4183
4184 if (tes) {
4185 if (tes->info.is_ngg) {
4186 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4187 } else if (tes->info.tes.as_es)
4188 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4189 else
4190 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4191 }
4192
4193 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4194
4195 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4196 tess->tf_param);
4197
4198 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4199 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4200 tess->ls_hs_config);
4201 else
4202 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4203 tess->ls_hs_config);
4204
4205 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4206 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4207 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4208 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4209 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4210 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4211 }
4212 }
4213
4214 static void
4215 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4216 struct radeon_cmdbuf *cs,
4217 struct radv_pipeline *pipeline,
4218 struct radv_shader_variant *gs)
4219 {
4220 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4221 unsigned gs_max_out_vertices;
4222 uint8_t *num_components;
4223 uint8_t max_stream;
4224 unsigned offset;
4225 uint64_t va;
4226
4227 gs_max_out_vertices = gs->info.gs.vertices_out;
4228 max_stream = gs->info.gs.max_stream;
4229 num_components = gs->info.gs.num_stream_output_components;
4230
4231 offset = num_components[0] * gs_max_out_vertices;
4232
4233 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4234 radeon_emit(ctx_cs, offset);
4235 if (max_stream >= 1)
4236 offset += num_components[1] * gs_max_out_vertices;
4237 radeon_emit(ctx_cs, offset);
4238 if (max_stream >= 2)
4239 offset += num_components[2] * gs_max_out_vertices;
4240 radeon_emit(ctx_cs, offset);
4241 if (max_stream >= 3)
4242 offset += num_components[3] * gs_max_out_vertices;
4243 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4244
4245 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4246 radeon_emit(ctx_cs, num_components[0]);
4247 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4248 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4249 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4250
4251 uint32_t gs_num_invocations = gs->info.gs.invocations;
4252 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4253 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4254 S_028B90_ENABLE(gs_num_invocations > 0));
4255
4256 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4257 gs_state->vgt_esgs_ring_itemsize);
4258
4259 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4260
4261 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4262 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4263 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4264 radeon_emit(cs, va >> 8);
4265 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4266 } else {
4267 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4268 radeon_emit(cs, va >> 8);
4269 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4270 }
4271
4272 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4273 radeon_emit(cs, gs->config.rsrc1);
4274 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4275
4276 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4277 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4278 } else {
4279 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4280 radeon_emit(cs, va >> 8);
4281 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4282 radeon_emit(cs, gs->config.rsrc1);
4283 radeon_emit(cs, gs->config.rsrc2);
4284 }
4285
4286 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4287 }
4288
4289 static void
4290 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4291 struct radeon_cmdbuf *cs,
4292 struct radv_pipeline *pipeline)
4293 {
4294 struct radv_shader_variant *gs;
4295
4296 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4297 if (!gs)
4298 return;
4299
4300 if (gs->info.is_ngg)
4301 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4302 else
4303 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4304
4305 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4306 gs->info.gs.vertices_out);
4307 }
4308
4309 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4310 bool explicit, bool float16)
4311 {
4312 uint32_t ps_input_cntl;
4313 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4314 ps_input_cntl = S_028644_OFFSET(offset);
4315 if (flat_shade || explicit)
4316 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4317 if (explicit) {
4318 /* Force parameter cache to be read in passthrough
4319 * mode.
4320 */
4321 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4322 }
4323 if (float16) {
4324 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4325 S_028644_ATTR0_VALID(1);
4326 }
4327 } else {
4328 /* The input is a DEFAULT_VAL constant. */
4329 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4330 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4331 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4332 ps_input_cntl = S_028644_OFFSET(0x20) |
4333 S_028644_DEFAULT_VAL(offset);
4334 }
4335 return ps_input_cntl;
4336 }
4337
4338 static void
4339 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4340 struct radv_pipeline *pipeline)
4341 {
4342 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4343 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4344 uint32_t ps_input_cntl[32];
4345
4346 unsigned ps_offset = 0;
4347
4348 if (ps->info.ps.prim_id_input) {
4349 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4350 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4351 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4352 ++ps_offset;
4353 }
4354 }
4355
4356 if (ps->info.ps.layer_input ||
4357 ps->info.needs_multiview_view_index) {
4358 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4359 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4360 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4361 else
4362 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4363 ++ps_offset;
4364 }
4365
4366 if (ps->info.ps.viewport_index_input) {
4367 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4368 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4369 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4370 else
4371 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4372 ++ps_offset;
4373 }
4374
4375 if (ps->info.ps.has_pcoord) {
4376 unsigned val;
4377 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4378 ps_input_cntl[ps_offset] = val;
4379 ps_offset++;
4380 }
4381
4382 if (ps->info.ps.num_input_clips_culls) {
4383 unsigned vs_offset;
4384
4385 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4386 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4387 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4388 ++ps_offset;
4389 }
4390
4391 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4392 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4393 ps->info.ps.num_input_clips_culls > 4) {
4394 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4395 ++ps_offset;
4396 }
4397 }
4398
4399 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4400 unsigned vs_offset;
4401 bool flat_shade;
4402 bool explicit;
4403 bool float16;
4404 if (!(ps->info.ps.input_mask & (1u << i)))
4405 continue;
4406
4407 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4408 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4409 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4410 ++ps_offset;
4411 continue;
4412 }
4413
4414 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4415 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4416 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4417
4418 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4419 ++ps_offset;
4420 }
4421
4422 if (ps_offset) {
4423 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4424 for (unsigned i = 0; i < ps_offset; i++) {
4425 radeon_emit(ctx_cs, ps_input_cntl[i]);
4426 }
4427 }
4428 }
4429
4430 static uint32_t
4431 radv_compute_db_shader_control(const struct radv_device *device,
4432 const struct radv_pipeline *pipeline,
4433 const struct radv_shader_variant *ps)
4434 {
4435 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4436 unsigned z_order;
4437 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4438 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4439 else
4440 z_order = V_02880C_LATE_Z;
4441
4442 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4443 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4444 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4445 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4446
4447 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4448 !device->physical_device->rad_info.rbplus_allowed;
4449
4450 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4451 * but this appears to break Project Cars (DXVK). See
4452 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4453 */
4454 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4455
4456 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4457 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4458 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4459 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4460 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4461 S_02880C_Z_ORDER(z_order) |
4462 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4463 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4464 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4465 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4466 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4467 }
4468
4469 static void
4470 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4471 struct radeon_cmdbuf *cs,
4472 struct radv_pipeline *pipeline)
4473 {
4474 struct radv_shader_variant *ps;
4475 uint64_t va;
4476 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4477
4478 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4479 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4480
4481 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4482 radeon_emit(cs, va >> 8);
4483 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4484 radeon_emit(cs, ps->config.rsrc1);
4485 radeon_emit(cs, ps->config.rsrc2);
4486
4487 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4488 radv_compute_db_shader_control(pipeline->device,
4489 pipeline, ps));
4490
4491 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4492 ps->config.spi_ps_input_ena);
4493
4494 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4495 ps->config.spi_ps_input_addr);
4496
4497 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4498 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4499 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4500
4501 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4502
4503 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4504 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4505 ps->info.ps.writes_stencil,
4506 ps->info.ps.writes_sample_mask));
4507
4508 if (pipeline->device->dfsm_allowed) {
4509 /* optimise this? */
4510 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4511 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4512 }
4513 }
4514
4515 static void
4516 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4517 struct radv_pipeline *pipeline)
4518 {
4519 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4520 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4521 return;
4522
4523 unsigned vtx_reuse_depth = 30;
4524 if (radv_pipeline_has_tess(pipeline) &&
4525 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4526 vtx_reuse_depth = 14;
4527 }
4528 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4529 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4530 }
4531
4532 static uint32_t
4533 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4534 {
4535 uint32_t stages = 0;
4536 if (radv_pipeline_has_tess(pipeline)) {
4537 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4538 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4539
4540 if (radv_pipeline_has_gs(pipeline))
4541 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4542 S_028B54_GS_EN(1);
4543 else if (radv_pipeline_has_ngg(pipeline))
4544 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4545 else
4546 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4547 } else if (radv_pipeline_has_gs(pipeline)) {
4548 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4549 S_028B54_GS_EN(1);
4550 } else if (radv_pipeline_has_ngg(pipeline)) {
4551 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4552 }
4553
4554 if (radv_pipeline_has_ngg(pipeline)) {
4555 stages |= S_028B54_PRIMGEN_EN(1);
4556 if (pipeline->streamout_shader)
4557 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4558 if (radv_pipeline_has_ngg_passthrough(pipeline))
4559 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4560 } else if (radv_pipeline_has_gs(pipeline)) {
4561 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4562 }
4563
4564 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4565 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4566
4567 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4568 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4569
4570 if (radv_pipeline_has_tess(pipeline))
4571 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4572
4573 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4574 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4575 if (pipeline->gs_copy_shader)
4576 vs_size = pipeline->gs_copy_shader->info.wave_size;
4577 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4578 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4579 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4580 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4581
4582 if (radv_pipeline_has_ngg(pipeline))
4583 gs_size = vs_size;
4584
4585 /* legacy GS only supports Wave64 */
4586 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4587 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4588 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4589 }
4590
4591 return stages;
4592 }
4593
4594 static uint32_t
4595 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4596 {
4597 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4598 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4599
4600 if (!discard_rectangle_info)
4601 return 0xffff;
4602
4603 unsigned mask = 0;
4604
4605 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4606 /* Interpret i as a bitmask, and then set the bit in the mask if
4607 * that combination of rectangles in which the pixel is contained
4608 * should pass the cliprect test. */
4609 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4610
4611 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4612 !relevant_subset)
4613 continue;
4614
4615 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4616 relevant_subset)
4617 continue;
4618
4619 mask |= 1u << i;
4620 }
4621
4622 return mask;
4623 }
4624
4625 static void
4626 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4627 struct radv_pipeline *pipeline,
4628 const struct radv_tessellation_state *tess)
4629 {
4630 bool break_wave_at_eoi = false;
4631 unsigned primgroup_size;
4632 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4633
4634 if (radv_pipeline_has_tess(pipeline)) {
4635 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4636 } else if (radv_pipeline_has_gs(pipeline)) {
4637 const struct gfx9_gs_info *gs_state =
4638 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4639 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4640 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4641 } else {
4642 primgroup_size = 128; /* recommended without a GS and tess */
4643 }
4644
4645 if (radv_pipeline_has_tess(pipeline)) {
4646 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4647 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4648 break_wave_at_eoi = true;
4649 }
4650
4651 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4652 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4653 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4654 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4655 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4656 }
4657
4658 static void
4659 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4660 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4661 const struct radv_graphics_pipeline_create_info *extra,
4662 const struct radv_blend_state *blend,
4663 const struct radv_tessellation_state *tess,
4664 unsigned gs_out)
4665 {
4666 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4667 struct radeon_cmdbuf *cs = &pipeline->cs;
4668
4669 cs->max_dw = 64;
4670 ctx_cs->max_dw = 256;
4671 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4672 ctx_cs->buf = cs->buf + cs->max_dw;
4673
4674 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4675 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4676 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4677 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4678 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4679 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4680 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4681 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4682 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4683 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4684 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4685 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4686
4687 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4688 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4689
4690 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4691 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4692
4693 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4694
4695 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4696
4697 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4698 assert(cs->cdw <= cs->max_dw);
4699 }
4700
4701 static struct radv_ia_multi_vgt_param_helpers
4702 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4703 const struct radv_tessellation_state *tess)
4704 {
4705 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4706 const struct radv_device *device = pipeline->device;
4707
4708 if (radv_pipeline_has_tess(pipeline))
4709 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4710 else if (radv_pipeline_has_gs(pipeline))
4711 ia_multi_vgt_param.primgroup_size = 64;
4712 else
4713 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4714
4715 /* GS requirement. */
4716 ia_multi_vgt_param.partial_es_wave = false;
4717 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4718 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4719 ia_multi_vgt_param.partial_es_wave = true;
4720
4721 ia_multi_vgt_param.ia_switch_on_eoi = false;
4722 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4723 ia_multi_vgt_param.ia_switch_on_eoi = true;
4724 if (radv_pipeline_has_gs(pipeline) &&
4725 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4726 ia_multi_vgt_param.ia_switch_on_eoi = true;
4727 if (radv_pipeline_has_tess(pipeline)) {
4728 /* SWITCH_ON_EOI must be set if PrimID is used. */
4729 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4730 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4731 ia_multi_vgt_param.ia_switch_on_eoi = true;
4732 }
4733
4734 ia_multi_vgt_param.partial_vs_wave = false;
4735 if (radv_pipeline_has_tess(pipeline)) {
4736 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4737 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4738 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4739 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4740 radv_pipeline_has_gs(pipeline))
4741 ia_multi_vgt_param.partial_vs_wave = true;
4742 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4743 if (device->physical_device->rad_info.has_distributed_tess) {
4744 if (radv_pipeline_has_gs(pipeline)) {
4745 if (device->physical_device->rad_info.chip_class <= GFX8)
4746 ia_multi_vgt_param.partial_es_wave = true;
4747 } else {
4748 ia_multi_vgt_param.partial_vs_wave = true;
4749 }
4750 }
4751 }
4752
4753 if (radv_pipeline_has_gs(pipeline)) {
4754 /* On these chips there is the possibility of a hang if the
4755 * pipeline uses a GS and partial_vs_wave is not set.
4756 *
4757 * This mostly does not hit 4-SE chips, as those typically set
4758 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4759 * with GS due to another workaround.
4760 *
4761 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4762 */
4763 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4764 device->physical_device->rad_info.family == CHIP_FIJI ||
4765 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4766 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4767 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4768 device->physical_device->rad_info.family == CHIP_VEGAM) {
4769 ia_multi_vgt_param.partial_vs_wave = true;
4770 }
4771 }
4772
4773 ia_multi_vgt_param.base =
4774 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4775 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4776 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4777 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4778 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4779
4780 return ia_multi_vgt_param;
4781 }
4782
4783
4784 static void
4785 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4786 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4787 {
4788 const VkPipelineVertexInputStateCreateInfo *vi_info =
4789 pCreateInfo->pVertexInputState;
4790 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4791
4792 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4793 const VkVertexInputAttributeDescription *desc =
4794 &vi_info->pVertexAttributeDescriptions[i];
4795 unsigned loc = desc->location;
4796 const struct vk_format_description *format_desc;
4797
4798 format_desc = vk_format_description(desc->format);
4799
4800 velems->format_size[loc] = format_desc->block.bits / 8;
4801 }
4802
4803 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4804 const VkVertexInputBindingDescription *desc =
4805 &vi_info->pVertexBindingDescriptions[i];
4806
4807 pipeline->binding_stride[desc->binding] = desc->stride;
4808 pipeline->num_vertex_bindings =
4809 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4810 }
4811 }
4812
4813 static struct radv_shader_variant *
4814 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4815 {
4816 int i;
4817
4818 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4819 struct radv_shader_variant *shader =
4820 radv_get_shader(pipeline, i);
4821
4822 if (shader && shader->info.so.num_outputs > 0)
4823 return shader;
4824 }
4825
4826 return NULL;
4827 }
4828
4829 static VkResult
4830 radv_pipeline_init(struct radv_pipeline *pipeline,
4831 struct radv_device *device,
4832 struct radv_pipeline_cache *cache,
4833 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4834 const struct radv_graphics_pipeline_create_info *extra)
4835 {
4836 VkResult result;
4837 bool has_view_index = false;
4838
4839 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4840 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4841 if (subpass->view_mask)
4842 has_view_index = true;
4843
4844 pipeline->device = device;
4845 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4846 assert(pipeline->layout);
4847
4848 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4849
4850 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4851 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4852 radv_init_feedback(creation_feedback);
4853
4854 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4855
4856 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4857 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4858 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4859 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4860 pStages[stage] = &pCreateInfo->pStages[i];
4861 if(creation_feedback)
4862 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4863 }
4864
4865 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4866
4867 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
4868 pCreateInfo->flags, pipeline_feedback,
4869 stage_feedbacks);
4870 if (result != VK_SUCCESS)
4871 return result;
4872
4873 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4874 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4875 uint32_t gs_out;
4876
4877 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4878
4879 if (radv_pipeline_has_gs(pipeline)) {
4880 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4881 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4882 } else if (radv_pipeline_has_tess(pipeline)) {
4883 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4884 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4885 else
4886 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4887 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4888 } else {
4889 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4890 }
4891 if (extra && extra->use_rectlist) {
4892 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4893 pipeline->graphics.can_use_guardband = true;
4894 if (radv_pipeline_has_ngg(pipeline))
4895 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4896 }
4897 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4898
4899 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra);
4900
4901 /* Ensure that some export memory is always allocated, for two reasons:
4902 *
4903 * 1) Correctness: The hardware ignores the EXEC mask if no export
4904 * memory is allocated, so KILL and alpha test do not work correctly
4905 * without this.
4906 * 2) Performance: Every shader needs at least a NULL export, even when
4907 * it writes no color/depth output. The NULL export instruction
4908 * stalls without this setting.
4909 *
4910 * Don't add this to CB_SHADER_MASK.
4911 *
4912 * GFX10 supports pixel shaders without exports by setting both the
4913 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4914 * instructions if any are present.
4915 */
4916 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4917 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4918 ps->info.ps.can_discard) &&
4919 !blend.spi_shader_col_format) {
4920 if (!ps->info.ps.writes_z &&
4921 !ps->info.ps.writes_stencil &&
4922 !ps->info.ps.writes_sample_mask)
4923 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4924 }
4925
4926 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
4927
4928 if (extra &&
4929 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
4930 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
4931 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
4932 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
4933 /* According to the CB spec states, CB_SHADER_MASK should be
4934 * set to enable writes to all four channels of MRT0.
4935 */
4936 blend.cb_shader_mask = 0xf;
4937 }
4938
4939 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4940 if (pipeline->shaders[i]) {
4941 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4942 }
4943 }
4944
4945 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4946 struct radv_shader_variant *gs =
4947 pipeline->shaders[MESA_SHADER_GEOMETRY];
4948
4949 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4950 }
4951
4952 struct radv_tessellation_state tess = {0};
4953 if (radv_pipeline_has_tess(pipeline)) {
4954 pipeline->graphics.tess_patch_control_points =
4955 pCreateInfo->pTessellationState->patchControlPoints;
4956 tess = calculate_tess_state(pipeline, pCreateInfo);
4957 }
4958
4959 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess);
4960
4961 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4962
4963 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4964 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4965
4966 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4967 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4968 if (loc->sgpr_idx != -1) {
4969 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4970 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4971 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4972 pipeline->graphics.vtx_emit_num = 3;
4973 else
4974 pipeline->graphics.vtx_emit_num = 2;
4975 }
4976
4977 /* Find the last vertex shader stage that eventually uses streamout. */
4978 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4979
4980 result = radv_pipeline_scratch_init(device, pipeline);
4981 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, gs_out);
4982
4983 return result;
4984 }
4985
4986 VkResult
4987 radv_graphics_pipeline_create(
4988 VkDevice _device,
4989 VkPipelineCache _cache,
4990 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4991 const struct radv_graphics_pipeline_create_info *extra,
4992 const VkAllocationCallbacks *pAllocator,
4993 VkPipeline *pPipeline)
4994 {
4995 RADV_FROM_HANDLE(radv_device, device, _device);
4996 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4997 struct radv_pipeline *pipeline;
4998 VkResult result;
4999
5000 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5001 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5002 if (pipeline == NULL)
5003 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5004
5005 vk_object_base_init(&device->vk, &pipeline->base,
5006 VK_OBJECT_TYPE_PIPELINE);
5007
5008 result = radv_pipeline_init(pipeline, device, cache,
5009 pCreateInfo, extra);
5010 if (result != VK_SUCCESS) {
5011 radv_pipeline_destroy(device, pipeline, pAllocator);
5012 return result;
5013 }
5014
5015 *pPipeline = radv_pipeline_to_handle(pipeline);
5016
5017 return VK_SUCCESS;
5018 }
5019
5020 VkResult radv_CreateGraphicsPipelines(
5021 VkDevice _device,
5022 VkPipelineCache pipelineCache,
5023 uint32_t count,
5024 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5025 const VkAllocationCallbacks* pAllocator,
5026 VkPipeline* pPipelines)
5027 {
5028 VkResult result = VK_SUCCESS;
5029 unsigned i = 0;
5030
5031 for (; i < count; i++) {
5032 VkResult r;
5033 r = radv_graphics_pipeline_create(_device,
5034 pipelineCache,
5035 &pCreateInfos[i],
5036 NULL, pAllocator, &pPipelines[i]);
5037 if (r != VK_SUCCESS) {
5038 result = r;
5039 pPipelines[i] = VK_NULL_HANDLE;
5040
5041 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5042 break;
5043 }
5044 }
5045
5046 for (; i < count; ++i)
5047 pPipelines[i] = VK_NULL_HANDLE;
5048
5049 return result;
5050 }
5051
5052
5053 static void
5054 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5055 {
5056 struct radv_shader_variant *compute_shader;
5057 struct radv_device *device = pipeline->device;
5058 unsigned threads_per_threadgroup;
5059 unsigned threadgroups_per_cu = 1;
5060 unsigned waves_per_threadgroup;
5061 unsigned max_waves_per_sh = 0;
5062 uint64_t va;
5063
5064 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5065 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5066
5067 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5068 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5069
5070 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5071 radeon_emit(&pipeline->cs, va >> 8);
5072 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5073
5074 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5075 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5076 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5077 if (device->physical_device->rad_info.chip_class >= GFX10) {
5078 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5079 }
5080
5081 /* Calculate best compute resource limits. */
5082 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5083 compute_shader->info.cs.block_size[1] *
5084 compute_shader->info.cs.block_size[2];
5085 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5086 compute_shader->info.wave_size);
5087
5088 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5089 waves_per_threadgroup == 1)
5090 threadgroups_per_cu = 2;
5091
5092 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5093 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5094 waves_per_threadgroup,
5095 max_waves_per_sh,
5096 threadgroups_per_cu));
5097
5098 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5099 radeon_emit(&pipeline->cs,
5100 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5101 radeon_emit(&pipeline->cs,
5102 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5103 radeon_emit(&pipeline->cs,
5104 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5105
5106 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5107 }
5108
5109 static struct radv_pipeline_key
5110 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5111 const VkComputePipelineCreateInfo *pCreateInfo)
5112 {
5113 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5114 struct radv_pipeline_key key;
5115 memset(&key, 0, sizeof(key));
5116
5117 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5118 key.optimisations_disabled = 1;
5119
5120 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5121 vk_find_struct_const(stage->pNext,
5122 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5123
5124 if (subgroup_size) {
5125 assert(subgroup_size->requiredSubgroupSize == 32 ||
5126 subgroup_size->requiredSubgroupSize == 64);
5127 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5128 }
5129
5130 return key;
5131 }
5132
5133 static VkResult radv_compute_pipeline_create(
5134 VkDevice _device,
5135 VkPipelineCache _cache,
5136 const VkComputePipelineCreateInfo* pCreateInfo,
5137 const VkAllocationCallbacks* pAllocator,
5138 VkPipeline* pPipeline)
5139 {
5140 RADV_FROM_HANDLE(radv_device, device, _device);
5141 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5142 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5143 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5144 struct radv_pipeline *pipeline;
5145 VkResult result;
5146
5147 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5148 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5149 if (pipeline == NULL)
5150 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5151
5152 vk_object_base_init(&device->vk, &pipeline->base,
5153 VK_OBJECT_TYPE_PIPELINE);
5154
5155 pipeline->device = device;
5156 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5157 assert(pipeline->layout);
5158
5159 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5160 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5161 radv_init_feedback(creation_feedback);
5162
5163 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5164 if (creation_feedback)
5165 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5166
5167 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5168
5169 struct radv_pipeline_key key =
5170 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5171
5172 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5173 pCreateInfo->flags, pipeline_feedback,
5174 stage_feedbacks);
5175 if (result != VK_SUCCESS) {
5176 radv_pipeline_destroy(device, pipeline, pAllocator);
5177 return result;
5178 }
5179
5180 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5181 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5182 result = radv_pipeline_scratch_init(device, pipeline);
5183 if (result != VK_SUCCESS) {
5184 radv_pipeline_destroy(device, pipeline, pAllocator);
5185 return result;
5186 }
5187
5188 radv_compute_generate_pm4(pipeline);
5189
5190 *pPipeline = radv_pipeline_to_handle(pipeline);
5191
5192 return VK_SUCCESS;
5193 }
5194
5195 VkResult radv_CreateComputePipelines(
5196 VkDevice _device,
5197 VkPipelineCache pipelineCache,
5198 uint32_t count,
5199 const VkComputePipelineCreateInfo* pCreateInfos,
5200 const VkAllocationCallbacks* pAllocator,
5201 VkPipeline* pPipelines)
5202 {
5203 VkResult result = VK_SUCCESS;
5204
5205 unsigned i = 0;
5206 for (; i < count; i++) {
5207 VkResult r;
5208 r = radv_compute_pipeline_create(_device, pipelineCache,
5209 &pCreateInfos[i],
5210 pAllocator, &pPipelines[i]);
5211 if (r != VK_SUCCESS) {
5212 result = r;
5213 pPipelines[i] = VK_NULL_HANDLE;
5214
5215 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5216 break;
5217 }
5218 }
5219
5220 for (; i < count; ++i)
5221 pPipelines[i] = VK_NULL_HANDLE;
5222
5223 return result;
5224 }
5225
5226
5227 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5228 {
5229 uint32_t ret = 0;
5230 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5231 if (!pipeline->shaders[i])
5232 continue;
5233
5234 if (i == MESA_SHADER_GEOMETRY &&
5235 !radv_pipeline_has_ngg(pipeline)) {
5236 ret += 2u;
5237 } else {
5238 ret += 1u;
5239 }
5240
5241 }
5242 return ret;
5243 }
5244
5245 static struct radv_shader_variant *
5246 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5247 {
5248 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5249 if (!pipeline->shaders[i])
5250 continue;
5251 if (!index) {
5252 *stage = i;
5253 return pipeline->shaders[i];
5254 }
5255
5256 --index;
5257
5258 if (i == MESA_SHADER_GEOMETRY &&
5259 !radv_pipeline_has_ngg(pipeline)) {
5260 if (!index) {
5261 *stage = i;
5262 return pipeline->gs_copy_shader;
5263 }
5264 --index;
5265 }
5266 }
5267
5268 *stage = -1;
5269 return NULL;
5270 }
5271
5272 /* Basically strlcpy (which does not exist on linux) specialized for
5273 * descriptions. */
5274 static void desc_copy(char *desc, const char *src) {
5275 int len = strlen(src);
5276 assert(len < VK_MAX_DESCRIPTION_SIZE);
5277 memcpy(desc, src, len);
5278 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5279 }
5280
5281 VkResult radv_GetPipelineExecutablePropertiesKHR(
5282 VkDevice _device,
5283 const VkPipelineInfoKHR* pPipelineInfo,
5284 uint32_t* pExecutableCount,
5285 VkPipelineExecutablePropertiesKHR* pProperties)
5286 {
5287 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5288 const uint32_t total_count = radv_get_executable_count(pipeline);
5289
5290 if (!pProperties) {
5291 *pExecutableCount = total_count;
5292 return VK_SUCCESS;
5293 }
5294
5295 const uint32_t count = MIN2(total_count, *pExecutableCount);
5296 for (unsigned i = 0, executable_idx = 0;
5297 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5298 if (!pipeline->shaders[i])
5299 continue;
5300 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5301 const char *name = NULL;
5302 const char *description = NULL;
5303 switch(i) {
5304 case MESA_SHADER_VERTEX:
5305 name = "Vertex Shader";
5306 description = "Vulkan Vertex Shader";
5307 break;
5308 case MESA_SHADER_TESS_CTRL:
5309 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5310 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5311 name = "Vertex + Tessellation Control Shaders";
5312 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5313 } else {
5314 name = "Tessellation Control Shader";
5315 description = "Vulkan Tessellation Control Shader";
5316 }
5317 break;
5318 case MESA_SHADER_TESS_EVAL:
5319 name = "Tessellation Evaluation Shader";
5320 description = "Vulkan Tessellation Evaluation Shader";
5321 break;
5322 case MESA_SHADER_GEOMETRY:
5323 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5324 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5325 name = "Tessellation Evaluation + Geometry Shaders";
5326 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5327 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5328 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5329 name = "Vertex + Geometry Shader";
5330 description = "Combined Vulkan Vertex and Geometry Shaders";
5331 } else {
5332 name = "Geometry Shader";
5333 description = "Vulkan Geometry Shader";
5334 }
5335 break;
5336 case MESA_SHADER_FRAGMENT:
5337 name = "Fragment Shader";
5338 description = "Vulkan Fragment Shader";
5339 break;
5340 case MESA_SHADER_COMPUTE:
5341 name = "Compute Shader";
5342 description = "Vulkan Compute Shader";
5343 break;
5344 }
5345
5346 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5347 desc_copy(pProperties[executable_idx].name, name);
5348 desc_copy(pProperties[executable_idx].description, description);
5349
5350 ++executable_idx;
5351 if (i == MESA_SHADER_GEOMETRY &&
5352 !radv_pipeline_has_ngg(pipeline)) {
5353 assert(pipeline->gs_copy_shader);
5354 if (executable_idx >= count)
5355 break;
5356
5357 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5358 pProperties[executable_idx].subgroupSize = 64;
5359 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5360 desc_copy(pProperties[executable_idx].description,
5361 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5362
5363 ++executable_idx;
5364 }
5365 }
5366
5367 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5368 *pExecutableCount = count;
5369 return result;
5370 }
5371
5372 VkResult radv_GetPipelineExecutableStatisticsKHR(
5373 VkDevice _device,
5374 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5375 uint32_t* pStatisticCount,
5376 VkPipelineExecutableStatisticKHR* pStatistics)
5377 {
5378 RADV_FROM_HANDLE(radv_device, device, _device);
5379 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5380 gl_shader_stage stage;
5381 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5382
5383 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5384 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5385 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5386
5387 VkPipelineExecutableStatisticKHR *s = pStatistics;
5388 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5389 VkResult result = VK_SUCCESS;
5390
5391 if (s < end) {
5392 desc_copy(s->name, "SGPRs");
5393 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5394 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5395 s->value.u64 = shader->config.num_sgprs;
5396 }
5397 ++s;
5398
5399 if (s < end) {
5400 desc_copy(s->name, "VGPRs");
5401 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5402 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5403 s->value.u64 = shader->config.num_vgprs;
5404 }
5405 ++s;
5406
5407 if (s < end) {
5408 desc_copy(s->name, "Spilled SGPRs");
5409 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5410 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5411 s->value.u64 = shader->config.spilled_sgprs;
5412 }
5413 ++s;
5414
5415 if (s < end) {
5416 desc_copy(s->name, "Spilled VGPRs");
5417 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5418 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5419 s->value.u64 = shader->config.spilled_vgprs;
5420 }
5421 ++s;
5422
5423 if (s < end) {
5424 desc_copy(s->name, "PrivMem VGPRs");
5425 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5426 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5427 s->value.u64 = shader->info.private_mem_vgprs;
5428 }
5429 ++s;
5430
5431 if (s < end) {
5432 desc_copy(s->name, "Code size");
5433 desc_copy(s->description, "Code size in bytes");
5434 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5435 s->value.u64 = shader->exec_size;
5436 }
5437 ++s;
5438
5439 if (s < end) {
5440 desc_copy(s->name, "LDS size");
5441 desc_copy(s->description, "LDS size in bytes per workgroup");
5442 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5443 s->value.u64 = shader->config.lds_size * lds_increment;
5444 }
5445 ++s;
5446
5447 if (s < end) {
5448 desc_copy(s->name, "Scratch size");
5449 desc_copy(s->description, "Private memory in bytes per subgroup");
5450 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5451 s->value.u64 = shader->config.scratch_bytes_per_wave;
5452 }
5453 ++s;
5454
5455 if (s < end) {
5456 desc_copy(s->name, "Subgroups per SIMD");
5457 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5458 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5459 s->value.u64 = max_waves;
5460 }
5461 ++s;
5462
5463 if (shader->statistics) {
5464 for (unsigned i = 0; i < shader->statistics->count; i++) {
5465 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5466 uint32_t value = shader->statistics->values[i];
5467 if (s < end) {
5468 desc_copy(s->name, info->name);
5469 desc_copy(s->description, info->desc);
5470 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5471 s->value.u64 = value;
5472 }
5473 ++s;
5474 }
5475 }
5476
5477 if (!pStatistics)
5478 *pStatisticCount = s - pStatistics;
5479 else if (s > end) {
5480 *pStatisticCount = end - pStatistics;
5481 result = VK_INCOMPLETE;
5482 } else {
5483 *pStatisticCount = s - pStatistics;
5484 }
5485
5486 return result;
5487 }
5488
5489 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5490 {
5491 size_t total_size = strlen(src) + 1;
5492
5493 if (!data) {
5494 *data_size = total_size;
5495 return VK_SUCCESS;
5496 }
5497
5498 size_t size = MIN2(total_size, *data_size);
5499
5500 memcpy(data, src, size);
5501 if (size)
5502 *((char*)data + size - 1) = 0;
5503 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5504 }
5505
5506 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5507 VkDevice device,
5508 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5509 uint32_t* pInternalRepresentationCount,
5510 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5511 {
5512 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5513 gl_shader_stage stage;
5514 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5515
5516 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5517 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5518 VkResult result = VK_SUCCESS;
5519 /* optimized NIR */
5520 if (p < end) {
5521 p->isText = true;
5522 desc_copy(p->name, "NIR Shader(s)");
5523 desc_copy(p->description, "The optimized NIR shader(s)");
5524 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5525 result = VK_INCOMPLETE;
5526 }
5527 ++p;
5528
5529 /* backend IR */
5530 if (p < end) {
5531 p->isText = true;
5532 if (pipeline->device->physical_device->use_llvm) {
5533 desc_copy(p->name, "LLVM IR");
5534 desc_copy(p->description, "The LLVM IR after some optimizations");
5535 } else {
5536 desc_copy(p->name, "ACO IR");
5537 desc_copy(p->description, "The ACO IR after some optimizations");
5538 }
5539 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5540 result = VK_INCOMPLETE;
5541 }
5542 ++p;
5543
5544 /* Disassembler */
5545 if (p < end) {
5546 p->isText = true;
5547 desc_copy(p->name, "Assembly");
5548 desc_copy(p->description, "Final Assembly");
5549 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5550 result = VK_INCOMPLETE;
5551 }
5552 ++p;
5553
5554 if (!pInternalRepresentations)
5555 *pInternalRepresentationCount = p - pInternalRepresentations;
5556 else if(p > end) {
5557 result = VK_INCOMPLETE;
5558 *pInternalRepresentationCount = end - pInternalRepresentations;
5559 } else {
5560 *pInternalRepresentationCount = p - pInternalRepresentations;
5561 }
5562
5563 return result;
5564 }