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radv: add support for push constants inlining when possible
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 static void
101 radv_pipeline_destroy(struct radv_device *device,
102 struct radv_pipeline *pipeline,
103 const VkAllocationCallbacks* allocator)
104 {
105 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
106 if (pipeline->shaders[i])
107 radv_shader_variant_destroy(device, pipeline->shaders[i]);
108
109 if (pipeline->gs_copy_shader)
110 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
111
112 if(pipeline->cs.buf)
113 free(pipeline->cs.buf);
114 vk_free2(&device->alloc, allocator, pipeline);
115 }
116
117 void radv_DestroyPipeline(
118 VkDevice _device,
119 VkPipeline _pipeline,
120 const VkAllocationCallbacks* pAllocator)
121 {
122 RADV_FROM_HANDLE(radv_device, device, _device);
123 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
124
125 if (!_pipeline)
126 return;
127
128 radv_pipeline_destroy(device, pipeline, pAllocator);
129 }
130
131 static uint32_t get_hash_flags(struct radv_device *device)
132 {
133 uint32_t hash_flags = 0;
134
135 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
136 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
137 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
138 hash_flags |= RADV_HASH_SHADER_SISCHED;
139 return hash_flags;
140 }
141
142 static VkResult
143 radv_pipeline_scratch_init(struct radv_device *device,
144 struct radv_pipeline *pipeline)
145 {
146 unsigned scratch_bytes_per_wave = 0;
147 unsigned max_waves = 0;
148 unsigned min_waves = 1;
149
150 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
151 if (pipeline->shaders[i]) {
152 unsigned max_stage_waves = device->scratch_waves;
153
154 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
155 pipeline->shaders[i]->config.scratch_bytes_per_wave);
156
157 max_stage_waves = MIN2(max_stage_waves,
158 4 * device->physical_device->rad_info.num_good_compute_units *
159 (256 / pipeline->shaders[i]->config.num_vgprs));
160 max_waves = MAX2(max_waves, max_stage_waves);
161 }
162 }
163
164 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
165 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
167 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
168 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
169 }
170
171 if (scratch_bytes_per_wave)
172 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
173
174 if (scratch_bytes_per_wave && max_waves < min_waves) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
178 }
179 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
180 pipeline->max_waves = max_waves;
181 return VK_SUCCESS;
182 }
183
184 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
185 {
186 switch (op) {
187 case VK_LOGIC_OP_CLEAR:
188 return V_028808_ROP3_CLEAR;
189 case VK_LOGIC_OP_AND:
190 return V_028808_ROP3_AND;
191 case VK_LOGIC_OP_AND_REVERSE:
192 return V_028808_ROP3_AND_REVERSE;
193 case VK_LOGIC_OP_COPY:
194 return V_028808_ROP3_COPY;
195 case VK_LOGIC_OP_AND_INVERTED:
196 return V_028808_ROP3_AND_INVERTED;
197 case VK_LOGIC_OP_NO_OP:
198 return V_028808_ROP3_NO_OP;
199 case VK_LOGIC_OP_XOR:
200 return V_028808_ROP3_XOR;
201 case VK_LOGIC_OP_OR:
202 return V_028808_ROP3_OR;
203 case VK_LOGIC_OP_NOR:
204 return V_028808_ROP3_NOR;
205 case VK_LOGIC_OP_EQUIVALENT:
206 return V_028808_ROP3_EQUIVALENT;
207 case VK_LOGIC_OP_INVERT:
208 return V_028808_ROP3_INVERT;
209 case VK_LOGIC_OP_OR_REVERSE:
210 return V_028808_ROP3_OR_REVERSE;
211 case VK_LOGIC_OP_COPY_INVERTED:
212 return V_028808_ROP3_COPY_INVERTED;
213 case VK_LOGIC_OP_OR_INVERTED:
214 return V_028808_ROP3_OR_INVERTED;
215 case VK_LOGIC_OP_NAND:
216 return V_028808_ROP3_NAND;
217 case VK_LOGIC_OP_SET:
218 return V_028808_ROP3_SET;
219 default:
220 unreachable("Unhandled logic op");
221 }
222 }
223
224
225 static uint32_t si_translate_blend_function(VkBlendOp op)
226 {
227 switch (op) {
228 case VK_BLEND_OP_ADD:
229 return V_028780_COMB_DST_PLUS_SRC;
230 case VK_BLEND_OP_SUBTRACT:
231 return V_028780_COMB_SRC_MINUS_DST;
232 case VK_BLEND_OP_REVERSE_SUBTRACT:
233 return V_028780_COMB_DST_MINUS_SRC;
234 case VK_BLEND_OP_MIN:
235 return V_028780_COMB_MIN_DST_SRC;
236 case VK_BLEND_OP_MAX:
237 return V_028780_COMB_MAX_DST_SRC;
238 default:
239 return 0;
240 }
241 }
242
243 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
244 {
245 switch (factor) {
246 case VK_BLEND_FACTOR_ZERO:
247 return V_028780_BLEND_ZERO;
248 case VK_BLEND_FACTOR_ONE:
249 return V_028780_BLEND_ONE;
250 case VK_BLEND_FACTOR_SRC_COLOR:
251 return V_028780_BLEND_SRC_COLOR;
252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
254 case VK_BLEND_FACTOR_DST_COLOR:
255 return V_028780_BLEND_DST_COLOR;
256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
257 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
258 case VK_BLEND_FACTOR_SRC_ALPHA:
259 return V_028780_BLEND_SRC_ALPHA;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
262 case VK_BLEND_FACTOR_DST_ALPHA:
263 return V_028780_BLEND_DST_ALPHA;
264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
266 case VK_BLEND_FACTOR_CONSTANT_COLOR:
267 return V_028780_BLEND_CONSTANT_COLOR;
268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
270 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
271 return V_028780_BLEND_CONSTANT_ALPHA;
272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
275 return V_028780_BLEND_SRC_ALPHA_SATURATE;
276 case VK_BLEND_FACTOR_SRC1_COLOR:
277 return V_028780_BLEND_SRC1_COLOR;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
279 return V_028780_BLEND_INV_SRC1_COLOR;
280 case VK_BLEND_FACTOR_SRC1_ALPHA:
281 return V_028780_BLEND_SRC1_ALPHA;
282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
283 return V_028780_BLEND_INV_SRC1_ALPHA;
284 default:
285 return 0;
286 }
287 }
288
289 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
290 {
291 switch (op) {
292 case VK_BLEND_OP_ADD:
293 return V_028760_OPT_COMB_ADD;
294 case VK_BLEND_OP_SUBTRACT:
295 return V_028760_OPT_COMB_SUBTRACT;
296 case VK_BLEND_OP_REVERSE_SUBTRACT:
297 return V_028760_OPT_COMB_REVSUBTRACT;
298 case VK_BLEND_OP_MIN:
299 return V_028760_OPT_COMB_MIN;
300 case VK_BLEND_OP_MAX:
301 return V_028760_OPT_COMB_MAX;
302 default:
303 return V_028760_OPT_COMB_BLEND_DISABLED;
304 }
305 }
306
307 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
308 {
309 switch (factor) {
310 case VK_BLEND_FACTOR_ZERO:
311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
312 case VK_BLEND_FACTOR_ONE:
313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
314 case VK_BLEND_FACTOR_SRC_COLOR:
315 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
318 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
320 case VK_BLEND_FACTOR_SRC_ALPHA:
321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
327 default:
328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
329 }
330 }
331
332 /**
333 * Get rid of DST in the blend factors by commuting the operands:
334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
335 */
336 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
337 unsigned *dst_factor, unsigned expected_dst,
338 unsigned replacement_src)
339 {
340 if (*src_factor == expected_dst &&
341 *dst_factor == VK_BLEND_FACTOR_ZERO) {
342 *src_factor = VK_BLEND_FACTOR_ZERO;
343 *dst_factor = replacement_src;
344
345 /* Commuting the operands requires reversing subtractions. */
346 if (*func == VK_BLEND_OP_SUBTRACT)
347 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
348 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
349 *func = VK_BLEND_OP_SUBTRACT;
350 }
351 }
352
353 static bool si_blend_factor_uses_dst(unsigned factor)
354 {
355 return factor == VK_BLEND_FACTOR_DST_COLOR ||
356 factor == VK_BLEND_FACTOR_DST_ALPHA ||
357 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
358 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
359 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
360 }
361
362 static bool is_dual_src(VkBlendFactor factor)
363 {
364 switch (factor) {
365 case VK_BLEND_FACTOR_SRC1_COLOR:
366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
367 case VK_BLEND_FACTOR_SRC1_ALPHA:
368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
369 return true;
370 default:
371 return false;
372 }
373 }
374
375 static unsigned si_choose_spi_color_format(VkFormat vk_format,
376 bool blend_enable,
377 bool blend_need_alpha)
378 {
379 const struct vk_format_description *desc = vk_format_description(vk_format);
380 unsigned format, ntype, swap;
381
382 /* Alpha is needed for alpha-to-coverage.
383 * Blending may be with or without alpha.
384 */
385 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
386 unsigned alpha = 0; /* exports alpha, but may not support blending */
387 unsigned blend = 0; /* supports blending, but may not export alpha */
388 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
389
390 format = radv_translate_colorformat(vk_format);
391 ntype = radv_translate_color_numformat(vk_format, desc,
392 vk_format_get_first_non_void_channel(vk_format));
393 swap = radv_translate_colorswap(vk_format, false);
394
395 /* Choose the SPI color formats. These are required values for Stoney/RB+.
396 * Other chips have multiple choices, though they are not necessarily better.
397 */
398 switch (format) {
399 case V_028C70_COLOR_5_6_5:
400 case V_028C70_COLOR_1_5_5_5:
401 case V_028C70_COLOR_5_5_5_1:
402 case V_028C70_COLOR_4_4_4_4:
403 case V_028C70_COLOR_10_11_11:
404 case V_028C70_COLOR_11_11_10:
405 case V_028C70_COLOR_8:
406 case V_028C70_COLOR_8_8:
407 case V_028C70_COLOR_8_8_8_8:
408 case V_028C70_COLOR_10_10_10_2:
409 case V_028C70_COLOR_2_10_10_10:
410 if (ntype == V_028C70_NUMBER_UINT)
411 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
412 else if (ntype == V_028C70_NUMBER_SINT)
413 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
414 else
415 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
416 break;
417
418 case V_028C70_COLOR_16:
419 case V_028C70_COLOR_16_16:
420 case V_028C70_COLOR_16_16_16_16:
421 if (ntype == V_028C70_NUMBER_UNORM ||
422 ntype == V_028C70_NUMBER_SNORM) {
423 /* UNORM16 and SNORM16 don't support blending */
424 if (ntype == V_028C70_NUMBER_UNORM)
425 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
426 else
427 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
428
429 /* Use 32 bits per channel for blending. */
430 if (format == V_028C70_COLOR_16) {
431 if (swap == V_028C70_SWAP_STD) { /* R */
432 blend = V_028714_SPI_SHADER_32_R;
433 blend_alpha = V_028714_SPI_SHADER_32_AR;
434 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
435 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
436 else
437 assert(0);
438 } else if (format == V_028C70_COLOR_16_16) {
439 if (swap == V_028C70_SWAP_STD) { /* RG */
440 blend = V_028714_SPI_SHADER_32_GR;
441 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
442 } else if (swap == V_028C70_SWAP_ALT) /* RA */
443 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
444 else
445 assert(0);
446 } else /* 16_16_16_16 */
447 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
448 } else if (ntype == V_028C70_NUMBER_UINT)
449 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
450 else if (ntype == V_028C70_NUMBER_SINT)
451 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
452 else if (ntype == V_028C70_NUMBER_FLOAT)
453 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
454 else
455 assert(0);
456 break;
457
458 case V_028C70_COLOR_32:
459 if (swap == V_028C70_SWAP_STD) { /* R */
460 blend = normal = V_028714_SPI_SHADER_32_R;
461 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
462 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
463 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
464 else
465 assert(0);
466 break;
467
468 case V_028C70_COLOR_32_32:
469 if (swap == V_028C70_SWAP_STD) { /* RG */
470 blend = normal = V_028714_SPI_SHADER_32_GR;
471 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
472 } else if (swap == V_028C70_SWAP_ALT) /* RA */
473 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
474 else
475 assert(0);
476 break;
477
478 case V_028C70_COLOR_32_32_32_32:
479 case V_028C70_COLOR_8_24:
480 case V_028C70_COLOR_24_8:
481 case V_028C70_COLOR_X24_8_32_FLOAT:
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
483 break;
484
485 default:
486 unreachable("unhandled blend format");
487 }
488
489 if (blend_enable && blend_need_alpha)
490 return blend_alpha;
491 else if(blend_need_alpha)
492 return alpha;
493 else if(blend_enable)
494 return blend;
495 else
496 return normal;
497 }
498
499 static void
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
502 struct radv_blend_state *blend)
503 {
504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
506 unsigned col_format = 0;
507 unsigned num_targets;
508
509 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
510 unsigned cf;
511
512 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
513 cf = V_028714_SPI_SHADER_ZERO;
514 } else {
515 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
516 bool blend_enable =
517 blend->blend_enable_4bit & (0xfu << (i * 4));
518
519 cf = si_choose_spi_color_format(attachment->format,
520 blend_enable,
521 blend->need_src_alpha & (1 << i));
522 }
523
524 col_format |= cf << (4 * i);
525 }
526
527 /* If the i-th target format is set, all previous target formats must
528 * be non-zero to avoid hangs.
529 */
530 num_targets = (util_last_bit(col_format) + 3) / 4;
531 for (unsigned i = 0; i < num_targets; i++) {
532 if (!(col_format & (0xf << (i * 4)))) {
533 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
534 }
535 }
536
537 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
538
539 if (blend->mrt0_is_dual_src)
540 col_format |= (col_format & 0xf) << 4;
541 blend->spi_shader_col_format = col_format;
542 }
543
544 static bool
545 format_is_int8(VkFormat format)
546 {
547 const struct vk_format_description *desc = vk_format_description(format);
548 int channel = vk_format_get_first_non_void_channel(format);
549
550 return channel >= 0 && desc->channel[channel].pure_integer &&
551 desc->channel[channel].size == 8;
552 }
553
554 static bool
555 format_is_int10(VkFormat format)
556 {
557 const struct vk_format_description *desc = vk_format_description(format);
558
559 if (desc->nr_channels != 4)
560 return false;
561 for (unsigned i = 0; i < 4; i++) {
562 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
563 return true;
564 }
565 return false;
566 }
567
568 /*
569 * Ordered so that for each i,
570 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
571 */
572 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
573 VK_FORMAT_R32_SFLOAT,
574 VK_FORMAT_R32G32_SFLOAT,
575 VK_FORMAT_R8G8B8A8_UNORM,
576 VK_FORMAT_R16G16B16A16_UNORM,
577 VK_FORMAT_R16G16B16A16_SNORM,
578 VK_FORMAT_R16G16B16A16_UINT,
579 VK_FORMAT_R16G16B16A16_SINT,
580 VK_FORMAT_R32G32B32A32_SFLOAT,
581 VK_FORMAT_R8G8B8A8_UINT,
582 VK_FORMAT_R8G8B8A8_SINT,
583 VK_FORMAT_A2R10G10B10_UINT_PACK32,
584 VK_FORMAT_A2R10G10B10_SINT_PACK32,
585 };
586
587 unsigned radv_format_meta_fs_key(VkFormat format)
588 {
589 unsigned col_format = si_choose_spi_color_format(format, false, false);
590
591 assert(col_format != V_028714_SPI_SHADER_32_AR);
592 if (col_format >= V_028714_SPI_SHADER_32_AR)
593 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
594
595 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
596 bool is_int8 = format_is_int8(format);
597 bool is_int10 = format_is_int10(format);
598
599 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
600 }
601
602 static void
603 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
604 unsigned *is_int8, unsigned *is_int10)
605 {
606 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
607 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
608 *is_int8 = 0;
609 *is_int10 = 0;
610
611 for (unsigned i = 0; i < subpass->color_count; ++i) {
612 struct radv_render_pass_attachment *attachment;
613
614 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
615 continue;
616
617 attachment = pass->attachments + subpass->color_attachments[i].attachment;
618
619 if (format_is_int8(attachment->format))
620 *is_int8 |= 1 << i;
621 if (format_is_int10(attachment->format))
622 *is_int10 |= 1 << i;
623 }
624 }
625
626 static void
627 radv_blend_check_commutativity(struct radv_blend_state *blend,
628 VkBlendOp op, VkBlendFactor src,
629 VkBlendFactor dst, unsigned chanmask)
630 {
631 /* Src factor is allowed when it does not depend on Dst. */
632 static const uint32_t src_allowed =
633 (1u << VK_BLEND_FACTOR_ONE) |
634 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
635 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
636 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
637 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
638 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
639 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
640 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
641 (1u << VK_BLEND_FACTOR_ZERO) |
642 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
643 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
644 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
645 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
646 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
647 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
648
649 if (dst == VK_BLEND_FACTOR_ONE &&
650 (src_allowed & (1u << src))) {
651 /* Addition is commutative, but floating point addition isn't
652 * associative: subtle changes can be introduced via different
653 * rounding. Be conservative, only enable for min and max.
654 */
655 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
656 blend->commutative_4bit |= chanmask;
657 }
658 }
659
660 static struct radv_blend_state
661 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
662 const VkGraphicsPipelineCreateInfo *pCreateInfo,
663 const struct radv_graphics_pipeline_create_info *extra)
664 {
665 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
666 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
667 struct radv_blend_state blend = {0};
668 unsigned mode = V_028808_CB_NORMAL;
669 int i;
670
671 if (!vkblend)
672 return blend;
673
674 if (extra && extra->custom_blend_mode) {
675 blend.single_cb_enable = true;
676 mode = extra->custom_blend_mode;
677 }
678 blend.cb_color_control = 0;
679 if (vkblend->logicOpEnable)
680 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
681 else
682 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
683
684 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
685 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
686 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
687 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
688 S_028B70_OFFSET_ROUND(1);
689
690 if (vkms && vkms->alphaToCoverageEnable) {
691 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
692 }
693
694 blend.cb_target_mask = 0;
695 for (i = 0; i < vkblend->attachmentCount; i++) {
696 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
697 unsigned blend_cntl = 0;
698 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
699 VkBlendOp eqRGB = att->colorBlendOp;
700 VkBlendFactor srcRGB = att->srcColorBlendFactor;
701 VkBlendFactor dstRGB = att->dstColorBlendFactor;
702 VkBlendOp eqA = att->alphaBlendOp;
703 VkBlendFactor srcA = att->srcAlphaBlendFactor;
704 VkBlendFactor dstA = att->dstAlphaBlendFactor;
705
706 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
707
708 if (!att->colorWriteMask)
709 continue;
710
711 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
712 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
713 if (!att->blendEnable) {
714 blend.cb_blend_control[i] = blend_cntl;
715 continue;
716 }
717
718 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
719 if (i == 0)
720 blend.mrt0_is_dual_src = true;
721
722 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
723 srcRGB = VK_BLEND_FACTOR_ONE;
724 dstRGB = VK_BLEND_FACTOR_ONE;
725 }
726 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
727 srcA = VK_BLEND_FACTOR_ONE;
728 dstA = VK_BLEND_FACTOR_ONE;
729 }
730
731 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
732 0x7 << (4 * i));
733 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
734 0x8 << (4 * i));
735
736 /* Blending optimizations for RB+.
737 * These transformations don't change the behavior.
738 *
739 * First, get rid of DST in the blend factors:
740 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
741 */
742 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
743 VK_BLEND_FACTOR_DST_COLOR,
744 VK_BLEND_FACTOR_SRC_COLOR);
745
746 si_blend_remove_dst(&eqA, &srcA, &dstA,
747 VK_BLEND_FACTOR_DST_COLOR,
748 VK_BLEND_FACTOR_SRC_COLOR);
749
750 si_blend_remove_dst(&eqA, &srcA, &dstA,
751 VK_BLEND_FACTOR_DST_ALPHA,
752 VK_BLEND_FACTOR_SRC_ALPHA);
753
754 /* Look up the ideal settings from tables. */
755 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
756 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
757 srcA_opt = si_translate_blend_opt_factor(srcA, true);
758 dstA_opt = si_translate_blend_opt_factor(dstA, true);
759
760 /* Handle interdependencies. */
761 if (si_blend_factor_uses_dst(srcRGB))
762 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
763 if (si_blend_factor_uses_dst(srcA))
764 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
765
766 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
767 (dstRGB == VK_BLEND_FACTOR_ZERO ||
768 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
769 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
770 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
771
772 /* Set the final value. */
773 blend.sx_mrt_blend_opt[i] =
774 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
775 S_028760_COLOR_DST_OPT(dstRGB_opt) |
776 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
777 S_028760_ALPHA_SRC_OPT(srcA_opt) |
778 S_028760_ALPHA_DST_OPT(dstA_opt) |
779 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
780 blend_cntl |= S_028780_ENABLE(1);
781
782 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
783 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
784 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
785 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
786 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
787 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
788 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
789 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
790 }
791 blend.cb_blend_control[i] = blend_cntl;
792
793 blend.blend_enable_4bit |= 0xfu << (i * 4);
794
795 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
796 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
797 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
798 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
799 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
800 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
801 blend.need_src_alpha |= 1 << i;
802 }
803 for (i = vkblend->attachmentCount; i < 8; i++) {
804 blend.cb_blend_control[i] = 0;
805 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
806 }
807
808 if (pipeline->device->physical_device->has_rbplus) {
809 /* Disable RB+ blend optimizations for dual source blending. */
810 if (blend.mrt0_is_dual_src) {
811 for (i = 0; i < 8; i++) {
812 blend.sx_mrt_blend_opt[i] =
813 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
814 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
815 }
816 }
817
818 /* RB+ doesn't work with dual source blending, logic op and
819 * RESOLVE.
820 */
821 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
822 mode == V_028808_CB_RESOLVE)
823 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
824 }
825
826 if (blend.cb_target_mask)
827 blend.cb_color_control |= S_028808_MODE(mode);
828 else
829 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
830
831 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
832 return blend;
833 }
834
835 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
836 {
837 switch (op) {
838 case VK_STENCIL_OP_KEEP:
839 return V_02842C_STENCIL_KEEP;
840 case VK_STENCIL_OP_ZERO:
841 return V_02842C_STENCIL_ZERO;
842 case VK_STENCIL_OP_REPLACE:
843 return V_02842C_STENCIL_REPLACE_TEST;
844 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
845 return V_02842C_STENCIL_ADD_CLAMP;
846 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
847 return V_02842C_STENCIL_SUB_CLAMP;
848 case VK_STENCIL_OP_INVERT:
849 return V_02842C_STENCIL_INVERT;
850 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
851 return V_02842C_STENCIL_ADD_WRAP;
852 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
853 return V_02842C_STENCIL_SUB_WRAP;
854 default:
855 return 0;
856 }
857 }
858
859 static uint32_t si_translate_fill(VkPolygonMode func)
860 {
861 switch(func) {
862 case VK_POLYGON_MODE_FILL:
863 return V_028814_X_DRAW_TRIANGLES;
864 case VK_POLYGON_MODE_LINE:
865 return V_028814_X_DRAW_LINES;
866 case VK_POLYGON_MODE_POINT:
867 return V_028814_X_DRAW_POINTS;
868 default:
869 assert(0);
870 return V_028814_X_DRAW_POINTS;
871 }
872 }
873
874 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
875 {
876 uint32_t num_samples = vkms->rasterizationSamples;
877 uint32_t ps_iter_samples = 1;
878
879 if (vkms->sampleShadingEnable) {
880 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
881 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
882 }
883 return ps_iter_samples;
884 }
885
886 static bool
887 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
888 {
889 return pCreateInfo->depthTestEnable &&
890 pCreateInfo->depthWriteEnable &&
891 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
892 }
893
894 static bool
895 radv_writes_stencil(const VkStencilOpState *state)
896 {
897 return state->writeMask &&
898 (state->failOp != VK_STENCIL_OP_KEEP ||
899 state->passOp != VK_STENCIL_OP_KEEP ||
900 state->depthFailOp != VK_STENCIL_OP_KEEP);
901 }
902
903 static bool
904 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
905 {
906 return pCreateInfo->stencilTestEnable &&
907 (radv_writes_stencil(&pCreateInfo->front) ||
908 radv_writes_stencil(&pCreateInfo->back));
909 }
910
911 static bool
912 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
913 {
914 return radv_is_depth_write_enabled(pCreateInfo) ||
915 radv_is_stencil_write_enabled(pCreateInfo);
916 }
917
918 static bool
919 radv_order_invariant_stencil_op(VkStencilOp op)
920 {
921 /* REPLACE is normally order invariant, except when the stencil
922 * reference value is written by the fragment shader. Tracking this
923 * interaction does not seem worth the effort, so be conservative.
924 */
925 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
926 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
927 op != VK_STENCIL_OP_REPLACE;
928 }
929
930 static bool
931 radv_order_invariant_stencil_state(const VkStencilOpState *state)
932 {
933 /* Compute whether, assuming Z writes are disabled, this stencil state
934 * is order invariant in the sense that the set of passing fragments as
935 * well as the final stencil buffer result does not depend on the order
936 * of fragments.
937 */
938 return !state->writeMask ||
939 /* The following assumes that Z writes are disabled. */
940 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
941 radv_order_invariant_stencil_op(state->passOp) &&
942 radv_order_invariant_stencil_op(state->depthFailOp)) ||
943 (state->compareOp == VK_COMPARE_OP_NEVER &&
944 radv_order_invariant_stencil_op(state->failOp));
945 }
946
947 static bool
948 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
949 struct radv_blend_state *blend,
950 const VkGraphicsPipelineCreateInfo *pCreateInfo)
951 {
952 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
953 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
954 unsigned colormask = blend->cb_target_enabled_4bit;
955
956 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
957 return false;
958
959 /* Be conservative if a logic operation is enabled with color buffers. */
960 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
961 return false;
962
963 /* Default depth/stencil invariance when no attachment is bound. */
964 struct radv_dsa_order_invariance dsa_order_invariant = {
965 .zs = true, .pass_set = true
966 };
967
968 if (pCreateInfo->pDepthStencilState &&
969 subpass->depth_stencil_attachment) {
970 const VkPipelineDepthStencilStateCreateInfo *vkds =
971 pCreateInfo->pDepthStencilState;
972 struct radv_render_pass_attachment *attachment =
973 pass->attachments + subpass->depth_stencil_attachment->attachment;
974 bool has_stencil = vk_format_is_stencil(attachment->format);
975 struct radv_dsa_order_invariance order_invariance[2];
976 struct radv_shader_variant *ps =
977 pipeline->shaders[MESA_SHADER_FRAGMENT];
978
979 /* Compute depth/stencil order invariance in order to know if
980 * it's safe to enable out-of-order.
981 */
982 bool zfunc_is_ordered =
983 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
984 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
985 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
986 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
987 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
988
989 bool nozwrite_and_order_invariant_stencil =
990 !radv_is_ds_write_enabled(vkds) ||
991 (!radv_is_depth_write_enabled(vkds) &&
992 radv_order_invariant_stencil_state(&vkds->front) &&
993 radv_order_invariant_stencil_state(&vkds->back));
994
995 order_invariance[1].zs =
996 nozwrite_and_order_invariant_stencil ||
997 (!radv_is_stencil_write_enabled(vkds) &&
998 zfunc_is_ordered);
999 order_invariance[0].zs =
1000 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1001
1002 order_invariance[1].pass_set =
1003 nozwrite_and_order_invariant_stencil ||
1004 (!radv_is_stencil_write_enabled(vkds) &&
1005 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1006 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1007 order_invariance[0].pass_set =
1008 !radv_is_depth_write_enabled(vkds) ||
1009 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1010 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1011
1012 dsa_order_invariant = order_invariance[has_stencil];
1013 if (!dsa_order_invariant.zs)
1014 return false;
1015
1016 /* The set of PS invocations is always order invariant,
1017 * except when early Z/S tests are requested.
1018 */
1019 if (ps &&
1020 ps->info.info.ps.writes_memory &&
1021 ps->info.fs.early_fragment_test &&
1022 !dsa_order_invariant.pass_set)
1023 return false;
1024
1025 /* Determine if out-of-order rasterization should be disabled
1026 * when occlusion queries are used.
1027 */
1028 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1029 !dsa_order_invariant.pass_set;
1030 }
1031
1032 /* No color buffers are enabled for writing. */
1033 if (!colormask)
1034 return true;
1035
1036 unsigned blendmask = colormask & blend->blend_enable_4bit;
1037
1038 if (blendmask) {
1039 /* Only commutative blending. */
1040 if (blendmask & ~blend->commutative_4bit)
1041 return false;
1042
1043 if (!dsa_order_invariant.pass_set)
1044 return false;
1045 }
1046
1047 if (colormask & ~blendmask)
1048 return false;
1049
1050 return true;
1051 }
1052
1053 static void
1054 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1055 struct radv_blend_state *blend,
1056 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1057 {
1058 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1059 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1060 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1061 bool out_of_order_rast = false;
1062 int ps_iter_samples = 1;
1063 uint32_t mask = 0xffff;
1064
1065 if (vkms)
1066 ms->num_samples = vkms->rasterizationSamples;
1067 else
1068 ms->num_samples = 1;
1069
1070 if (vkms)
1071 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1072 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1073 ps_iter_samples = ms->num_samples;
1074 }
1075
1076 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1077 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1078 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1079 /* Out-of-order rasterization is explicitly enabled by the
1080 * application.
1081 */
1082 out_of_order_rast = true;
1083 } else {
1084 /* Determine if the driver can enable out-of-order
1085 * rasterization internally.
1086 */
1087 out_of_order_rast =
1088 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1089 }
1090
1091 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1092 ms->pa_sc_aa_config = 0;
1093 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1094 S_028804_INCOHERENT_EQAA_READS(1) |
1095 S_028804_INTERPOLATE_COMP_Z(1) |
1096 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1097 ms->pa_sc_mode_cntl_1 =
1098 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1099 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1100 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1101 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1102 /* always 1: */
1103 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1104 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1105 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1106 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1107 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1108 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1109 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1110 S_028A48_VPORT_SCISSOR_ENABLE(1);
1111
1112 if (ms->num_samples > 1) {
1113 unsigned log_samples = util_logbase2(ms->num_samples);
1114 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1115 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1116 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1117 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1118 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1119 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1120 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1121 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1122 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1123 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1124 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1125 if (ps_iter_samples > 1)
1126 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1127 }
1128
1129 if (vkms && vkms->pSampleMask) {
1130 mask = vkms->pSampleMask[0] & 0xffff;
1131 }
1132
1133 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1134 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1135 }
1136
1137 static bool
1138 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1139 {
1140 switch (topology) {
1141 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1142 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1143 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1144 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1145 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1146 return false;
1147 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1148 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1149 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1150 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1151 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1152 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1153 return true;
1154 default:
1155 unreachable("unhandled primitive type");
1156 }
1157 }
1158
1159 static uint32_t
1160 si_translate_prim(enum VkPrimitiveTopology topology)
1161 {
1162 switch (topology) {
1163 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1164 return V_008958_DI_PT_POINTLIST;
1165 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1166 return V_008958_DI_PT_LINELIST;
1167 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1168 return V_008958_DI_PT_LINESTRIP;
1169 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1170 return V_008958_DI_PT_TRILIST;
1171 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1172 return V_008958_DI_PT_TRISTRIP;
1173 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1174 return V_008958_DI_PT_TRIFAN;
1175 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1176 return V_008958_DI_PT_LINELIST_ADJ;
1177 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1178 return V_008958_DI_PT_LINESTRIP_ADJ;
1179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1180 return V_008958_DI_PT_TRILIST_ADJ;
1181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1182 return V_008958_DI_PT_TRISTRIP_ADJ;
1183 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1184 return V_008958_DI_PT_PATCH;
1185 default:
1186 assert(0);
1187 return 0;
1188 }
1189 }
1190
1191 static uint32_t
1192 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1193 {
1194 switch (gl_prim) {
1195 case 0: /* GL_POINTS */
1196 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1197 case 1: /* GL_LINES */
1198 case 3: /* GL_LINE_STRIP */
1199 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1200 case 0x8E7A: /* GL_ISOLINES */
1201 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1202
1203 case 4: /* GL_TRIANGLES */
1204 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1205 case 5: /* GL_TRIANGLE_STRIP */
1206 case 7: /* GL_QUADS */
1207 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1208 default:
1209 assert(0);
1210 return 0;
1211 }
1212 }
1213
1214 static uint32_t
1215 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1216 {
1217 switch (topology) {
1218 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1219 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1220 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1221 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1222 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1223 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1224 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1225 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1228 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1231 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1232 default:
1233 assert(0);
1234 return 0;
1235 }
1236 }
1237
1238 static unsigned si_map_swizzle(unsigned swizzle)
1239 {
1240 switch (swizzle) {
1241 case VK_SWIZZLE_Y:
1242 return V_008F0C_SQ_SEL_Y;
1243 case VK_SWIZZLE_Z:
1244 return V_008F0C_SQ_SEL_Z;
1245 case VK_SWIZZLE_W:
1246 return V_008F0C_SQ_SEL_W;
1247 case VK_SWIZZLE_0:
1248 return V_008F0C_SQ_SEL_0;
1249 case VK_SWIZZLE_1:
1250 return V_008F0C_SQ_SEL_1;
1251 default: /* VK_SWIZZLE_X */
1252 return V_008F0C_SQ_SEL_X;
1253 }
1254 }
1255
1256
1257 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1258 {
1259 switch(state) {
1260 case VK_DYNAMIC_STATE_VIEWPORT:
1261 return RADV_DYNAMIC_VIEWPORT;
1262 case VK_DYNAMIC_STATE_SCISSOR:
1263 return RADV_DYNAMIC_SCISSOR;
1264 case VK_DYNAMIC_STATE_LINE_WIDTH:
1265 return RADV_DYNAMIC_LINE_WIDTH;
1266 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1267 return RADV_DYNAMIC_DEPTH_BIAS;
1268 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1269 return RADV_DYNAMIC_BLEND_CONSTANTS;
1270 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1271 return RADV_DYNAMIC_DEPTH_BOUNDS;
1272 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1273 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1274 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1275 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1276 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1277 return RADV_DYNAMIC_STENCIL_REFERENCE;
1278 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1279 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1280 default:
1281 unreachable("Unhandled dynamic state");
1282 }
1283 }
1284
1285 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1286 {
1287 uint32_t states = RADV_DYNAMIC_ALL;
1288
1289 /* If rasterization is disabled we do not care about any of the dynamic states,
1290 * since they are all rasterization related only. */
1291 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1292 return 0;
1293
1294 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1295 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1296
1297 if (!pCreateInfo->pDepthStencilState ||
1298 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1299 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1300
1301 if (!pCreateInfo->pDepthStencilState ||
1302 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1303 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1304 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1305 RADV_DYNAMIC_STENCIL_REFERENCE);
1306
1307 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1308 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1309
1310 /* TODO: blend constants & line width. */
1311
1312 return states;
1313 }
1314
1315
1316 static void
1317 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1318 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1319 {
1320 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1321 uint32_t states = needed_states;
1322 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1323 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1324
1325 pipeline->dynamic_state = default_dynamic_state;
1326 pipeline->graphics.needed_dynamic_state = needed_states;
1327
1328 if (pCreateInfo->pDynamicState) {
1329 /* Remove all of the states that are marked as dynamic */
1330 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1331 for (uint32_t s = 0; s < count; s++)
1332 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1333 }
1334
1335 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1336
1337 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1338 assert(pCreateInfo->pViewportState);
1339
1340 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1341 if (states & RADV_DYNAMIC_VIEWPORT) {
1342 typed_memcpy(dynamic->viewport.viewports,
1343 pCreateInfo->pViewportState->pViewports,
1344 pCreateInfo->pViewportState->viewportCount);
1345 }
1346 }
1347
1348 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1349 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1350 if (states & RADV_DYNAMIC_SCISSOR) {
1351 typed_memcpy(dynamic->scissor.scissors,
1352 pCreateInfo->pViewportState->pScissors,
1353 pCreateInfo->pViewportState->scissorCount);
1354 }
1355 }
1356
1357 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1358 assert(pCreateInfo->pRasterizationState);
1359 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1360 }
1361
1362 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1363 assert(pCreateInfo->pRasterizationState);
1364 dynamic->depth_bias.bias =
1365 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1366 dynamic->depth_bias.clamp =
1367 pCreateInfo->pRasterizationState->depthBiasClamp;
1368 dynamic->depth_bias.slope =
1369 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1370 }
1371
1372 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1373 *
1374 * pColorBlendState is [...] NULL if the pipeline has rasterization
1375 * disabled or if the subpass of the render pass the pipeline is
1376 * created against does not use any color attachments.
1377 */
1378 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1379 assert(pCreateInfo->pColorBlendState);
1380 typed_memcpy(dynamic->blend_constants,
1381 pCreateInfo->pColorBlendState->blendConstants, 4);
1382 }
1383
1384 /* If there is no depthstencil attachment, then don't read
1385 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1386 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1387 * no need to override the depthstencil defaults in
1388 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1389 *
1390 * Section 9.2 of the Vulkan 1.0.15 spec says:
1391 *
1392 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1393 * disabled or if the subpass of the render pass the pipeline is created
1394 * against does not use a depth/stencil attachment.
1395 */
1396 if (needed_states && subpass->depth_stencil_attachment) {
1397 assert(pCreateInfo->pDepthStencilState);
1398
1399 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1400 dynamic->depth_bounds.min =
1401 pCreateInfo->pDepthStencilState->minDepthBounds;
1402 dynamic->depth_bounds.max =
1403 pCreateInfo->pDepthStencilState->maxDepthBounds;
1404 }
1405
1406 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1407 dynamic->stencil_compare_mask.front =
1408 pCreateInfo->pDepthStencilState->front.compareMask;
1409 dynamic->stencil_compare_mask.back =
1410 pCreateInfo->pDepthStencilState->back.compareMask;
1411 }
1412
1413 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1414 dynamic->stencil_write_mask.front =
1415 pCreateInfo->pDepthStencilState->front.writeMask;
1416 dynamic->stencil_write_mask.back =
1417 pCreateInfo->pDepthStencilState->back.writeMask;
1418 }
1419
1420 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1421 dynamic->stencil_reference.front =
1422 pCreateInfo->pDepthStencilState->front.reference;
1423 dynamic->stencil_reference.back =
1424 pCreateInfo->pDepthStencilState->back.reference;
1425 }
1426 }
1427
1428 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1429 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1430 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1431 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1432 typed_memcpy(dynamic->discard_rectangle.rectangles,
1433 discard_rectangle_info->pDiscardRectangles,
1434 discard_rectangle_info->discardRectangleCount);
1435 }
1436
1437 pipeline->dynamic_state.mask = states;
1438 }
1439
1440 static struct radv_gs_state
1441 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1442 const struct radv_pipeline *pipeline)
1443 {
1444 struct radv_gs_state gs = {0};
1445 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1446 struct radv_es_output_info *es_info;
1447 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1448 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1449 else
1450 es_info = radv_pipeline_has_tess(pipeline) ?
1451 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1452 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1453
1454 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1455 bool uses_adjacency;
1456 switch(pCreateInfo->pInputAssemblyState->topology) {
1457 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1458 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1459 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1460 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1461 uses_adjacency = true;
1462 break;
1463 default:
1464 uses_adjacency = false;
1465 break;
1466 }
1467
1468 /* All these are in dwords: */
1469 /* We can't allow using the whole LDS, because GS waves compete with
1470 * other shader stages for LDS space. */
1471 const unsigned max_lds_size = 8 * 1024;
1472 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1473 unsigned esgs_lds_size;
1474
1475 /* All these are per subgroup: */
1476 const unsigned max_out_prims = 32 * 1024;
1477 const unsigned max_es_verts = 255;
1478 const unsigned ideal_gs_prims = 64;
1479 unsigned max_gs_prims, gs_prims;
1480 unsigned min_es_verts, es_verts, worst_case_es_verts;
1481
1482 if (uses_adjacency || gs_num_invocations > 1)
1483 max_gs_prims = 127 / gs_num_invocations;
1484 else
1485 max_gs_prims = 255;
1486
1487 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1488 * Make sure we don't go over the maximum value.
1489 */
1490 if (gs_info->gs.vertices_out > 0) {
1491 max_gs_prims = MIN2(max_gs_prims,
1492 max_out_prims /
1493 (gs_info->gs.vertices_out * gs_num_invocations));
1494 }
1495 assert(max_gs_prims > 0);
1496
1497 /* If the primitive has adjacency, halve the number of vertices
1498 * that will be reused in multiple primitives.
1499 */
1500 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1501
1502 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1503 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1504
1505 /* Compute ESGS LDS size based on the worst case number of ES vertices
1506 * needed to create the target number of GS prims per subgroup.
1507 */
1508 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1509
1510 /* If total LDS usage is too big, refactor partitions based on ratio
1511 * of ESGS item sizes.
1512 */
1513 if (esgs_lds_size > max_lds_size) {
1514 /* Our target GS Prims Per Subgroup was too large. Calculate
1515 * the maximum number of GS Prims Per Subgroup that will fit
1516 * into LDS, capped by the maximum that the hardware can support.
1517 */
1518 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1519 max_gs_prims);
1520 assert(gs_prims > 0);
1521 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1522 max_es_verts);
1523
1524 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1525 assert(esgs_lds_size <= max_lds_size);
1526 }
1527
1528 /* Now calculate remaining ESGS information. */
1529 if (esgs_lds_size)
1530 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1531 else
1532 es_verts = max_es_verts;
1533
1534 /* Vertices for adjacency primitives are not always reused, so restore
1535 * it for ES_VERTS_PER_SUBGRP.
1536 */
1537 min_es_verts = gs_info->gs.vertices_in;
1538
1539 /* For normal primitives, the VGT only checks if they are past the ES
1540 * verts per subgroup after allocating a full GS primitive and if they
1541 * are, kick off a new subgroup. But if those additional ES verts are
1542 * unique (e.g. not reused) we need to make sure there is enough LDS
1543 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1544 */
1545 es_verts -= min_es_verts - 1;
1546
1547 uint32_t es_verts_per_subgroup = es_verts;
1548 uint32_t gs_prims_per_subgroup = gs_prims;
1549 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1550 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1551 gs.lds_size = align(esgs_lds_size, 128) / 128;
1552 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1553 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1554 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1555 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1556 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1557 assert(max_prims_per_subgroup <= max_out_prims);
1558
1559 return gs;
1560 }
1561
1562 static void
1563 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1564 {
1565 struct radv_device *device = pipeline->device;
1566 unsigned num_se = device->physical_device->rad_info.max_se;
1567 unsigned wave_size = 64;
1568 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1569 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
1570 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1571 */
1572 unsigned gs_vertex_reuse =
1573 (device->physical_device->rad_info.chip_class >= VI ? 32 : 16) * num_se;
1574 unsigned alignment = 256 * num_se;
1575 /* The maximum size is 63.999 MB per SE. */
1576 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1577 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1578
1579 /* Calculate the minimum size. */
1580 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1581 wave_size, alignment);
1582 /* These are recommended sizes, not minimum sizes. */
1583 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1584 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1585 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1586 gs_info->gs.max_gsvs_emit_size;
1587
1588 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1589 esgs_ring_size = align(esgs_ring_size, alignment);
1590 gsvs_ring_size = align(gsvs_ring_size, alignment);
1591
1592 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1593 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1594
1595 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1596 }
1597
1598 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1599 unsigned *lds_size)
1600 {
1601 /* If tessellation is all offchip and on-chip GS isn't used, this
1602 * workaround is not needed.
1603 */
1604 return;
1605
1606 /* SPI barrier management bug:
1607 * Make sure we have at least 4k of LDS in use to avoid the bug.
1608 * It applies to workgroup sizes of more than one wavefront.
1609 */
1610 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1611 device->physical_device->rad_info.family == CHIP_KABINI ||
1612 device->physical_device->rad_info.family == CHIP_MULLINS)
1613 *lds_size = MAX2(*lds_size, 8);
1614 }
1615
1616 struct radv_shader_variant *
1617 radv_get_shader(struct radv_pipeline *pipeline,
1618 gl_shader_stage stage)
1619 {
1620 if (stage == MESA_SHADER_VERTEX) {
1621 if (pipeline->shaders[MESA_SHADER_VERTEX])
1622 return pipeline->shaders[MESA_SHADER_VERTEX];
1623 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1624 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1625 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1626 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1627 } else if (stage == MESA_SHADER_TESS_EVAL) {
1628 if (!radv_pipeline_has_tess(pipeline))
1629 return NULL;
1630 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1631 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1632 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1633 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1634 }
1635 return pipeline->shaders[stage];
1636 }
1637
1638 static struct radv_tessellation_state
1639 calculate_tess_state(struct radv_pipeline *pipeline,
1640 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1641 {
1642 unsigned num_tcs_input_cp;
1643 unsigned num_tcs_output_cp;
1644 unsigned lds_size;
1645 unsigned num_patches;
1646 struct radv_tessellation_state tess = {0};
1647
1648 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1649 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1650 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1651
1652 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1653
1654 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1655 assert(lds_size <= 65536);
1656 lds_size = align(lds_size, 512) / 512;
1657 } else {
1658 assert(lds_size <= 32768);
1659 lds_size = align(lds_size, 256) / 256;
1660 }
1661 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1662
1663 tess.lds_size = lds_size;
1664
1665 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1666 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1667 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1668 tess.num_patches = num_patches;
1669
1670 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1671 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1672
1673 switch (tes->info.tes.primitive_mode) {
1674 case GL_TRIANGLES:
1675 type = V_028B6C_TESS_TRIANGLE;
1676 break;
1677 case GL_QUADS:
1678 type = V_028B6C_TESS_QUAD;
1679 break;
1680 case GL_ISOLINES:
1681 type = V_028B6C_TESS_ISOLINE;
1682 break;
1683 }
1684
1685 switch (tes->info.tes.spacing) {
1686 case TESS_SPACING_EQUAL:
1687 partitioning = V_028B6C_PART_INTEGER;
1688 break;
1689 case TESS_SPACING_FRACTIONAL_ODD:
1690 partitioning = V_028B6C_PART_FRAC_ODD;
1691 break;
1692 case TESS_SPACING_FRACTIONAL_EVEN:
1693 partitioning = V_028B6C_PART_FRAC_EVEN;
1694 break;
1695 default:
1696 break;
1697 }
1698
1699 bool ccw = tes->info.tes.ccw;
1700 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1701 vk_find_struct_const(pCreateInfo->pTessellationState,
1702 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
1703
1704 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
1705 ccw = !ccw;
1706
1707 if (tes->info.tes.point_mode)
1708 topology = V_028B6C_OUTPUT_POINT;
1709 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1710 topology = V_028B6C_OUTPUT_LINE;
1711 else if (ccw)
1712 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1713 else
1714 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1715
1716 if (pipeline->device->has_distributed_tess) {
1717 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1718 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1719 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1720 else
1721 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1722 } else
1723 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1724
1725 tess.tf_param = S_028B6C_TYPE(type) |
1726 S_028B6C_PARTITIONING(partitioning) |
1727 S_028B6C_TOPOLOGY(topology) |
1728 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1729
1730 return tess;
1731 }
1732
1733 static const struct radv_prim_vertex_count prim_size_table[] = {
1734 [V_008958_DI_PT_NONE] = {0, 0},
1735 [V_008958_DI_PT_POINTLIST] = {1, 1},
1736 [V_008958_DI_PT_LINELIST] = {2, 2},
1737 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1738 [V_008958_DI_PT_TRILIST] = {3, 3},
1739 [V_008958_DI_PT_TRIFAN] = {3, 1},
1740 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1741 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1742 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1743 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1744 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1745 [V_008958_DI_PT_RECTLIST] = {3, 3},
1746 [V_008958_DI_PT_LINELOOP] = {2, 1},
1747 [V_008958_DI_PT_POLYGON] = {3, 1},
1748 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1749 };
1750
1751 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1752 {
1753 if (radv_pipeline_has_gs(pipeline))
1754 return &pipeline->gs_copy_shader->info.vs.outinfo;
1755 else if (radv_pipeline_has_tess(pipeline))
1756 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1757 else
1758 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1759 }
1760
1761 static void
1762 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1763 {
1764 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1765 int shader_count = 0;
1766
1767 if(shaders[MESA_SHADER_FRAGMENT]) {
1768 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1769 }
1770 if(shaders[MESA_SHADER_GEOMETRY]) {
1771 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1772 }
1773 if(shaders[MESA_SHADER_TESS_EVAL]) {
1774 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1775 }
1776 if(shaders[MESA_SHADER_TESS_CTRL]) {
1777 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1778 }
1779 if(shaders[MESA_SHADER_VERTEX]) {
1780 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1781 }
1782
1783 if (shader_count > 1) {
1784 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
1785 unsigned last = ordered_shaders[0]->info.stage;
1786
1787 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
1788 ordered_shaders[1]->info.has_transform_feedback_varyings)
1789 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
1790
1791 for (int i = 0; i < shader_count; ++i) {
1792 nir_variable_mode mask = 0;
1793
1794 if (ordered_shaders[i]->info.stage != first)
1795 mask = mask | nir_var_shader_in;
1796
1797 if (ordered_shaders[i]->info.stage != last)
1798 mask = mask | nir_var_shader_out;
1799
1800 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
1801 radv_optimize_nir(ordered_shaders[i], false, false);
1802 }
1803 }
1804
1805 for (int i = 1; i < shader_count; ++i) {
1806 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1807 ordered_shaders[i - 1]);
1808
1809 if (nir_link_opt_varyings(ordered_shaders[i],
1810 ordered_shaders[i - 1]))
1811 radv_optimize_nir(ordered_shaders[i - 1], false, false);
1812
1813 nir_remove_dead_variables(ordered_shaders[i],
1814 nir_var_shader_out);
1815 nir_remove_dead_variables(ordered_shaders[i - 1],
1816 nir_var_shader_in);
1817
1818 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1819 ordered_shaders[i - 1]);
1820
1821 nir_compact_varyings(ordered_shaders[i],
1822 ordered_shaders[i - 1], true);
1823
1824 if (progress) {
1825 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1826 ac_lower_indirect_derefs(ordered_shaders[i],
1827 pipeline->device->physical_device->rad_info.chip_class);
1828 }
1829 radv_optimize_nir(ordered_shaders[i], false, false);
1830
1831 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1832 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1833 pipeline->device->physical_device->rad_info.chip_class);
1834 }
1835 radv_optimize_nir(ordered_shaders[i - 1], false, false);
1836 }
1837 }
1838 }
1839
1840
1841 static struct radv_pipeline_key
1842 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1843 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1844 const struct radv_blend_state *blend,
1845 bool has_view_index)
1846 {
1847 const VkPipelineVertexInputStateCreateInfo *input_state =
1848 pCreateInfo->pVertexInputState;
1849 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
1850 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1851
1852 struct radv_pipeline_key key;
1853 memset(&key, 0, sizeof(key));
1854
1855 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
1856 key.optimisations_disabled = 1;
1857
1858 key.has_multiview_view_index = has_view_index;
1859
1860 uint32_t binding_input_rate = 0;
1861 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
1862 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1863 if (input_state->pVertexBindingDescriptions[i].inputRate) {
1864 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
1865 binding_input_rate |= 1u << binding;
1866 instance_rate_divisors[binding] = 1;
1867 }
1868 }
1869 if (divisor_state) {
1870 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
1871 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
1872 divisor_state->pVertexBindingDivisors[i].divisor;
1873 }
1874 }
1875
1876 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1877 unsigned location = input_state->pVertexAttributeDescriptions[i].location;
1878 unsigned binding = input_state->pVertexAttributeDescriptions[i].binding;
1879 if (binding_input_rate & (1u << binding)) {
1880 key.instance_rate_inputs |= 1u << location;
1881 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
1882 }
1883
1884 if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
1885 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
1886 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
1887 uint64_t adjust;
1888 switch(format) {
1889 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
1890 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
1891 adjust = RADV_ALPHA_ADJUST_SNORM;
1892 break;
1893 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
1894 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
1895 adjust = RADV_ALPHA_ADJUST_SSCALED;
1896 break;
1897 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
1898 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
1899 adjust = RADV_ALPHA_ADJUST_SINT;
1900 break;
1901 default:
1902 adjust = 0;
1903 break;
1904 }
1905 key.vertex_alpha_adjust |= adjust << (2 * location);
1906 }
1907 }
1908
1909 if (pCreateInfo->pTessellationState)
1910 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1911
1912
1913 if (pCreateInfo->pMultisampleState &&
1914 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1915 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1916 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1917 key.num_samples = num_samples;
1918 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1919 }
1920
1921 key.col_format = blend->spi_shader_col_format;
1922 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1923 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1924
1925 return key;
1926 }
1927
1928 static void
1929 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1930 const struct radv_pipeline_key *key,
1931 nir_shader **nir)
1932 {
1933 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1934 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
1935 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
1936 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
1937
1938 if (nir[MESA_SHADER_TESS_CTRL]) {
1939 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1940 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1941 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1942 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1943
1944 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1945 }
1946
1947 if (nir[MESA_SHADER_GEOMETRY]) {
1948 if (nir[MESA_SHADER_TESS_CTRL])
1949 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1950 else
1951 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1952 }
1953
1954 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1955 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1956
1957 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1958 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1959 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1960 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1961 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
1962 }
1963
1964 static void
1965 merge_tess_info(struct shader_info *tes_info,
1966 const struct shader_info *tcs_info)
1967 {
1968 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1969 *
1970 * "PointMode. Controls generation of points rather than triangles
1971 * or lines. This functionality defaults to disabled, and is
1972 * enabled if either shader stage includes the execution mode.
1973 *
1974 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1975 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1976 * and OutputVertices, it says:
1977 *
1978 * "One mode must be set in at least one of the tessellation
1979 * shader stages."
1980 *
1981 * So, the fields can be set in either the TCS or TES, but they must
1982 * agree if set in both. Our backend looks at TES, so bitwise-or in
1983 * the values from the TCS.
1984 */
1985 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1986 tes_info->tess.tcs_vertices_out == 0 ||
1987 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1988 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1989
1990 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1991 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1992 tcs_info->tess.spacing == tes_info->tess.spacing);
1993 tes_info->tess.spacing |= tcs_info->tess.spacing;
1994
1995 assert(tcs_info->tess.primitive_mode == 0 ||
1996 tes_info->tess.primitive_mode == 0 ||
1997 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1998 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1999 tes_info->tess.ccw |= tcs_info->tess.ccw;
2000 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2001 }
2002
2003 static
2004 void radv_create_shaders(struct radv_pipeline *pipeline,
2005 struct radv_device *device,
2006 struct radv_pipeline_cache *cache,
2007 const struct radv_pipeline_key *key,
2008 const VkPipelineShaderStageCreateInfo **pStages,
2009 const VkPipelineCreateFlags flags)
2010 {
2011 struct radv_shader_module fs_m = {0};
2012 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2013 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2014 void *codes[MESA_SHADER_STAGES] = {0};
2015 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
2016 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
2017 unsigned char hash[20], gs_copy_hash[20];
2018
2019 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2020 if (pStages[i]) {
2021 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2022 if (modules[i]->nir)
2023 _mesa_sha1_compute(modules[i]->nir->info.name,
2024 strlen(modules[i]->nir->info.name),
2025 modules[i]->sha1);
2026
2027 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2028 }
2029 }
2030
2031 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2032 memcpy(gs_copy_hash, hash, 20);
2033 gs_copy_hash[0] ^= 1;
2034
2035 if (modules[MESA_SHADER_GEOMETRY]) {
2036 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2037 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
2038 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2039 }
2040
2041 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
2042 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2043 return;
2044 }
2045
2046 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2047 nir_builder fs_b;
2048 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2049 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2050 fs_m.nir = fs_b.shader;
2051 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2052 }
2053
2054 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2055 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2056
2057 if (!modules[i])
2058 continue;
2059
2060 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2061 stage ? stage->pName : "main", i,
2062 stage ? stage->pSpecializationInfo : NULL,
2063 flags);
2064
2065 /* We don't want to alter meta shaders IR directly so clone it
2066 * first.
2067 */
2068 if (nir[i]->info.name) {
2069 nir[i] = nir_shader_clone(NULL, nir[i]);
2070 }
2071 }
2072
2073 if (nir[MESA_SHADER_TESS_CTRL]) {
2074 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2075 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2076 }
2077
2078 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2079 radv_link_shaders(pipeline, nir);
2080
2081 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2082 if (nir[i]) {
2083 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2084 }
2085
2086 if (radv_can_dump_shader(device, modules[i], false))
2087 nir_print_shader(nir[i], stderr);
2088 }
2089
2090 radv_fill_shader_keys(keys, key, nir);
2091
2092 if (nir[MESA_SHADER_FRAGMENT]) {
2093 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2094 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2095 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2096 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2097 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
2098 }
2099
2100 /* TODO: These are no longer used as keys we should refactor this */
2101 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
2102 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2103 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
2104 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2105 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
2106 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2107 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
2108 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2109 }
2110
2111 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2112 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2113 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2114 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2115 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2116 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2117 pipeline->layout,
2118 &key, &codes[MESA_SHADER_TESS_CTRL],
2119 &code_sizes[MESA_SHADER_TESS_CTRL]);
2120 }
2121 modules[MESA_SHADER_VERTEX] = NULL;
2122 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2123 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2124 }
2125
2126 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2127 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2128 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2129 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2130 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2131 pipeline->layout,
2132 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
2133 &code_sizes[MESA_SHADER_GEOMETRY]);
2134 }
2135 modules[pre_stage] = NULL;
2136 }
2137
2138 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2139 if(modules[i] && !pipeline->shaders[i]) {
2140 if (i == MESA_SHADER_TESS_CTRL) {
2141 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2142 }
2143 if (i == MESA_SHADER_TESS_EVAL) {
2144 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2145 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2146 }
2147 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2148 pipeline->layout,
2149 keys + i, &codes[i],
2150 &code_sizes[i]);
2151 }
2152 }
2153
2154 if(modules[MESA_SHADER_GEOMETRY]) {
2155 void *gs_copy_code = NULL;
2156 unsigned gs_copy_code_size = 0;
2157 if (!pipeline->gs_copy_shader) {
2158 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2159 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2160 &gs_copy_code_size,
2161 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2162 }
2163
2164 if (pipeline->gs_copy_shader) {
2165 void *code[MESA_SHADER_STAGES] = {0};
2166 unsigned code_size[MESA_SHADER_STAGES] = {0};
2167 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2168
2169 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2170 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2171 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2172
2173 radv_pipeline_cache_insert_shaders(device, cache,
2174 gs_copy_hash,
2175 variants,
2176 (const void**)code,
2177 code_size);
2178 }
2179 free(gs_copy_code);
2180 }
2181
2182 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2183 (const void**)codes, code_sizes);
2184
2185 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2186 free(codes[i]);
2187 if (nir[i]) {
2188 if (!pipeline->device->keep_shader_info)
2189 ralloc_free(nir[i]);
2190
2191 if (radv_can_dump_shader_stats(device, modules[i]))
2192 radv_shader_dump_stats(device,
2193 pipeline->shaders[i],
2194 i, stderr);
2195 }
2196 }
2197
2198 if (fs_m.nir)
2199 ralloc_free(fs_m.nir);
2200 }
2201
2202 static uint32_t
2203 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2204 gl_shader_stage stage, enum chip_class chip_class)
2205 {
2206 bool has_gs = radv_pipeline_has_gs(pipeline);
2207 bool has_tess = radv_pipeline_has_tess(pipeline);
2208 switch (stage) {
2209 case MESA_SHADER_FRAGMENT:
2210 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2211 case MESA_SHADER_VERTEX:
2212 if (chip_class >= GFX9) {
2213 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2214 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2215 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2216 }
2217 if (has_tess)
2218 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2219 else
2220 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2221 case MESA_SHADER_GEOMETRY:
2222 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2223 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2224 case MESA_SHADER_COMPUTE:
2225 return R_00B900_COMPUTE_USER_DATA_0;
2226 case MESA_SHADER_TESS_CTRL:
2227 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2228 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2229 case MESA_SHADER_TESS_EVAL:
2230 if (chip_class >= GFX9) {
2231 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2232 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2233 }
2234 if (has_gs)
2235 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2236 else
2237 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2238 default:
2239 unreachable("unknown shader");
2240 }
2241 }
2242
2243 struct radv_bin_size_entry {
2244 unsigned bpp;
2245 VkExtent2D extent;
2246 };
2247
2248 static VkExtent2D
2249 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2250 {
2251 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2252 {
2253 /* One RB / SE */
2254 {
2255 /* One shader engine */
2256 { 0, {128, 128}},
2257 { 1, { 64, 128}},
2258 { 2, { 32, 128}},
2259 { 3, { 16, 128}},
2260 { 17, { 0, 0}},
2261 { UINT_MAX, { 0, 0}},
2262 },
2263 {
2264 /* Two shader engines */
2265 { 0, {128, 128}},
2266 { 2, { 64, 128}},
2267 { 3, { 32, 128}},
2268 { 5, { 16, 128}},
2269 { 17, { 0, 0}},
2270 { UINT_MAX, { 0, 0}},
2271 },
2272 {
2273 /* Four shader engines */
2274 { 0, {128, 128}},
2275 { 3, { 64, 128}},
2276 { 5, { 16, 128}},
2277 { 17, { 0, 0}},
2278 { UINT_MAX, { 0, 0}},
2279 },
2280 },
2281 {
2282 /* Two RB / SE */
2283 {
2284 /* One shader engine */
2285 { 0, {128, 128}},
2286 { 2, { 64, 128}},
2287 { 3, { 32, 128}},
2288 { 5, { 16, 128}},
2289 { 33, { 0, 0}},
2290 { UINT_MAX, { 0, 0}},
2291 },
2292 {
2293 /* Two shader engines */
2294 { 0, {128, 128}},
2295 { 3, { 64, 128}},
2296 { 5, { 32, 128}},
2297 { 9, { 16, 128}},
2298 { 33, { 0, 0}},
2299 { UINT_MAX, { 0, 0}},
2300 },
2301 {
2302 /* Four shader engines */
2303 { 0, {256, 256}},
2304 { 2, {128, 256}},
2305 { 3, {128, 128}},
2306 { 5, { 64, 128}},
2307 { 9, { 16, 128}},
2308 { 33, { 0, 0}},
2309 { UINT_MAX, { 0, 0}},
2310 },
2311 },
2312 {
2313 /* Four RB / SE */
2314 {
2315 /* One shader engine */
2316 { 0, {128, 256}},
2317 { 2, {128, 128}},
2318 { 3, { 64, 128}},
2319 { 5, { 32, 128}},
2320 { 9, { 16, 128}},
2321 { 33, { 0, 0}},
2322 { UINT_MAX, { 0, 0}},
2323 },
2324 {
2325 /* Two shader engines */
2326 { 0, {256, 256}},
2327 { 2, {128, 256}},
2328 { 3, {128, 128}},
2329 { 5, { 64, 128}},
2330 { 9, { 32, 128}},
2331 { 17, { 16, 128}},
2332 { 33, { 0, 0}},
2333 { UINT_MAX, { 0, 0}},
2334 },
2335 {
2336 /* Four shader engines */
2337 { 0, {256, 512}},
2338 { 2, {256, 256}},
2339 { 3, {128, 256}},
2340 { 5, {128, 128}},
2341 { 9, { 64, 128}},
2342 { 17, { 16, 128}},
2343 { 33, { 0, 0}},
2344 { UINT_MAX, { 0, 0}},
2345 },
2346 },
2347 };
2348 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2349 {
2350 // One RB / SE
2351 {
2352 // One shader engine
2353 { 0, {128, 256}},
2354 { 2, {128, 128}},
2355 { 4, { 64, 128}},
2356 { 7, { 32, 128}},
2357 { 13, { 16, 128}},
2358 { 49, { 0, 0}},
2359 { UINT_MAX, { 0, 0}},
2360 },
2361 {
2362 // Two shader engines
2363 { 0, {256, 256}},
2364 { 2, {128, 256}},
2365 { 4, {128, 128}},
2366 { 7, { 64, 128}},
2367 { 13, { 32, 128}},
2368 { 25, { 16, 128}},
2369 { 49, { 0, 0}},
2370 { UINT_MAX, { 0, 0}},
2371 },
2372 {
2373 // Four shader engines
2374 { 0, {256, 512}},
2375 { 2, {256, 256}},
2376 { 4, {128, 256}},
2377 { 7, {128, 128}},
2378 { 13, { 64, 128}},
2379 { 25, { 16, 128}},
2380 { 49, { 0, 0}},
2381 { UINT_MAX, { 0, 0}},
2382 },
2383 },
2384 {
2385 // Two RB / SE
2386 {
2387 // One shader engine
2388 { 0, {256, 256}},
2389 { 2, {128, 256}},
2390 { 4, {128, 128}},
2391 { 7, { 64, 128}},
2392 { 13, { 32, 128}},
2393 { 25, { 16, 128}},
2394 { 97, { 0, 0}},
2395 { UINT_MAX, { 0, 0}},
2396 },
2397 {
2398 // Two shader engines
2399 { 0, {256, 512}},
2400 { 2, {256, 256}},
2401 { 4, {128, 256}},
2402 { 7, {128, 128}},
2403 { 13, { 64, 128}},
2404 { 25, { 32, 128}},
2405 { 49, { 16, 128}},
2406 { 97, { 0, 0}},
2407 { UINT_MAX, { 0, 0}},
2408 },
2409 {
2410 // Four shader engines
2411 { 0, {512, 512}},
2412 { 2, {256, 512}},
2413 { 4, {256, 256}},
2414 { 7, {128, 256}},
2415 { 13, {128, 128}},
2416 { 25, { 64, 128}},
2417 { 49, { 16, 128}},
2418 { 97, { 0, 0}},
2419 { UINT_MAX, { 0, 0}},
2420 },
2421 },
2422 {
2423 // Four RB / SE
2424 {
2425 // One shader engine
2426 { 0, {256, 512}},
2427 { 2, {256, 256}},
2428 { 4, {128, 256}},
2429 { 7, {128, 128}},
2430 { 13, { 64, 128}},
2431 { 25, { 32, 128}},
2432 { 49, { 16, 128}},
2433 { UINT_MAX, { 0, 0}},
2434 },
2435 {
2436 // Two shader engines
2437 { 0, {512, 512}},
2438 { 2, {256, 512}},
2439 { 4, {256, 256}},
2440 { 7, {128, 256}},
2441 { 13, {128, 128}},
2442 { 25, { 64, 128}},
2443 { 49, { 32, 128}},
2444 { 97, { 16, 128}},
2445 { UINT_MAX, { 0, 0}},
2446 },
2447 {
2448 // Four shader engines
2449 { 0, {512, 512}},
2450 { 4, {256, 512}},
2451 { 7, {256, 256}},
2452 { 13, {128, 256}},
2453 { 25, {128, 128}},
2454 { 49, { 64, 128}},
2455 { 97, { 16, 128}},
2456 { UINT_MAX, { 0, 0}},
2457 },
2458 },
2459 };
2460
2461 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2462 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2463 VkExtent2D extent = {512, 512};
2464
2465 unsigned log_num_rb_per_se =
2466 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2467 pipeline->device->physical_device->rad_info.max_se);
2468 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2469
2470 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
2471 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2472 unsigned effective_samples = total_samples;
2473 unsigned color_bytes_per_pixel = 0;
2474
2475 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2476 if (vkblend) {
2477 for (unsigned i = 0; i < subpass->color_count; i++) {
2478 if (!vkblend->pAttachments[i].colorWriteMask)
2479 continue;
2480
2481 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2482 continue;
2483
2484 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2485 color_bytes_per_pixel += vk_format_get_blocksize(format);
2486 }
2487
2488 /* MSAA images typically don't use all samples all the time. */
2489 if (effective_samples >= 2 && ps_iter_samples <= 1)
2490 effective_samples = 2;
2491 color_bytes_per_pixel *= effective_samples;
2492 }
2493
2494 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2495 while(color_entry[1].bpp <= color_bytes_per_pixel)
2496 ++color_entry;
2497
2498 extent = color_entry->extent;
2499
2500 if (subpass->depth_stencil_attachment) {
2501 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
2502
2503 /* Coefficients taken from AMDVLK */
2504 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2505 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2506 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2507
2508 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2509 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
2510 ++ds_entry;
2511
2512 extent.width = MIN2(extent.width, ds_entry->extent.width);
2513 extent.height = MIN2(extent.height, ds_entry->extent.height);
2514 }
2515
2516 return extent;
2517 }
2518
2519 static void
2520 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
2521 struct radv_pipeline *pipeline,
2522 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2523 {
2524 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2525 return;
2526
2527 uint32_t pa_sc_binner_cntl_0 =
2528 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2529 S_028C44_DISABLE_START_OF_PRIM(1);
2530 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2531
2532 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2533
2534 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2535 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2536 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2537
2538 switch (pipeline->device->physical_device->rad_info.family) {
2539 case CHIP_VEGA10:
2540 case CHIP_VEGA12:
2541 case CHIP_VEGA20:
2542 context_states_per_bin = 1;
2543 persistent_states_per_bin = 1;
2544 fpovs_per_batch = 63;
2545 break;
2546 case CHIP_RAVEN:
2547 case CHIP_RAVEN2:
2548 context_states_per_bin = 6;
2549 persistent_states_per_bin = 32;
2550 fpovs_per_batch = 63;
2551 break;
2552 default:
2553 unreachable("unhandled family while determining binning state.");
2554 }
2555
2556 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2557 pa_sc_binner_cntl_0 =
2558 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2559 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2560 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2561 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2562 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2563 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2564 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2565 S_028C44_DISABLE_START_OF_PRIM(1) |
2566 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2567 S_028C44_OPTIMAL_BIN_SELECTION(1);
2568 }
2569
2570 radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0,
2571 pa_sc_binner_cntl_0);
2572 radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
2573 db_dfsm_control);
2574 }
2575
2576
2577 static void
2578 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
2579 struct radv_pipeline *pipeline,
2580 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2581 const struct radv_graphics_pipeline_create_info *extra)
2582 {
2583 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2584 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2585 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2586 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2587 struct radv_render_pass_attachment *attachment = NULL;
2588 uint32_t db_depth_control = 0, db_stencil_control = 0;
2589 uint32_t db_render_control = 0, db_render_override2 = 0;
2590 uint32_t db_render_override = 0;
2591
2592 if (subpass->depth_stencil_attachment)
2593 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
2594
2595 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2596 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2597
2598 if (vkds && has_depth_attachment) {
2599 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2600 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2601 S_028800_ZFUNC(vkds->depthCompareOp) |
2602 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2603
2604 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2605 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2606 }
2607
2608 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2609 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2610 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2611 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2612 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2613 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2614
2615 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2616 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2617 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2618 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2619 }
2620
2621 if (attachment && extra) {
2622 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2623 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2624
2625 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2626 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2627 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2628 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2629 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2630 }
2631
2632 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2633 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2634
2635 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2636 !pCreateInfo->pRasterizationState->depthClampEnable &&
2637 ps->info.info.ps.writes_z) {
2638 /* From VK_EXT_depth_range_unrestricted spec:
2639 *
2640 * "The behavior described in Primitive Clipping still applies.
2641 * If depth clamping is disabled the depth values are still
2642 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2643 * depth clamping is enabled the above equation is ignored and
2644 * the depth values are instead clamped to the VkViewport
2645 * minDepth and maxDepth values, which in the case of this
2646 * extension can be outside of the 0.0 to 1.0 range."
2647 */
2648 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2649 }
2650
2651 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2652 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2653
2654 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2655 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2656 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2657 }
2658
2659 static void
2660 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
2661 struct radv_pipeline *pipeline,
2662 const struct radv_blend_state *blend)
2663 {
2664 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
2665 radeon_emit_array(ctx_cs, blend->cb_blend_control,
2666 8);
2667 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2668 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2669
2670 if (pipeline->device->physical_device->has_rbplus) {
2671
2672 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2673 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
2674 }
2675
2676 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2677
2678 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2679 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2680
2681 pipeline->graphics.col_format = blend->spi_shader_col_format;
2682 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
2683 }
2684
2685 static const VkConservativeRasterizationModeEXT
2686 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
2687 {
2688 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
2689 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
2690
2691 if (!conservative_raster)
2692 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
2693 return conservative_raster->conservativeRasterizationMode;
2694 }
2695
2696 static void
2697 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
2698 struct radv_pipeline *pipeline,
2699 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2700 {
2701 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2702 const VkConservativeRasterizationModeEXT mode =
2703 radv_get_conservative_raster_mode(vkraster);
2704 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
2705
2706 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
2707 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2708 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2709 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2710 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2711 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2712
2713 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
2714 S_0286D4_FLAT_SHADE_ENA(1) |
2715 S_0286D4_PNT_SPRITE_ENA(1) |
2716 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2717 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2718 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2719 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2720 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2721
2722 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
2723 S_028BE4_PIX_CENTER(1) | // TODO verify
2724 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2725 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2726
2727 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
2728 S_028814_FACE(vkraster->frontFace) |
2729 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2730 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2731 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2732 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2733 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2734 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2735 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2736 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2737
2738 /* Conservative rasterization. */
2739 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
2740 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2741
2742 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
2743 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
2744 S_028804_OVERRASTERIZATION_AMOUNT(4);
2745
2746 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
2747 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
2748 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
2749
2750 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
2751 pa_sc_conservative_rast |=
2752 S_028C4C_OVER_RAST_ENABLE(1) |
2753 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
2754 S_028C4C_UNDER_RAST_ENABLE(0) |
2755 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
2756 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
2757 } else {
2758 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
2759 pa_sc_conservative_rast |=
2760 S_028C4C_OVER_RAST_ENABLE(0) |
2761 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
2762 S_028C4C_UNDER_RAST_ENABLE(1) |
2763 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
2764 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
2765 }
2766 }
2767
2768 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
2769 pa_sc_conservative_rast);
2770 }
2771
2772
2773 static void
2774 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
2775 struct radv_pipeline *pipeline)
2776 {
2777 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2778
2779 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2780 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
2781 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
2782
2783 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
2784 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2785
2786 /* The exclusion bits can be set to improve rasterization efficiency
2787 * if no sample lies on the pixel boundary (-8 sample offset). It's
2788 * currently always TRUE because the driver doesn't support 16 samples.
2789 */
2790 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= CIK;
2791 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
2792 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
2793 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
2794 }
2795
2796 static void
2797 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
2798 struct radv_pipeline *pipeline)
2799 {
2800 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2801
2802 uint32_t vgt_primitiveid_en = false;
2803 uint32_t vgt_gs_mode = 0;
2804
2805 if (radv_pipeline_has_gs(pipeline)) {
2806 const struct radv_shader_variant *gs =
2807 pipeline->shaders[MESA_SHADER_GEOMETRY];
2808
2809 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2810 pipeline->device->physical_device->rad_info.chip_class);
2811 } else if (outinfo->export_prim_id) {
2812 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2813 vgt_primitiveid_en = true;
2814 }
2815
2816 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2817 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2818 }
2819
2820 static void
2821 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
2822 struct radeon_cmdbuf *cs,
2823 struct radv_pipeline *pipeline,
2824 struct radv_shader_variant *shader)
2825 {
2826 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2827
2828 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2829 radeon_emit(cs, va >> 8);
2830 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2831 radeon_emit(cs, shader->rsrc1);
2832 radeon_emit(cs, shader->rsrc2);
2833
2834 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2835 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2836 clip_dist_mask = outinfo->clip_dist_mask;
2837 cull_dist_mask = outinfo->cull_dist_mask;
2838 total_mask = clip_dist_mask | cull_dist_mask;
2839 bool misc_vec_ena = outinfo->writes_pointsize ||
2840 outinfo->writes_layer ||
2841 outinfo->writes_viewport_index;
2842
2843 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
2844 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2845
2846 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
2847 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2848 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2849 V_02870C_SPI_SHADER_4COMP :
2850 V_02870C_SPI_SHADER_NONE) |
2851 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2852 V_02870C_SPI_SHADER_4COMP :
2853 V_02870C_SPI_SHADER_NONE) |
2854 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2855 V_02870C_SPI_SHADER_4COMP :
2856 V_02870C_SPI_SHADER_NONE));
2857
2858 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
2859 S_028818_VTX_W0_FMT(1) |
2860 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2861 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2862 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2863
2864 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
2865 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2866 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2867 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2868 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2869 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2870 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2871 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2872 cull_dist_mask << 8 |
2873 clip_dist_mask);
2874
2875 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2876 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
2877 outinfo->writes_viewport_index);
2878 }
2879
2880 static void
2881 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
2882 struct radv_pipeline *pipeline,
2883 struct radv_shader_variant *shader)
2884 {
2885 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2886
2887 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2888 radeon_emit(cs, va >> 8);
2889 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2890 radeon_emit(cs, shader->rsrc1);
2891 radeon_emit(cs, shader->rsrc2);
2892 }
2893
2894 static void
2895 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
2896 struct radv_pipeline *pipeline,
2897 struct radv_shader_variant *shader,
2898 const struct radv_tessellation_state *tess)
2899 {
2900 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2901 uint32_t rsrc2 = shader->rsrc2;
2902
2903 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2904 radeon_emit(cs, va >> 8);
2905 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2906
2907 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2908 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2909 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2910 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2911
2912 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2913 radeon_emit(cs, shader->rsrc1);
2914 radeon_emit(cs, rsrc2);
2915 }
2916
2917 static void
2918 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
2919 struct radv_pipeline *pipeline,
2920 struct radv_shader_variant *shader,
2921 const struct radv_tessellation_state *tess)
2922 {
2923 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2924
2925 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2926 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2927 radeon_emit(cs, va >> 8);
2928 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2929
2930 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2931 radeon_emit(cs, shader->rsrc1);
2932 radeon_emit(cs, shader->rsrc2 |
2933 S_00B42C_LDS_SIZE(tess->lds_size));
2934 } else {
2935 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2936 radeon_emit(cs, va >> 8);
2937 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2938 radeon_emit(cs, shader->rsrc1);
2939 radeon_emit(cs, shader->rsrc2);
2940 }
2941 }
2942
2943 static void
2944 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
2945 struct radeon_cmdbuf *cs,
2946 struct radv_pipeline *pipeline,
2947 const struct radv_tessellation_state *tess)
2948 {
2949 struct radv_shader_variant *vs;
2950
2951 /* Skip shaders merged into HS/GS */
2952 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2953 if (!vs)
2954 return;
2955
2956 if (vs->info.vs.as_ls)
2957 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2958 else if (vs->info.vs.as_es)
2959 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2960 else
2961 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
2962 }
2963
2964 static void
2965 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
2966 struct radeon_cmdbuf *cs,
2967 struct radv_pipeline *pipeline,
2968 const struct radv_tessellation_state *tess)
2969 {
2970 if (!radv_pipeline_has_tess(pipeline))
2971 return;
2972
2973 struct radv_shader_variant *tes, *tcs;
2974
2975 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2976 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2977
2978 if (tes) {
2979 if (tes->info.tes.as_es)
2980 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2981 else
2982 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
2983 }
2984
2985 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2986
2987 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
2988 tess->tf_param);
2989
2990 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2991 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2992 tess->ls_hs_config);
2993 else
2994 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
2995 tess->ls_hs_config);
2996 }
2997
2998 static void
2999 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
3000 struct radeon_cmdbuf *cs,
3001 struct radv_pipeline *pipeline,
3002 const struct radv_gs_state *gs_state)
3003 {
3004 struct radv_shader_variant *gs;
3005 unsigned gs_max_out_vertices;
3006 uint8_t *num_components;
3007 uint8_t max_stream;
3008 unsigned offset;
3009 uint64_t va;
3010
3011 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3012 if (!gs)
3013 return;
3014
3015 gs_max_out_vertices = gs->info.gs.vertices_out;
3016 max_stream = gs->info.info.gs.max_stream;
3017 num_components = gs->info.info.gs.num_stream_output_components;
3018
3019 offset = num_components[0] * gs_max_out_vertices;
3020
3021 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3022 radeon_emit(ctx_cs, offset);
3023 if (max_stream >= 1)
3024 offset += num_components[1] * gs_max_out_vertices;
3025 radeon_emit(ctx_cs, offset);
3026 if (max_stream >= 2)
3027 offset += num_components[2] * gs_max_out_vertices;
3028 radeon_emit(ctx_cs, offset);
3029 if (max_stream >= 3)
3030 offset += num_components[3] * gs_max_out_vertices;
3031 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3032
3033 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
3034
3035 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3036 radeon_emit(ctx_cs, num_components[0]);
3037 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
3038 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
3039 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
3040
3041 uint32_t gs_num_invocations = gs->info.gs.invocations;
3042 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3043 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3044 S_028B90_ENABLE(gs_num_invocations > 0));
3045
3046 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3047 gs_state->vgt_esgs_ring_itemsize);
3048
3049 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
3050
3051 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3052 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
3053 radeon_emit(cs, va >> 8);
3054 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
3055
3056 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3057 radeon_emit(cs, gs->rsrc1);
3058 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
3059
3060 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
3061 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
3062 } else {
3063 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
3064 radeon_emit(cs, va >> 8);
3065 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
3066 radeon_emit(cs, gs->rsrc1);
3067 radeon_emit(cs, gs->rsrc2);
3068 }
3069
3070 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
3071 }
3072
3073 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
3074 {
3075 uint32_t ps_input_cntl;
3076 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3077 ps_input_cntl = S_028644_OFFSET(offset);
3078 if (flat_shade)
3079 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3080 } else {
3081 /* The input is a DEFAULT_VAL constant. */
3082 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3083 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3084 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3085 ps_input_cntl = S_028644_OFFSET(0x20) |
3086 S_028644_DEFAULT_VAL(offset);
3087 }
3088 return ps_input_cntl;
3089 }
3090
3091 static void
3092 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
3093 struct radv_pipeline *pipeline)
3094 {
3095 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3096 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3097 uint32_t ps_input_cntl[32];
3098
3099 unsigned ps_offset = 0;
3100
3101 if (ps->info.info.ps.prim_id_input) {
3102 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3103 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3104 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3105 ++ps_offset;
3106 }
3107 }
3108
3109 if (ps->info.info.ps.layer_input ||
3110 ps->info.info.ps.uses_input_attachments ||
3111 ps->info.info.needs_multiview_view_index) {
3112 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3113 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3114 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3115 else
3116 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
3117 ++ps_offset;
3118 }
3119
3120 if (ps->info.info.ps.has_pcoord) {
3121 unsigned val;
3122 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3123 ps_input_cntl[ps_offset] = val;
3124 ps_offset++;
3125 }
3126
3127 if (ps->info.info.ps.num_input_clips_culls) {
3128 unsigned vs_offset;
3129
3130 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
3131 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3132 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
3133 ++ps_offset;
3134 }
3135
3136 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
3137 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
3138 ps->info.info.ps.num_input_clips_culls > 4) {
3139 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
3140 ++ps_offset;
3141 }
3142 }
3143
3144 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3145 unsigned vs_offset;
3146 bool flat_shade;
3147 if (!(ps->info.fs.input_mask & (1u << i)))
3148 continue;
3149
3150 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3151 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3152 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3153 ++ps_offset;
3154 continue;
3155 }
3156
3157 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
3158
3159 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
3160 ++ps_offset;
3161 }
3162
3163 if (ps_offset) {
3164 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
3165 for (unsigned i = 0; i < ps_offset; i++) {
3166 radeon_emit(ctx_cs, ps_input_cntl[i]);
3167 }
3168 }
3169 }
3170
3171 static uint32_t
3172 radv_compute_db_shader_control(const struct radv_device *device,
3173 const struct radv_pipeline *pipeline,
3174 const struct radv_shader_variant *ps)
3175 {
3176 const struct radv_multisample_state *ms = &pipeline->graphics.ms;
3177 unsigned z_order;
3178 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3179 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3180 else
3181 z_order = V_02880C_LATE_Z;
3182
3183 bool disable_rbplus = device->physical_device->has_rbplus &&
3184 !device->physical_device->rbplus_allowed;
3185
3186 /* Do not enable the gl_SampleMask fragment shader output if MSAA is
3187 * disabled.
3188 */
3189 bool mask_export_enable = ms->num_samples > 1 &&
3190 ps->info.info.ps.writes_sample_mask;
3191
3192 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
3193 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
3194 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
3195 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
3196 S_02880C_Z_ORDER(z_order) |
3197 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3198 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3199 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3200 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
3201 }
3202
3203 static void
3204 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
3205 struct radeon_cmdbuf *cs,
3206 struct radv_pipeline *pipeline)
3207 {
3208 struct radv_shader_variant *ps;
3209 uint64_t va;
3210 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3211
3212 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3213 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3214
3215 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3216 radeon_emit(cs, va >> 8);
3217 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3218 radeon_emit(cs, ps->rsrc1);
3219 radeon_emit(cs, ps->rsrc2);
3220
3221 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
3222 radv_compute_db_shader_control(pipeline->device,
3223 pipeline, ps));
3224
3225 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
3226 ps->config.spi_ps_input_ena);
3227
3228 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
3229 ps->config.spi_ps_input_addr);
3230
3231 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
3232 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3233
3234 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3235
3236 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
3237 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3238 ps->info.info.ps.writes_stencil,
3239 ps->info.info.ps.writes_sample_mask));
3240
3241 if (pipeline->device->dfsm_allowed) {
3242 /* optimise this? */
3243 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3244 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3245 }
3246 }
3247
3248 static void
3249 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
3250 struct radv_pipeline *pipeline)
3251 {
3252 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
3253 return;
3254
3255 unsigned vtx_reuse_depth = 30;
3256 if (radv_pipeline_has_tess(pipeline) &&
3257 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3258 vtx_reuse_depth = 14;
3259 }
3260 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3261 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3262 }
3263
3264 static uint32_t
3265 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3266 {
3267 uint32_t stages = 0;
3268 if (radv_pipeline_has_tess(pipeline)) {
3269 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3270 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3271
3272 if (radv_pipeline_has_gs(pipeline))
3273 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3274 S_028B54_GS_EN(1) |
3275 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3276 else
3277 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3278
3279 } else if (radv_pipeline_has_gs(pipeline))
3280 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3281 S_028B54_GS_EN(1) |
3282 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3283
3284 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3285 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3286
3287 return stages;
3288 }
3289
3290 static uint32_t
3291 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3292 {
3293 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3294 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3295
3296 if (!discard_rectangle_info)
3297 return 0xffff;
3298
3299 unsigned mask = 0;
3300
3301 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3302 /* Interpret i as a bitmask, and then set the bit in the mask if
3303 * that combination of rectangles in which the pixel is contained
3304 * should pass the cliprect test. */
3305 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3306
3307 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3308 !relevant_subset)
3309 continue;
3310
3311 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3312 relevant_subset)
3313 continue;
3314
3315 mask |= 1u << i;
3316 }
3317
3318 return mask;
3319 }
3320
3321 static void
3322 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
3323 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3324 const struct radv_graphics_pipeline_create_info *extra,
3325 const struct radv_blend_state *blend,
3326 const struct radv_tessellation_state *tess,
3327 const struct radv_gs_state *gs,
3328 unsigned prim, unsigned gs_out)
3329 {
3330 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
3331 struct radeon_cmdbuf *cs = &pipeline->cs;
3332
3333 cs->max_dw = 64;
3334 ctx_cs->max_dw = 256;
3335 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
3336 ctx_cs->buf = cs->buf + cs->max_dw;
3337
3338 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
3339 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
3340 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
3341 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
3342 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
3343 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
3344 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
3345 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs);
3346 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
3347 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
3348 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
3349 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
3350
3351 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
3352 S_0286E8_WAVES(pipeline->max_waves) |
3353 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3354
3355 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
3356
3357 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
3358 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
3359 } else {
3360 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
3361 }
3362 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
3363
3364 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
3365
3366 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
3367
3368 assert(ctx_cs->cdw <= ctx_cs->max_dw);
3369 assert(cs->cdw <= cs->max_dw);
3370 }
3371
3372 static struct radv_ia_multi_vgt_param_helpers
3373 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
3374 const struct radv_tessellation_state *tess,
3375 uint32_t prim)
3376 {
3377 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
3378 const struct radv_device *device = pipeline->device;
3379
3380 if (radv_pipeline_has_tess(pipeline))
3381 ia_multi_vgt_param.primgroup_size = tess->num_patches;
3382 else if (radv_pipeline_has_gs(pipeline))
3383 ia_multi_vgt_param.primgroup_size = 64;
3384 else
3385 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3386
3387 /* GS requirement. */
3388 ia_multi_vgt_param.partial_es_wave = false;
3389 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
3390 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3391 ia_multi_vgt_param.partial_es_wave = true;
3392
3393 ia_multi_vgt_param.wd_switch_on_eop = false;
3394 if (device->physical_device->rad_info.chip_class >= CIK) {
3395 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3396 * 4 shader engines. Set 1 to pass the assertion below.
3397 * The other cases are hardware requirements. */
3398 if (device->physical_device->rad_info.max_se < 4 ||
3399 prim == V_008958_DI_PT_POLYGON ||
3400 prim == V_008958_DI_PT_LINELOOP ||
3401 prim == V_008958_DI_PT_TRIFAN ||
3402 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3403 (pipeline->graphics.prim_restart_enable &&
3404 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3405 (prim != V_008958_DI_PT_POINTLIST &&
3406 prim != V_008958_DI_PT_LINESTRIP))))
3407 ia_multi_vgt_param.wd_switch_on_eop = true;
3408 }
3409
3410 ia_multi_vgt_param.ia_switch_on_eoi = false;
3411 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3412 ia_multi_vgt_param.ia_switch_on_eoi = true;
3413 if (radv_pipeline_has_gs(pipeline) &&
3414 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3415 ia_multi_vgt_param.ia_switch_on_eoi = true;
3416 if (radv_pipeline_has_tess(pipeline)) {
3417 /* SWITCH_ON_EOI must be set if PrimID is used. */
3418 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3419 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
3420 ia_multi_vgt_param.ia_switch_on_eoi = true;
3421 }
3422
3423 ia_multi_vgt_param.partial_vs_wave = false;
3424 if (radv_pipeline_has_tess(pipeline)) {
3425 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3426 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3427 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3428 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3429 radv_pipeline_has_gs(pipeline))
3430 ia_multi_vgt_param.partial_vs_wave = true;
3431 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3432 if (device->has_distributed_tess) {
3433 if (radv_pipeline_has_gs(pipeline)) {
3434 if (device->physical_device->rad_info.chip_class <= VI)
3435 ia_multi_vgt_param.partial_es_wave = true;
3436 } else {
3437 ia_multi_vgt_param.partial_vs_wave = true;
3438 }
3439 }
3440 }
3441
3442 /* Workaround for a VGT hang when strip primitive types are used with
3443 * primitive restart.
3444 */
3445 if (pipeline->graphics.prim_restart_enable &&
3446 (prim == V_008958_DI_PT_LINESTRIP ||
3447 prim == V_008958_DI_PT_TRISTRIP ||
3448 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
3449 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
3450 ia_multi_vgt_param.partial_vs_wave = true;
3451 }
3452
3453 if (radv_pipeline_has_gs(pipeline)) {
3454 /* On these chips there is the possibility of a hang if the
3455 * pipeline uses a GS and partial_vs_wave is not set.
3456 *
3457 * This mostly does not hit 4-SE chips, as those typically set
3458 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
3459 * with GS due to another workaround.
3460 *
3461 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
3462 */
3463 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3464 device->physical_device->rad_info.family == CHIP_FIJI ||
3465 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3466 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3467 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
3468 device->physical_device->rad_info.family == CHIP_VEGAM) {
3469 ia_multi_vgt_param.partial_vs_wave = true;
3470 }
3471 }
3472
3473 ia_multi_vgt_param.base =
3474 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3475 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3476 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3477 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3478 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3479
3480 return ia_multi_vgt_param;
3481 }
3482
3483
3484 static void
3485 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3486 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3487 {
3488 const VkPipelineVertexInputStateCreateInfo *vi_info =
3489 pCreateInfo->pVertexInputState;
3490 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3491
3492 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3493 const VkVertexInputAttributeDescription *desc =
3494 &vi_info->pVertexAttributeDescriptions[i];
3495 unsigned loc = desc->location;
3496 const struct vk_format_description *format_desc;
3497 int first_non_void;
3498 uint32_t num_format, data_format;
3499 format_desc = vk_format_description(desc->format);
3500 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3501
3502 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3503 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3504
3505 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3506 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3507 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3508 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3509 S_008F0C_NUM_FORMAT(num_format) |
3510 S_008F0C_DATA_FORMAT(data_format);
3511 velems->format_size[loc] = format_desc->block.bits / 8;
3512 velems->offset[loc] = desc->offset;
3513 velems->binding[loc] = desc->binding;
3514 velems->count = MAX2(velems->count, loc + 1);
3515 }
3516
3517 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3518 const VkVertexInputBindingDescription *desc =
3519 &vi_info->pVertexBindingDescriptions[i];
3520
3521 pipeline->binding_stride[desc->binding] = desc->stride;
3522 }
3523 }
3524
3525 static struct radv_shader_variant *
3526 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
3527 {
3528 int i;
3529
3530 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
3531 struct radv_shader_variant *shader =
3532 radv_get_shader(pipeline, i);
3533
3534 if (shader && shader->info.info.so.num_outputs > 0)
3535 return shader;
3536 }
3537
3538 return NULL;
3539 }
3540
3541 static VkResult
3542 radv_pipeline_init(struct radv_pipeline *pipeline,
3543 struct radv_device *device,
3544 struct radv_pipeline_cache *cache,
3545 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3546 const struct radv_graphics_pipeline_create_info *extra)
3547 {
3548 VkResult result;
3549 bool has_view_index = false;
3550
3551 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3552 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3553 if (subpass->view_mask)
3554 has_view_index = true;
3555
3556 pipeline->device = device;
3557 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3558 assert(pipeline->layout);
3559
3560 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3561
3562 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3563 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3564 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3565 pStages[stage] = &pCreateInfo->pStages[i];
3566 }
3567
3568 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
3569 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags);
3570
3571 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3572 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
3573 uint32_t gs_out;
3574 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3575
3576 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3577
3578 if (radv_pipeline_has_gs(pipeline)) {
3579 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3580 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3581 } else {
3582 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3583 }
3584 if (extra && extra->use_rectlist) {
3585 prim = V_008958_DI_PT_RECTLIST;
3586 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3587 pipeline->graphics.can_use_guardband = true;
3588 }
3589 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3590 /* prim vertex count will need TESS changes */
3591 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3592
3593 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3594
3595 /* Ensure that some export memory is always allocated, for two reasons:
3596 *
3597 * 1) Correctness: The hardware ignores the EXEC mask if no export
3598 * memory is allocated, so KILL and alpha test do not work correctly
3599 * without this.
3600 * 2) Performance: Every shader needs at least a NULL export, even when
3601 * it writes no color/depth output. The NULL export instruction
3602 * stalls without this setting.
3603 *
3604 * Don't add this to CB_SHADER_MASK.
3605 */
3606 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3607 if (!blend.spi_shader_col_format) {
3608 if (!ps->info.info.ps.writes_z &&
3609 !ps->info.info.ps.writes_stencil &&
3610 !ps->info.info.ps.writes_sample_mask)
3611 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3612 }
3613
3614 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3615 if (pipeline->shaders[i]) {
3616 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3617 }
3618 }
3619
3620 struct radv_gs_state gs = {0};
3621 if (radv_pipeline_has_gs(pipeline)) {
3622 gs = calculate_gs_info(pCreateInfo, pipeline);
3623 calculate_gs_ring_sizes(pipeline, &gs);
3624 }
3625
3626 struct radv_tessellation_state tess = {0};
3627 if (radv_pipeline_has_tess(pipeline)) {
3628 if (prim == V_008958_DI_PT_PATCH) {
3629 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3630 pipeline->graphics.prim_vertex_count.incr = 1;
3631 }
3632 tess = calculate_tess_state(pipeline, pCreateInfo);
3633 }
3634
3635 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3636
3637 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3638
3639 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3640 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3641
3642 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3643 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3644 if (loc->sgpr_idx != -1) {
3645 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3646 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3647 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
3648 pipeline->graphics.vtx_emit_num = 3;
3649 else
3650 pipeline->graphics.vtx_emit_num = 2;
3651 }
3652
3653 /* Find the last vertex shader stage that eventually uses streamout. */
3654 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
3655
3656 result = radv_pipeline_scratch_init(device, pipeline);
3657 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3658
3659 return result;
3660 }
3661
3662 VkResult
3663 radv_graphics_pipeline_create(
3664 VkDevice _device,
3665 VkPipelineCache _cache,
3666 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3667 const struct radv_graphics_pipeline_create_info *extra,
3668 const VkAllocationCallbacks *pAllocator,
3669 VkPipeline *pPipeline)
3670 {
3671 RADV_FROM_HANDLE(radv_device, device, _device);
3672 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3673 struct radv_pipeline *pipeline;
3674 VkResult result;
3675
3676 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3677 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3678 if (pipeline == NULL)
3679 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3680
3681 result = radv_pipeline_init(pipeline, device, cache,
3682 pCreateInfo, extra);
3683 if (result != VK_SUCCESS) {
3684 radv_pipeline_destroy(device, pipeline, pAllocator);
3685 return result;
3686 }
3687
3688 *pPipeline = radv_pipeline_to_handle(pipeline);
3689
3690 return VK_SUCCESS;
3691 }
3692
3693 VkResult radv_CreateGraphicsPipelines(
3694 VkDevice _device,
3695 VkPipelineCache pipelineCache,
3696 uint32_t count,
3697 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3698 const VkAllocationCallbacks* pAllocator,
3699 VkPipeline* pPipelines)
3700 {
3701 VkResult result = VK_SUCCESS;
3702 unsigned i = 0;
3703
3704 for (; i < count; i++) {
3705 VkResult r;
3706 r = radv_graphics_pipeline_create(_device,
3707 pipelineCache,
3708 &pCreateInfos[i],
3709 NULL, pAllocator, &pPipelines[i]);
3710 if (r != VK_SUCCESS) {
3711 result = r;
3712 pPipelines[i] = VK_NULL_HANDLE;
3713 }
3714 }
3715
3716 return result;
3717 }
3718
3719
3720 static void
3721 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3722 {
3723 struct radv_shader_variant *compute_shader;
3724 struct radv_device *device = pipeline->device;
3725 unsigned compute_resource_limits;
3726 unsigned waves_per_threadgroup;
3727 uint64_t va;
3728
3729 pipeline->cs.buf = malloc(20 * 4);
3730 pipeline->cs.max_dw = 20;
3731
3732 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3733 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3734
3735 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3736 radeon_emit(&pipeline->cs, va >> 8);
3737 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3738
3739 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3740 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3741 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3742
3743 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3744 S_00B860_WAVES(pipeline->max_waves) |
3745 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3746
3747 /* Calculate best compute resource limits. */
3748 waves_per_threadgroup =
3749 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3750 compute_shader->info.cs.block_size[1] *
3751 compute_shader->info.cs.block_size[2], 64);
3752 compute_resource_limits =
3753 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3754
3755 if (device->physical_device->rad_info.chip_class >= CIK) {
3756 unsigned num_cu_per_se =
3757 device->physical_device->rad_info.num_good_compute_units /
3758 device->physical_device->rad_info.max_se;
3759
3760 /* Force even distribution on all SIMDs in CU if the workgroup
3761 * size is 64. This has shown some good improvements if # of
3762 * CUs per SE is not a multiple of 4.
3763 */
3764 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3765 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3766 }
3767
3768 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3769 compute_resource_limits);
3770
3771 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3772 radeon_emit(&pipeline->cs,
3773 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3774 radeon_emit(&pipeline->cs,
3775 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3776 radeon_emit(&pipeline->cs,
3777 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3778
3779 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3780 }
3781
3782 static VkResult radv_compute_pipeline_create(
3783 VkDevice _device,
3784 VkPipelineCache _cache,
3785 const VkComputePipelineCreateInfo* pCreateInfo,
3786 const VkAllocationCallbacks* pAllocator,
3787 VkPipeline* pPipeline)
3788 {
3789 RADV_FROM_HANDLE(radv_device, device, _device);
3790 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3791 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3792 struct radv_pipeline *pipeline;
3793 VkResult result;
3794
3795 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3796 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3797 if (pipeline == NULL)
3798 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3799
3800 pipeline->device = device;
3801 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3802 assert(pipeline->layout);
3803
3804 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3805 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
3806
3807 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3808 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3809 result = radv_pipeline_scratch_init(device, pipeline);
3810 if (result != VK_SUCCESS) {
3811 radv_pipeline_destroy(device, pipeline, pAllocator);
3812 return result;
3813 }
3814
3815 radv_compute_generate_pm4(pipeline);
3816
3817 *pPipeline = radv_pipeline_to_handle(pipeline);
3818
3819 return VK_SUCCESS;
3820 }
3821
3822 VkResult radv_CreateComputePipelines(
3823 VkDevice _device,
3824 VkPipelineCache pipelineCache,
3825 uint32_t count,
3826 const VkComputePipelineCreateInfo* pCreateInfos,
3827 const VkAllocationCallbacks* pAllocator,
3828 VkPipeline* pPipelines)
3829 {
3830 VkResult result = VK_SUCCESS;
3831
3832 unsigned i = 0;
3833 for (; i < count; i++) {
3834 VkResult r;
3835 r = radv_compute_pipeline_create(_device, pipelineCache,
3836 &pCreateInfos[i],
3837 pAllocator, &pPipelines[i]);
3838 if (r != VK_SUCCESS) {
3839 result = r;
3840 pPipelines[i] = VK_NULL_HANDLE;
3841 }
3842 }
3843
3844 return result;
3845 }