2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
54 struct radv_blend_state
{
55 uint32_t blend_enable_4bit
;
56 uint32_t need_src_alpha
;
58 uint32_t cb_color_control
;
59 uint32_t cb_target_mask
;
60 uint32_t cb_target_enabled_4bit
;
61 uint32_t sx_mrt_blend_opt
[8];
62 uint32_t cb_blend_control
[8];
64 uint32_t spi_shader_col_format
;
65 uint32_t cb_shader_mask
;
66 uint32_t db_alpha_to_mask
;
68 uint32_t commutative_4bit
;
70 bool single_cb_enable
;
71 bool mrt0_is_dual_src
;
74 struct radv_dsa_order_invariance
{
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
87 struct radv_tessellation_state
{
88 uint32_t ls_hs_config
;
94 static const VkPipelineMultisampleStateCreateInfo
*
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
97 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
98 return pCreateInfo
->pMultisampleState
;
102 static const VkPipelineTessellationStateCreateInfo
*
103 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
105 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
106 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
107 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
108 return pCreateInfo
->pTessellationState
;
114 static const VkPipelineDepthStencilStateCreateInfo
*
115 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
117 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
118 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
120 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
121 subpass
->depth_stencil_attachment
)
122 return pCreateInfo
->pDepthStencilState
;
126 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
128 struct radv_shader_variant
*variant
= NULL
;
129 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
130 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
131 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
132 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
133 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
134 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
137 return variant
->info
.is_ngg
;
140 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
142 if (!radv_pipeline_has_gs(pipeline
))
145 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
146 * On GFX10, it might be required in rare cases if it's not possible to
149 if (radv_pipeline_has_ngg(pipeline
))
152 assert(pipeline
->gs_copy_shader
);
157 radv_pipeline_destroy(struct radv_device
*device
,
158 struct radv_pipeline
*pipeline
,
159 const VkAllocationCallbacks
* allocator
)
161 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
162 if (pipeline
->shaders
[i
])
163 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
165 if (pipeline
->gs_copy_shader
)
166 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
169 free(pipeline
->cs
.buf
);
170 vk_free2(&device
->alloc
, allocator
, pipeline
);
173 void radv_DestroyPipeline(
175 VkPipeline _pipeline
,
176 const VkAllocationCallbacks
* pAllocator
)
178 RADV_FROM_HANDLE(radv_device
, device
, _device
);
179 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
184 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
187 static uint32_t get_hash_flags(struct radv_device
*device
)
189 uint32_t hash_flags
= 0;
191 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
192 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
193 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
194 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
195 if (device
->physical_device
->cs_wave_size
== 32)
196 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
197 if (device
->physical_device
->ps_wave_size
== 32)
198 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
199 if (device
->physical_device
->ge_wave_size
== 32)
200 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
201 if (device
->physical_device
->use_aco
)
202 hash_flags
|= RADV_HASH_SHADER_ACO
;
207 radv_pipeline_scratch_init(struct radv_device
*device
,
208 struct radv_pipeline
*pipeline
)
210 unsigned scratch_bytes_per_wave
= 0;
211 unsigned max_waves
= 0;
212 unsigned min_waves
= 1;
214 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
215 if (pipeline
->shaders
[i
] &&
216 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
217 unsigned max_stage_waves
= device
->scratch_waves
;
219 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
220 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
222 max_stage_waves
= MIN2(max_stage_waves
,
223 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
224 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
225 max_waves
= MAX2(max_waves
, max_stage_waves
);
229 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
230 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
231 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
232 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
233 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
236 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
237 pipeline
->max_waves
= max_waves
;
241 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
244 case VK_LOGIC_OP_CLEAR
:
245 return V_028808_ROP3_CLEAR
;
246 case VK_LOGIC_OP_AND
:
247 return V_028808_ROP3_AND
;
248 case VK_LOGIC_OP_AND_REVERSE
:
249 return V_028808_ROP3_AND_REVERSE
;
250 case VK_LOGIC_OP_COPY
:
251 return V_028808_ROP3_COPY
;
252 case VK_LOGIC_OP_AND_INVERTED
:
253 return V_028808_ROP3_AND_INVERTED
;
254 case VK_LOGIC_OP_NO_OP
:
255 return V_028808_ROP3_NO_OP
;
256 case VK_LOGIC_OP_XOR
:
257 return V_028808_ROP3_XOR
;
259 return V_028808_ROP3_OR
;
260 case VK_LOGIC_OP_NOR
:
261 return V_028808_ROP3_NOR
;
262 case VK_LOGIC_OP_EQUIVALENT
:
263 return V_028808_ROP3_EQUIVALENT
;
264 case VK_LOGIC_OP_INVERT
:
265 return V_028808_ROP3_INVERT
;
266 case VK_LOGIC_OP_OR_REVERSE
:
267 return V_028808_ROP3_OR_REVERSE
;
268 case VK_LOGIC_OP_COPY_INVERTED
:
269 return V_028808_ROP3_COPY_INVERTED
;
270 case VK_LOGIC_OP_OR_INVERTED
:
271 return V_028808_ROP3_OR_INVERTED
;
272 case VK_LOGIC_OP_NAND
:
273 return V_028808_ROP3_NAND
;
274 case VK_LOGIC_OP_SET
:
275 return V_028808_ROP3_SET
;
277 unreachable("Unhandled logic op");
282 static uint32_t si_translate_blend_function(VkBlendOp op
)
285 case VK_BLEND_OP_ADD
:
286 return V_028780_COMB_DST_PLUS_SRC
;
287 case VK_BLEND_OP_SUBTRACT
:
288 return V_028780_COMB_SRC_MINUS_DST
;
289 case VK_BLEND_OP_REVERSE_SUBTRACT
:
290 return V_028780_COMB_DST_MINUS_SRC
;
291 case VK_BLEND_OP_MIN
:
292 return V_028780_COMB_MIN_DST_SRC
;
293 case VK_BLEND_OP_MAX
:
294 return V_028780_COMB_MAX_DST_SRC
;
300 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
303 case VK_BLEND_FACTOR_ZERO
:
304 return V_028780_BLEND_ZERO
;
305 case VK_BLEND_FACTOR_ONE
:
306 return V_028780_BLEND_ONE
;
307 case VK_BLEND_FACTOR_SRC_COLOR
:
308 return V_028780_BLEND_SRC_COLOR
;
309 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
311 case VK_BLEND_FACTOR_DST_COLOR
:
312 return V_028780_BLEND_DST_COLOR
;
313 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
314 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
315 case VK_BLEND_FACTOR_SRC_ALPHA
:
316 return V_028780_BLEND_SRC_ALPHA
;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
318 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
319 case VK_BLEND_FACTOR_DST_ALPHA
:
320 return V_028780_BLEND_DST_ALPHA
;
321 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
322 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
323 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
324 return V_028780_BLEND_CONSTANT_COLOR
;
325 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
326 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
327 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
328 return V_028780_BLEND_CONSTANT_ALPHA
;
329 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
330 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
331 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
332 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
333 case VK_BLEND_FACTOR_SRC1_COLOR
:
334 return V_028780_BLEND_SRC1_COLOR
;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
336 return V_028780_BLEND_INV_SRC1_COLOR
;
337 case VK_BLEND_FACTOR_SRC1_ALPHA
:
338 return V_028780_BLEND_SRC1_ALPHA
;
339 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
340 return V_028780_BLEND_INV_SRC1_ALPHA
;
346 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
349 case VK_BLEND_OP_ADD
:
350 return V_028760_OPT_COMB_ADD
;
351 case VK_BLEND_OP_SUBTRACT
:
352 return V_028760_OPT_COMB_SUBTRACT
;
353 case VK_BLEND_OP_REVERSE_SUBTRACT
:
354 return V_028760_OPT_COMB_REVSUBTRACT
;
355 case VK_BLEND_OP_MIN
:
356 return V_028760_OPT_COMB_MIN
;
357 case VK_BLEND_OP_MAX
:
358 return V_028760_OPT_COMB_MAX
;
360 return V_028760_OPT_COMB_BLEND_DISABLED
;
364 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
367 case VK_BLEND_FACTOR_ZERO
:
368 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
369 case VK_BLEND_FACTOR_ONE
:
370 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
371 case VK_BLEND_FACTOR_SRC_COLOR
:
372 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
373 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
374 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
375 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
376 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
377 case VK_BLEND_FACTOR_SRC_ALPHA
:
378 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
379 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
380 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
381 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
382 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
383 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
385 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
390 * Get rid of DST in the blend factors by commuting the operands:
391 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
393 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
394 unsigned *dst_factor
, unsigned expected_dst
,
395 unsigned replacement_src
)
397 if (*src_factor
== expected_dst
&&
398 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
399 *src_factor
= VK_BLEND_FACTOR_ZERO
;
400 *dst_factor
= replacement_src
;
402 /* Commuting the operands requires reversing subtractions. */
403 if (*func
== VK_BLEND_OP_SUBTRACT
)
404 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
405 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
406 *func
= VK_BLEND_OP_SUBTRACT
;
410 static bool si_blend_factor_uses_dst(unsigned factor
)
412 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
413 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
414 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
415 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
416 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
419 static bool is_dual_src(VkBlendFactor factor
)
422 case VK_BLEND_FACTOR_SRC1_COLOR
:
423 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
424 case VK_BLEND_FACTOR_SRC1_ALPHA
:
425 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
432 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
434 bool blend_need_alpha
)
436 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
437 unsigned format
, ntype
, swap
;
439 /* Alpha is needed for alpha-to-coverage.
440 * Blending may be with or without alpha.
442 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
443 unsigned alpha
= 0; /* exports alpha, but may not support blending */
444 unsigned blend
= 0; /* supports blending, but may not export alpha */
445 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
447 format
= radv_translate_colorformat(vk_format
);
448 ntype
= radv_translate_color_numformat(vk_format
, desc
,
449 vk_format_get_first_non_void_channel(vk_format
));
450 swap
= radv_translate_colorswap(vk_format
, false);
452 /* Choose the SPI color formats. These are required values for Stoney/RB+.
453 * Other chips have multiple choices, though they are not necessarily better.
456 case V_028C70_COLOR_5_6_5
:
457 case V_028C70_COLOR_1_5_5_5
:
458 case V_028C70_COLOR_5_5_5_1
:
459 case V_028C70_COLOR_4_4_4_4
:
460 case V_028C70_COLOR_10_11_11
:
461 case V_028C70_COLOR_11_11_10
:
462 case V_028C70_COLOR_8
:
463 case V_028C70_COLOR_8_8
:
464 case V_028C70_COLOR_8_8_8_8
:
465 case V_028C70_COLOR_10_10_10_2
:
466 case V_028C70_COLOR_2_10_10_10
:
467 if (ntype
== V_028C70_NUMBER_UINT
)
468 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
469 else if (ntype
== V_028C70_NUMBER_SINT
)
470 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
472 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
475 case V_028C70_COLOR_16
:
476 case V_028C70_COLOR_16_16
:
477 case V_028C70_COLOR_16_16_16_16
:
478 if (ntype
== V_028C70_NUMBER_UNORM
||
479 ntype
== V_028C70_NUMBER_SNORM
) {
480 /* UNORM16 and SNORM16 don't support blending */
481 if (ntype
== V_028C70_NUMBER_UNORM
)
482 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
484 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
486 /* Use 32 bits per channel for blending. */
487 if (format
== V_028C70_COLOR_16
) {
488 if (swap
== V_028C70_SWAP_STD
) { /* R */
489 blend
= V_028714_SPI_SHADER_32_R
;
490 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
491 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
492 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
495 } else if (format
== V_028C70_COLOR_16_16
) {
496 if (swap
== V_028C70_SWAP_STD
) { /* RG */
497 blend
= V_028714_SPI_SHADER_32_GR
;
498 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
499 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
500 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
503 } else /* 16_16_16_16 */
504 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
505 } else if (ntype
== V_028C70_NUMBER_UINT
)
506 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
507 else if (ntype
== V_028C70_NUMBER_SINT
)
508 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
509 else if (ntype
== V_028C70_NUMBER_FLOAT
)
510 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
515 case V_028C70_COLOR_32
:
516 if (swap
== V_028C70_SWAP_STD
) { /* R */
517 blend
= normal
= V_028714_SPI_SHADER_32_R
;
518 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
519 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
520 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
525 case V_028C70_COLOR_32_32
:
526 if (swap
== V_028C70_SWAP_STD
) { /* RG */
527 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
528 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
529 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
530 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
535 case V_028C70_COLOR_32_32_32_32
:
536 case V_028C70_COLOR_8_24
:
537 case V_028C70_COLOR_24_8
:
538 case V_028C70_COLOR_X24_8_32_FLOAT
:
539 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
543 unreachable("unhandled blend format");
546 if (blend_enable
&& blend_need_alpha
)
548 else if(blend_need_alpha
)
550 else if(blend_enable
)
557 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
558 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
559 struct radv_blend_state
*blend
)
561 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
562 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
563 unsigned col_format
= 0;
564 unsigned num_targets
;
566 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
569 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
570 cf
= V_028714_SPI_SHADER_ZERO
;
572 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
574 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
576 cf
= si_choose_spi_color_format(attachment
->format
,
578 blend
->need_src_alpha
& (1 << i
));
581 col_format
|= cf
<< (4 * i
);
584 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
585 /* When a subpass doesn't have any color attachments, write the
586 * alpha channel of MRT0 when alpha coverage is enabled because
587 * the depth attachment needs it.
589 col_format
|= V_028714_SPI_SHADER_32_AR
;
592 /* If the i-th target format is set, all previous target formats must
593 * be non-zero to avoid hangs.
595 num_targets
= (util_last_bit(col_format
) + 3) / 4;
596 for (unsigned i
= 0; i
< num_targets
; i
++) {
597 if (!(col_format
& (0xf << (i
* 4)))) {
598 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
602 /* The output for dual source blending should have the same format as
605 if (blend
->mrt0_is_dual_src
)
606 col_format
|= (col_format
& 0xf) << 4;
608 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
609 blend
->spi_shader_col_format
= col_format
;
613 format_is_int8(VkFormat format
)
615 const struct vk_format_description
*desc
= vk_format_description(format
);
616 int channel
= vk_format_get_first_non_void_channel(format
);
618 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
619 desc
->channel
[channel
].size
== 8;
623 format_is_int10(VkFormat format
)
625 const struct vk_format_description
*desc
= vk_format_description(format
);
627 if (desc
->nr_channels
!= 4)
629 for (unsigned i
= 0; i
< 4; i
++) {
630 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
637 * Ordered so that for each i,
638 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
640 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
641 VK_FORMAT_R32_SFLOAT
,
642 VK_FORMAT_R32G32_SFLOAT
,
643 VK_FORMAT_R8G8B8A8_UNORM
,
644 VK_FORMAT_R16G16B16A16_UNORM
,
645 VK_FORMAT_R16G16B16A16_SNORM
,
646 VK_FORMAT_R16G16B16A16_UINT
,
647 VK_FORMAT_R16G16B16A16_SINT
,
648 VK_FORMAT_R32G32B32A32_SFLOAT
,
649 VK_FORMAT_R8G8B8A8_UINT
,
650 VK_FORMAT_R8G8B8A8_SINT
,
651 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
652 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
655 unsigned radv_format_meta_fs_key(VkFormat format
)
657 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
659 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
660 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
661 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
663 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
664 bool is_int8
= format_is_int8(format
);
665 bool is_int10
= format_is_int10(format
);
667 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
671 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
672 unsigned *is_int8
, unsigned *is_int10
)
674 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
675 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
679 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
680 struct radv_render_pass_attachment
*attachment
;
682 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
685 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
687 if (format_is_int8(attachment
->format
))
689 if (format_is_int10(attachment
->format
))
695 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
696 VkBlendOp op
, VkBlendFactor src
,
697 VkBlendFactor dst
, unsigned chanmask
)
699 /* Src factor is allowed when it does not depend on Dst. */
700 static const uint32_t src_allowed
=
701 (1u << VK_BLEND_FACTOR_ONE
) |
702 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
703 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
704 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
705 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
706 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
707 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
708 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
709 (1u << VK_BLEND_FACTOR_ZERO
) |
710 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
711 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
712 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
713 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
714 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
715 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
717 if (dst
== VK_BLEND_FACTOR_ONE
&&
718 (src_allowed
& (1u << src
))) {
719 /* Addition is commutative, but floating point addition isn't
720 * associative: subtle changes can be introduced via different
721 * rounding. Be conservative, only enable for min and max.
723 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
724 blend
->commutative_4bit
|= chanmask
;
728 static struct radv_blend_state
729 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
730 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
731 const struct radv_graphics_pipeline_create_info
*extra
)
733 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
734 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
735 struct radv_blend_state blend
= {0};
736 unsigned mode
= V_028808_CB_NORMAL
;
739 if (extra
&& extra
->custom_blend_mode
) {
740 blend
.single_cb_enable
= true;
741 mode
= extra
->custom_blend_mode
;
744 blend
.cb_color_control
= 0;
746 if (vkblend
->logicOpEnable
)
747 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
749 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
752 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
753 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
754 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
755 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
756 S_028B70_OFFSET_ROUND(1);
758 if (vkms
&& vkms
->alphaToCoverageEnable
) {
759 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
760 blend
.need_src_alpha
|= 0x1;
763 blend
.cb_target_mask
= 0;
765 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
766 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
767 unsigned blend_cntl
= 0;
768 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
769 VkBlendOp eqRGB
= att
->colorBlendOp
;
770 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
771 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
772 VkBlendOp eqA
= att
->alphaBlendOp
;
773 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
774 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
776 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
778 if (!att
->colorWriteMask
)
781 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
782 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
783 if (!att
->blendEnable
) {
784 blend
.cb_blend_control
[i
] = blend_cntl
;
788 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
790 blend
.mrt0_is_dual_src
= true;
792 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
793 srcRGB
= VK_BLEND_FACTOR_ONE
;
794 dstRGB
= VK_BLEND_FACTOR_ONE
;
796 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
797 srcA
= VK_BLEND_FACTOR_ONE
;
798 dstA
= VK_BLEND_FACTOR_ONE
;
801 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
803 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
806 /* Blending optimizations for RB+.
807 * These transformations don't change the behavior.
809 * First, get rid of DST in the blend factors:
810 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
812 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
813 VK_BLEND_FACTOR_DST_COLOR
,
814 VK_BLEND_FACTOR_SRC_COLOR
);
816 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
817 VK_BLEND_FACTOR_DST_COLOR
,
818 VK_BLEND_FACTOR_SRC_COLOR
);
820 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
821 VK_BLEND_FACTOR_DST_ALPHA
,
822 VK_BLEND_FACTOR_SRC_ALPHA
);
824 /* Look up the ideal settings from tables. */
825 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
826 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
827 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
828 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
830 /* Handle interdependencies. */
831 if (si_blend_factor_uses_dst(srcRGB
))
832 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
833 if (si_blend_factor_uses_dst(srcA
))
834 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
836 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
837 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
838 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
839 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
840 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
842 /* Set the final value. */
843 blend
.sx_mrt_blend_opt
[i
] =
844 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
845 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
846 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
847 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
848 S_028760_ALPHA_DST_OPT(dstA_opt
) |
849 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
850 blend_cntl
|= S_028780_ENABLE(1);
852 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
853 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
854 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
855 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
856 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
857 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
858 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
859 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
861 blend
.cb_blend_control
[i
] = blend_cntl
;
863 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
865 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
866 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
867 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
868 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
869 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
870 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
871 blend
.need_src_alpha
|= 1 << i
;
873 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
874 blend
.cb_blend_control
[i
] = 0;
875 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
879 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
880 /* Disable RB+ blend optimizations for dual source blending. */
881 if (blend
.mrt0_is_dual_src
) {
882 for (i
= 0; i
< 8; i
++) {
883 blend
.sx_mrt_blend_opt
[i
] =
884 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
885 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
889 /* RB+ doesn't work with dual source blending, logic op and
892 if (blend
.mrt0_is_dual_src
||
893 (vkblend
&& vkblend
->logicOpEnable
) ||
894 mode
== V_028808_CB_RESOLVE
)
895 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
898 if (blend
.cb_target_mask
)
899 blend
.cb_color_control
|= S_028808_MODE(mode
);
901 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
903 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
907 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
910 case VK_STENCIL_OP_KEEP
:
911 return V_02842C_STENCIL_KEEP
;
912 case VK_STENCIL_OP_ZERO
:
913 return V_02842C_STENCIL_ZERO
;
914 case VK_STENCIL_OP_REPLACE
:
915 return V_02842C_STENCIL_REPLACE_TEST
;
916 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
917 return V_02842C_STENCIL_ADD_CLAMP
;
918 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
919 return V_02842C_STENCIL_SUB_CLAMP
;
920 case VK_STENCIL_OP_INVERT
:
921 return V_02842C_STENCIL_INVERT
;
922 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
923 return V_02842C_STENCIL_ADD_WRAP
;
924 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
925 return V_02842C_STENCIL_SUB_WRAP
;
931 static uint32_t si_translate_fill(VkPolygonMode func
)
934 case VK_POLYGON_MODE_FILL
:
935 return V_028814_X_DRAW_TRIANGLES
;
936 case VK_POLYGON_MODE_LINE
:
937 return V_028814_X_DRAW_LINES
;
938 case VK_POLYGON_MODE_POINT
:
939 return V_028814_X_DRAW_POINTS
;
942 return V_028814_X_DRAW_POINTS
;
946 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
948 uint32_t num_samples
= vkms
->rasterizationSamples
;
949 uint32_t ps_iter_samples
= 1;
951 if (vkms
->sampleShadingEnable
) {
952 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
953 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
955 return ps_iter_samples
;
959 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
961 return pCreateInfo
->depthTestEnable
&&
962 pCreateInfo
->depthWriteEnable
&&
963 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
967 radv_writes_stencil(const VkStencilOpState
*state
)
969 return state
->writeMask
&&
970 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
971 state
->passOp
!= VK_STENCIL_OP_KEEP
||
972 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
976 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
978 return pCreateInfo
->stencilTestEnable
&&
979 (radv_writes_stencil(&pCreateInfo
->front
) ||
980 radv_writes_stencil(&pCreateInfo
->back
));
984 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
986 return radv_is_depth_write_enabled(pCreateInfo
) ||
987 radv_is_stencil_write_enabled(pCreateInfo
);
991 radv_order_invariant_stencil_op(VkStencilOp op
)
993 /* REPLACE is normally order invariant, except when the stencil
994 * reference value is written by the fragment shader. Tracking this
995 * interaction does not seem worth the effort, so be conservative.
997 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
998 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
999 op
!= VK_STENCIL_OP_REPLACE
;
1003 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
1005 /* Compute whether, assuming Z writes are disabled, this stencil state
1006 * is order invariant in the sense that the set of passing fragments as
1007 * well as the final stencil buffer result does not depend on the order
1010 return !state
->writeMask
||
1011 /* The following assumes that Z writes are disabled. */
1012 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
1013 radv_order_invariant_stencil_op(state
->passOp
) &&
1014 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
1015 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
1016 radv_order_invariant_stencil_op(state
->failOp
));
1020 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
1021 struct radv_blend_state
*blend
,
1022 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1024 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1025 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1026 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
1027 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1029 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1032 /* Be conservative if a logic operation is enabled with color buffers. */
1033 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
1036 /* Default depth/stencil invariance when no attachment is bound. */
1037 struct radv_dsa_order_invariance dsa_order_invariant
= {
1038 .zs
= true, .pass_set
= true
1042 struct radv_render_pass_attachment
*attachment
=
1043 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1044 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1045 struct radv_dsa_order_invariance order_invariance
[2];
1046 struct radv_shader_variant
*ps
=
1047 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1049 /* Compute depth/stencil order invariance in order to know if
1050 * it's safe to enable out-of-order.
1052 bool zfunc_is_ordered
=
1053 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1054 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1055 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1056 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1057 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1059 bool nozwrite_and_order_invariant_stencil
=
1060 !radv_is_ds_write_enabled(vkds
) ||
1061 (!radv_is_depth_write_enabled(vkds
) &&
1062 radv_order_invariant_stencil_state(&vkds
->front
) &&
1063 radv_order_invariant_stencil_state(&vkds
->back
));
1065 order_invariance
[1].zs
=
1066 nozwrite_and_order_invariant_stencil
||
1067 (!radv_is_stencil_write_enabled(vkds
) &&
1069 order_invariance
[0].zs
=
1070 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1072 order_invariance
[1].pass_set
=
1073 nozwrite_and_order_invariant_stencil
||
1074 (!radv_is_stencil_write_enabled(vkds
) &&
1075 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1076 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1077 order_invariance
[0].pass_set
=
1078 !radv_is_depth_write_enabled(vkds
) ||
1079 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1080 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1082 dsa_order_invariant
= order_invariance
[has_stencil
];
1083 if (!dsa_order_invariant
.zs
)
1086 /* The set of PS invocations is always order invariant,
1087 * except when early Z/S tests are requested.
1090 ps
->info
.ps
.writes_memory
&&
1091 ps
->info
.ps
.early_fragment_test
&&
1092 !dsa_order_invariant
.pass_set
)
1095 /* Determine if out-of-order rasterization should be disabled
1096 * when occlusion queries are used.
1098 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1099 !dsa_order_invariant
.pass_set
;
1102 /* No color buffers are enabled for writing. */
1106 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1109 /* Only commutative blending. */
1110 if (blendmask
& ~blend
->commutative_4bit
)
1113 if (!dsa_order_invariant
.pass_set
)
1117 if (colormask
& ~blendmask
)
1124 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1125 struct radv_blend_state
*blend
,
1126 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1128 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1129 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1130 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1131 bool out_of_order_rast
= false;
1132 int ps_iter_samples
= 1;
1133 uint32_t mask
= 0xffff;
1136 ms
->num_samples
= vkms
->rasterizationSamples
;
1138 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1140 * "Sample shading is enabled for a graphics pipeline:
1142 * - If the interface of the fragment shader entry point of the
1143 * graphics pipeline includes an input variable decorated
1144 * with SampleId or SamplePosition. In this case
1145 * minSampleShadingFactor takes the value 1.0.
1146 * - Else if the sampleShadingEnable member of the
1147 * VkPipelineMultisampleStateCreateInfo structure specified
1148 * when creating the graphics pipeline is set to VK_TRUE. In
1149 * this case minSampleShadingFactor takes the value of
1150 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1152 * Otherwise, sample shading is considered disabled."
1154 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1155 ps_iter_samples
= ms
->num_samples
;
1157 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1160 ms
->num_samples
= 1;
1163 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1164 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1165 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1166 /* Out-of-order rasterization is explicitly enabled by the
1169 out_of_order_rast
= true;
1171 /* Determine if the driver can enable out-of-order
1172 * rasterization internally.
1175 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1178 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1179 ms
->pa_sc_aa_config
= 0;
1180 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1181 S_028804_INCOHERENT_EQAA_READS(1) |
1182 S_028804_INTERPOLATE_COMP_Z(1) |
1183 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1184 ms
->pa_sc_mode_cntl_1
=
1185 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1186 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1187 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1188 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1190 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1191 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1192 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1193 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1194 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1195 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1196 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1197 S_028A48_VPORT_SCISSOR_ENABLE(1);
1199 if (ms
->num_samples
> 1) {
1200 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1201 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1202 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1203 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1204 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1205 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1206 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1207 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1208 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1209 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1210 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1211 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1212 if (ps_iter_samples
> 1)
1213 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1216 if (vkms
&& vkms
->pSampleMask
) {
1217 mask
= vkms
->pSampleMask
[0] & 0xffff;
1220 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1221 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1225 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1228 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1239 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1242 unreachable("unhandled primitive type");
1247 si_translate_prim(enum VkPrimitiveTopology topology
)
1250 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1251 return V_008958_DI_PT_POINTLIST
;
1252 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1253 return V_008958_DI_PT_LINELIST
;
1254 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1255 return V_008958_DI_PT_LINESTRIP
;
1256 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1257 return V_008958_DI_PT_TRILIST
;
1258 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1259 return V_008958_DI_PT_TRISTRIP
;
1260 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1261 return V_008958_DI_PT_TRIFAN
;
1262 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1263 return V_008958_DI_PT_LINELIST_ADJ
;
1264 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1265 return V_008958_DI_PT_LINESTRIP_ADJ
;
1266 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1267 return V_008958_DI_PT_TRILIST_ADJ
;
1268 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1269 return V_008958_DI_PT_TRISTRIP_ADJ
;
1270 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1271 return V_008958_DI_PT_PATCH
;
1279 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1282 case 0: /* GL_POINTS */
1283 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1284 case 1: /* GL_LINES */
1285 case 3: /* GL_LINE_STRIP */
1286 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1287 case 0x8E7A: /* GL_ISOLINES */
1288 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1290 case 4: /* GL_TRIANGLES */
1291 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1292 case 5: /* GL_TRIANGLE_STRIP */
1293 case 7: /* GL_QUADS */
1294 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1302 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1305 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1306 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1307 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1308 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1309 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1310 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1311 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1312 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1313 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1314 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1315 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1316 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1317 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1318 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1325 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1328 case VK_DYNAMIC_STATE_VIEWPORT
:
1329 return RADV_DYNAMIC_VIEWPORT
;
1330 case VK_DYNAMIC_STATE_SCISSOR
:
1331 return RADV_DYNAMIC_SCISSOR
;
1332 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1333 return RADV_DYNAMIC_LINE_WIDTH
;
1334 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1335 return RADV_DYNAMIC_DEPTH_BIAS
;
1336 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1337 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1338 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1339 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1340 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1341 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1342 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1343 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1344 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1345 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1346 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1347 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1348 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1349 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1351 unreachable("Unhandled dynamic state");
1355 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1357 uint32_t states
= RADV_DYNAMIC_ALL
;
1359 /* If rasterization is disabled we do not care about any of the dynamic states,
1360 * since they are all rasterization related only. */
1361 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1364 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1365 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1367 if (!pCreateInfo
->pDepthStencilState
||
1368 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1369 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1371 if (!pCreateInfo
->pDepthStencilState
||
1372 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1373 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1374 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1375 RADV_DYNAMIC_STENCIL_REFERENCE
);
1377 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1378 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1380 if (!pCreateInfo
->pMultisampleState
||
1381 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1382 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1383 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1385 /* TODO: blend constants & line width. */
1392 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1393 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1395 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1396 uint32_t states
= needed_states
;
1397 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1398 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1400 pipeline
->dynamic_state
= default_dynamic_state
;
1401 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1403 if (pCreateInfo
->pDynamicState
) {
1404 /* Remove all of the states that are marked as dynamic */
1405 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1406 for (uint32_t s
= 0; s
< count
; s
++)
1407 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1410 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1412 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1413 assert(pCreateInfo
->pViewportState
);
1415 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1416 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1417 typed_memcpy(dynamic
->viewport
.viewports
,
1418 pCreateInfo
->pViewportState
->pViewports
,
1419 pCreateInfo
->pViewportState
->viewportCount
);
1423 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1424 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1425 if (states
& RADV_DYNAMIC_SCISSOR
) {
1426 typed_memcpy(dynamic
->scissor
.scissors
,
1427 pCreateInfo
->pViewportState
->pScissors
,
1428 pCreateInfo
->pViewportState
->scissorCount
);
1432 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1433 assert(pCreateInfo
->pRasterizationState
);
1434 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1437 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1438 assert(pCreateInfo
->pRasterizationState
);
1439 dynamic
->depth_bias
.bias
=
1440 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1441 dynamic
->depth_bias
.clamp
=
1442 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1443 dynamic
->depth_bias
.slope
=
1444 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1447 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1449 * pColorBlendState is [...] NULL if the pipeline has rasterization
1450 * disabled or if the subpass of the render pass the pipeline is
1451 * created against does not use any color attachments.
1453 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1454 assert(pCreateInfo
->pColorBlendState
);
1455 typed_memcpy(dynamic
->blend_constants
,
1456 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1459 /* If there is no depthstencil attachment, then don't read
1460 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1461 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1462 * no need to override the depthstencil defaults in
1463 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1465 * Section 9.2 of the Vulkan 1.0.15 spec says:
1467 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1468 * disabled or if the subpass of the render pass the pipeline is created
1469 * against does not use a depth/stencil attachment.
1471 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1472 assert(pCreateInfo
->pDepthStencilState
);
1474 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1475 dynamic
->depth_bounds
.min
=
1476 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1477 dynamic
->depth_bounds
.max
=
1478 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1481 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1482 dynamic
->stencil_compare_mask
.front
=
1483 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1484 dynamic
->stencil_compare_mask
.back
=
1485 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1488 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1489 dynamic
->stencil_write_mask
.front
=
1490 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1491 dynamic
->stencil_write_mask
.back
=
1492 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1495 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1496 dynamic
->stencil_reference
.front
=
1497 pCreateInfo
->pDepthStencilState
->front
.reference
;
1498 dynamic
->stencil_reference
.back
=
1499 pCreateInfo
->pDepthStencilState
->back
.reference
;
1503 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1504 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1505 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1506 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1507 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1508 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1509 discard_rectangle_info
->pDiscardRectangles
,
1510 discard_rectangle_info
->discardRectangleCount
);
1514 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1515 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1516 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1517 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1518 /* If sampleLocationsEnable is VK_FALSE, the default sample
1519 * locations are used and the values specified in
1520 * sampleLocationsInfo are ignored.
1522 if (sample_location_info
->sampleLocationsEnable
) {
1523 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1524 &sample_location_info
->sampleLocationsInfo
;
1526 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1528 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1529 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1530 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1531 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1532 pSampleLocationsInfo
->pSampleLocations
,
1533 pSampleLocationsInfo
->sampleLocationsCount
);
1537 pipeline
->dynamic_state
.mask
= states
;
1541 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1542 const struct radv_pipeline
*pipeline
,
1544 struct radv_shader_info
*infos
,
1545 struct gfx9_gs_info
*out
)
1547 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1548 struct radv_es_output_info
*es_info
;
1549 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1550 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1552 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1553 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1554 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1556 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1557 bool uses_adjacency
;
1558 switch(key
->topology
) {
1559 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1560 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1561 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1562 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1563 uses_adjacency
= true;
1566 uses_adjacency
= false;
1570 /* All these are in dwords: */
1571 /* We can't allow using the whole LDS, because GS waves compete with
1572 * other shader stages for LDS space. */
1573 const unsigned max_lds_size
= 8 * 1024;
1574 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1575 unsigned esgs_lds_size
;
1577 /* All these are per subgroup: */
1578 const unsigned max_out_prims
= 32 * 1024;
1579 const unsigned max_es_verts
= 255;
1580 const unsigned ideal_gs_prims
= 64;
1581 unsigned max_gs_prims
, gs_prims
;
1582 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1584 if (uses_adjacency
|| gs_num_invocations
> 1)
1585 max_gs_prims
= 127 / gs_num_invocations
;
1589 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1590 * Make sure we don't go over the maximum value.
1592 if (gs_info
->gs
.vertices_out
> 0) {
1593 max_gs_prims
= MIN2(max_gs_prims
,
1595 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1597 assert(max_gs_prims
> 0);
1599 /* If the primitive has adjacency, halve the number of vertices
1600 * that will be reused in multiple primitives.
1602 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1604 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1605 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1607 /* Compute ESGS LDS size based on the worst case number of ES vertices
1608 * needed to create the target number of GS prims per subgroup.
1610 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1612 /* If total LDS usage is too big, refactor partitions based on ratio
1613 * of ESGS item sizes.
1615 if (esgs_lds_size
> max_lds_size
) {
1616 /* Our target GS Prims Per Subgroup was too large. Calculate
1617 * the maximum number of GS Prims Per Subgroup that will fit
1618 * into LDS, capped by the maximum that the hardware can support.
1620 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1622 assert(gs_prims
> 0);
1623 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1626 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1627 assert(esgs_lds_size
<= max_lds_size
);
1630 /* Now calculate remaining ESGS information. */
1632 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1634 es_verts
= max_es_verts
;
1636 /* Vertices for adjacency primitives are not always reused, so restore
1637 * it for ES_VERTS_PER_SUBGRP.
1639 min_es_verts
= gs_info
->gs
.vertices_in
;
1641 /* For normal primitives, the VGT only checks if they are past the ES
1642 * verts per subgroup after allocating a full GS primitive and if they
1643 * are, kick off a new subgroup. But if those additional ES verts are
1644 * unique (e.g. not reused) we need to make sure there is enough LDS
1645 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1647 es_verts
-= min_es_verts
- 1;
1649 uint32_t es_verts_per_subgroup
= es_verts
;
1650 uint32_t gs_prims_per_subgroup
= gs_prims
;
1651 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1652 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1653 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1654 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1655 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1656 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1657 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1658 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1659 assert(max_prims_per_subgroup
<= max_out_prims
);
1662 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1663 unsigned min_verts_per_prim
, bool use_adjacency
)
1665 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1668 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1672 radv_get_num_input_vertices(nir_shader
**nir
)
1674 if (nir
[MESA_SHADER_GEOMETRY
]) {
1675 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1677 return gs
->info
.gs
.vertices_in
;
1680 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1681 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1683 if (tes
->info
.tess
.point_mode
)
1685 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1694 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1695 struct radv_pipeline
*pipeline
,
1697 struct radv_shader_info
*infos
,
1698 struct gfx10_ngg_info
*ngg
)
1700 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1701 struct radv_es_output_info
*es_info
=
1702 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1703 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1704 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1705 unsigned min_verts_per_prim
=
1706 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1707 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1708 bool uses_adjacency
;
1709 switch(key
->topology
) {
1710 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1711 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1712 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1713 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1714 uses_adjacency
= true;
1717 uses_adjacency
= false;
1721 /* All these are in dwords: */
1722 /* We can't allow using the whole LDS, because GS waves compete with
1723 * other shader stages for LDS space.
1725 * TODO: We should really take the shader's internal LDS use into
1726 * account. The linker will fail if the size is greater than
1729 const unsigned max_lds_size
= 8 * 1024 - 768;
1730 const unsigned target_lds_size
= max_lds_size
;
1731 unsigned esvert_lds_size
= 0;
1732 unsigned gsprim_lds_size
= 0;
1734 /* All these are per subgroup: */
1735 bool max_vert_out_per_gs_instance
= false;
1736 unsigned max_esverts_base
= 256;
1737 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1739 /* Hardware has the following non-natural restrictions on the value
1740 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1742 * - at most 252 for any line input primitive type
1743 * - at most 251 for any quad input primitive type
1744 * - at most 251 for triangle strips with adjacency (this happens to
1745 * be the natural limit for triangle *lists* with adjacency)
1747 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1749 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1750 unsigned max_out_verts_per_gsprim
=
1751 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1753 if (max_out_verts_per_gsprim
<= 256) {
1754 if (max_out_verts_per_gsprim
) {
1755 max_gsprims_base
= MIN2(max_gsprims_base
,
1756 256 / max_out_verts_per_gsprim
);
1759 /* Use special multi-cycling mode in which each GS
1760 * instance gets its own subgroup. Does not work with
1762 max_vert_out_per_gs_instance
= true;
1763 max_gsprims_base
= 1;
1764 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1767 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1768 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1771 /* LDS size for passing data from GS to ES. */
1772 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1773 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1774 : &infos
[MESA_SHADER_VERTEX
].so
;
1776 if (so_info
->num_outputs
)
1777 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1779 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1780 * corresponding to the ES thread of the provoking vertex. All
1781 * ES threads load and export PrimitiveID for their thread.
1783 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1784 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1785 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1788 unsigned max_gsprims
= max_gsprims_base
;
1789 unsigned max_esverts
= max_esverts_base
;
1791 if (esvert_lds_size
)
1792 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1793 if (gsprim_lds_size
)
1794 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1796 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1797 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1798 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1800 if (esvert_lds_size
|| gsprim_lds_size
) {
1801 /* Now that we have a rough proportionality between esverts
1802 * and gsprims based on the primitive type, scale both of them
1803 * down simultaneously based on required LDS space.
1805 * We could be smarter about this if we knew how much vertex
1808 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1809 max_gsprims
* gsprim_lds_size
;
1810 if (lds_total
> target_lds_size
) {
1811 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1812 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1814 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1815 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1816 min_verts_per_prim
, uses_adjacency
);
1817 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1821 /* Round up towards full wave sizes for better ALU utilization. */
1822 if (!max_vert_out_per_gs_instance
) {
1823 unsigned orig_max_esverts
;
1824 unsigned orig_max_gsprims
;
1827 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1828 wavesize
= gs_info
->wave_size
;
1830 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1831 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1832 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1836 orig_max_esverts
= max_esverts
;
1837 orig_max_gsprims
= max_gsprims
;
1839 max_esverts
= align(max_esverts
, wavesize
);
1840 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1841 if (esvert_lds_size
)
1842 max_esverts
= MIN2(max_esverts
,
1843 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1845 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1847 max_gsprims
= align(max_gsprims
, wavesize
);
1848 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1849 if (gsprim_lds_size
)
1850 max_gsprims
= MIN2(max_gsprims
,
1851 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1853 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1854 min_verts_per_prim
, uses_adjacency
);
1855 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1856 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1859 /* Hardware restriction: minimum value of max_esverts */
1860 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1862 unsigned max_out_vertices
=
1863 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1864 gs_type
== MESA_SHADER_GEOMETRY
?
1865 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1867 assert(max_out_vertices
<= 256);
1869 unsigned prim_amp_factor
= 1;
1870 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1871 /* Number of output primitives per GS input primitive after
1873 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1876 /* The GE only checks against the maximum number of ES verts after
1877 * allocating a full GS primitive. So we need to ensure that whenever
1878 * this check passes, there is enough space for a full primitive without
1881 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1882 ngg
->max_gsprims
= max_gsprims
;
1883 ngg
->max_out_verts
= max_out_vertices
;
1884 ngg
->prim_amp_factor
= prim_amp_factor
;
1885 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1886 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1887 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1889 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1890 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1892 ngg
->vgt_esgs_ring_itemsize
= 1;
1895 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1897 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1901 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1902 const struct gfx9_gs_info
*gs
)
1904 struct radv_device
*device
= pipeline
->device
;
1905 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1906 unsigned wave_size
= 64;
1907 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1908 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1909 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1911 unsigned gs_vertex_reuse
=
1912 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1913 unsigned alignment
= 256 * num_se
;
1914 /* The maximum size is 63.999 MB per SE. */
1915 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1916 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1918 /* Calculate the minimum size. */
1919 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1920 wave_size
, alignment
);
1921 /* These are recommended sizes, not minimum sizes. */
1922 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1923 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1924 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1925 gs_info
->gs
.max_gsvs_emit_size
;
1927 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1928 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1929 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1931 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1932 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1934 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1937 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1940 /* If tessellation is all offchip and on-chip GS isn't used, this
1941 * workaround is not needed.
1945 /* SPI barrier management bug:
1946 * Make sure we have at least 4k of LDS in use to avoid the bug.
1947 * It applies to workgroup sizes of more than one wavefront.
1949 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1950 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1951 *lds_size
= MAX2(*lds_size
, 8);
1954 struct radv_shader_variant
*
1955 radv_get_shader(struct radv_pipeline
*pipeline
,
1956 gl_shader_stage stage
)
1958 if (stage
== MESA_SHADER_VERTEX
) {
1959 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1960 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1961 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1962 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1963 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1964 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1965 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1966 if (!radv_pipeline_has_tess(pipeline
))
1968 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1969 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1970 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1971 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1973 return pipeline
->shaders
[stage
];
1976 static struct radv_tessellation_state
1977 calculate_tess_state(struct radv_pipeline
*pipeline
,
1978 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1980 unsigned num_tcs_input_cp
;
1981 unsigned num_tcs_output_cp
;
1983 unsigned num_patches
;
1984 struct radv_tessellation_state tess
= {0};
1986 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1987 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1988 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1990 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1992 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1993 assert(lds_size
<= 65536);
1994 lds_size
= align(lds_size
, 512) / 512;
1996 assert(lds_size
<= 32768);
1997 lds_size
= align(lds_size
, 256) / 256;
1999 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
2001 tess
.lds_size
= lds_size
;
2003 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2004 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2005 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2006 tess
.num_patches
= num_patches
;
2008 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2009 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2011 switch (tes
->info
.tes
.primitive_mode
) {
2013 type
= V_028B6C_TESS_TRIANGLE
;
2016 type
= V_028B6C_TESS_QUAD
;
2019 type
= V_028B6C_TESS_ISOLINE
;
2023 switch (tes
->info
.tes
.spacing
) {
2024 case TESS_SPACING_EQUAL
:
2025 partitioning
= V_028B6C_PART_INTEGER
;
2027 case TESS_SPACING_FRACTIONAL_ODD
:
2028 partitioning
= V_028B6C_PART_FRAC_ODD
;
2030 case TESS_SPACING_FRACTIONAL_EVEN
:
2031 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2037 bool ccw
= tes
->info
.tes
.ccw
;
2038 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2039 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2040 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2042 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2045 if (tes
->info
.tes
.point_mode
)
2046 topology
= V_028B6C_OUTPUT_POINT
;
2047 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2048 topology
= V_028B6C_OUTPUT_LINE
;
2050 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2052 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2054 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2055 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2056 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2057 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2059 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2061 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2063 tess
.tf_param
= S_028B6C_TYPE(type
) |
2064 S_028B6C_PARTITIONING(partitioning
) |
2065 S_028B6C_TOPOLOGY(topology
) |
2066 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2071 static const struct radv_prim_vertex_count prim_size_table
[] = {
2072 [V_008958_DI_PT_NONE
] = {0, 0},
2073 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2074 [V_008958_DI_PT_LINELIST
] = {2, 2},
2075 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2076 [V_008958_DI_PT_TRILIST
] = {3, 3},
2077 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2078 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2079 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2080 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2081 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2082 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2083 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2084 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2085 [V_008958_DI_PT_POLYGON
] = {3, 1},
2086 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2089 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2091 if (radv_pipeline_has_gs(pipeline
))
2092 if (radv_pipeline_has_ngg(pipeline
))
2093 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2095 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2096 else if (radv_pipeline_has_tess(pipeline
))
2097 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2099 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2103 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2105 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2106 int shader_count
= 0;
2108 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2109 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2111 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2112 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2114 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2115 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2117 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2118 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2120 if(shaders
[MESA_SHADER_VERTEX
]) {
2121 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2124 if (shader_count
> 1) {
2125 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2126 unsigned last
= ordered_shaders
[0]->info
.stage
;
2128 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2129 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2130 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2132 for (int i
= 0; i
< shader_count
; ++i
) {
2133 nir_variable_mode mask
= 0;
2135 if (ordered_shaders
[i
]->info
.stage
!= first
)
2136 mask
= mask
| nir_var_shader_in
;
2138 if (ordered_shaders
[i
]->info
.stage
!= last
)
2139 mask
= mask
| nir_var_shader_out
;
2141 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2142 radv_optimize_nir(ordered_shaders
[i
], false, false);
2146 for (int i
= 1; i
< shader_count
; ++i
) {
2147 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2148 ordered_shaders
[i
- 1]);
2150 if (nir_link_opt_varyings(ordered_shaders
[i
],
2151 ordered_shaders
[i
- 1]))
2152 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2154 nir_remove_dead_variables(ordered_shaders
[i
],
2155 nir_var_shader_out
);
2156 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2159 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2160 ordered_shaders
[i
- 1]);
2162 nir_compact_varyings(ordered_shaders
[i
],
2163 ordered_shaders
[i
- 1], true);
2166 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2167 ac_lower_indirect_derefs(ordered_shaders
[i
],
2168 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2170 radv_optimize_nir(ordered_shaders
[i
], false, false);
2172 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2173 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2174 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2176 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2182 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2183 uint32_t attrib_binding
)
2185 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2186 const VkVertexInputBindingDescription
*input_binding
=
2187 &input_state
->pVertexBindingDescriptions
[i
];
2189 if (input_binding
->binding
== attrib_binding
)
2190 return input_binding
->stride
;
2196 static struct radv_pipeline_key
2197 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2198 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2199 const struct radv_blend_state
*blend
,
2200 bool has_view_index
)
2202 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2203 pCreateInfo
->pVertexInputState
;
2204 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2205 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2207 struct radv_pipeline_key key
;
2208 memset(&key
, 0, sizeof(key
));
2210 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2211 key
.optimisations_disabled
= 1;
2213 key
.has_multiview_view_index
= has_view_index
;
2215 uint32_t binding_input_rate
= 0;
2216 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2217 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2218 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2219 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2220 binding_input_rate
|= 1u << binding
;
2221 instance_rate_divisors
[binding
] = 1;
2224 if (divisor_state
) {
2225 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2226 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2227 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2231 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2232 const VkVertexInputAttributeDescription
*desc
=
2233 &input_state
->pVertexAttributeDescriptions
[i
];
2234 const struct vk_format_description
*format_desc
;
2235 unsigned location
= desc
->location
;
2236 unsigned binding
= desc
->binding
;
2237 unsigned num_format
, data_format
;
2240 if (binding_input_rate
& (1u << binding
)) {
2241 key
.instance_rate_inputs
|= 1u << location
;
2242 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2245 format_desc
= vk_format_description(desc
->format
);
2246 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2248 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2249 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2251 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2252 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2253 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2254 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2256 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2257 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2258 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2261 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2262 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2263 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2265 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2266 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2267 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2269 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2270 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2271 adjust
= RADV_ALPHA_ADJUST_SINT
;
2277 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2280 switch (desc
->format
) {
2281 case VK_FORMAT_B8G8R8A8_UNORM
:
2282 case VK_FORMAT_B8G8R8A8_SNORM
:
2283 case VK_FORMAT_B8G8R8A8_USCALED
:
2284 case VK_FORMAT_B8G8R8A8_SSCALED
:
2285 case VK_FORMAT_B8G8R8A8_UINT
:
2286 case VK_FORMAT_B8G8R8A8_SINT
:
2287 case VK_FORMAT_B8G8R8A8_SRGB
:
2288 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2289 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2290 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2291 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2292 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2293 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2294 key
.vertex_post_shuffle
|= 1 << location
;
2301 const VkPipelineTessellationStateCreateInfo
*tess
=
2302 radv_pipeline_get_tessellation_state(pCreateInfo
);
2304 key
.tess_input_vertices
= tess
->patchControlPoints
;
2306 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2307 radv_pipeline_get_multisample_state(pCreateInfo
);
2308 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2309 uint32_t num_samples
= vkms
->rasterizationSamples
;
2310 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
2311 key
.num_samples
= num_samples
;
2312 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2315 key
.col_format
= blend
->spi_shader_col_format
;
2316 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2317 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2319 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2320 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2326 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2328 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2329 bool uses_xfb
= !!xfb
;
2336 radv_fill_shader_keys(struct radv_device
*device
,
2337 struct radv_shader_variant_key
*keys
,
2338 const struct radv_pipeline_key
*key
,
2341 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2342 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2343 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2344 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2345 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2346 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2347 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2348 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2349 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2351 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2353 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2354 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2355 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2356 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2357 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2359 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2362 if (nir
[MESA_SHADER_GEOMETRY
]) {
2363 if (nir
[MESA_SHADER_TESS_CTRL
])
2364 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2366 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2369 if (device
->physical_device
->use_ngg
) {
2370 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2371 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2373 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2376 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2377 nir
[MESA_SHADER_GEOMETRY
] &&
2378 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2379 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2380 /* Fallback to the legacy path if tessellation is
2381 * enabled with extreme geometry because
2382 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2385 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2389 * Disable NGG with geometry shaders. There are a bunch of
2391 * * GS primitives in pipeline statistic queries do not get
2392 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2394 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2396 if (nir
[MESA_SHADER_GEOMETRY
]) {
2397 if (nir
[MESA_SHADER_TESS_CTRL
])
2398 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2400 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2403 if (!device
->physical_device
->use_ngg_streamout
) {
2404 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2406 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2411 if (nir
[last_xfb_stage
] &&
2412 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
])) {
2413 if (nir
[MESA_SHADER_TESS_CTRL
])
2414 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2416 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2421 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2422 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2424 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2425 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2426 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2427 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2428 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2430 if (nir
[MESA_SHADER_COMPUTE
]) {
2431 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2436 radv_get_wave_size(struct radv_device
*device
,
2437 const VkPipelineShaderStageCreateInfo
*pStage
,
2438 gl_shader_stage stage
,
2439 const struct radv_shader_variant_key
*key
)
2441 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2443 else if (stage
== MESA_SHADER_COMPUTE
) {
2444 if (key
->cs
.subgroup_size
) {
2445 /* Return the required subgroup size if specified. */
2446 return key
->cs
.subgroup_size
;
2448 return device
->physical_device
->cs_wave_size
;
2450 else if (stage
== MESA_SHADER_FRAGMENT
)
2451 return device
->physical_device
->ps_wave_size
;
2453 return device
->physical_device
->ge_wave_size
;
2457 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2458 const VkPipelineShaderStageCreateInfo
**pStages
,
2459 struct radv_shader_variant_key
*keys
,
2460 struct radv_shader_info
*infos
,
2463 unsigned active_stages
= 0;
2464 unsigned filled_stages
= 0;
2466 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2468 active_stages
|= (1 << i
);
2471 if (nir
[MESA_SHADER_FRAGMENT
]) {
2472 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2473 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2475 &keys
[MESA_SHADER_FRAGMENT
],
2476 &infos
[MESA_SHADER_FRAGMENT
]);
2478 /* TODO: These are no longer used as keys we should refactor this */
2479 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2480 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2481 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2482 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2483 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2484 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2485 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2486 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2487 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2488 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2489 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2490 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2492 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2495 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2496 nir
[MESA_SHADER_TESS_CTRL
]) {
2497 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2498 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2499 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2501 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2503 for (int i
= 0; i
< 2; i
++) {
2504 radv_nir_shader_info_pass(combined_nir
[i
],
2505 pipeline
->layout
, &key
,
2506 &infos
[MESA_SHADER_TESS_CTRL
]);
2509 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2510 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2511 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2512 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2514 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2515 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2518 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2519 nir
[MESA_SHADER_GEOMETRY
]) {
2520 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2521 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2523 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2525 for (int i
= 0; i
< 2; i
++) {
2526 radv_nir_shader_info_pass(combined_nir
[i
],
2529 &infos
[MESA_SHADER_GEOMETRY
]);
2532 filled_stages
|= (1 << pre_stage
);
2533 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2536 active_stages
^= filled_stages
;
2537 while (active_stages
) {
2538 int i
= u_bit_scan(&active_stages
);
2540 if (i
== MESA_SHADER_TESS_CTRL
) {
2541 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2542 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2545 if (i
== MESA_SHADER_TESS_EVAL
) {
2546 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2547 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2548 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2549 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2552 radv_nir_shader_info_init(&infos
[i
]);
2553 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2554 &keys
[i
], &infos
[i
]);
2557 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2559 infos
[i
].wave_size
=
2560 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2566 merge_tess_info(struct shader_info
*tes_info
,
2567 const struct shader_info
*tcs_info
)
2569 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2571 * "PointMode. Controls generation of points rather than triangles
2572 * or lines. This functionality defaults to disabled, and is
2573 * enabled if either shader stage includes the execution mode.
2575 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2576 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2577 * and OutputVertices, it says:
2579 * "One mode must be set in at least one of the tessellation
2582 * So, the fields can be set in either the TCS or TES, but they must
2583 * agree if set in both. Our backend looks at TES, so bitwise-or in
2584 * the values from the TCS.
2586 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2587 tes_info
->tess
.tcs_vertices_out
== 0 ||
2588 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2589 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2591 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2592 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2593 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2594 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2596 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2597 tes_info
->tess
.primitive_mode
== 0 ||
2598 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2599 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2600 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2601 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2605 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2610 if (ext
->pPipelineCreationFeedback
) {
2611 ext
->pPipelineCreationFeedback
->flags
= 0;
2612 ext
->pPipelineCreationFeedback
->duration
= 0;
2615 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2616 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2617 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2622 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2627 feedback
->duration
-= radv_get_current_time();
2628 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2632 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2637 feedback
->duration
+= radv_get_current_time();
2638 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2639 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2643 bool radv_aco_supported_stage(gl_shader_stage stage
, bool has_gs
, bool has_ts
)
2645 return (stage
== MESA_SHADER_VERTEX
&& !has_gs
&& !has_ts
) ||
2646 stage
== MESA_SHADER_FRAGMENT
||
2647 stage
== MESA_SHADER_COMPUTE
;
2650 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2651 struct radv_device
*device
,
2652 struct radv_pipeline_cache
*cache
,
2653 const struct radv_pipeline_key
*key
,
2654 const VkPipelineShaderStageCreateInfo
**pStages
,
2655 const VkPipelineCreateFlags flags
,
2656 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2657 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2659 struct radv_shader_module fs_m
= {0};
2660 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2661 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2662 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2663 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2664 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2665 unsigned char hash
[20], gs_copy_hash
[20];
2666 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2668 radv_start_feedback(pipeline_feedback
);
2670 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2672 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2673 if (modules
[i
]->nir
)
2674 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2675 strlen(modules
[i
]->nir
->info
.name
),
2678 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2682 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2683 memcpy(gs_copy_hash
, hash
, 20);
2684 gs_copy_hash
[0] ^= 1;
2686 bool found_in_application_cache
= true;
2687 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2688 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2689 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2690 &found_in_application_cache
);
2691 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2694 if (!keep_executable_info
&&
2695 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2696 &found_in_application_cache
) &&
2697 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2698 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2702 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2704 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2705 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2706 fs_m
.nir
= fs_b
.shader
;
2707 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2710 bool has_gs
= modules
[MESA_SHADER_GEOMETRY
];
2711 bool has_ts
= modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
];
2712 bool use_aco
= device
->physical_device
->use_aco
;
2714 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2715 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2720 radv_start_feedback(stage_feedbacks
[i
]);
2722 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2723 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2724 stage
? stage
->pName
: "main", i
,
2725 stage
? stage
->pSpecializationInfo
: NULL
,
2726 flags
, pipeline
->layout
, aco
);
2728 /* We don't want to alter meta shaders IR directly so clone it
2731 if (nir
[i
]->info
.name
) {
2732 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2735 radv_stop_feedback(stage_feedbacks
[i
], false);
2738 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2739 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2740 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2743 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2744 radv_link_shaders(pipeline
, nir
);
2746 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2748 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2749 nir_lower_non_uniform_ubo_access
|
2750 nir_lower_non_uniform_ssbo_access
|
2751 nir_lower_non_uniform_texture_access
|
2752 nir_lower_non_uniform_image_access
);
2754 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2756 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2759 if (radv_can_dump_shader(device
, modules
[i
], false))
2760 nir_print_shader(nir
[i
], stderr
);
2763 if (nir
[MESA_SHADER_FRAGMENT
])
2764 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2766 radv_fill_shader_keys(device
, keys
, key
, nir
);
2768 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2770 if ((nir
[MESA_SHADER_VERTEX
] &&
2771 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2772 (nir
[MESA_SHADER_TESS_EVAL
] &&
2773 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2774 struct gfx10_ngg_info
*ngg_info
;
2776 if (nir
[MESA_SHADER_GEOMETRY
])
2777 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2778 else if (nir
[MESA_SHADER_TESS_CTRL
])
2779 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2781 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2783 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2784 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2785 struct gfx9_gs_info
*gs_info
=
2786 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2788 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2791 if (nir
[MESA_SHADER_FRAGMENT
]) {
2792 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2793 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2795 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_FRAGMENT
, has_gs
, has_ts
);
2796 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2797 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2798 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2799 infos
+ MESA_SHADER_FRAGMENT
,
2800 keep_executable_info
, aco
,
2801 &binaries
[MESA_SHADER_FRAGMENT
]);
2803 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2806 /* TODO: These are no longer used as keys we should refactor this */
2807 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2808 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2809 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2810 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2811 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2812 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2813 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2814 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2815 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2816 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2817 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2818 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2821 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2822 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2823 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2824 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2825 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2827 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2829 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2831 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2832 false, &binaries
[MESA_SHADER_TESS_CTRL
]);
2834 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2836 modules
[MESA_SHADER_VERTEX
] = NULL
;
2837 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2838 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2841 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2842 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2843 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2844 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2846 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2848 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2850 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2851 false, &binaries
[MESA_SHADER_GEOMETRY
]);
2853 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2855 modules
[pre_stage
] = NULL
;
2858 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2859 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2860 if (i
== MESA_SHADER_TESS_CTRL
) {
2861 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2863 if (i
== MESA_SHADER_TESS_EVAL
) {
2864 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2865 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2868 radv_start_feedback(stage_feedbacks
[i
]);
2870 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2871 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2873 keys
+ i
, infos
+ i
,keep_executable_info
,
2876 radv_stop_feedback(stage_feedbacks
[i
], false);
2880 if(modules
[MESA_SHADER_GEOMETRY
]) {
2881 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2882 if (!pipeline
->gs_copy_shader
&&
2883 !radv_pipeline_has_ngg(pipeline
)) {
2884 struct radv_shader_info info
= {};
2885 struct radv_shader_variant_key key
= {};
2887 key
.has_multiview_view_index
=
2888 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2890 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2891 pipeline
->layout
, &key
,
2893 info
.wave_size
= 64; /* Wave32 not supported. */
2895 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2896 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2897 &gs_copy_binary
, keep_executable_info
,
2898 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2901 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2902 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2903 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2905 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2906 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2908 radv_pipeline_cache_insert_shaders(device
, cache
,
2913 free(gs_copy_binary
);
2916 if (!keep_executable_info
) {
2917 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2921 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2924 ralloc_free(nir
[i
]);
2926 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2927 radv_shader_dump_stats(device
,
2928 pipeline
->shaders
[i
],
2934 ralloc_free(fs_m
.nir
);
2936 radv_stop_feedback(pipeline_feedback
, false);
2940 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2941 gl_shader_stage stage
, enum chip_class chip_class
)
2943 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2944 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2945 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2948 case MESA_SHADER_FRAGMENT
:
2949 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2950 case MESA_SHADER_VERTEX
:
2952 if (chip_class
>= GFX10
) {
2953 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2954 } else if (chip_class
== GFX9
) {
2955 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2957 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2963 if (chip_class
>= GFX10
) {
2964 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2966 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2971 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2973 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2974 case MESA_SHADER_GEOMETRY
:
2975 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2976 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2977 case MESA_SHADER_COMPUTE
:
2978 return R_00B900_COMPUTE_USER_DATA_0
;
2979 case MESA_SHADER_TESS_CTRL
:
2980 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2981 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2982 case MESA_SHADER_TESS_EVAL
:
2984 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
2985 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2986 } else if (has_ngg
) {
2987 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2989 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2992 unreachable("unknown shader");
2996 struct radv_bin_size_entry
{
3002 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3004 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3008 /* One shader engine */
3014 { UINT_MAX
, { 0, 0}},
3017 /* Two shader engines */
3023 { UINT_MAX
, { 0, 0}},
3026 /* Four shader engines */
3031 { UINT_MAX
, { 0, 0}},
3037 /* One shader engine */
3043 { UINT_MAX
, { 0, 0}},
3046 /* Two shader engines */
3052 { UINT_MAX
, { 0, 0}},
3055 /* Four shader engines */
3062 { UINT_MAX
, { 0, 0}},
3068 /* One shader engine */
3075 { UINT_MAX
, { 0, 0}},
3078 /* Two shader engines */
3086 { UINT_MAX
, { 0, 0}},
3089 /* Four shader engines */
3097 { UINT_MAX
, { 0, 0}},
3101 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3105 // One shader engine
3112 { UINT_MAX
, { 0, 0}},
3115 // Two shader engines
3123 { UINT_MAX
, { 0, 0}},
3126 // Four shader engines
3134 { UINT_MAX
, { 0, 0}},
3140 // One shader engine
3148 { UINT_MAX
, { 0, 0}},
3151 // Two shader engines
3160 { UINT_MAX
, { 0, 0}},
3163 // Four shader engines
3172 { UINT_MAX
, { 0, 0}},
3178 // One shader engine
3186 { UINT_MAX
, { 0, 0}},
3189 // Two shader engines
3198 { UINT_MAX
, { 0, 0}},
3201 // Four shader engines
3209 { UINT_MAX
, { 0, 0}},
3214 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3215 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3216 VkExtent2D extent
= {512, 512};
3218 unsigned log_num_rb_per_se
=
3219 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3220 pipeline
->device
->physical_device
->rad_info
.max_se
);
3221 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3223 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3224 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3225 unsigned effective_samples
= total_samples
;
3226 unsigned color_bytes_per_pixel
= 0;
3228 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3230 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3231 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3234 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3237 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3238 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3241 /* MSAA images typically don't use all samples all the time. */
3242 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3243 effective_samples
= 2;
3244 color_bytes_per_pixel
*= effective_samples
;
3247 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3248 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3251 extent
= color_entry
->extent
;
3253 if (subpass
->depth_stencil_attachment
) {
3254 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3256 /* Coefficients taken from AMDVLK */
3257 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3258 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3259 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3261 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3262 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3265 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3266 extent
= ds_entry
->extent
;
3273 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3275 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3276 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3277 VkExtent2D extent
= {512, 512};
3279 const unsigned db_tag_size
= 64;
3280 const unsigned db_tag_count
= 312;
3281 const unsigned color_tag_size
= 1024;
3282 const unsigned color_tag_count
= 31;
3283 const unsigned fmask_tag_size
= 256;
3284 const unsigned fmask_tag_count
= 44;
3286 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3287 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3289 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3290 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3291 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3293 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3294 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3296 unsigned color_bytes_per_pixel
= 0;
3297 unsigned fmask_bytes_per_pixel
= 0;
3299 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3301 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3302 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3305 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3308 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3309 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3311 if (total_samples
> 1) {
3312 assert(samples_log
<= 3);
3313 const unsigned fmask_array
[] = {0, 1, 1, 4};
3314 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3318 color_bytes_per_pixel
*= total_samples
;
3320 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3322 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3323 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3324 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3326 if (fmask_bytes_per_pixel
) {
3327 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3329 const VkExtent2D fmask_extent
= (VkExtent2D
){
3330 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3331 .height
= 1ull << (color_pixel_count_log
/ 2)
3334 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3335 extent
= fmask_extent
;
3338 if (subpass
->depth_stencil_attachment
) {
3339 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3341 /* Coefficients taken from AMDVLK */
3342 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3343 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3344 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3346 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3348 const VkExtent2D db_extent
= (VkExtent2D
){
3349 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3350 .height
= 1ull << (color_pixel_count_log
/ 2)
3353 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3357 extent
.width
= MAX2(extent
.width
, 128);
3358 extent
.height
= MAX2(extent
.width
, 64);
3364 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3365 struct radv_pipeline
*pipeline
,
3366 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3368 uint32_t pa_sc_binner_cntl_0
=
3369 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3370 S_028C44_DISABLE_START_OF_PRIM(1);
3371 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3373 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3374 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3375 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3376 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3377 unsigned min_bytes_per_pixel
= 0;
3380 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3381 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3384 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3387 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3388 unsigned bytes
= vk_format_get_blocksize(format
);
3389 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3390 min_bytes_per_pixel
= bytes
;
3394 pa_sc_binner_cntl_0
=
3395 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3396 S_028C44_BIN_SIZE_X(0) |
3397 S_028C44_BIN_SIZE_Y(0) |
3398 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3399 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3400 S_028C44_DISABLE_START_OF_PRIM(1);
3403 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3404 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3408 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3409 struct radv_pipeline
*pipeline
,
3410 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3411 const struct radv_blend_state
*blend
)
3413 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3416 VkExtent2D bin_size
;
3417 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3418 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3419 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3420 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3422 unreachable("Unhandled generation for binning bin size calculation");
3424 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3425 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
3426 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
3427 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
3429 if (pipeline
->device
->physical_device
->rad_info
.has_dedicated_vram
) {
3430 context_states_per_bin
= 1;
3431 persistent_states_per_bin
= 1;
3432 fpovs_per_batch
= 63;
3434 /* The context states are affected by the scissor bug. */
3435 context_states_per_bin
= pipeline
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
? 1 : 6;
3436 /* 32 causes hangs for RAVEN. */
3437 persistent_states_per_bin
= 16;
3438 fpovs_per_batch
= 63;
3441 bool disable_start_of_prim
= true;
3442 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3444 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3446 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3447 !ps
->info
.ps
.can_discard
&&
3448 !ps
->info
.ps
.writes_memory
&&
3449 blend
->cb_target_enabled_4bit
) {
3450 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3451 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3454 const uint32_t pa_sc_binner_cntl_0
=
3455 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3456 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3457 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3458 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3459 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3460 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
3461 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
3462 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3463 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
3464 S_028C44_OPTIMAL_BIN_SELECTION(1);
3466 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3467 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3469 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3474 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3475 struct radv_pipeline
*pipeline
,
3476 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3477 const struct radv_graphics_pipeline_create_info
*extra
)
3479 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3480 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3481 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3482 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3483 struct radv_render_pass_attachment
*attachment
= NULL
;
3484 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3485 uint32_t db_render_control
= 0, db_render_override2
= 0;
3486 uint32_t db_render_override
= 0;
3488 if (subpass
->depth_stencil_attachment
)
3489 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3491 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3492 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3494 if (vkds
&& has_depth_attachment
) {
3495 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3496 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3497 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3498 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3500 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3501 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3504 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3505 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3506 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3507 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3508 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3509 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3511 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3512 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3513 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3514 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3517 if (attachment
&& extra
) {
3518 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3519 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3521 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3522 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3523 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3524 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3525 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3528 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3529 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3531 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3532 ps
->info
.ps
.writes_z
) {
3533 /* From VK_EXT_depth_range_unrestricted spec:
3535 * "The behavior described in Primitive Clipping still applies.
3536 * If depth clamping is disabled the depth values are still
3537 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3538 * depth clamping is enabled the above equation is ignored and
3539 * the depth values are instead clamped to the VkViewport
3540 * minDepth and maxDepth values, which in the case of this
3541 * extension can be outside of the 0.0 to 1.0 range."
3543 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3546 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3547 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3549 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3550 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3551 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3555 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3556 struct radv_pipeline
*pipeline
,
3557 const struct radv_blend_state
*blend
)
3559 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3560 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3562 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3563 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3565 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3567 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3568 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3571 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3573 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3574 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3576 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3577 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3580 static const VkConservativeRasterizationModeEXT
3581 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3583 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3584 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3586 if (!conservative_raster
)
3587 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3588 return conservative_raster
->conservativeRasterizationMode
;
3592 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3593 struct radv_pipeline
*pipeline
,
3594 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3596 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3597 const VkConservativeRasterizationModeEXT mode
=
3598 radv_get_conservative_raster_mode(vkraster
);
3599 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3600 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3602 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3603 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3604 if (depth_clip_state
) {
3605 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3608 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3609 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3610 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3611 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3612 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3613 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3615 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3616 S_0286D4_FLAT_SHADE_ENA(1) |
3617 S_0286D4_PNT_SPRITE_ENA(1) |
3618 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3619 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3620 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3621 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3622 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3624 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3625 S_028BE4_PIX_CENTER(1) | // TODO verify
3626 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3627 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3629 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3630 S_028814_FACE(vkraster
->frontFace
) |
3631 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3632 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3633 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3634 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3635 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3636 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3637 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3638 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3640 /* Conservative rasterization. */
3641 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3642 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3644 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3645 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3646 S_028804_OVERRASTERIZATION_AMOUNT(4);
3648 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3649 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3650 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3652 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3653 pa_sc_conservative_rast
|=
3654 S_028C4C_OVER_RAST_ENABLE(1) |
3655 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3656 S_028C4C_UNDER_RAST_ENABLE(0) |
3657 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3658 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3660 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3661 pa_sc_conservative_rast
|=
3662 S_028C4C_OVER_RAST_ENABLE(0) |
3663 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3664 S_028C4C_UNDER_RAST_ENABLE(1) |
3665 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3666 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3670 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3671 pa_sc_conservative_rast
);
3676 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3677 struct radv_pipeline
*pipeline
)
3679 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3681 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3682 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3683 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3685 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3686 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3687 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3688 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3689 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3691 /* The exclusion bits can be set to improve rasterization efficiency
3692 * if no sample lies on the pixel boundary (-8 sample offset). It's
3693 * currently always TRUE because the driver doesn't support 16 samples.
3695 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3696 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3697 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3698 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3700 /* GFX9: Flush DFSM when the AA mode changes. */
3701 if (pipeline
->device
->dfsm_allowed
) {
3702 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3703 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3708 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3709 struct radv_pipeline
*pipeline
)
3711 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3712 const struct radv_shader_variant
*vs
=
3713 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3714 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3715 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3716 unsigned vgt_primitiveid_en
= 0;
3717 uint32_t vgt_gs_mode
= 0;
3719 if (radv_pipeline_has_ngg(pipeline
))
3722 if (radv_pipeline_has_gs(pipeline
)) {
3723 const struct radv_shader_variant
*gs
=
3724 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3726 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3727 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3728 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3729 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3730 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3733 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3734 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3738 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3739 struct radeon_cmdbuf
*cs
,
3740 struct radv_pipeline
*pipeline
,
3741 struct radv_shader_variant
*shader
)
3743 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3745 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3746 radeon_emit(cs
, va
>> 8);
3747 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3748 radeon_emit(cs
, shader
->config
.rsrc1
);
3749 radeon_emit(cs
, shader
->config
.rsrc2
);
3751 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3752 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3753 clip_dist_mask
= outinfo
->clip_dist_mask
;
3754 cull_dist_mask
= outinfo
->cull_dist_mask
;
3755 total_mask
= clip_dist_mask
| cull_dist_mask
;
3756 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3757 outinfo
->writes_layer
||
3758 outinfo
->writes_viewport_index
;
3759 unsigned spi_vs_out_config
, nparams
;
3761 /* VS is required to export at least one param. */
3762 nparams
= MAX2(outinfo
->param_exports
, 1);
3763 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3765 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3766 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3769 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3771 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3772 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3773 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3774 V_02870C_SPI_SHADER_4COMP
:
3775 V_02870C_SPI_SHADER_NONE
) |
3776 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3777 V_02870C_SPI_SHADER_4COMP
:
3778 V_02870C_SPI_SHADER_NONE
) |
3779 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3780 V_02870C_SPI_SHADER_4COMP
:
3781 V_02870C_SPI_SHADER_NONE
));
3783 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3784 S_028818_VTX_W0_FMT(1) |
3785 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3786 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3787 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3789 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3790 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3791 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3792 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3793 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3794 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3795 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3796 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3797 cull_dist_mask
<< 8 |
3800 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3801 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3802 outinfo
->writes_viewport_index
);
3806 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3807 struct radv_pipeline
*pipeline
,
3808 struct radv_shader_variant
*shader
)
3810 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3812 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3813 radeon_emit(cs
, va
>> 8);
3814 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3815 radeon_emit(cs
, shader
->config
.rsrc1
);
3816 radeon_emit(cs
, shader
->config
.rsrc2
);
3820 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3821 struct radv_pipeline
*pipeline
,
3822 struct radv_shader_variant
*shader
,
3823 const struct radv_tessellation_state
*tess
)
3825 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3826 uint32_t rsrc2
= shader
->config
.rsrc2
;
3828 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3829 radeon_emit(cs
, va
>> 8);
3830 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3832 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3833 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3834 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3835 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3837 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3838 radeon_emit(cs
, shader
->config
.rsrc1
);
3839 radeon_emit(cs
, rsrc2
);
3843 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3844 struct radeon_cmdbuf
*cs
,
3845 struct radv_pipeline
*pipeline
,
3846 struct radv_shader_variant
*shader
)
3848 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3849 gl_shader_stage es_type
=
3850 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3851 struct radv_shader_variant
*es
=
3852 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3853 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3855 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3856 radeon_emit(cs
, va
>> 8);
3857 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3858 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3859 radeon_emit(cs
, shader
->config
.rsrc1
);
3860 radeon_emit(cs
, shader
->config
.rsrc2
);
3862 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3863 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3864 clip_dist_mask
= outinfo
->clip_dist_mask
;
3865 cull_dist_mask
= outinfo
->cull_dist_mask
;
3866 total_mask
= clip_dist_mask
| cull_dist_mask
;
3867 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3868 outinfo
->writes_layer
||
3869 outinfo
->writes_viewport_index
;
3870 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3871 (es
&& es
->info
.uses_prim_id
);
3872 bool break_wave_at_eoi
= false;
3876 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3877 struct radv_shader_variant
*gs
=
3878 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3880 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3881 break_wave_at_eoi
= true;
3884 nparams
= MAX2(outinfo
->param_exports
, 1);
3885 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3886 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3887 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3889 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3890 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3891 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3892 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3893 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3894 V_02870C_SPI_SHADER_4COMP
:
3895 V_02870C_SPI_SHADER_NONE
) |
3896 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3897 V_02870C_SPI_SHADER_4COMP
:
3898 V_02870C_SPI_SHADER_NONE
) |
3899 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3900 V_02870C_SPI_SHADER_4COMP
:
3901 V_02870C_SPI_SHADER_NONE
));
3903 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3904 S_028818_VTX_W0_FMT(1) |
3905 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3906 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3907 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3908 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3909 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3910 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3911 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3912 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3913 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3914 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3915 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3916 cull_dist_mask
<< 8 |
3919 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3920 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3921 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
));
3923 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3924 ngg_state
->vgt_esgs_ring_itemsize
);
3926 /* NGG specific registers. */
3927 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3928 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3930 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3931 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3932 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3933 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3934 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3935 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3936 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3937 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3938 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3939 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3940 S_028B90_CNT(gs_num_invocations
) |
3941 S_028B90_ENABLE(gs_num_invocations
> 1) |
3942 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3944 /* User edge flags are set by the pos exports. If user edge flags are
3945 * not used, we must use hw-generated edge flags and pass them via
3946 * the prim export to prevent drawing lines on internal edges of
3947 * decomposed primitives (such as quads) with polygon mode = lines.
3949 * TODO: We should combine hw-generated edge flags with user edge
3950 * flags in the shader.
3952 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3953 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3954 !radv_pipeline_has_gs(pipeline
)));
3956 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3957 S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
) |
3958 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
3960 /* Bug workaround for a possible hang with non-tessellation cases.
3961 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3963 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3965 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3966 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3967 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3968 !radv_pipeline_has_tess(pipeline
) &&
3969 ngg_state
->hw_max_esverts
!= 256) {
3970 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
3972 if (ngg_state
->hw_max_esverts
> 5) {
3973 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
3977 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
3981 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3982 struct radv_pipeline
*pipeline
,
3983 struct radv_shader_variant
*shader
,
3984 const struct radv_tessellation_state
*tess
)
3986 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3988 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3989 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
3991 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3992 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
3994 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
3997 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3998 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3999 radeon_emit(cs
, va
>> 8);
4000 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4002 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4003 radeon_emit(cs
, va
>> 8);
4004 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4007 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4008 radeon_emit(cs
, shader
->config
.rsrc1
);
4009 radeon_emit(cs
, hs_rsrc2
);
4011 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4012 radeon_emit(cs
, va
>> 8);
4013 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4014 radeon_emit(cs
, shader
->config
.rsrc1
);
4015 radeon_emit(cs
, shader
->config
.rsrc2
);
4020 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4021 struct radeon_cmdbuf
*cs
,
4022 struct radv_pipeline
*pipeline
,
4023 const struct radv_tessellation_state
*tess
)
4025 struct radv_shader_variant
*vs
;
4027 /* Skip shaders merged into HS/GS */
4028 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4032 if (vs
->info
.vs
.as_ls
)
4033 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4034 else if (vs
->info
.vs
.as_es
)
4035 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4036 else if (vs
->info
.is_ngg
)
4037 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4039 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4043 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4044 struct radeon_cmdbuf
*cs
,
4045 struct radv_pipeline
*pipeline
,
4046 const struct radv_tessellation_state
*tess
)
4048 if (!radv_pipeline_has_tess(pipeline
))
4051 struct radv_shader_variant
*tes
, *tcs
;
4053 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4054 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4057 if (tes
->info
.is_ngg
) {
4058 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4059 } else if (tes
->info
.tes
.as_es
)
4060 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4062 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4065 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4067 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4070 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4071 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4072 tess
->ls_hs_config
);
4074 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4075 tess
->ls_hs_config
);
4077 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4078 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4079 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4080 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4081 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4082 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4087 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4088 struct radeon_cmdbuf
*cs
,
4089 struct radv_pipeline
*pipeline
,
4090 struct radv_shader_variant
*gs
)
4092 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4093 unsigned gs_max_out_vertices
;
4094 uint8_t *num_components
;
4099 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4100 max_stream
= gs
->info
.gs
.max_stream
;
4101 num_components
= gs
->info
.gs
.num_stream_output_components
;
4103 offset
= num_components
[0] * gs_max_out_vertices
;
4105 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4106 radeon_emit(ctx_cs
, offset
);
4107 if (max_stream
>= 1)
4108 offset
+= num_components
[1] * gs_max_out_vertices
;
4109 radeon_emit(ctx_cs
, offset
);
4110 if (max_stream
>= 2)
4111 offset
+= num_components
[2] * gs_max_out_vertices
;
4112 radeon_emit(ctx_cs
, offset
);
4113 if (max_stream
>= 3)
4114 offset
+= num_components
[3] * gs_max_out_vertices
;
4115 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4117 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4118 radeon_emit(ctx_cs
, num_components
[0]);
4119 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4120 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4121 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4123 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4124 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4125 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4126 S_028B90_ENABLE(gs_num_invocations
> 0));
4128 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4129 gs_state
->vgt_esgs_ring_itemsize
);
4131 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4133 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4134 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4135 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4136 radeon_emit(cs
, va
>> 8);
4137 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4139 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4140 radeon_emit(cs
, va
>> 8);
4141 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4144 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4145 radeon_emit(cs
, gs
->config
.rsrc1
);
4146 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4148 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4149 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4151 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4152 radeon_emit(cs
, va
>> 8);
4153 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4154 radeon_emit(cs
, gs
->config
.rsrc1
);
4155 radeon_emit(cs
, gs
->config
.rsrc2
);
4158 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4162 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4163 struct radeon_cmdbuf
*cs
,
4164 struct radv_pipeline
*pipeline
)
4166 struct radv_shader_variant
*gs
;
4168 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4172 if (gs
->info
.is_ngg
)
4173 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4175 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4177 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4178 gs
->info
.gs
.vertices_out
);
4181 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
4183 uint32_t ps_input_cntl
;
4184 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4185 ps_input_cntl
= S_028644_OFFSET(offset
);
4187 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4189 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4190 S_028644_ATTR0_VALID(1);
4193 /* The input is a DEFAULT_VAL constant. */
4194 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4195 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4196 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4197 ps_input_cntl
= S_028644_OFFSET(0x20) |
4198 S_028644_DEFAULT_VAL(offset
);
4200 return ps_input_cntl
;
4204 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4205 struct radv_pipeline
*pipeline
)
4207 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4208 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4209 uint32_t ps_input_cntl
[32];
4211 unsigned ps_offset
= 0;
4213 if (ps
->info
.ps
.prim_id_input
) {
4214 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4215 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4216 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4221 if (ps
->info
.ps
.layer_input
||
4222 ps
->info
.needs_multiview_view_index
) {
4223 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4224 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4225 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4227 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
4231 if (ps
->info
.ps
.has_pcoord
) {
4233 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4234 ps_input_cntl
[ps_offset
] = val
;
4238 if (ps
->info
.ps
.num_input_clips_culls
) {
4241 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4242 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4243 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4247 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4248 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4249 ps
->info
.ps
.num_input_clips_culls
> 4) {
4250 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4255 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4259 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4262 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4263 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4264 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4269 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4270 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4272 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
4277 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4278 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4279 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4285 radv_compute_db_shader_control(const struct radv_device
*device
,
4286 const struct radv_pipeline
*pipeline
,
4287 const struct radv_shader_variant
*ps
)
4290 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4291 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4293 z_order
= V_02880C_LATE_Z
;
4295 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4296 !device
->physical_device
->rad_info
.rbplus_allowed
;
4298 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4299 * but this appears to break Project Cars (DXVK). See
4300 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4302 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4304 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4305 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4306 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4307 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4308 S_02880C_Z_ORDER(z_order
) |
4309 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4310 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4311 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4312 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4313 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4317 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4318 struct radeon_cmdbuf
*cs
,
4319 struct radv_pipeline
*pipeline
)
4321 struct radv_shader_variant
*ps
;
4323 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4325 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4326 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4328 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4329 radeon_emit(cs
, va
>> 8);
4330 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4331 radeon_emit(cs
, ps
->config
.rsrc1
);
4332 radeon_emit(cs
, ps
->config
.rsrc2
);
4334 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4335 radv_compute_db_shader_control(pipeline
->device
,
4338 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4339 ps
->config
.spi_ps_input_ena
);
4341 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4342 ps
->config
.spi_ps_input_addr
);
4344 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4345 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4346 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4348 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4350 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4351 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4352 ps
->info
.ps
.writes_stencil
,
4353 ps
->info
.ps
.writes_sample_mask
));
4355 if (pipeline
->device
->dfsm_allowed
) {
4356 /* optimise this? */
4357 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4358 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4363 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4364 struct radv_pipeline
*pipeline
)
4366 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4367 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4370 unsigned vtx_reuse_depth
= 30;
4371 if (radv_pipeline_has_tess(pipeline
) &&
4372 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4373 vtx_reuse_depth
= 14;
4375 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4376 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4380 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4382 uint32_t stages
= 0;
4383 if (radv_pipeline_has_tess(pipeline
)) {
4384 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4385 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4387 if (radv_pipeline_has_gs(pipeline
))
4388 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4390 else if (radv_pipeline_has_ngg(pipeline
))
4391 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4393 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4394 } else if (radv_pipeline_has_gs(pipeline
)) {
4395 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4397 } else if (radv_pipeline_has_ngg(pipeline
)) {
4398 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4401 if (radv_pipeline_has_ngg(pipeline
)) {
4402 stages
|= S_028B54_PRIMGEN_EN(1);
4403 if (pipeline
->streamout_shader
)
4404 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4405 } else if (radv_pipeline_has_gs(pipeline
)) {
4406 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4409 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4410 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4412 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4413 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4415 if (radv_pipeline_has_tess(pipeline
))
4416 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4418 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4419 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4420 if (pipeline
->gs_copy_shader
)
4421 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4422 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4423 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4424 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4425 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4427 if (radv_pipeline_has_ngg(pipeline
))
4430 /* legacy GS only supports Wave64 */
4431 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4432 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4433 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4440 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4442 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4443 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4445 if (!discard_rectangle_info
)
4450 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4451 /* Interpret i as a bitmask, and then set the bit in the mask if
4452 * that combination of rectangles in which the pixel is contained
4453 * should pass the cliprect test. */
4454 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4456 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4460 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4471 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4472 struct radv_pipeline
*pipeline
,
4473 const struct radv_tessellation_state
*tess
)
4475 bool break_wave_at_eoi
= false;
4476 unsigned primgroup_size
;
4477 unsigned vertgroup_size
;
4479 if (radv_pipeline_has_tess(pipeline
)) {
4480 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4482 } else if (radv_pipeline_has_gs(pipeline
)) {
4483 const struct gfx9_gs_info
*gs_state
=
4484 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4485 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4486 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4487 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4489 primgroup_size
= 128; /* recommended without a GS and tess */
4493 if (radv_pipeline_has_tess(pipeline
)) {
4494 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4495 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4496 break_wave_at_eoi
= true;
4499 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4500 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4501 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4502 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4503 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4507 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4508 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4509 const struct radv_graphics_pipeline_create_info
*extra
,
4510 const struct radv_blend_state
*blend
,
4511 const struct radv_tessellation_state
*tess
,
4512 unsigned prim
, unsigned gs_out
)
4514 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4515 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4518 ctx_cs
->max_dw
= 256;
4519 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4520 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4522 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4523 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4524 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4525 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4526 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4527 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4528 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4529 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4530 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4531 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4532 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4533 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4535 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4536 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4538 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4540 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4541 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4542 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4544 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4546 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4548 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4550 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4552 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4553 assert(cs
->cdw
<= cs
->max_dw
);
4556 static struct radv_ia_multi_vgt_param_helpers
4557 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4558 const struct radv_tessellation_state
*tess
,
4561 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4562 const struct radv_device
*device
= pipeline
->device
;
4564 if (radv_pipeline_has_tess(pipeline
))
4565 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4566 else if (radv_pipeline_has_gs(pipeline
))
4567 ia_multi_vgt_param
.primgroup_size
= 64;
4569 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4571 /* GS requirement. */
4572 ia_multi_vgt_param
.partial_es_wave
= false;
4573 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4574 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4575 ia_multi_vgt_param
.partial_es_wave
= true;
4577 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4578 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4579 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4580 * 4 shader engines. Set 1 to pass the assertion below.
4581 * The other cases are hardware requirements. */
4582 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4583 prim
== V_008958_DI_PT_POLYGON
||
4584 prim
== V_008958_DI_PT_LINELOOP
||
4585 prim
== V_008958_DI_PT_TRIFAN
||
4586 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4587 (pipeline
->graphics
.prim_restart_enable
&&
4588 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4589 (prim
!= V_008958_DI_PT_POINTLIST
&&
4590 prim
!= V_008958_DI_PT_LINESTRIP
))))
4591 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4594 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4595 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4596 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4597 if (radv_pipeline_has_gs(pipeline
) &&
4598 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4599 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4600 if (radv_pipeline_has_tess(pipeline
)) {
4601 /* SWITCH_ON_EOI must be set if PrimID is used. */
4602 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4603 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4604 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4607 ia_multi_vgt_param
.partial_vs_wave
= false;
4608 if (radv_pipeline_has_tess(pipeline
)) {
4609 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4610 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4611 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4612 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4613 radv_pipeline_has_gs(pipeline
))
4614 ia_multi_vgt_param
.partial_vs_wave
= true;
4615 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4616 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4617 if (radv_pipeline_has_gs(pipeline
)) {
4618 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4619 ia_multi_vgt_param
.partial_es_wave
= true;
4621 ia_multi_vgt_param
.partial_vs_wave
= true;
4626 /* Workaround for a VGT hang when strip primitive types are used with
4627 * primitive restart.
4629 if (pipeline
->graphics
.prim_restart_enable
&&
4630 (prim
== V_008958_DI_PT_LINESTRIP
||
4631 prim
== V_008958_DI_PT_TRISTRIP
||
4632 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4633 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4634 ia_multi_vgt_param
.partial_vs_wave
= true;
4637 if (radv_pipeline_has_gs(pipeline
)) {
4638 /* On these chips there is the possibility of a hang if the
4639 * pipeline uses a GS and partial_vs_wave is not set.
4641 * This mostly does not hit 4-SE chips, as those typically set
4642 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4643 * with GS due to another workaround.
4645 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4647 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4648 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4649 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4650 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4651 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4652 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4653 ia_multi_vgt_param
.partial_vs_wave
= true;
4657 ia_multi_vgt_param
.base
=
4658 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4659 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4660 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4661 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4662 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4664 return ia_multi_vgt_param
;
4669 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4670 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4672 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4673 pCreateInfo
->pVertexInputState
;
4674 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4676 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4677 const VkVertexInputAttributeDescription
*desc
=
4678 &vi_info
->pVertexAttributeDescriptions
[i
];
4679 unsigned loc
= desc
->location
;
4680 const struct vk_format_description
*format_desc
;
4682 format_desc
= vk_format_description(desc
->format
);
4684 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4687 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4688 const VkVertexInputBindingDescription
*desc
=
4689 &vi_info
->pVertexBindingDescriptions
[i
];
4691 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4692 pipeline
->num_vertex_bindings
=
4693 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4697 static struct radv_shader_variant
*
4698 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4702 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4703 struct radv_shader_variant
*shader
=
4704 radv_get_shader(pipeline
, i
);
4706 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4714 radv_secure_compile(struct radv_pipeline
*pipeline
,
4715 struct radv_device
*device
,
4716 const struct radv_pipeline_key
*key
,
4717 const VkPipelineShaderStageCreateInfo
**pStages
,
4718 const VkPipelineCreateFlags flags
,
4719 unsigned num_stages
)
4721 uint8_t allowed_pipeline_hashes
[2][20];
4722 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4723 pipeline
->layout
, key
, get_hash_flags(device
));
4725 /* Generate the GC copy hash */
4726 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4727 allowed_pipeline_hashes
[1][0] ^= 1;
4729 uint8_t allowed_hashes
[2][20];
4730 for (unsigned i
= 0; i
< 2; ++i
) {
4731 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4732 allowed_pipeline_hashes
[i
], 20,
4736 /* Do an early exit if all cache entries are already there. */
4737 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4738 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4739 void *copy_entry
= NULL
;
4740 if (may_need_copy_shader
)
4741 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4743 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4747 if(has_all_cache_entries
)
4750 unsigned process
= 0;
4751 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4753 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4754 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4755 device
->sc_state
->secure_compile_thread_counter
++;
4756 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4757 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4758 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4763 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4766 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4769 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4770 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4772 /* Fork a copy of the slim untainted secure compile process */
4773 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4774 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4776 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4777 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4778 return VK_ERROR_DEVICE_LOST
;
4780 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4781 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4783 /* Write pipeline / shader module out to secure process via pipe */
4784 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4785 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4787 /* Write pipeline layout out to secure process */
4788 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4789 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4790 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4791 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4792 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4793 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4796 /* Write pipeline key out to secure process */
4797 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4799 /* Write pipeline create flags out to secure process */
4800 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4802 /* Write stage and shader information out to secure process */
4803 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4804 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4808 /* Write stage out to secure process */
4809 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4810 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4812 /* Write entry point name out to secure process */
4813 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4814 write(fd_secure_input
, &name_size
, sizeof(size_t));
4815 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4817 /* Write shader module out to secure process */
4818 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4819 assert(!module
->nir
);
4820 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4821 write(fd_secure_input
, &module_size
, sizeof(size_t));
4822 write(fd_secure_input
, module
, module_size
);
4824 /* Write specialization info out to secure process */
4825 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4826 bool has_spec_info
= specInfo
? true : false;
4827 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4829 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4830 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4832 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4833 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4834 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4838 /* Read the data returned from the secure process */
4839 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4840 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4841 return VK_ERROR_DEVICE_LOST
;
4843 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4844 assert(device
->physical_device
->disk_cache
);
4846 uint8_t disk_sha1
[20];
4847 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4848 return VK_ERROR_DEVICE_LOST
;
4850 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4851 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4852 return VK_ERROR_DEVICE_LOST
;
4854 uint32_t entry_size
;
4855 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4856 return VK_ERROR_DEVICE_LOST
;
4858 struct cache_entry
*entry
= malloc(entry_size
);
4859 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4860 return VK_ERROR_DEVICE_LOST
;
4862 disk_cache_put(device
->physical_device
->disk_cache
,
4863 disk_sha1
, entry
, entry_size
,
4867 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4868 uint8_t disk_sha1
[20];
4869 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4870 return VK_ERROR_DEVICE_LOST
;
4872 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4873 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4874 return VK_ERROR_DEVICE_LOST
;
4877 struct cache_entry
*entry
= (struct cache_entry
*)
4878 disk_cache_get(device
->physical_device
->disk_cache
,
4881 uint8_t found
= entry
? 1 : 0;
4882 write(fd_secure_input
, &found
, sizeof(uint8_t));
4885 write(fd_secure_input
, &size
, sizeof(size_t));
4886 write(fd_secure_input
, entry
, size
);
4893 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
4894 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4896 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4897 device
->sc_state
->secure_compile_thread_counter
--;
4898 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
4899 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4905 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4906 struct radv_device
*device
,
4907 struct radv_pipeline_cache
*cache
,
4908 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4909 const struct radv_graphics_pipeline_create_info
*extra
)
4912 bool has_view_index
= false;
4914 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4915 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4916 if (subpass
->view_mask
)
4917 has_view_index
= true;
4919 pipeline
->device
= device
;
4920 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4921 assert(pipeline
->layout
);
4923 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4925 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4926 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4927 radv_init_feedback(creation_feedback
);
4929 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4931 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4932 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4933 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4934 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4935 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4936 if(creation_feedback
)
4937 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4940 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4941 if (radv_device_use_secure_compile(device
->instance
)) {
4942 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
4944 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
4947 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4948 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4950 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
4952 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4954 if (radv_pipeline_has_gs(pipeline
)) {
4955 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4956 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4957 } else if (radv_pipeline_has_tess(pipeline
)) {
4958 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4959 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4961 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4962 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4964 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4966 if (extra
&& extra
->use_rectlist
) {
4967 prim
= V_008958_DI_PT_RECTLIST
;
4968 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4969 pipeline
->graphics
.can_use_guardband
= true;
4970 if (radv_pipeline_has_ngg(pipeline
))
4971 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4973 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4974 /* prim vertex count will need TESS changes */
4975 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
4977 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
4979 /* Ensure that some export memory is always allocated, for two reasons:
4981 * 1) Correctness: The hardware ignores the EXEC mask if no export
4982 * memory is allocated, so KILL and alpha test do not work correctly
4984 * 2) Performance: Every shader needs at least a NULL export, even when
4985 * it writes no color/depth output. The NULL export instruction
4986 * stalls without this setting.
4988 * Don't add this to CB_SHADER_MASK.
4990 * GFX10 supports pixel shaders without exports by setting both the
4991 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4992 * instructions if any are present.
4994 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4995 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4996 ps
->info
.ps
.can_discard
) &&
4997 !blend
.spi_shader_col_format
) {
4998 if (!ps
->info
.ps
.writes_z
&&
4999 !ps
->info
.ps
.writes_stencil
&&
5000 !ps
->info
.ps
.writes_sample_mask
)
5001 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5004 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5005 if (pipeline
->shaders
[i
]) {
5006 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5010 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5011 struct radv_shader_variant
*gs
=
5012 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5014 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5017 struct radv_tessellation_state tess
= {0};
5018 if (radv_pipeline_has_tess(pipeline
)) {
5019 if (prim
== V_008958_DI_PT_PATCH
) {
5020 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5021 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5023 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5026 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5028 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5030 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5031 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5033 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5034 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5035 if (loc
->sgpr_idx
!= -1) {
5036 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5037 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5038 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5039 pipeline
->graphics
.vtx_emit_num
= 3;
5041 pipeline
->graphics
.vtx_emit_num
= 2;
5044 /* Find the last vertex shader stage that eventually uses streamout. */
5045 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5047 result
= radv_pipeline_scratch_init(device
, pipeline
);
5048 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5054 radv_graphics_pipeline_create(
5056 VkPipelineCache _cache
,
5057 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5058 const struct radv_graphics_pipeline_create_info
*extra
,
5059 const VkAllocationCallbacks
*pAllocator
,
5060 VkPipeline
*pPipeline
)
5062 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5063 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5064 struct radv_pipeline
*pipeline
;
5067 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5068 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5069 if (pipeline
== NULL
)
5070 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5072 result
= radv_pipeline_init(pipeline
, device
, cache
,
5073 pCreateInfo
, extra
);
5074 if (result
!= VK_SUCCESS
) {
5075 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5079 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5084 VkResult
radv_CreateGraphicsPipelines(
5086 VkPipelineCache pipelineCache
,
5088 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5089 const VkAllocationCallbacks
* pAllocator
,
5090 VkPipeline
* pPipelines
)
5092 VkResult result
= VK_SUCCESS
;
5095 for (; i
< count
; i
++) {
5097 r
= radv_graphics_pipeline_create(_device
,
5100 NULL
, pAllocator
, &pPipelines
[i
]);
5101 if (r
!= VK_SUCCESS
) {
5103 pPipelines
[i
] = VK_NULL_HANDLE
;
5112 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5114 struct radv_shader_variant
*compute_shader
;
5115 struct radv_device
*device
= pipeline
->device
;
5116 unsigned threads_per_threadgroup
;
5117 unsigned threadgroups_per_cu
= 1;
5118 unsigned waves_per_threadgroup
;
5119 unsigned max_waves_per_sh
= 0;
5122 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5123 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5125 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5126 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5128 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5129 radeon_emit(&pipeline
->cs
, va
>> 8);
5130 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5132 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5133 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5134 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5135 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5136 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5139 /* Calculate best compute resource limits. */
5140 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5141 compute_shader
->info
.cs
.block_size
[1] *
5142 compute_shader
->info
.cs
.block_size
[2];
5143 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5144 compute_shader
->info
.wave_size
);
5146 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5147 waves_per_threadgroup
== 1)
5148 threadgroups_per_cu
= 2;
5150 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5151 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5152 waves_per_threadgroup
,
5154 threadgroups_per_cu
));
5156 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5157 radeon_emit(&pipeline
->cs
,
5158 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5159 radeon_emit(&pipeline
->cs
,
5160 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5161 radeon_emit(&pipeline
->cs
,
5162 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5164 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5167 static struct radv_pipeline_key
5168 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5169 const VkComputePipelineCreateInfo
*pCreateInfo
)
5171 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5172 struct radv_pipeline_key key
;
5173 memset(&key
, 0, sizeof(key
));
5175 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5176 key
.optimisations_disabled
= 1;
5178 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5179 vk_find_struct_const(stage
->pNext
,
5180 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5182 if (subgroup_size
) {
5183 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5184 subgroup_size
->requiredSubgroupSize
== 64);
5185 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5191 static VkResult
radv_compute_pipeline_create(
5193 VkPipelineCache _cache
,
5194 const VkComputePipelineCreateInfo
* pCreateInfo
,
5195 const VkAllocationCallbacks
* pAllocator
,
5196 VkPipeline
* pPipeline
)
5198 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5199 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5200 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5201 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5202 struct radv_pipeline
*pipeline
;
5205 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5206 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5207 if (pipeline
== NULL
)
5208 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5210 pipeline
->device
= device
;
5211 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5212 assert(pipeline
->layout
);
5214 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5215 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5216 radv_init_feedback(creation_feedback
);
5218 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5219 if (creation_feedback
)
5220 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5222 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5224 struct radv_pipeline_key key
=
5225 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5227 if (radv_device_use_secure_compile(device
->instance
)) {
5228 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5229 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5233 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5236 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5237 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5238 result
= radv_pipeline_scratch_init(device
, pipeline
);
5239 if (result
!= VK_SUCCESS
) {
5240 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5244 radv_compute_generate_pm4(pipeline
);
5246 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5251 VkResult
radv_CreateComputePipelines(
5253 VkPipelineCache pipelineCache
,
5255 const VkComputePipelineCreateInfo
* pCreateInfos
,
5256 const VkAllocationCallbacks
* pAllocator
,
5257 VkPipeline
* pPipelines
)
5259 VkResult result
= VK_SUCCESS
;
5262 for (; i
< count
; i
++) {
5264 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5266 pAllocator
, &pPipelines
[i
]);
5267 if (r
!= VK_SUCCESS
) {
5269 pPipelines
[i
] = VK_NULL_HANDLE
;
5277 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5280 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5281 if (!pipeline
->shaders
[i
])
5284 if (i
== MESA_SHADER_GEOMETRY
&&
5285 !radv_pipeline_has_ngg(pipeline
)) {
5295 static struct radv_shader_variant
*
5296 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5298 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5299 if (!pipeline
->shaders
[i
])
5303 return pipeline
->shaders
[i
];
5308 if (i
== MESA_SHADER_GEOMETRY
&&
5309 !radv_pipeline_has_ngg(pipeline
)) {
5312 return pipeline
->gs_copy_shader
;
5322 /* Basically strlcpy (which does not exist on linux) specialized for
5324 static void desc_copy(char *desc
, const char *src
) {
5325 int len
= strlen(src
);
5326 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5327 memcpy(desc
, src
, len
);
5328 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5331 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5333 const VkPipelineInfoKHR
* pPipelineInfo
,
5334 uint32_t* pExecutableCount
,
5335 VkPipelineExecutablePropertiesKHR
* pProperties
)
5337 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5338 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5341 *pExecutableCount
= total_count
;
5345 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5346 for (unsigned i
= 0, executable_idx
= 0;
5347 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5348 if (!pipeline
->shaders
[i
])
5350 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5351 const char *name
= NULL
;
5352 const char *description
= NULL
;
5354 case MESA_SHADER_VERTEX
:
5355 name
= "Vertex Shader";
5356 description
= "Vulkan Vertex Shader";
5358 case MESA_SHADER_TESS_CTRL
:
5359 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5360 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5361 name
= "Vertex + Tessellation Control Shaders";
5362 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5364 name
= "Tessellation Control Shader";
5365 description
= "Vulkan Tessellation Control Shader";
5368 case MESA_SHADER_TESS_EVAL
:
5369 name
= "Tessellation Evaluation Shader";
5370 description
= "Vulkan Tessellation Evaluation Shader";
5372 case MESA_SHADER_GEOMETRY
:
5373 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5374 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5375 name
= "Tessellation Evaluation + Geometry Shaders";
5376 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5377 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5378 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5379 name
= "Vertex + Geometry Shader";
5380 description
= "Combined Vulkan Vertex and Geometry Shaders";
5382 name
= "Geometry Shader";
5383 description
= "Vulkan Geometry Shader";
5386 case MESA_SHADER_FRAGMENT
:
5387 name
= "Fragment Shader";
5388 description
= "Vulkan Fragment Shader";
5390 case MESA_SHADER_COMPUTE
:
5391 name
= "Compute Shader";
5392 description
= "Vulkan Compute Shader";
5396 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5397 desc_copy(pProperties
[executable_idx
].name
, name
);
5398 desc_copy(pProperties
[executable_idx
].description
, description
);
5401 if (i
== MESA_SHADER_GEOMETRY
&&
5402 !radv_pipeline_has_ngg(pipeline
)) {
5403 assert(pipeline
->gs_copy_shader
);
5404 if (executable_idx
>= count
)
5407 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5408 pProperties
[executable_idx
].subgroupSize
= 64;
5409 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5410 desc_copy(pProperties
[executable_idx
].description
,
5411 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5417 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5418 *pExecutableCount
= count
;
5422 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5424 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5425 uint32_t* pStatisticCount
,
5426 VkPipelineExecutableStatisticKHR
* pStatistics
)
5428 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5429 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5430 gl_shader_stage stage
;
5431 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5433 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5434 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5435 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5437 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5438 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5439 VkResult result
= VK_SUCCESS
;
5442 desc_copy(s
->name
, "SGPRs");
5443 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5444 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5445 s
->value
.u64
= shader
->config
.num_sgprs
;
5450 desc_copy(s
->name
, "VGPRs");
5451 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5452 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5453 s
->value
.u64
= shader
->config
.num_vgprs
;
5458 desc_copy(s
->name
, "Spilled SGPRs");
5459 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5460 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5461 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5466 desc_copy(s
->name
, "Spilled VGPRs");
5467 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5468 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5469 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5474 desc_copy(s
->name
, "PrivMem VGPRs");
5475 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5476 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5477 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5482 desc_copy(s
->name
, "Code size");
5483 desc_copy(s
->description
, "Code size in bytes");
5484 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5485 s
->value
.u64
= shader
->exec_size
;
5490 desc_copy(s
->name
, "LDS size");
5491 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5492 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5493 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5498 desc_copy(s
->name
, "Scratch size");
5499 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5500 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5501 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5506 desc_copy(s
->name
, "Subgroups per SIMD");
5507 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5508 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5509 s
->value
.u64
= max_waves
;
5514 *pStatisticCount
= s
- pStatistics
;
5516 *pStatisticCount
= end
- pStatistics
;
5517 result
= VK_INCOMPLETE
;
5519 *pStatisticCount
= s
- pStatistics
;
5525 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5527 size_t total_size
= strlen(src
) + 1;
5530 *data_size
= total_size
;
5534 size_t size
= MIN2(total_size
, *data_size
);
5536 memcpy(data
, src
, size
);
5538 *((char*)data
+ size
- 1) = 0;
5539 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5542 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5544 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5545 uint32_t* pInternalRepresentationCount
,
5546 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5548 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5549 gl_shader_stage stage
;
5550 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5552 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5553 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5554 VkResult result
= VK_SUCCESS
;
5558 desc_copy(p
->name
, "NIR Shader(s)");
5559 desc_copy(p
->description
, "The optimized NIR shader(s)");
5560 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5561 result
= VK_INCOMPLETE
;
5568 if (shader
->aco_used
) {
5569 desc_copy(p
->name
, "ACO IR");
5570 desc_copy(p
->description
, "The ACO IR after some optimizations");
5572 desc_copy(p
->name
, "LLVM IR");
5573 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5575 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5576 result
= VK_INCOMPLETE
;
5583 desc_copy(p
->name
, "Assembly");
5584 desc_copy(p
->description
, "Final Assembly");
5585 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5586 result
= VK_INCOMPLETE
;
5590 if (!pInternalRepresentations
)
5591 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5593 result
= VK_INCOMPLETE
;
5594 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5596 *pInternalRepresentationCount
= p
- pInternalRepresentations
;