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radv: Make tess winding order a bit more intuitive.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "vk_util.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40
41 #include "sid.h"
42 #include "gfx9d.h"
43 #include "r600d_common.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 static void
52 radv_pipeline_destroy(struct radv_device *device,
53 struct radv_pipeline *pipeline,
54 const VkAllocationCallbacks* allocator)
55 {
56 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
57 if (pipeline->shaders[i])
58 radv_shader_variant_destroy(device, pipeline->shaders[i]);
59
60 if (pipeline->gs_copy_shader)
61 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
62
63 vk_free2(&device->alloc, allocator, pipeline);
64 }
65
66 void radv_DestroyPipeline(
67 VkDevice _device,
68 VkPipeline _pipeline,
69 const VkAllocationCallbacks* pAllocator)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
73
74 if (!_pipeline)
75 return;
76
77 radv_pipeline_destroy(device, pipeline, pAllocator);
78 }
79
80 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
81 {
82 int i;
83
84 for (i = 0; i < MESA_SHADER_STAGES; i++) {
85 if (!pipeline->shaders[i])
86 continue;
87
88 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
89 }
90 }
91
92 static struct radv_shader_variant *
93 radv_pipeline_compile(struct radv_pipeline *pipeline,
94 struct radv_pipeline_cache *cache,
95 struct radv_shader_module *module,
96 const char *entrypoint,
97 gl_shader_stage stage,
98 const VkSpecializationInfo *spec_info,
99 struct radv_pipeline_layout *layout,
100 const struct ac_shader_variant_key *key)
101 {
102 unsigned char sha1[20];
103 unsigned char gs_copy_sha1[20];
104 struct radv_shader_variant *variant;
105 nir_shader *nir;
106 void *code = NULL;
107 unsigned code_size = 0;
108
109 if (module->nir)
110 _mesa_sha1_compute(module->nir->info.name,
111 strlen(module->nir->info.name),
112 module->sha1);
113
114 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
115 if (stage == MESA_SHADER_GEOMETRY)
116 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
117 layout, key, 1);
118
119 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
120 cache,
121 sha1);
122
123 if (stage == MESA_SHADER_GEOMETRY) {
124 pipeline->gs_copy_shader =
125 radv_create_shader_variant_from_pipeline_cache(
126 pipeline->device,
127 cache,
128 gs_copy_sha1);
129 }
130
131 if (variant &&
132 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
133 return variant;
134
135 nir = radv_shader_compile_to_nir(pipeline->device,
136 module, entrypoint, stage,
137 spec_info);
138 if (nir == NULL)
139 return NULL;
140
141 if (!variant) {
142 variant = radv_shader_variant_create(pipeline->device, module, nir,
143 layout, key, &code,
144 &code_size);
145 }
146
147 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
148 void *gs_copy_code = NULL;
149 unsigned gs_copy_code_size = 0;
150 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
151 pipeline->device, nir, &gs_copy_code,
152 &gs_copy_code_size, key->has_multiview_view_index);
153
154 if (pipeline->gs_copy_shader) {
155 pipeline->gs_copy_shader =
156 radv_pipeline_cache_insert_shader(pipeline->device,
157 cache,
158 gs_copy_sha1,
159 pipeline->gs_copy_shader,
160 gs_copy_code,
161 gs_copy_code_size);
162 }
163
164 free(gs_copy_code);
165 }
166 if (!module->nir && !pipeline->device->trace_bo)
167 ralloc_free(nir);
168
169 if (variant)
170 variant = radv_pipeline_cache_insert_shader(pipeline->device,
171 cache, sha1,
172 variant, code,
173 code_size);
174
175 if (code)
176 free(code);
177 return variant;
178 }
179
180 static struct ac_shader_variant_key
181 radv_compute_tes_key(bool as_es, bool export_prim_id)
182 {
183 struct ac_shader_variant_key key;
184 memset(&key, 0, sizeof(key));
185 key.tes.as_es = as_es;
186 /* export prim id only happens when no geom shader */
187 if (!as_es)
188 key.tes.export_prim_id = export_prim_id;
189 return key;
190 }
191
192 static struct ac_shader_variant_key
193 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
194 {
195 struct ac_shader_variant_key key;
196 memset(&key, 0, sizeof(key));
197 key.tcs.primitive_mode = primitive_mode;
198 key.tcs.input_vertices = input_vertices;
199 return key;
200 }
201
202 static void
203 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
204 struct radv_pipeline_cache *cache,
205 struct radv_shader_module *tcs_module,
206 struct radv_shader_module *tes_module,
207 const char *tcs_entrypoint,
208 const char *tes_entrypoint,
209 const VkSpecializationInfo *tcs_spec_info,
210 const VkSpecializationInfo *tes_spec_info,
211 struct radv_pipeline_layout *layout,
212 unsigned input_vertices,
213 bool has_view_index)
214 {
215 unsigned char tcs_sha1[20], tes_sha1[20];
216 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
217 nir_shader *tes_nir, *tcs_nir;
218 void *tes_code = NULL, *tcs_code = NULL;
219 unsigned tes_code_size = 0, tcs_code_size = 0;
220 struct ac_shader_variant_key tes_key;
221 struct ac_shader_variant_key tcs_key;
222
223 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
224 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
225 tes_key.has_multiview_view_index = has_view_index;
226 if (tes_module->nir)
227 _mesa_sha1_compute(tes_module->nir->info.name,
228 strlen(tes_module->nir->info.name),
229 tes_module->sha1);
230 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
231
232 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
233 cache,
234 tes_sha1);
235
236 if (tes_variant) {
237 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
238
239 if (tcs_module->nir)
240 _mesa_sha1_compute(tcs_module->nir->info.name,
241 strlen(tcs_module->nir->info.name),
242 tcs_module->sha1);
243
244 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
245
246 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
247 cache,
248 tcs_sha1);
249 }
250
251 if (tcs_variant && tes_variant) {
252 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
253 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
254 return;
255 }
256
257 tes_nir = radv_shader_compile_to_nir(pipeline->device,
258 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
259 tes_spec_info);
260 if (tes_nir == NULL)
261 return;
262
263 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
264 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
265 tcs_spec_info);
266 if (tcs_nir == NULL)
267 return;
268
269 nir_lower_tes_patch_vertices(tes_nir,
270 tcs_nir->info.tess.tcs_vertices_out);
271
272 tes_variant = radv_shader_variant_create(pipeline->device, tes_module, tes_nir,
273 layout, &tes_key, &tes_code,
274 &tes_code_size);
275
276 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
277 if (tcs_module->nir)
278 _mesa_sha1_compute(tcs_module->nir->info.name,
279 strlen(tcs_module->nir->info.name),
280 tcs_module->sha1);
281
282 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
283
284 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_module, tcs_nir,
285 layout, &tcs_key, &tcs_code,
286 &tcs_code_size);
287
288 if (!tes_module->nir && !pipeline->device->trace_bo)
289 ralloc_free(tes_nir);
290
291 if (!tcs_module->nir && !pipeline->device->trace_bo)
292 ralloc_free(tcs_nir);
293
294 if (tes_variant)
295 tes_variant = radv_pipeline_cache_insert_shader(pipeline->device, cache, tes_sha1, tes_variant,
296 tes_code, tes_code_size);
297
298 if (tcs_variant)
299 tcs_variant = radv_pipeline_cache_insert_shader(pipeline->device, cache, tcs_sha1, tcs_variant,
300 tcs_code, tcs_code_size);
301
302 if (tes_code)
303 free(tes_code);
304 if (tcs_code)
305 free(tcs_code);
306 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
307 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
308 return;
309 }
310
311 static VkResult
312 radv_pipeline_scratch_init(struct radv_device *device,
313 struct radv_pipeline *pipeline)
314 {
315 unsigned scratch_bytes_per_wave = 0;
316 unsigned max_waves = 0;
317 unsigned min_waves = 1;
318
319 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
320 if (pipeline->shaders[i]) {
321 unsigned max_stage_waves = device->scratch_waves;
322
323 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
324 pipeline->shaders[i]->config.scratch_bytes_per_wave);
325
326 max_stage_waves = MIN2(max_stage_waves,
327 4 * device->physical_device->rad_info.num_good_compute_units *
328 (256 / pipeline->shaders[i]->config.num_vgprs));
329 max_waves = MAX2(max_waves, max_stage_waves);
330 }
331 }
332
333 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
334 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
335 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
336 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
337 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
338 }
339
340 if (scratch_bytes_per_wave)
341 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
342
343 if (scratch_bytes_per_wave && max_waves < min_waves) {
344 /* Not really true at this moment, but will be true on first
345 * execution. Avoid having hanging shaders. */
346 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
347 }
348 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
349 pipeline->max_waves = max_waves;
350 return VK_SUCCESS;
351 }
352
353 static uint32_t si_translate_blend_function(VkBlendOp op)
354 {
355 switch (op) {
356 case VK_BLEND_OP_ADD:
357 return V_028780_COMB_DST_PLUS_SRC;
358 case VK_BLEND_OP_SUBTRACT:
359 return V_028780_COMB_SRC_MINUS_DST;
360 case VK_BLEND_OP_REVERSE_SUBTRACT:
361 return V_028780_COMB_DST_MINUS_SRC;
362 case VK_BLEND_OP_MIN:
363 return V_028780_COMB_MIN_DST_SRC;
364 case VK_BLEND_OP_MAX:
365 return V_028780_COMB_MAX_DST_SRC;
366 default:
367 return 0;
368 }
369 }
370
371 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
372 {
373 switch (factor) {
374 case VK_BLEND_FACTOR_ZERO:
375 return V_028780_BLEND_ZERO;
376 case VK_BLEND_FACTOR_ONE:
377 return V_028780_BLEND_ONE;
378 case VK_BLEND_FACTOR_SRC_COLOR:
379 return V_028780_BLEND_SRC_COLOR;
380 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
381 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
382 case VK_BLEND_FACTOR_DST_COLOR:
383 return V_028780_BLEND_DST_COLOR;
384 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
385 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
386 case VK_BLEND_FACTOR_SRC_ALPHA:
387 return V_028780_BLEND_SRC_ALPHA;
388 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
389 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
390 case VK_BLEND_FACTOR_DST_ALPHA:
391 return V_028780_BLEND_DST_ALPHA;
392 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
393 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
394 case VK_BLEND_FACTOR_CONSTANT_COLOR:
395 return V_028780_BLEND_CONSTANT_COLOR;
396 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
397 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
398 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
399 return V_028780_BLEND_CONSTANT_ALPHA;
400 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
401 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
402 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
403 return V_028780_BLEND_SRC_ALPHA_SATURATE;
404 case VK_BLEND_FACTOR_SRC1_COLOR:
405 return V_028780_BLEND_SRC1_COLOR;
406 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
407 return V_028780_BLEND_INV_SRC1_COLOR;
408 case VK_BLEND_FACTOR_SRC1_ALPHA:
409 return V_028780_BLEND_SRC1_ALPHA;
410 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
411 return V_028780_BLEND_INV_SRC1_ALPHA;
412 default:
413 return 0;
414 }
415 }
416
417 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
418 {
419 switch (op) {
420 case VK_BLEND_OP_ADD:
421 return V_028760_OPT_COMB_ADD;
422 case VK_BLEND_OP_SUBTRACT:
423 return V_028760_OPT_COMB_SUBTRACT;
424 case VK_BLEND_OP_REVERSE_SUBTRACT:
425 return V_028760_OPT_COMB_REVSUBTRACT;
426 case VK_BLEND_OP_MIN:
427 return V_028760_OPT_COMB_MIN;
428 case VK_BLEND_OP_MAX:
429 return V_028760_OPT_COMB_MAX;
430 default:
431 return V_028760_OPT_COMB_BLEND_DISABLED;
432 }
433 }
434
435 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
436 {
437 switch (factor) {
438 case VK_BLEND_FACTOR_ZERO:
439 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
440 case VK_BLEND_FACTOR_ONE:
441 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
442 case VK_BLEND_FACTOR_SRC_COLOR:
443 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
444 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
445 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
446 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
447 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
448 case VK_BLEND_FACTOR_SRC_ALPHA:
449 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
450 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
451 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
452 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
453 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
454 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
455 default:
456 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
457 }
458 }
459
460 /**
461 * Get rid of DST in the blend factors by commuting the operands:
462 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
463 */
464 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
465 unsigned *dst_factor, unsigned expected_dst,
466 unsigned replacement_src)
467 {
468 if (*src_factor == expected_dst &&
469 *dst_factor == VK_BLEND_FACTOR_ZERO) {
470 *src_factor = VK_BLEND_FACTOR_ZERO;
471 *dst_factor = replacement_src;
472
473 /* Commuting the operands requires reversing subtractions. */
474 if (*func == VK_BLEND_OP_SUBTRACT)
475 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
476 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
477 *func = VK_BLEND_OP_SUBTRACT;
478 }
479 }
480
481 static bool si_blend_factor_uses_dst(unsigned factor)
482 {
483 return factor == VK_BLEND_FACTOR_DST_COLOR ||
484 factor == VK_BLEND_FACTOR_DST_ALPHA ||
485 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
486 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
487 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
488 }
489
490 static bool is_dual_src(VkBlendFactor factor)
491 {
492 switch (factor) {
493 case VK_BLEND_FACTOR_SRC1_COLOR:
494 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
495 case VK_BLEND_FACTOR_SRC1_ALPHA:
496 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
497 return true;
498 default:
499 return false;
500 }
501 }
502
503 static unsigned si_choose_spi_color_format(VkFormat vk_format,
504 bool blend_enable,
505 bool blend_need_alpha)
506 {
507 const struct vk_format_description *desc = vk_format_description(vk_format);
508 unsigned format, ntype, swap;
509
510 /* Alpha is needed for alpha-to-coverage.
511 * Blending may be with or without alpha.
512 */
513 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
514 unsigned alpha = 0; /* exports alpha, but may not support blending */
515 unsigned blend = 0; /* supports blending, but may not export alpha */
516 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
517
518 format = radv_translate_colorformat(vk_format);
519 ntype = radv_translate_color_numformat(vk_format, desc,
520 vk_format_get_first_non_void_channel(vk_format));
521 swap = radv_translate_colorswap(vk_format, false);
522
523 /* Choose the SPI color formats. These are required values for Stoney/RB+.
524 * Other chips have multiple choices, though they are not necessarily better.
525 */
526 switch (format) {
527 case V_028C70_COLOR_5_6_5:
528 case V_028C70_COLOR_1_5_5_5:
529 case V_028C70_COLOR_5_5_5_1:
530 case V_028C70_COLOR_4_4_4_4:
531 case V_028C70_COLOR_10_11_11:
532 case V_028C70_COLOR_11_11_10:
533 case V_028C70_COLOR_8:
534 case V_028C70_COLOR_8_8:
535 case V_028C70_COLOR_8_8_8_8:
536 case V_028C70_COLOR_10_10_10_2:
537 case V_028C70_COLOR_2_10_10_10:
538 if (ntype == V_028C70_NUMBER_UINT)
539 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
540 else if (ntype == V_028C70_NUMBER_SINT)
541 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
542 else
543 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
544 break;
545
546 case V_028C70_COLOR_16:
547 case V_028C70_COLOR_16_16:
548 case V_028C70_COLOR_16_16_16_16:
549 if (ntype == V_028C70_NUMBER_UNORM ||
550 ntype == V_028C70_NUMBER_SNORM) {
551 /* UNORM16 and SNORM16 don't support blending */
552 if (ntype == V_028C70_NUMBER_UNORM)
553 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
554 else
555 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
556
557 /* Use 32 bits per channel for blending. */
558 if (format == V_028C70_COLOR_16) {
559 if (swap == V_028C70_SWAP_STD) { /* R */
560 blend = V_028714_SPI_SHADER_32_R;
561 blend_alpha = V_028714_SPI_SHADER_32_AR;
562 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
563 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
564 else
565 assert(0);
566 } else if (format == V_028C70_COLOR_16_16) {
567 if (swap == V_028C70_SWAP_STD) { /* RG */
568 blend = V_028714_SPI_SHADER_32_GR;
569 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
570 } else if (swap == V_028C70_SWAP_ALT) /* RA */
571 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
572 else
573 assert(0);
574 } else /* 16_16_16_16 */
575 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
576 } else if (ntype == V_028C70_NUMBER_UINT)
577 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
578 else if (ntype == V_028C70_NUMBER_SINT)
579 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
580 else if (ntype == V_028C70_NUMBER_FLOAT)
581 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
582 else
583 assert(0);
584 break;
585
586 case V_028C70_COLOR_32:
587 if (swap == V_028C70_SWAP_STD) { /* R */
588 blend = normal = V_028714_SPI_SHADER_32_R;
589 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
590 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
591 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
592 else
593 assert(0);
594 break;
595
596 case V_028C70_COLOR_32_32:
597 if (swap == V_028C70_SWAP_STD) { /* RG */
598 blend = normal = V_028714_SPI_SHADER_32_GR;
599 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
600 } else if (swap == V_028C70_SWAP_ALT) /* RA */
601 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
602 else
603 assert(0);
604 break;
605
606 case V_028C70_COLOR_32_32_32_32:
607 case V_028C70_COLOR_8_24:
608 case V_028C70_COLOR_24_8:
609 case V_028C70_COLOR_X24_8_32_FLOAT:
610 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
611 break;
612
613 default:
614 unreachable("unhandled blend format");
615 }
616
617 if (blend_enable && blend_need_alpha)
618 return blend_alpha;
619 else if(blend_need_alpha)
620 return alpha;
621 else if(blend_enable)
622 return blend;
623 else
624 return normal;
625 }
626
627 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
628 {
629 unsigned i, cb_shader_mask = 0;
630
631 for (i = 0; i < 8; i++) {
632 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
633 case V_028714_SPI_SHADER_ZERO:
634 break;
635 case V_028714_SPI_SHADER_32_R:
636 cb_shader_mask |= 0x1 << (i * 4);
637 break;
638 case V_028714_SPI_SHADER_32_GR:
639 cb_shader_mask |= 0x3 << (i * 4);
640 break;
641 case V_028714_SPI_SHADER_32_AR:
642 cb_shader_mask |= 0x9 << (i * 4);
643 break;
644 case V_028714_SPI_SHADER_FP16_ABGR:
645 case V_028714_SPI_SHADER_UNORM16_ABGR:
646 case V_028714_SPI_SHADER_SNORM16_ABGR:
647 case V_028714_SPI_SHADER_UINT16_ABGR:
648 case V_028714_SPI_SHADER_SINT16_ABGR:
649 case V_028714_SPI_SHADER_32_ABGR:
650 cb_shader_mask |= 0xf << (i * 4);
651 break;
652 default:
653 assert(0);
654 }
655 }
656 return cb_shader_mask;
657 }
658
659 static void
660 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
661 const VkGraphicsPipelineCreateInfo *pCreateInfo,
662 uint32_t blend_enable,
663 uint32_t blend_need_alpha,
664 bool single_cb_enable,
665 bool blend_mrt0_is_dual_src)
666 {
667 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
668 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
669 struct radv_blend_state *blend = &pipeline->graphics.blend;
670 unsigned col_format = 0;
671
672 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
673 unsigned cf;
674
675 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
676 cf = V_028714_SPI_SHADER_ZERO;
677 } else {
678 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
679
680 cf = si_choose_spi_color_format(attachment->format,
681 blend_enable & (1 << i),
682 blend_need_alpha & (1 << i));
683 }
684
685 col_format |= cf << (4 * i);
686 }
687
688 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
689
690 if (blend_mrt0_is_dual_src)
691 col_format |= (col_format & 0xf) << 4;
692 blend->spi_shader_col_format = col_format;
693 }
694
695 static bool
696 format_is_int8(VkFormat format)
697 {
698 const struct vk_format_description *desc = vk_format_description(format);
699 int channel = vk_format_get_first_non_void_channel(format);
700
701 return channel >= 0 && desc->channel[channel].pure_integer &&
702 desc->channel[channel].size == 8;
703 }
704
705 static bool
706 format_is_int10(VkFormat format)
707 {
708 const struct vk_format_description *desc = vk_format_description(format);
709
710 if (desc->nr_channels != 4)
711 return false;
712 for (unsigned i = 0; i < 4; i++) {
713 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
714 return true;
715 }
716 return false;
717 }
718
719 unsigned radv_format_meta_fs_key(VkFormat format)
720 {
721 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
722 bool is_int8 = format_is_int8(format);
723 bool is_int10 = format_is_int10(format);
724
725 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
726 }
727
728 static void
729 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
730 unsigned *is_int8, unsigned *is_int10)
731 {
732 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
733 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
734 *is_int8 = 0;
735 *is_int10 = 0;
736
737 for (unsigned i = 0; i < subpass->color_count; ++i) {
738 struct radv_render_pass_attachment *attachment;
739
740 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
741 continue;
742
743 attachment = pass->attachments + subpass->color_attachments[i].attachment;
744
745 if (format_is_int8(attachment->format))
746 *is_int8 |= 1 << i;
747 if (format_is_int10(attachment->format))
748 *is_int10 |= 1 << i;
749 }
750 }
751
752 static void
753 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
754 const VkGraphicsPipelineCreateInfo *pCreateInfo,
755 const struct radv_graphics_pipeline_create_info *extra)
756 {
757 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
758 struct radv_blend_state *blend = &pipeline->graphics.blend;
759 unsigned mode = V_028808_CB_NORMAL;
760 uint32_t blend_enable = 0, blend_need_alpha = 0;
761 bool blend_mrt0_is_dual_src = false;
762 int i;
763 bool single_cb_enable = false;
764
765 if (!vkblend)
766 return;
767
768 if (extra && extra->custom_blend_mode) {
769 single_cb_enable = true;
770 mode = extra->custom_blend_mode;
771 }
772 blend->cb_color_control = 0;
773 if (vkblend->logicOpEnable)
774 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
775 else
776 blend->cb_color_control |= S_028808_ROP3(0xcc);
777
778 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
779 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
780 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
781 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
782
783 blend->cb_target_mask = 0;
784 for (i = 0; i < vkblend->attachmentCount; i++) {
785 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
786 unsigned blend_cntl = 0;
787 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
788 VkBlendOp eqRGB = att->colorBlendOp;
789 VkBlendFactor srcRGB = att->srcColorBlendFactor;
790 VkBlendFactor dstRGB = att->dstColorBlendFactor;
791 VkBlendOp eqA = att->alphaBlendOp;
792 VkBlendFactor srcA = att->srcAlphaBlendFactor;
793 VkBlendFactor dstA = att->dstAlphaBlendFactor;
794
795 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
796
797 if (!att->colorWriteMask)
798 continue;
799
800 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
801 if (!att->blendEnable) {
802 blend->cb_blend_control[i] = blend_cntl;
803 continue;
804 }
805
806 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
807 if (i == 0)
808 blend_mrt0_is_dual_src = true;
809
810 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
811 srcRGB = VK_BLEND_FACTOR_ONE;
812 dstRGB = VK_BLEND_FACTOR_ONE;
813 }
814 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
815 srcA = VK_BLEND_FACTOR_ONE;
816 dstA = VK_BLEND_FACTOR_ONE;
817 }
818
819 /* Blending optimizations for RB+.
820 * These transformations don't change the behavior.
821 *
822 * First, get rid of DST in the blend factors:
823 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
824 */
825 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
826 VK_BLEND_FACTOR_DST_COLOR,
827 VK_BLEND_FACTOR_SRC_COLOR);
828
829 si_blend_remove_dst(&eqA, &srcA, &dstA,
830 VK_BLEND_FACTOR_DST_COLOR,
831 VK_BLEND_FACTOR_SRC_COLOR);
832
833 si_blend_remove_dst(&eqA, &srcA, &dstA,
834 VK_BLEND_FACTOR_DST_ALPHA,
835 VK_BLEND_FACTOR_SRC_ALPHA);
836
837 /* Look up the ideal settings from tables. */
838 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
839 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
840 srcA_opt = si_translate_blend_opt_factor(srcA, true);
841 dstA_opt = si_translate_blend_opt_factor(dstA, true);
842
843 /* Handle interdependencies. */
844 if (si_blend_factor_uses_dst(srcRGB))
845 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
846 if (si_blend_factor_uses_dst(srcA))
847 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
848
849 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
850 (dstRGB == VK_BLEND_FACTOR_ZERO ||
851 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
852 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
853 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
854
855 /* Set the final value. */
856 blend->sx_mrt_blend_opt[i] =
857 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
858 S_028760_COLOR_DST_OPT(dstRGB_opt) |
859 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
860 S_028760_ALPHA_SRC_OPT(srcA_opt) |
861 S_028760_ALPHA_DST_OPT(dstA_opt) |
862 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
863 blend_cntl |= S_028780_ENABLE(1);
864
865 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
866 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
867 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
868 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
869 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
870 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
871 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
872 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
873 }
874 blend->cb_blend_control[i] = blend_cntl;
875
876 blend_enable |= 1 << i;
877
878 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
879 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
880 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
881 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
882 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
883 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
884 blend_need_alpha |= 1 << i;
885 }
886 for (i = vkblend->attachmentCount; i < 8; i++) {
887 blend->cb_blend_control[i] = 0;
888 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
889 }
890
891 /* disable RB+ for now */
892 if (pipeline->device->physical_device->has_rbplus)
893 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
894
895 if (blend->cb_target_mask)
896 blend->cb_color_control |= S_028808_MODE(mode);
897 else
898 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
899
900 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
901 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
902 }
903
904 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
905 {
906 switch (op) {
907 case VK_STENCIL_OP_KEEP:
908 return V_02842C_STENCIL_KEEP;
909 case VK_STENCIL_OP_ZERO:
910 return V_02842C_STENCIL_ZERO;
911 case VK_STENCIL_OP_REPLACE:
912 return V_02842C_STENCIL_REPLACE_TEST;
913 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
914 return V_02842C_STENCIL_ADD_CLAMP;
915 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
916 return V_02842C_STENCIL_SUB_CLAMP;
917 case VK_STENCIL_OP_INVERT:
918 return V_02842C_STENCIL_INVERT;
919 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
920 return V_02842C_STENCIL_ADD_WRAP;
921 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
922 return V_02842C_STENCIL_SUB_WRAP;
923 default:
924 return 0;
925 }
926 }
927 static void
928 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
929 const VkGraphicsPipelineCreateInfo *pCreateInfo,
930 const struct radv_graphics_pipeline_create_info *extra)
931 {
932 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
933 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
934
935 memset(ds, 0, sizeof(*ds));
936 if (!vkds)
937 return;
938
939 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
940 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
941 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
942 return;
943
944 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
945 bool has_depth_attachment = vk_format_is_depth(attachment->format);
946 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
947
948 if (has_depth_attachment) {
949 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
950 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
951 S_028800_ZFUNC(vkds->depthCompareOp) |
952 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
953 }
954
955 if (has_stencil_attachment && vkds->stencilTestEnable) {
956 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
957 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
958 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
959 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
960 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
961
962 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
963 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
964 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
965 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
966 }
967
968 if (extra) {
969
970 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
971 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
972
973 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
974 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
975 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
976 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
977 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
978 }
979 }
980
981 static uint32_t si_translate_fill(VkPolygonMode func)
982 {
983 switch(func) {
984 case VK_POLYGON_MODE_FILL:
985 return V_028814_X_DRAW_TRIANGLES;
986 case VK_POLYGON_MODE_LINE:
987 return V_028814_X_DRAW_LINES;
988 case VK_POLYGON_MODE_POINT:
989 return V_028814_X_DRAW_POINTS;
990 default:
991 assert(0);
992 return V_028814_X_DRAW_POINTS;
993 }
994 }
995 static void
996 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
997 const VkGraphicsPipelineCreateInfo *pCreateInfo)
998 {
999 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1000 struct radv_raster_state *raster = &pipeline->graphics.raster;
1001
1002 memset(raster, 0, sizeof(*raster));
1003
1004 raster->spi_interp_control =
1005 S_0286D4_FLAT_SHADE_ENA(1) |
1006 S_0286D4_PNT_SPRITE_ENA(1) |
1007 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1008 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1009 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1010 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1011 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1012
1013
1014 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1015 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1016 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1017 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1018 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1019 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1020
1021 raster->pa_su_vtx_cntl =
1022 S_028BE4_PIX_CENTER(1) | // TODO verify
1023 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1024 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1025
1026 raster->pa_su_sc_mode_cntl =
1027 S_028814_FACE(vkraster->frontFace) |
1028 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1029 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1030 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1031 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1032 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1033 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1034 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1035 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1036
1037 }
1038
1039 static void
1040 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1041 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1042 {
1043 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1044 struct radv_blend_state *blend = &pipeline->graphics.blend;
1045 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1046 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1047 int ps_iter_samples = 1;
1048 uint32_t mask = 0xffff;
1049
1050 if (vkms)
1051 ms->num_samples = vkms->rasterizationSamples;
1052 else
1053 ms->num_samples = 1;
1054
1055 if (vkms && vkms->sampleShadingEnable) {
1056 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1057 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1058 ps_iter_samples = ms->num_samples;
1059 }
1060
1061 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1062 ms->pa_sc_aa_config = 0;
1063 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1064 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1065 ms->pa_sc_mode_cntl_1 =
1066 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1067 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1068 /* always 1: */
1069 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1070 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1071 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1072 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1073 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1074 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1075 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1076
1077 if (ms->num_samples > 1) {
1078 unsigned log_samples = util_logbase2(ms->num_samples);
1079 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1080 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1081 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1082 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1083 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1084 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1085 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1086 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1087 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1088 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1089 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1090 }
1091
1092 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1093 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1094 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1095 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1096 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1097 }
1098
1099 if (vkms) {
1100 if (vkms->alphaToCoverageEnable)
1101 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1102
1103 if (vkms->pSampleMask)
1104 mask = vkms->pSampleMask[0] & 0xffff;
1105 }
1106
1107 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1108 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1109 }
1110
1111 static bool
1112 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1113 {
1114 switch (topology) {
1115 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1116 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1117 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1118 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1119 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1120 return false;
1121 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1122 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1123 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1124 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1125 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1126 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1127 return true;
1128 default:
1129 unreachable("unhandled primitive type");
1130 }
1131 }
1132
1133 static uint32_t
1134 si_translate_prim(enum VkPrimitiveTopology topology)
1135 {
1136 switch (topology) {
1137 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1138 return V_008958_DI_PT_POINTLIST;
1139 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1140 return V_008958_DI_PT_LINELIST;
1141 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1142 return V_008958_DI_PT_LINESTRIP;
1143 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1144 return V_008958_DI_PT_TRILIST;
1145 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1146 return V_008958_DI_PT_TRISTRIP;
1147 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1148 return V_008958_DI_PT_TRIFAN;
1149 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1150 return V_008958_DI_PT_LINELIST_ADJ;
1151 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1152 return V_008958_DI_PT_LINESTRIP_ADJ;
1153 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1154 return V_008958_DI_PT_TRILIST_ADJ;
1155 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1156 return V_008958_DI_PT_TRISTRIP_ADJ;
1157 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1158 return V_008958_DI_PT_PATCH;
1159 default:
1160 assert(0);
1161 return 0;
1162 }
1163 }
1164
1165 static uint32_t
1166 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1167 {
1168 switch (gl_prim) {
1169 case 0: /* GL_POINTS */
1170 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1171 case 1: /* GL_LINES */
1172 case 3: /* GL_LINE_STRIP */
1173 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1174 case 0x8E7A: /* GL_ISOLINES */
1175 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1176
1177 case 4: /* GL_TRIANGLES */
1178 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1179 case 5: /* GL_TRIANGLE_STRIP */
1180 case 7: /* GL_QUADS */
1181 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1182 default:
1183 assert(0);
1184 return 0;
1185 }
1186 }
1187
1188 static uint32_t
1189 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1190 {
1191 switch (topology) {
1192 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1193 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1194 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1195 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1199 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1205 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1206 default:
1207 assert(0);
1208 return 0;
1209 }
1210 }
1211
1212 static unsigned si_map_swizzle(unsigned swizzle)
1213 {
1214 switch (swizzle) {
1215 case VK_SWIZZLE_Y:
1216 return V_008F0C_SQ_SEL_Y;
1217 case VK_SWIZZLE_Z:
1218 return V_008F0C_SQ_SEL_Z;
1219 case VK_SWIZZLE_W:
1220 return V_008F0C_SQ_SEL_W;
1221 case VK_SWIZZLE_0:
1222 return V_008F0C_SQ_SEL_0;
1223 case VK_SWIZZLE_1:
1224 return V_008F0C_SQ_SEL_1;
1225 default: /* VK_SWIZZLE_X */
1226 return V_008F0C_SQ_SEL_X;
1227 }
1228 }
1229
1230 static void
1231 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1232 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1233 {
1234 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1235 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1236 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1237
1238 pipeline->dynamic_state = default_dynamic_state;
1239
1240 if (pCreateInfo->pDynamicState) {
1241 /* Remove all of the states that are marked as dynamic */
1242 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1243 for (uint32_t s = 0; s < count; s++)
1244 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1245 }
1246
1247 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1248
1249 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1250 *
1251 * pViewportState is [...] NULL if the pipeline
1252 * has rasterization disabled.
1253 */
1254 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1255 assert(pCreateInfo->pViewportState);
1256
1257 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1258 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1259 typed_memcpy(dynamic->viewport.viewports,
1260 pCreateInfo->pViewportState->pViewports,
1261 pCreateInfo->pViewportState->viewportCount);
1262 }
1263
1264 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1265 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1266 typed_memcpy(dynamic->scissor.scissors,
1267 pCreateInfo->pViewportState->pScissors,
1268 pCreateInfo->pViewportState->scissorCount);
1269 }
1270 }
1271
1272 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1273 assert(pCreateInfo->pRasterizationState);
1274 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1275 }
1276
1277 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1278 assert(pCreateInfo->pRasterizationState);
1279 dynamic->depth_bias.bias =
1280 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1281 dynamic->depth_bias.clamp =
1282 pCreateInfo->pRasterizationState->depthBiasClamp;
1283 dynamic->depth_bias.slope =
1284 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1285 }
1286
1287 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1288 *
1289 * pColorBlendState is [...] NULL if the pipeline has rasterization
1290 * disabled or if the subpass of the render pass the pipeline is
1291 * created against does not use any color attachments.
1292 */
1293 bool uses_color_att = false;
1294 for (unsigned i = 0; i < subpass->color_count; ++i) {
1295 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1296 uses_color_att = true;
1297 break;
1298 }
1299 }
1300
1301 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1302 assert(pCreateInfo->pColorBlendState);
1303 typed_memcpy(dynamic->blend_constants,
1304 pCreateInfo->pColorBlendState->blendConstants, 4);
1305 }
1306
1307 /* If there is no depthstencil attachment, then don't read
1308 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1309 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1310 * no need to override the depthstencil defaults in
1311 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1312 *
1313 * Section 9.2 of the Vulkan 1.0.15 spec says:
1314 *
1315 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1316 * disabled or if the subpass of the render pass the pipeline is created
1317 * against does not use a depth/stencil attachment.
1318 */
1319 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1320 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1321 assert(pCreateInfo->pDepthStencilState);
1322
1323 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1324 dynamic->depth_bounds.min =
1325 pCreateInfo->pDepthStencilState->minDepthBounds;
1326 dynamic->depth_bounds.max =
1327 pCreateInfo->pDepthStencilState->maxDepthBounds;
1328 }
1329
1330 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1331 dynamic->stencil_compare_mask.front =
1332 pCreateInfo->pDepthStencilState->front.compareMask;
1333 dynamic->stencil_compare_mask.back =
1334 pCreateInfo->pDepthStencilState->back.compareMask;
1335 }
1336
1337 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1338 dynamic->stencil_write_mask.front =
1339 pCreateInfo->pDepthStencilState->front.writeMask;
1340 dynamic->stencil_write_mask.back =
1341 pCreateInfo->pDepthStencilState->back.writeMask;
1342 }
1343
1344 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1345 dynamic->stencil_reference.front =
1346 pCreateInfo->pDepthStencilState->front.reference;
1347 dynamic->stencil_reference.back =
1348 pCreateInfo->pDepthStencilState->back.reference;
1349 }
1350 }
1351
1352 pipeline->dynamic_state_mask = states;
1353 }
1354
1355 static struct ac_shader_variant_key
1356 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1357 {
1358 struct ac_shader_variant_key key;
1359 const VkPipelineVertexInputStateCreateInfo *input_state =
1360 pCreateInfo->pVertexInputState;
1361
1362 memset(&key, 0, sizeof(key));
1363 key.vs.instance_rate_inputs = 0;
1364 key.vs.as_es = as_es;
1365 key.vs.as_ls = as_ls;
1366 key.vs.export_prim_id = export_prim_id;
1367
1368 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1369 unsigned binding;
1370 binding = input_state->pVertexAttributeDescriptions[i].binding;
1371 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1372 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1373 }
1374 return key;
1375 }
1376
1377 static void
1378 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1379 {
1380 struct radv_device *device = pipeline->device;
1381 unsigned num_se = device->physical_device->rad_info.max_se;
1382 unsigned wave_size = 64;
1383 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1384 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1385 unsigned alignment = 256 * num_se;
1386 /* The maximum size is 63.999 MB per SE. */
1387 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1388 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1389 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1390 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1391 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1392
1393 /* Calculate the minimum size. */
1394 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1395 wave_size, alignment);
1396 /* These are recommended sizes, not minimum sizes. */
1397 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1398 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1399 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1400 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1401
1402 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1403 esgs_ring_size = align(esgs_ring_size, alignment);
1404 gsvs_ring_size = align(gsvs_ring_size, alignment);
1405
1406 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1407 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1408 }
1409
1410 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1411 unsigned *lds_size)
1412 {
1413 /* SPI barrier management bug:
1414 * Make sure we have at least 4k of LDS in use to avoid the bug.
1415 * It applies to workgroup sizes of more than one wavefront.
1416 */
1417 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1418 device->physical_device->rad_info.family == CHIP_KABINI ||
1419 device->physical_device->rad_info.family == CHIP_MULLINS)
1420 *lds_size = MAX2(*lds_size, 8);
1421 }
1422
1423 static void
1424 calculate_tess_state(struct radv_pipeline *pipeline,
1425 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1426 {
1427 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1428 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1429 unsigned num_tcs_patch_outputs;
1430 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1431 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1432 unsigned lds_size, hardware_lds_size;
1433 unsigned perpatch_output_offset;
1434 unsigned num_patches;
1435 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1436
1437 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1438 * are laid out in LDS. */
1439 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1440
1441 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1442 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1443 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1444
1445 /* Ensure that we only need one wave per SIMD so we don't need to check
1446 * resource usage. Also ensures that the number of tcs in and out
1447 * vertices per threadgroup are at most 256.
1448 */
1449 input_vertex_size = num_tcs_inputs * 16;
1450 output_vertex_size = num_tcs_outputs * 16;
1451
1452 input_patch_size = num_tcs_input_cp * input_vertex_size;
1453
1454 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1455 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1456 /* Ensure that we only need one wave per SIMD so we don't need to check
1457 * resource usage. Also ensures that the number of tcs in and out
1458 * vertices per threadgroup are at most 256.
1459 */
1460 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1461
1462 /* Make sure that the data fits in LDS. This assumes the shaders only
1463 * use LDS for the inputs and outputs.
1464 */
1465 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1466 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1467
1468 /* Make sure the output data fits in the offchip buffer */
1469 num_patches = MIN2(num_patches,
1470 (pipeline->device->tess_offchip_block_dw_size * 4) /
1471 output_patch_size);
1472
1473 /* Not necessary for correctness, but improves performance. The
1474 * specific value is taken from the proprietary driver.
1475 */
1476 num_patches = MIN2(num_patches, 40);
1477
1478 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1479 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1480 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1481 num_patches = MIN2(num_patches, one_wave);
1482 }
1483
1484 output_patch0_offset = input_patch_size * num_patches;
1485 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1486
1487 lds_size = output_patch0_offset + output_patch_size * num_patches;
1488
1489 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1490 assert(lds_size <= 65536);
1491 lds_size = align(lds_size, 512) / 512;
1492 } else {
1493 assert(lds_size <= 32768);
1494 lds_size = align(lds_size, 256) / 256;
1495 }
1496 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1497
1498 tess->lds_size = lds_size;
1499
1500 tess->tcs_in_layout = (input_patch_size / 4) |
1501 ((input_vertex_size / 4) << 13);
1502 tess->tcs_out_layout = (output_patch_size / 4) |
1503 ((output_vertex_size / 4) << 13);
1504 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1505 ((perpatch_output_offset / 16) << 16);
1506 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1507 (num_tcs_output_cp << 9) | num_patches;
1508
1509 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1510 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1511 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1512 tess->num_patches = num_patches;
1513 tess->num_tcs_input_cp = num_tcs_input_cp;
1514
1515 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1516 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1517
1518 switch (tes->info.tes.primitive_mode) {
1519 case GL_TRIANGLES:
1520 type = V_028B6C_TESS_TRIANGLE;
1521 break;
1522 case GL_QUADS:
1523 type = V_028B6C_TESS_QUAD;
1524 break;
1525 case GL_ISOLINES:
1526 type = V_028B6C_TESS_ISOLINE;
1527 break;
1528 }
1529
1530 switch (tes->info.tes.spacing) {
1531 case TESS_SPACING_EQUAL:
1532 partitioning = V_028B6C_PART_INTEGER;
1533 break;
1534 case TESS_SPACING_FRACTIONAL_ODD:
1535 partitioning = V_028B6C_PART_FRAC_ODD;
1536 break;
1537 case TESS_SPACING_FRACTIONAL_EVEN:
1538 partitioning = V_028B6C_PART_FRAC_EVEN;
1539 break;
1540 default:
1541 break;
1542 }
1543
1544 bool ccw = tes->info.tes.ccw;
1545 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1546 vk_find_struct_const(pCreateInfo->pTessellationState,
1547 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1548
1549 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1550 ccw = !ccw;
1551
1552 if (tes->info.tes.point_mode)
1553 topology = V_028B6C_OUTPUT_POINT;
1554 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1555 topology = V_028B6C_OUTPUT_LINE;
1556 else if (ccw)
1557 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1558 else
1559 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1560
1561 if (pipeline->device->has_distributed_tess) {
1562 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1563 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1564 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1565 else
1566 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1567 } else
1568 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1569
1570 tess->tf_param = S_028B6C_TYPE(type) |
1571 S_028B6C_PARTITIONING(partitioning) |
1572 S_028B6C_TOPOLOGY(topology) |
1573 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1574 }
1575
1576 static const struct radv_prim_vertex_count prim_size_table[] = {
1577 [V_008958_DI_PT_NONE] = {0, 0},
1578 [V_008958_DI_PT_POINTLIST] = {1, 1},
1579 [V_008958_DI_PT_LINELIST] = {2, 2},
1580 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1581 [V_008958_DI_PT_TRILIST] = {3, 3},
1582 [V_008958_DI_PT_TRIFAN] = {3, 1},
1583 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1584 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1585 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1586 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1587 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1588 [V_008958_DI_PT_RECTLIST] = {3, 3},
1589 [V_008958_DI_PT_LINELOOP] = {2, 1},
1590 [V_008958_DI_PT_POLYGON] = {3, 1},
1591 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1592 };
1593
1594 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1595 {
1596 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1597 unsigned cut_mode;
1598
1599 if (gs_max_vert_out <= 128) {
1600 cut_mode = V_028A40_GS_CUT_128;
1601 } else if (gs_max_vert_out <= 256) {
1602 cut_mode = V_028A40_GS_CUT_256;
1603 } else if (gs_max_vert_out <= 512) {
1604 cut_mode = V_028A40_GS_CUT_512;
1605 } else {
1606 assert(gs_max_vert_out <= 1024);
1607 cut_mode = V_028A40_GS_CUT_1024;
1608 }
1609
1610 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1611 S_028A40_CUT_MODE(cut_mode)|
1612 S_028A40_ES_WRITE_OPTIMIZE(1) |
1613 S_028A40_GS_WRITE_OPTIMIZE(1);
1614 }
1615
1616 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1617 {
1618 struct radv_shader_variant *vs;
1619 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1620
1621 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1622
1623 pipeline->graphics.vgt_primitiveid_en = false;
1624 pipeline->graphics.vgt_gs_mode = 0;
1625
1626 if (radv_pipeline_has_gs(pipeline)) {
1627 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1628 } else if (outinfo->export_prim_id) {
1629 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1630 pipeline->graphics.vgt_primitiveid_en = true;
1631 }
1632 }
1633
1634 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1635 {
1636 struct radv_shader_variant *vs;
1637 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1638
1639 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1640
1641 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1642 clip_dist_mask = outinfo->clip_dist_mask;
1643 cull_dist_mask = outinfo->cull_dist_mask;
1644 total_mask = clip_dist_mask | cull_dist_mask;
1645
1646 bool misc_vec_ena = outinfo->writes_pointsize ||
1647 outinfo->writes_layer ||
1648 outinfo->writes_viewport_index;
1649 pipeline->graphics.pa_cl_vs_out_cntl =
1650 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1651 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1652 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1653 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1654 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1655 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1656 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1657 cull_dist_mask << 8 |
1658 clip_dist_mask;
1659
1660 }
1661
1662 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1663 {
1664 uint32_t ps_input_cntl;
1665 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1666 ps_input_cntl = S_028644_OFFSET(offset);
1667 if (flat_shade)
1668 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1669 } else {
1670 /* The input is a DEFAULT_VAL constant. */
1671 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1672 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1673 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1674 ps_input_cntl = S_028644_OFFSET(0x20) |
1675 S_028644_DEFAULT_VAL(offset);
1676 }
1677 return ps_input_cntl;
1678 }
1679
1680 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1681 {
1682 struct radv_shader_variant *ps, *vs;
1683 struct ac_vs_output_info *outinfo;
1684
1685 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1686 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1687
1688 outinfo = &vs->info.vs.outinfo;
1689
1690 unsigned ps_offset = 0;
1691
1692 if (ps->info.fs.prim_id_input) {
1693 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1694 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1695 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1696 ++ps_offset;
1697 }
1698 }
1699
1700 if (ps->info.fs.layer_input) {
1701 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1702 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1703 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1704 else
1705 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1706 ++ps_offset;
1707 }
1708
1709 if (ps->info.fs.has_pcoord) {
1710 unsigned val;
1711 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1712 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1713 ps_offset++;
1714 }
1715
1716 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1717 unsigned vs_offset;
1718 bool flat_shade;
1719 if (!(ps->info.fs.input_mask & (1u << i)))
1720 continue;
1721
1722 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1723 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1724 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1725 ++ps_offset;
1726 continue;
1727 }
1728
1729 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1730
1731 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1732 ++ps_offset;
1733 }
1734
1735 pipeline->graphics.ps_input_cntl_num = ps_offset;
1736 }
1737
1738 static VkResult
1739 radv_pipeline_init(struct radv_pipeline *pipeline,
1740 struct radv_device *device,
1741 struct radv_pipeline_cache *cache,
1742 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1743 const struct radv_graphics_pipeline_create_info *extra,
1744 const VkAllocationCallbacks *alloc)
1745 {
1746 struct radv_shader_module fs_m = {0};
1747 VkResult result;
1748 bool has_view_index = false;
1749
1750 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1751 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1752 if (subpass->view_mask)
1753 has_view_index = true;
1754 if (alloc == NULL)
1755 alloc = &device->alloc;
1756
1757 pipeline->device = device;
1758 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1759
1760 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1761 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1762 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1763 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1764 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1765 pStages[stage] = &pCreateInfo->pStages[i];
1766 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1767 }
1768
1769 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1770
1771 if (!modules[MESA_SHADER_FRAGMENT]) {
1772 nir_builder fs_b;
1773 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1774 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1775 fs_m.nir = fs_b.shader;
1776 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1777 }
1778
1779 if (modules[MESA_SHADER_FRAGMENT]) {
1780 struct ac_shader_variant_key key = {0};
1781 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1782 if (pCreateInfo->pMultisampleState &&
1783 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1784 key.fs.multisample = true;
1785
1786 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1787 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
1788
1789 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1790
1791 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1792 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1793 stage ? stage->pName : "main",
1794 MESA_SHADER_FRAGMENT,
1795 stage ? stage->pSpecializationInfo : NULL,
1796 pipeline->layout, &key);
1797 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1798 }
1799
1800 if (fs_m.nir)
1801 ralloc_free(fs_m.nir);
1802
1803 if (modules[MESA_SHADER_VERTEX]) {
1804 bool as_es = false;
1805 bool as_ls = false;
1806 bool export_prim_id = false;
1807 if (modules[MESA_SHADER_TESS_CTRL])
1808 as_ls = true;
1809 else if (modules[MESA_SHADER_GEOMETRY])
1810 as_es = true;
1811 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
1812 export_prim_id = true;
1813 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
1814 key.has_multiview_view_index = has_view_index;
1815
1816 pipeline->shaders[MESA_SHADER_VERTEX] =
1817 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1818 pStages[MESA_SHADER_VERTEX]->pName,
1819 MESA_SHADER_VERTEX,
1820 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1821 pipeline->layout, &key);
1822
1823 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1824 }
1825
1826 if (modules[MESA_SHADER_GEOMETRY]) {
1827 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
1828 key.has_multiview_view_index = has_view_index;
1829
1830 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1831 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1832 pStages[MESA_SHADER_GEOMETRY]->pName,
1833 MESA_SHADER_GEOMETRY,
1834 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1835 pipeline->layout, &key);
1836
1837 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1838 }
1839
1840 if (modules[MESA_SHADER_TESS_EVAL]) {
1841 assert(modules[MESA_SHADER_TESS_CTRL]);
1842
1843 radv_tess_pipeline_compile(pipeline,
1844 cache,
1845 modules[MESA_SHADER_TESS_CTRL],
1846 modules[MESA_SHADER_TESS_EVAL],
1847 pStages[MESA_SHADER_TESS_CTRL]->pName,
1848 pStages[MESA_SHADER_TESS_EVAL]->pName,
1849 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1850 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
1851 pipeline->layout,
1852 pCreateInfo->pTessellationState->patchControlPoints,
1853 has_view_index);
1854 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
1855 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
1856 }
1857
1858 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1859 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1860 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1861 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1862 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
1863
1864 if (radv_pipeline_has_gs(pipeline)) {
1865 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1866 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1867 } else {
1868 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1869 }
1870 if (extra && extra->use_rectlist) {
1871 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1872 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1873 pipeline->graphics.can_use_guardband = true;
1874 }
1875 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1876 /* prim vertex count will need TESS changes */
1877 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1878
1879 /* Ensure that some export memory is always allocated, for two reasons:
1880 *
1881 * 1) Correctness: The hardware ignores the EXEC mask if no export
1882 * memory is allocated, so KILL and alpha test do not work correctly
1883 * without this.
1884 * 2) Performance: Every shader needs at least a NULL export, even when
1885 * it writes no color/depth output. The NULL export instruction
1886 * stalls without this setting.
1887 *
1888 * Don't add this to CB_SHADER_MASK.
1889 */
1890 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1891 if (!pipeline->graphics.blend.spi_shader_col_format) {
1892 if (!ps->info.fs.writes_z &&
1893 !ps->info.fs.writes_stencil &&
1894 !ps->info.fs.writes_sample_mask)
1895 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1896 }
1897
1898 unsigned z_order;
1899 pipeline->graphics.db_shader_control = 0;
1900 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1901 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1902 else
1903 z_order = V_02880C_LATE_Z;
1904
1905 pipeline->graphics.db_shader_control =
1906 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1907 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1908 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1909 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1910 S_02880C_Z_ORDER(z_order) |
1911 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1912 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1913 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1914
1915 if (pipeline->device->physical_device->has_rbplus)
1916 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1917
1918 pipeline->graphics.shader_z_format =
1919 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
1920 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
1921 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
1922 V_028710_SPI_SHADER_ZERO;
1923
1924 calculate_vgt_gs_mode(pipeline);
1925 calculate_pa_cl_vs_out_cntl(pipeline);
1926 calculate_ps_inputs(pipeline);
1927
1928 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1929 if (pipeline->shaders[i]) {
1930 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
1931 }
1932 }
1933
1934 uint32_t stages = 0;
1935 if (radv_pipeline_has_tess(pipeline)) {
1936 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1937 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1938
1939 if (radv_pipeline_has_gs(pipeline))
1940 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1941 S_028B54_GS_EN(1) |
1942 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1943 else
1944 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1945
1946 } else if (radv_pipeline_has_gs(pipeline))
1947 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1948 S_028B54_GS_EN(1) |
1949 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1950
1951 if (device->physical_device->rad_info.chip_class >= GFX9)
1952 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1953
1954 pipeline->graphics.vgt_shader_stages_en = stages;
1955
1956 if (radv_pipeline_has_gs(pipeline))
1957 calculate_gs_ring_sizes(pipeline);
1958
1959 if (radv_pipeline_has_tess(pipeline)) {
1960 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
1961 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
1962 pipeline->graphics.prim_vertex_count.incr = 1;
1963 }
1964 calculate_tess_state(pipeline, pCreateInfo);
1965 }
1966
1967 if (radv_pipeline_has_tess(pipeline))
1968 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
1969 else if (radv_pipeline_has_gs(pipeline))
1970 pipeline->graphics.primgroup_size = 64;
1971 else
1972 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
1973
1974 pipeline->graphics.partial_es_wave = false;
1975 if (pipeline->device->has_distributed_tess) {
1976 if (radv_pipeline_has_gs(pipeline)) {
1977 if (device->physical_device->rad_info.chip_class <= VI)
1978 pipeline->graphics.partial_es_wave = true;
1979 }
1980 }
1981 /* GS requirement. */
1982 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
1983 pipeline->graphics.partial_es_wave = true;
1984
1985 pipeline->graphics.wd_switch_on_eop = false;
1986 if (device->physical_device->rad_info.chip_class >= CIK) {
1987 unsigned prim = pipeline->graphics.prim;
1988 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
1989 * 4 shader engines. Set 1 to pass the assertion below.
1990 * The other cases are hardware requirements. */
1991 if (device->physical_device->rad_info.max_se < 4 ||
1992 prim == V_008958_DI_PT_POLYGON ||
1993 prim == V_008958_DI_PT_LINELOOP ||
1994 prim == V_008958_DI_PT_TRIFAN ||
1995 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
1996 (pipeline->graphics.prim_restart_enable &&
1997 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
1998 (prim != V_008958_DI_PT_POINTLIST &&
1999 prim != V_008958_DI_PT_LINESTRIP &&
2000 prim != V_008958_DI_PT_TRISTRIP))))
2001 pipeline->graphics.wd_switch_on_eop = true;
2002 }
2003
2004 pipeline->graphics.ia_switch_on_eoi = false;
2005 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2006 pipeline->graphics.ia_switch_on_eoi = true;
2007 if (radv_pipeline_has_gs(pipeline) &&
2008 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
2009 pipeline->graphics.ia_switch_on_eoi = true;
2010 if (radv_pipeline_has_tess(pipeline)) {
2011 /* SWITCH_ON_EOI must be set if PrimID is used. */
2012 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
2013 pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
2014 pipeline->graphics.ia_switch_on_eoi = true;
2015 }
2016
2017 pipeline->graphics.partial_vs_wave = false;
2018 if (radv_pipeline_has_tess(pipeline)) {
2019 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2020 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2021 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2022 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2023 radv_pipeline_has_gs(pipeline))
2024 pipeline->graphics.partial_vs_wave = true;
2025 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2026 if (device->has_distributed_tess) {
2027 if (radv_pipeline_has_gs(pipeline)) {
2028 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2029 device->physical_device->rad_info.family == CHIP_FIJI ||
2030 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2031 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2032 device->physical_device->rad_info.family == CHIP_POLARIS12)
2033 pipeline->graphics.partial_vs_wave = true;
2034 } else {
2035 pipeline->graphics.partial_vs_wave = true;
2036 }
2037 }
2038 }
2039
2040 pipeline->graphics.base_ia_multi_vgt_param =
2041 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
2042 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
2043 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
2044 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
2045 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
2046
2047 const VkPipelineVertexInputStateCreateInfo *vi_info =
2048 pCreateInfo->pVertexInputState;
2049 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2050
2051 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2052 const VkVertexInputAttributeDescription *desc =
2053 &vi_info->pVertexAttributeDescriptions[i];
2054 unsigned loc = desc->location;
2055 const struct vk_format_description *format_desc;
2056 int first_non_void;
2057 uint32_t num_format, data_format;
2058 format_desc = vk_format_description(desc->format);
2059 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2060
2061 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2062 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2063
2064 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2065 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2066 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2067 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2068 S_008F0C_NUM_FORMAT(num_format) |
2069 S_008F0C_DATA_FORMAT(data_format);
2070 velems->format_size[loc] = format_desc->block.bits / 8;
2071 velems->offset[loc] = desc->offset;
2072 velems->binding[loc] = desc->binding;
2073 velems->count = MAX2(velems->count, loc + 1);
2074 }
2075
2076 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2077 const VkVertexInputBindingDescription *desc =
2078 &vi_info->pVertexBindingDescriptions[i];
2079
2080 pipeline->binding_stride[desc->binding] = desc->stride;
2081 }
2082
2083 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2084 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2085 if (loc->sgpr_idx != -1) {
2086 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2087 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2088 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2089 pipeline->graphics.vtx_emit_num = 3;
2090 else
2091 pipeline->graphics.vtx_emit_num = 2;
2092 }
2093 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2094 radv_dump_pipeline_stats(device, pipeline);
2095 }
2096
2097 result = radv_pipeline_scratch_init(device, pipeline);
2098 return result;
2099 }
2100
2101 VkResult
2102 radv_graphics_pipeline_create(
2103 VkDevice _device,
2104 VkPipelineCache _cache,
2105 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2106 const struct radv_graphics_pipeline_create_info *extra,
2107 const VkAllocationCallbacks *pAllocator,
2108 VkPipeline *pPipeline)
2109 {
2110 RADV_FROM_HANDLE(radv_device, device, _device);
2111 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2112 struct radv_pipeline *pipeline;
2113 VkResult result;
2114
2115 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2116 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2117 if (pipeline == NULL)
2118 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2119
2120 memset(pipeline, 0, sizeof(*pipeline));
2121 result = radv_pipeline_init(pipeline, device, cache,
2122 pCreateInfo, extra, pAllocator);
2123 if (result != VK_SUCCESS) {
2124 radv_pipeline_destroy(device, pipeline, pAllocator);
2125 return result;
2126 }
2127
2128 *pPipeline = radv_pipeline_to_handle(pipeline);
2129
2130 return VK_SUCCESS;
2131 }
2132
2133 VkResult radv_CreateGraphicsPipelines(
2134 VkDevice _device,
2135 VkPipelineCache pipelineCache,
2136 uint32_t count,
2137 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2138 const VkAllocationCallbacks* pAllocator,
2139 VkPipeline* pPipelines)
2140 {
2141 VkResult result = VK_SUCCESS;
2142 unsigned i = 0;
2143
2144 for (; i < count; i++) {
2145 VkResult r;
2146 r = radv_graphics_pipeline_create(_device,
2147 pipelineCache,
2148 &pCreateInfos[i],
2149 NULL, pAllocator, &pPipelines[i]);
2150 if (r != VK_SUCCESS) {
2151 result = r;
2152 pPipelines[i] = VK_NULL_HANDLE;
2153 }
2154 }
2155
2156 return result;
2157 }
2158
2159 static VkResult radv_compute_pipeline_create(
2160 VkDevice _device,
2161 VkPipelineCache _cache,
2162 const VkComputePipelineCreateInfo* pCreateInfo,
2163 const VkAllocationCallbacks* pAllocator,
2164 VkPipeline* pPipeline)
2165 {
2166 RADV_FROM_HANDLE(radv_device, device, _device);
2167 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2168 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2169 struct radv_pipeline *pipeline;
2170 VkResult result;
2171
2172 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2173 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2174 if (pipeline == NULL)
2175 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2176
2177 memset(pipeline, 0, sizeof(*pipeline));
2178 pipeline->device = device;
2179 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2180
2181 pipeline->shaders[MESA_SHADER_COMPUTE] =
2182 radv_pipeline_compile(pipeline, cache, module,
2183 pCreateInfo->stage.pName,
2184 MESA_SHADER_COMPUTE,
2185 pCreateInfo->stage.pSpecializationInfo,
2186 pipeline->layout, NULL);
2187
2188
2189 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2190 result = radv_pipeline_scratch_init(device, pipeline);
2191 if (result != VK_SUCCESS) {
2192 radv_pipeline_destroy(device, pipeline, pAllocator);
2193 return result;
2194 }
2195
2196 *pPipeline = radv_pipeline_to_handle(pipeline);
2197
2198 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2199 radv_dump_pipeline_stats(device, pipeline);
2200 }
2201 return VK_SUCCESS;
2202 }
2203 VkResult radv_CreateComputePipelines(
2204 VkDevice _device,
2205 VkPipelineCache pipelineCache,
2206 uint32_t count,
2207 const VkComputePipelineCreateInfo* pCreateInfos,
2208 const VkAllocationCallbacks* pAllocator,
2209 VkPipeline* pPipelines)
2210 {
2211 VkResult result = VK_SUCCESS;
2212
2213 unsigned i = 0;
2214 for (; i < count; i++) {
2215 VkResult r;
2216 r = radv_compute_pipeline_create(_device, pipelineCache,
2217 &pCreateInfos[i],
2218 pAllocator, &pPipelines[i]);
2219 if (r != VK_SUCCESS) {
2220 result = r;
2221 pPipelines[i] = VK_NULL_HANDLE;
2222 }
2223 }
2224
2225 return result;
2226 }