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radv: Fix up 2_10_10_10 alpha sign.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 static void
101 radv_pipeline_destroy(struct radv_device *device,
102 struct radv_pipeline *pipeline,
103 const VkAllocationCallbacks* allocator)
104 {
105 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
106 if (pipeline->shaders[i])
107 radv_shader_variant_destroy(device, pipeline->shaders[i]);
108
109 if (pipeline->gs_copy_shader)
110 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
111
112 if(pipeline->cs.buf)
113 free(pipeline->cs.buf);
114 vk_free2(&device->alloc, allocator, pipeline);
115 }
116
117 void radv_DestroyPipeline(
118 VkDevice _device,
119 VkPipeline _pipeline,
120 const VkAllocationCallbacks* pAllocator)
121 {
122 RADV_FROM_HANDLE(radv_device, device, _device);
123 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
124
125 if (!_pipeline)
126 return;
127
128 radv_pipeline_destroy(device, pipeline, pAllocator);
129 }
130
131 static uint32_t get_hash_flags(struct radv_device *device)
132 {
133 uint32_t hash_flags = 0;
134
135 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
136 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
137 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
138 hash_flags |= RADV_HASH_SHADER_SISCHED;
139 return hash_flags;
140 }
141
142 static VkResult
143 radv_pipeline_scratch_init(struct radv_device *device,
144 struct radv_pipeline *pipeline)
145 {
146 unsigned scratch_bytes_per_wave = 0;
147 unsigned max_waves = 0;
148 unsigned min_waves = 1;
149
150 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
151 if (pipeline->shaders[i]) {
152 unsigned max_stage_waves = device->scratch_waves;
153
154 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
155 pipeline->shaders[i]->config.scratch_bytes_per_wave);
156
157 max_stage_waves = MIN2(max_stage_waves,
158 4 * device->physical_device->rad_info.num_good_compute_units *
159 (256 / pipeline->shaders[i]->config.num_vgprs));
160 max_waves = MAX2(max_waves, max_stage_waves);
161 }
162 }
163
164 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
165 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
167 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
168 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
169 }
170
171 if (scratch_bytes_per_wave)
172 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
173
174 if (scratch_bytes_per_wave && max_waves < min_waves) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
178 }
179 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
180 pipeline->max_waves = max_waves;
181 return VK_SUCCESS;
182 }
183
184 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
185 {
186 switch (op) {
187 case VK_LOGIC_OP_CLEAR:
188 return V_028808_ROP3_CLEAR;
189 case VK_LOGIC_OP_AND:
190 return V_028808_ROP3_AND;
191 case VK_LOGIC_OP_AND_REVERSE:
192 return V_028808_ROP3_AND_REVERSE;
193 case VK_LOGIC_OP_COPY:
194 return V_028808_ROP3_COPY;
195 case VK_LOGIC_OP_AND_INVERTED:
196 return V_028808_ROP3_AND_INVERTED;
197 case VK_LOGIC_OP_NO_OP:
198 return V_028808_ROP3_NO_OP;
199 case VK_LOGIC_OP_XOR:
200 return V_028808_ROP3_XOR;
201 case VK_LOGIC_OP_OR:
202 return V_028808_ROP3_OR;
203 case VK_LOGIC_OP_NOR:
204 return V_028808_ROP3_NOR;
205 case VK_LOGIC_OP_EQUIVALENT:
206 return V_028808_ROP3_EQUIVALENT;
207 case VK_LOGIC_OP_INVERT:
208 return V_028808_ROP3_INVERT;
209 case VK_LOGIC_OP_OR_REVERSE:
210 return V_028808_ROP3_OR_REVERSE;
211 case VK_LOGIC_OP_COPY_INVERTED:
212 return V_028808_ROP3_COPY_INVERTED;
213 case VK_LOGIC_OP_OR_INVERTED:
214 return V_028808_ROP3_OR_INVERTED;
215 case VK_LOGIC_OP_NAND:
216 return V_028808_ROP3_NAND;
217 case VK_LOGIC_OP_SET:
218 return V_028808_ROP3_SET;
219 default:
220 unreachable("Unhandled logic op");
221 }
222 }
223
224
225 static uint32_t si_translate_blend_function(VkBlendOp op)
226 {
227 switch (op) {
228 case VK_BLEND_OP_ADD:
229 return V_028780_COMB_DST_PLUS_SRC;
230 case VK_BLEND_OP_SUBTRACT:
231 return V_028780_COMB_SRC_MINUS_DST;
232 case VK_BLEND_OP_REVERSE_SUBTRACT:
233 return V_028780_COMB_DST_MINUS_SRC;
234 case VK_BLEND_OP_MIN:
235 return V_028780_COMB_MIN_DST_SRC;
236 case VK_BLEND_OP_MAX:
237 return V_028780_COMB_MAX_DST_SRC;
238 default:
239 return 0;
240 }
241 }
242
243 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
244 {
245 switch (factor) {
246 case VK_BLEND_FACTOR_ZERO:
247 return V_028780_BLEND_ZERO;
248 case VK_BLEND_FACTOR_ONE:
249 return V_028780_BLEND_ONE;
250 case VK_BLEND_FACTOR_SRC_COLOR:
251 return V_028780_BLEND_SRC_COLOR;
252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
254 case VK_BLEND_FACTOR_DST_COLOR:
255 return V_028780_BLEND_DST_COLOR;
256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
257 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
258 case VK_BLEND_FACTOR_SRC_ALPHA:
259 return V_028780_BLEND_SRC_ALPHA;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
262 case VK_BLEND_FACTOR_DST_ALPHA:
263 return V_028780_BLEND_DST_ALPHA;
264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
266 case VK_BLEND_FACTOR_CONSTANT_COLOR:
267 return V_028780_BLEND_CONSTANT_COLOR;
268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
270 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
271 return V_028780_BLEND_CONSTANT_ALPHA;
272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
275 return V_028780_BLEND_SRC_ALPHA_SATURATE;
276 case VK_BLEND_FACTOR_SRC1_COLOR:
277 return V_028780_BLEND_SRC1_COLOR;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
279 return V_028780_BLEND_INV_SRC1_COLOR;
280 case VK_BLEND_FACTOR_SRC1_ALPHA:
281 return V_028780_BLEND_SRC1_ALPHA;
282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
283 return V_028780_BLEND_INV_SRC1_ALPHA;
284 default:
285 return 0;
286 }
287 }
288
289 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
290 {
291 switch (op) {
292 case VK_BLEND_OP_ADD:
293 return V_028760_OPT_COMB_ADD;
294 case VK_BLEND_OP_SUBTRACT:
295 return V_028760_OPT_COMB_SUBTRACT;
296 case VK_BLEND_OP_REVERSE_SUBTRACT:
297 return V_028760_OPT_COMB_REVSUBTRACT;
298 case VK_BLEND_OP_MIN:
299 return V_028760_OPT_COMB_MIN;
300 case VK_BLEND_OP_MAX:
301 return V_028760_OPT_COMB_MAX;
302 default:
303 return V_028760_OPT_COMB_BLEND_DISABLED;
304 }
305 }
306
307 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
308 {
309 switch (factor) {
310 case VK_BLEND_FACTOR_ZERO:
311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
312 case VK_BLEND_FACTOR_ONE:
313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
314 case VK_BLEND_FACTOR_SRC_COLOR:
315 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
318 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
320 case VK_BLEND_FACTOR_SRC_ALPHA:
321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
327 default:
328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
329 }
330 }
331
332 /**
333 * Get rid of DST in the blend factors by commuting the operands:
334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
335 */
336 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
337 unsigned *dst_factor, unsigned expected_dst,
338 unsigned replacement_src)
339 {
340 if (*src_factor == expected_dst &&
341 *dst_factor == VK_BLEND_FACTOR_ZERO) {
342 *src_factor = VK_BLEND_FACTOR_ZERO;
343 *dst_factor = replacement_src;
344
345 /* Commuting the operands requires reversing subtractions. */
346 if (*func == VK_BLEND_OP_SUBTRACT)
347 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
348 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
349 *func = VK_BLEND_OP_SUBTRACT;
350 }
351 }
352
353 static bool si_blend_factor_uses_dst(unsigned factor)
354 {
355 return factor == VK_BLEND_FACTOR_DST_COLOR ||
356 factor == VK_BLEND_FACTOR_DST_ALPHA ||
357 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
358 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
359 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
360 }
361
362 static bool is_dual_src(VkBlendFactor factor)
363 {
364 switch (factor) {
365 case VK_BLEND_FACTOR_SRC1_COLOR:
366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
367 case VK_BLEND_FACTOR_SRC1_ALPHA:
368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
369 return true;
370 default:
371 return false;
372 }
373 }
374
375 static unsigned si_choose_spi_color_format(VkFormat vk_format,
376 bool blend_enable,
377 bool blend_need_alpha)
378 {
379 const struct vk_format_description *desc = vk_format_description(vk_format);
380 unsigned format, ntype, swap;
381
382 /* Alpha is needed for alpha-to-coverage.
383 * Blending may be with or without alpha.
384 */
385 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
386 unsigned alpha = 0; /* exports alpha, but may not support blending */
387 unsigned blend = 0; /* supports blending, but may not export alpha */
388 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
389
390 format = radv_translate_colorformat(vk_format);
391 ntype = radv_translate_color_numformat(vk_format, desc,
392 vk_format_get_first_non_void_channel(vk_format));
393 swap = radv_translate_colorswap(vk_format, false);
394
395 /* Choose the SPI color formats. These are required values for Stoney/RB+.
396 * Other chips have multiple choices, though they are not necessarily better.
397 */
398 switch (format) {
399 case V_028C70_COLOR_5_6_5:
400 case V_028C70_COLOR_1_5_5_5:
401 case V_028C70_COLOR_5_5_5_1:
402 case V_028C70_COLOR_4_4_4_4:
403 case V_028C70_COLOR_10_11_11:
404 case V_028C70_COLOR_11_11_10:
405 case V_028C70_COLOR_8:
406 case V_028C70_COLOR_8_8:
407 case V_028C70_COLOR_8_8_8_8:
408 case V_028C70_COLOR_10_10_10_2:
409 case V_028C70_COLOR_2_10_10_10:
410 if (ntype == V_028C70_NUMBER_UINT)
411 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
412 else if (ntype == V_028C70_NUMBER_SINT)
413 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
414 else
415 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
416 break;
417
418 case V_028C70_COLOR_16:
419 case V_028C70_COLOR_16_16:
420 case V_028C70_COLOR_16_16_16_16:
421 if (ntype == V_028C70_NUMBER_UNORM ||
422 ntype == V_028C70_NUMBER_SNORM) {
423 /* UNORM16 and SNORM16 don't support blending */
424 if (ntype == V_028C70_NUMBER_UNORM)
425 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
426 else
427 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
428
429 /* Use 32 bits per channel for blending. */
430 if (format == V_028C70_COLOR_16) {
431 if (swap == V_028C70_SWAP_STD) { /* R */
432 blend = V_028714_SPI_SHADER_32_R;
433 blend_alpha = V_028714_SPI_SHADER_32_AR;
434 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
435 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
436 else
437 assert(0);
438 } else if (format == V_028C70_COLOR_16_16) {
439 if (swap == V_028C70_SWAP_STD) { /* RG */
440 blend = V_028714_SPI_SHADER_32_GR;
441 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
442 } else if (swap == V_028C70_SWAP_ALT) /* RA */
443 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
444 else
445 assert(0);
446 } else /* 16_16_16_16 */
447 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
448 } else if (ntype == V_028C70_NUMBER_UINT)
449 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
450 else if (ntype == V_028C70_NUMBER_SINT)
451 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
452 else if (ntype == V_028C70_NUMBER_FLOAT)
453 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
454 else
455 assert(0);
456 break;
457
458 case V_028C70_COLOR_32:
459 if (swap == V_028C70_SWAP_STD) { /* R */
460 blend = normal = V_028714_SPI_SHADER_32_R;
461 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
462 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
463 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
464 else
465 assert(0);
466 break;
467
468 case V_028C70_COLOR_32_32:
469 if (swap == V_028C70_SWAP_STD) { /* RG */
470 blend = normal = V_028714_SPI_SHADER_32_GR;
471 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
472 } else if (swap == V_028C70_SWAP_ALT) /* RA */
473 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
474 else
475 assert(0);
476 break;
477
478 case V_028C70_COLOR_32_32_32_32:
479 case V_028C70_COLOR_8_24:
480 case V_028C70_COLOR_24_8:
481 case V_028C70_COLOR_X24_8_32_FLOAT:
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
483 break;
484
485 default:
486 unreachable("unhandled blend format");
487 }
488
489 if (blend_enable && blend_need_alpha)
490 return blend_alpha;
491 else if(blend_need_alpha)
492 return alpha;
493 else if(blend_enable)
494 return blend;
495 else
496 return normal;
497 }
498
499 static void
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
502 struct radv_blend_state *blend)
503 {
504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
506 unsigned col_format = 0;
507
508 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
509 unsigned cf;
510
511 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
512 cf = V_028714_SPI_SHADER_ZERO;
513 } else {
514 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
515 bool blend_enable =
516 blend->blend_enable_4bit & (0xfu << (i * 4));
517
518 cf = si_choose_spi_color_format(attachment->format,
519 blend_enable,
520 blend->need_src_alpha & (1 << i));
521 }
522
523 col_format |= cf << (4 * i);
524 }
525
526 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
527
528 if (blend->mrt0_is_dual_src)
529 col_format |= (col_format & 0xf) << 4;
530 blend->spi_shader_col_format = col_format;
531 }
532
533 static bool
534 format_is_int8(VkFormat format)
535 {
536 const struct vk_format_description *desc = vk_format_description(format);
537 int channel = vk_format_get_first_non_void_channel(format);
538
539 return channel >= 0 && desc->channel[channel].pure_integer &&
540 desc->channel[channel].size == 8;
541 }
542
543 static bool
544 format_is_int10(VkFormat format)
545 {
546 const struct vk_format_description *desc = vk_format_description(format);
547
548 if (desc->nr_channels != 4)
549 return false;
550 for (unsigned i = 0; i < 4; i++) {
551 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
552 return true;
553 }
554 return false;
555 }
556
557 unsigned radv_format_meta_fs_key(VkFormat format)
558 {
559 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
560 bool is_int8 = format_is_int8(format);
561 bool is_int10 = format_is_int10(format);
562
563 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
564 }
565
566 static void
567 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
568 unsigned *is_int8, unsigned *is_int10)
569 {
570 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
571 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
572 *is_int8 = 0;
573 *is_int10 = 0;
574
575 for (unsigned i = 0; i < subpass->color_count; ++i) {
576 struct radv_render_pass_attachment *attachment;
577
578 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
579 continue;
580
581 attachment = pass->attachments + subpass->color_attachments[i].attachment;
582
583 if (format_is_int8(attachment->format))
584 *is_int8 |= 1 << i;
585 if (format_is_int10(attachment->format))
586 *is_int10 |= 1 << i;
587 }
588 }
589
590 static void
591 radv_blend_check_commutativity(struct radv_blend_state *blend,
592 VkBlendOp op, VkBlendFactor src,
593 VkBlendFactor dst, unsigned chanmask)
594 {
595 /* Src factor is allowed when it does not depend on Dst. */
596 static const uint32_t src_allowed =
597 (1u << VK_BLEND_FACTOR_ONE) |
598 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
599 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
600 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
601 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
602 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
603 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
604 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
605 (1u << VK_BLEND_FACTOR_ZERO) |
606 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
607 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
608 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
609 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
610 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
611 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
612
613 if (dst == VK_BLEND_FACTOR_ONE &&
614 (src_allowed && (1u << src))) {
615 /* Addition is commutative, but floating point addition isn't
616 * associative: subtle changes can be introduced via different
617 * rounding. Be conservative, only enable for min and max.
618 */
619 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
620 blend->commutative_4bit |= chanmask;
621 }
622 }
623
624 static struct radv_blend_state
625 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
626 const VkGraphicsPipelineCreateInfo *pCreateInfo,
627 const struct radv_graphics_pipeline_create_info *extra)
628 {
629 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
630 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
631 struct radv_blend_state blend = {0};
632 unsigned mode = V_028808_CB_NORMAL;
633 int i;
634
635 if (!vkblend)
636 return blend;
637
638 if (extra && extra->custom_blend_mode) {
639 blend.single_cb_enable = true;
640 mode = extra->custom_blend_mode;
641 }
642 blend.cb_color_control = 0;
643 if (vkblend->logicOpEnable)
644 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
645 else
646 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
647
648 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
649 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
650 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
651 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
652
653 if (vkms && vkms->alphaToCoverageEnable) {
654 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
655 }
656
657 blend.cb_target_mask = 0;
658 for (i = 0; i < vkblend->attachmentCount; i++) {
659 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
660 unsigned blend_cntl = 0;
661 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
662 VkBlendOp eqRGB = att->colorBlendOp;
663 VkBlendFactor srcRGB = att->srcColorBlendFactor;
664 VkBlendFactor dstRGB = att->dstColorBlendFactor;
665 VkBlendOp eqA = att->alphaBlendOp;
666 VkBlendFactor srcA = att->srcAlphaBlendFactor;
667 VkBlendFactor dstA = att->dstAlphaBlendFactor;
668
669 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
670
671 if (!att->colorWriteMask)
672 continue;
673
674 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
675 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
676 if (!att->blendEnable) {
677 blend.cb_blend_control[i] = blend_cntl;
678 continue;
679 }
680
681 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
682 if (i == 0)
683 blend.mrt0_is_dual_src = true;
684
685 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
686 srcRGB = VK_BLEND_FACTOR_ONE;
687 dstRGB = VK_BLEND_FACTOR_ONE;
688 }
689 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
690 srcA = VK_BLEND_FACTOR_ONE;
691 dstA = VK_BLEND_FACTOR_ONE;
692 }
693
694 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
695 0x7 << (4 * i));
696 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
697 0x8 << (4 * i));
698
699 /* Blending optimizations for RB+.
700 * These transformations don't change the behavior.
701 *
702 * First, get rid of DST in the blend factors:
703 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
704 */
705 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
706 VK_BLEND_FACTOR_DST_COLOR,
707 VK_BLEND_FACTOR_SRC_COLOR);
708
709 si_blend_remove_dst(&eqA, &srcA, &dstA,
710 VK_BLEND_FACTOR_DST_COLOR,
711 VK_BLEND_FACTOR_SRC_COLOR);
712
713 si_blend_remove_dst(&eqA, &srcA, &dstA,
714 VK_BLEND_FACTOR_DST_ALPHA,
715 VK_BLEND_FACTOR_SRC_ALPHA);
716
717 /* Look up the ideal settings from tables. */
718 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
719 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
720 srcA_opt = si_translate_blend_opt_factor(srcA, true);
721 dstA_opt = si_translate_blend_opt_factor(dstA, true);
722
723 /* Handle interdependencies. */
724 if (si_blend_factor_uses_dst(srcRGB))
725 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
726 if (si_blend_factor_uses_dst(srcA))
727 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
728
729 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
730 (dstRGB == VK_BLEND_FACTOR_ZERO ||
731 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
732 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
733 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
734
735 /* Set the final value. */
736 blend.sx_mrt_blend_opt[i] =
737 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
738 S_028760_COLOR_DST_OPT(dstRGB_opt) |
739 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
740 S_028760_ALPHA_SRC_OPT(srcA_opt) |
741 S_028760_ALPHA_DST_OPT(dstA_opt) |
742 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
743 blend_cntl |= S_028780_ENABLE(1);
744
745 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
746 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
747 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
748 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
749 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
750 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
751 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
752 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
753 }
754 blend.cb_blend_control[i] = blend_cntl;
755
756 blend.blend_enable_4bit |= 0xfu << (i * 4);
757
758 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
759 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
760 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
761 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
762 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
763 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
764 blend.need_src_alpha |= 1 << i;
765 }
766 for (i = vkblend->attachmentCount; i < 8; i++) {
767 blend.cb_blend_control[i] = 0;
768 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
769 }
770
771 if (pipeline->device->physical_device->has_rbplus) {
772 /* Disable RB+ blend optimizations for dual source blending. */
773 if (blend.mrt0_is_dual_src) {
774 for (i = 0; i < 8; i++) {
775 blend.sx_mrt_blend_opt[i] =
776 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
777 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
778 }
779 }
780
781 /* RB+ doesn't work with dual source blending, logic op and
782 * RESOLVE.
783 */
784 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
785 mode == V_028808_CB_RESOLVE)
786 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
787 }
788
789 if (blend.cb_target_mask)
790 blend.cb_color_control |= S_028808_MODE(mode);
791 else
792 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
793
794 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
795 return blend;
796 }
797
798 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
799 {
800 switch (op) {
801 case VK_STENCIL_OP_KEEP:
802 return V_02842C_STENCIL_KEEP;
803 case VK_STENCIL_OP_ZERO:
804 return V_02842C_STENCIL_ZERO;
805 case VK_STENCIL_OP_REPLACE:
806 return V_02842C_STENCIL_REPLACE_TEST;
807 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
808 return V_02842C_STENCIL_ADD_CLAMP;
809 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
810 return V_02842C_STENCIL_SUB_CLAMP;
811 case VK_STENCIL_OP_INVERT:
812 return V_02842C_STENCIL_INVERT;
813 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
814 return V_02842C_STENCIL_ADD_WRAP;
815 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
816 return V_02842C_STENCIL_SUB_WRAP;
817 default:
818 return 0;
819 }
820 }
821
822 static uint32_t si_translate_fill(VkPolygonMode func)
823 {
824 switch(func) {
825 case VK_POLYGON_MODE_FILL:
826 return V_028814_X_DRAW_TRIANGLES;
827 case VK_POLYGON_MODE_LINE:
828 return V_028814_X_DRAW_LINES;
829 case VK_POLYGON_MODE_POINT:
830 return V_028814_X_DRAW_POINTS;
831 default:
832 assert(0);
833 return V_028814_X_DRAW_POINTS;
834 }
835 }
836
837 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
838 {
839 uint32_t num_samples = vkms->rasterizationSamples;
840 uint32_t ps_iter_samples = 1;
841
842 if (vkms->sampleShadingEnable) {
843 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
844 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
845 }
846 return ps_iter_samples;
847 }
848
849 static bool
850 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
851 {
852 return pCreateInfo->depthTestEnable &&
853 pCreateInfo->depthWriteEnable &&
854 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
855 }
856
857 static bool
858 radv_writes_stencil(const VkStencilOpState *state)
859 {
860 return state->writeMask &&
861 (state->failOp != VK_STENCIL_OP_KEEP ||
862 state->passOp != VK_STENCIL_OP_KEEP ||
863 state->depthFailOp != VK_STENCIL_OP_KEEP);
864 }
865
866 static bool
867 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
868 {
869 return pCreateInfo->stencilTestEnable &&
870 (radv_writes_stencil(&pCreateInfo->front) ||
871 radv_writes_stencil(&pCreateInfo->back));
872 }
873
874 static bool
875 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
876 {
877 return radv_is_depth_write_enabled(pCreateInfo) ||
878 radv_is_stencil_write_enabled(pCreateInfo);
879 }
880
881 static bool
882 radv_order_invariant_stencil_op(VkStencilOp op)
883 {
884 /* REPLACE is normally order invariant, except when the stencil
885 * reference value is written by the fragment shader. Tracking this
886 * interaction does not seem worth the effort, so be conservative.
887 */
888 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
889 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
890 op != VK_STENCIL_OP_REPLACE;
891 }
892
893 static bool
894 radv_order_invariant_stencil_state(const VkStencilOpState *state)
895 {
896 /* Compute whether, assuming Z writes are disabled, this stencil state
897 * is order invariant in the sense that the set of passing fragments as
898 * well as the final stencil buffer result does not depend on the order
899 * of fragments.
900 */
901 return !state->writeMask ||
902 /* The following assumes that Z writes are disabled. */
903 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
904 radv_order_invariant_stencil_op(state->passOp) &&
905 radv_order_invariant_stencil_op(state->depthFailOp)) ||
906 (state->compareOp == VK_COMPARE_OP_NEVER &&
907 radv_order_invariant_stencil_op(state->failOp));
908 }
909
910 static bool
911 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
912 struct radv_blend_state *blend,
913 const VkGraphicsPipelineCreateInfo *pCreateInfo)
914 {
915 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
916 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
917 unsigned colormask = blend->cb_target_enabled_4bit;
918
919 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
920 return false;
921
922 /* Be conservative if a logic operation is enabled with color buffers. */
923 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
924 return false;
925
926 /* Default depth/stencil invariance when no attachment is bound. */
927 struct radv_dsa_order_invariance dsa_order_invariant = {
928 .zs = true, .pass_set = true
929 };
930
931 if (pCreateInfo->pDepthStencilState &&
932 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
933 const VkPipelineDepthStencilStateCreateInfo *vkds =
934 pCreateInfo->pDepthStencilState;
935 struct radv_render_pass_attachment *attachment =
936 pass->attachments + subpass->depth_stencil_attachment.attachment;
937 bool has_stencil = vk_format_is_stencil(attachment->format);
938 struct radv_dsa_order_invariance order_invariance[2];
939 struct radv_shader_variant *ps =
940 pipeline->shaders[MESA_SHADER_FRAGMENT];
941
942 /* Compute depth/stencil order invariance in order to know if
943 * it's safe to enable out-of-order.
944 */
945 bool zfunc_is_ordered =
946 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
947 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
948 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
949 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
950 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
951
952 bool nozwrite_and_order_invariant_stencil =
953 !radv_is_ds_write_enabled(vkds) ||
954 (!radv_is_depth_write_enabled(vkds) &&
955 radv_order_invariant_stencil_state(&vkds->front) &&
956 radv_order_invariant_stencil_state(&vkds->back));
957
958 order_invariance[1].zs =
959 nozwrite_and_order_invariant_stencil ||
960 (!radv_is_stencil_write_enabled(vkds) &&
961 zfunc_is_ordered);
962 order_invariance[0].zs =
963 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
964
965 order_invariance[1].pass_set =
966 nozwrite_and_order_invariant_stencil ||
967 (!radv_is_stencil_write_enabled(vkds) &&
968 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
969 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
970 order_invariance[0].pass_set =
971 !radv_is_depth_write_enabled(vkds) ||
972 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
973 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
974
975 dsa_order_invariant = order_invariance[has_stencil];
976 if (!dsa_order_invariant.zs)
977 return false;
978
979 /* The set of PS invocations is always order invariant,
980 * except when early Z/S tests are requested.
981 */
982 if (ps &&
983 ps->info.info.ps.writes_memory &&
984 ps->info.fs.early_fragment_test &&
985 !dsa_order_invariant.pass_set)
986 return false;
987
988 /* Determine if out-of-order rasterization should be disabled
989 * when occlusion queries are used.
990 */
991 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
992 !dsa_order_invariant.pass_set;
993 }
994
995 /* No color buffers are enabled for writing. */
996 if (!colormask)
997 return true;
998
999 unsigned blendmask = colormask & blend->blend_enable_4bit;
1000
1001 if (blendmask) {
1002 /* Only commutative blending. */
1003 if (blendmask & ~blend->commutative_4bit)
1004 return false;
1005
1006 if (!dsa_order_invariant.pass_set)
1007 return false;
1008 }
1009
1010 if (colormask & ~blendmask)
1011 return false;
1012
1013 return true;
1014 }
1015
1016 static void
1017 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1018 struct radv_blend_state *blend,
1019 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1020 {
1021 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1022 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1023 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1024 bool out_of_order_rast = false;
1025 int ps_iter_samples = 1;
1026 uint32_t mask = 0xffff;
1027
1028 if (vkms)
1029 ms->num_samples = vkms->rasterizationSamples;
1030 else
1031 ms->num_samples = 1;
1032
1033 if (vkms)
1034 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1035 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1036 ps_iter_samples = ms->num_samples;
1037 }
1038
1039 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1040 ms->pa_sc_aa_config = 0;
1041 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1042 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1043 ms->pa_sc_mode_cntl_1 =
1044 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1045 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1046 /* always 1: */
1047 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1048 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1049 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1050 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1051 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1052 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1053 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1054 S_028A48_VPORT_SCISSOR_ENABLE(1);
1055
1056 if (ms->num_samples > 1) {
1057 unsigned log_samples = util_logbase2(ms->num_samples);
1058 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1059 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1060 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1061 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1062 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1063 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1064 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1065 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1066 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1067 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1068 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1069 if (ps_iter_samples > 1)
1070 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1071 }
1072
1073 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1074 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1075 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1076 /* Out-of-order rasterization is explicitly enabled by the
1077 * application.
1078 */
1079 out_of_order_rast = true;
1080 } else {
1081 /* Determine if the driver can enable out-of-order
1082 * rasterization internally.
1083 */
1084 out_of_order_rast =
1085 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1086 }
1087
1088 if (out_of_order_rast) {
1089 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1090 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1091 }
1092
1093 if (vkms && vkms->pSampleMask) {
1094 mask = vkms->pSampleMask[0] & 0xffff;
1095 }
1096
1097 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1098 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1099 }
1100
1101 static bool
1102 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1103 {
1104 switch (topology) {
1105 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1106 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1107 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1108 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1109 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1110 return false;
1111 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1112 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1113 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1114 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1115 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1116 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1117 return true;
1118 default:
1119 unreachable("unhandled primitive type");
1120 }
1121 }
1122
1123 static uint32_t
1124 si_translate_prim(enum VkPrimitiveTopology topology)
1125 {
1126 switch (topology) {
1127 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1128 return V_008958_DI_PT_POINTLIST;
1129 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1130 return V_008958_DI_PT_LINELIST;
1131 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1132 return V_008958_DI_PT_LINESTRIP;
1133 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1134 return V_008958_DI_PT_TRILIST;
1135 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1136 return V_008958_DI_PT_TRISTRIP;
1137 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1138 return V_008958_DI_PT_TRIFAN;
1139 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1140 return V_008958_DI_PT_LINELIST_ADJ;
1141 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1142 return V_008958_DI_PT_LINESTRIP_ADJ;
1143 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1144 return V_008958_DI_PT_TRILIST_ADJ;
1145 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1146 return V_008958_DI_PT_TRISTRIP_ADJ;
1147 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1148 return V_008958_DI_PT_PATCH;
1149 default:
1150 assert(0);
1151 return 0;
1152 }
1153 }
1154
1155 static uint32_t
1156 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1157 {
1158 switch (gl_prim) {
1159 case 0: /* GL_POINTS */
1160 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1161 case 1: /* GL_LINES */
1162 case 3: /* GL_LINE_STRIP */
1163 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1164 case 0x8E7A: /* GL_ISOLINES */
1165 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1166
1167 case 4: /* GL_TRIANGLES */
1168 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1169 case 5: /* GL_TRIANGLE_STRIP */
1170 case 7: /* GL_QUADS */
1171 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1172 default:
1173 assert(0);
1174 return 0;
1175 }
1176 }
1177
1178 static uint32_t
1179 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1180 {
1181 switch (topology) {
1182 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1183 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1184 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1189 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1195 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1196 default:
1197 assert(0);
1198 return 0;
1199 }
1200 }
1201
1202 static unsigned si_map_swizzle(unsigned swizzle)
1203 {
1204 switch (swizzle) {
1205 case VK_SWIZZLE_Y:
1206 return V_008F0C_SQ_SEL_Y;
1207 case VK_SWIZZLE_Z:
1208 return V_008F0C_SQ_SEL_Z;
1209 case VK_SWIZZLE_W:
1210 return V_008F0C_SQ_SEL_W;
1211 case VK_SWIZZLE_0:
1212 return V_008F0C_SQ_SEL_0;
1213 case VK_SWIZZLE_1:
1214 return V_008F0C_SQ_SEL_1;
1215 default: /* VK_SWIZZLE_X */
1216 return V_008F0C_SQ_SEL_X;
1217 }
1218 }
1219
1220
1221 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1222 {
1223 switch(state) {
1224 case VK_DYNAMIC_STATE_VIEWPORT:
1225 return RADV_DYNAMIC_VIEWPORT;
1226 case VK_DYNAMIC_STATE_SCISSOR:
1227 return RADV_DYNAMIC_SCISSOR;
1228 case VK_DYNAMIC_STATE_LINE_WIDTH:
1229 return RADV_DYNAMIC_LINE_WIDTH;
1230 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1231 return RADV_DYNAMIC_DEPTH_BIAS;
1232 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1233 return RADV_DYNAMIC_BLEND_CONSTANTS;
1234 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1235 return RADV_DYNAMIC_DEPTH_BOUNDS;
1236 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1237 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1238 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1239 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1240 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1241 return RADV_DYNAMIC_STENCIL_REFERENCE;
1242 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1243 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1244 default:
1245 unreachable("Unhandled dynamic state");
1246 }
1247 }
1248
1249 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1250 {
1251 uint32_t states = RADV_DYNAMIC_ALL;
1252
1253 /* If rasterization is disabled we do not care about any of the dynamic states,
1254 * since they are all rasterization related only. */
1255 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1256 return 0;
1257
1258 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1259 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1260
1261 if (!pCreateInfo->pDepthStencilState ||
1262 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1263 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1264
1265 if (!pCreateInfo->pDepthStencilState ||
1266 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1267 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1268 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1269 RADV_DYNAMIC_STENCIL_REFERENCE);
1270
1271 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1272 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1273
1274 /* TODO: blend constants & line width. */
1275
1276 return states;
1277 }
1278
1279
1280 static void
1281 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1282 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1283 {
1284 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1285 uint32_t states = needed_states;
1286 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1287 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1288
1289 pipeline->dynamic_state = default_dynamic_state;
1290 pipeline->graphics.needed_dynamic_state = needed_states;
1291
1292 if (pCreateInfo->pDynamicState) {
1293 /* Remove all of the states that are marked as dynamic */
1294 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1295 for (uint32_t s = 0; s < count; s++)
1296 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1297 }
1298
1299 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1300
1301 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1302 assert(pCreateInfo->pViewportState);
1303
1304 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1305 if (states & RADV_DYNAMIC_VIEWPORT) {
1306 typed_memcpy(dynamic->viewport.viewports,
1307 pCreateInfo->pViewportState->pViewports,
1308 pCreateInfo->pViewportState->viewportCount);
1309 }
1310 }
1311
1312 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1313 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1314 if (states & RADV_DYNAMIC_SCISSOR) {
1315 typed_memcpy(dynamic->scissor.scissors,
1316 pCreateInfo->pViewportState->pScissors,
1317 pCreateInfo->pViewportState->scissorCount);
1318 }
1319 }
1320
1321 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1322 assert(pCreateInfo->pRasterizationState);
1323 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1324 }
1325
1326 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1327 assert(pCreateInfo->pRasterizationState);
1328 dynamic->depth_bias.bias =
1329 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1330 dynamic->depth_bias.clamp =
1331 pCreateInfo->pRasterizationState->depthBiasClamp;
1332 dynamic->depth_bias.slope =
1333 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1334 }
1335
1336 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1337 *
1338 * pColorBlendState is [...] NULL if the pipeline has rasterization
1339 * disabled or if the subpass of the render pass the pipeline is
1340 * created against does not use any color attachments.
1341 */
1342 bool uses_color_att = false;
1343 for (unsigned i = 0; i < subpass->color_count; ++i) {
1344 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1345 uses_color_att = true;
1346 break;
1347 }
1348 }
1349
1350 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1351 assert(pCreateInfo->pColorBlendState);
1352 typed_memcpy(dynamic->blend_constants,
1353 pCreateInfo->pColorBlendState->blendConstants, 4);
1354 }
1355
1356 /* If there is no depthstencil attachment, then don't read
1357 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1358 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1359 * no need to override the depthstencil defaults in
1360 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1361 *
1362 * Section 9.2 of the Vulkan 1.0.15 spec says:
1363 *
1364 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1365 * disabled or if the subpass of the render pass the pipeline is created
1366 * against does not use a depth/stencil attachment.
1367 */
1368 if (needed_states &&
1369 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1370 assert(pCreateInfo->pDepthStencilState);
1371
1372 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1373 dynamic->depth_bounds.min =
1374 pCreateInfo->pDepthStencilState->minDepthBounds;
1375 dynamic->depth_bounds.max =
1376 pCreateInfo->pDepthStencilState->maxDepthBounds;
1377 }
1378
1379 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1380 dynamic->stencil_compare_mask.front =
1381 pCreateInfo->pDepthStencilState->front.compareMask;
1382 dynamic->stencil_compare_mask.back =
1383 pCreateInfo->pDepthStencilState->back.compareMask;
1384 }
1385
1386 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1387 dynamic->stencil_write_mask.front =
1388 pCreateInfo->pDepthStencilState->front.writeMask;
1389 dynamic->stencil_write_mask.back =
1390 pCreateInfo->pDepthStencilState->back.writeMask;
1391 }
1392
1393 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1394 dynamic->stencil_reference.front =
1395 pCreateInfo->pDepthStencilState->front.reference;
1396 dynamic->stencil_reference.back =
1397 pCreateInfo->pDepthStencilState->back.reference;
1398 }
1399 }
1400
1401 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1402 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1403 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1404 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1405 typed_memcpy(dynamic->discard_rectangle.rectangles,
1406 discard_rectangle_info->pDiscardRectangles,
1407 discard_rectangle_info->discardRectangleCount);
1408 }
1409
1410 pipeline->dynamic_state.mask = states;
1411 }
1412
1413 static struct radv_gs_state
1414 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1415 const struct radv_pipeline *pipeline)
1416 {
1417 struct radv_gs_state gs = {0};
1418 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1419 struct radv_es_output_info *es_info;
1420 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1421 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1422 else
1423 es_info = radv_pipeline_has_tess(pipeline) ?
1424 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1425 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1426
1427 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1428 bool uses_adjacency;
1429 switch(pCreateInfo->pInputAssemblyState->topology) {
1430 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1431 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1432 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1433 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1434 uses_adjacency = true;
1435 break;
1436 default:
1437 uses_adjacency = false;
1438 break;
1439 }
1440
1441 /* All these are in dwords: */
1442 /* We can't allow using the whole LDS, because GS waves compete with
1443 * other shader stages for LDS space. */
1444 const unsigned max_lds_size = 8 * 1024;
1445 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1446 unsigned esgs_lds_size;
1447
1448 /* All these are per subgroup: */
1449 const unsigned max_out_prims = 32 * 1024;
1450 const unsigned max_es_verts = 255;
1451 const unsigned ideal_gs_prims = 64;
1452 unsigned max_gs_prims, gs_prims;
1453 unsigned min_es_verts, es_verts, worst_case_es_verts;
1454
1455 if (uses_adjacency || gs_num_invocations > 1)
1456 max_gs_prims = 127 / gs_num_invocations;
1457 else
1458 max_gs_prims = 255;
1459
1460 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1461 * Make sure we don't go over the maximum value.
1462 */
1463 if (gs_info->gs.vertices_out > 0) {
1464 max_gs_prims = MIN2(max_gs_prims,
1465 max_out_prims /
1466 (gs_info->gs.vertices_out * gs_num_invocations));
1467 }
1468 assert(max_gs_prims > 0);
1469
1470 /* If the primitive has adjacency, halve the number of vertices
1471 * that will be reused in multiple primitives.
1472 */
1473 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1474
1475 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1476 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1477
1478 /* Compute ESGS LDS size based on the worst case number of ES vertices
1479 * needed to create the target number of GS prims per subgroup.
1480 */
1481 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1482
1483 /* If total LDS usage is too big, refactor partitions based on ratio
1484 * of ESGS item sizes.
1485 */
1486 if (esgs_lds_size > max_lds_size) {
1487 /* Our target GS Prims Per Subgroup was too large. Calculate
1488 * the maximum number of GS Prims Per Subgroup that will fit
1489 * into LDS, capped by the maximum that the hardware can support.
1490 */
1491 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1492 max_gs_prims);
1493 assert(gs_prims > 0);
1494 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1495 max_es_verts);
1496
1497 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1498 assert(esgs_lds_size <= max_lds_size);
1499 }
1500
1501 /* Now calculate remaining ESGS information. */
1502 if (esgs_lds_size)
1503 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1504 else
1505 es_verts = max_es_verts;
1506
1507 /* Vertices for adjacency primitives are not always reused, so restore
1508 * it for ES_VERTS_PER_SUBGRP.
1509 */
1510 min_es_verts = gs_info->gs.vertices_in;
1511
1512 /* For normal primitives, the VGT only checks if they are past the ES
1513 * verts per subgroup after allocating a full GS primitive and if they
1514 * are, kick off a new subgroup. But if those additional ES verts are
1515 * unique (e.g. not reused) we need to make sure there is enough LDS
1516 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1517 */
1518 es_verts -= min_es_verts - 1;
1519
1520 uint32_t es_verts_per_subgroup = es_verts;
1521 uint32_t gs_prims_per_subgroup = gs_prims;
1522 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1523 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1524 gs.lds_size = align(esgs_lds_size, 128) / 128;
1525 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1526 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1527 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1528 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1529 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1530 assert(max_prims_per_subgroup <= max_out_prims);
1531
1532 return gs;
1533 }
1534
1535 static void
1536 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1537 {
1538 struct radv_device *device = pipeline->device;
1539 unsigned num_se = device->physical_device->rad_info.max_se;
1540 unsigned wave_size = 64;
1541 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1542 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1543 unsigned alignment = 256 * num_se;
1544 /* The maximum size is 63.999 MB per SE. */
1545 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1546 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1547
1548 /* Calculate the minimum size. */
1549 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1550 wave_size, alignment);
1551 /* These are recommended sizes, not minimum sizes. */
1552 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1553 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1554 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1555 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1556
1557 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1558 esgs_ring_size = align(esgs_ring_size, alignment);
1559 gsvs_ring_size = align(gsvs_ring_size, alignment);
1560
1561 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1562 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1563
1564 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1565 }
1566
1567 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1568 unsigned *lds_size)
1569 {
1570 /* If tessellation is all offchip and on-chip GS isn't used, this
1571 * workaround is not needed.
1572 */
1573 return;
1574
1575 /* SPI barrier management bug:
1576 * Make sure we have at least 4k of LDS in use to avoid the bug.
1577 * It applies to workgroup sizes of more than one wavefront.
1578 */
1579 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1580 device->physical_device->rad_info.family == CHIP_KABINI ||
1581 device->physical_device->rad_info.family == CHIP_MULLINS)
1582 *lds_size = MAX2(*lds_size, 8);
1583 }
1584
1585 struct radv_shader_variant *
1586 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1587 {
1588 if (pipeline->shaders[MESA_SHADER_VERTEX])
1589 return pipeline->shaders[MESA_SHADER_VERTEX];
1590 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1591 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1592 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1593 }
1594
1595 static struct radv_shader_variant *
1596 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1597 {
1598 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1599 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1600 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1601 }
1602
1603 static struct radv_tessellation_state
1604 calculate_tess_state(struct radv_pipeline *pipeline,
1605 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1606 {
1607 unsigned num_tcs_input_cp;
1608 unsigned num_tcs_output_cp;
1609 unsigned lds_size;
1610 unsigned num_patches;
1611 struct radv_tessellation_state tess = {0};
1612
1613 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1614 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1615 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1616
1617 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1618
1619 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1620 assert(lds_size <= 65536);
1621 lds_size = align(lds_size, 512) / 512;
1622 } else {
1623 assert(lds_size <= 32768);
1624 lds_size = align(lds_size, 256) / 256;
1625 }
1626 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1627
1628 tess.lds_size = lds_size;
1629
1630 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1631 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1632 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1633 tess.num_patches = num_patches;
1634
1635 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1636 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1637
1638 switch (tes->info.tes.primitive_mode) {
1639 case GL_TRIANGLES:
1640 type = V_028B6C_TESS_TRIANGLE;
1641 break;
1642 case GL_QUADS:
1643 type = V_028B6C_TESS_QUAD;
1644 break;
1645 case GL_ISOLINES:
1646 type = V_028B6C_TESS_ISOLINE;
1647 break;
1648 }
1649
1650 switch (tes->info.tes.spacing) {
1651 case TESS_SPACING_EQUAL:
1652 partitioning = V_028B6C_PART_INTEGER;
1653 break;
1654 case TESS_SPACING_FRACTIONAL_ODD:
1655 partitioning = V_028B6C_PART_FRAC_ODD;
1656 break;
1657 case TESS_SPACING_FRACTIONAL_EVEN:
1658 partitioning = V_028B6C_PART_FRAC_EVEN;
1659 break;
1660 default:
1661 break;
1662 }
1663
1664 bool ccw = tes->info.tes.ccw;
1665 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1666 vk_find_struct_const(pCreateInfo->pTessellationState,
1667 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1668
1669 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1670 ccw = !ccw;
1671
1672 if (tes->info.tes.point_mode)
1673 topology = V_028B6C_OUTPUT_POINT;
1674 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1675 topology = V_028B6C_OUTPUT_LINE;
1676 else if (ccw)
1677 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1678 else
1679 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1680
1681 if (pipeline->device->has_distributed_tess) {
1682 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1683 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1684 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1685 else
1686 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1687 } else
1688 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1689
1690 tess.tf_param = S_028B6C_TYPE(type) |
1691 S_028B6C_PARTITIONING(partitioning) |
1692 S_028B6C_TOPOLOGY(topology) |
1693 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1694
1695 return tess;
1696 }
1697
1698 static const struct radv_prim_vertex_count prim_size_table[] = {
1699 [V_008958_DI_PT_NONE] = {0, 0},
1700 [V_008958_DI_PT_POINTLIST] = {1, 1},
1701 [V_008958_DI_PT_LINELIST] = {2, 2},
1702 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1703 [V_008958_DI_PT_TRILIST] = {3, 3},
1704 [V_008958_DI_PT_TRIFAN] = {3, 1},
1705 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1706 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1707 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1708 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1709 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1710 [V_008958_DI_PT_RECTLIST] = {3, 3},
1711 [V_008958_DI_PT_LINELOOP] = {2, 1},
1712 [V_008958_DI_PT_POLYGON] = {3, 1},
1713 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1714 };
1715
1716 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1717 {
1718 if (radv_pipeline_has_gs(pipeline))
1719 return &pipeline->gs_copy_shader->info.vs.outinfo;
1720 else if (radv_pipeline_has_tess(pipeline))
1721 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1722 else
1723 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1724 }
1725
1726 static void
1727 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1728 {
1729 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1730 int shader_count = 0;
1731
1732 if(shaders[MESA_SHADER_FRAGMENT]) {
1733 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1734 }
1735 if(shaders[MESA_SHADER_GEOMETRY]) {
1736 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1737 }
1738 if(shaders[MESA_SHADER_TESS_EVAL]) {
1739 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1740 }
1741 if(shaders[MESA_SHADER_TESS_CTRL]) {
1742 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1743 }
1744 if(shaders[MESA_SHADER_VERTEX]) {
1745 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1746 }
1747
1748 for (int i = 1; i < shader_count; ++i) {
1749 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1750 ordered_shaders[i - 1]);
1751
1752 nir_remove_dead_variables(ordered_shaders[i],
1753 nir_var_shader_out);
1754 nir_remove_dead_variables(ordered_shaders[i - 1],
1755 nir_var_shader_in);
1756
1757 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1758 ordered_shaders[i - 1]);
1759
1760 nir_compact_varyings(ordered_shaders[i],
1761 ordered_shaders[i - 1], true);
1762
1763 if (progress) {
1764 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1765 ac_lower_indirect_derefs(ordered_shaders[i],
1766 pipeline->device->physical_device->rad_info.chip_class);
1767 }
1768 radv_optimize_nir(ordered_shaders[i], false);
1769
1770 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1771 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1772 pipeline->device->physical_device->rad_info.chip_class);
1773 }
1774 radv_optimize_nir(ordered_shaders[i - 1], false);
1775 }
1776 }
1777 }
1778
1779
1780 static struct radv_pipeline_key
1781 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1782 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1783 const struct radv_blend_state *blend,
1784 bool has_view_index)
1785 {
1786 const VkPipelineVertexInputStateCreateInfo *input_state =
1787 pCreateInfo->pVertexInputState;
1788 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
1789 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1790
1791 struct radv_pipeline_key key;
1792 memset(&key, 0, sizeof(key));
1793
1794 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
1795 key.optimisations_disabled = 1;
1796
1797 key.has_multiview_view_index = has_view_index;
1798
1799 uint32_t binding_input_rate = 0;
1800 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
1801 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1802 if (input_state->pVertexBindingDescriptions[i].inputRate) {
1803 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
1804 binding_input_rate |= 1u << binding;
1805 instance_rate_divisors[binding] = 1;
1806 }
1807 }
1808 if (divisor_state) {
1809 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
1810 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
1811 divisor_state->pVertexBindingDivisors[i].divisor;
1812 }
1813 }
1814
1815 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1816 unsigned location = input_state->pVertexAttributeDescriptions[i].location;
1817 unsigned binding = input_state->pVertexAttributeDescriptions[i].binding;
1818 if (binding_input_rate & (1u << binding)) {
1819 key.instance_rate_inputs |= 1u << location;
1820 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
1821 }
1822
1823 if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
1824 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
1825 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
1826 uint64_t adjust;
1827 switch(format) {
1828 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
1829 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
1830 adjust = RADV_ALPHA_ADJUST_SNORM;
1831 break;
1832 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
1833 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
1834 adjust = RADV_ALPHA_ADJUST_SSCALED;
1835 break;
1836 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
1837 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
1838 adjust = RADV_ALPHA_ADJUST_SINT;
1839 break;
1840 default:
1841 adjust = 0;
1842 break;
1843 }
1844 key.vertex_alpha_adjust |= adjust << (2 * location);
1845 }
1846 }
1847
1848 if (pCreateInfo->pTessellationState)
1849 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1850
1851
1852 if (pCreateInfo->pMultisampleState &&
1853 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1854 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1855 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1856 key.multisample = true;
1857 key.log2_num_samples = util_logbase2(num_samples);
1858 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1859 }
1860
1861 key.col_format = blend->spi_shader_col_format;
1862 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1863 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1864
1865 return key;
1866 }
1867
1868 static void
1869 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1870 const struct radv_pipeline_key *key,
1871 nir_shader **nir)
1872 {
1873 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1874 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
1875 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
1876 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
1877
1878 if (nir[MESA_SHADER_TESS_CTRL]) {
1879 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1880 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1881 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1882 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1883
1884 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1885 }
1886
1887 if (nir[MESA_SHADER_GEOMETRY]) {
1888 if (nir[MESA_SHADER_TESS_CTRL])
1889 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1890 else
1891 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1892 }
1893
1894 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1895 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1896
1897 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1898 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1899 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1900 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1901 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1902 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1903 }
1904
1905 static void
1906 merge_tess_info(struct shader_info *tes_info,
1907 const struct shader_info *tcs_info)
1908 {
1909 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1910 *
1911 * "PointMode. Controls generation of points rather than triangles
1912 * or lines. This functionality defaults to disabled, and is
1913 * enabled if either shader stage includes the execution mode.
1914 *
1915 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1916 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1917 * and OutputVertices, it says:
1918 *
1919 * "One mode must be set in at least one of the tessellation
1920 * shader stages."
1921 *
1922 * So, the fields can be set in either the TCS or TES, but they must
1923 * agree if set in both. Our backend looks at TES, so bitwise-or in
1924 * the values from the TCS.
1925 */
1926 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1927 tes_info->tess.tcs_vertices_out == 0 ||
1928 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1929 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1930
1931 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1932 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1933 tcs_info->tess.spacing == tes_info->tess.spacing);
1934 tes_info->tess.spacing |= tcs_info->tess.spacing;
1935
1936 assert(tcs_info->tess.primitive_mode == 0 ||
1937 tes_info->tess.primitive_mode == 0 ||
1938 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1939 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1940 tes_info->tess.ccw |= tcs_info->tess.ccw;
1941 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1942 }
1943
1944 static
1945 void radv_create_shaders(struct radv_pipeline *pipeline,
1946 struct radv_device *device,
1947 struct radv_pipeline_cache *cache,
1948 struct radv_pipeline_key key,
1949 const VkPipelineShaderStageCreateInfo **pStages,
1950 const VkPipelineCreateFlags flags)
1951 {
1952 struct radv_shader_module fs_m = {0};
1953 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1954 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1955 void *codes[MESA_SHADER_STAGES] = {0};
1956 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1957 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1958 unsigned char hash[20], gs_copy_hash[20];
1959
1960 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1961 if (pStages[i]) {
1962 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1963 if (modules[i]->nir)
1964 _mesa_sha1_compute(modules[i]->nir->info.name,
1965 strlen(modules[i]->nir->info.name),
1966 modules[i]->sha1);
1967 }
1968 }
1969
1970 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1971 memcpy(gs_copy_hash, hash, 20);
1972 gs_copy_hash[0] ^= 1;
1973
1974 if (modules[MESA_SHADER_GEOMETRY]) {
1975 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1976 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1977 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1978 }
1979
1980 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1981 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1982 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1983 if (pipeline->shaders[i])
1984 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1985 }
1986 return;
1987 }
1988
1989 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1990 nir_builder fs_b;
1991 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1992 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1993 fs_m.nir = fs_b.shader;
1994 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1995 }
1996
1997 /* Determine first and last stage. */
1998 unsigned first = MESA_SHADER_STAGES;
1999 unsigned last = 0;
2000 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2001 if (!pStages[i])
2002 continue;
2003 if (first == MESA_SHADER_STAGES)
2004 first = i;
2005 last = i;
2006 }
2007
2008 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2009 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2010
2011 if (!modules[i])
2012 continue;
2013
2014 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2015 stage ? stage->pName : "main", i,
2016 stage ? stage->pSpecializationInfo : NULL,
2017 flags);
2018 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2019
2020 /* We don't want to alter meta shaders IR directly so clone it
2021 * first.
2022 */
2023 if (nir[i]->info.name) {
2024 nir[i] = nir_shader_clone(NULL, nir[i]);
2025 }
2026
2027 if (first != last) {
2028 nir_variable_mode mask = 0;
2029
2030 if (i != first)
2031 mask = mask | nir_var_shader_in;
2032
2033 if (i != last)
2034 mask = mask | nir_var_shader_out;
2035
2036 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) {
2037 nir_lower_io_to_scalar_early(nir[i], mask);
2038 radv_optimize_nir(nir[i], false);
2039 }
2040 }
2041 }
2042
2043 if (nir[MESA_SHADER_TESS_CTRL]) {
2044 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
2045 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2046 }
2047
2048 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2049 radv_link_shaders(pipeline, nir);
2050
2051 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2052 if (radv_can_dump_shader(device, modules[i], false))
2053 nir_print_shader(nir[i], stderr);
2054 }
2055
2056 radv_fill_shader_keys(keys, &key, nir);
2057
2058 if (nir[MESA_SHADER_FRAGMENT]) {
2059 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2060 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2061 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2062 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2063 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
2064 }
2065
2066 /* TODO: These are no longer used as keys we should refactor this */
2067 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
2068 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2069 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
2070 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2071 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
2072 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2073 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
2074 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2075 }
2076
2077 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2078 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2079 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2080 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2081 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2082 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2083 pipeline->layout,
2084 &key, &codes[MESA_SHADER_TESS_CTRL],
2085 &code_sizes[MESA_SHADER_TESS_CTRL]);
2086 }
2087 modules[MESA_SHADER_VERTEX] = NULL;
2088 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2089 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2090 }
2091
2092 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2093 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2094 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2095 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2096 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2097 pipeline->layout,
2098 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
2099 &code_sizes[MESA_SHADER_GEOMETRY]);
2100 }
2101 modules[pre_stage] = NULL;
2102 }
2103
2104 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2105 if(modules[i] && !pipeline->shaders[i]) {
2106 if (i == MESA_SHADER_TESS_CTRL) {
2107 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2108 }
2109 if (i == MESA_SHADER_TESS_EVAL) {
2110 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2111 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2112 }
2113 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2114 pipeline->layout,
2115 keys + i, &codes[i],
2116 &code_sizes[i]);
2117 }
2118 }
2119
2120 if(modules[MESA_SHADER_GEOMETRY]) {
2121 void *gs_copy_code = NULL;
2122 unsigned gs_copy_code_size = 0;
2123 if (!pipeline->gs_copy_shader) {
2124 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2125 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2126 &gs_copy_code_size,
2127 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2128 }
2129
2130 if (pipeline->gs_copy_shader) {
2131 void *code[MESA_SHADER_STAGES] = {0};
2132 unsigned code_size[MESA_SHADER_STAGES] = {0};
2133 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2134
2135 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2136 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2137 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2138
2139 radv_pipeline_cache_insert_shaders(device, cache,
2140 gs_copy_hash,
2141 variants,
2142 (const void**)code,
2143 code_size);
2144 }
2145 free(gs_copy_code);
2146 }
2147
2148 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2149 (const void**)codes, code_sizes);
2150
2151 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2152 free(codes[i]);
2153 if (modules[i]) {
2154 if (!pipeline->device->keep_shader_info)
2155 ralloc_free(nir[i]);
2156
2157 if (radv_can_dump_shader_stats(device, modules[i]))
2158 radv_shader_dump_stats(device,
2159 pipeline->shaders[i],
2160 i, stderr);
2161 }
2162 }
2163
2164 if (fs_m.nir)
2165 ralloc_free(fs_m.nir);
2166 }
2167
2168 static uint32_t
2169 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2170 gl_shader_stage stage, enum chip_class chip_class)
2171 {
2172 bool has_gs = radv_pipeline_has_gs(pipeline);
2173 bool has_tess = radv_pipeline_has_tess(pipeline);
2174 switch (stage) {
2175 case MESA_SHADER_FRAGMENT:
2176 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2177 case MESA_SHADER_VERTEX:
2178 if (chip_class >= GFX9) {
2179 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2180 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2181 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2182 }
2183 if (has_tess)
2184 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2185 else
2186 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2187 case MESA_SHADER_GEOMETRY:
2188 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2189 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2190 case MESA_SHADER_COMPUTE:
2191 return R_00B900_COMPUTE_USER_DATA_0;
2192 case MESA_SHADER_TESS_CTRL:
2193 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2194 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2195 case MESA_SHADER_TESS_EVAL:
2196 if (chip_class >= GFX9) {
2197 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2198 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2199 }
2200 if (has_gs)
2201 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2202 else
2203 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2204 default:
2205 unreachable("unknown shader");
2206 }
2207 }
2208
2209 struct radv_bin_size_entry {
2210 unsigned bpp;
2211 VkExtent2D extent;
2212 };
2213
2214 static VkExtent2D
2215 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2216 {
2217 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2218 {
2219 /* One RB / SE */
2220 {
2221 /* One shader engine */
2222 { 0, {128, 128}},
2223 { 1, { 64, 128}},
2224 { 2, { 32, 128}},
2225 { 3, { 16, 128}},
2226 { 17, { 0, 0}},
2227 { UINT_MAX, { 0, 0}},
2228 },
2229 {
2230 /* Two shader engines */
2231 { 0, {128, 128}},
2232 { 2, { 64, 128}},
2233 { 3, { 32, 128}},
2234 { 5, { 16, 128}},
2235 { 17, { 0, 0}},
2236 { UINT_MAX, { 0, 0}},
2237 },
2238 {
2239 /* Four shader engines */
2240 { 0, {128, 128}},
2241 { 3, { 64, 128}},
2242 { 5, { 16, 128}},
2243 { 17, { 0, 0}},
2244 { UINT_MAX, { 0, 0}},
2245 },
2246 },
2247 {
2248 /* Two RB / SE */
2249 {
2250 /* One shader engine */
2251 { 0, {128, 128}},
2252 { 2, { 64, 128}},
2253 { 3, { 32, 128}},
2254 { 5, { 16, 128}},
2255 { 33, { 0, 0}},
2256 { UINT_MAX, { 0, 0}},
2257 },
2258 {
2259 /* Two shader engines */
2260 { 0, {128, 128}},
2261 { 3, { 64, 128}},
2262 { 5, { 32, 128}},
2263 { 9, { 16, 128}},
2264 { 33, { 0, 0}},
2265 { UINT_MAX, { 0, 0}},
2266 },
2267 {
2268 /* Four shader engines */
2269 { 0, {256, 256}},
2270 { 2, {128, 256}},
2271 { 3, {128, 128}},
2272 { 5, { 64, 128}},
2273 { 9, { 16, 128}},
2274 { 33, { 0, 0}},
2275 { UINT_MAX, { 0, 0}},
2276 },
2277 },
2278 {
2279 /* Four RB / SE */
2280 {
2281 /* One shader engine */
2282 { 0, {128, 256}},
2283 { 2, {128, 128}},
2284 { 3, { 64, 128}},
2285 { 5, { 32, 128}},
2286 { 9, { 16, 128}},
2287 { 33, { 0, 0}},
2288 { UINT_MAX, { 0, 0}},
2289 },
2290 {
2291 /* Two shader engines */
2292 { 0, {256, 256}},
2293 { 2, {128, 256}},
2294 { 3, {128, 128}},
2295 { 5, { 64, 128}},
2296 { 9, { 32, 128}},
2297 { 17, { 16, 128}},
2298 { 33, { 0, 0}},
2299 { UINT_MAX, { 0, 0}},
2300 },
2301 {
2302 /* Four shader engines */
2303 { 0, {256, 512}},
2304 { 2, {256, 256}},
2305 { 3, {128, 256}},
2306 { 5, {128, 128}},
2307 { 9, { 64, 128}},
2308 { 17, { 16, 128}},
2309 { 33, { 0, 0}},
2310 { UINT_MAX, { 0, 0}},
2311 },
2312 },
2313 };
2314 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2315 {
2316 // One RB / SE
2317 {
2318 // One shader engine
2319 { 0, {128, 256}},
2320 { 2, {128, 128}},
2321 { 4, { 64, 128}},
2322 { 7, { 32, 128}},
2323 { 13, { 16, 128}},
2324 { 49, { 0, 0}},
2325 { UINT_MAX, { 0, 0}},
2326 },
2327 {
2328 // Two shader engines
2329 { 0, {256, 256}},
2330 { 2, {128, 256}},
2331 { 4, {128, 128}},
2332 { 7, { 64, 128}},
2333 { 13, { 32, 128}},
2334 { 25, { 16, 128}},
2335 { 49, { 0, 0}},
2336 { UINT_MAX, { 0, 0}},
2337 },
2338 {
2339 // Four shader engines
2340 { 0, {256, 512}},
2341 { 2, {256, 256}},
2342 { 4, {128, 256}},
2343 { 7, {128, 128}},
2344 { 13, { 64, 128}},
2345 { 25, { 16, 128}},
2346 { 49, { 0, 0}},
2347 { UINT_MAX, { 0, 0}},
2348 },
2349 },
2350 {
2351 // Two RB / SE
2352 {
2353 // One shader engine
2354 { 0, {256, 256}},
2355 { 2, {128, 256}},
2356 { 4, {128, 128}},
2357 { 7, { 64, 128}},
2358 { 13, { 32, 128}},
2359 { 25, { 16, 128}},
2360 { 97, { 0, 0}},
2361 { UINT_MAX, { 0, 0}},
2362 },
2363 {
2364 // Two shader engines
2365 { 0, {256, 512}},
2366 { 2, {256, 256}},
2367 { 4, {128, 256}},
2368 { 7, {128, 128}},
2369 { 13, { 64, 128}},
2370 { 25, { 32, 128}},
2371 { 49, { 16, 128}},
2372 { 97, { 0, 0}},
2373 { UINT_MAX, { 0, 0}},
2374 },
2375 {
2376 // Four shader engines
2377 { 0, {512, 512}},
2378 { 2, {256, 512}},
2379 { 4, {256, 256}},
2380 { 7, {128, 256}},
2381 { 13, {128, 128}},
2382 { 25, { 64, 128}},
2383 { 49, { 16, 128}},
2384 { 97, { 0, 0}},
2385 { UINT_MAX, { 0, 0}},
2386 },
2387 },
2388 {
2389 // Four RB / SE
2390 {
2391 // One shader engine
2392 { 0, {256, 512}},
2393 { 2, {256, 256}},
2394 { 4, {128, 256}},
2395 { 7, {128, 128}},
2396 { 13, { 64, 128}},
2397 { 25, { 32, 128}},
2398 { 49, { 16, 128}},
2399 { UINT_MAX, { 0, 0}},
2400 },
2401 {
2402 // Two shader engines
2403 { 0, {512, 512}},
2404 { 2, {256, 512}},
2405 { 4, {256, 256}},
2406 { 7, {128, 256}},
2407 { 13, {128, 128}},
2408 { 25, { 64, 128}},
2409 { 49, { 32, 128}},
2410 { 97, { 16, 128}},
2411 { UINT_MAX, { 0, 0}},
2412 },
2413 {
2414 // Four shader engines
2415 { 0, {512, 512}},
2416 { 4, {256, 512}},
2417 { 7, {256, 256}},
2418 { 13, {128, 256}},
2419 { 25, {128, 128}},
2420 { 49, { 64, 128}},
2421 { 97, { 16, 128}},
2422 { UINT_MAX, { 0, 0}},
2423 },
2424 },
2425 };
2426
2427 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2428 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2429 VkExtent2D extent = {512, 512};
2430
2431 unsigned log_num_rb_per_se =
2432 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2433 pipeline->device->physical_device->rad_info.max_se);
2434 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2435
2436 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2437 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2438 unsigned effective_samples = total_samples;
2439 unsigned color_bytes_per_pixel = 0;
2440
2441 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2442 if (vkblend) {
2443 for (unsigned i = 0; i < subpass->color_count; i++) {
2444 if (!vkblend->pAttachments[i].colorWriteMask)
2445 continue;
2446
2447 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2448 continue;
2449
2450 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2451 color_bytes_per_pixel += vk_format_get_blocksize(format);
2452 }
2453
2454 /* MSAA images typically don't use all samples all the time. */
2455 if (effective_samples >= 2 && ps_iter_samples <= 1)
2456 effective_samples = 2;
2457 color_bytes_per_pixel *= effective_samples;
2458 }
2459
2460 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2461 while(color_entry->bpp <= color_bytes_per_pixel)
2462 ++color_entry;
2463
2464 extent = color_entry->extent;
2465
2466 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2467 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2468
2469 /* Coefficients taken from AMDVLK */
2470 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2471 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2472 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2473
2474 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2475 while(ds_entry->bpp <= ds_bytes_per_pixel)
2476 ++ds_entry;
2477
2478 extent.width = MIN2(extent.width, ds_entry->extent.width);
2479 extent.height = MIN2(extent.height, ds_entry->extent.height);
2480 }
2481
2482 return extent;
2483 }
2484
2485 static void
2486 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2487 struct radv_pipeline *pipeline,
2488 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2489 {
2490 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2491 return;
2492
2493 uint32_t pa_sc_binner_cntl_0 =
2494 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2495 S_028C44_DISABLE_START_OF_PRIM(1);
2496 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2497
2498 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2499
2500 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2501 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2502 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2503
2504 switch (pipeline->device->physical_device->rad_info.family) {
2505 case CHIP_VEGA10:
2506 case CHIP_VEGA12:
2507 context_states_per_bin = 1;
2508 persistent_states_per_bin = 1;
2509 fpovs_per_batch = 63;
2510 break;
2511 case CHIP_RAVEN:
2512 context_states_per_bin = 6;
2513 persistent_states_per_bin = 32;
2514 fpovs_per_batch = 63;
2515 break;
2516 default:
2517 unreachable("unhandled family while determining binning state.");
2518 }
2519
2520 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2521 pa_sc_binner_cntl_0 =
2522 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2523 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2524 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2525 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2526 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2527 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2528 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2529 S_028C44_DISABLE_START_OF_PRIM(1) |
2530 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2531 S_028C44_OPTIMAL_BIN_SELECTION(1);
2532 }
2533
2534 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2535 pa_sc_binner_cntl_0);
2536 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2537 db_dfsm_control);
2538 }
2539
2540
2541 static void
2542 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2543 struct radv_pipeline *pipeline,
2544 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2545 const struct radv_graphics_pipeline_create_info *extra)
2546 {
2547 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2548 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2549 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2550 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2551 struct radv_render_pass_attachment *attachment = NULL;
2552 uint32_t db_depth_control = 0, db_stencil_control = 0;
2553 uint32_t db_render_control = 0, db_render_override2 = 0;
2554 uint32_t db_render_override = 0;
2555
2556 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2557 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2558
2559 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2560 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2561
2562 if (vkds && has_depth_attachment) {
2563 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2564 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2565 S_028800_ZFUNC(vkds->depthCompareOp) |
2566 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2567
2568 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2569 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2570 }
2571
2572 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2573 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2574 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2575 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2576 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2577 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2578
2579 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2580 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2581 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2582 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2583 }
2584
2585 if (attachment && extra) {
2586 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2587 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2588
2589 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2590 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2591 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2592 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2593 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2594 }
2595
2596 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2597 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2598
2599 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2600 !pCreateInfo->pRasterizationState->depthClampEnable &&
2601 ps->info.info.ps.writes_z) {
2602 /* From VK_EXT_depth_range_unrestricted spec:
2603 *
2604 * "The behavior described in Primitive Clipping still applies.
2605 * If depth clamping is disabled the depth values are still
2606 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2607 * depth clamping is enabled the above equation is ignored and
2608 * the depth values are instead clamped to the VkViewport
2609 * minDepth and maxDepth values, which in the case of this
2610 * extension can be outside of the 0.0 to 1.0 range."
2611 */
2612 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2613 }
2614
2615 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2616 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2617
2618 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2619 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2620 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2621 }
2622
2623 static void
2624 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2625 struct radv_pipeline *pipeline,
2626 const struct radv_blend_state *blend)
2627 {
2628 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2629 radeon_emit_array(cs, blend->cb_blend_control,
2630 8);
2631 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2632 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2633
2634 if (pipeline->device->physical_device->has_rbplus) {
2635
2636 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2637 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2638 }
2639
2640 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2641
2642 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2643 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2644
2645 pipeline->graphics.col_format = blend->spi_shader_col_format;
2646 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
2647 }
2648
2649
2650 static void
2651 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2652 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2653 {
2654 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2655
2656 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2657 S_028810_PS_UCP_MODE(3) |
2658 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2659 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2660 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2661 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2662 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2663
2664 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2665 S_0286D4_FLAT_SHADE_ENA(1) |
2666 S_0286D4_PNT_SPRITE_ENA(1) |
2667 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2668 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2669 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2670 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2671 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2672
2673 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2674 S_028BE4_PIX_CENTER(1) | // TODO verify
2675 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2676 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2677
2678 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2679 S_028814_FACE(vkraster->frontFace) |
2680 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2681 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2682 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2683 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2684 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2685 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2686 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2687 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2688 }
2689
2690
2691 static void
2692 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2693 struct radv_pipeline *pipeline)
2694 {
2695 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2696
2697 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2698 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2699 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2700
2701 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2702 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2703
2704 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2705 uint32_t offset;
2706 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2707 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2708 if (loc->sgpr_idx == -1)
2709 return;
2710 assert(loc->num_sgprs == 1);
2711 assert(!loc->indirect);
2712 switch (pipeline->graphics.ms.num_samples) {
2713 default:
2714 offset = 0;
2715 break;
2716 case 2:
2717 offset = 1;
2718 break;
2719 case 4:
2720 offset = 3;
2721 break;
2722 case 8:
2723 offset = 7;
2724 break;
2725 case 16:
2726 offset = 15;
2727 break;
2728 }
2729
2730 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2731 }
2732 }
2733
2734 static void
2735 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2736 const struct radv_pipeline *pipeline)
2737 {
2738 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2739
2740 uint32_t vgt_primitiveid_en = false;
2741 uint32_t vgt_gs_mode = 0;
2742
2743 if (radv_pipeline_has_gs(pipeline)) {
2744 const struct radv_shader_variant *gs =
2745 pipeline->shaders[MESA_SHADER_GEOMETRY];
2746
2747 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2748 pipeline->device->physical_device->rad_info.chip_class);
2749 } else if (outinfo->export_prim_id) {
2750 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2751 vgt_primitiveid_en = true;
2752 }
2753
2754 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2755 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2756 }
2757
2758 static void
2759 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2760 struct radv_pipeline *pipeline,
2761 struct radv_shader_variant *shader)
2762 {
2763 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2764
2765 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2766 radeon_emit(cs, va >> 8);
2767 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2768 radeon_emit(cs, shader->rsrc1);
2769 radeon_emit(cs, shader->rsrc2);
2770
2771 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2772 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2773 clip_dist_mask = outinfo->clip_dist_mask;
2774 cull_dist_mask = outinfo->cull_dist_mask;
2775 total_mask = clip_dist_mask | cull_dist_mask;
2776 bool misc_vec_ena = outinfo->writes_pointsize ||
2777 outinfo->writes_layer ||
2778 outinfo->writes_viewport_index;
2779
2780 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2781 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2782
2783 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2784 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2785 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2786 V_02870C_SPI_SHADER_4COMP :
2787 V_02870C_SPI_SHADER_NONE) |
2788 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2789 V_02870C_SPI_SHADER_4COMP :
2790 V_02870C_SPI_SHADER_NONE) |
2791 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2792 V_02870C_SPI_SHADER_4COMP :
2793 V_02870C_SPI_SHADER_NONE));
2794
2795 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2796 S_028818_VTX_W0_FMT(1) |
2797 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2798 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2799 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2800
2801 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2802 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2803 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2804 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2805 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2806 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2807 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2808 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2809 cull_dist_mask << 8 |
2810 clip_dist_mask);
2811
2812 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2813 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2814 outinfo->writes_viewport_index);
2815 }
2816
2817 static void
2818 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2819 struct radv_pipeline *pipeline,
2820 struct radv_shader_variant *shader)
2821 {
2822 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2823
2824 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2825 radeon_emit(cs, va >> 8);
2826 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2827 radeon_emit(cs, shader->rsrc1);
2828 radeon_emit(cs, shader->rsrc2);
2829 }
2830
2831 static void
2832 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2833 struct radv_pipeline *pipeline,
2834 struct radv_shader_variant *shader,
2835 const struct radv_tessellation_state *tess)
2836 {
2837 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2838 uint32_t rsrc2 = shader->rsrc2;
2839
2840 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2841 radeon_emit(cs, va >> 8);
2842 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2843
2844 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2845 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2846 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2847 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2848
2849 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2850 radeon_emit(cs, shader->rsrc1);
2851 radeon_emit(cs, rsrc2);
2852 }
2853
2854 static void
2855 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2856 struct radv_pipeline *pipeline,
2857 struct radv_shader_variant *shader,
2858 const struct radv_tessellation_state *tess)
2859 {
2860 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2861
2862 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2863 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2864 radeon_emit(cs, va >> 8);
2865 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2866
2867 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2868 radeon_emit(cs, shader->rsrc1);
2869 radeon_emit(cs, shader->rsrc2 |
2870 S_00B42C_LDS_SIZE(tess->lds_size));
2871 } else {
2872 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2873 radeon_emit(cs, va >> 8);
2874 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2875 radeon_emit(cs, shader->rsrc1);
2876 radeon_emit(cs, shader->rsrc2);
2877 }
2878 }
2879
2880 static void
2881 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2882 struct radv_pipeline *pipeline,
2883 const struct radv_tessellation_state *tess)
2884 {
2885 struct radv_shader_variant *vs;
2886
2887 /* Skip shaders merged into HS/GS */
2888 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2889 if (!vs)
2890 return;
2891
2892 if (vs->info.vs.as_ls)
2893 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2894 else if (vs->info.vs.as_es)
2895 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2896 else
2897 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2898 }
2899
2900 static void
2901 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2902 struct radv_pipeline *pipeline,
2903 const struct radv_tessellation_state *tess)
2904 {
2905 if (!radv_pipeline_has_tess(pipeline))
2906 return;
2907
2908 struct radv_shader_variant *tes, *tcs;
2909
2910 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2911 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2912
2913 if (tes) {
2914 if (tes->info.tes.as_es)
2915 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2916 else
2917 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2918 }
2919
2920 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2921
2922 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2923 tess->tf_param);
2924
2925 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2926 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2927 tess->ls_hs_config);
2928 else
2929 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2930 tess->ls_hs_config);
2931 }
2932
2933 static void
2934 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2935 struct radv_pipeline *pipeline,
2936 const struct radv_gs_state *gs_state)
2937 {
2938 struct radv_shader_variant *gs;
2939 uint64_t va;
2940
2941 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2942 if (!gs)
2943 return;
2944
2945 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2946
2947 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2948 radeon_emit(cs, gsvs_itemsize);
2949 radeon_emit(cs, gsvs_itemsize);
2950 radeon_emit(cs, gsvs_itemsize);
2951
2952 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2953
2954 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2955
2956 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2957 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2958 radeon_emit(cs, gs_vert_itemsize >> 2);
2959 radeon_emit(cs, 0);
2960 radeon_emit(cs, 0);
2961 radeon_emit(cs, 0);
2962
2963 uint32_t gs_num_invocations = gs->info.gs.invocations;
2964 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2965 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2966 S_028B90_ENABLE(gs_num_invocations > 0));
2967
2968 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2969 gs_state->vgt_esgs_ring_itemsize);
2970
2971 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2972
2973 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2974 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2975 radeon_emit(cs, va >> 8);
2976 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
2977
2978 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2979 radeon_emit(cs, gs->rsrc1);
2980 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2981
2982 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2983 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2984 } else {
2985 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2986 radeon_emit(cs, va >> 8);
2987 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
2988 radeon_emit(cs, gs->rsrc1);
2989 radeon_emit(cs, gs->rsrc2);
2990 }
2991
2992 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2993 }
2994
2995 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2996 {
2997 uint32_t ps_input_cntl;
2998 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2999 ps_input_cntl = S_028644_OFFSET(offset);
3000 if (flat_shade)
3001 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3002 } else {
3003 /* The input is a DEFAULT_VAL constant. */
3004 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3005 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3006 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3007 ps_input_cntl = S_028644_OFFSET(0x20) |
3008 S_028644_DEFAULT_VAL(offset);
3009 }
3010 return ps_input_cntl;
3011 }
3012
3013 static void
3014 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
3015 struct radv_pipeline *pipeline)
3016 {
3017 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3018 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3019 uint32_t ps_input_cntl[32];
3020
3021 unsigned ps_offset = 0;
3022
3023 if (ps->info.info.ps.prim_id_input) {
3024 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3025 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3026 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3027 ++ps_offset;
3028 }
3029 }
3030
3031 if (ps->info.info.ps.layer_input ||
3032 ps->info.info.ps.uses_input_attachments ||
3033 ps->info.info.needs_multiview_view_index) {
3034 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3035 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3036 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3037 else
3038 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
3039 ++ps_offset;
3040 }
3041
3042 if (ps->info.info.ps.has_pcoord) {
3043 unsigned val;
3044 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3045 ps_input_cntl[ps_offset] = val;
3046 ps_offset++;
3047 }
3048
3049 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3050 unsigned vs_offset;
3051 bool flat_shade;
3052 if (!(ps->info.fs.input_mask & (1u << i)))
3053 continue;
3054
3055 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3056 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3057 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3058 ++ps_offset;
3059 continue;
3060 }
3061
3062 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
3063
3064 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
3065 ++ps_offset;
3066 }
3067
3068 if (ps_offset) {
3069 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
3070 for (unsigned i = 0; i < ps_offset; i++) {
3071 radeon_emit(cs, ps_input_cntl[i]);
3072 }
3073 }
3074 }
3075
3076 static uint32_t
3077 radv_compute_db_shader_control(const struct radv_device *device,
3078 const struct radv_shader_variant *ps)
3079 {
3080 unsigned z_order;
3081 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3082 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3083 else
3084 z_order = V_02880C_LATE_Z;
3085
3086 bool disable_rbplus = device->physical_device->has_rbplus &&
3087 !device->physical_device->rbplus_allowed;
3088
3089 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
3090 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
3091 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
3092 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
3093 S_02880C_Z_ORDER(z_order) |
3094 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3095 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3096 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3097 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
3098 }
3099
3100 static void
3101 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
3102 struct radv_pipeline *pipeline)
3103 {
3104 struct radv_shader_variant *ps;
3105 uint64_t va;
3106 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3107
3108 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3109 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3110
3111 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3112 radeon_emit(cs, va >> 8);
3113 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3114 radeon_emit(cs, ps->rsrc1);
3115 radeon_emit(cs, ps->rsrc2);
3116
3117 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
3118 radv_compute_db_shader_control(pipeline->device, ps));
3119
3120 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
3121 ps->config.spi_ps_input_ena);
3122
3123 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
3124 ps->config.spi_ps_input_addr);
3125
3126 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
3127 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3128
3129 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3130
3131 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
3132 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3133 ps->info.info.ps.writes_stencil,
3134 ps->info.info.ps.writes_sample_mask));
3135
3136 if (pipeline->device->dfsm_allowed) {
3137 /* optimise this? */
3138 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3139 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3140 }
3141 }
3142
3143 static void
3144 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
3145 struct radv_pipeline *pipeline)
3146 {
3147 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
3148 return;
3149
3150 unsigned vtx_reuse_depth = 30;
3151 if (radv_pipeline_has_tess(pipeline) &&
3152 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3153 vtx_reuse_depth = 14;
3154 }
3155 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3156 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3157 }
3158
3159 static uint32_t
3160 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3161 {
3162 uint32_t stages = 0;
3163 if (radv_pipeline_has_tess(pipeline)) {
3164 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3165 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3166
3167 if (radv_pipeline_has_gs(pipeline))
3168 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3169 S_028B54_GS_EN(1) |
3170 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3171 else
3172 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3173
3174 } else if (radv_pipeline_has_gs(pipeline))
3175 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3176 S_028B54_GS_EN(1) |
3177 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3178
3179 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3180 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3181
3182 return stages;
3183 }
3184
3185 static uint32_t
3186 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3187 {
3188 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3189 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3190
3191 if (!discard_rectangle_info)
3192 return 0xffff;
3193
3194 unsigned mask = 0;
3195
3196 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3197 /* Interpret i as a bitmask, and then set the bit in the mask if
3198 * that combination of rectangles in which the pixel is contained
3199 * should pass the cliprect test. */
3200 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3201
3202 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3203 !relevant_subset)
3204 continue;
3205
3206 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3207 relevant_subset)
3208 continue;
3209
3210 mask |= 1u << i;
3211 }
3212
3213 return mask;
3214 }
3215
3216 static void
3217 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
3218 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3219 const struct radv_graphics_pipeline_create_info *extra,
3220 const struct radv_blend_state *blend,
3221 const struct radv_tessellation_state *tess,
3222 const struct radv_gs_state *gs,
3223 unsigned prim, unsigned gs_out)
3224 {
3225 pipeline->cs.buf = malloc(4 * 256);
3226 pipeline->cs.max_dw = 256;
3227
3228 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
3229 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
3230 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
3231 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
3232 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
3233 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
3234 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
3235 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
3236 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
3237 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
3238 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
3239 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
3240
3241 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
3242 S_0286E8_WAVES(pipeline->max_waves) |
3243 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3244
3245 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
3246
3247 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
3248 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
3249 } else {
3250 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
3251 }
3252 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
3253
3254 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
3255
3256 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3257 }
3258
3259 static struct radv_ia_multi_vgt_param_helpers
3260 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
3261 const struct radv_tessellation_state *tess,
3262 uint32_t prim)
3263 {
3264 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
3265 const struct radv_device *device = pipeline->device;
3266
3267 if (radv_pipeline_has_tess(pipeline))
3268 ia_multi_vgt_param.primgroup_size = tess->num_patches;
3269 else if (radv_pipeline_has_gs(pipeline))
3270 ia_multi_vgt_param.primgroup_size = 64;
3271 else
3272 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3273
3274 ia_multi_vgt_param.partial_es_wave = false;
3275 if (pipeline->device->has_distributed_tess) {
3276 if (radv_pipeline_has_gs(pipeline)) {
3277 if (device->physical_device->rad_info.chip_class <= VI)
3278 ia_multi_vgt_param.partial_es_wave = true;
3279 }
3280 }
3281 /* GS requirement. */
3282 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
3283 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3284 ia_multi_vgt_param.partial_es_wave = true;
3285
3286 ia_multi_vgt_param.wd_switch_on_eop = false;
3287 if (device->physical_device->rad_info.chip_class >= CIK) {
3288 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3289 * 4 shader engines. Set 1 to pass the assertion below.
3290 * The other cases are hardware requirements. */
3291 if (device->physical_device->rad_info.max_se < 4 ||
3292 prim == V_008958_DI_PT_POLYGON ||
3293 prim == V_008958_DI_PT_LINELOOP ||
3294 prim == V_008958_DI_PT_TRIFAN ||
3295 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3296 (pipeline->graphics.prim_restart_enable &&
3297 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3298 (prim != V_008958_DI_PT_POINTLIST &&
3299 prim != V_008958_DI_PT_LINESTRIP &&
3300 prim != V_008958_DI_PT_TRISTRIP))))
3301 ia_multi_vgt_param.wd_switch_on_eop = true;
3302 }
3303
3304 ia_multi_vgt_param.ia_switch_on_eoi = false;
3305 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3306 ia_multi_vgt_param.ia_switch_on_eoi = true;
3307 if (radv_pipeline_has_gs(pipeline) &&
3308 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3309 ia_multi_vgt_param.ia_switch_on_eoi = true;
3310 if (radv_pipeline_has_tess(pipeline)) {
3311 /* SWITCH_ON_EOI must be set if PrimID is used. */
3312 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3313 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3314 ia_multi_vgt_param.ia_switch_on_eoi = true;
3315 }
3316
3317 ia_multi_vgt_param.partial_vs_wave = false;
3318 if (radv_pipeline_has_tess(pipeline)) {
3319 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3320 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3321 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3322 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3323 radv_pipeline_has_gs(pipeline))
3324 ia_multi_vgt_param.partial_vs_wave = true;
3325 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3326 if (device->has_distributed_tess) {
3327 if (radv_pipeline_has_gs(pipeline)) {
3328 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3329 device->physical_device->rad_info.family == CHIP_FIJI ||
3330 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3331 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3332 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
3333 device->physical_device->rad_info.family == CHIP_VEGAM)
3334 ia_multi_vgt_param.partial_vs_wave = true;
3335 } else {
3336 ia_multi_vgt_param.partial_vs_wave = true;
3337 }
3338 }
3339 }
3340
3341 ia_multi_vgt_param.base =
3342 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3343 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3344 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3345 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3346 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3347
3348 return ia_multi_vgt_param;
3349 }
3350
3351
3352 static void
3353 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3354 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3355 {
3356 const VkPipelineVertexInputStateCreateInfo *vi_info =
3357 pCreateInfo->pVertexInputState;
3358 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3359
3360 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3361 const VkVertexInputAttributeDescription *desc =
3362 &vi_info->pVertexAttributeDescriptions[i];
3363 unsigned loc = desc->location;
3364 const struct vk_format_description *format_desc;
3365 int first_non_void;
3366 uint32_t num_format, data_format;
3367 format_desc = vk_format_description(desc->format);
3368 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3369
3370 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3371 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3372
3373 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3374 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3375 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3376 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3377 S_008F0C_NUM_FORMAT(num_format) |
3378 S_008F0C_DATA_FORMAT(data_format);
3379 velems->format_size[loc] = format_desc->block.bits / 8;
3380 velems->offset[loc] = desc->offset;
3381 velems->binding[loc] = desc->binding;
3382 velems->count = MAX2(velems->count, loc + 1);
3383 }
3384
3385 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3386 const VkVertexInputBindingDescription *desc =
3387 &vi_info->pVertexBindingDescriptions[i];
3388
3389 pipeline->binding_stride[desc->binding] = desc->stride;
3390 }
3391 }
3392
3393 static VkResult
3394 radv_pipeline_init(struct radv_pipeline *pipeline,
3395 struct radv_device *device,
3396 struct radv_pipeline_cache *cache,
3397 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3398 const struct radv_graphics_pipeline_create_info *extra,
3399 const VkAllocationCallbacks *alloc)
3400 {
3401 VkResult result;
3402 bool has_view_index = false;
3403
3404 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3405 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3406 if (subpass->view_mask)
3407 has_view_index = true;
3408 if (alloc == NULL)
3409 alloc = &device->alloc;
3410
3411 pipeline->device = device;
3412 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3413 assert(pipeline->layout);
3414
3415 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3416
3417 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3418 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3419 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3420 pStages[stage] = &pCreateInfo->pStages[i];
3421 }
3422
3423 radv_create_shaders(pipeline, device, cache,
3424 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3425 pStages, pCreateInfo->flags);
3426
3427 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3428 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
3429 uint32_t gs_out;
3430 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3431
3432 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3433
3434 if (radv_pipeline_has_gs(pipeline)) {
3435 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3436 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3437 } else {
3438 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3439 }
3440 if (extra && extra->use_rectlist) {
3441 prim = V_008958_DI_PT_RECTLIST;
3442 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3443 pipeline->graphics.can_use_guardband = true;
3444 }
3445 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3446 /* prim vertex count will need TESS changes */
3447 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3448
3449 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3450
3451 /* Ensure that some export memory is always allocated, for two reasons:
3452 *
3453 * 1) Correctness: The hardware ignores the EXEC mask if no export
3454 * memory is allocated, so KILL and alpha test do not work correctly
3455 * without this.
3456 * 2) Performance: Every shader needs at least a NULL export, even when
3457 * it writes no color/depth output. The NULL export instruction
3458 * stalls without this setting.
3459 *
3460 * Don't add this to CB_SHADER_MASK.
3461 */
3462 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3463 if (!blend.spi_shader_col_format) {
3464 if (!ps->info.info.ps.writes_z &&
3465 !ps->info.info.ps.writes_stencil &&
3466 !ps->info.info.ps.writes_sample_mask)
3467 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3468 }
3469
3470 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3471 if (pipeline->shaders[i]) {
3472 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3473 }
3474 }
3475
3476 struct radv_gs_state gs = {0};
3477 if (radv_pipeline_has_gs(pipeline)) {
3478 gs = calculate_gs_info(pCreateInfo, pipeline);
3479 calculate_gs_ring_sizes(pipeline, &gs);
3480 }
3481
3482 struct radv_tessellation_state tess = {0};
3483 if (radv_pipeline_has_tess(pipeline)) {
3484 if (prim == V_008958_DI_PT_PATCH) {
3485 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3486 pipeline->graphics.prim_vertex_count.incr = 1;
3487 }
3488 tess = calculate_tess_state(pipeline, pCreateInfo);
3489 }
3490
3491 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3492
3493 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3494
3495 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3496 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3497
3498 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3499 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3500 if (loc->sgpr_idx != -1) {
3501 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3502 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3503 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3504 pipeline->graphics.vtx_emit_num = 3;
3505 else
3506 pipeline->graphics.vtx_emit_num = 2;
3507 }
3508
3509 result = radv_pipeline_scratch_init(device, pipeline);
3510 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3511
3512 return result;
3513 }
3514
3515 VkResult
3516 radv_graphics_pipeline_create(
3517 VkDevice _device,
3518 VkPipelineCache _cache,
3519 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3520 const struct radv_graphics_pipeline_create_info *extra,
3521 const VkAllocationCallbacks *pAllocator,
3522 VkPipeline *pPipeline)
3523 {
3524 RADV_FROM_HANDLE(radv_device, device, _device);
3525 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3526 struct radv_pipeline *pipeline;
3527 VkResult result;
3528
3529 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3530 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3531 if (pipeline == NULL)
3532 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3533
3534 result = radv_pipeline_init(pipeline, device, cache,
3535 pCreateInfo, extra, pAllocator);
3536 if (result != VK_SUCCESS) {
3537 radv_pipeline_destroy(device, pipeline, pAllocator);
3538 return result;
3539 }
3540
3541 *pPipeline = radv_pipeline_to_handle(pipeline);
3542
3543 return VK_SUCCESS;
3544 }
3545
3546 VkResult radv_CreateGraphicsPipelines(
3547 VkDevice _device,
3548 VkPipelineCache pipelineCache,
3549 uint32_t count,
3550 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3551 const VkAllocationCallbacks* pAllocator,
3552 VkPipeline* pPipelines)
3553 {
3554 VkResult result = VK_SUCCESS;
3555 unsigned i = 0;
3556
3557 for (; i < count; i++) {
3558 VkResult r;
3559 r = radv_graphics_pipeline_create(_device,
3560 pipelineCache,
3561 &pCreateInfos[i],
3562 NULL, pAllocator, &pPipelines[i]);
3563 if (r != VK_SUCCESS) {
3564 result = r;
3565 pPipelines[i] = VK_NULL_HANDLE;
3566 }
3567 }
3568
3569 return result;
3570 }
3571
3572
3573 static void
3574 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3575 {
3576 struct radv_shader_variant *compute_shader;
3577 struct radv_device *device = pipeline->device;
3578 unsigned compute_resource_limits;
3579 unsigned waves_per_threadgroup;
3580 uint64_t va;
3581
3582 pipeline->cs.buf = malloc(20 * 4);
3583 pipeline->cs.max_dw = 20;
3584
3585 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3586 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3587
3588 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3589 radeon_emit(&pipeline->cs, va >> 8);
3590 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3591
3592 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3593 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3594 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3595
3596 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3597 S_00B860_WAVES(pipeline->max_waves) |
3598 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3599
3600 /* Calculate best compute resource limits. */
3601 waves_per_threadgroup =
3602 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3603 compute_shader->info.cs.block_size[1] *
3604 compute_shader->info.cs.block_size[2], 64);
3605 compute_resource_limits =
3606 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3607
3608 if (device->physical_device->rad_info.chip_class >= CIK) {
3609 unsigned num_cu_per_se =
3610 device->physical_device->rad_info.num_good_compute_units /
3611 device->physical_device->rad_info.max_se;
3612
3613 /* Force even distribution on all SIMDs in CU if the workgroup
3614 * size is 64. This has shown some good improvements if # of
3615 * CUs per SE is not a multiple of 4.
3616 */
3617 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3618 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3619 }
3620
3621 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3622 compute_resource_limits);
3623
3624 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3625 radeon_emit(&pipeline->cs,
3626 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3627 radeon_emit(&pipeline->cs,
3628 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3629 radeon_emit(&pipeline->cs,
3630 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3631
3632 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3633 }
3634
3635 static VkResult radv_compute_pipeline_create(
3636 VkDevice _device,
3637 VkPipelineCache _cache,
3638 const VkComputePipelineCreateInfo* pCreateInfo,
3639 const VkAllocationCallbacks* pAllocator,
3640 VkPipeline* pPipeline)
3641 {
3642 RADV_FROM_HANDLE(radv_device, device, _device);
3643 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3644 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3645 struct radv_pipeline *pipeline;
3646 VkResult result;
3647
3648 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3649 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3650 if (pipeline == NULL)
3651 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3652
3653 pipeline->device = device;
3654 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3655 assert(pipeline->layout);
3656
3657 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3658 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
3659
3660 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3661 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3662 result = radv_pipeline_scratch_init(device, pipeline);
3663 if (result != VK_SUCCESS) {
3664 radv_pipeline_destroy(device, pipeline, pAllocator);
3665 return result;
3666 }
3667
3668 radv_compute_generate_pm4(pipeline);
3669
3670 *pPipeline = radv_pipeline_to_handle(pipeline);
3671
3672 return VK_SUCCESS;
3673 }
3674
3675 VkResult radv_CreateComputePipelines(
3676 VkDevice _device,
3677 VkPipelineCache pipelineCache,
3678 uint32_t count,
3679 const VkComputePipelineCreateInfo* pCreateInfos,
3680 const VkAllocationCallbacks* pAllocator,
3681 VkPipeline* pPipelines)
3682 {
3683 VkResult result = VK_SUCCESS;
3684
3685 unsigned i = 0;
3686 for (; i < count; i++) {
3687 VkResult r;
3688 r = radv_compute_pipeline_create(_device, pipelineCache,
3689 &pCreateInfos[i],
3690 pAllocator, &pPipelines[i]);
3691 if (r != VK_SUCCESS) {
3692 result = r;
3693 pPipelines[i] = VK_NULL_HANDLE;
3694 }
3695 }
3696
3697 return result;
3698 }