2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
33 #include "radv_shader.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
53 struct radv_blend_state
{
54 uint32_t blend_enable_4bit
;
55 uint32_t need_src_alpha
;
57 uint32_t cb_color_control
;
58 uint32_t cb_target_mask
;
59 uint32_t cb_target_enabled_4bit
;
60 uint32_t sx_mrt_blend_opt
[8];
61 uint32_t cb_blend_control
[8];
63 uint32_t spi_shader_col_format
;
64 uint32_t cb_shader_mask
;
65 uint32_t db_alpha_to_mask
;
67 uint32_t commutative_4bit
;
69 bool single_cb_enable
;
70 bool mrt0_is_dual_src
;
73 struct radv_dsa_order_invariance
{
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
86 struct radv_tessellation_state
{
87 uint32_t ls_hs_config
;
93 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
95 struct radv_shader_variant
*variant
= NULL
;
96 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
97 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
98 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
99 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
100 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
101 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
104 return variant
->info
.is_ngg
;
107 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
109 if (!radv_pipeline_has_gs(pipeline
))
112 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
113 * On GFX10, it might be required in rare cases if it's not possible to
116 if (radv_pipeline_has_ngg(pipeline
))
119 assert(pipeline
->gs_copy_shader
);
124 radv_pipeline_destroy(struct radv_device
*device
,
125 struct radv_pipeline
*pipeline
,
126 const VkAllocationCallbacks
* allocator
)
128 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
129 if (pipeline
->shaders
[i
])
130 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
132 if (pipeline
->gs_copy_shader
)
133 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
136 free(pipeline
->cs
.buf
);
137 vk_free2(&device
->alloc
, allocator
, pipeline
);
140 void radv_DestroyPipeline(
142 VkPipeline _pipeline
,
143 const VkAllocationCallbacks
* pAllocator
)
145 RADV_FROM_HANDLE(radv_device
, device
, _device
);
146 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
151 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
154 static uint32_t get_hash_flags(struct radv_device
*device
)
156 uint32_t hash_flags
= 0;
158 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
159 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
160 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
161 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
162 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
163 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
164 if (device
->physical_device
->cs_wave_size
== 32)
165 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
166 if (device
->physical_device
->ps_wave_size
== 32)
167 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
168 if (device
->physical_device
->ge_wave_size
== 32)
169 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
170 if (device
->physical_device
->use_aco
)
171 hash_flags
|= RADV_HASH_SHADER_ACO
;
176 radv_pipeline_scratch_init(struct radv_device
*device
,
177 struct radv_pipeline
*pipeline
)
179 unsigned scratch_bytes_per_wave
= 0;
180 unsigned max_waves
= 0;
181 unsigned min_waves
= 1;
183 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
184 if (pipeline
->shaders
[i
]) {
185 unsigned max_stage_waves
= device
->scratch_waves
;
187 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
188 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
190 max_stage_waves
= MIN2(max_stage_waves
,
191 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
192 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
193 max_waves
= MAX2(max_waves
, max_stage_waves
);
197 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
198 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
199 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
200 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
201 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
204 if (scratch_bytes_per_wave
)
205 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
207 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
208 /* Not really true at this moment, but will be true on first
209 * execution. Avoid having hanging shaders. */
210 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
212 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
213 pipeline
->max_waves
= max_waves
;
217 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
220 case VK_LOGIC_OP_CLEAR
:
221 return V_028808_ROP3_CLEAR
;
222 case VK_LOGIC_OP_AND
:
223 return V_028808_ROP3_AND
;
224 case VK_LOGIC_OP_AND_REVERSE
:
225 return V_028808_ROP3_AND_REVERSE
;
226 case VK_LOGIC_OP_COPY
:
227 return V_028808_ROP3_COPY
;
228 case VK_LOGIC_OP_AND_INVERTED
:
229 return V_028808_ROP3_AND_INVERTED
;
230 case VK_LOGIC_OP_NO_OP
:
231 return V_028808_ROP3_NO_OP
;
232 case VK_LOGIC_OP_XOR
:
233 return V_028808_ROP3_XOR
;
235 return V_028808_ROP3_OR
;
236 case VK_LOGIC_OP_NOR
:
237 return V_028808_ROP3_NOR
;
238 case VK_LOGIC_OP_EQUIVALENT
:
239 return V_028808_ROP3_EQUIVALENT
;
240 case VK_LOGIC_OP_INVERT
:
241 return V_028808_ROP3_INVERT
;
242 case VK_LOGIC_OP_OR_REVERSE
:
243 return V_028808_ROP3_OR_REVERSE
;
244 case VK_LOGIC_OP_COPY_INVERTED
:
245 return V_028808_ROP3_COPY_INVERTED
;
246 case VK_LOGIC_OP_OR_INVERTED
:
247 return V_028808_ROP3_OR_INVERTED
;
248 case VK_LOGIC_OP_NAND
:
249 return V_028808_ROP3_NAND
;
250 case VK_LOGIC_OP_SET
:
251 return V_028808_ROP3_SET
;
253 unreachable("Unhandled logic op");
258 static uint32_t si_translate_blend_function(VkBlendOp op
)
261 case VK_BLEND_OP_ADD
:
262 return V_028780_COMB_DST_PLUS_SRC
;
263 case VK_BLEND_OP_SUBTRACT
:
264 return V_028780_COMB_SRC_MINUS_DST
;
265 case VK_BLEND_OP_REVERSE_SUBTRACT
:
266 return V_028780_COMB_DST_MINUS_SRC
;
267 case VK_BLEND_OP_MIN
:
268 return V_028780_COMB_MIN_DST_SRC
;
269 case VK_BLEND_OP_MAX
:
270 return V_028780_COMB_MAX_DST_SRC
;
276 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
279 case VK_BLEND_FACTOR_ZERO
:
280 return V_028780_BLEND_ZERO
;
281 case VK_BLEND_FACTOR_ONE
:
282 return V_028780_BLEND_ONE
;
283 case VK_BLEND_FACTOR_SRC_COLOR
:
284 return V_028780_BLEND_SRC_COLOR
;
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
286 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
287 case VK_BLEND_FACTOR_DST_COLOR
:
288 return V_028780_BLEND_DST_COLOR
;
289 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
290 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
291 case VK_BLEND_FACTOR_SRC_ALPHA
:
292 return V_028780_BLEND_SRC_ALPHA
;
293 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
294 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
295 case VK_BLEND_FACTOR_DST_ALPHA
:
296 return V_028780_BLEND_DST_ALPHA
;
297 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
298 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
299 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
300 return V_028780_BLEND_CONSTANT_COLOR
;
301 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
302 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
303 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
304 return V_028780_BLEND_CONSTANT_ALPHA
;
305 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
306 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
307 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
308 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
309 case VK_BLEND_FACTOR_SRC1_COLOR
:
310 return V_028780_BLEND_SRC1_COLOR
;
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
312 return V_028780_BLEND_INV_SRC1_COLOR
;
313 case VK_BLEND_FACTOR_SRC1_ALPHA
:
314 return V_028780_BLEND_SRC1_ALPHA
;
315 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
316 return V_028780_BLEND_INV_SRC1_ALPHA
;
322 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
325 case VK_BLEND_OP_ADD
:
326 return V_028760_OPT_COMB_ADD
;
327 case VK_BLEND_OP_SUBTRACT
:
328 return V_028760_OPT_COMB_SUBTRACT
;
329 case VK_BLEND_OP_REVERSE_SUBTRACT
:
330 return V_028760_OPT_COMB_REVSUBTRACT
;
331 case VK_BLEND_OP_MIN
:
332 return V_028760_OPT_COMB_MIN
;
333 case VK_BLEND_OP_MAX
:
334 return V_028760_OPT_COMB_MAX
;
336 return V_028760_OPT_COMB_BLEND_DISABLED
;
340 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
343 case VK_BLEND_FACTOR_ZERO
:
344 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
345 case VK_BLEND_FACTOR_ONE
:
346 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
347 case VK_BLEND_FACTOR_SRC_COLOR
:
348 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
349 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
350 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
351 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
352 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
353 case VK_BLEND_FACTOR_SRC_ALPHA
:
354 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
355 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
356 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
358 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
359 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
361 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
366 * Get rid of DST in the blend factors by commuting the operands:
367 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
369 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
370 unsigned *dst_factor
, unsigned expected_dst
,
371 unsigned replacement_src
)
373 if (*src_factor
== expected_dst
&&
374 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
375 *src_factor
= VK_BLEND_FACTOR_ZERO
;
376 *dst_factor
= replacement_src
;
378 /* Commuting the operands requires reversing subtractions. */
379 if (*func
== VK_BLEND_OP_SUBTRACT
)
380 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
381 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
382 *func
= VK_BLEND_OP_SUBTRACT
;
386 static bool si_blend_factor_uses_dst(unsigned factor
)
388 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
389 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
390 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
391 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
392 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
395 static bool is_dual_src(VkBlendFactor factor
)
398 case VK_BLEND_FACTOR_SRC1_COLOR
:
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
400 case VK_BLEND_FACTOR_SRC1_ALPHA
:
401 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
408 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
410 bool blend_need_alpha
)
412 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
413 unsigned format
, ntype
, swap
;
415 /* Alpha is needed for alpha-to-coverage.
416 * Blending may be with or without alpha.
418 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
419 unsigned alpha
= 0; /* exports alpha, but may not support blending */
420 unsigned blend
= 0; /* supports blending, but may not export alpha */
421 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
423 format
= radv_translate_colorformat(vk_format
);
424 ntype
= radv_translate_color_numformat(vk_format
, desc
,
425 vk_format_get_first_non_void_channel(vk_format
));
426 swap
= radv_translate_colorswap(vk_format
, false);
428 /* Choose the SPI color formats. These are required values for Stoney/RB+.
429 * Other chips have multiple choices, though they are not necessarily better.
432 case V_028C70_COLOR_5_6_5
:
433 case V_028C70_COLOR_1_5_5_5
:
434 case V_028C70_COLOR_5_5_5_1
:
435 case V_028C70_COLOR_4_4_4_4
:
436 case V_028C70_COLOR_10_11_11
:
437 case V_028C70_COLOR_11_11_10
:
438 case V_028C70_COLOR_8
:
439 case V_028C70_COLOR_8_8
:
440 case V_028C70_COLOR_8_8_8_8
:
441 case V_028C70_COLOR_10_10_10_2
:
442 case V_028C70_COLOR_2_10_10_10
:
443 if (ntype
== V_028C70_NUMBER_UINT
)
444 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
445 else if (ntype
== V_028C70_NUMBER_SINT
)
446 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
448 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
451 case V_028C70_COLOR_16
:
452 case V_028C70_COLOR_16_16
:
453 case V_028C70_COLOR_16_16_16_16
:
454 if (ntype
== V_028C70_NUMBER_UNORM
||
455 ntype
== V_028C70_NUMBER_SNORM
) {
456 /* UNORM16 and SNORM16 don't support blending */
457 if (ntype
== V_028C70_NUMBER_UNORM
)
458 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
460 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
462 /* Use 32 bits per channel for blending. */
463 if (format
== V_028C70_COLOR_16
) {
464 if (swap
== V_028C70_SWAP_STD
) { /* R */
465 blend
= V_028714_SPI_SHADER_32_R
;
466 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
467 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
468 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
471 } else if (format
== V_028C70_COLOR_16_16
) {
472 if (swap
== V_028C70_SWAP_STD
) { /* RG */
473 blend
= V_028714_SPI_SHADER_32_GR
;
474 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
475 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
476 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
479 } else /* 16_16_16_16 */
480 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
481 } else if (ntype
== V_028C70_NUMBER_UINT
)
482 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
483 else if (ntype
== V_028C70_NUMBER_SINT
)
484 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
485 else if (ntype
== V_028C70_NUMBER_FLOAT
)
486 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
491 case V_028C70_COLOR_32
:
492 if (swap
== V_028C70_SWAP_STD
) { /* R */
493 blend
= normal
= V_028714_SPI_SHADER_32_R
;
494 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
495 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
496 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
501 case V_028C70_COLOR_32_32
:
502 if (swap
== V_028C70_SWAP_STD
) { /* RG */
503 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
504 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
505 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
506 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
511 case V_028C70_COLOR_32_32_32_32
:
512 case V_028C70_COLOR_8_24
:
513 case V_028C70_COLOR_24_8
:
514 case V_028C70_COLOR_X24_8_32_FLOAT
:
515 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
519 unreachable("unhandled blend format");
522 if (blend_enable
&& blend_need_alpha
)
524 else if(blend_need_alpha
)
526 else if(blend_enable
)
533 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
534 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
535 struct radv_blend_state
*blend
)
537 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
538 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
539 unsigned col_format
= 0;
540 unsigned num_targets
;
542 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
545 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
546 cf
= V_028714_SPI_SHADER_ZERO
;
548 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
550 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
552 cf
= si_choose_spi_color_format(attachment
->format
,
554 blend
->need_src_alpha
& (1 << i
));
557 col_format
|= cf
<< (4 * i
);
560 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
561 /* When a subpass doesn't have any color attachments, write the
562 * alpha channel of MRT0 when alpha coverage is enabled because
563 * the depth attachment needs it.
565 col_format
|= V_028714_SPI_SHADER_32_AR
;
568 /* If the i-th target format is set, all previous target formats must
569 * be non-zero to avoid hangs.
571 num_targets
= (util_last_bit(col_format
) + 3) / 4;
572 for (unsigned i
= 0; i
< num_targets
; i
++) {
573 if (!(col_format
& (0xf << (i
* 4)))) {
574 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
578 /* The output for dual source blending should have the same format as
581 if (blend
->mrt0_is_dual_src
)
582 col_format
|= (col_format
& 0xf) << 4;
584 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
585 blend
->spi_shader_col_format
= col_format
;
589 format_is_int8(VkFormat format
)
591 const struct vk_format_description
*desc
= vk_format_description(format
);
592 int channel
= vk_format_get_first_non_void_channel(format
);
594 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
595 desc
->channel
[channel
].size
== 8;
599 format_is_int10(VkFormat format
)
601 const struct vk_format_description
*desc
= vk_format_description(format
);
603 if (desc
->nr_channels
!= 4)
605 for (unsigned i
= 0; i
< 4; i
++) {
606 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
613 * Ordered so that for each i,
614 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
616 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
617 VK_FORMAT_R32_SFLOAT
,
618 VK_FORMAT_R32G32_SFLOAT
,
619 VK_FORMAT_R8G8B8A8_UNORM
,
620 VK_FORMAT_R16G16B16A16_UNORM
,
621 VK_FORMAT_R16G16B16A16_SNORM
,
622 VK_FORMAT_R16G16B16A16_UINT
,
623 VK_FORMAT_R16G16B16A16_SINT
,
624 VK_FORMAT_R32G32B32A32_SFLOAT
,
625 VK_FORMAT_R8G8B8A8_UINT
,
626 VK_FORMAT_R8G8B8A8_SINT
,
627 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
628 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
631 unsigned radv_format_meta_fs_key(VkFormat format
)
633 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
635 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
636 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
637 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
639 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
640 bool is_int8
= format_is_int8(format
);
641 bool is_int10
= format_is_int10(format
);
643 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
647 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
648 unsigned *is_int8
, unsigned *is_int10
)
650 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
651 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
655 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
656 struct radv_render_pass_attachment
*attachment
;
658 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
661 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
663 if (format_is_int8(attachment
->format
))
665 if (format_is_int10(attachment
->format
))
671 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
672 VkBlendOp op
, VkBlendFactor src
,
673 VkBlendFactor dst
, unsigned chanmask
)
675 /* Src factor is allowed when it does not depend on Dst. */
676 static const uint32_t src_allowed
=
677 (1u << VK_BLEND_FACTOR_ONE
) |
678 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
679 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
680 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
681 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
682 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
683 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
684 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
685 (1u << VK_BLEND_FACTOR_ZERO
) |
686 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
687 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
688 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
689 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
690 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
691 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
693 if (dst
== VK_BLEND_FACTOR_ONE
&&
694 (src_allowed
& (1u << src
))) {
695 /* Addition is commutative, but floating point addition isn't
696 * associative: subtle changes can be introduced via different
697 * rounding. Be conservative, only enable for min and max.
699 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
700 blend
->commutative_4bit
|= chanmask
;
704 static struct radv_blend_state
705 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
706 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
707 const struct radv_graphics_pipeline_create_info
*extra
)
709 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
710 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
711 struct radv_blend_state blend
= {0};
712 unsigned mode
= V_028808_CB_NORMAL
;
718 if (extra
&& extra
->custom_blend_mode
) {
719 blend
.single_cb_enable
= true;
720 mode
= extra
->custom_blend_mode
;
722 blend
.cb_color_control
= 0;
723 if (vkblend
->logicOpEnable
)
724 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
726 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
728 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
729 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
730 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
731 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
732 S_028B70_OFFSET_ROUND(1);
734 if (vkms
&& vkms
->alphaToCoverageEnable
) {
735 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
736 blend
.need_src_alpha
|= 0x1;
739 blend
.cb_target_mask
= 0;
740 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
741 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
742 unsigned blend_cntl
= 0;
743 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
744 VkBlendOp eqRGB
= att
->colorBlendOp
;
745 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
746 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
747 VkBlendOp eqA
= att
->alphaBlendOp
;
748 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
749 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
751 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
753 if (!att
->colorWriteMask
)
756 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
757 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
758 if (!att
->blendEnable
) {
759 blend
.cb_blend_control
[i
] = blend_cntl
;
763 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
765 blend
.mrt0_is_dual_src
= true;
767 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
768 srcRGB
= VK_BLEND_FACTOR_ONE
;
769 dstRGB
= VK_BLEND_FACTOR_ONE
;
771 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
772 srcA
= VK_BLEND_FACTOR_ONE
;
773 dstA
= VK_BLEND_FACTOR_ONE
;
776 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
778 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
781 /* Blending optimizations for RB+.
782 * These transformations don't change the behavior.
784 * First, get rid of DST in the blend factors:
785 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
787 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
788 VK_BLEND_FACTOR_DST_COLOR
,
789 VK_BLEND_FACTOR_SRC_COLOR
);
791 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
792 VK_BLEND_FACTOR_DST_COLOR
,
793 VK_BLEND_FACTOR_SRC_COLOR
);
795 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
796 VK_BLEND_FACTOR_DST_ALPHA
,
797 VK_BLEND_FACTOR_SRC_ALPHA
);
799 /* Look up the ideal settings from tables. */
800 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
801 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
802 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
803 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
805 /* Handle interdependencies. */
806 if (si_blend_factor_uses_dst(srcRGB
))
807 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
808 if (si_blend_factor_uses_dst(srcA
))
809 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
811 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
812 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
813 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
814 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
815 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
817 /* Set the final value. */
818 blend
.sx_mrt_blend_opt
[i
] =
819 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
820 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
821 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
822 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
823 S_028760_ALPHA_DST_OPT(dstA_opt
) |
824 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
825 blend_cntl
|= S_028780_ENABLE(1);
827 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
828 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
829 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
830 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
831 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
832 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
833 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
834 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
836 blend
.cb_blend_control
[i
] = blend_cntl
;
838 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
840 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
841 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
842 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
843 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
844 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
845 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
846 blend
.need_src_alpha
|= 1 << i
;
848 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
849 blend
.cb_blend_control
[i
] = 0;
850 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
853 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
854 /* Disable RB+ blend optimizations for dual source blending. */
855 if (blend
.mrt0_is_dual_src
) {
856 for (i
= 0; i
< 8; i
++) {
857 blend
.sx_mrt_blend_opt
[i
] =
858 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
859 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
863 /* RB+ doesn't work with dual source blending, logic op and
866 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
867 mode
== V_028808_CB_RESOLVE
)
868 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
871 if (blend
.cb_target_mask
)
872 blend
.cb_color_control
|= S_028808_MODE(mode
);
874 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
876 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
880 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
883 case VK_STENCIL_OP_KEEP
:
884 return V_02842C_STENCIL_KEEP
;
885 case VK_STENCIL_OP_ZERO
:
886 return V_02842C_STENCIL_ZERO
;
887 case VK_STENCIL_OP_REPLACE
:
888 return V_02842C_STENCIL_REPLACE_TEST
;
889 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
890 return V_02842C_STENCIL_ADD_CLAMP
;
891 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
892 return V_02842C_STENCIL_SUB_CLAMP
;
893 case VK_STENCIL_OP_INVERT
:
894 return V_02842C_STENCIL_INVERT
;
895 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
896 return V_02842C_STENCIL_ADD_WRAP
;
897 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
898 return V_02842C_STENCIL_SUB_WRAP
;
904 static uint32_t si_translate_fill(VkPolygonMode func
)
907 case VK_POLYGON_MODE_FILL
:
908 return V_028814_X_DRAW_TRIANGLES
;
909 case VK_POLYGON_MODE_LINE
:
910 return V_028814_X_DRAW_LINES
;
911 case VK_POLYGON_MODE_POINT
:
912 return V_028814_X_DRAW_POINTS
;
915 return V_028814_X_DRAW_POINTS
;
919 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
921 uint32_t num_samples
= vkms
->rasterizationSamples
;
922 uint32_t ps_iter_samples
= 1;
924 if (vkms
->sampleShadingEnable
) {
925 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
926 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
928 return ps_iter_samples
;
932 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
934 return pCreateInfo
->depthTestEnable
&&
935 pCreateInfo
->depthWriteEnable
&&
936 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
940 radv_writes_stencil(const VkStencilOpState
*state
)
942 return state
->writeMask
&&
943 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
944 state
->passOp
!= VK_STENCIL_OP_KEEP
||
945 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
949 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
951 return pCreateInfo
->stencilTestEnable
&&
952 (radv_writes_stencil(&pCreateInfo
->front
) ||
953 radv_writes_stencil(&pCreateInfo
->back
));
957 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
959 return radv_is_depth_write_enabled(pCreateInfo
) ||
960 radv_is_stencil_write_enabled(pCreateInfo
);
964 radv_order_invariant_stencil_op(VkStencilOp op
)
966 /* REPLACE is normally order invariant, except when the stencil
967 * reference value is written by the fragment shader. Tracking this
968 * interaction does not seem worth the effort, so be conservative.
970 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
971 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
972 op
!= VK_STENCIL_OP_REPLACE
;
976 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
978 /* Compute whether, assuming Z writes are disabled, this stencil state
979 * is order invariant in the sense that the set of passing fragments as
980 * well as the final stencil buffer result does not depend on the order
983 return !state
->writeMask
||
984 /* The following assumes that Z writes are disabled. */
985 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
986 radv_order_invariant_stencil_op(state
->passOp
) &&
987 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
988 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
989 radv_order_invariant_stencil_op(state
->failOp
));
993 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
994 struct radv_blend_state
*blend
,
995 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
997 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
998 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
999 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1001 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1004 /* Be conservative if a logic operation is enabled with color buffers. */
1005 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
1008 /* Default depth/stencil invariance when no attachment is bound. */
1009 struct radv_dsa_order_invariance dsa_order_invariant
= {
1010 .zs
= true, .pass_set
= true
1013 if (pCreateInfo
->pDepthStencilState
&&
1014 subpass
->depth_stencil_attachment
) {
1015 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
1016 pCreateInfo
->pDepthStencilState
;
1017 struct radv_render_pass_attachment
*attachment
=
1018 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1019 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1020 struct radv_dsa_order_invariance order_invariance
[2];
1021 struct radv_shader_variant
*ps
=
1022 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1024 /* Compute depth/stencil order invariance in order to know if
1025 * it's safe to enable out-of-order.
1027 bool zfunc_is_ordered
=
1028 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1029 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1030 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1031 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1032 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1034 bool nozwrite_and_order_invariant_stencil
=
1035 !radv_is_ds_write_enabled(vkds
) ||
1036 (!radv_is_depth_write_enabled(vkds
) &&
1037 radv_order_invariant_stencil_state(&vkds
->front
) &&
1038 radv_order_invariant_stencil_state(&vkds
->back
));
1040 order_invariance
[1].zs
=
1041 nozwrite_and_order_invariant_stencil
||
1042 (!radv_is_stencil_write_enabled(vkds
) &&
1044 order_invariance
[0].zs
=
1045 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1047 order_invariance
[1].pass_set
=
1048 nozwrite_and_order_invariant_stencil
||
1049 (!radv_is_stencil_write_enabled(vkds
) &&
1050 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1051 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1052 order_invariance
[0].pass_set
=
1053 !radv_is_depth_write_enabled(vkds
) ||
1054 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1055 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1057 dsa_order_invariant
= order_invariance
[has_stencil
];
1058 if (!dsa_order_invariant
.zs
)
1061 /* The set of PS invocations is always order invariant,
1062 * except when early Z/S tests are requested.
1065 ps
->info
.ps
.writes_memory
&&
1066 ps
->info
.ps
.early_fragment_test
&&
1067 !dsa_order_invariant
.pass_set
)
1070 /* Determine if out-of-order rasterization should be disabled
1071 * when occlusion queries are used.
1073 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1074 !dsa_order_invariant
.pass_set
;
1077 /* No color buffers are enabled for writing. */
1081 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1084 /* Only commutative blending. */
1085 if (blendmask
& ~blend
->commutative_4bit
)
1088 if (!dsa_order_invariant
.pass_set
)
1092 if (colormask
& ~blendmask
)
1099 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1100 struct radv_blend_state
*blend
,
1101 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1103 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1104 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1105 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1106 bool out_of_order_rast
= false;
1107 int ps_iter_samples
= 1;
1108 uint32_t mask
= 0xffff;
1111 ms
->num_samples
= vkms
->rasterizationSamples
;
1113 ms
->num_samples
= 1;
1116 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1117 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1118 ps_iter_samples
= ms
->num_samples
;
1121 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1122 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1123 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1124 /* Out-of-order rasterization is explicitly enabled by the
1127 out_of_order_rast
= true;
1129 /* Determine if the driver can enable out-of-order
1130 * rasterization internally.
1133 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1136 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1137 ms
->pa_sc_aa_config
= 0;
1138 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1139 S_028804_INCOHERENT_EQAA_READS(1) |
1140 S_028804_INTERPOLATE_COMP_Z(1) |
1141 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1142 ms
->pa_sc_mode_cntl_1
=
1143 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1144 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1145 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1146 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1148 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1149 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1150 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1151 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1152 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1153 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1154 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1155 S_028A48_VPORT_SCISSOR_ENABLE(1);
1157 if (ms
->num_samples
> 1) {
1158 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1159 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1160 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1161 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1162 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1163 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1164 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1165 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1166 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1167 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1168 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1169 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1170 if (ps_iter_samples
> 1)
1171 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1174 if (vkms
&& vkms
->pSampleMask
) {
1175 mask
= vkms
->pSampleMask
[0] & 0xffff;
1178 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1179 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1183 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1186 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1189 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1190 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1195 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1196 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1197 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1200 unreachable("unhandled primitive type");
1205 si_translate_prim(enum VkPrimitiveTopology topology
)
1208 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1209 return V_008958_DI_PT_POINTLIST
;
1210 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1211 return V_008958_DI_PT_LINELIST
;
1212 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1213 return V_008958_DI_PT_LINESTRIP
;
1214 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1215 return V_008958_DI_PT_TRILIST
;
1216 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1217 return V_008958_DI_PT_TRISTRIP
;
1218 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1219 return V_008958_DI_PT_TRIFAN
;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1221 return V_008958_DI_PT_LINELIST_ADJ
;
1222 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1223 return V_008958_DI_PT_LINESTRIP_ADJ
;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1225 return V_008958_DI_PT_TRILIST_ADJ
;
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1227 return V_008958_DI_PT_TRISTRIP_ADJ
;
1228 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1229 return V_008958_DI_PT_PATCH
;
1237 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1240 case 0: /* GL_POINTS */
1241 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1242 case 1: /* GL_LINES */
1243 case 3: /* GL_LINE_STRIP */
1244 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1245 case 0x8E7A: /* GL_ISOLINES */
1246 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1248 case 4: /* GL_TRIANGLES */
1249 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1250 case 5: /* GL_TRIANGLE_STRIP */
1251 case 7: /* GL_QUADS */
1252 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1260 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1263 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1264 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1265 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1266 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1267 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1268 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1269 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1270 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1273 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1274 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1275 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1276 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1283 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1286 case VK_DYNAMIC_STATE_VIEWPORT
:
1287 return RADV_DYNAMIC_VIEWPORT
;
1288 case VK_DYNAMIC_STATE_SCISSOR
:
1289 return RADV_DYNAMIC_SCISSOR
;
1290 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1291 return RADV_DYNAMIC_LINE_WIDTH
;
1292 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1293 return RADV_DYNAMIC_DEPTH_BIAS
;
1294 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1295 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1296 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1297 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1298 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1299 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1300 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1301 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1302 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1303 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1304 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1305 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1306 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1307 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1309 unreachable("Unhandled dynamic state");
1313 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1315 uint32_t states
= RADV_DYNAMIC_ALL
;
1317 /* If rasterization is disabled we do not care about any of the dynamic states,
1318 * since they are all rasterization related only. */
1319 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1322 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1323 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1325 if (!pCreateInfo
->pDepthStencilState
||
1326 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1327 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1329 if (!pCreateInfo
->pDepthStencilState
||
1330 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1331 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1332 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1333 RADV_DYNAMIC_STENCIL_REFERENCE
);
1335 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1336 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1338 if (!pCreateInfo
->pMultisampleState
||
1339 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1340 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1341 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1343 /* TODO: blend constants & line width. */
1350 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1351 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1353 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1354 uint32_t states
= needed_states
;
1355 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1356 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1358 pipeline
->dynamic_state
= default_dynamic_state
;
1359 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1361 if (pCreateInfo
->pDynamicState
) {
1362 /* Remove all of the states that are marked as dynamic */
1363 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1364 for (uint32_t s
= 0; s
< count
; s
++)
1365 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1368 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1370 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1371 assert(pCreateInfo
->pViewportState
);
1373 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1374 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1375 typed_memcpy(dynamic
->viewport
.viewports
,
1376 pCreateInfo
->pViewportState
->pViewports
,
1377 pCreateInfo
->pViewportState
->viewportCount
);
1381 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1382 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1383 if (states
& RADV_DYNAMIC_SCISSOR
) {
1384 typed_memcpy(dynamic
->scissor
.scissors
,
1385 pCreateInfo
->pViewportState
->pScissors
,
1386 pCreateInfo
->pViewportState
->scissorCount
);
1390 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1391 assert(pCreateInfo
->pRasterizationState
);
1392 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1395 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1396 assert(pCreateInfo
->pRasterizationState
);
1397 dynamic
->depth_bias
.bias
=
1398 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1399 dynamic
->depth_bias
.clamp
=
1400 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1401 dynamic
->depth_bias
.slope
=
1402 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1405 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1407 * pColorBlendState is [...] NULL if the pipeline has rasterization
1408 * disabled or if the subpass of the render pass the pipeline is
1409 * created against does not use any color attachments.
1411 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1412 assert(pCreateInfo
->pColorBlendState
);
1413 typed_memcpy(dynamic
->blend_constants
,
1414 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1417 /* If there is no depthstencil attachment, then don't read
1418 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1419 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1420 * no need to override the depthstencil defaults in
1421 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1423 * Section 9.2 of the Vulkan 1.0.15 spec says:
1425 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1426 * disabled or if the subpass of the render pass the pipeline is created
1427 * against does not use a depth/stencil attachment.
1429 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1430 assert(pCreateInfo
->pDepthStencilState
);
1432 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1433 dynamic
->depth_bounds
.min
=
1434 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1435 dynamic
->depth_bounds
.max
=
1436 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1439 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1440 dynamic
->stencil_compare_mask
.front
=
1441 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1442 dynamic
->stencil_compare_mask
.back
=
1443 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1446 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1447 dynamic
->stencil_write_mask
.front
=
1448 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1449 dynamic
->stencil_write_mask
.back
=
1450 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1453 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1454 dynamic
->stencil_reference
.front
=
1455 pCreateInfo
->pDepthStencilState
->front
.reference
;
1456 dynamic
->stencil_reference
.back
=
1457 pCreateInfo
->pDepthStencilState
->back
.reference
;
1461 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1462 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1463 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1464 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1465 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1466 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1467 discard_rectangle_info
->pDiscardRectangles
,
1468 discard_rectangle_info
->discardRectangleCount
);
1472 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1473 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1474 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1475 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1476 /* If sampleLocationsEnable is VK_FALSE, the default sample
1477 * locations are used and the values specified in
1478 * sampleLocationsInfo are ignored.
1480 if (sample_location_info
->sampleLocationsEnable
) {
1481 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1482 &sample_location_info
->sampleLocationsInfo
;
1484 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1486 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1487 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1488 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1489 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1490 pSampleLocationsInfo
->pSampleLocations
,
1491 pSampleLocationsInfo
->sampleLocationsCount
);
1495 pipeline
->dynamic_state
.mask
= states
;
1499 gfx9_get_gs_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1500 const struct radv_pipeline
*pipeline
,
1502 struct radv_shader_info
*infos
,
1503 struct gfx9_gs_info
*out
)
1505 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1506 struct radv_es_output_info
*es_info
;
1507 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1508 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1510 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1511 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1512 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1514 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1515 bool uses_adjacency
;
1516 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1517 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1518 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1519 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1520 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1521 uses_adjacency
= true;
1524 uses_adjacency
= false;
1528 /* All these are in dwords: */
1529 /* We can't allow using the whole LDS, because GS waves compete with
1530 * other shader stages for LDS space. */
1531 const unsigned max_lds_size
= 8 * 1024;
1532 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1533 unsigned esgs_lds_size
;
1535 /* All these are per subgroup: */
1536 const unsigned max_out_prims
= 32 * 1024;
1537 const unsigned max_es_verts
= 255;
1538 const unsigned ideal_gs_prims
= 64;
1539 unsigned max_gs_prims
, gs_prims
;
1540 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1542 if (uses_adjacency
|| gs_num_invocations
> 1)
1543 max_gs_prims
= 127 / gs_num_invocations
;
1547 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1548 * Make sure we don't go over the maximum value.
1550 if (gs_info
->gs
.vertices_out
> 0) {
1551 max_gs_prims
= MIN2(max_gs_prims
,
1553 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1555 assert(max_gs_prims
> 0);
1557 /* If the primitive has adjacency, halve the number of vertices
1558 * that will be reused in multiple primitives.
1560 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1562 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1563 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1565 /* Compute ESGS LDS size based on the worst case number of ES vertices
1566 * needed to create the target number of GS prims per subgroup.
1568 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1570 /* If total LDS usage is too big, refactor partitions based on ratio
1571 * of ESGS item sizes.
1573 if (esgs_lds_size
> max_lds_size
) {
1574 /* Our target GS Prims Per Subgroup was too large. Calculate
1575 * the maximum number of GS Prims Per Subgroup that will fit
1576 * into LDS, capped by the maximum that the hardware can support.
1578 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1580 assert(gs_prims
> 0);
1581 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1584 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1585 assert(esgs_lds_size
<= max_lds_size
);
1588 /* Now calculate remaining ESGS information. */
1590 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1592 es_verts
= max_es_verts
;
1594 /* Vertices for adjacency primitives are not always reused, so restore
1595 * it for ES_VERTS_PER_SUBGRP.
1597 min_es_verts
= gs_info
->gs
.vertices_in
;
1599 /* For normal primitives, the VGT only checks if they are past the ES
1600 * verts per subgroup after allocating a full GS primitive and if they
1601 * are, kick off a new subgroup. But if those additional ES verts are
1602 * unique (e.g. not reused) we need to make sure there is enough LDS
1603 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1605 es_verts
-= min_es_verts
- 1;
1607 uint32_t es_verts_per_subgroup
= es_verts
;
1608 uint32_t gs_prims_per_subgroup
= gs_prims
;
1609 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1610 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1611 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1612 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1613 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1614 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1615 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1616 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1617 assert(max_prims_per_subgroup
<= max_out_prims
);
1620 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1621 unsigned min_verts_per_prim
, bool use_adjacency
)
1623 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1626 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1630 radv_get_num_input_vertices(nir_shader
**nir
)
1632 if (nir
[MESA_SHADER_GEOMETRY
]) {
1633 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1635 return gs
->info
.gs
.vertices_in
;
1638 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1639 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1641 if (tes
->info
.tess
.point_mode
)
1643 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1652 gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1653 struct radv_pipeline
*pipeline
,
1655 struct radv_shader_info
*infos
,
1656 struct gfx10_ngg_info
*ngg
)
1658 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1659 struct radv_es_output_info
*es_info
=
1660 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1661 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1662 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1663 unsigned min_verts_per_prim
=
1664 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1665 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1666 bool uses_adjacency
;
1667 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1668 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1669 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1670 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1671 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1672 uses_adjacency
= true;
1675 uses_adjacency
= false;
1679 /* All these are in dwords: */
1680 /* We can't allow using the whole LDS, because GS waves compete with
1681 * other shader stages for LDS space.
1683 * TODO: We should really take the shader's internal LDS use into
1684 * account. The linker will fail if the size is greater than
1687 const unsigned max_lds_size
= 8 * 1024 - 768;
1688 const unsigned target_lds_size
= max_lds_size
;
1689 unsigned esvert_lds_size
= 0;
1690 unsigned gsprim_lds_size
= 0;
1692 /* All these are per subgroup: */
1693 bool max_vert_out_per_gs_instance
= false;
1694 unsigned max_esverts_base
= 256;
1695 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1697 /* Hardware has the following non-natural restrictions on the value
1698 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1700 * - at most 252 for any line input primitive type
1701 * - at most 251 for any quad input primitive type
1702 * - at most 251 for triangle strips with adjacency (this happens to
1703 * be the natural limit for triangle *lists* with adjacency)
1705 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1707 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1708 unsigned max_out_verts_per_gsprim
=
1709 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1711 if (max_out_verts_per_gsprim
<= 256) {
1712 if (max_out_verts_per_gsprim
) {
1713 max_gsprims_base
= MIN2(max_gsprims_base
,
1714 256 / max_out_verts_per_gsprim
);
1717 /* Use special multi-cycling mode in which each GS
1718 * instance gets its own subgroup. Does not work with
1720 max_vert_out_per_gs_instance
= true;
1721 max_gsprims_base
= 1;
1722 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1725 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1726 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1729 /* LDS size for passing data from GS to ES. */
1730 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1731 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1732 : &infos
[MESA_SHADER_VERTEX
].so
;
1734 if (so_info
->num_outputs
)
1735 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1737 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1738 * corresponding to the ES thread of the provoking vertex. All
1739 * ES threads load and export PrimitiveID for their thread.
1741 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1742 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1743 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1746 unsigned max_gsprims
= max_gsprims_base
;
1747 unsigned max_esverts
= max_esverts_base
;
1749 if (esvert_lds_size
)
1750 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1751 if (gsprim_lds_size
)
1752 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1754 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1755 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1756 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1758 if (esvert_lds_size
|| gsprim_lds_size
) {
1759 /* Now that we have a rough proportionality between esverts
1760 * and gsprims based on the primitive type, scale both of them
1761 * down simultaneously based on required LDS space.
1763 * We could be smarter about this if we knew how much vertex
1766 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1767 max_gsprims
* gsprim_lds_size
;
1768 if (lds_total
> target_lds_size
) {
1769 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1770 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1772 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1773 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1774 min_verts_per_prim
, uses_adjacency
);
1775 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1779 /* Round up towards full wave sizes for better ALU utilization. */
1780 if (!max_vert_out_per_gs_instance
) {
1781 const unsigned wavesize
= pipeline
->device
->physical_device
->ge_wave_size
;
1782 unsigned orig_max_esverts
;
1783 unsigned orig_max_gsprims
;
1785 orig_max_esverts
= max_esverts
;
1786 orig_max_gsprims
= max_gsprims
;
1788 max_esverts
= align(max_esverts
, wavesize
);
1789 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1790 if (esvert_lds_size
)
1791 max_esverts
= MIN2(max_esverts
,
1792 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1794 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1796 max_gsprims
= align(max_gsprims
, wavesize
);
1797 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1798 if (gsprim_lds_size
)
1799 max_gsprims
= MIN2(max_gsprims
,
1800 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1802 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1803 min_verts_per_prim
, uses_adjacency
);
1804 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1805 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1808 /* Hardware restriction: minimum value of max_esverts */
1809 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1811 unsigned max_out_vertices
=
1812 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1813 gs_type
== MESA_SHADER_GEOMETRY
?
1814 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1816 assert(max_out_vertices
<= 256);
1818 unsigned prim_amp_factor
= 1;
1819 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1820 /* Number of output primitives per GS input primitive after
1822 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1825 /* The GE only checks against the maximum number of ES verts after
1826 * allocating a full GS primitive. So we need to ensure that whenever
1827 * this check passes, there is enough space for a full primitive without
1830 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1831 ngg
->max_gsprims
= max_gsprims
;
1832 ngg
->max_out_verts
= max_out_vertices
;
1833 ngg
->prim_amp_factor
= prim_amp_factor
;
1834 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1835 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1836 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1838 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1839 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1841 ngg
->vgt_esgs_ring_itemsize
= 1;
1844 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1846 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1850 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1851 const struct gfx9_gs_info
*gs
)
1853 struct radv_device
*device
= pipeline
->device
;
1854 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1855 unsigned wave_size
= 64;
1856 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1857 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1858 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1860 unsigned gs_vertex_reuse
=
1861 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1862 unsigned alignment
= 256 * num_se
;
1863 /* The maximum size is 63.999 MB per SE. */
1864 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1865 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1867 /* Calculate the minimum size. */
1868 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1869 wave_size
, alignment
);
1870 /* These are recommended sizes, not minimum sizes. */
1871 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1872 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1873 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1874 gs_info
->gs
.max_gsvs_emit_size
;
1876 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1877 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1878 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1880 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1881 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1883 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1886 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1889 /* If tessellation is all offchip and on-chip GS isn't used, this
1890 * workaround is not needed.
1894 /* SPI barrier management bug:
1895 * Make sure we have at least 4k of LDS in use to avoid the bug.
1896 * It applies to workgroup sizes of more than one wavefront.
1898 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1899 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1900 *lds_size
= MAX2(*lds_size
, 8);
1903 struct radv_shader_variant
*
1904 radv_get_shader(struct radv_pipeline
*pipeline
,
1905 gl_shader_stage stage
)
1907 if (stage
== MESA_SHADER_VERTEX
) {
1908 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1909 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1910 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1911 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1912 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1913 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1914 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1915 if (!radv_pipeline_has_tess(pipeline
))
1917 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1918 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1919 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1920 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1922 return pipeline
->shaders
[stage
];
1925 static struct radv_tessellation_state
1926 calculate_tess_state(struct radv_pipeline
*pipeline
,
1927 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1929 unsigned num_tcs_input_cp
;
1930 unsigned num_tcs_output_cp
;
1932 unsigned num_patches
;
1933 struct radv_tessellation_state tess
= {0};
1935 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1936 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1937 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1939 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1941 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1942 assert(lds_size
<= 65536);
1943 lds_size
= align(lds_size
, 512) / 512;
1945 assert(lds_size
<= 32768);
1946 lds_size
= align(lds_size
, 256) / 256;
1948 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1950 tess
.lds_size
= lds_size
;
1952 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1953 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1954 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1955 tess
.num_patches
= num_patches
;
1957 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1958 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1960 switch (tes
->info
.tes
.primitive_mode
) {
1962 type
= V_028B6C_TESS_TRIANGLE
;
1965 type
= V_028B6C_TESS_QUAD
;
1968 type
= V_028B6C_TESS_ISOLINE
;
1972 switch (tes
->info
.tes
.spacing
) {
1973 case TESS_SPACING_EQUAL
:
1974 partitioning
= V_028B6C_PART_INTEGER
;
1976 case TESS_SPACING_FRACTIONAL_ODD
:
1977 partitioning
= V_028B6C_PART_FRAC_ODD
;
1979 case TESS_SPACING_FRACTIONAL_EVEN
:
1980 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1986 bool ccw
= tes
->info
.tes
.ccw
;
1987 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1988 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1989 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
1991 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
1994 if (tes
->info
.tes
.point_mode
)
1995 topology
= V_028B6C_OUTPUT_POINT
;
1996 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1997 topology
= V_028B6C_OUTPUT_LINE
;
1999 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2001 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2003 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2004 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2005 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2006 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2008 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2010 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2012 tess
.tf_param
= S_028B6C_TYPE(type
) |
2013 S_028B6C_PARTITIONING(partitioning
) |
2014 S_028B6C_TOPOLOGY(topology
) |
2015 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2020 static const struct radv_prim_vertex_count prim_size_table
[] = {
2021 [V_008958_DI_PT_NONE
] = {0, 0},
2022 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2023 [V_008958_DI_PT_LINELIST
] = {2, 2},
2024 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2025 [V_008958_DI_PT_TRILIST
] = {3, 3},
2026 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2027 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2028 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2029 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2030 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2031 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2032 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2033 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2034 [V_008958_DI_PT_POLYGON
] = {3, 1},
2035 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2038 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2040 if (radv_pipeline_has_gs(pipeline
))
2041 if (radv_pipeline_has_ngg(pipeline
))
2042 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2044 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2045 else if (radv_pipeline_has_tess(pipeline
))
2046 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2048 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2052 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2054 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2055 int shader_count
= 0;
2057 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2058 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2060 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2061 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2063 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2064 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2066 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2067 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2069 if(shaders
[MESA_SHADER_VERTEX
]) {
2070 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2073 if (shader_count
> 1) {
2074 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2075 unsigned last
= ordered_shaders
[0]->info
.stage
;
2077 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2078 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2079 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2081 for (int i
= 0; i
< shader_count
; ++i
) {
2082 nir_variable_mode mask
= 0;
2084 if (ordered_shaders
[i
]->info
.stage
!= first
)
2085 mask
= mask
| nir_var_shader_in
;
2087 if (ordered_shaders
[i
]->info
.stage
!= last
)
2088 mask
= mask
| nir_var_shader_out
;
2090 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2091 radv_optimize_nir(ordered_shaders
[i
], false, false);
2095 for (int i
= 1; i
< shader_count
; ++i
) {
2096 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2097 ordered_shaders
[i
- 1]);
2099 if (nir_link_opt_varyings(ordered_shaders
[i
],
2100 ordered_shaders
[i
- 1]))
2101 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2103 nir_remove_dead_variables(ordered_shaders
[i
],
2104 nir_var_shader_out
);
2105 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2108 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2109 ordered_shaders
[i
- 1]);
2111 nir_compact_varyings(ordered_shaders
[i
],
2112 ordered_shaders
[i
- 1], true);
2115 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2116 ac_lower_indirect_derefs(ordered_shaders
[i
],
2117 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2119 radv_optimize_nir(ordered_shaders
[i
], false, false);
2121 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2122 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2123 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2125 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2131 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2132 uint32_t attrib_binding
)
2134 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2135 const VkVertexInputBindingDescription
*input_binding
=
2136 &input_state
->pVertexBindingDescriptions
[i
];
2138 if (input_binding
->binding
== attrib_binding
)
2139 return input_binding
->stride
;
2145 static struct radv_pipeline_key
2146 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2147 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2148 const struct radv_blend_state
*blend
,
2149 bool has_view_index
)
2151 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2152 pCreateInfo
->pVertexInputState
;
2153 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2154 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2156 struct radv_pipeline_key key
;
2157 memset(&key
, 0, sizeof(key
));
2159 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2160 key
.optimisations_disabled
= 1;
2162 key
.has_multiview_view_index
= has_view_index
;
2164 uint32_t binding_input_rate
= 0;
2165 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2166 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2167 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2168 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2169 binding_input_rate
|= 1u << binding
;
2170 instance_rate_divisors
[binding
] = 1;
2173 if (divisor_state
) {
2174 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2175 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2176 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2180 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2181 const VkVertexInputAttributeDescription
*desc
=
2182 &input_state
->pVertexAttributeDescriptions
[i
];
2183 const struct vk_format_description
*format_desc
;
2184 unsigned location
= desc
->location
;
2185 unsigned binding
= desc
->binding
;
2186 unsigned num_format
, data_format
;
2189 if (binding_input_rate
& (1u << binding
)) {
2190 key
.instance_rate_inputs
|= 1u << location
;
2191 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2194 format_desc
= vk_format_description(desc
->format
);
2195 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2197 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2198 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2200 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2201 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2202 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2203 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2205 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2206 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2207 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2210 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2211 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2212 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2214 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2215 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2216 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2218 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2219 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2220 adjust
= RADV_ALPHA_ADJUST_SINT
;
2226 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2229 switch (desc
->format
) {
2230 case VK_FORMAT_B8G8R8A8_UNORM
:
2231 case VK_FORMAT_B8G8R8A8_SNORM
:
2232 case VK_FORMAT_B8G8R8A8_USCALED
:
2233 case VK_FORMAT_B8G8R8A8_SSCALED
:
2234 case VK_FORMAT_B8G8R8A8_UINT
:
2235 case VK_FORMAT_B8G8R8A8_SINT
:
2236 case VK_FORMAT_B8G8R8A8_SRGB
:
2237 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2238 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2239 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2240 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2241 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2242 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2243 key
.vertex_post_shuffle
|= 1 << location
;
2250 if (pCreateInfo
->pTessellationState
)
2251 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2254 if (pCreateInfo
->pMultisampleState
&&
2255 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
2256 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
2257 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
2258 key
.num_samples
= num_samples
;
2259 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2262 key
.col_format
= blend
->spi_shader_col_format
;
2263 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2264 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2266 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2267 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2273 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2275 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2276 bool uses_xfb
= !!xfb
;
2283 radv_fill_shader_keys(struct radv_device
*device
,
2284 struct radv_shader_variant_key
*keys
,
2285 const struct radv_pipeline_key
*key
,
2288 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2289 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2290 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2291 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2292 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2293 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2294 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2295 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2296 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2298 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2300 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2301 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2302 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2303 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2304 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2306 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2309 if (nir
[MESA_SHADER_GEOMETRY
]) {
2310 if (nir
[MESA_SHADER_TESS_CTRL
])
2311 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2313 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2316 if (device
->physical_device
->use_ngg
) {
2317 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2318 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2320 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2323 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2324 nir
[MESA_SHADER_GEOMETRY
] &&
2325 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2326 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2327 /* Fallback to the legacy path if tessellation is
2328 * enabled with extreme geometry because
2329 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2332 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2336 * Disable NGG with geometry shaders. There are a bunch of
2338 * * GS primitives in pipeline statistic queries do not get
2339 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2340 * * General issues with the last primitive missing/corrupt:
2341 * https://bugs.freedesktop.org/show_bug.cgi?id=111248
2343 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2345 if (nir
[MESA_SHADER_GEOMETRY
]) {
2346 if (nir
[MESA_SHADER_TESS_CTRL
])
2347 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2349 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2352 if (!device
->physical_device
->use_ngg_streamout
) {
2353 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2355 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2360 if (nir
[last_xfb_stage
] &&
2361 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
])) {
2362 if (nir
[MESA_SHADER_TESS_CTRL
])
2363 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2365 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2370 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2371 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2373 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2374 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2375 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2376 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2377 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2381 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2382 struct radv_shader_variant_key
*keys
,
2383 struct radv_shader_info
*infos
,
2386 unsigned active_stages
= 0;
2387 unsigned filled_stages
= 0;
2389 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2391 active_stages
|= (1 << i
);
2394 if (nir
[MESA_SHADER_FRAGMENT
]) {
2395 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2396 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2398 &keys
[MESA_SHADER_FRAGMENT
],
2399 &infos
[MESA_SHADER_FRAGMENT
]);
2401 /* TODO: These are no longer used as keys we should refactor this */
2402 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2403 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2404 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2405 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2406 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2407 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2408 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2409 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2410 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2411 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2412 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2413 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2415 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2418 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2419 nir
[MESA_SHADER_TESS_CTRL
]) {
2420 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2421 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2422 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2424 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2426 for (int i
= 0; i
< 2; i
++) {
2427 radv_nir_shader_info_pass(combined_nir
[i
],
2428 pipeline
->layout
, &key
,
2429 &infos
[MESA_SHADER_TESS_CTRL
]);
2432 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2433 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2434 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2435 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2437 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2438 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2441 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2442 nir
[MESA_SHADER_GEOMETRY
]) {
2443 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2444 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2446 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2448 for (int i
= 0; i
< 2; i
++) {
2449 radv_nir_shader_info_pass(combined_nir
[i
],
2452 &infos
[MESA_SHADER_GEOMETRY
]);
2455 filled_stages
|= (1 << pre_stage
);
2456 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2459 active_stages
^= filled_stages
;
2460 while (active_stages
) {
2461 int i
= u_bit_scan(&active_stages
);
2463 if (i
== MESA_SHADER_TESS_CTRL
) {
2464 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2465 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2468 if (i
== MESA_SHADER_TESS_EVAL
) {
2469 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2470 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2471 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2472 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2475 radv_nir_shader_info_init(&infos
[i
]);
2476 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2477 &keys
[i
], &infos
[i
]);
2482 merge_tess_info(struct shader_info
*tes_info
,
2483 const struct shader_info
*tcs_info
)
2485 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2487 * "PointMode. Controls generation of points rather than triangles
2488 * or lines. This functionality defaults to disabled, and is
2489 * enabled if either shader stage includes the execution mode.
2491 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2492 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2493 * and OutputVertices, it says:
2495 * "One mode must be set in at least one of the tessellation
2498 * So, the fields can be set in either the TCS or TES, but they must
2499 * agree if set in both. Our backend looks at TES, so bitwise-or in
2500 * the values from the TCS.
2502 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2503 tes_info
->tess
.tcs_vertices_out
== 0 ||
2504 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2505 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2507 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2508 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2509 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2510 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2512 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2513 tes_info
->tess
.primitive_mode
== 0 ||
2514 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2515 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2516 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2517 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2521 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2526 if (ext
->pPipelineCreationFeedback
) {
2527 ext
->pPipelineCreationFeedback
->flags
= 0;
2528 ext
->pPipelineCreationFeedback
->duration
= 0;
2531 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2532 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2533 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2538 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2543 feedback
->duration
-= radv_get_current_time();
2544 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2548 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2553 feedback
->duration
+= radv_get_current_time();
2554 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2555 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2559 bool radv_aco_supported_stage(gl_shader_stage stage
, bool has_gs
, bool has_ts
)
2561 return (stage
== MESA_SHADER_VERTEX
&& !has_gs
&& !has_ts
) ||
2562 stage
== MESA_SHADER_FRAGMENT
||
2563 stage
== MESA_SHADER_COMPUTE
;
2567 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2568 struct radv_device
*device
,
2569 struct radv_pipeline_cache
*cache
,
2570 const struct radv_pipeline_key
*key
,
2571 const VkPipelineShaderStageCreateInfo
**pStages
,
2572 const VkPipelineCreateFlags flags
,
2573 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2574 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2575 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2577 struct radv_shader_module fs_m
= {0};
2578 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2579 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2580 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2581 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2582 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2583 unsigned char hash
[20], gs_copy_hash
[20];
2584 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2586 radv_start_feedback(pipeline_feedback
);
2588 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2590 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2591 if (modules
[i
]->nir
)
2592 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2593 strlen(modules
[i
]->nir
->info
.name
),
2596 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2600 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2601 memcpy(gs_copy_hash
, hash
, 20);
2602 gs_copy_hash
[0] ^= 1;
2604 bool found_in_application_cache
= true;
2605 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2606 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2607 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2608 &found_in_application_cache
);
2609 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2612 if (!keep_executable_info
&&
2613 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2614 &found_in_application_cache
) &&
2615 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2616 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2620 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2622 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2623 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2624 fs_m
.nir
= fs_b
.shader
;
2625 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2628 bool has_gs
= modules
[MESA_SHADER_GEOMETRY
];
2629 bool has_ts
= modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
];
2630 bool use_aco
= device
->physical_device
->use_aco
;
2632 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2633 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2638 radv_start_feedback(stage_feedbacks
[i
]);
2640 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2641 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2642 stage
? stage
->pName
: "main", i
,
2643 stage
? stage
->pSpecializationInfo
: NULL
,
2644 flags
, pipeline
->layout
, aco
);
2646 /* We don't want to alter meta shaders IR directly so clone it
2649 if (nir
[i
]->info
.name
) {
2650 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2653 radv_stop_feedback(stage_feedbacks
[i
], false);
2656 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2657 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2658 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2661 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2662 radv_link_shaders(pipeline
, nir
);
2664 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2666 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2667 nir_lower_non_uniform_ubo_access
|
2668 nir_lower_non_uniform_ssbo_access
|
2669 nir_lower_non_uniform_texture_access
|
2670 nir_lower_non_uniform_image_access
);
2672 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2674 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2677 if (radv_can_dump_shader(device
, modules
[i
], false))
2678 nir_print_shader(nir
[i
], stderr
);
2681 if (nir
[MESA_SHADER_FRAGMENT
])
2682 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2684 radv_fill_shader_keys(device
, keys
, key
, nir
);
2686 radv_fill_shader_info(pipeline
, keys
, infos
, nir
);
2688 if ((nir
[MESA_SHADER_VERTEX
] &&
2689 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2690 (nir
[MESA_SHADER_TESS_EVAL
] &&
2691 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2692 struct gfx10_ngg_info
*ngg_info
;
2694 if (nir
[MESA_SHADER_GEOMETRY
])
2695 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2696 else if (nir
[MESA_SHADER_TESS_CTRL
])
2697 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2699 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2701 gfx10_get_ngg_info(pCreateInfo
, pipeline
, nir
, infos
, ngg_info
);
2702 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2703 struct gfx9_gs_info
*gs_info
=
2704 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2706 gfx9_get_gs_info(pCreateInfo
, pipeline
, nir
, infos
, gs_info
);
2709 if (nir
[MESA_SHADER_FRAGMENT
]) {
2710 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2711 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2713 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_FRAGMENT
, has_gs
, has_ts
);
2714 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2715 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2716 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2717 infos
+ MESA_SHADER_FRAGMENT
,
2718 keep_executable_info
, aco
,
2719 &binaries
[MESA_SHADER_FRAGMENT
]);
2721 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2724 /* TODO: These are no longer used as keys we should refactor this */
2725 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2726 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2727 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2728 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2729 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2730 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2731 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2732 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2733 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2734 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2735 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2736 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2739 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2740 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2741 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2742 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2743 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2745 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2747 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2749 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2750 false, &binaries
[MESA_SHADER_TESS_CTRL
]);
2752 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2754 modules
[MESA_SHADER_VERTEX
] = NULL
;
2755 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2756 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2759 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2760 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2761 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2762 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2764 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2766 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2768 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2769 false, &binaries
[MESA_SHADER_GEOMETRY
]);
2771 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2773 modules
[pre_stage
] = NULL
;
2776 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2777 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2778 if (i
== MESA_SHADER_TESS_CTRL
) {
2779 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2781 if (i
== MESA_SHADER_TESS_EVAL
) {
2782 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2783 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2786 radv_start_feedback(stage_feedbacks
[i
]);
2788 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2789 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2791 keys
+ i
, infos
+ i
,keep_executable_info
,
2794 radv_stop_feedback(stage_feedbacks
[i
], false);
2798 if(modules
[MESA_SHADER_GEOMETRY
]) {
2799 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2800 if (!pipeline
->gs_copy_shader
&&
2801 !radv_pipeline_has_ngg(pipeline
)) {
2802 struct radv_shader_info info
= {};
2803 struct radv_shader_variant_key key
= {};
2805 key
.has_multiview_view_index
=
2806 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2808 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2809 pipeline
->layout
, &key
,
2812 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2813 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2814 &gs_copy_binary
, keep_executable_info
,
2815 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2818 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2819 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2820 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2822 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2823 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2825 radv_pipeline_cache_insert_shaders(device
, cache
,
2830 free(gs_copy_binary
);
2833 if (!keep_executable_info
) {
2834 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2838 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2841 ralloc_free(nir
[i
]);
2843 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2844 radv_shader_dump_stats(device
,
2845 pipeline
->shaders
[i
],
2851 ralloc_free(fs_m
.nir
);
2853 radv_stop_feedback(pipeline_feedback
, false);
2857 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2858 gl_shader_stage stage
, enum chip_class chip_class
)
2860 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2861 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2862 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2865 case MESA_SHADER_FRAGMENT
:
2866 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2867 case MESA_SHADER_VERTEX
:
2869 if (chip_class
>= GFX10
) {
2870 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2871 } else if (chip_class
== GFX9
) {
2872 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2874 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2880 if (chip_class
>= GFX10
) {
2881 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2883 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2888 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2890 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2891 case MESA_SHADER_GEOMETRY
:
2892 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2893 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2894 case MESA_SHADER_COMPUTE
:
2895 return R_00B900_COMPUTE_USER_DATA_0
;
2896 case MESA_SHADER_TESS_CTRL
:
2897 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2898 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2899 case MESA_SHADER_TESS_EVAL
:
2901 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
2902 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2903 } else if (has_ngg
) {
2904 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2906 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2909 unreachable("unknown shader");
2913 struct radv_bin_size_entry
{
2919 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2921 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2925 /* One shader engine */
2931 { UINT_MAX
, { 0, 0}},
2934 /* Two shader engines */
2940 { UINT_MAX
, { 0, 0}},
2943 /* Four shader engines */
2948 { UINT_MAX
, { 0, 0}},
2954 /* One shader engine */
2960 { UINT_MAX
, { 0, 0}},
2963 /* Two shader engines */
2969 { UINT_MAX
, { 0, 0}},
2972 /* Four shader engines */
2979 { UINT_MAX
, { 0, 0}},
2985 /* One shader engine */
2992 { UINT_MAX
, { 0, 0}},
2995 /* Two shader engines */
3003 { UINT_MAX
, { 0, 0}},
3006 /* Four shader engines */
3014 { UINT_MAX
, { 0, 0}},
3018 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3022 // One shader engine
3029 { UINT_MAX
, { 0, 0}},
3032 // Two shader engines
3040 { UINT_MAX
, { 0, 0}},
3043 // Four shader engines
3051 { UINT_MAX
, { 0, 0}},
3057 // One shader engine
3065 { UINT_MAX
, { 0, 0}},
3068 // Two shader engines
3077 { UINT_MAX
, { 0, 0}},
3080 // Four shader engines
3089 { UINT_MAX
, { 0, 0}},
3095 // One shader engine
3103 { UINT_MAX
, { 0, 0}},
3106 // Two shader engines
3115 { UINT_MAX
, { 0, 0}},
3118 // Four shader engines
3126 { UINT_MAX
, { 0, 0}},
3131 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3132 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3133 VkExtent2D extent
= {512, 512};
3135 unsigned log_num_rb_per_se
=
3136 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3137 pipeline
->device
->physical_device
->rad_info
.max_se
);
3138 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3140 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3141 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3142 unsigned effective_samples
= total_samples
;
3143 unsigned color_bytes_per_pixel
= 0;
3145 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3147 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3148 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3151 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3154 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3155 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3158 /* MSAA images typically don't use all samples all the time. */
3159 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3160 effective_samples
= 2;
3161 color_bytes_per_pixel
*= effective_samples
;
3164 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3165 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3168 extent
= color_entry
->extent
;
3170 if (subpass
->depth_stencil_attachment
) {
3171 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3173 /* Coefficients taken from AMDVLK */
3174 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3175 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3176 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3178 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3179 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3182 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3183 extent
= ds_entry
->extent
;
3190 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3192 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3193 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3194 VkExtent2D extent
= {512, 512};
3196 const unsigned db_tag_size
= 64;
3197 const unsigned db_tag_count
= 312;
3198 const unsigned color_tag_size
= 1024;
3199 const unsigned color_tag_count
= 31;
3200 const unsigned fmask_tag_size
= 256;
3201 const unsigned fmask_tag_count
= 44;
3203 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3204 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3206 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3207 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3208 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3210 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3211 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3213 unsigned color_bytes_per_pixel
= 0;
3214 unsigned fmask_bytes_per_pixel
= 0;
3216 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3218 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3219 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3222 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3225 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3226 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3228 if (total_samples
> 1) {
3229 assert(samples_log
<= 3);
3230 const unsigned fmask_array
[] = {0, 1, 1, 4};
3231 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3235 color_bytes_per_pixel
*= total_samples
;
3237 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3239 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3240 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3241 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3243 if (fmask_bytes_per_pixel
) {
3244 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3246 const VkExtent2D fmask_extent
= (VkExtent2D
){
3247 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3248 .height
= 1ull << (color_pixel_count_log
/ 2)
3251 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3252 extent
= fmask_extent
;
3255 if (subpass
->depth_stencil_attachment
) {
3256 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3258 /* Coefficients taken from AMDVLK */
3259 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3260 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3261 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3263 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3265 const VkExtent2D db_extent
= (VkExtent2D
){
3266 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3267 .height
= 1ull << (color_pixel_count_log
/ 2)
3270 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3274 extent
.width
= MAX2(extent
.width
, 128);
3275 extent
.height
= MAX2(extent
.width
, 64);
3281 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3282 struct radv_pipeline
*pipeline
,
3283 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3285 uint32_t pa_sc_binner_cntl_0
=
3286 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3287 S_028C44_DISABLE_START_OF_PRIM(1);
3288 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3290 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3291 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3292 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3293 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3294 unsigned min_bytes_per_pixel
= 0;
3297 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3298 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3301 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3304 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3305 unsigned bytes
= vk_format_get_blocksize(format
);
3306 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3307 min_bytes_per_pixel
= bytes
;
3311 pa_sc_binner_cntl_0
=
3312 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3313 S_028C44_BIN_SIZE_X(0) |
3314 S_028C44_BIN_SIZE_Y(0) |
3315 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3316 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3317 S_028C44_DISABLE_START_OF_PRIM(1);
3320 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3321 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3325 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3326 struct radv_pipeline
*pipeline
,
3327 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3328 const struct radv_blend_state
*blend
)
3330 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3333 VkExtent2D bin_size
;
3334 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3335 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3336 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3337 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3339 unreachable("Unhandled generation for binning bin size calculation");
3341 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3342 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
3343 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
3344 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
3346 if (pipeline
->device
->physical_device
->rad_info
.has_dedicated_vram
) {
3347 context_states_per_bin
= 1;
3348 persistent_states_per_bin
= 1;
3349 fpovs_per_batch
= 63;
3351 /* The context states are affected by the scissor bug. */
3352 context_states_per_bin
= pipeline
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
? 1 : 6;
3353 /* 32 causes hangs for RAVEN. */
3354 persistent_states_per_bin
= 16;
3355 fpovs_per_batch
= 63;
3358 bool disable_start_of_prim
= true;
3359 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3361 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3363 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3364 !ps
->info
.ps
.can_discard
&&
3365 !ps
->info
.ps
.writes_memory
&&
3366 blend
->cb_target_enabled_4bit
) {
3367 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3368 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3371 const uint32_t pa_sc_binner_cntl_0
=
3372 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3373 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3374 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3375 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3376 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3377 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
3378 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
3379 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3380 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
3381 S_028C44_OPTIMAL_BIN_SELECTION(1);
3383 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3384 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3386 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3391 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3392 struct radv_pipeline
*pipeline
,
3393 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3394 const struct radv_graphics_pipeline_create_info
*extra
)
3396 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
3397 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3398 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3399 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3400 struct radv_render_pass_attachment
*attachment
= NULL
;
3401 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3402 uint32_t db_render_control
= 0, db_render_override2
= 0;
3403 uint32_t db_render_override
= 0;
3405 if (subpass
->depth_stencil_attachment
)
3406 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3408 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3409 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3411 if (vkds
&& has_depth_attachment
) {
3412 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3413 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3414 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3415 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3417 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3418 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3421 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3422 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3423 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3424 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3425 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3426 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3428 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3429 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3430 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3431 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3434 if (attachment
&& extra
) {
3435 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3436 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3438 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3439 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3440 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3441 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3442 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3445 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3446 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3448 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3449 ps
->info
.ps
.writes_z
) {
3450 /* From VK_EXT_depth_range_unrestricted spec:
3452 * "The behavior described in Primitive Clipping still applies.
3453 * If depth clamping is disabled the depth values are still
3454 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3455 * depth clamping is enabled the above equation is ignored and
3456 * the depth values are instead clamped to the VkViewport
3457 * minDepth and maxDepth values, which in the case of this
3458 * extension can be outside of the 0.0 to 1.0 range."
3460 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3463 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3464 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3466 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3467 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3468 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3472 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3473 struct radv_pipeline
*pipeline
,
3474 const struct radv_blend_state
*blend
)
3476 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3477 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3479 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3480 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3482 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3484 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3485 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3488 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3490 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3491 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3493 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3494 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3497 static const VkConservativeRasterizationModeEXT
3498 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3500 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3501 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3503 if (!conservative_raster
)
3504 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3505 return conservative_raster
->conservativeRasterizationMode
;
3509 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3510 struct radv_pipeline
*pipeline
,
3511 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3513 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3514 const VkConservativeRasterizationModeEXT mode
=
3515 radv_get_conservative_raster_mode(vkraster
);
3516 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3517 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3519 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3520 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3521 if (depth_clip_state
) {
3522 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3525 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3526 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3527 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3528 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3529 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3530 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3532 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3533 S_0286D4_FLAT_SHADE_ENA(1) |
3534 S_0286D4_PNT_SPRITE_ENA(1) |
3535 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3536 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3537 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3538 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3539 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3541 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3542 S_028BE4_PIX_CENTER(1) | // TODO verify
3543 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3544 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3546 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3547 S_028814_FACE(vkraster
->frontFace
) |
3548 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3549 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3550 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3551 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3552 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3553 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3554 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3555 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3557 /* Conservative rasterization. */
3558 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3559 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3561 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3562 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3563 S_028804_OVERRASTERIZATION_AMOUNT(4);
3565 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3566 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3567 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3569 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3570 pa_sc_conservative_rast
|=
3571 S_028C4C_OVER_RAST_ENABLE(1) |
3572 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3573 S_028C4C_UNDER_RAST_ENABLE(0) |
3574 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3575 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3577 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3578 pa_sc_conservative_rast
|=
3579 S_028C4C_OVER_RAST_ENABLE(0) |
3580 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3581 S_028C4C_UNDER_RAST_ENABLE(1) |
3582 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3583 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3587 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3588 pa_sc_conservative_rast
);
3593 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3594 struct radv_pipeline
*pipeline
)
3596 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3598 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3599 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3600 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3602 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3603 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3605 /* The exclusion bits can be set to improve rasterization efficiency
3606 * if no sample lies on the pixel boundary (-8 sample offset). It's
3607 * currently always TRUE because the driver doesn't support 16 samples.
3609 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3610 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3611 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3612 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3616 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3617 struct radv_pipeline
*pipeline
)
3619 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3620 const struct radv_shader_variant
*vs
=
3621 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3622 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3623 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3624 unsigned vgt_primitiveid_en
= 0;
3625 uint32_t vgt_gs_mode
= 0;
3627 if (radv_pipeline_has_ngg(pipeline
))
3630 if (radv_pipeline_has_gs(pipeline
)) {
3631 const struct radv_shader_variant
*gs
=
3632 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3634 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3635 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3636 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3637 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3638 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3641 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3642 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3646 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3647 struct radeon_cmdbuf
*cs
,
3648 struct radv_pipeline
*pipeline
,
3649 struct radv_shader_variant
*shader
)
3651 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3653 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3654 radeon_emit(cs
, va
>> 8);
3655 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3656 radeon_emit(cs
, shader
->config
.rsrc1
);
3657 radeon_emit(cs
, shader
->config
.rsrc2
);
3659 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3660 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3661 clip_dist_mask
= outinfo
->clip_dist_mask
;
3662 cull_dist_mask
= outinfo
->cull_dist_mask
;
3663 total_mask
= clip_dist_mask
| cull_dist_mask
;
3664 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3665 outinfo
->writes_layer
||
3666 outinfo
->writes_viewport_index
;
3667 unsigned spi_vs_out_config
, nparams
;
3669 /* VS is required to export at least one param. */
3670 nparams
= MAX2(outinfo
->param_exports
, 1);
3671 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3673 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3674 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3677 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3679 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3680 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3681 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3682 V_02870C_SPI_SHADER_4COMP
:
3683 V_02870C_SPI_SHADER_NONE
) |
3684 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3685 V_02870C_SPI_SHADER_4COMP
:
3686 V_02870C_SPI_SHADER_NONE
) |
3687 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3688 V_02870C_SPI_SHADER_4COMP
:
3689 V_02870C_SPI_SHADER_NONE
));
3691 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3692 S_028818_VTX_W0_FMT(1) |
3693 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3694 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3695 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3697 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3698 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3699 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3700 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3701 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3702 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3703 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3704 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3705 cull_dist_mask
<< 8 |
3708 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3709 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3710 outinfo
->writes_viewport_index
);
3714 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3715 struct radv_pipeline
*pipeline
,
3716 struct radv_shader_variant
*shader
)
3718 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3720 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3721 radeon_emit(cs
, va
>> 8);
3722 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3723 radeon_emit(cs
, shader
->config
.rsrc1
);
3724 radeon_emit(cs
, shader
->config
.rsrc2
);
3728 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3729 struct radv_pipeline
*pipeline
,
3730 struct radv_shader_variant
*shader
,
3731 const struct radv_tessellation_state
*tess
)
3733 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3734 uint32_t rsrc2
= shader
->config
.rsrc2
;
3736 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3737 radeon_emit(cs
, va
>> 8);
3738 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3740 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3741 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3742 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3743 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3745 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3746 radeon_emit(cs
, shader
->config
.rsrc1
);
3747 radeon_emit(cs
, rsrc2
);
3751 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3752 struct radeon_cmdbuf
*cs
,
3753 struct radv_pipeline
*pipeline
,
3754 struct radv_shader_variant
*shader
)
3756 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3757 gl_shader_stage es_type
=
3758 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3759 struct radv_shader_variant
*es
=
3760 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3761 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3763 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3764 radeon_emit(cs
, va
>> 8);
3765 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3766 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3767 radeon_emit(cs
, shader
->config
.rsrc1
);
3768 radeon_emit(cs
, shader
->config
.rsrc2
);
3770 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3771 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3772 clip_dist_mask
= outinfo
->clip_dist_mask
;
3773 cull_dist_mask
= outinfo
->cull_dist_mask
;
3774 total_mask
= clip_dist_mask
| cull_dist_mask
;
3775 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3776 outinfo
->writes_layer
||
3777 outinfo
->writes_viewport_index
;
3778 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3779 (es
&& es
->info
.uses_prim_id
);
3780 bool break_wave_at_eoi
= false;
3784 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3785 struct radv_shader_variant
*gs
=
3786 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3788 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3789 break_wave_at_eoi
= true;
3792 nparams
= MAX2(outinfo
->param_exports
, 1);
3793 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3794 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3795 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3797 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3798 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3799 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3800 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3801 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3802 V_02870C_SPI_SHADER_4COMP
:
3803 V_02870C_SPI_SHADER_NONE
) |
3804 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3805 V_02870C_SPI_SHADER_4COMP
:
3806 V_02870C_SPI_SHADER_NONE
) |
3807 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3808 V_02870C_SPI_SHADER_4COMP
:
3809 V_02870C_SPI_SHADER_NONE
));
3811 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3812 S_028818_VTX_W0_FMT(1) |
3813 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3814 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3815 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3816 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3817 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3818 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3819 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3820 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3821 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3822 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3823 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3824 cull_dist_mask
<< 8 |
3827 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3828 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3829 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
));
3831 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3832 ngg_state
->vgt_esgs_ring_itemsize
);
3834 /* NGG specific registers. */
3835 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3836 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3838 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3839 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3840 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3841 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3842 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3843 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3844 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3845 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3846 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3847 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3848 S_028B90_CNT(gs_num_invocations
) |
3849 S_028B90_ENABLE(gs_num_invocations
> 1) |
3850 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3852 /* User edge flags are set by the pos exports. If user edge flags are
3853 * not used, we must use hw-generated edge flags and pass them via
3854 * the prim export to prevent drawing lines on internal edges of
3855 * decomposed primitives (such as quads) with polygon mode = lines.
3857 * TODO: We should combine hw-generated edge flags with user edge
3858 * flags in the shader.
3860 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3861 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3862 !radv_pipeline_has_gs(pipeline
)));
3864 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3865 S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
) |
3866 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
3868 /* Bug workaround for a possible hang with non-tessellation cases.
3869 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3871 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3873 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3874 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3875 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3876 !radv_pipeline_has_tess(pipeline
) &&
3877 ngg_state
->hw_max_esverts
!= 256) {
3878 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
3880 if (ngg_state
->hw_max_esverts
> 5) {
3881 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
3885 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
3889 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3890 struct radv_pipeline
*pipeline
,
3891 struct radv_shader_variant
*shader
,
3892 const struct radv_tessellation_state
*tess
)
3894 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3896 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3897 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
3899 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3900 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
3902 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
3905 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3906 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3907 radeon_emit(cs
, va
>> 8);
3908 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3910 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
3911 radeon_emit(cs
, va
>> 8);
3912 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
3915 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
3916 radeon_emit(cs
, shader
->config
.rsrc1
);
3917 radeon_emit(cs
, hs_rsrc2
);
3919 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
3920 radeon_emit(cs
, va
>> 8);
3921 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
3922 radeon_emit(cs
, shader
->config
.rsrc1
);
3923 radeon_emit(cs
, shader
->config
.rsrc2
);
3928 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
3929 struct radeon_cmdbuf
*cs
,
3930 struct radv_pipeline
*pipeline
,
3931 const struct radv_tessellation_state
*tess
)
3933 struct radv_shader_variant
*vs
;
3935 /* Skip shaders merged into HS/GS */
3936 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
3940 if (vs
->info
.vs
.as_ls
)
3941 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
3942 else if (vs
->info
.vs
.as_es
)
3943 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
3944 else if (vs
->info
.is_ngg
)
3945 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
3947 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
3951 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
3952 struct radeon_cmdbuf
*cs
,
3953 struct radv_pipeline
*pipeline
,
3954 const struct radv_tessellation_state
*tess
)
3956 if (!radv_pipeline_has_tess(pipeline
))
3959 struct radv_shader_variant
*tes
, *tcs
;
3961 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
3962 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
3965 if (tes
->info
.is_ngg
) {
3966 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
3967 } else if (tes
->info
.tes
.as_es
)
3968 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
3970 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
3973 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
3975 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
3978 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3979 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
3980 tess
->ls_hs_config
);
3982 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
3983 tess
->ls_hs_config
);
3985 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
3986 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
3987 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3988 S_028A44_ES_VERTS_PER_SUBGRP(250) |
3989 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
3990 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
3995 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
3996 struct radeon_cmdbuf
*cs
,
3997 struct radv_pipeline
*pipeline
,
3998 struct radv_shader_variant
*gs
)
4000 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4001 unsigned gs_max_out_vertices
;
4002 uint8_t *num_components
;
4007 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4008 max_stream
= gs
->info
.gs
.max_stream
;
4009 num_components
= gs
->info
.gs
.num_stream_output_components
;
4011 offset
= num_components
[0] * gs_max_out_vertices
;
4013 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4014 radeon_emit(ctx_cs
, offset
);
4015 if (max_stream
>= 1)
4016 offset
+= num_components
[1] * gs_max_out_vertices
;
4017 radeon_emit(ctx_cs
, offset
);
4018 if (max_stream
>= 2)
4019 offset
+= num_components
[2] * gs_max_out_vertices
;
4020 radeon_emit(ctx_cs
, offset
);
4021 if (max_stream
>= 3)
4022 offset
+= num_components
[3] * gs_max_out_vertices
;
4023 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4025 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4026 radeon_emit(ctx_cs
, num_components
[0]);
4027 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4028 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4029 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4031 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4032 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4033 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4034 S_028B90_ENABLE(gs_num_invocations
> 0));
4036 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4037 gs_state
->vgt_esgs_ring_itemsize
);
4039 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4041 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4042 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4043 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4044 radeon_emit(cs
, va
>> 8);
4045 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4047 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4048 radeon_emit(cs
, va
>> 8);
4049 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4052 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4053 radeon_emit(cs
, gs
->config
.rsrc1
);
4054 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4056 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4057 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4059 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4060 radeon_emit(cs
, va
>> 8);
4061 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4062 radeon_emit(cs
, gs
->config
.rsrc1
);
4063 radeon_emit(cs
, gs
->config
.rsrc2
);
4066 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4070 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4071 struct radeon_cmdbuf
*cs
,
4072 struct radv_pipeline
*pipeline
)
4074 struct radv_shader_variant
*gs
;
4076 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4080 if (gs
->info
.is_ngg
)
4081 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4083 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4085 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4086 gs
->info
.gs
.vertices_out
);
4089 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
4091 uint32_t ps_input_cntl
;
4092 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4093 ps_input_cntl
= S_028644_OFFSET(offset
);
4095 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4097 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4098 S_028644_ATTR0_VALID(1);
4101 /* The input is a DEFAULT_VAL constant. */
4102 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4103 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4104 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4105 ps_input_cntl
= S_028644_OFFSET(0x20) |
4106 S_028644_DEFAULT_VAL(offset
);
4108 return ps_input_cntl
;
4112 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4113 struct radv_pipeline
*pipeline
)
4115 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4116 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4117 uint32_t ps_input_cntl
[32];
4119 unsigned ps_offset
= 0;
4121 if (ps
->info
.ps
.prim_id_input
) {
4122 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4123 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4124 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4129 if (ps
->info
.ps
.layer_input
||
4130 ps
->info
.needs_multiview_view_index
) {
4131 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4132 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4133 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4135 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
4139 if (ps
->info
.ps
.has_pcoord
) {
4141 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4142 ps_input_cntl
[ps_offset
] = val
;
4146 if (ps
->info
.ps
.num_input_clips_culls
) {
4149 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4150 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4151 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4155 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4156 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4157 ps
->info
.ps
.num_input_clips_culls
> 4) {
4158 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4163 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4167 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4170 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4171 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4172 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4177 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4178 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4180 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
4185 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4186 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4187 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4193 radv_compute_db_shader_control(const struct radv_device
*device
,
4194 const struct radv_pipeline
*pipeline
,
4195 const struct radv_shader_variant
*ps
)
4198 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4199 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4201 z_order
= V_02880C_LATE_Z
;
4203 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4204 !device
->physical_device
->rad_info
.rbplus_allowed
;
4206 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4207 * but this appears to break Project Cars (DXVK). See
4208 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4210 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4212 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4213 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4214 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4215 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4216 S_02880C_Z_ORDER(z_order
) |
4217 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4218 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4219 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4220 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4221 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4225 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4226 struct radeon_cmdbuf
*cs
,
4227 struct radv_pipeline
*pipeline
)
4229 struct radv_shader_variant
*ps
;
4231 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4233 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4234 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4236 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4237 radeon_emit(cs
, va
>> 8);
4238 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4239 radeon_emit(cs
, ps
->config
.rsrc1
);
4240 radeon_emit(cs
, ps
->config
.rsrc2
);
4242 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4243 radv_compute_db_shader_control(pipeline
->device
,
4246 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4247 ps
->config
.spi_ps_input_ena
);
4249 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4250 ps
->config
.spi_ps_input_addr
);
4252 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4253 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4254 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4256 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4258 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4259 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4260 ps
->info
.ps
.writes_stencil
,
4261 ps
->info
.ps
.writes_sample_mask
));
4263 if (pipeline
->device
->dfsm_allowed
) {
4264 /* optimise this? */
4265 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4266 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4271 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4272 struct radv_pipeline
*pipeline
)
4274 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4275 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4278 unsigned vtx_reuse_depth
= 30;
4279 if (radv_pipeline_has_tess(pipeline
) &&
4280 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4281 vtx_reuse_depth
= 14;
4283 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4284 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4288 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4290 uint32_t stages
= 0;
4291 if (radv_pipeline_has_tess(pipeline
)) {
4292 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4293 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4295 if (radv_pipeline_has_gs(pipeline
))
4296 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4298 else if (radv_pipeline_has_ngg(pipeline
))
4299 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4301 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4302 } else if (radv_pipeline_has_gs(pipeline
)) {
4303 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4305 } else if (radv_pipeline_has_ngg(pipeline
)) {
4306 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4309 if (radv_pipeline_has_ngg(pipeline
)) {
4310 stages
|= S_028B54_PRIMGEN_EN(1);
4311 if (pipeline
->streamout_shader
)
4312 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4313 } else if (radv_pipeline_has_gs(pipeline
)) {
4314 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4317 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4318 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4320 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4321 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4323 if (radv_pipeline_has_tess(pipeline
))
4324 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4326 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4327 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4328 if (pipeline
->gs_copy_shader
)
4329 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4330 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4331 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4332 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4333 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4335 if (radv_pipeline_has_ngg(pipeline
))
4338 /* legacy GS only supports Wave64 */
4339 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4340 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4341 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4348 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4350 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4351 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4353 if (!discard_rectangle_info
)
4358 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4359 /* Interpret i as a bitmask, and then set the bit in the mask if
4360 * that combination of rectangles in which the pixel is contained
4361 * should pass the cliprect test. */
4362 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4364 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4368 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4379 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4380 struct radv_pipeline
*pipeline
,
4381 const struct radv_tessellation_state
*tess
)
4383 bool break_wave_at_eoi
= false;
4384 unsigned primgroup_size
;
4385 unsigned vertgroup_size
;
4387 if (radv_pipeline_has_tess(pipeline
)) {
4388 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4390 } else if (radv_pipeline_has_gs(pipeline
)) {
4391 const struct gfx9_gs_info
*gs_state
=
4392 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4393 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4394 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4395 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4397 primgroup_size
= 128; /* recommended without a GS and tess */
4401 if (radv_pipeline_has_tess(pipeline
)) {
4402 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4403 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4404 break_wave_at_eoi
= true;
4407 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4408 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4409 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4410 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4411 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4415 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4416 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4417 const struct radv_graphics_pipeline_create_info
*extra
,
4418 const struct radv_blend_state
*blend
,
4419 const struct radv_tessellation_state
*tess
,
4420 unsigned prim
, unsigned gs_out
)
4422 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4423 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4426 ctx_cs
->max_dw
= 256;
4427 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4428 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4430 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4431 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4432 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4433 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4434 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4435 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4436 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4437 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4438 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4439 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4440 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4441 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4443 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4444 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4446 radeon_set_context_reg(ctx_cs
, R_0286E8_SPI_TMPRING_SIZE
,
4447 S_0286E8_WAVES(pipeline
->max_waves
) |
4448 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
4450 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4452 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4453 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4454 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4456 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4458 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4460 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4462 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4464 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4465 assert(cs
->cdw
<= cs
->max_dw
);
4468 static struct radv_ia_multi_vgt_param_helpers
4469 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4470 const struct radv_tessellation_state
*tess
,
4473 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4474 const struct radv_device
*device
= pipeline
->device
;
4476 if (radv_pipeline_has_tess(pipeline
))
4477 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4478 else if (radv_pipeline_has_gs(pipeline
))
4479 ia_multi_vgt_param
.primgroup_size
= 64;
4481 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4483 /* GS requirement. */
4484 ia_multi_vgt_param
.partial_es_wave
= false;
4485 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4486 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4487 ia_multi_vgt_param
.partial_es_wave
= true;
4489 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4490 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4491 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4492 * 4 shader engines. Set 1 to pass the assertion below.
4493 * The other cases are hardware requirements. */
4494 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4495 prim
== V_008958_DI_PT_POLYGON
||
4496 prim
== V_008958_DI_PT_LINELOOP
||
4497 prim
== V_008958_DI_PT_TRIFAN
||
4498 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4499 (pipeline
->graphics
.prim_restart_enable
&&
4500 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4501 (prim
!= V_008958_DI_PT_POINTLIST
&&
4502 prim
!= V_008958_DI_PT_LINESTRIP
))))
4503 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4506 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4507 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4508 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4509 if (radv_pipeline_has_gs(pipeline
) &&
4510 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4511 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4512 if (radv_pipeline_has_tess(pipeline
)) {
4513 /* SWITCH_ON_EOI must be set if PrimID is used. */
4514 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4515 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4516 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4519 ia_multi_vgt_param
.partial_vs_wave
= false;
4520 if (radv_pipeline_has_tess(pipeline
)) {
4521 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4522 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4523 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4524 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4525 radv_pipeline_has_gs(pipeline
))
4526 ia_multi_vgt_param
.partial_vs_wave
= true;
4527 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4528 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4529 if (radv_pipeline_has_gs(pipeline
)) {
4530 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4531 ia_multi_vgt_param
.partial_es_wave
= true;
4533 ia_multi_vgt_param
.partial_vs_wave
= true;
4538 /* Workaround for a VGT hang when strip primitive types are used with
4539 * primitive restart.
4541 if (pipeline
->graphics
.prim_restart_enable
&&
4542 (prim
== V_008958_DI_PT_LINESTRIP
||
4543 prim
== V_008958_DI_PT_TRISTRIP
||
4544 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4545 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4546 ia_multi_vgt_param
.partial_vs_wave
= true;
4549 if (radv_pipeline_has_gs(pipeline
)) {
4550 /* On these chips there is the possibility of a hang if the
4551 * pipeline uses a GS and partial_vs_wave is not set.
4553 * This mostly does not hit 4-SE chips, as those typically set
4554 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4555 * with GS due to another workaround.
4557 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4559 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4560 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4561 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4562 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4563 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4564 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4565 ia_multi_vgt_param
.partial_vs_wave
= true;
4569 ia_multi_vgt_param
.base
=
4570 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4571 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4572 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4573 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4574 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4576 return ia_multi_vgt_param
;
4581 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4582 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4584 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4585 pCreateInfo
->pVertexInputState
;
4586 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4588 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4589 const VkVertexInputAttributeDescription
*desc
=
4590 &vi_info
->pVertexAttributeDescriptions
[i
];
4591 unsigned loc
= desc
->location
;
4592 const struct vk_format_description
*format_desc
;
4594 format_desc
= vk_format_description(desc
->format
);
4596 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4599 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4600 const VkVertexInputBindingDescription
*desc
=
4601 &vi_info
->pVertexBindingDescriptions
[i
];
4603 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4604 pipeline
->num_vertex_bindings
=
4605 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4609 static struct radv_shader_variant
*
4610 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4614 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4615 struct radv_shader_variant
*shader
=
4616 radv_get_shader(pipeline
, i
);
4618 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4626 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4627 struct radv_device
*device
,
4628 struct radv_pipeline_cache
*cache
,
4629 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4630 const struct radv_graphics_pipeline_create_info
*extra
)
4633 bool has_view_index
= false;
4635 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4636 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4637 if (subpass
->view_mask
)
4638 has_view_index
= true;
4640 pipeline
->device
= device
;
4641 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4642 assert(pipeline
->layout
);
4644 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4646 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4647 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4648 radv_init_feedback(creation_feedback
);
4650 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4652 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4653 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4654 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4655 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4656 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4657 if(creation_feedback
)
4658 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4661 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4662 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
, pipeline_feedback
, stage_feedbacks
);
4664 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4665 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4667 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
4669 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4671 if (radv_pipeline_has_gs(pipeline
)) {
4672 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4673 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4674 } else if (radv_pipeline_has_tess(pipeline
)) {
4675 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4676 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4678 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4679 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4681 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4683 if (extra
&& extra
->use_rectlist
) {
4684 prim
= V_008958_DI_PT_RECTLIST
;
4685 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4686 pipeline
->graphics
.can_use_guardband
= true;
4687 if (radv_pipeline_has_ngg(pipeline
))
4688 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4690 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4691 /* prim vertex count will need TESS changes */
4692 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
4694 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
4696 /* Ensure that some export memory is always allocated, for two reasons:
4698 * 1) Correctness: The hardware ignores the EXEC mask if no export
4699 * memory is allocated, so KILL and alpha test do not work correctly
4701 * 2) Performance: Every shader needs at least a NULL export, even when
4702 * it writes no color/depth output. The NULL export instruction
4703 * stalls without this setting.
4705 * Don't add this to CB_SHADER_MASK.
4707 * GFX10 supports pixel shaders without exports by setting both the
4708 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4709 * instructions if any are present.
4711 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4712 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4713 ps
->info
.ps
.can_discard
) &&
4714 !blend
.spi_shader_col_format
) {
4715 if (!ps
->info
.ps
.writes_z
&&
4716 !ps
->info
.ps
.writes_stencil
&&
4717 !ps
->info
.ps
.writes_sample_mask
)
4718 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4721 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4722 if (pipeline
->shaders
[i
]) {
4723 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4727 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4728 struct radv_shader_variant
*gs
=
4729 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4731 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4734 struct radv_tessellation_state tess
= {0};
4735 if (radv_pipeline_has_tess(pipeline
)) {
4736 if (prim
== V_008958_DI_PT_PATCH
) {
4737 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
4738 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
4740 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4743 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
4745 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4747 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4748 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4750 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4751 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4752 if (loc
->sgpr_idx
!= -1) {
4753 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4754 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4755 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4756 pipeline
->graphics
.vtx_emit_num
= 3;
4758 pipeline
->graphics
.vtx_emit_num
= 2;
4761 /* Find the last vertex shader stage that eventually uses streamout. */
4762 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4764 result
= radv_pipeline_scratch_init(device
, pipeline
);
4765 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
4771 radv_graphics_pipeline_create(
4773 VkPipelineCache _cache
,
4774 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4775 const struct radv_graphics_pipeline_create_info
*extra
,
4776 const VkAllocationCallbacks
*pAllocator
,
4777 VkPipeline
*pPipeline
)
4779 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4780 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4781 struct radv_pipeline
*pipeline
;
4784 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
4785 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4786 if (pipeline
== NULL
)
4787 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4789 result
= radv_pipeline_init(pipeline
, device
, cache
,
4790 pCreateInfo
, extra
);
4791 if (result
!= VK_SUCCESS
) {
4792 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4796 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4801 VkResult
radv_CreateGraphicsPipelines(
4803 VkPipelineCache pipelineCache
,
4805 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4806 const VkAllocationCallbacks
* pAllocator
,
4807 VkPipeline
* pPipelines
)
4809 VkResult result
= VK_SUCCESS
;
4812 for (; i
< count
; i
++) {
4814 r
= radv_graphics_pipeline_create(_device
,
4817 NULL
, pAllocator
, &pPipelines
[i
]);
4818 if (r
!= VK_SUCCESS
) {
4820 pPipelines
[i
] = VK_NULL_HANDLE
;
4829 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
4831 struct radv_shader_variant
*compute_shader
;
4832 struct radv_device
*device
= pipeline
->device
;
4833 unsigned threads_per_threadgroup
;
4834 unsigned threadgroups_per_cu
= 1;
4835 unsigned waves_per_threadgroup
;
4836 unsigned max_waves_per_sh
= 0;
4839 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
4840 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
4842 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4843 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
4845 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
4846 radeon_emit(&pipeline
->cs
, va
>> 8);
4847 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
4849 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
4850 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
4851 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
4852 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4853 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
4856 radeon_set_sh_reg(&pipeline
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
4857 S_00B860_WAVES(pipeline
->max_waves
) |
4858 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
4860 /* Calculate best compute resource limits. */
4861 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
4862 compute_shader
->info
.cs
.block_size
[1] *
4863 compute_shader
->info
.cs
.block_size
[2];
4864 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
4865 device
->physical_device
->cs_wave_size
);
4867 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4868 waves_per_threadgroup
== 1)
4869 threadgroups_per_cu
= 2;
4871 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
4872 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
4873 waves_per_threadgroup
,
4875 threadgroups_per_cu
));
4877 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4878 radeon_emit(&pipeline
->cs
,
4879 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
4880 radeon_emit(&pipeline
->cs
,
4881 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
4882 radeon_emit(&pipeline
->cs
,
4883 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
4885 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
4888 static VkResult
radv_compute_pipeline_create(
4890 VkPipelineCache _cache
,
4891 const VkComputePipelineCreateInfo
* pCreateInfo
,
4892 const VkAllocationCallbacks
* pAllocator
,
4893 VkPipeline
* pPipeline
)
4895 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4896 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4897 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4898 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4899 struct radv_pipeline
*pipeline
;
4902 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
4903 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4904 if (pipeline
== NULL
)
4905 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4907 pipeline
->device
= device
;
4908 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4909 assert(pipeline
->layout
);
4911 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4912 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4913 radv_init_feedback(creation_feedback
);
4915 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4916 if (creation_feedback
)
4917 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
4919 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
4920 radv_create_shaders(pipeline
, device
, cache
, &(struct radv_pipeline_key
) {0}, pStages
, pCreateInfo
->flags
, NULL
, pipeline_feedback
, stage_feedbacks
);
4922 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
4923 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
4924 result
= radv_pipeline_scratch_init(device
, pipeline
);
4925 if (result
!= VK_SUCCESS
) {
4926 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4930 radv_compute_generate_pm4(pipeline
);
4932 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4937 VkResult
radv_CreateComputePipelines(
4939 VkPipelineCache pipelineCache
,
4941 const VkComputePipelineCreateInfo
* pCreateInfos
,
4942 const VkAllocationCallbacks
* pAllocator
,
4943 VkPipeline
* pPipelines
)
4945 VkResult result
= VK_SUCCESS
;
4948 for (; i
< count
; i
++) {
4950 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
4952 pAllocator
, &pPipelines
[i
]);
4953 if (r
!= VK_SUCCESS
) {
4955 pPipelines
[i
] = VK_NULL_HANDLE
;
4963 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
4966 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
4967 if (!pipeline
->shaders
[i
])
4970 if (i
== MESA_SHADER_GEOMETRY
&&
4971 !radv_pipeline_has_ngg(pipeline
)) {
4981 static struct radv_shader_variant
*
4982 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
4984 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
4985 if (!pipeline
->shaders
[i
])
4989 return pipeline
->shaders
[i
];
4994 if (i
== MESA_SHADER_GEOMETRY
&&
4995 !radv_pipeline_has_ngg(pipeline
)) {
4998 return pipeline
->gs_copy_shader
;
5008 /* Basically strlcpy (which does not exist on linux) specialized for
5010 static void desc_copy(char *desc
, const char *src
) {
5011 int len
= strlen(src
);
5012 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5013 memcpy(desc
, src
, len
);
5014 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5017 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5019 const VkPipelineInfoKHR
* pPipelineInfo
,
5020 uint32_t* pExecutableCount
,
5021 VkPipelineExecutablePropertiesKHR
* pProperties
)
5023 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5024 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5027 *pExecutableCount
= total_count
;
5031 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5032 for (unsigned i
= 0, executable_idx
= 0;
5033 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5034 if (!pipeline
->shaders
[i
])
5036 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5037 const char *name
= NULL
;
5038 const char *description
= NULL
;
5040 case MESA_SHADER_VERTEX
:
5041 name
= "Vertex Shader";
5042 description
= "Vulkan Vertex Shader";
5044 case MESA_SHADER_TESS_CTRL
:
5045 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5046 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5047 name
= "Vertex + Tessellation Control Shaders";
5048 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5050 name
= "Tessellation Control Shader";
5051 description
= "Vulkan Tessellation Control Shader";
5054 case MESA_SHADER_TESS_EVAL
:
5055 name
= "Tessellation Evaluation Shader";
5056 description
= "Vulkan Tessellation Evaluation Shader";
5058 case MESA_SHADER_GEOMETRY
:
5059 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5060 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5061 name
= "Tessellation Evaluation + Geometry Shaders";
5062 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5063 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5064 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5065 name
= "Vertex + Geometry Shader";
5066 description
= "Combined Vulkan Vertex and Geometry Shaders";
5068 name
= "Geometry Shader";
5069 description
= "Vulkan Geometry Shader";
5072 case MESA_SHADER_FRAGMENT
:
5073 name
= "Fragment Shader";
5074 description
= "Vulkan Fragment Shader";
5076 case MESA_SHADER_COMPUTE
:
5077 name
= "Compute Shader";
5078 description
= "Vulkan Compute Shader";
5082 desc_copy(pProperties
[executable_idx
].name
, name
);
5083 desc_copy(pProperties
[executable_idx
].description
, description
);
5086 if (i
== MESA_SHADER_GEOMETRY
&&
5087 !radv_pipeline_has_ngg(pipeline
)) {
5088 assert(pipeline
->gs_copy_shader
);
5089 if (executable_idx
>= count
)
5092 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5093 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5094 desc_copy(pProperties
[executable_idx
].description
,
5095 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5101 for (unsigned i
= 0; i
< count
; ++i
)
5102 pProperties
[i
].subgroupSize
= 64;
5104 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5105 *pExecutableCount
= count
;
5109 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5111 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5112 uint32_t* pStatisticCount
,
5113 VkPipelineExecutableStatisticKHR
* pStatistics
)
5115 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5116 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5117 gl_shader_stage stage
;
5118 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5120 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5121 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5122 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5124 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5125 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5126 VkResult result
= VK_SUCCESS
;
5129 desc_copy(s
->name
, "SGPRs");
5130 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5131 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5132 s
->value
.u64
= shader
->config
.num_sgprs
;
5137 desc_copy(s
->name
, "VGPRs");
5138 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5139 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5140 s
->value
.u64
= shader
->config
.num_vgprs
;
5145 desc_copy(s
->name
, "Spilled SGPRs");
5146 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5147 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5148 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5153 desc_copy(s
->name
, "Spilled VGPRs");
5154 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5155 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5156 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5161 desc_copy(s
->name
, "PrivMem VGPRs");
5162 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5163 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5164 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5169 desc_copy(s
->name
, "Code size");
5170 desc_copy(s
->description
, "Code size in bytes");
5171 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5172 s
->value
.u64
= shader
->exec_size
;
5177 desc_copy(s
->name
, "LDS size");
5178 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5179 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5180 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5185 desc_copy(s
->name
, "Scratch size");
5186 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5187 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5188 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5193 desc_copy(s
->name
, "Subgroups per SIMD");
5194 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5195 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5196 s
->value
.u64
= max_waves
;
5201 *pStatisticCount
= s
- pStatistics
;
5203 *pStatisticCount
= end
- pStatistics
;
5204 result
= VK_INCOMPLETE
;
5206 *pStatisticCount
= s
- pStatistics
;
5212 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5214 size_t total_size
= strlen(src
) + 1;
5217 *data_size
= total_size
;
5221 size_t size
= MIN2(total_size
, *data_size
);
5223 memcpy(data
, src
, size
);
5225 *((char*)data
+ size
- 1) = 0;
5226 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5229 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5231 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5232 uint32_t* pInternalRepresentationCount
,
5233 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5235 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5236 gl_shader_stage stage
;
5237 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5239 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5240 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5241 VkResult result
= VK_SUCCESS
;
5245 desc_copy(p
->name
, "NIR Shader(s)");
5246 desc_copy(p
->description
, "The optimized NIR shader(s)");
5247 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5248 result
= VK_INCOMPLETE
;
5255 if (shader
->aco_used
) {
5256 desc_copy(p
->name
, "ACO IR");
5257 desc_copy(p
->description
, "The ACO IR after some optimizations");
5259 desc_copy(p
->name
, "LLVM IR");
5260 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5262 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5263 result
= VK_INCOMPLETE
;
5270 desc_copy(p
->name
, "Assembly");
5271 desc_copy(p
->description
, "Final Assembly");
5272 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5273 result
= VK_INCOMPLETE
;
5277 if (!pInternalRepresentations
)
5278 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5280 result
= VK_INCOMPLETE
;
5281 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5283 *pInternalRepresentationCount
= p
- pInternalRepresentations
;