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radv: Add support for shaderStorageImageWriteWithoutFormat.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107
108 static void
109 radv_pipeline_destroy(struct radv_device *device,
110 struct radv_pipeline *pipeline,
111 const VkAllocationCallbacks* allocator)
112 {
113 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
114 if (pipeline->shaders[i])
115 radv_shader_variant_destroy(device, pipeline->shaders[i]);
116
117 if (pipeline->gs_copy_shader)
118 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
119
120 vk_free2(&device->alloc, allocator, pipeline);
121 }
122
123 void radv_DestroyPipeline(
124 VkDevice _device,
125 VkPipeline _pipeline,
126 const VkAllocationCallbacks* pAllocator)
127 {
128 RADV_FROM_HANDLE(radv_device, device, _device);
129 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
130
131 if (!_pipeline)
132 return;
133
134 radv_pipeline_destroy(device, pipeline, pAllocator);
135 }
136
137
138 static void
139 radv_optimize_nir(struct nir_shader *shader)
140 {
141 bool progress;
142
143 do {
144 progress = false;
145
146 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
147 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
148 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
149
150 NIR_PASS(progress, shader, nir_copy_prop);
151 NIR_PASS(progress, shader, nir_opt_remove_phis);
152 NIR_PASS(progress, shader, nir_opt_dce);
153 NIR_PASS(progress, shader, nir_opt_dead_cf);
154 NIR_PASS(progress, shader, nir_opt_cse);
155 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
156 NIR_PASS(progress, shader, nir_opt_algebraic);
157 NIR_PASS(progress, shader, nir_opt_constant_folding);
158 NIR_PASS(progress, shader, nir_opt_undef);
159 NIR_PASS(progress, shader, nir_opt_conditional_discard);
160 } while (progress);
161 }
162
163 static nir_shader *
164 radv_shader_compile_to_nir(struct radv_device *device,
165 struct radv_shader_module *module,
166 const char *entrypoint_name,
167 gl_shader_stage stage,
168 const VkSpecializationInfo *spec_info,
169 bool dump)
170 {
171 if (strcmp(entrypoint_name, "main") != 0) {
172 radv_finishme("Multiple shaders per module not really supported");
173 }
174
175 nir_shader *nir;
176 nir_function *entry_point;
177 if (module->nir) {
178 /* Some things such as our meta clear/blit code will give us a NIR
179 * shader directly. In that case, we just ignore the SPIR-V entirely
180 * and just use the NIR shader */
181 nir = module->nir;
182 nir->options = &nir_options;
183 nir_validate_shader(nir);
184
185 assert(exec_list_length(&nir->functions) == 1);
186 struct exec_node *node = exec_list_get_head(&nir->functions);
187 entry_point = exec_node_data(nir_function, node, node);
188 } else {
189 uint32_t *spirv = (uint32_t *) module->data;
190 assert(module->size % 4 == 0);
191
192 uint32_t num_spec_entries = 0;
193 struct nir_spirv_specialization *spec_entries = NULL;
194 if (spec_info && spec_info->mapEntryCount > 0) {
195 num_spec_entries = spec_info->mapEntryCount;
196 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
197 for (uint32_t i = 0; i < num_spec_entries; i++) {
198 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
199 const void *data = spec_info->pData + entry.offset;
200 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
201
202 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
203 if (spec_info->dataSize == 8)
204 spec_entries[i].data64 = *(const uint64_t *)data;
205 else
206 spec_entries[i].data32 = *(const uint32_t *)data;
207 }
208 }
209 const struct nir_spirv_supported_extensions supported_ext = {
210 .draw_parameters = true,
211 .float64 = true,
212 .image_write_without_format = true,
213 };
214 entry_point = spirv_to_nir(spirv, module->size / 4,
215 spec_entries, num_spec_entries,
216 stage, entrypoint_name, &supported_ext, &nir_options);
217 nir = entry_point->shader;
218 assert(nir->stage == stage);
219 nir_validate_shader(nir);
220
221 free(spec_entries);
222
223 /* We have to lower away local constant initializers right before we
224 * inline functions. That way they get properly initialized at the top
225 * of the function and not at the top of its caller.
226 */
227 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
228 NIR_PASS_V(nir, nir_lower_returns);
229 NIR_PASS_V(nir, nir_inline_functions);
230
231 /* Pick off the single entrypoint that we want */
232 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
233 if (func != entry_point)
234 exec_node_remove(&func->node);
235 }
236 assert(exec_list_length(&nir->functions) == 1);
237 entry_point->name = ralloc_strdup(entry_point, "main");
238
239 NIR_PASS_V(nir, nir_remove_dead_variables,
240 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
241
242 /* Now that we've deleted all but the main function, we can go ahead and
243 * lower the rest of the constant initializers.
244 */
245 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
246 NIR_PASS_V(nir, nir_lower_system_values);
247 }
248
249 /* Vulkan uses the separate-shader linking model */
250 nir->info->separate_shader = true;
251
252 // nir = brw_preprocess_nir(compiler, nir);
253
254 nir_shader_gather_info(nir, entry_point->impl);
255
256 nir_variable_mode indirect_mask = 0;
257 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
258 indirect_mask |= nir_var_shader_in;
259 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
260 indirect_mask |= nir_var_local;
261
262 nir_lower_indirect_derefs(nir, indirect_mask);
263
264 static const nir_lower_tex_options tex_options = {
265 .lower_txp = ~0,
266 };
267
268 nir_lower_tex(nir, &tex_options);
269
270 nir_lower_vars_to_ssa(nir);
271 nir_lower_var_copies(nir);
272 nir_lower_global_vars_to_local(nir);
273 nir_remove_dead_variables(nir, nir_var_local);
274 radv_optimize_nir(nir);
275
276 if (dump)
277 nir_print_shader(nir, stderr);
278
279 return nir;
280 }
281
282 static const char *radv_get_shader_name(struct radv_shader_variant *var,
283 gl_shader_stage stage)
284 {
285 switch (stage) {
286 case MESA_SHADER_VERTEX: return var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
287 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
288 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
289 case MESA_SHADER_COMPUTE: return "Compute Shader";
290 default:
291 return "Unknown shader";
292 };
293
294 }
295 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
296 {
297 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
298 struct radv_shader_variant *var;
299 struct ac_shader_config *conf;
300 int i;
301 FILE *file = stderr;
302 unsigned max_simd_waves = 10;
303 unsigned lds_per_wave = 0;
304
305 for (i = 0; i < MESA_SHADER_STAGES; i++) {
306 if (!pipeline->shaders[i])
307 continue;
308 var = pipeline->shaders[i];
309
310 conf = &var->config;
311
312 if (i == MESA_SHADER_FRAGMENT) {
313 lds_per_wave = conf->lds_size * lds_increment +
314 align(var->info.fs.num_interp * 48, lds_increment);
315 }
316
317 if (conf->num_sgprs) {
318 if (device->physical_device->rad_info.chip_class >= VI)
319 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
320 else
321 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
322 }
323
324 if (conf->num_vgprs)
325 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
326
327 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
328 * that PS can use.
329 */
330 if (lds_per_wave)
331 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
332
333 fprintf(file, "\n%s:\n",
334 radv_get_shader_name(var, i));
335 if (i == MESA_SHADER_FRAGMENT) {
336 fprintf(file, "*** SHADER CONFIG ***\n"
337 "SPI_PS_INPUT_ADDR = 0x%04x\n"
338 "SPI_PS_INPUT_ENA = 0x%04x\n",
339 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
340 }
341 fprintf(file, "*** SHADER STATS ***\n"
342 "SGPRS: %d\n"
343 "VGPRS: %d\n"
344 "Spilled SGPRs: %d\n"
345 "Spilled VGPRs: %d\n"
346 "Code Size: %d bytes\n"
347 "LDS: %d blocks\n"
348 "Scratch: %d bytes per wave\n"
349 "Max Waves: %d\n"
350 "********************\n\n\n",
351 conf->num_sgprs, conf->num_vgprs,
352 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
353 conf->lds_size, conf->scratch_bytes_per_wave,
354 max_simd_waves);
355 }
356 }
357
358 void radv_shader_variant_destroy(struct radv_device *device,
359 struct radv_shader_variant *variant)
360 {
361 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
362 return;
363
364 device->ws->buffer_destroy(variant->bo);
365 free(variant);
366 }
367
368 static void radv_fill_shader_variant(struct radv_device *device,
369 struct radv_shader_variant *variant,
370 struct ac_shader_binary *binary,
371 gl_shader_stage stage)
372 {
373 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
374 unsigned vgpr_comp_cnt = 0;
375
376 if (scratch_enabled && !device->llvm_supports_spill)
377 radv_finishme("shader scratch support only available with LLVM 4.0");
378
379 variant->code_size = binary->code_size;
380
381 switch (stage) {
382 case MESA_SHADER_VERTEX:
383 case MESA_SHADER_GEOMETRY:
384 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
385 S_00B12C_SCRATCH_EN(scratch_enabled);
386 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
387 break;
388 case MESA_SHADER_FRAGMENT:
389 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
390 S_00B12C_SCRATCH_EN(scratch_enabled);
391 break;
392 case MESA_SHADER_COMPUTE:
393 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
394 S_00B84C_SCRATCH_EN(scratch_enabled) |
395 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
396 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
397 S_00B84C_TG_SIZE_EN(1) |
398 S_00B84C_LDS_SIZE(variant->config.lds_size);
399 break;
400 default:
401 unreachable("unsupported shader type");
402 break;
403 }
404
405 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
406 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
407 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
408 S_00B848_DX10_CLAMP(1) |
409 S_00B848_FLOAT_MODE(variant->config.float_mode);
410
411 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
412 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
413
414 void *ptr = device->ws->buffer_map(variant->bo);
415 memcpy(ptr, binary->code, binary->code_size);
416 device->ws->buffer_unmap(variant->bo);
417
418
419 }
420
421 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
422 struct nir_shader *shader,
423 struct radv_pipeline_layout *layout,
424 const union ac_shader_variant_key *key,
425 void** code_out,
426 unsigned *code_size_out,
427 bool dump)
428 {
429 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
430 enum radeon_family chip_family = device->physical_device->rad_info.family;
431 LLVMTargetMachineRef tm;
432 if (!variant)
433 return NULL;
434
435 struct ac_nir_compiler_options options = {0};
436 options.layout = layout;
437 if (key)
438 options.key = *key;
439
440 struct ac_shader_binary binary;
441
442 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
443 options.family = chip_family;
444 options.chip_class = device->physical_device->rad_info.chip_class;
445 options.supports_spill = device->llvm_supports_spill;
446 tm = ac_create_target_machine(chip_family, options.supports_spill);
447 ac_compile_nir_shader(tm, &binary, &variant->config,
448 &variant->info, shader, &options, dump);
449 LLVMDisposeTargetMachine(tm);
450
451 radv_fill_shader_variant(device, variant, &binary, shader->stage);
452
453 if (code_out) {
454 *code_out = binary.code;
455 *code_size_out = binary.code_size;
456 } else
457 free(binary.code);
458 free(binary.config);
459 free(binary.rodata);
460 free(binary.global_symbol_offsets);
461 free(binary.relocs);
462 free(binary.disasm_string);
463 variant->ref_count = 1;
464 return variant;
465 }
466
467 static struct radv_shader_variant *
468 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
469 struct nir_shader *nir,
470 void** code_out,
471 unsigned *code_size_out,
472 bool dump_shader)
473 {
474 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
475 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
476 LLVMTargetMachineRef tm;
477 if (!variant)
478 return NULL;
479
480 struct ac_nir_compiler_options options = {0};
481 struct ac_shader_binary binary;
482 options.family = chip_family;
483 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
484 options.supports_spill = pipeline->device->llvm_supports_spill;
485 tm = ac_create_target_machine(chip_family, options.supports_spill);
486 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
487 LLVMDisposeTargetMachine(tm);
488
489 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
490
491 if (code_out) {
492 *code_out = binary.code;
493 *code_size_out = binary.code_size;
494 } else
495 free(binary.code);
496 free(binary.config);
497 free(binary.rodata);
498 free(binary.global_symbol_offsets);
499 free(binary.relocs);
500 free(binary.disasm_string);
501 variant->ref_count = 1;
502 return variant;
503 }
504
505 static struct radv_shader_variant *
506 radv_pipeline_compile(struct radv_pipeline *pipeline,
507 struct radv_pipeline_cache *cache,
508 struct radv_shader_module *module,
509 const char *entrypoint,
510 gl_shader_stage stage,
511 const VkSpecializationInfo *spec_info,
512 struct radv_pipeline_layout *layout,
513 const union ac_shader_variant_key *key)
514 {
515 unsigned char sha1[20];
516 unsigned char gs_copy_sha1[20];
517 struct radv_shader_variant *variant;
518 nir_shader *nir;
519 void *code = NULL;
520 unsigned code_size = 0;
521 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
522
523 if (module->nir)
524 _mesa_sha1_compute(module->nir->info->name,
525 strlen(module->nir->info->name),
526 module->sha1);
527
528 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
529 if (stage == MESA_SHADER_GEOMETRY)
530 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
531 layout, key, 1);
532
533 if (cache) {
534 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
535 cache,
536 sha1);
537
538 if (stage == MESA_SHADER_GEOMETRY) {
539 pipeline->gs_copy_shader =
540 radv_create_shader_variant_from_pipeline_cache(
541 pipeline->device,
542 cache,
543 gs_copy_sha1);
544 }
545 if (variant)
546 return variant;
547 }
548
549 nir = radv_shader_compile_to_nir(pipeline->device,
550 module, entrypoint, stage,
551 spec_info, dump);
552 if (nir == NULL)
553 return NULL;
554
555 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
556 &code, &code_size, dump);
557
558 if (stage == MESA_SHADER_GEOMETRY) {
559 void *gs_copy_code = NULL;
560 unsigned gs_copy_code_size = 0;
561 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
562 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
563
564 if (pipeline->gs_copy_shader && cache) {
565 pipeline->gs_copy_shader =
566 radv_pipeline_cache_insert_shader(cache,
567 gs_copy_sha1,
568 pipeline->gs_copy_shader,
569 gs_copy_code,
570 gs_copy_code_size);
571 }
572 }
573 if (!module->nir)
574 ralloc_free(nir);
575
576 if (variant && cache)
577 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
578 code, code_size);
579
580 if (code)
581 free(code);
582 return variant;
583 }
584
585 static VkResult
586 radv_pipeline_scratch_init(struct radv_device *device,
587 struct radv_pipeline *pipeline)
588 {
589 unsigned scratch_bytes_per_wave = 0;
590 unsigned max_waves = 0;
591 unsigned min_waves = 1;
592
593 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
594 if (pipeline->shaders[i]) {
595 unsigned max_stage_waves = device->scratch_waves;
596
597 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
598 pipeline->shaders[i]->config.scratch_bytes_per_wave);
599
600 max_stage_waves = MIN2(max_stage_waves,
601 4 * device->physical_device->rad_info.num_good_compute_units *
602 (256 / pipeline->shaders[i]->config.num_vgprs));
603 max_waves = MAX2(max_waves, max_stage_waves);
604 }
605 }
606
607 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
608 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
609 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
610 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
611 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
612 }
613
614 if (scratch_bytes_per_wave)
615 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
616
617 if (scratch_bytes_per_wave && max_waves < min_waves) {
618 /* Not really true at this moment, but will be true on first
619 * execution. Avoid having hanging shaders. */
620 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
621 }
622 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
623 pipeline->max_waves = max_waves;
624 return VK_SUCCESS;
625 }
626
627 static uint32_t si_translate_blend_function(VkBlendOp op)
628 {
629 switch (op) {
630 case VK_BLEND_OP_ADD:
631 return V_028780_COMB_DST_PLUS_SRC;
632 case VK_BLEND_OP_SUBTRACT:
633 return V_028780_COMB_SRC_MINUS_DST;
634 case VK_BLEND_OP_REVERSE_SUBTRACT:
635 return V_028780_COMB_DST_MINUS_SRC;
636 case VK_BLEND_OP_MIN:
637 return V_028780_COMB_MIN_DST_SRC;
638 case VK_BLEND_OP_MAX:
639 return V_028780_COMB_MAX_DST_SRC;
640 default:
641 return 0;
642 }
643 }
644
645 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
646 {
647 switch (factor) {
648 case VK_BLEND_FACTOR_ZERO:
649 return V_028780_BLEND_ZERO;
650 case VK_BLEND_FACTOR_ONE:
651 return V_028780_BLEND_ONE;
652 case VK_BLEND_FACTOR_SRC_COLOR:
653 return V_028780_BLEND_SRC_COLOR;
654 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
655 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
656 case VK_BLEND_FACTOR_DST_COLOR:
657 return V_028780_BLEND_DST_COLOR;
658 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
659 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
660 case VK_BLEND_FACTOR_SRC_ALPHA:
661 return V_028780_BLEND_SRC_ALPHA;
662 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
663 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
664 case VK_BLEND_FACTOR_DST_ALPHA:
665 return V_028780_BLEND_DST_ALPHA;
666 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
667 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
668 case VK_BLEND_FACTOR_CONSTANT_COLOR:
669 return V_028780_BLEND_CONSTANT_COLOR;
670 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
671 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
672 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
673 return V_028780_BLEND_CONSTANT_ALPHA;
674 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
675 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
676 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
677 return V_028780_BLEND_SRC_ALPHA_SATURATE;
678 case VK_BLEND_FACTOR_SRC1_COLOR:
679 return V_028780_BLEND_SRC1_COLOR;
680 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
681 return V_028780_BLEND_INV_SRC1_COLOR;
682 case VK_BLEND_FACTOR_SRC1_ALPHA:
683 return V_028780_BLEND_SRC1_ALPHA;
684 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
685 return V_028780_BLEND_INV_SRC1_ALPHA;
686 default:
687 return 0;
688 }
689 }
690
691 static bool is_dual_src(VkBlendFactor factor)
692 {
693 switch (factor) {
694 case VK_BLEND_FACTOR_SRC1_COLOR:
695 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
696 case VK_BLEND_FACTOR_SRC1_ALPHA:
697 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
698 return true;
699 default:
700 return false;
701 }
702 }
703
704 static unsigned si_choose_spi_color_format(VkFormat vk_format,
705 bool blend_enable,
706 bool blend_need_alpha)
707 {
708 const struct vk_format_description *desc = vk_format_description(vk_format);
709 unsigned format, ntype, swap;
710
711 /* Alpha is needed for alpha-to-coverage.
712 * Blending may be with or without alpha.
713 */
714 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
715 unsigned alpha = 0; /* exports alpha, but may not support blending */
716 unsigned blend = 0; /* supports blending, but may not export alpha */
717 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
718
719 format = radv_translate_colorformat(vk_format);
720 ntype = radv_translate_color_numformat(vk_format, desc,
721 vk_format_get_first_non_void_channel(vk_format));
722 swap = radv_translate_colorswap(vk_format, false);
723
724 /* Choose the SPI color formats. These are required values for Stoney/RB+.
725 * Other chips have multiple choices, though they are not necessarily better.
726 */
727 switch (format) {
728 case V_028C70_COLOR_5_6_5:
729 case V_028C70_COLOR_1_5_5_5:
730 case V_028C70_COLOR_5_5_5_1:
731 case V_028C70_COLOR_4_4_4_4:
732 case V_028C70_COLOR_10_11_11:
733 case V_028C70_COLOR_11_11_10:
734 case V_028C70_COLOR_8:
735 case V_028C70_COLOR_8_8:
736 case V_028C70_COLOR_8_8_8_8:
737 case V_028C70_COLOR_10_10_10_2:
738 case V_028C70_COLOR_2_10_10_10:
739 if (ntype == V_028C70_NUMBER_UINT)
740 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
741 else if (ntype == V_028C70_NUMBER_SINT)
742 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
743 else
744 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
745 break;
746
747 case V_028C70_COLOR_16:
748 case V_028C70_COLOR_16_16:
749 case V_028C70_COLOR_16_16_16_16:
750 if (ntype == V_028C70_NUMBER_UNORM ||
751 ntype == V_028C70_NUMBER_SNORM) {
752 /* UNORM16 and SNORM16 don't support blending */
753 if (ntype == V_028C70_NUMBER_UNORM)
754 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
755 else
756 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
757
758 /* Use 32 bits per channel for blending. */
759 if (format == V_028C70_COLOR_16) {
760 if (swap == V_028C70_SWAP_STD) { /* R */
761 blend = V_028714_SPI_SHADER_32_R;
762 blend_alpha = V_028714_SPI_SHADER_32_AR;
763 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
764 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
765 else
766 assert(0);
767 } else if (format == V_028C70_COLOR_16_16) {
768 if (swap == V_028C70_SWAP_STD) { /* RG */
769 blend = V_028714_SPI_SHADER_32_GR;
770 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
771 } else if (swap == V_028C70_SWAP_ALT) /* RA */
772 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
773 else
774 assert(0);
775 } else /* 16_16_16_16 */
776 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
777 } else if (ntype == V_028C70_NUMBER_UINT)
778 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
779 else if (ntype == V_028C70_NUMBER_SINT)
780 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
781 else if (ntype == V_028C70_NUMBER_FLOAT)
782 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
783 else
784 assert(0);
785 break;
786
787 case V_028C70_COLOR_32:
788 if (swap == V_028C70_SWAP_STD) { /* R */
789 blend = normal = V_028714_SPI_SHADER_32_R;
790 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
791 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
792 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
793 else
794 assert(0);
795 break;
796
797 case V_028C70_COLOR_32_32:
798 if (swap == V_028C70_SWAP_STD) { /* RG */
799 blend = normal = V_028714_SPI_SHADER_32_GR;
800 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
801 } else if (swap == V_028C70_SWAP_ALT) /* RA */
802 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
803 else
804 assert(0);
805 break;
806
807 case V_028C70_COLOR_32_32_32_32:
808 case V_028C70_COLOR_8_24:
809 case V_028C70_COLOR_24_8:
810 case V_028C70_COLOR_X24_8_32_FLOAT:
811 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
812 break;
813
814 default:
815 unreachable("unhandled blend format");
816 }
817
818 if (blend_enable && blend_need_alpha)
819 return blend_alpha;
820 else if(blend_need_alpha)
821 return alpha;
822 else if(blend_enable)
823 return blend;
824 else
825 return normal;
826 }
827
828 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
829 {
830 unsigned i, cb_shader_mask = 0;
831
832 for (i = 0; i < 8; i++) {
833 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
834 case V_028714_SPI_SHADER_ZERO:
835 break;
836 case V_028714_SPI_SHADER_32_R:
837 cb_shader_mask |= 0x1 << (i * 4);
838 break;
839 case V_028714_SPI_SHADER_32_GR:
840 cb_shader_mask |= 0x3 << (i * 4);
841 break;
842 case V_028714_SPI_SHADER_32_AR:
843 cb_shader_mask |= 0x9 << (i * 4);
844 break;
845 case V_028714_SPI_SHADER_FP16_ABGR:
846 case V_028714_SPI_SHADER_UNORM16_ABGR:
847 case V_028714_SPI_SHADER_SNORM16_ABGR:
848 case V_028714_SPI_SHADER_UINT16_ABGR:
849 case V_028714_SPI_SHADER_SINT16_ABGR:
850 case V_028714_SPI_SHADER_32_ABGR:
851 cb_shader_mask |= 0xf << (i * 4);
852 break;
853 default:
854 assert(0);
855 }
856 }
857 return cb_shader_mask;
858 }
859
860 static void
861 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
862 const VkGraphicsPipelineCreateInfo *pCreateInfo,
863 uint32_t blend_enable,
864 uint32_t blend_need_alpha,
865 bool single_cb_enable,
866 bool blend_mrt0_is_dual_src)
867 {
868 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
869 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
870 struct radv_blend_state *blend = &pipeline->graphics.blend;
871 unsigned col_format = 0;
872
873 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
874 struct radv_render_pass_attachment *attachment;
875 unsigned cf;
876
877 attachment = pass->attachments + subpass->color_attachments[i].attachment;
878
879 cf = si_choose_spi_color_format(attachment->format,
880 blend_enable & (1 << i),
881 blend_need_alpha & (1 << i));
882
883 col_format |= cf << (4 * i);
884 }
885
886 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
887
888 if (blend_mrt0_is_dual_src)
889 col_format |= (col_format & 0xf) << 4;
890 if (!col_format)
891 col_format |= V_028714_SPI_SHADER_32_R;
892 blend->spi_shader_col_format = col_format;
893 }
894
895 static bool
896 format_is_int8(VkFormat format)
897 {
898 const struct vk_format_description *desc = vk_format_description(format);
899 int channel = vk_format_get_first_non_void_channel(format);
900
901 return channel >= 0 && desc->channel[channel].pure_integer &&
902 desc->channel[channel].size == 8;
903 }
904
905 unsigned radv_format_meta_fs_key(VkFormat format)
906 {
907 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
908 bool is_int8 = format_is_int8(format);
909
910 return col_format + (is_int8 ? 3 : 0);
911 }
912
913 static unsigned
914 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
915 {
916 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
917 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
918 unsigned is_int8 = 0;
919
920 for (unsigned i = 0; i < subpass->color_count; ++i) {
921 struct radv_render_pass_attachment *attachment;
922
923 attachment = pass->attachments + subpass->color_attachments[i].attachment;
924
925 if (format_is_int8(attachment->format))
926 is_int8 |= 1 << i;
927 }
928
929 return is_int8;
930 }
931
932 static void
933 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
934 const VkGraphicsPipelineCreateInfo *pCreateInfo,
935 const struct radv_graphics_pipeline_create_info *extra)
936 {
937 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
938 struct radv_blend_state *blend = &pipeline->graphics.blend;
939 unsigned mode = V_028808_CB_NORMAL;
940 uint32_t blend_enable = 0, blend_need_alpha = 0;
941 bool blend_mrt0_is_dual_src = false;
942 int i;
943 bool single_cb_enable = false;
944
945 if (!vkblend)
946 return;
947
948 if (extra && extra->custom_blend_mode) {
949 single_cb_enable = true;
950 mode = extra->custom_blend_mode;
951 }
952 blend->cb_color_control = 0;
953 if (vkblend->logicOpEnable)
954 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
955 else
956 blend->cb_color_control |= S_028808_ROP3(0xcc);
957
958 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
959 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
960 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
961 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
962
963 blend->cb_target_mask = 0;
964 for (i = 0; i < vkblend->attachmentCount; i++) {
965 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
966 unsigned blend_cntl = 0;
967 VkBlendOp eqRGB = att->colorBlendOp;
968 VkBlendFactor srcRGB = att->srcColorBlendFactor;
969 VkBlendFactor dstRGB = att->dstColorBlendFactor;
970 VkBlendOp eqA = att->alphaBlendOp;
971 VkBlendFactor srcA = att->srcAlphaBlendFactor;
972 VkBlendFactor dstA = att->dstAlphaBlendFactor;
973
974 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
975
976 if (!att->colorWriteMask)
977 continue;
978
979 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
980 if (!att->blendEnable) {
981 blend->cb_blend_control[i] = blend_cntl;
982 continue;
983 }
984
985 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
986 if (i == 0)
987 blend_mrt0_is_dual_src = true;
988
989 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
990 srcRGB = VK_BLEND_FACTOR_ONE;
991 dstRGB = VK_BLEND_FACTOR_ONE;
992 }
993 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
994 srcA = VK_BLEND_FACTOR_ONE;
995 dstA = VK_BLEND_FACTOR_ONE;
996 }
997
998 blend_cntl |= S_028780_ENABLE(1);
999
1000 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1001 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1002 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1003 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1004 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1005 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1006 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1007 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1008 }
1009 blend->cb_blend_control[i] = blend_cntl;
1010
1011 blend_enable |= 1 << i;
1012
1013 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1014 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1015 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1016 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1017 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1018 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1019 blend_need_alpha |= 1 << i;
1020 }
1021 for (i = vkblend->attachmentCount; i < 8; i++)
1022 blend->cb_blend_control[i] = 0;
1023
1024 if (blend->cb_target_mask)
1025 blend->cb_color_control |= S_028808_MODE(mode);
1026 else
1027 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1028
1029 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1030 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1031 }
1032
1033 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1034 {
1035 switch (op) {
1036 case VK_STENCIL_OP_KEEP:
1037 return V_02842C_STENCIL_KEEP;
1038 case VK_STENCIL_OP_ZERO:
1039 return V_02842C_STENCIL_ZERO;
1040 case VK_STENCIL_OP_REPLACE:
1041 return V_02842C_STENCIL_REPLACE_TEST;
1042 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1043 return V_02842C_STENCIL_ADD_CLAMP;
1044 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1045 return V_02842C_STENCIL_SUB_CLAMP;
1046 case VK_STENCIL_OP_INVERT:
1047 return V_02842C_STENCIL_INVERT;
1048 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1049 return V_02842C_STENCIL_ADD_WRAP;
1050 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1051 return V_02842C_STENCIL_SUB_WRAP;
1052 default:
1053 return 0;
1054 }
1055 }
1056 static void
1057 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1058 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1059 const struct radv_graphics_pipeline_create_info *extra)
1060 {
1061 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1062 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1063
1064 memset(ds, 0, sizeof(*ds));
1065 if (!vkds)
1066 return;
1067 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1068 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1069 S_028800_ZFUNC(vkds->depthCompareOp) |
1070 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1071
1072 if (vkds->stencilTestEnable) {
1073 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1074 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1075 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1076 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1077 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1078
1079 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1080 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1081 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1082 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1083 }
1084
1085 if (extra) {
1086
1087 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1088 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1089
1090 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1091 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1092 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1093 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1094 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1095 }
1096 }
1097
1098 static uint32_t si_translate_fill(VkPolygonMode func)
1099 {
1100 switch(func) {
1101 case VK_POLYGON_MODE_FILL:
1102 return V_028814_X_DRAW_TRIANGLES;
1103 case VK_POLYGON_MODE_LINE:
1104 return V_028814_X_DRAW_LINES;
1105 case VK_POLYGON_MODE_POINT:
1106 return V_028814_X_DRAW_POINTS;
1107 default:
1108 assert(0);
1109 return V_028814_X_DRAW_POINTS;
1110 }
1111 }
1112 static void
1113 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1114 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1115 {
1116 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1117 struct radv_raster_state *raster = &pipeline->graphics.raster;
1118
1119 memset(raster, 0, sizeof(*raster));
1120
1121 raster->spi_interp_control =
1122 S_0286D4_FLAT_SHADE_ENA(1) |
1123 S_0286D4_PNT_SPRITE_ENA(1) |
1124 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1125 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1126 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1127 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1128 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1129
1130 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
1131 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1132 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1133 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1134 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1135 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1136 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1137
1138 raster->pa_su_vtx_cntl =
1139 S_028BE4_PIX_CENTER(1) | // TODO verify
1140 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1141 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1142
1143 raster->pa_su_sc_mode_cntl =
1144 S_028814_FACE(vkraster->frontFace) |
1145 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1146 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1147 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1148 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1149 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1150 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1151 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1152 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1153
1154 }
1155
1156 static void
1157 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1158 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1159 {
1160 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1161 struct radv_blend_state *blend = &pipeline->graphics.blend;
1162 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1163 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1164 int ps_iter_samples = 1;
1165 uint32_t mask = 0xffff;
1166
1167 ms->num_samples = vkms->rasterizationSamples;
1168
1169 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1170 ps_iter_samples = vkms->rasterizationSamples;
1171 }
1172
1173 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1174 ms->pa_sc_aa_config = 0;
1175 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1176 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1177 ms->pa_sc_mode_cntl_1 =
1178 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1179 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1180 /* always 1: */
1181 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1182 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1183 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1184 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1185 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1186 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1187
1188 if (vkms->rasterizationSamples > 1) {
1189 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1190 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1191 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1192 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1193 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1194 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1195 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1196 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1197 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1198 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1199 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1200 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1201 }
1202
1203 if (vkms->alphaToCoverageEnable)
1204 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1205
1206 if (vkms->pSampleMask) {
1207 mask = vkms->pSampleMask[0] & 0xffff;
1208 }
1209
1210 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1211 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1212 }
1213
1214 static uint32_t
1215 si_translate_prim(enum VkPrimitiveTopology topology)
1216 {
1217 switch (topology) {
1218 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1219 return V_008958_DI_PT_POINTLIST;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1221 return V_008958_DI_PT_LINELIST;
1222 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1223 return V_008958_DI_PT_LINESTRIP;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1225 return V_008958_DI_PT_TRILIST;
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1227 return V_008958_DI_PT_TRISTRIP;
1228 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1229 return V_008958_DI_PT_TRIFAN;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1231 return V_008958_DI_PT_LINELIST_ADJ;
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1233 return V_008958_DI_PT_LINESTRIP_ADJ;
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1235 return V_008958_DI_PT_TRILIST_ADJ;
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1237 return V_008958_DI_PT_TRISTRIP_ADJ;
1238 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1239 return V_008958_DI_PT_PATCH;
1240 default:
1241 assert(0);
1242 return 0;
1243 }
1244 }
1245
1246 static uint32_t
1247 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1248 {
1249 switch (gl_prim) {
1250 case 0: /* GL_POINTS */
1251 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1252 case 1: /* GL_LINES */
1253 case 3: /* GL_LINE_STRIP */
1254 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1255 case 0x8E7A: /* GL_ISOLINES */
1256 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1257
1258 case 4: /* GL_TRIANGLES */
1259 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1260 case 5: /* GL_TRIANGLE_STRIP */
1261 case 7: /* GL_QUADS */
1262 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1263 default:
1264 assert(0);
1265 return 0;
1266 }
1267 }
1268
1269 static uint32_t
1270 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1271 {
1272 switch (topology) {
1273 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1274 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1275 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1276 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1278 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1279 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1280 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1282 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1283 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1284 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1285 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1286 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1287 default:
1288 assert(0);
1289 return 0;
1290 }
1291 }
1292
1293 static unsigned si_map_swizzle(unsigned swizzle)
1294 {
1295 switch (swizzle) {
1296 case VK_SWIZZLE_Y:
1297 return V_008F0C_SQ_SEL_Y;
1298 case VK_SWIZZLE_Z:
1299 return V_008F0C_SQ_SEL_Z;
1300 case VK_SWIZZLE_W:
1301 return V_008F0C_SQ_SEL_W;
1302 case VK_SWIZZLE_0:
1303 return V_008F0C_SQ_SEL_0;
1304 case VK_SWIZZLE_1:
1305 return V_008F0C_SQ_SEL_1;
1306 default: /* VK_SWIZZLE_X */
1307 return V_008F0C_SQ_SEL_X;
1308 }
1309 }
1310
1311 static void
1312 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1313 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1314 {
1315 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1316 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1317 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1318
1319 pipeline->dynamic_state = default_dynamic_state;
1320
1321 if (pCreateInfo->pDynamicState) {
1322 /* Remove all of the states that are marked as dynamic */
1323 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1324 for (uint32_t s = 0; s < count; s++)
1325 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1326 }
1327
1328 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1329
1330 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1331 *
1332 * pViewportState is [...] NULL if the pipeline
1333 * has rasterization disabled.
1334 */
1335 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1336 assert(pCreateInfo->pViewportState);
1337
1338 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1339 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1340 typed_memcpy(dynamic->viewport.viewports,
1341 pCreateInfo->pViewportState->pViewports,
1342 pCreateInfo->pViewportState->viewportCount);
1343 }
1344
1345 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1346 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1347 typed_memcpy(dynamic->scissor.scissors,
1348 pCreateInfo->pViewportState->pScissors,
1349 pCreateInfo->pViewportState->scissorCount);
1350 }
1351 }
1352
1353 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1354 assert(pCreateInfo->pRasterizationState);
1355 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1356 }
1357
1358 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1359 assert(pCreateInfo->pRasterizationState);
1360 dynamic->depth_bias.bias =
1361 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1362 dynamic->depth_bias.clamp =
1363 pCreateInfo->pRasterizationState->depthBiasClamp;
1364 dynamic->depth_bias.slope =
1365 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1366 }
1367
1368 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1369 *
1370 * pColorBlendState is [...] NULL if the pipeline has rasterization
1371 * disabled or if the subpass of the render pass the pipeline is
1372 * created against does not use any color attachments.
1373 */
1374 bool uses_color_att = false;
1375 for (unsigned i = 0; i < subpass->color_count; ++i) {
1376 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1377 uses_color_att = true;
1378 break;
1379 }
1380 }
1381
1382 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1383 assert(pCreateInfo->pColorBlendState);
1384 typed_memcpy(dynamic->blend_constants,
1385 pCreateInfo->pColorBlendState->blendConstants, 4);
1386 }
1387
1388 /* If there is no depthstencil attachment, then don't read
1389 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1390 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1391 * no need to override the depthstencil defaults in
1392 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1393 *
1394 * Section 9.2 of the Vulkan 1.0.15 spec says:
1395 *
1396 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1397 * disabled or if the subpass of the render pass the pipeline is created
1398 * against does not use a depth/stencil attachment.
1399 */
1400 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1401 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1402 assert(pCreateInfo->pDepthStencilState);
1403
1404 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1405 dynamic->depth_bounds.min =
1406 pCreateInfo->pDepthStencilState->minDepthBounds;
1407 dynamic->depth_bounds.max =
1408 pCreateInfo->pDepthStencilState->maxDepthBounds;
1409 }
1410
1411 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1412 dynamic->stencil_compare_mask.front =
1413 pCreateInfo->pDepthStencilState->front.compareMask;
1414 dynamic->stencil_compare_mask.back =
1415 pCreateInfo->pDepthStencilState->back.compareMask;
1416 }
1417
1418 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1419 dynamic->stencil_write_mask.front =
1420 pCreateInfo->pDepthStencilState->front.writeMask;
1421 dynamic->stencil_write_mask.back =
1422 pCreateInfo->pDepthStencilState->back.writeMask;
1423 }
1424
1425 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1426 dynamic->stencil_reference.front =
1427 pCreateInfo->pDepthStencilState->front.reference;
1428 dynamic->stencil_reference.back =
1429 pCreateInfo->pDepthStencilState->back.reference;
1430 }
1431 }
1432
1433 pipeline->dynamic_state_mask = states;
1434 }
1435
1436 static union ac_shader_variant_key
1437 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es)
1438 {
1439 union ac_shader_variant_key key;
1440 const VkPipelineVertexInputStateCreateInfo *input_state =
1441 pCreateInfo->pVertexInputState;
1442
1443 memset(&key, 0, sizeof(key));
1444 key.vs.instance_rate_inputs = 0;
1445 key.vs.as_es = as_es;
1446
1447 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1448 unsigned binding;
1449 binding = input_state->pVertexAttributeDescriptions[i].binding;
1450 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1451 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1452 }
1453 return key;
1454 }
1455
1456 static void
1457 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1458 {
1459 struct radv_device *device = pipeline->device;
1460 unsigned num_se = device->physical_device->rad_info.max_se;
1461 unsigned wave_size = 64;
1462 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1463 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1464 unsigned alignment = 256 * num_se;
1465 /* The maximum size is 63.999 MB per SE. */
1466 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1467
1468 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1469 struct ac_shader_variant_info *es_info = &pipeline->shaders[MESA_SHADER_VERTEX]->info;
1470 /* Calculate the minimum size. */
1471 unsigned min_esgs_ring_size = align(es_info->vs.esgs_itemsize * gs_vertex_reuse *
1472 wave_size, alignment);
1473 /* These are recommended sizes, not minimum sizes. */
1474 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1475 es_info->vs.esgs_itemsize * gs_info->gs.vertices_in;
1476 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1477 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1478
1479 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1480 esgs_ring_size = align(esgs_ring_size, alignment);
1481 gsvs_ring_size = align(gsvs_ring_size, alignment);
1482
1483 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1484 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1485 }
1486
1487 static const struct radv_prim_vertex_count prim_size_table[] = {
1488 [V_008958_DI_PT_NONE] = {0, 0},
1489 [V_008958_DI_PT_POINTLIST] = {1, 1},
1490 [V_008958_DI_PT_LINELIST] = {2, 2},
1491 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1492 [V_008958_DI_PT_TRILIST] = {3, 3},
1493 [V_008958_DI_PT_TRIFAN] = {3, 1},
1494 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1495 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1496 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1497 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1498 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1499 [V_008958_DI_PT_RECTLIST] = {3, 3},
1500 [V_008958_DI_PT_LINELOOP] = {2, 1},
1501 [V_008958_DI_PT_POLYGON] = {3, 1},
1502 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1503 };
1504
1505 VkResult
1506 radv_pipeline_init(struct radv_pipeline *pipeline,
1507 struct radv_device *device,
1508 struct radv_pipeline_cache *cache,
1509 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1510 const struct radv_graphics_pipeline_create_info *extra,
1511 const VkAllocationCallbacks *alloc)
1512 {
1513 struct radv_shader_module fs_m = {0};
1514 VkResult result;
1515
1516 if (alloc == NULL)
1517 alloc = &device->alloc;
1518
1519 pipeline->device = device;
1520 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1521
1522 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1523 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1524 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1525 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1526 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1527 pStages[stage] = &pCreateInfo->pStages[i];
1528 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1529 }
1530
1531 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1532
1533 /* */
1534 if (modules[MESA_SHADER_VERTEX]) {
1535 bool as_es = modules[MESA_SHADER_GEOMETRY] != NULL;
1536 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es);
1537
1538 pipeline->shaders[MESA_SHADER_VERTEX] =
1539 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1540 pStages[MESA_SHADER_VERTEX]->pName,
1541 MESA_SHADER_VERTEX,
1542 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1543 pipeline->layout, &key);
1544
1545 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1546 }
1547
1548 if (modules[MESA_SHADER_GEOMETRY]) {
1549 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false);
1550
1551 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1552 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1553 pStages[MESA_SHADER_GEOMETRY]->pName,
1554 MESA_SHADER_GEOMETRY,
1555 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1556 pipeline->layout, &key);
1557
1558 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1559 calculate_gs_ring_sizes(pipeline);
1560 }
1561
1562 if (!modules[MESA_SHADER_FRAGMENT]) {
1563 nir_builder fs_b;
1564 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1565 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1566 fs_m.nir = fs_b.shader;
1567 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1568 }
1569
1570 if (modules[MESA_SHADER_FRAGMENT]) {
1571 union ac_shader_variant_key key;
1572 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1573 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1574
1575 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1576
1577 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1578 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1579 stage ? stage->pName : "main",
1580 MESA_SHADER_FRAGMENT,
1581 stage ? stage->pSpecializationInfo : NULL,
1582 pipeline->layout, &key);
1583 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1584 }
1585
1586 if (fs_m.nir)
1587 ralloc_free(fs_m.nir);
1588
1589 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1590 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1591 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1592 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1593 if (radv_pipeline_has_gs(pipeline)) {
1594 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1595 } else {
1596 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1597 }
1598 if (extra && extra->use_rectlist) {
1599 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1600 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1601 }
1602 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1603 /* prim vertex count will need TESS changes */
1604 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1605
1606 const VkPipelineVertexInputStateCreateInfo *vi_info =
1607 pCreateInfo->pVertexInputState;
1608 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1609 const VkVertexInputAttributeDescription *desc =
1610 &vi_info->pVertexAttributeDescriptions[i];
1611 unsigned loc = desc->location;
1612 const struct vk_format_description *format_desc;
1613 int first_non_void;
1614 uint32_t num_format, data_format;
1615 format_desc = vk_format_description(desc->format);
1616 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1617
1618 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1619 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1620
1621 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1622 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1623 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1624 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1625 S_008F0C_NUM_FORMAT(num_format) |
1626 S_008F0C_DATA_FORMAT(data_format);
1627 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1628 pipeline->va_offset[loc] = desc->offset;
1629 pipeline->va_binding[loc] = desc->binding;
1630 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1631 }
1632
1633 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1634 const VkVertexInputBindingDescription *desc =
1635 &vi_info->pVertexBindingDescriptions[i];
1636
1637 pipeline->binding_stride[desc->binding] = desc->stride;
1638 }
1639
1640 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1641 radv_dump_pipeline_stats(device, pipeline);
1642 }
1643
1644 result = radv_pipeline_scratch_init(device, pipeline);
1645 return result;
1646 }
1647
1648 VkResult
1649 radv_graphics_pipeline_create(
1650 VkDevice _device,
1651 VkPipelineCache _cache,
1652 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1653 const struct radv_graphics_pipeline_create_info *extra,
1654 const VkAllocationCallbacks *pAllocator,
1655 VkPipeline *pPipeline)
1656 {
1657 RADV_FROM_HANDLE(radv_device, device, _device);
1658 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1659 struct radv_pipeline *pipeline;
1660 VkResult result;
1661
1662 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1663 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1664 if (pipeline == NULL)
1665 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1666
1667 memset(pipeline, 0, sizeof(*pipeline));
1668 result = radv_pipeline_init(pipeline, device, cache,
1669 pCreateInfo, extra, pAllocator);
1670 if (result != VK_SUCCESS) {
1671 radv_pipeline_destroy(device, pipeline, pAllocator);
1672 return result;
1673 }
1674
1675 *pPipeline = radv_pipeline_to_handle(pipeline);
1676
1677 return VK_SUCCESS;
1678 }
1679
1680 VkResult radv_CreateGraphicsPipelines(
1681 VkDevice _device,
1682 VkPipelineCache pipelineCache,
1683 uint32_t count,
1684 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1685 const VkAllocationCallbacks* pAllocator,
1686 VkPipeline* pPipelines)
1687 {
1688 VkResult result = VK_SUCCESS;
1689 unsigned i = 0;
1690
1691 for (; i < count; i++) {
1692 VkResult r;
1693 r = radv_graphics_pipeline_create(_device,
1694 pipelineCache,
1695 &pCreateInfos[i],
1696 NULL, pAllocator, &pPipelines[i]);
1697 if (r != VK_SUCCESS) {
1698 result = r;
1699 pPipelines[i] = VK_NULL_HANDLE;
1700 }
1701 }
1702
1703 return result;
1704 }
1705
1706 static VkResult radv_compute_pipeline_create(
1707 VkDevice _device,
1708 VkPipelineCache _cache,
1709 const VkComputePipelineCreateInfo* pCreateInfo,
1710 const VkAllocationCallbacks* pAllocator,
1711 VkPipeline* pPipeline)
1712 {
1713 RADV_FROM_HANDLE(radv_device, device, _device);
1714 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1715 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1716 struct radv_pipeline *pipeline;
1717 VkResult result;
1718
1719 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1720 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1721 if (pipeline == NULL)
1722 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1723
1724 memset(pipeline, 0, sizeof(*pipeline));
1725 pipeline->device = device;
1726 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1727
1728 pipeline->shaders[MESA_SHADER_COMPUTE] =
1729 radv_pipeline_compile(pipeline, cache, module,
1730 pCreateInfo->stage.pName,
1731 MESA_SHADER_COMPUTE,
1732 pCreateInfo->stage.pSpecializationInfo,
1733 pipeline->layout, NULL);
1734
1735
1736 result = radv_pipeline_scratch_init(device, pipeline);
1737 if (result != VK_SUCCESS) {
1738 radv_pipeline_destroy(device, pipeline, pAllocator);
1739 return result;
1740 }
1741
1742 *pPipeline = radv_pipeline_to_handle(pipeline);
1743
1744 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1745 radv_dump_pipeline_stats(device, pipeline);
1746 }
1747 return VK_SUCCESS;
1748 }
1749 VkResult radv_CreateComputePipelines(
1750 VkDevice _device,
1751 VkPipelineCache pipelineCache,
1752 uint32_t count,
1753 const VkComputePipelineCreateInfo* pCreateInfos,
1754 const VkAllocationCallbacks* pAllocator,
1755 VkPipeline* pPipelines)
1756 {
1757 VkResult result = VK_SUCCESS;
1758
1759 unsigned i = 0;
1760 for (; i < count; i++) {
1761 VkResult r;
1762 r = radv_compute_pipeline_create(_device, pipelineCache,
1763 &pCreateInfos[i],
1764 pAllocator, &pPipelines[i]);
1765 if (r != VK_SUCCESS) {
1766 result = r;
1767 pPipelines[i] = VK_NULL_HANDLE;
1768 }
1769 }
1770
1771 return result;
1772 }