2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
33 #include "radv_shader.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
53 struct radv_blend_state
{
54 uint32_t blend_enable_4bit
;
55 uint32_t need_src_alpha
;
57 uint32_t cb_color_control
;
58 uint32_t cb_target_mask
;
59 uint32_t cb_target_enabled_4bit
;
60 uint32_t sx_mrt_blend_opt
[8];
61 uint32_t cb_blend_control
[8];
63 uint32_t spi_shader_col_format
;
64 uint32_t cb_shader_mask
;
65 uint32_t db_alpha_to_mask
;
67 uint32_t commutative_4bit
;
69 bool single_cb_enable
;
70 bool mrt0_is_dual_src
;
73 struct radv_dsa_order_invariance
{
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
86 struct radv_tessellation_state
{
87 uint32_t ls_hs_config
;
93 struct radv_gs_state
{
94 uint32_t vgt_gs_onchip_cntl
;
95 uint32_t vgt_gs_max_prims_per_subgroup
;
96 uint32_t vgt_esgs_ring_itemsize
;
101 radv_pipeline_destroy(struct radv_device
*device
,
102 struct radv_pipeline
*pipeline
,
103 const VkAllocationCallbacks
* allocator
)
105 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
106 if (pipeline
->shaders
[i
])
107 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
109 if (pipeline
->gs_copy_shader
)
110 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
113 free(pipeline
->cs
.buf
);
114 vk_free2(&device
->alloc
, allocator
, pipeline
);
117 void radv_DestroyPipeline(
119 VkPipeline _pipeline
,
120 const VkAllocationCallbacks
* pAllocator
)
122 RADV_FROM_HANDLE(radv_device
, device
, _device
);
123 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
128 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
131 static uint32_t get_hash_flags(struct radv_device
*device
)
133 uint32_t hash_flags
= 0;
135 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
136 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
137 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
138 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
143 radv_pipeline_scratch_init(struct radv_device
*device
,
144 struct radv_pipeline
*pipeline
)
146 unsigned scratch_bytes_per_wave
= 0;
147 unsigned max_waves
= 0;
148 unsigned min_waves
= 1;
150 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
151 if (pipeline
->shaders
[i
]) {
152 unsigned max_stage_waves
= device
->scratch_waves
;
154 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
155 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
157 max_stage_waves
= MIN2(max_stage_waves
,
158 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
159 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
160 max_waves
= MAX2(max_waves
, max_stage_waves
);
164 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
165 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
166 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
167 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
168 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
171 if (scratch_bytes_per_wave
)
172 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
174 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
179 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
180 pipeline
->max_waves
= max_waves
;
184 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
187 case VK_LOGIC_OP_CLEAR
:
188 return V_028808_ROP3_CLEAR
;
189 case VK_LOGIC_OP_AND
:
190 return V_028808_ROP3_AND
;
191 case VK_LOGIC_OP_AND_REVERSE
:
192 return V_028808_ROP3_AND_REVERSE
;
193 case VK_LOGIC_OP_COPY
:
194 return V_028808_ROP3_COPY
;
195 case VK_LOGIC_OP_AND_INVERTED
:
196 return V_028808_ROP3_AND_INVERTED
;
197 case VK_LOGIC_OP_NO_OP
:
198 return V_028808_ROP3_NO_OP
;
199 case VK_LOGIC_OP_XOR
:
200 return V_028808_ROP3_XOR
;
202 return V_028808_ROP3_OR
;
203 case VK_LOGIC_OP_NOR
:
204 return V_028808_ROP3_NOR
;
205 case VK_LOGIC_OP_EQUIVALENT
:
206 return V_028808_ROP3_EQUIVALENT
;
207 case VK_LOGIC_OP_INVERT
:
208 return V_028808_ROP3_INVERT
;
209 case VK_LOGIC_OP_OR_REVERSE
:
210 return V_028808_ROP3_OR_REVERSE
;
211 case VK_LOGIC_OP_COPY_INVERTED
:
212 return V_028808_ROP3_COPY_INVERTED
;
213 case VK_LOGIC_OP_OR_INVERTED
:
214 return V_028808_ROP3_OR_INVERTED
;
215 case VK_LOGIC_OP_NAND
:
216 return V_028808_ROP3_NAND
;
217 case VK_LOGIC_OP_SET
:
218 return V_028808_ROP3_SET
;
220 unreachable("Unhandled logic op");
225 static uint32_t si_translate_blend_function(VkBlendOp op
)
228 case VK_BLEND_OP_ADD
:
229 return V_028780_COMB_DST_PLUS_SRC
;
230 case VK_BLEND_OP_SUBTRACT
:
231 return V_028780_COMB_SRC_MINUS_DST
;
232 case VK_BLEND_OP_REVERSE_SUBTRACT
:
233 return V_028780_COMB_DST_MINUS_SRC
;
234 case VK_BLEND_OP_MIN
:
235 return V_028780_COMB_MIN_DST_SRC
;
236 case VK_BLEND_OP_MAX
:
237 return V_028780_COMB_MAX_DST_SRC
;
243 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
246 case VK_BLEND_FACTOR_ZERO
:
247 return V_028780_BLEND_ZERO
;
248 case VK_BLEND_FACTOR_ONE
:
249 return V_028780_BLEND_ONE
;
250 case VK_BLEND_FACTOR_SRC_COLOR
:
251 return V_028780_BLEND_SRC_COLOR
;
252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
254 case VK_BLEND_FACTOR_DST_COLOR
:
255 return V_028780_BLEND_DST_COLOR
;
256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
257 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
258 case VK_BLEND_FACTOR_SRC_ALPHA
:
259 return V_028780_BLEND_SRC_ALPHA
;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
262 case VK_BLEND_FACTOR_DST_ALPHA
:
263 return V_028780_BLEND_DST_ALPHA
;
264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
266 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
267 return V_028780_BLEND_CONSTANT_COLOR
;
268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
270 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
271 return V_028780_BLEND_CONSTANT_ALPHA
;
272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
275 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
276 case VK_BLEND_FACTOR_SRC1_COLOR
:
277 return V_028780_BLEND_SRC1_COLOR
;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
279 return V_028780_BLEND_INV_SRC1_COLOR
;
280 case VK_BLEND_FACTOR_SRC1_ALPHA
:
281 return V_028780_BLEND_SRC1_ALPHA
;
282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
283 return V_028780_BLEND_INV_SRC1_ALPHA
;
289 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
292 case VK_BLEND_OP_ADD
:
293 return V_028760_OPT_COMB_ADD
;
294 case VK_BLEND_OP_SUBTRACT
:
295 return V_028760_OPT_COMB_SUBTRACT
;
296 case VK_BLEND_OP_REVERSE_SUBTRACT
:
297 return V_028760_OPT_COMB_REVSUBTRACT
;
298 case VK_BLEND_OP_MIN
:
299 return V_028760_OPT_COMB_MIN
;
300 case VK_BLEND_OP_MAX
:
301 return V_028760_OPT_COMB_MAX
;
303 return V_028760_OPT_COMB_BLEND_DISABLED
;
307 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
310 case VK_BLEND_FACTOR_ZERO
:
311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
312 case VK_BLEND_FACTOR_ONE
:
313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
314 case VK_BLEND_FACTOR_SRC_COLOR
:
315 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
318 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
320 case VK_BLEND_FACTOR_SRC_ALPHA
:
321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
325 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
333 * Get rid of DST in the blend factors by commuting the operands:
334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
336 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
337 unsigned *dst_factor
, unsigned expected_dst
,
338 unsigned replacement_src
)
340 if (*src_factor
== expected_dst
&&
341 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
342 *src_factor
= VK_BLEND_FACTOR_ZERO
;
343 *dst_factor
= replacement_src
;
345 /* Commuting the operands requires reversing subtractions. */
346 if (*func
== VK_BLEND_OP_SUBTRACT
)
347 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
348 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
349 *func
= VK_BLEND_OP_SUBTRACT
;
353 static bool si_blend_factor_uses_dst(unsigned factor
)
355 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
356 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
357 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
358 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
359 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
362 static bool is_dual_src(VkBlendFactor factor
)
365 case VK_BLEND_FACTOR_SRC1_COLOR
:
366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
367 case VK_BLEND_FACTOR_SRC1_ALPHA
:
368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
375 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
377 bool blend_need_alpha
)
379 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
380 unsigned format
, ntype
, swap
;
382 /* Alpha is needed for alpha-to-coverage.
383 * Blending may be with or without alpha.
385 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
386 unsigned alpha
= 0; /* exports alpha, but may not support blending */
387 unsigned blend
= 0; /* supports blending, but may not export alpha */
388 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
390 format
= radv_translate_colorformat(vk_format
);
391 ntype
= radv_translate_color_numformat(vk_format
, desc
,
392 vk_format_get_first_non_void_channel(vk_format
));
393 swap
= radv_translate_colorswap(vk_format
, false);
395 /* Choose the SPI color formats. These are required values for Stoney/RB+.
396 * Other chips have multiple choices, though they are not necessarily better.
399 case V_028C70_COLOR_5_6_5
:
400 case V_028C70_COLOR_1_5_5_5
:
401 case V_028C70_COLOR_5_5_5_1
:
402 case V_028C70_COLOR_4_4_4_4
:
403 case V_028C70_COLOR_10_11_11
:
404 case V_028C70_COLOR_11_11_10
:
405 case V_028C70_COLOR_8
:
406 case V_028C70_COLOR_8_8
:
407 case V_028C70_COLOR_8_8_8_8
:
408 case V_028C70_COLOR_10_10_10_2
:
409 case V_028C70_COLOR_2_10_10_10
:
410 if (ntype
== V_028C70_NUMBER_UINT
)
411 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
412 else if (ntype
== V_028C70_NUMBER_SINT
)
413 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
415 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
418 case V_028C70_COLOR_16
:
419 case V_028C70_COLOR_16_16
:
420 case V_028C70_COLOR_16_16_16_16
:
421 if (ntype
== V_028C70_NUMBER_UNORM
||
422 ntype
== V_028C70_NUMBER_SNORM
) {
423 /* UNORM16 and SNORM16 don't support blending */
424 if (ntype
== V_028C70_NUMBER_UNORM
)
425 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
427 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
429 /* Use 32 bits per channel for blending. */
430 if (format
== V_028C70_COLOR_16
) {
431 if (swap
== V_028C70_SWAP_STD
) { /* R */
432 blend
= V_028714_SPI_SHADER_32_R
;
433 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
434 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
435 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
438 } else if (format
== V_028C70_COLOR_16_16
) {
439 if (swap
== V_028C70_SWAP_STD
) { /* RG */
440 blend
= V_028714_SPI_SHADER_32_GR
;
441 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
442 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
443 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
446 } else /* 16_16_16_16 */
447 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
448 } else if (ntype
== V_028C70_NUMBER_UINT
)
449 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
450 else if (ntype
== V_028C70_NUMBER_SINT
)
451 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
452 else if (ntype
== V_028C70_NUMBER_FLOAT
)
453 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
458 case V_028C70_COLOR_32
:
459 if (swap
== V_028C70_SWAP_STD
) { /* R */
460 blend
= normal
= V_028714_SPI_SHADER_32_R
;
461 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
462 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
463 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
468 case V_028C70_COLOR_32_32
:
469 if (swap
== V_028C70_SWAP_STD
) { /* RG */
470 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
471 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
472 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
473 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
478 case V_028C70_COLOR_32_32_32_32
:
479 case V_028C70_COLOR_8_24
:
480 case V_028C70_COLOR_24_8
:
481 case V_028C70_COLOR_X24_8_32_FLOAT
:
482 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
486 unreachable("unhandled blend format");
489 if (blend_enable
&& blend_need_alpha
)
491 else if(blend_need_alpha
)
493 else if(blend_enable
)
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
501 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
502 struct radv_blend_state
*blend
)
504 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
505 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
506 unsigned col_format
= 0;
507 unsigned num_targets
;
509 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
512 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
513 cf
= V_028714_SPI_SHADER_ZERO
;
515 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
517 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
519 cf
= si_choose_spi_color_format(attachment
->format
,
521 blend
->need_src_alpha
& (1 << i
));
524 col_format
|= cf
<< (4 * i
);
527 /* If the i-th target format is set, all previous target formats must
528 * be non-zero to avoid hangs.
530 num_targets
= (util_last_bit(col_format
) + 3) / 4;
531 for (unsigned i
= 0; i
< num_targets
; i
++) {
532 if (!(col_format
& (0xf << (i
* 4)))) {
533 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
537 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
539 if (blend
->mrt0_is_dual_src
)
540 col_format
|= (col_format
& 0xf) << 4;
541 blend
->spi_shader_col_format
= col_format
;
545 format_is_int8(VkFormat format
)
547 const struct vk_format_description
*desc
= vk_format_description(format
);
548 int channel
= vk_format_get_first_non_void_channel(format
);
550 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
551 desc
->channel
[channel
].size
== 8;
555 format_is_int10(VkFormat format
)
557 const struct vk_format_description
*desc
= vk_format_description(format
);
559 if (desc
->nr_channels
!= 4)
561 for (unsigned i
= 0; i
< 4; i
++) {
562 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
569 * Ordered so that for each i,
570 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
572 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
573 VK_FORMAT_R32_SFLOAT
,
574 VK_FORMAT_R32G32_SFLOAT
,
575 VK_FORMAT_R8G8B8A8_UNORM
,
576 VK_FORMAT_R16G16B16A16_UNORM
,
577 VK_FORMAT_R16G16B16A16_SNORM
,
578 VK_FORMAT_R16G16B16A16_UINT
,
579 VK_FORMAT_R16G16B16A16_SINT
,
580 VK_FORMAT_R32G32B32A32_SFLOAT
,
581 VK_FORMAT_R8G8B8A8_UINT
,
582 VK_FORMAT_R8G8B8A8_SINT
,
583 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
584 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
587 unsigned radv_format_meta_fs_key(VkFormat format
)
589 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
591 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
592 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
593 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
595 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
596 bool is_int8
= format_is_int8(format
);
597 bool is_int10
= format_is_int10(format
);
599 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
603 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
604 unsigned *is_int8
, unsigned *is_int10
)
606 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
607 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
611 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
612 struct radv_render_pass_attachment
*attachment
;
614 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
617 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
619 if (format_is_int8(attachment
->format
))
621 if (format_is_int10(attachment
->format
))
627 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
628 VkBlendOp op
, VkBlendFactor src
,
629 VkBlendFactor dst
, unsigned chanmask
)
631 /* Src factor is allowed when it does not depend on Dst. */
632 static const uint32_t src_allowed
=
633 (1u << VK_BLEND_FACTOR_ONE
) |
634 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
635 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
636 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
637 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
638 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
639 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
640 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
641 (1u << VK_BLEND_FACTOR_ZERO
) |
642 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
643 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
644 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
645 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
646 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
647 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
649 if (dst
== VK_BLEND_FACTOR_ONE
&&
650 (src_allowed
& (1u << src
))) {
651 /* Addition is commutative, but floating point addition isn't
652 * associative: subtle changes can be introduced via different
653 * rounding. Be conservative, only enable for min and max.
655 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
656 blend
->commutative_4bit
|= chanmask
;
660 static struct radv_blend_state
661 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
662 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
663 const struct radv_graphics_pipeline_create_info
*extra
)
665 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
666 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
667 struct radv_blend_state blend
= {0};
668 unsigned mode
= V_028808_CB_NORMAL
;
674 if (extra
&& extra
->custom_blend_mode
) {
675 blend
.single_cb_enable
= true;
676 mode
= extra
->custom_blend_mode
;
678 blend
.cb_color_control
= 0;
679 if (vkblend
->logicOpEnable
)
680 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
682 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
684 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
685 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
686 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
687 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
689 if (vkms
&& vkms
->alphaToCoverageEnable
) {
690 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
693 blend
.cb_target_mask
= 0;
694 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
695 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
696 unsigned blend_cntl
= 0;
697 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
698 VkBlendOp eqRGB
= att
->colorBlendOp
;
699 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
700 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
701 VkBlendOp eqA
= att
->alphaBlendOp
;
702 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
703 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
705 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
707 if (!att
->colorWriteMask
)
710 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
711 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
712 if (!att
->blendEnable
) {
713 blend
.cb_blend_control
[i
] = blend_cntl
;
717 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
719 blend
.mrt0_is_dual_src
= true;
721 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
722 srcRGB
= VK_BLEND_FACTOR_ONE
;
723 dstRGB
= VK_BLEND_FACTOR_ONE
;
725 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
726 srcA
= VK_BLEND_FACTOR_ONE
;
727 dstA
= VK_BLEND_FACTOR_ONE
;
730 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
732 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
735 /* Blending optimizations for RB+.
736 * These transformations don't change the behavior.
738 * First, get rid of DST in the blend factors:
739 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
741 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
742 VK_BLEND_FACTOR_DST_COLOR
,
743 VK_BLEND_FACTOR_SRC_COLOR
);
745 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
746 VK_BLEND_FACTOR_DST_COLOR
,
747 VK_BLEND_FACTOR_SRC_COLOR
);
749 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
750 VK_BLEND_FACTOR_DST_ALPHA
,
751 VK_BLEND_FACTOR_SRC_ALPHA
);
753 /* Look up the ideal settings from tables. */
754 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
755 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
756 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
757 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
759 /* Handle interdependencies. */
760 if (si_blend_factor_uses_dst(srcRGB
))
761 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
762 if (si_blend_factor_uses_dst(srcA
))
763 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
765 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
766 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
767 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
768 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
769 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
771 /* Set the final value. */
772 blend
.sx_mrt_blend_opt
[i
] =
773 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
774 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
775 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
776 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
777 S_028760_ALPHA_DST_OPT(dstA_opt
) |
778 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
779 blend_cntl
|= S_028780_ENABLE(1);
781 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
782 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
783 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
784 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
785 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
786 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
787 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
788 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
790 blend
.cb_blend_control
[i
] = blend_cntl
;
792 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
794 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
795 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
796 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
797 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
798 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
799 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
800 blend
.need_src_alpha
|= 1 << i
;
802 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
803 blend
.cb_blend_control
[i
] = 0;
804 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
807 if (pipeline
->device
->physical_device
->has_rbplus
) {
808 /* Disable RB+ blend optimizations for dual source blending. */
809 if (blend
.mrt0_is_dual_src
) {
810 for (i
= 0; i
< 8; i
++) {
811 blend
.sx_mrt_blend_opt
[i
] =
812 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
813 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
817 /* RB+ doesn't work with dual source blending, logic op and
820 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
821 mode
== V_028808_CB_RESOLVE
)
822 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
825 if (blend
.cb_target_mask
)
826 blend
.cb_color_control
|= S_028808_MODE(mode
);
828 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
830 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
834 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
837 case VK_STENCIL_OP_KEEP
:
838 return V_02842C_STENCIL_KEEP
;
839 case VK_STENCIL_OP_ZERO
:
840 return V_02842C_STENCIL_ZERO
;
841 case VK_STENCIL_OP_REPLACE
:
842 return V_02842C_STENCIL_REPLACE_TEST
;
843 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
844 return V_02842C_STENCIL_ADD_CLAMP
;
845 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
846 return V_02842C_STENCIL_SUB_CLAMP
;
847 case VK_STENCIL_OP_INVERT
:
848 return V_02842C_STENCIL_INVERT
;
849 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
850 return V_02842C_STENCIL_ADD_WRAP
;
851 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
852 return V_02842C_STENCIL_SUB_WRAP
;
858 static uint32_t si_translate_fill(VkPolygonMode func
)
861 case VK_POLYGON_MODE_FILL
:
862 return V_028814_X_DRAW_TRIANGLES
;
863 case VK_POLYGON_MODE_LINE
:
864 return V_028814_X_DRAW_LINES
;
865 case VK_POLYGON_MODE_POINT
:
866 return V_028814_X_DRAW_POINTS
;
869 return V_028814_X_DRAW_POINTS
;
873 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
875 uint32_t num_samples
= vkms
->rasterizationSamples
;
876 uint32_t ps_iter_samples
= 1;
878 if (vkms
->sampleShadingEnable
) {
879 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
880 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
882 return ps_iter_samples
;
886 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
888 return pCreateInfo
->depthTestEnable
&&
889 pCreateInfo
->depthWriteEnable
&&
890 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
894 radv_writes_stencil(const VkStencilOpState
*state
)
896 return state
->writeMask
&&
897 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
898 state
->passOp
!= VK_STENCIL_OP_KEEP
||
899 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
903 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
905 return pCreateInfo
->stencilTestEnable
&&
906 (radv_writes_stencil(&pCreateInfo
->front
) ||
907 radv_writes_stencil(&pCreateInfo
->back
));
911 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
913 return radv_is_depth_write_enabled(pCreateInfo
) ||
914 radv_is_stencil_write_enabled(pCreateInfo
);
918 radv_order_invariant_stencil_op(VkStencilOp op
)
920 /* REPLACE is normally order invariant, except when the stencil
921 * reference value is written by the fragment shader. Tracking this
922 * interaction does not seem worth the effort, so be conservative.
924 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
925 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
926 op
!= VK_STENCIL_OP_REPLACE
;
930 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
932 /* Compute whether, assuming Z writes are disabled, this stencil state
933 * is order invariant in the sense that the set of passing fragments as
934 * well as the final stencil buffer result does not depend on the order
937 return !state
->writeMask
||
938 /* The following assumes that Z writes are disabled. */
939 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
940 radv_order_invariant_stencil_op(state
->passOp
) &&
941 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
942 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
943 radv_order_invariant_stencil_op(state
->failOp
));
947 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
948 struct radv_blend_state
*blend
,
949 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
951 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
952 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
953 unsigned colormask
= blend
->cb_target_enabled_4bit
;
955 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
958 /* Be conservative if a logic operation is enabled with color buffers. */
959 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
962 /* Default depth/stencil invariance when no attachment is bound. */
963 struct radv_dsa_order_invariance dsa_order_invariant
= {
964 .zs
= true, .pass_set
= true
967 if (pCreateInfo
->pDepthStencilState
&&
968 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
969 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
970 pCreateInfo
->pDepthStencilState
;
971 struct radv_render_pass_attachment
*attachment
=
972 pass
->attachments
+ subpass
->depth_stencil_attachment
.attachment
;
973 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
974 struct radv_dsa_order_invariance order_invariance
[2];
975 struct radv_shader_variant
*ps
=
976 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
978 /* Compute depth/stencil order invariance in order to know if
979 * it's safe to enable out-of-order.
981 bool zfunc_is_ordered
=
982 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
983 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
984 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
985 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
986 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
988 bool nozwrite_and_order_invariant_stencil
=
989 !radv_is_ds_write_enabled(vkds
) ||
990 (!radv_is_depth_write_enabled(vkds
) &&
991 radv_order_invariant_stencil_state(&vkds
->front
) &&
992 radv_order_invariant_stencil_state(&vkds
->back
));
994 order_invariance
[1].zs
=
995 nozwrite_and_order_invariant_stencil
||
996 (!radv_is_stencil_write_enabled(vkds
) &&
998 order_invariance
[0].zs
=
999 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1001 order_invariance
[1].pass_set
=
1002 nozwrite_and_order_invariant_stencil
||
1003 (!radv_is_stencil_write_enabled(vkds
) &&
1004 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1005 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1006 order_invariance
[0].pass_set
=
1007 !radv_is_depth_write_enabled(vkds
) ||
1008 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1009 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1011 dsa_order_invariant
= order_invariance
[has_stencil
];
1012 if (!dsa_order_invariant
.zs
)
1015 /* The set of PS invocations is always order invariant,
1016 * except when early Z/S tests are requested.
1019 ps
->info
.info
.ps
.writes_memory
&&
1020 ps
->info
.fs
.early_fragment_test
&&
1021 !dsa_order_invariant
.pass_set
)
1024 /* Determine if out-of-order rasterization should be disabled
1025 * when occlusion queries are used.
1027 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1028 !dsa_order_invariant
.pass_set
;
1031 /* No color buffers are enabled for writing. */
1035 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1038 /* Only commutative blending. */
1039 if (blendmask
& ~blend
->commutative_4bit
)
1042 if (!dsa_order_invariant
.pass_set
)
1046 if (colormask
& ~blendmask
)
1053 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1054 struct radv_blend_state
*blend
,
1055 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1057 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1058 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1059 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1060 bool out_of_order_rast
= false;
1061 int ps_iter_samples
= 1;
1062 uint32_t mask
= 0xffff;
1065 ms
->num_samples
= vkms
->rasterizationSamples
;
1067 ms
->num_samples
= 1;
1070 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1071 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.force_persample
) {
1072 ps_iter_samples
= ms
->num_samples
;
1075 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1076 ms
->pa_sc_aa_config
= 0;
1077 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1078 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1079 ms
->pa_sc_mode_cntl_1
=
1080 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1081 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1083 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1084 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1085 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1086 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1087 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1088 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1089 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1090 S_028A48_VPORT_SCISSOR_ENABLE(1);
1092 if (ms
->num_samples
> 1) {
1093 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1094 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1095 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1096 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1097 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1098 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1099 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1100 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1101 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1102 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
1103 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1104 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1105 if (ps_iter_samples
> 1)
1106 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1109 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1110 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1111 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1112 /* Out-of-order rasterization is explicitly enabled by the
1115 out_of_order_rast
= true;
1117 /* Determine if the driver can enable out-of-order
1118 * rasterization internally.
1121 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1124 if (out_of_order_rast
) {
1125 ms
->pa_sc_mode_cntl_1
|= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1126 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1129 if (vkms
&& vkms
->pSampleMask
) {
1130 mask
= vkms
->pSampleMask
[0] & 0xffff;
1133 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1134 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1138 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1141 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1142 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1143 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1144 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1145 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1147 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1148 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1149 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1150 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1151 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1152 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1155 unreachable("unhandled primitive type");
1160 si_translate_prim(enum VkPrimitiveTopology topology
)
1163 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1164 return V_008958_DI_PT_POINTLIST
;
1165 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1166 return V_008958_DI_PT_LINELIST
;
1167 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1168 return V_008958_DI_PT_LINESTRIP
;
1169 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1170 return V_008958_DI_PT_TRILIST
;
1171 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1172 return V_008958_DI_PT_TRISTRIP
;
1173 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1174 return V_008958_DI_PT_TRIFAN
;
1175 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1176 return V_008958_DI_PT_LINELIST_ADJ
;
1177 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1178 return V_008958_DI_PT_LINESTRIP_ADJ
;
1179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1180 return V_008958_DI_PT_TRILIST_ADJ
;
1181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1182 return V_008958_DI_PT_TRISTRIP_ADJ
;
1183 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1184 return V_008958_DI_PT_PATCH
;
1192 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1195 case 0: /* GL_POINTS */
1196 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1197 case 1: /* GL_LINES */
1198 case 3: /* GL_LINE_STRIP */
1199 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1200 case 0x8E7A: /* GL_ISOLINES */
1201 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1203 case 4: /* GL_TRIANGLES */
1204 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1205 case 5: /* GL_TRIANGLE_STRIP */
1206 case 7: /* GL_QUADS */
1207 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1215 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1218 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1219 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1220 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1221 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1222 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1223 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1224 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1225 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1228 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1231 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1238 static unsigned si_map_swizzle(unsigned swizzle
)
1242 return V_008F0C_SQ_SEL_Y
;
1244 return V_008F0C_SQ_SEL_Z
;
1246 return V_008F0C_SQ_SEL_W
;
1248 return V_008F0C_SQ_SEL_0
;
1250 return V_008F0C_SQ_SEL_1
;
1251 default: /* VK_SWIZZLE_X */
1252 return V_008F0C_SQ_SEL_X
;
1257 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1260 case VK_DYNAMIC_STATE_VIEWPORT
:
1261 return RADV_DYNAMIC_VIEWPORT
;
1262 case VK_DYNAMIC_STATE_SCISSOR
:
1263 return RADV_DYNAMIC_SCISSOR
;
1264 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1265 return RADV_DYNAMIC_LINE_WIDTH
;
1266 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1267 return RADV_DYNAMIC_DEPTH_BIAS
;
1268 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1269 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1270 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1271 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1272 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1273 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1274 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1275 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1276 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1277 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1278 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1279 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1281 unreachable("Unhandled dynamic state");
1285 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1287 uint32_t states
= RADV_DYNAMIC_ALL
;
1289 /* If rasterization is disabled we do not care about any of the dynamic states,
1290 * since they are all rasterization related only. */
1291 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1294 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1295 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1297 if (!pCreateInfo
->pDepthStencilState
||
1298 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1299 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1301 if (!pCreateInfo
->pDepthStencilState
||
1302 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1303 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1304 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1305 RADV_DYNAMIC_STENCIL_REFERENCE
);
1307 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1308 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1310 /* TODO: blend constants & line width. */
1317 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1318 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1320 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1321 uint32_t states
= needed_states
;
1322 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1323 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1325 pipeline
->dynamic_state
= default_dynamic_state
;
1326 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1328 if (pCreateInfo
->pDynamicState
) {
1329 /* Remove all of the states that are marked as dynamic */
1330 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1331 for (uint32_t s
= 0; s
< count
; s
++)
1332 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1335 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1337 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1338 assert(pCreateInfo
->pViewportState
);
1340 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1341 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1342 typed_memcpy(dynamic
->viewport
.viewports
,
1343 pCreateInfo
->pViewportState
->pViewports
,
1344 pCreateInfo
->pViewportState
->viewportCount
);
1348 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1349 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1350 if (states
& RADV_DYNAMIC_SCISSOR
) {
1351 typed_memcpy(dynamic
->scissor
.scissors
,
1352 pCreateInfo
->pViewportState
->pScissors
,
1353 pCreateInfo
->pViewportState
->scissorCount
);
1357 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1358 assert(pCreateInfo
->pRasterizationState
);
1359 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1362 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1363 assert(pCreateInfo
->pRasterizationState
);
1364 dynamic
->depth_bias
.bias
=
1365 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1366 dynamic
->depth_bias
.clamp
=
1367 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1368 dynamic
->depth_bias
.slope
=
1369 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1372 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1374 * pColorBlendState is [...] NULL if the pipeline has rasterization
1375 * disabled or if the subpass of the render pass the pipeline is
1376 * created against does not use any color attachments.
1378 bool uses_color_att
= false;
1379 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1380 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1381 uses_color_att
= true;
1386 if (uses_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1387 assert(pCreateInfo
->pColorBlendState
);
1388 typed_memcpy(dynamic
->blend_constants
,
1389 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1392 /* If there is no depthstencil attachment, then don't read
1393 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1394 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1395 * no need to override the depthstencil defaults in
1396 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1398 * Section 9.2 of the Vulkan 1.0.15 spec says:
1400 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1401 * disabled or if the subpass of the render pass the pipeline is created
1402 * against does not use a depth/stencil attachment.
1404 if (needed_states
&&
1405 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1406 assert(pCreateInfo
->pDepthStencilState
);
1408 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1409 dynamic
->depth_bounds
.min
=
1410 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1411 dynamic
->depth_bounds
.max
=
1412 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1415 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1416 dynamic
->stencil_compare_mask
.front
=
1417 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1418 dynamic
->stencil_compare_mask
.back
=
1419 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1422 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1423 dynamic
->stencil_write_mask
.front
=
1424 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1425 dynamic
->stencil_write_mask
.back
=
1426 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1429 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1430 dynamic
->stencil_reference
.front
=
1431 pCreateInfo
->pDepthStencilState
->front
.reference
;
1432 dynamic
->stencil_reference
.back
=
1433 pCreateInfo
->pDepthStencilState
->back
.reference
;
1437 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1438 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1439 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1440 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1441 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1442 discard_rectangle_info
->pDiscardRectangles
,
1443 discard_rectangle_info
->discardRectangleCount
);
1446 pipeline
->dynamic_state
.mask
= states
;
1449 static struct radv_gs_state
1450 calculate_gs_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1451 const struct radv_pipeline
*pipeline
)
1453 struct radv_gs_state gs
= {0};
1454 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1455 struct radv_es_output_info
*es_info
;
1456 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1457 es_info
= radv_pipeline_has_tess(pipeline
) ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1459 es_info
= radv_pipeline_has_tess(pipeline
) ?
1460 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1461 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1463 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1464 bool uses_adjacency
;
1465 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1466 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1467 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1468 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1469 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1470 uses_adjacency
= true;
1473 uses_adjacency
= false;
1477 /* All these are in dwords: */
1478 /* We can't allow using the whole LDS, because GS waves compete with
1479 * other shader stages for LDS space. */
1480 const unsigned max_lds_size
= 8 * 1024;
1481 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1482 unsigned esgs_lds_size
;
1484 /* All these are per subgroup: */
1485 const unsigned max_out_prims
= 32 * 1024;
1486 const unsigned max_es_verts
= 255;
1487 const unsigned ideal_gs_prims
= 64;
1488 unsigned max_gs_prims
, gs_prims
;
1489 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1491 if (uses_adjacency
|| gs_num_invocations
> 1)
1492 max_gs_prims
= 127 / gs_num_invocations
;
1496 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1497 * Make sure we don't go over the maximum value.
1499 if (gs_info
->gs
.vertices_out
> 0) {
1500 max_gs_prims
= MIN2(max_gs_prims
,
1502 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1504 assert(max_gs_prims
> 0);
1506 /* If the primitive has adjacency, halve the number of vertices
1507 * that will be reused in multiple primitives.
1509 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1511 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1512 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1514 /* Compute ESGS LDS size based on the worst case number of ES vertices
1515 * needed to create the target number of GS prims per subgroup.
1517 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1519 /* If total LDS usage is too big, refactor partitions based on ratio
1520 * of ESGS item sizes.
1522 if (esgs_lds_size
> max_lds_size
) {
1523 /* Our target GS Prims Per Subgroup was too large. Calculate
1524 * the maximum number of GS Prims Per Subgroup that will fit
1525 * into LDS, capped by the maximum that the hardware can support.
1527 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1529 assert(gs_prims
> 0);
1530 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1533 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1534 assert(esgs_lds_size
<= max_lds_size
);
1537 /* Now calculate remaining ESGS information. */
1539 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1541 es_verts
= max_es_verts
;
1543 /* Vertices for adjacency primitives are not always reused, so restore
1544 * it for ES_VERTS_PER_SUBGRP.
1546 min_es_verts
= gs_info
->gs
.vertices_in
;
1548 /* For normal primitives, the VGT only checks if they are past the ES
1549 * verts per subgroup after allocating a full GS primitive and if they
1550 * are, kick off a new subgroup. But if those additional ES verts are
1551 * unique (e.g. not reused) we need to make sure there is enough LDS
1552 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1554 es_verts
-= min_es_verts
- 1;
1556 uint32_t es_verts_per_subgroup
= es_verts
;
1557 uint32_t gs_prims_per_subgroup
= gs_prims
;
1558 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1559 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1560 gs
.lds_size
= align(esgs_lds_size
, 128) / 128;
1561 gs
.vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1562 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1563 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1564 gs
.vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1565 gs
.vgt_esgs_ring_itemsize
= esgs_itemsize
;
1566 assert(max_prims_per_subgroup
<= max_out_prims
);
1572 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
, const struct radv_gs_state
*gs
)
1574 struct radv_device
*device
= pipeline
->device
;
1575 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1576 unsigned wave_size
= 64;
1577 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1578 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1579 unsigned alignment
= 256 * num_se
;
1580 /* The maximum size is 63.999 MB per SE. */
1581 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1582 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1584 /* Calculate the minimum size. */
1585 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1586 wave_size
, alignment
);
1587 /* These are recommended sizes, not minimum sizes. */
1588 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1589 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1590 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1591 gs_info
->gs
.max_gsvs_emit_size
* 1; // no streams in VK (gs->max_gs_stream + 1);
1593 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1594 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1595 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1597 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= VI
)
1598 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1600 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1603 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1606 /* If tessellation is all offchip and on-chip GS isn't used, this
1607 * workaround is not needed.
1611 /* SPI barrier management bug:
1612 * Make sure we have at least 4k of LDS in use to avoid the bug.
1613 * It applies to workgroup sizes of more than one wavefront.
1615 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1616 device
->physical_device
->rad_info
.family
== CHIP_KABINI
||
1617 device
->physical_device
->rad_info
.family
== CHIP_MULLINS
)
1618 *lds_size
= MAX2(*lds_size
, 8);
1621 struct radv_shader_variant
*
1622 radv_get_shader(struct radv_pipeline
*pipeline
,
1623 gl_shader_stage stage
)
1625 if (stage
== MESA_SHADER_VERTEX
) {
1626 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1627 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1628 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1629 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1630 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1631 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1632 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1633 if (!radv_pipeline_has_tess(pipeline
))
1635 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1636 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1637 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1638 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1640 return pipeline
->shaders
[stage
];
1643 static struct radv_tessellation_state
1644 calculate_tess_state(struct radv_pipeline
*pipeline
,
1645 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1647 unsigned num_tcs_input_cp
;
1648 unsigned num_tcs_output_cp
;
1650 unsigned num_patches
;
1651 struct radv_tessellation_state tess
= {0};
1653 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1654 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1655 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1657 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1659 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1660 assert(lds_size
<= 65536);
1661 lds_size
= align(lds_size
, 512) / 512;
1663 assert(lds_size
<= 32768);
1664 lds_size
= align(lds_size
, 256) / 256;
1666 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1668 tess
.lds_size
= lds_size
;
1670 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1671 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1672 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1673 tess
.num_patches
= num_patches
;
1675 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1676 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1678 switch (tes
->info
.tes
.primitive_mode
) {
1680 type
= V_028B6C_TESS_TRIANGLE
;
1683 type
= V_028B6C_TESS_QUAD
;
1686 type
= V_028B6C_TESS_ISOLINE
;
1690 switch (tes
->info
.tes
.spacing
) {
1691 case TESS_SPACING_EQUAL
:
1692 partitioning
= V_028B6C_PART_INTEGER
;
1694 case TESS_SPACING_FRACTIONAL_ODD
:
1695 partitioning
= V_028B6C_PART_FRAC_ODD
;
1697 case TESS_SPACING_FRACTIONAL_EVEN
:
1698 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1704 bool ccw
= tes
->info
.tes
.ccw
;
1705 const VkPipelineTessellationDomainOriginStateCreateInfoKHR
*domain_origin_state
=
1706 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1707 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR
);
1709 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR
)
1712 if (tes
->info
.tes
.point_mode
)
1713 topology
= V_028B6C_OUTPUT_POINT
;
1714 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1715 topology
= V_028B6C_OUTPUT_LINE
;
1717 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1719 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
1721 if (pipeline
->device
->has_distributed_tess
) {
1722 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1723 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
1724 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
1726 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
1728 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
1730 tess
.tf_param
= S_028B6C_TYPE(type
) |
1731 S_028B6C_PARTITIONING(partitioning
) |
1732 S_028B6C_TOPOLOGY(topology
) |
1733 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
1738 static const struct radv_prim_vertex_count prim_size_table
[] = {
1739 [V_008958_DI_PT_NONE
] = {0, 0},
1740 [V_008958_DI_PT_POINTLIST
] = {1, 1},
1741 [V_008958_DI_PT_LINELIST
] = {2, 2},
1742 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
1743 [V_008958_DI_PT_TRILIST
] = {3, 3},
1744 [V_008958_DI_PT_TRIFAN
] = {3, 1},
1745 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
1746 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
1747 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
1748 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
1749 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
1750 [V_008958_DI_PT_RECTLIST
] = {3, 3},
1751 [V_008958_DI_PT_LINELOOP
] = {2, 1},
1752 [V_008958_DI_PT_POLYGON
] = {3, 1},
1753 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
1756 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
1758 if (radv_pipeline_has_gs(pipeline
))
1759 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
1760 else if (radv_pipeline_has_tess(pipeline
))
1761 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
1763 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
1767 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
1769 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
1770 int shader_count
= 0;
1772 if(shaders
[MESA_SHADER_FRAGMENT
]) {
1773 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
1775 if(shaders
[MESA_SHADER_GEOMETRY
]) {
1776 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
1778 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
1779 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
1781 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
1782 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
1784 if(shaders
[MESA_SHADER_VERTEX
]) {
1785 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
1788 for (int i
= 1; i
< shader_count
; ++i
) {
1789 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
1790 ordered_shaders
[i
- 1]);
1792 nir_remove_dead_variables(ordered_shaders
[i
],
1793 nir_var_shader_out
);
1794 nir_remove_dead_variables(ordered_shaders
[i
- 1],
1797 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
1798 ordered_shaders
[i
- 1]);
1800 nir_compact_varyings(ordered_shaders
[i
],
1801 ordered_shaders
[i
- 1], true);
1804 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
1805 ac_lower_indirect_derefs(ordered_shaders
[i
],
1806 pipeline
->device
->physical_device
->rad_info
.chip_class
);
1808 radv_optimize_nir(ordered_shaders
[i
], false);
1810 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
1811 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
1812 pipeline
->device
->physical_device
->rad_info
.chip_class
);
1814 radv_optimize_nir(ordered_shaders
[i
- 1], false);
1820 static struct radv_pipeline_key
1821 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
1822 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1823 const struct radv_blend_state
*blend
,
1824 bool has_view_index
)
1826 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1827 pCreateInfo
->pVertexInputState
;
1828 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
1829 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1831 struct radv_pipeline_key key
;
1832 memset(&key
, 0, sizeof(key
));
1834 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
1835 key
.optimisations_disabled
= 1;
1837 key
.has_multiview_view_index
= has_view_index
;
1839 uint32_t binding_input_rate
= 0;
1840 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
1841 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
1842 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
1843 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
1844 binding_input_rate
|= 1u << binding
;
1845 instance_rate_divisors
[binding
] = 1;
1848 if (divisor_state
) {
1849 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
1850 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
1851 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
1855 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1856 unsigned location
= input_state
->pVertexAttributeDescriptions
[i
].location
;
1857 unsigned binding
= input_state
->pVertexAttributeDescriptions
[i
].binding
;
1858 if (binding_input_rate
& (1u << binding
)) {
1859 key
.instance_rate_inputs
|= 1u << location
;
1860 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
1863 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= VI
&&
1864 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
1865 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
1868 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
1869 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
1870 adjust
= RADV_ALPHA_ADJUST_SNORM
;
1872 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
1873 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
1874 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
1876 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
1877 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
1878 adjust
= RADV_ALPHA_ADJUST_SINT
;
1884 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
1888 if (pCreateInfo
->pTessellationState
)
1889 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1892 if (pCreateInfo
->pMultisampleState
&&
1893 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
1894 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
1895 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
1896 key
.num_samples
= num_samples
;
1897 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1900 key
.col_format
= blend
->spi_shader_col_format
;
1901 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< VI
)
1902 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
1908 radv_fill_shader_keys(struct radv_shader_variant_key
*keys
,
1909 const struct radv_pipeline_key
*key
,
1912 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
1913 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
1914 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
)
1915 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
1917 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1918 keys
[MESA_SHADER_VERTEX
].vs
.as_ls
= true;
1919 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
1920 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
1921 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
1923 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
1926 if (nir
[MESA_SHADER_GEOMETRY
]) {
1927 if (nir
[MESA_SHADER_TESS_CTRL
])
1928 keys
[MESA_SHADER_TESS_EVAL
].tes
.as_es
= true;
1930 keys
[MESA_SHADER_VERTEX
].vs
.as_es
= true;
1933 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
1934 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
1936 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
1937 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
1938 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
1939 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
1940 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
1944 merge_tess_info(struct shader_info
*tes_info
,
1945 const struct shader_info
*tcs_info
)
1947 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1949 * "PointMode. Controls generation of points rather than triangles
1950 * or lines. This functionality defaults to disabled, and is
1951 * enabled if either shader stage includes the execution mode.
1953 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1954 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1955 * and OutputVertices, it says:
1957 * "One mode must be set in at least one of the tessellation
1960 * So, the fields can be set in either the TCS or TES, but they must
1961 * agree if set in both. Our backend looks at TES, so bitwise-or in
1962 * the values from the TCS.
1964 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
1965 tes_info
->tess
.tcs_vertices_out
== 0 ||
1966 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
1967 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
1969 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
1970 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
1971 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
1972 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
1974 assert(tcs_info
->tess
.primitive_mode
== 0 ||
1975 tes_info
->tess
.primitive_mode
== 0 ||
1976 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
1977 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
1978 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
1979 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
1983 void radv_create_shaders(struct radv_pipeline
*pipeline
,
1984 struct radv_device
*device
,
1985 struct radv_pipeline_cache
*cache
,
1986 struct radv_pipeline_key key
,
1987 const VkPipelineShaderStageCreateInfo
**pStages
,
1988 const VkPipelineCreateFlags flags
)
1990 struct radv_shader_module fs_m
= {0};
1991 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1992 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
1993 void *codes
[MESA_SHADER_STAGES
] = {0};
1994 unsigned code_sizes
[MESA_SHADER_STAGES
] = {0};
1995 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{0}}}};
1996 unsigned char hash
[20], gs_copy_hash
[20];
1998 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2000 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2001 if (modules
[i
]->nir
)
2002 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2003 strlen(modules
[i
]->nir
->info
.name
),
2006 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2010 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, &key
, get_hash_flags(device
));
2011 memcpy(gs_copy_hash
, hash
, 20);
2012 gs_copy_hash
[0] ^= 1;
2014 if (modules
[MESA_SHADER_GEOMETRY
]) {
2015 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2016 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
);
2017 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2020 if (radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
) &&
2021 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2025 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2027 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2028 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2029 fs_m
.nir
= fs_b
.shader
;
2030 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2033 /* Determine first and last stage. */
2034 unsigned first
= MESA_SHADER_STAGES
;
2036 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2039 if (first
== MESA_SHADER_STAGES
)
2044 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2045 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2050 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2051 stage
? stage
->pName
: "main", i
,
2052 stage
? stage
->pSpecializationInfo
: NULL
,
2055 /* We don't want to alter meta shaders IR directly so clone it
2058 if (nir
[i
]->info
.name
) {
2059 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2062 if (first
!= last
) {
2063 nir_variable_mode mask
= 0;
2066 mask
= mask
| nir_var_shader_in
;
2069 mask
= mask
| nir_var_shader_out
;
2071 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)) {
2072 nir_lower_io_to_scalar_early(nir
[i
], mask
);
2073 radv_optimize_nir(nir
[i
], false);
2078 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2079 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2080 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2083 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2084 radv_link_shaders(pipeline
, nir
);
2086 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2087 if (radv_can_dump_shader(device
, modules
[i
], false))
2088 nir_print_shader(nir
[i
], stderr
);
2091 radv_fill_shader_keys(keys
, &key
, nir
);
2093 if (nir
[MESA_SHADER_FRAGMENT
]) {
2094 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2095 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2096 radv_shader_variant_create(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2097 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2098 &codes
[MESA_SHADER_FRAGMENT
], &code_sizes
[MESA_SHADER_FRAGMENT
]);
2101 /* TODO: These are no longer used as keys we should refactor this */
2102 keys
[MESA_SHADER_VERTEX
].vs
.export_prim_id
=
2103 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2104 keys
[MESA_SHADER_VERTEX
].vs
.export_layer_id
=
2105 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2106 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_prim_id
=
2107 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2108 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_layer_id
=
2109 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2112 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2113 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2114 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2115 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2116 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2117 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2119 &key
, &codes
[MESA_SHADER_TESS_CTRL
],
2120 &code_sizes
[MESA_SHADER_TESS_CTRL
]);
2122 modules
[MESA_SHADER_VERTEX
] = NULL
;
2123 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2124 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2127 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2128 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2129 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2130 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2131 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2133 &keys
[pre_stage
] , &codes
[MESA_SHADER_GEOMETRY
],
2134 &code_sizes
[MESA_SHADER_GEOMETRY
]);
2136 modules
[pre_stage
] = NULL
;
2139 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2140 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2141 if (i
== MESA_SHADER_TESS_CTRL
) {
2142 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.ls_outputs_written
);
2144 if (i
== MESA_SHADER_TESS_EVAL
) {
2145 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2146 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2148 pipeline
->shaders
[i
] = radv_shader_variant_create(device
, modules
[i
], &nir
[i
], 1,
2150 keys
+ i
, &codes
[i
],
2155 if(modules
[MESA_SHADER_GEOMETRY
]) {
2156 void *gs_copy_code
= NULL
;
2157 unsigned gs_copy_code_size
= 0;
2158 if (!pipeline
->gs_copy_shader
) {
2159 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2160 device
, nir
[MESA_SHADER_GEOMETRY
], &gs_copy_code
,
2162 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2165 if (pipeline
->gs_copy_shader
) {
2166 void *code
[MESA_SHADER_STAGES
] = {0};
2167 unsigned code_size
[MESA_SHADER_STAGES
] = {0};
2168 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2170 code
[MESA_SHADER_GEOMETRY
] = gs_copy_code
;
2171 code_size
[MESA_SHADER_GEOMETRY
] = gs_copy_code_size
;
2172 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2174 radv_pipeline_cache_insert_shaders(device
, cache
,
2183 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2184 (const void**)codes
, code_sizes
);
2186 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2189 if (!pipeline
->device
->keep_shader_info
)
2190 ralloc_free(nir
[i
]);
2192 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2193 radv_shader_dump_stats(device
,
2194 pipeline
->shaders
[i
],
2200 ralloc_free(fs_m
.nir
);
2204 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2205 gl_shader_stage stage
, enum chip_class chip_class
)
2207 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2208 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2210 case MESA_SHADER_FRAGMENT
:
2211 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2212 case MESA_SHADER_VERTEX
:
2213 if (chip_class
>= GFX9
) {
2214 return has_tess
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2215 has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2216 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2219 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2221 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2222 case MESA_SHADER_GEOMETRY
:
2223 return chip_class
>= GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2224 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2225 case MESA_SHADER_COMPUTE
:
2226 return R_00B900_COMPUTE_USER_DATA_0
;
2227 case MESA_SHADER_TESS_CTRL
:
2228 return chip_class
>= GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2229 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2230 case MESA_SHADER_TESS_EVAL
:
2231 if (chip_class
>= GFX9
) {
2232 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2233 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2236 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2238 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2240 unreachable("unknown shader");
2244 struct radv_bin_size_entry
{
2250 radv_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2252 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2256 /* One shader engine */
2262 { UINT_MAX
, { 0, 0}},
2265 /* Two shader engines */
2271 { UINT_MAX
, { 0, 0}},
2274 /* Four shader engines */
2279 { UINT_MAX
, { 0, 0}},
2285 /* One shader engine */
2291 { UINT_MAX
, { 0, 0}},
2294 /* Two shader engines */
2300 { UINT_MAX
, { 0, 0}},
2303 /* Four shader engines */
2310 { UINT_MAX
, { 0, 0}},
2316 /* One shader engine */
2323 { UINT_MAX
, { 0, 0}},
2326 /* Two shader engines */
2334 { UINT_MAX
, { 0, 0}},
2337 /* Four shader engines */
2345 { UINT_MAX
, { 0, 0}},
2349 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
2353 // One shader engine
2360 { UINT_MAX
, { 0, 0}},
2363 // Two shader engines
2371 { UINT_MAX
, { 0, 0}},
2374 // Four shader engines
2382 { UINT_MAX
, { 0, 0}},
2388 // One shader engine
2396 { UINT_MAX
, { 0, 0}},
2399 // Two shader engines
2408 { UINT_MAX
, { 0, 0}},
2411 // Four shader engines
2420 { UINT_MAX
, { 0, 0}},
2426 // One shader engine
2434 { UINT_MAX
, { 0, 0}},
2437 // Two shader engines
2446 { UINT_MAX
, { 0, 0}},
2449 // Four shader engines
2457 { UINT_MAX
, { 0, 0}},
2462 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2463 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2464 VkExtent2D extent
= {512, 512};
2466 unsigned log_num_rb_per_se
=
2467 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
2468 pipeline
->device
->physical_device
->rad_info
.max_se
);
2469 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
2471 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
2472 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
2473 unsigned effective_samples
= total_samples
;
2474 unsigned color_bytes_per_pixel
= 0;
2476 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
2478 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2479 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
2482 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
2485 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
2486 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
2489 /* MSAA images typically don't use all samples all the time. */
2490 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
2491 effective_samples
= 2;
2492 color_bytes_per_pixel
*= effective_samples
;
2495 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
2496 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
2499 extent
= color_entry
->extent
;
2501 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2502 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
.attachment
;
2504 /* Coefficients taken from AMDVLK */
2505 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
2506 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
2507 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
2509 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
2510 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
2513 extent
.width
= MIN2(extent
.width
, ds_entry
->extent
.width
);
2514 extent
.height
= MIN2(extent
.height
, ds_entry
->extent
.height
);
2521 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*cs
,
2522 struct radv_pipeline
*pipeline
,
2523 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2525 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
2528 uint32_t pa_sc_binner_cntl_0
=
2529 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
2530 S_028C44_DISABLE_START_OF_PRIM(1);
2531 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
2533 VkExtent2D bin_size
= radv_compute_bin_size(pipeline
, pCreateInfo
);
2535 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
2536 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
2537 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
2539 switch (pipeline
->device
->physical_device
->rad_info
.family
) {
2542 context_states_per_bin
= 1;
2543 persistent_states_per_bin
= 1;
2544 fpovs_per_batch
= 63;
2547 context_states_per_bin
= 6;
2548 persistent_states_per_bin
= 32;
2549 fpovs_per_batch
= 63;
2552 unreachable("unhandled family while determining binning state.");
2555 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
2556 pa_sc_binner_cntl_0
=
2557 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
2558 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
2559 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
2560 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
2561 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
2562 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
2563 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
2564 S_028C44_DISABLE_START_OF_PRIM(1) |
2565 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
2566 S_028C44_OPTIMAL_BIN_SELECTION(1);
2569 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
2570 pa_sc_binner_cntl_0
);
2571 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
2577 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*cs
,
2578 struct radv_pipeline
*pipeline
,
2579 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2580 const struct radv_graphics_pipeline_create_info
*extra
)
2582 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
2583 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2584 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2585 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
2586 struct radv_render_pass_attachment
*attachment
= NULL
;
2587 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
2588 uint32_t db_render_control
= 0, db_render_override2
= 0;
2589 uint32_t db_render_override
= 0;
2591 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
2592 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
.attachment
;
2594 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
2595 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
2597 if (vkds
&& has_depth_attachment
) {
2598 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
2599 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
2600 S_028800_ZFUNC(vkds
->depthCompareOp
) |
2601 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
2603 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2604 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
2607 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
2608 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2609 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
2610 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
2611 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
2612 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
2614 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
2615 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
2616 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
2617 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
2620 if (attachment
&& extra
) {
2621 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
2622 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
2624 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
2625 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
2626 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
2627 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
2628 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
2631 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2632 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2634 if (pipeline
->device
->enabled_extensions
.EXT_depth_range_unrestricted
&&
2635 !pCreateInfo
->pRasterizationState
->depthClampEnable
&&
2636 ps
->info
.info
.ps
.writes_z
) {
2637 /* From VK_EXT_depth_range_unrestricted spec:
2639 * "The behavior described in Primitive Clipping still applies.
2640 * If depth clamping is disabled the depth values are still
2641 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2642 * depth clamping is enabled the above equation is ignored and
2643 * the depth values are instead clamped to the VkViewport
2644 * minDepth and maxDepth values, which in the case of this
2645 * extension can be outside of the 0.0 to 1.0 range."
2647 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2650 radeon_set_context_reg(cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
2651 radeon_set_context_reg(cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
2653 radeon_set_context_reg(cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
2654 radeon_set_context_reg(cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2655 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
2659 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*cs
,
2660 struct radv_pipeline
*pipeline
,
2661 const struct radv_blend_state
*blend
)
2663 radeon_set_context_reg_seq(cs
, R_028780_CB_BLEND0_CONTROL
, 8);
2664 radeon_emit_array(cs
, blend
->cb_blend_control
,
2666 radeon_set_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
2667 radeon_set_context_reg(cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
2669 if (pipeline
->device
->physical_device
->has_rbplus
) {
2671 radeon_set_context_reg_seq(cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
2672 radeon_emit_array(cs
, blend
->sx_mrt_blend_opt
, 8);
2675 radeon_set_context_reg(cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
2677 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
2678 radeon_set_context_reg(cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
2680 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
2681 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
2686 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*cs
,
2687 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2689 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
2691 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
2692 S_028810_PS_UCP_MODE(3) |
2693 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2694 S_028810_ZCLIP_NEAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
2695 S_028810_ZCLIP_FAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
2696 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
2697 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2699 radeon_set_context_reg(cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
2700 S_0286D4_FLAT_SHADE_ENA(1) |
2701 S_0286D4_PNT_SPRITE_ENA(1) |
2702 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
2703 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
2704 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
2705 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
2706 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2708 radeon_set_context_reg(cs
, R_028BE4_PA_SU_VTX_CNTL
,
2709 S_028BE4_PIX_CENTER(1) | // TODO verify
2710 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
2711 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
2713 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
,
2714 S_028814_FACE(vkraster
->frontFace
) |
2715 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
2716 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
2717 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
2718 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
2719 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
2720 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
2721 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
2722 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
2727 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*cs
,
2728 struct radv_pipeline
*pipeline
)
2730 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
2732 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2733 radeon_emit(cs
, ms
->pa_sc_aa_mask
[0]);
2734 radeon_emit(cs
, ms
->pa_sc_aa_mask
[1]);
2736 radeon_set_context_reg(cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
2737 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
2741 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*cs
,
2742 const struct radv_pipeline
*pipeline
)
2744 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2746 uint32_t vgt_primitiveid_en
= false;
2747 uint32_t vgt_gs_mode
= 0;
2749 if (radv_pipeline_has_gs(pipeline
)) {
2750 const struct radv_shader_variant
*gs
=
2751 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2753 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
2754 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2755 } else if (outinfo
->export_prim_id
) {
2756 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2757 vgt_primitiveid_en
= true;
2760 radeon_set_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
2761 radeon_set_context_reg(cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
2765 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*cs
,
2766 struct radv_pipeline
*pipeline
,
2767 struct radv_shader_variant
*shader
)
2769 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2771 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
2772 radeon_emit(cs
, va
>> 8);
2773 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
2774 radeon_emit(cs
, shader
->rsrc1
);
2775 radeon_emit(cs
, shader
->rsrc2
);
2777 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2778 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
2779 clip_dist_mask
= outinfo
->clip_dist_mask
;
2780 cull_dist_mask
= outinfo
->cull_dist_mask
;
2781 total_mask
= clip_dist_mask
| cull_dist_mask
;
2782 bool misc_vec_ena
= outinfo
->writes_pointsize
||
2783 outinfo
->writes_layer
||
2784 outinfo
->writes_viewport_index
;
2786 radeon_set_context_reg(cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
2787 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo
->param_exports
) - 1));
2789 radeon_set_context_reg(cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
2790 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
2791 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
2792 V_02870C_SPI_SHADER_4COMP
:
2793 V_02870C_SPI_SHADER_NONE
) |
2794 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
2795 V_02870C_SPI_SHADER_4COMP
:
2796 V_02870C_SPI_SHADER_NONE
) |
2797 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
2798 V_02870C_SPI_SHADER_4COMP
:
2799 V_02870C_SPI_SHADER_NONE
));
2801 radeon_set_context_reg(cs
, R_028818_PA_CL_VTE_CNTL
,
2802 S_028818_VTX_W0_FMT(1) |
2803 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2804 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2805 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2807 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
2808 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
2809 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
2810 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
2811 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2812 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
2813 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
2814 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
2815 cull_dist_mask
<< 8 |
2818 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= VI
)
2819 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
2820 outinfo
->writes_viewport_index
);
2824 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
2825 struct radv_pipeline
*pipeline
,
2826 struct radv_shader_variant
*shader
)
2828 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2830 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
2831 radeon_emit(cs
, va
>> 8);
2832 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
2833 radeon_emit(cs
, shader
->rsrc1
);
2834 radeon_emit(cs
, shader
->rsrc2
);
2838 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
2839 struct radv_pipeline
*pipeline
,
2840 struct radv_shader_variant
*shader
,
2841 const struct radv_tessellation_state
*tess
)
2843 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2844 uint32_t rsrc2
= shader
->rsrc2
;
2846 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
2847 radeon_emit(cs
, va
>> 8);
2848 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
2850 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
2851 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
2852 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
2853 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
2855 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
2856 radeon_emit(cs
, shader
->rsrc1
);
2857 radeon_emit(cs
, rsrc2
);
2861 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
2862 struct radv_pipeline
*pipeline
,
2863 struct radv_shader_variant
*shader
,
2864 const struct radv_tessellation_state
*tess
)
2866 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2868 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2869 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
2870 radeon_emit(cs
, va
>> 8);
2871 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
2873 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
2874 radeon_emit(cs
, shader
->rsrc1
);
2875 radeon_emit(cs
, shader
->rsrc2
|
2876 S_00B42C_LDS_SIZE(tess
->lds_size
));
2878 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
2879 radeon_emit(cs
, va
>> 8);
2880 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
2881 radeon_emit(cs
, shader
->rsrc1
);
2882 radeon_emit(cs
, shader
->rsrc2
);
2887 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*cs
,
2888 struct radv_pipeline
*pipeline
,
2889 const struct radv_tessellation_state
*tess
)
2891 struct radv_shader_variant
*vs
;
2893 /* Skip shaders merged into HS/GS */
2894 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
2898 if (vs
->info
.vs
.as_ls
)
2899 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
2900 else if (vs
->info
.vs
.as_es
)
2901 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
2903 radv_pipeline_generate_hw_vs(cs
, pipeline
, vs
);
2907 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*cs
,
2908 struct radv_pipeline
*pipeline
,
2909 const struct radv_tessellation_state
*tess
)
2911 if (!radv_pipeline_has_tess(pipeline
))
2914 struct radv_shader_variant
*tes
, *tcs
;
2916 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
2917 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2920 if (tes
->info
.tes
.as_es
)
2921 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
2923 radv_pipeline_generate_hw_vs(cs
, pipeline
, tes
);
2926 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
2928 radeon_set_context_reg(cs
, R_028B6C_VGT_TF_PARAM
,
2931 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
2932 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
2933 tess
->ls_hs_config
);
2935 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
2936 tess
->ls_hs_config
);
2940 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*cs
,
2941 struct radv_pipeline
*pipeline
,
2942 const struct radv_gs_state
*gs_state
)
2944 struct radv_shader_variant
*gs
;
2947 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2951 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
2953 radeon_set_context_reg_seq(cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
2954 radeon_emit(cs
, gsvs_itemsize
);
2955 radeon_emit(cs
, gsvs_itemsize
);
2956 radeon_emit(cs
, gsvs_itemsize
);
2958 radeon_set_context_reg(cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
2960 radeon_set_context_reg(cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
2962 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
2963 radeon_set_context_reg_seq(cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
2964 radeon_emit(cs
, gs_vert_itemsize
>> 2);
2969 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
2970 radeon_set_context_reg(cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
2971 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
2972 S_028B90_ENABLE(gs_num_invocations
> 0));
2974 radeon_set_context_reg(cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
2975 gs_state
->vgt_esgs_ring_itemsize
);
2977 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
2979 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2980 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
2981 radeon_emit(cs
, va
>> 8);
2982 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
2984 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
2985 radeon_emit(cs
, gs
->rsrc1
);
2986 radeon_emit(cs
, gs
->rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
2988 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
2989 radeon_set_context_reg(cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
2991 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
2992 radeon_emit(cs
, va
>> 8);
2993 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
2994 radeon_emit(cs
, gs
->rsrc1
);
2995 radeon_emit(cs
, gs
->rsrc2
);
2998 radv_pipeline_generate_hw_vs(cs
, pipeline
, pipeline
->gs_copy_shader
);
3001 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
)
3003 uint32_t ps_input_cntl
;
3004 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3005 ps_input_cntl
= S_028644_OFFSET(offset
);
3007 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3009 /* The input is a DEFAULT_VAL constant. */
3010 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3011 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3012 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3013 ps_input_cntl
= S_028644_OFFSET(0x20) |
3014 S_028644_DEFAULT_VAL(offset
);
3016 return ps_input_cntl
;
3020 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*cs
,
3021 struct radv_pipeline
*pipeline
)
3023 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3024 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3025 uint32_t ps_input_cntl
[32];
3027 unsigned ps_offset
= 0;
3029 if (ps
->info
.info
.ps
.prim_id_input
) {
3030 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
3031 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3032 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
3037 if (ps
->info
.info
.ps
.layer_input
||
3038 ps
->info
.info
.ps
.uses_input_attachments
||
3039 ps
->info
.info
.needs_multiview_view_index
) {
3040 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
3041 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
3042 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
3044 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true);
3048 if (ps
->info
.info
.ps
.has_pcoord
) {
3050 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3051 ps_input_cntl
[ps_offset
] = val
;
3055 if (ps
->info
.info
.ps
.num_input_clips_culls
) {
3058 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
3059 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3060 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
3064 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
3065 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
3066 ps
->info
.info
.ps
.num_input_clips_culls
> 4) {
3067 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
3072 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
3075 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
3078 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
3079 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
3080 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
3085 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
3087 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
);
3092 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
3093 for (unsigned i
= 0; i
< ps_offset
; i
++) {
3094 radeon_emit(cs
, ps_input_cntl
[i
]);
3100 radv_compute_db_shader_control(const struct radv_device
*device
,
3101 const struct radv_shader_variant
*ps
)
3104 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.info
.ps
.writes_memory
)
3105 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
3107 z_order
= V_02880C_LATE_Z
;
3109 bool disable_rbplus
= device
->physical_device
->has_rbplus
&&
3110 !device
->physical_device
->rbplus_allowed
;
3112 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_z
) |
3113 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_stencil
) |
3114 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
3115 S_02880C_MASK_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_sample_mask
) |
3116 S_02880C_Z_ORDER(z_order
) |
3117 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
3118 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.info
.ps
.writes_memory
) |
3119 S_02880C_EXEC_ON_NOOP(ps
->info
.info
.ps
.writes_memory
) |
3120 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
3124 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*cs
,
3125 struct radv_pipeline
*pipeline
)
3127 struct radv_shader_variant
*ps
;
3129 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
3131 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3132 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
3134 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
3135 radeon_emit(cs
, va
>> 8);
3136 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
3137 radeon_emit(cs
, ps
->rsrc1
);
3138 radeon_emit(cs
, ps
->rsrc2
);
3140 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
3141 radv_compute_db_shader_control(pipeline
->device
, ps
));
3143 radeon_set_context_reg(cs
, R_0286CC_SPI_PS_INPUT_ENA
,
3144 ps
->config
.spi_ps_input_ena
);
3146 radeon_set_context_reg(cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
3147 ps
->config
.spi_ps_input_addr
);
3149 radeon_set_context_reg(cs
, R_0286D8_SPI_PS_IN_CONTROL
,
3150 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
3152 radeon_set_context_reg(cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
3154 radeon_set_context_reg(cs
, R_028710_SPI_SHADER_Z_FORMAT
,
3155 ac_get_spi_shader_z_format(ps
->info
.info
.ps
.writes_z
,
3156 ps
->info
.info
.ps
.writes_stencil
,
3157 ps
->info
.info
.ps
.writes_sample_mask
));
3159 if (pipeline
->device
->dfsm_allowed
) {
3160 /* optimise this? */
3161 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3162 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3167 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*cs
,
3168 struct radv_pipeline
*pipeline
)
3170 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
3173 unsigned vtx_reuse_depth
= 30;
3174 if (radv_pipeline_has_tess(pipeline
) &&
3175 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
3176 vtx_reuse_depth
= 14;
3178 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
3179 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
3183 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
3185 uint32_t stages
= 0;
3186 if (radv_pipeline_has_tess(pipeline
)) {
3187 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3188 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3190 if (radv_pipeline_has_gs(pipeline
))
3191 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3193 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3195 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3197 } else if (radv_pipeline_has_gs(pipeline
))
3198 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3200 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3202 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
3203 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3209 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3211 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
3212 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
3214 if (!discard_rectangle_info
)
3219 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
3220 /* Interpret i as a bitmask, and then set the bit in the mask if
3221 * that combination of rectangles in which the pixel is contained
3222 * should pass the cliprect test. */
3223 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
3225 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
3229 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
3240 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
3241 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3242 const struct radv_graphics_pipeline_create_info
*extra
,
3243 const struct radv_blend_state
*blend
,
3244 const struct radv_tessellation_state
*tess
,
3245 const struct radv_gs_state
*gs
,
3246 unsigned prim
, unsigned gs_out
)
3248 pipeline
->cs
.buf
= malloc(4 * 256);
3249 pipeline
->cs
.max_dw
= 256;
3251 radv_pipeline_generate_depth_stencil_state(&pipeline
->cs
, pipeline
, pCreateInfo
, extra
);
3252 radv_pipeline_generate_blend_state(&pipeline
->cs
, pipeline
, blend
);
3253 radv_pipeline_generate_raster_state(&pipeline
->cs
, pCreateInfo
);
3254 radv_pipeline_generate_multisample_state(&pipeline
->cs
, pipeline
);
3255 radv_pipeline_generate_vgt_gs_mode(&pipeline
->cs
, pipeline
);
3256 radv_pipeline_generate_vertex_shader(&pipeline
->cs
, pipeline
, tess
);
3257 radv_pipeline_generate_tess_shaders(&pipeline
->cs
, pipeline
, tess
);
3258 radv_pipeline_generate_geometry_shader(&pipeline
->cs
, pipeline
, gs
);
3259 radv_pipeline_generate_fragment_shader(&pipeline
->cs
, pipeline
);
3260 radv_pipeline_generate_ps_inputs(&pipeline
->cs
, pipeline
);
3261 radv_pipeline_generate_vgt_vertex_reuse(&pipeline
->cs
, pipeline
);
3262 radv_pipeline_generate_binning_state(&pipeline
->cs
, pipeline
, pCreateInfo
);
3264 radeon_set_context_reg(&pipeline
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
3265 S_0286E8_WAVES(pipeline
->max_waves
) |
3266 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3268 radeon_set_context_reg(&pipeline
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
3270 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3271 radeon_set_uconfig_reg_idx(&pipeline
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
3273 radeon_set_config_reg(&pipeline
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
3275 radeon_set_context_reg(&pipeline
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
3277 radeon_set_context_reg(&pipeline
->cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
3279 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
3282 static struct radv_ia_multi_vgt_param_helpers
3283 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
3284 const struct radv_tessellation_state
*tess
,
3287 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
3288 const struct radv_device
*device
= pipeline
->device
;
3290 if (radv_pipeline_has_tess(pipeline
))
3291 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
3292 else if (radv_pipeline_has_gs(pipeline
))
3293 ia_multi_vgt_param
.primgroup_size
= 64;
3295 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
3297 ia_multi_vgt_param
.partial_es_wave
= false;
3298 if (pipeline
->device
->has_distributed_tess
) {
3299 if (radv_pipeline_has_gs(pipeline
)) {
3300 if (device
->physical_device
->rad_info
.chip_class
<= VI
)
3301 ia_multi_vgt_param
.partial_es_wave
= true;
3304 /* GS requirement. */
3305 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= VI
)
3306 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
3307 ia_multi_vgt_param
.partial_es_wave
= true;
3309 ia_multi_vgt_param
.wd_switch_on_eop
= false;
3310 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3311 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3312 * 4 shader engines. Set 1 to pass the assertion below.
3313 * The other cases are hardware requirements. */
3314 if (device
->physical_device
->rad_info
.max_se
< 4 ||
3315 prim
== V_008958_DI_PT_POLYGON
||
3316 prim
== V_008958_DI_PT_LINELOOP
||
3317 prim
== V_008958_DI_PT_TRIFAN
||
3318 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
3319 (pipeline
->graphics
.prim_restart_enable
&&
3320 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
3321 (prim
!= V_008958_DI_PT_POINTLIST
&&
3322 prim
!= V_008958_DI_PT_LINESTRIP
&&
3323 prim
!= V_008958_DI_PT_TRISTRIP
))))
3324 ia_multi_vgt_param
.wd_switch_on_eop
= true;
3327 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
3328 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
)
3329 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3330 if (radv_pipeline_has_gs(pipeline
) &&
3331 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.info
.uses_prim_id
)
3332 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3333 if (radv_pipeline_has_tess(pipeline
)) {
3334 /* SWITCH_ON_EOI must be set if PrimID is used. */
3335 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.uses_prim_id
||
3336 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.info
.uses_prim_id
)
3337 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3340 ia_multi_vgt_param
.partial_vs_wave
= false;
3341 if (radv_pipeline_has_tess(pipeline
)) {
3342 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3343 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
3344 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
3345 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
3346 radv_pipeline_has_gs(pipeline
))
3347 ia_multi_vgt_param
.partial_vs_wave
= true;
3348 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3349 if (device
->has_distributed_tess
) {
3350 if (radv_pipeline_has_gs(pipeline
)) {
3351 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
3352 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
3353 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
3354 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
3355 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
3356 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
)
3357 ia_multi_vgt_param
.partial_vs_wave
= true;
3359 ia_multi_vgt_param
.partial_vs_wave
= true;
3364 ia_multi_vgt_param
.base
=
3365 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
3366 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3367 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== VI
? 2 : 0) |
3368 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
3369 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
3371 return ia_multi_vgt_param
;
3376 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
3377 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3379 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
3380 pCreateInfo
->pVertexInputState
;
3381 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
3383 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
3384 const VkVertexInputAttributeDescription
*desc
=
3385 &vi_info
->pVertexAttributeDescriptions
[i
];
3386 unsigned loc
= desc
->location
;
3387 const struct vk_format_description
*format_desc
;
3389 uint32_t num_format
, data_format
;
3390 format_desc
= vk_format_description(desc
->format
);
3391 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
3393 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
3394 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
3396 velems
->rsrc_word3
[loc
] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc
->swizzle
[0])) |
3397 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc
->swizzle
[1])) |
3398 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc
->swizzle
[2])) |
3399 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc
->swizzle
[3])) |
3400 S_008F0C_NUM_FORMAT(num_format
) |
3401 S_008F0C_DATA_FORMAT(data_format
);
3402 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
3403 velems
->offset
[loc
] = desc
->offset
;
3404 velems
->binding
[loc
] = desc
->binding
;
3405 velems
->count
= MAX2(velems
->count
, loc
+ 1);
3408 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
3409 const VkVertexInputBindingDescription
*desc
=
3410 &vi_info
->pVertexBindingDescriptions
[i
];
3412 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
3417 radv_pipeline_init(struct radv_pipeline
*pipeline
,
3418 struct radv_device
*device
,
3419 struct radv_pipeline_cache
*cache
,
3420 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3421 const struct radv_graphics_pipeline_create_info
*extra
,
3422 const VkAllocationCallbacks
*alloc
)
3425 bool has_view_index
= false;
3427 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3428 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3429 if (subpass
->view_mask
)
3430 has_view_index
= true;
3432 alloc
= &device
->alloc
;
3434 pipeline
->device
= device
;
3435 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3436 assert(pipeline
->layout
);
3438 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
3440 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3441 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
3442 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
3443 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
3446 radv_create_shaders(pipeline
, device
, cache
,
3447 radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
),
3448 pStages
, pCreateInfo
->flags
);
3450 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
3451 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
3453 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
3455 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
3457 if (radv_pipeline_has_gs(pipeline
)) {
3458 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
3459 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3461 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
3463 if (extra
&& extra
->use_rectlist
) {
3464 prim
= V_008958_DI_PT_RECTLIST
;
3465 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3466 pipeline
->graphics
.can_use_guardband
= true;
3468 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
3469 /* prim vertex count will need TESS changes */
3470 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
3472 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
3474 /* Ensure that some export memory is always allocated, for two reasons:
3476 * 1) Correctness: The hardware ignores the EXEC mask if no export
3477 * memory is allocated, so KILL and alpha test do not work correctly
3479 * 2) Performance: Every shader needs at least a NULL export, even when
3480 * it writes no color/depth output. The NULL export instruction
3481 * stalls without this setting.
3483 * Don't add this to CB_SHADER_MASK.
3485 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3486 if (!blend
.spi_shader_col_format
) {
3487 if (!ps
->info
.info
.ps
.writes_z
&&
3488 !ps
->info
.info
.ps
.writes_stencil
&&
3489 !ps
->info
.info
.ps
.writes_sample_mask
)
3490 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
3493 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
3494 if (pipeline
->shaders
[i
]) {
3495 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
3499 struct radv_gs_state gs
= {0};
3500 if (radv_pipeline_has_gs(pipeline
)) {
3501 gs
= calculate_gs_info(pCreateInfo
, pipeline
);
3502 calculate_gs_ring_sizes(pipeline
, &gs
);
3505 struct radv_tessellation_state tess
= {0};
3506 if (radv_pipeline_has_tess(pipeline
)) {
3507 if (prim
== V_008958_DI_PT_PATCH
) {
3508 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
3509 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
3511 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
3514 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
3516 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
3518 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
3519 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
3521 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
3522 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
3523 if (loc
->sgpr_idx
!= -1) {
3524 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
3525 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
3526 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
)
3527 pipeline
->graphics
.vtx_emit_num
= 3;
3529 pipeline
->graphics
.vtx_emit_num
= 2;
3532 result
= radv_pipeline_scratch_init(device
, pipeline
);
3533 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, &gs
, prim
, gs_out
);
3539 radv_graphics_pipeline_create(
3541 VkPipelineCache _cache
,
3542 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3543 const struct radv_graphics_pipeline_create_info
*extra
,
3544 const VkAllocationCallbacks
*pAllocator
,
3545 VkPipeline
*pPipeline
)
3547 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3548 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3549 struct radv_pipeline
*pipeline
;
3552 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3553 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3554 if (pipeline
== NULL
)
3555 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3557 result
= radv_pipeline_init(pipeline
, device
, cache
,
3558 pCreateInfo
, extra
, pAllocator
);
3559 if (result
!= VK_SUCCESS
) {
3560 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3564 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3569 VkResult
radv_CreateGraphicsPipelines(
3571 VkPipelineCache pipelineCache
,
3573 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
3574 const VkAllocationCallbacks
* pAllocator
,
3575 VkPipeline
* pPipelines
)
3577 VkResult result
= VK_SUCCESS
;
3580 for (; i
< count
; i
++) {
3582 r
= radv_graphics_pipeline_create(_device
,
3585 NULL
, pAllocator
, &pPipelines
[i
]);
3586 if (r
!= VK_SUCCESS
) {
3588 pPipelines
[i
] = VK_NULL_HANDLE
;
3597 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
3599 struct radv_shader_variant
*compute_shader
;
3600 struct radv_device
*device
= pipeline
->device
;
3601 unsigned compute_resource_limits
;
3602 unsigned waves_per_threadgroup
;
3605 pipeline
->cs
.buf
= malloc(20 * 4);
3606 pipeline
->cs
.max_dw
= 20;
3608 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3609 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
3611 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
3612 radeon_emit(&pipeline
->cs
, va
>> 8);
3613 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
3615 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
3616 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc1
);
3617 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc2
);
3619 radeon_set_sh_reg(&pipeline
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3620 S_00B860_WAVES(pipeline
->max_waves
) |
3621 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3623 /* Calculate best compute resource limits. */
3624 waves_per_threadgroup
=
3625 DIV_ROUND_UP(compute_shader
->info
.cs
.block_size
[0] *
3626 compute_shader
->info
.cs
.block_size
[1] *
3627 compute_shader
->info
.cs
.block_size
[2], 64);
3628 compute_resource_limits
=
3629 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
3631 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3632 unsigned num_cu_per_se
=
3633 device
->physical_device
->rad_info
.num_good_compute_units
/
3634 device
->physical_device
->rad_info
.max_se
;
3636 /* Force even distribution on all SIMDs in CU if the workgroup
3637 * size is 64. This has shown some good improvements if # of
3638 * CUs per SE is not a multiple of 4.
3640 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
3641 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
3644 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
3645 compute_resource_limits
);
3647 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3648 radeon_emit(&pipeline
->cs
,
3649 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
3650 radeon_emit(&pipeline
->cs
,
3651 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
3652 radeon_emit(&pipeline
->cs
,
3653 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
3655 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
3658 static VkResult
radv_compute_pipeline_create(
3660 VkPipelineCache _cache
,
3661 const VkComputePipelineCreateInfo
* pCreateInfo
,
3662 const VkAllocationCallbacks
* pAllocator
,
3663 VkPipeline
* pPipeline
)
3665 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3666 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3667 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3668 struct radv_pipeline
*pipeline
;
3671 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3672 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3673 if (pipeline
== NULL
)
3674 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3676 pipeline
->device
= device
;
3677 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3678 assert(pipeline
->layout
);
3680 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
3681 radv_create_shaders(pipeline
, device
, cache
, (struct radv_pipeline_key
) {0}, pStages
, pCreateInfo
->flags
);
3683 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
3684 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
3685 result
= radv_pipeline_scratch_init(device
, pipeline
);
3686 if (result
!= VK_SUCCESS
) {
3687 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3691 radv_compute_generate_pm4(pipeline
);
3693 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3698 VkResult
radv_CreateComputePipelines(
3700 VkPipelineCache pipelineCache
,
3702 const VkComputePipelineCreateInfo
* pCreateInfos
,
3703 const VkAllocationCallbacks
* pAllocator
,
3704 VkPipeline
* pPipelines
)
3706 VkResult result
= VK_SUCCESS
;
3709 for (; i
< count
; i
++) {
3711 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
3713 pAllocator
, &pPipelines
[i
]);
3714 if (r
!= VK_SUCCESS
) {
3716 pPipelines
[i
] = VK_NULL_HANDLE
;