2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
54 struct radv_blend_state
{
55 uint32_t blend_enable_4bit
;
56 uint32_t need_src_alpha
;
58 uint32_t cb_color_control
;
59 uint32_t cb_target_mask
;
60 uint32_t cb_target_enabled_4bit
;
61 uint32_t sx_mrt_blend_opt
[8];
62 uint32_t cb_blend_control
[8];
64 uint32_t spi_shader_col_format
;
65 uint32_t cb_shader_mask
;
66 uint32_t db_alpha_to_mask
;
68 uint32_t commutative_4bit
;
70 bool single_cb_enable
;
71 bool mrt0_is_dual_src
;
74 struct radv_dsa_order_invariance
{
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
87 struct radv_tessellation_state
{
88 uint32_t ls_hs_config
;
94 static const VkPipelineMultisampleStateCreateInfo
*
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
97 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
98 return pCreateInfo
->pMultisampleState
;
102 static const VkPipelineTessellationStateCreateInfo
*
103 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
105 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
106 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
107 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
108 return pCreateInfo
->pTessellationState
;
114 static const VkPipelineDepthStencilStateCreateInfo
*
115 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
117 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
118 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
120 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
121 subpass
->depth_stencil_attachment
)
122 return pCreateInfo
->pDepthStencilState
;
126 static const VkPipelineColorBlendStateCreateInfo
*
127 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
129 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
130 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
132 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
133 subpass
->has_color_att
)
134 return pCreateInfo
->pColorBlendState
;
138 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
140 struct radv_shader_variant
*variant
= NULL
;
141 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
142 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
143 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
144 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
145 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
146 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
149 return variant
->info
.is_ngg
;
152 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
154 assert(radv_pipeline_has_ngg(pipeline
));
156 struct radv_shader_variant
*variant
= NULL
;
157 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
158 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
159 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
160 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
161 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
162 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
165 return variant
->info
.is_ngg_passthrough
;
168 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
170 if (!radv_pipeline_has_gs(pipeline
))
173 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
174 * On GFX10, it might be required in rare cases if it's not possible to
177 if (radv_pipeline_has_ngg(pipeline
))
180 assert(pipeline
->gs_copy_shader
);
185 radv_pipeline_destroy(struct radv_device
*device
,
186 struct radv_pipeline
*pipeline
,
187 const VkAllocationCallbacks
* allocator
)
189 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
190 if (pipeline
->shaders
[i
])
191 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
193 if (pipeline
->gs_copy_shader
)
194 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
197 free(pipeline
->cs
.buf
);
198 vk_free2(&device
->alloc
, allocator
, pipeline
);
201 void radv_DestroyPipeline(
203 VkPipeline _pipeline
,
204 const VkAllocationCallbacks
* pAllocator
)
206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
207 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
215 static uint32_t get_hash_flags(struct radv_device
*device
)
217 uint32_t hash_flags
= 0;
219 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
220 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
221 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
222 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
223 if (device
->physical_device
->cs_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
225 if (device
->physical_device
->ps_wave_size
== 32)
226 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
227 if (device
->physical_device
->ge_wave_size
== 32)
228 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
229 if (device
->physical_device
->use_aco
)
230 hash_flags
|= RADV_HASH_SHADER_ACO
;
235 radv_pipeline_scratch_init(struct radv_device
*device
,
236 struct radv_pipeline
*pipeline
)
238 unsigned scratch_bytes_per_wave
= 0;
239 unsigned max_waves
= 0;
240 unsigned min_waves
= 1;
242 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
243 if (pipeline
->shaders
[i
] &&
244 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
245 unsigned max_stage_waves
= device
->scratch_waves
;
247 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
248 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
250 max_stage_waves
= MIN2(max_stage_waves
,
251 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
252 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
253 max_waves
= MAX2(max_waves
, max_stage_waves
);
257 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
258 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
259 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
260 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
261 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
264 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
265 pipeline
->max_waves
= max_waves
;
269 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
272 case VK_LOGIC_OP_CLEAR
:
273 return V_028808_ROP3_CLEAR
;
274 case VK_LOGIC_OP_AND
:
275 return V_028808_ROP3_AND
;
276 case VK_LOGIC_OP_AND_REVERSE
:
277 return V_028808_ROP3_AND_REVERSE
;
278 case VK_LOGIC_OP_COPY
:
279 return V_028808_ROP3_COPY
;
280 case VK_LOGIC_OP_AND_INVERTED
:
281 return V_028808_ROP3_AND_INVERTED
;
282 case VK_LOGIC_OP_NO_OP
:
283 return V_028808_ROP3_NO_OP
;
284 case VK_LOGIC_OP_XOR
:
285 return V_028808_ROP3_XOR
;
287 return V_028808_ROP3_OR
;
288 case VK_LOGIC_OP_NOR
:
289 return V_028808_ROP3_NOR
;
290 case VK_LOGIC_OP_EQUIVALENT
:
291 return V_028808_ROP3_EQUIVALENT
;
292 case VK_LOGIC_OP_INVERT
:
293 return V_028808_ROP3_INVERT
;
294 case VK_LOGIC_OP_OR_REVERSE
:
295 return V_028808_ROP3_OR_REVERSE
;
296 case VK_LOGIC_OP_COPY_INVERTED
:
297 return V_028808_ROP3_COPY_INVERTED
;
298 case VK_LOGIC_OP_OR_INVERTED
:
299 return V_028808_ROP3_OR_INVERTED
;
300 case VK_LOGIC_OP_NAND
:
301 return V_028808_ROP3_NAND
;
302 case VK_LOGIC_OP_SET
:
303 return V_028808_ROP3_SET
;
305 unreachable("Unhandled logic op");
310 static uint32_t si_translate_blend_function(VkBlendOp op
)
313 case VK_BLEND_OP_ADD
:
314 return V_028780_COMB_DST_PLUS_SRC
;
315 case VK_BLEND_OP_SUBTRACT
:
316 return V_028780_COMB_SRC_MINUS_DST
;
317 case VK_BLEND_OP_REVERSE_SUBTRACT
:
318 return V_028780_COMB_DST_MINUS_SRC
;
319 case VK_BLEND_OP_MIN
:
320 return V_028780_COMB_MIN_DST_SRC
;
321 case VK_BLEND_OP_MAX
:
322 return V_028780_COMB_MAX_DST_SRC
;
328 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
331 case VK_BLEND_FACTOR_ZERO
:
332 return V_028780_BLEND_ZERO
;
333 case VK_BLEND_FACTOR_ONE
:
334 return V_028780_BLEND_ONE
;
335 case VK_BLEND_FACTOR_SRC_COLOR
:
336 return V_028780_BLEND_SRC_COLOR
;
337 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
338 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
339 case VK_BLEND_FACTOR_DST_COLOR
:
340 return V_028780_BLEND_DST_COLOR
;
341 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
342 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
343 case VK_BLEND_FACTOR_SRC_ALPHA
:
344 return V_028780_BLEND_SRC_ALPHA
;
345 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
346 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
347 case VK_BLEND_FACTOR_DST_ALPHA
:
348 return V_028780_BLEND_DST_ALPHA
;
349 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
350 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
351 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
352 return V_028780_BLEND_CONSTANT_COLOR
;
353 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
354 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
355 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
356 return V_028780_BLEND_CONSTANT_ALPHA
;
357 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
358 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
359 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
360 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
361 case VK_BLEND_FACTOR_SRC1_COLOR
:
362 return V_028780_BLEND_SRC1_COLOR
;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
364 return V_028780_BLEND_INV_SRC1_COLOR
;
365 case VK_BLEND_FACTOR_SRC1_ALPHA
:
366 return V_028780_BLEND_SRC1_ALPHA
;
367 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
368 return V_028780_BLEND_INV_SRC1_ALPHA
;
374 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
377 case VK_BLEND_OP_ADD
:
378 return V_028760_OPT_COMB_ADD
;
379 case VK_BLEND_OP_SUBTRACT
:
380 return V_028760_OPT_COMB_SUBTRACT
;
381 case VK_BLEND_OP_REVERSE_SUBTRACT
:
382 return V_028760_OPT_COMB_REVSUBTRACT
;
383 case VK_BLEND_OP_MIN
:
384 return V_028760_OPT_COMB_MIN
;
385 case VK_BLEND_OP_MAX
:
386 return V_028760_OPT_COMB_MAX
;
388 return V_028760_OPT_COMB_BLEND_DISABLED
;
392 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
395 case VK_BLEND_FACTOR_ZERO
:
396 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
397 case VK_BLEND_FACTOR_ONE
:
398 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
399 case VK_BLEND_FACTOR_SRC_COLOR
:
400 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
401 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
402 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
403 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
404 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
405 case VK_BLEND_FACTOR_SRC_ALPHA
:
406 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
407 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
408 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
409 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
410 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
411 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
413 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
418 * Get rid of DST in the blend factors by commuting the operands:
419 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
421 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
422 unsigned *dst_factor
, unsigned expected_dst
,
423 unsigned replacement_src
)
425 if (*src_factor
== expected_dst
&&
426 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
427 *src_factor
= VK_BLEND_FACTOR_ZERO
;
428 *dst_factor
= replacement_src
;
430 /* Commuting the operands requires reversing subtractions. */
431 if (*func
== VK_BLEND_OP_SUBTRACT
)
432 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
433 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
434 *func
= VK_BLEND_OP_SUBTRACT
;
438 static bool si_blend_factor_uses_dst(unsigned factor
)
440 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
441 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
442 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
443 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
444 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
447 static bool is_dual_src(VkBlendFactor factor
)
450 case VK_BLEND_FACTOR_SRC1_COLOR
:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
452 case VK_BLEND_FACTOR_SRC1_ALPHA
:
453 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
460 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
462 bool blend_need_alpha
)
464 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
465 unsigned format
, ntype
, swap
;
467 /* Alpha is needed for alpha-to-coverage.
468 * Blending may be with or without alpha.
470 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
471 unsigned alpha
= 0; /* exports alpha, but may not support blending */
472 unsigned blend
= 0; /* supports blending, but may not export alpha */
473 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
475 format
= radv_translate_colorformat(vk_format
);
476 ntype
= radv_translate_color_numformat(vk_format
, desc
,
477 vk_format_get_first_non_void_channel(vk_format
));
478 swap
= radv_translate_colorswap(vk_format
, false);
480 /* Choose the SPI color formats. These are required values for Stoney/RB+.
481 * Other chips have multiple choices, though they are not necessarily better.
484 case V_028C70_COLOR_5_6_5
:
485 case V_028C70_COLOR_1_5_5_5
:
486 case V_028C70_COLOR_5_5_5_1
:
487 case V_028C70_COLOR_4_4_4_4
:
488 case V_028C70_COLOR_10_11_11
:
489 case V_028C70_COLOR_11_11_10
:
490 case V_028C70_COLOR_8
:
491 case V_028C70_COLOR_8_8
:
492 case V_028C70_COLOR_8_8_8_8
:
493 case V_028C70_COLOR_10_10_10_2
:
494 case V_028C70_COLOR_2_10_10_10
:
495 if (ntype
== V_028C70_NUMBER_UINT
)
496 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
497 else if (ntype
== V_028C70_NUMBER_SINT
)
498 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
500 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
503 case V_028C70_COLOR_16
:
504 case V_028C70_COLOR_16_16
:
505 case V_028C70_COLOR_16_16_16_16
:
506 if (ntype
== V_028C70_NUMBER_UNORM
||
507 ntype
== V_028C70_NUMBER_SNORM
) {
508 /* UNORM16 and SNORM16 don't support blending */
509 if (ntype
== V_028C70_NUMBER_UNORM
)
510 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
512 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
514 /* Use 32 bits per channel for blending. */
515 if (format
== V_028C70_COLOR_16
) {
516 if (swap
== V_028C70_SWAP_STD
) { /* R */
517 blend
= V_028714_SPI_SHADER_32_R
;
518 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
519 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
520 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
523 } else if (format
== V_028C70_COLOR_16_16
) {
524 if (swap
== V_028C70_SWAP_STD
) { /* RG */
525 blend
= V_028714_SPI_SHADER_32_GR
;
526 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
527 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
528 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
531 } else /* 16_16_16_16 */
532 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
533 } else if (ntype
== V_028C70_NUMBER_UINT
)
534 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
535 else if (ntype
== V_028C70_NUMBER_SINT
)
536 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
537 else if (ntype
== V_028C70_NUMBER_FLOAT
)
538 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
543 case V_028C70_COLOR_32
:
544 if (swap
== V_028C70_SWAP_STD
) { /* R */
545 blend
= normal
= V_028714_SPI_SHADER_32_R
;
546 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
547 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
548 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
553 case V_028C70_COLOR_32_32
:
554 if (swap
== V_028C70_SWAP_STD
) { /* RG */
555 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
556 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
557 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
558 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
563 case V_028C70_COLOR_32_32_32_32
:
564 case V_028C70_COLOR_8_24
:
565 case V_028C70_COLOR_24_8
:
566 case V_028C70_COLOR_X24_8_32_FLOAT
:
567 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
571 unreachable("unhandled blend format");
574 if (blend_enable
&& blend_need_alpha
)
576 else if(blend_need_alpha
)
578 else if(blend_enable
)
585 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
586 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
587 struct radv_blend_state
*blend
)
589 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
590 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
591 unsigned col_format
= 0;
592 unsigned num_targets
;
594 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
597 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
598 cf
= V_028714_SPI_SHADER_ZERO
;
600 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
602 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
604 cf
= si_choose_spi_color_format(attachment
->format
,
606 blend
->need_src_alpha
& (1 << i
));
609 col_format
|= cf
<< (4 * i
);
612 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
613 /* When a subpass doesn't have any color attachments, write the
614 * alpha channel of MRT0 when alpha coverage is enabled because
615 * the depth attachment needs it.
617 col_format
|= V_028714_SPI_SHADER_32_AR
;
620 /* If the i-th target format is set, all previous target formats must
621 * be non-zero to avoid hangs.
623 num_targets
= (util_last_bit(col_format
) + 3) / 4;
624 for (unsigned i
= 0; i
< num_targets
; i
++) {
625 if (!(col_format
& (0xf << (i
* 4)))) {
626 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
630 /* The output for dual source blending should have the same format as
633 if (blend
->mrt0_is_dual_src
)
634 col_format
|= (col_format
& 0xf) << 4;
636 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
637 blend
->spi_shader_col_format
= col_format
;
641 format_is_int8(VkFormat format
)
643 const struct vk_format_description
*desc
= vk_format_description(format
);
644 int channel
= vk_format_get_first_non_void_channel(format
);
646 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
647 desc
->channel
[channel
].size
== 8;
651 format_is_int10(VkFormat format
)
653 const struct vk_format_description
*desc
= vk_format_description(format
);
655 if (desc
->nr_channels
!= 4)
657 for (unsigned i
= 0; i
< 4; i
++) {
658 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
665 * Ordered so that for each i,
666 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
668 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
669 VK_FORMAT_R32_SFLOAT
,
670 VK_FORMAT_R32G32_SFLOAT
,
671 VK_FORMAT_R8G8B8A8_UNORM
,
672 VK_FORMAT_R16G16B16A16_UNORM
,
673 VK_FORMAT_R16G16B16A16_SNORM
,
674 VK_FORMAT_R16G16B16A16_UINT
,
675 VK_FORMAT_R16G16B16A16_SINT
,
676 VK_FORMAT_R32G32B32A32_SFLOAT
,
677 VK_FORMAT_R8G8B8A8_UINT
,
678 VK_FORMAT_R8G8B8A8_SINT
,
679 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
680 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
683 unsigned radv_format_meta_fs_key(VkFormat format
)
685 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
687 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
688 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
689 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
691 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
692 bool is_int8
= format_is_int8(format
);
693 bool is_int10
= format_is_int10(format
);
695 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
699 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
700 unsigned *is_int8
, unsigned *is_int10
)
702 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
703 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
707 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
708 struct radv_render_pass_attachment
*attachment
;
710 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
713 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
715 if (format_is_int8(attachment
->format
))
717 if (format_is_int10(attachment
->format
))
723 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
724 VkBlendOp op
, VkBlendFactor src
,
725 VkBlendFactor dst
, unsigned chanmask
)
727 /* Src factor is allowed when it does not depend on Dst. */
728 static const uint32_t src_allowed
=
729 (1u << VK_BLEND_FACTOR_ONE
) |
730 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
731 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
732 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
733 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
734 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
735 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
736 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
737 (1u << VK_BLEND_FACTOR_ZERO
) |
738 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
739 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
740 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
741 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
742 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
743 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
745 if (dst
== VK_BLEND_FACTOR_ONE
&&
746 (src_allowed
& (1u << src
))) {
747 /* Addition is commutative, but floating point addition isn't
748 * associative: subtle changes can be introduced via different
749 * rounding. Be conservative, only enable for min and max.
751 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
752 blend
->commutative_4bit
|= chanmask
;
756 static struct radv_blend_state
757 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
758 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
759 const struct radv_graphics_pipeline_create_info
*extra
)
761 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
762 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
763 struct radv_blend_state blend
= {0};
764 unsigned mode
= V_028808_CB_NORMAL
;
767 if (extra
&& extra
->custom_blend_mode
) {
768 blend
.single_cb_enable
= true;
769 mode
= extra
->custom_blend_mode
;
772 blend
.cb_color_control
= 0;
774 if (vkblend
->logicOpEnable
)
775 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
777 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
780 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
781 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
782 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
783 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
784 S_028B70_OFFSET_ROUND(1);
786 if (vkms
&& vkms
->alphaToCoverageEnable
) {
787 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
788 blend
.need_src_alpha
|= 0x1;
791 blend
.cb_target_mask
= 0;
793 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
794 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
795 unsigned blend_cntl
= 0;
796 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
797 VkBlendOp eqRGB
= att
->colorBlendOp
;
798 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
799 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
800 VkBlendOp eqA
= att
->alphaBlendOp
;
801 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
802 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
804 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
806 if (!att
->colorWriteMask
)
809 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
810 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
811 if (!att
->blendEnable
) {
812 blend
.cb_blend_control
[i
] = blend_cntl
;
816 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
818 blend
.mrt0_is_dual_src
= true;
820 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
821 srcRGB
= VK_BLEND_FACTOR_ONE
;
822 dstRGB
= VK_BLEND_FACTOR_ONE
;
824 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
825 srcA
= VK_BLEND_FACTOR_ONE
;
826 dstA
= VK_BLEND_FACTOR_ONE
;
829 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
831 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
834 /* Blending optimizations for RB+.
835 * These transformations don't change the behavior.
837 * First, get rid of DST in the blend factors:
838 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
840 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
841 VK_BLEND_FACTOR_DST_COLOR
,
842 VK_BLEND_FACTOR_SRC_COLOR
);
844 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
845 VK_BLEND_FACTOR_DST_COLOR
,
846 VK_BLEND_FACTOR_SRC_COLOR
);
848 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
849 VK_BLEND_FACTOR_DST_ALPHA
,
850 VK_BLEND_FACTOR_SRC_ALPHA
);
852 /* Look up the ideal settings from tables. */
853 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
854 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
855 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
856 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
858 /* Handle interdependencies. */
859 if (si_blend_factor_uses_dst(srcRGB
))
860 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
861 if (si_blend_factor_uses_dst(srcA
))
862 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
864 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
865 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
866 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
867 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
868 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
870 /* Set the final value. */
871 blend
.sx_mrt_blend_opt
[i
] =
872 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
873 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
874 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
875 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
876 S_028760_ALPHA_DST_OPT(dstA_opt
) |
877 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
878 blend_cntl
|= S_028780_ENABLE(1);
880 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
881 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
882 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
883 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
884 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
885 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
886 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
887 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
889 blend
.cb_blend_control
[i
] = blend_cntl
;
891 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
893 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
894 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
895 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
896 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
897 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
898 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
899 blend
.need_src_alpha
|= 1 << i
;
901 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
902 blend
.cb_blend_control
[i
] = 0;
903 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
907 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
908 /* Disable RB+ blend optimizations for dual source blending. */
909 if (blend
.mrt0_is_dual_src
) {
910 for (i
= 0; i
< 8; i
++) {
911 blend
.sx_mrt_blend_opt
[i
] =
912 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
913 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
917 /* RB+ doesn't work with dual source blending, logic op and
920 if (blend
.mrt0_is_dual_src
||
921 (vkblend
&& vkblend
->logicOpEnable
) ||
922 mode
== V_028808_CB_RESOLVE
)
923 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
926 if (blend
.cb_target_mask
)
927 blend
.cb_color_control
|= S_028808_MODE(mode
);
929 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
931 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
935 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
938 case VK_STENCIL_OP_KEEP
:
939 return V_02842C_STENCIL_KEEP
;
940 case VK_STENCIL_OP_ZERO
:
941 return V_02842C_STENCIL_ZERO
;
942 case VK_STENCIL_OP_REPLACE
:
943 return V_02842C_STENCIL_REPLACE_TEST
;
944 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
945 return V_02842C_STENCIL_ADD_CLAMP
;
946 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
947 return V_02842C_STENCIL_SUB_CLAMP
;
948 case VK_STENCIL_OP_INVERT
:
949 return V_02842C_STENCIL_INVERT
;
950 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
951 return V_02842C_STENCIL_ADD_WRAP
;
952 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
953 return V_02842C_STENCIL_SUB_WRAP
;
959 static uint32_t si_translate_fill(VkPolygonMode func
)
962 case VK_POLYGON_MODE_FILL
:
963 return V_028814_X_DRAW_TRIANGLES
;
964 case VK_POLYGON_MODE_LINE
:
965 return V_028814_X_DRAW_LINES
;
966 case VK_POLYGON_MODE_POINT
:
967 return V_028814_X_DRAW_POINTS
;
970 return V_028814_X_DRAW_POINTS
;
974 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
976 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
977 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
978 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
979 uint32_t ps_iter_samples
= 1;
980 uint32_t num_samples
;
982 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
984 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
985 * subpass uses color attachments, totalSamples is the number of
986 * samples of the color attachments. Otherwise, totalSamples is the
987 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
988 * specified at pipeline creation time."
990 if (subpass
->has_color_att
) {
991 num_samples
= subpass
->color_sample_count
;
993 num_samples
= vkms
->rasterizationSamples
;
996 if (vkms
->sampleShadingEnable
) {
997 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
998 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
1000 return ps_iter_samples
;
1004 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1006 return pCreateInfo
->depthTestEnable
&&
1007 pCreateInfo
->depthWriteEnable
&&
1008 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
1012 radv_writes_stencil(const VkStencilOpState
*state
)
1014 return state
->writeMask
&&
1015 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
1016 state
->passOp
!= VK_STENCIL_OP_KEEP
||
1017 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
1021 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1023 return pCreateInfo
->stencilTestEnable
&&
1024 (radv_writes_stencil(&pCreateInfo
->front
) ||
1025 radv_writes_stencil(&pCreateInfo
->back
));
1029 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1031 return radv_is_depth_write_enabled(pCreateInfo
) ||
1032 radv_is_stencil_write_enabled(pCreateInfo
);
1036 radv_order_invariant_stencil_op(VkStencilOp op
)
1038 /* REPLACE is normally order invariant, except when the stencil
1039 * reference value is written by the fragment shader. Tracking this
1040 * interaction does not seem worth the effort, so be conservative.
1042 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
1043 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
1044 op
!= VK_STENCIL_OP_REPLACE
;
1048 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
1050 /* Compute whether, assuming Z writes are disabled, this stencil state
1051 * is order invariant in the sense that the set of passing fragments as
1052 * well as the final stencil buffer result does not depend on the order
1055 return !state
->writeMask
||
1056 /* The following assumes that Z writes are disabled. */
1057 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
1058 radv_order_invariant_stencil_op(state
->passOp
) &&
1059 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
1060 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
1061 radv_order_invariant_stencil_op(state
->failOp
));
1065 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
1066 struct radv_blend_state
*blend
,
1067 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1069 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1070 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1071 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
1072 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
1073 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1075 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1078 /* Be conservative if a logic operation is enabled with color buffers. */
1079 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
1082 /* Default depth/stencil invariance when no attachment is bound. */
1083 struct radv_dsa_order_invariance dsa_order_invariant
= {
1084 .zs
= true, .pass_set
= true
1088 struct radv_render_pass_attachment
*attachment
=
1089 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1090 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1091 struct radv_dsa_order_invariance order_invariance
[2];
1092 struct radv_shader_variant
*ps
=
1093 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1095 /* Compute depth/stencil order invariance in order to know if
1096 * it's safe to enable out-of-order.
1098 bool zfunc_is_ordered
=
1099 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1100 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1101 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1102 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1103 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1105 bool nozwrite_and_order_invariant_stencil
=
1106 !radv_is_ds_write_enabled(vkds
) ||
1107 (!radv_is_depth_write_enabled(vkds
) &&
1108 radv_order_invariant_stencil_state(&vkds
->front
) &&
1109 radv_order_invariant_stencil_state(&vkds
->back
));
1111 order_invariance
[1].zs
=
1112 nozwrite_and_order_invariant_stencil
||
1113 (!radv_is_stencil_write_enabled(vkds
) &&
1115 order_invariance
[0].zs
=
1116 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1118 order_invariance
[1].pass_set
=
1119 nozwrite_and_order_invariant_stencil
||
1120 (!radv_is_stencil_write_enabled(vkds
) &&
1121 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1122 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1123 order_invariance
[0].pass_set
=
1124 !radv_is_depth_write_enabled(vkds
) ||
1125 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1126 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1128 dsa_order_invariant
= order_invariance
[has_stencil
];
1129 if (!dsa_order_invariant
.zs
)
1132 /* The set of PS invocations is always order invariant,
1133 * except when early Z/S tests are requested.
1136 ps
->info
.ps
.writes_memory
&&
1137 ps
->info
.ps
.early_fragment_test
&&
1138 !dsa_order_invariant
.pass_set
)
1141 /* Determine if out-of-order rasterization should be disabled
1142 * when occlusion queries are used.
1144 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1145 !dsa_order_invariant
.pass_set
;
1148 /* No color buffers are enabled for writing. */
1152 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1155 /* Only commutative blending. */
1156 if (blendmask
& ~blend
->commutative_4bit
)
1159 if (!dsa_order_invariant
.pass_set
)
1163 if (colormask
& ~blendmask
)
1170 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1171 struct radv_blend_state
*blend
,
1172 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1174 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1175 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1176 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1177 bool out_of_order_rast
= false;
1178 int ps_iter_samples
= 1;
1179 uint32_t mask
= 0xffff;
1182 ms
->num_samples
= vkms
->rasterizationSamples
;
1184 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1186 * "Sample shading is enabled for a graphics pipeline:
1188 * - If the interface of the fragment shader entry point of the
1189 * graphics pipeline includes an input variable decorated
1190 * with SampleId or SamplePosition. In this case
1191 * minSampleShadingFactor takes the value 1.0.
1192 * - Else if the sampleShadingEnable member of the
1193 * VkPipelineMultisampleStateCreateInfo structure specified
1194 * when creating the graphics pipeline is set to VK_TRUE. In
1195 * this case minSampleShadingFactor takes the value of
1196 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1198 * Otherwise, sample shading is considered disabled."
1200 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1201 ps_iter_samples
= ms
->num_samples
;
1203 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1206 ms
->num_samples
= 1;
1209 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1210 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1211 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1212 /* Out-of-order rasterization is explicitly enabled by the
1215 out_of_order_rast
= true;
1217 /* Determine if the driver can enable out-of-order
1218 * rasterization internally.
1221 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1224 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1225 ms
->pa_sc_aa_config
= 0;
1226 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1227 S_028804_INCOHERENT_EQAA_READS(1) |
1228 S_028804_INTERPOLATE_COMP_Z(1) |
1229 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1230 ms
->pa_sc_mode_cntl_1
=
1231 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1232 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1233 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1234 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1236 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1237 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1238 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1239 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1240 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1241 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1242 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1243 S_028A48_VPORT_SCISSOR_ENABLE(1);
1245 if (ms
->num_samples
> 1) {
1246 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1247 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1248 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1249 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1250 unsigned log_z_samples
= util_logbase2(z_samples
);
1251 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1252 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1253 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1254 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1255 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1256 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1257 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1258 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1259 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1260 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1261 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1262 if (ps_iter_samples
> 1)
1263 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1266 if (vkms
&& vkms
->pSampleMask
) {
1267 mask
= vkms
->pSampleMask
[0] & 0xffff;
1270 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1271 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1275 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1278 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1279 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1280 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1281 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1282 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1284 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1285 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1286 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1287 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1288 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1289 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1292 unreachable("unhandled primitive type");
1297 si_translate_prim(enum VkPrimitiveTopology topology
)
1300 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1301 return V_008958_DI_PT_POINTLIST
;
1302 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1303 return V_008958_DI_PT_LINELIST
;
1304 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1305 return V_008958_DI_PT_LINESTRIP
;
1306 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1307 return V_008958_DI_PT_TRILIST
;
1308 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1309 return V_008958_DI_PT_TRISTRIP
;
1310 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1311 return V_008958_DI_PT_TRIFAN
;
1312 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1313 return V_008958_DI_PT_LINELIST_ADJ
;
1314 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1315 return V_008958_DI_PT_LINESTRIP_ADJ
;
1316 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1317 return V_008958_DI_PT_TRILIST_ADJ
;
1318 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1319 return V_008958_DI_PT_TRISTRIP_ADJ
;
1320 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1321 return V_008958_DI_PT_PATCH
;
1329 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1332 case 0: /* GL_POINTS */
1333 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1334 case 1: /* GL_LINES */
1335 case 3: /* GL_LINE_STRIP */
1336 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1337 case 0x8E7A: /* GL_ISOLINES */
1338 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1340 case 4: /* GL_TRIANGLES */
1341 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1342 case 5: /* GL_TRIANGLE_STRIP */
1343 case 7: /* GL_QUADS */
1344 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1352 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1355 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1356 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1357 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1358 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1359 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1360 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1361 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1362 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1363 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1364 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1365 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1366 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1367 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1368 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1375 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1378 case VK_DYNAMIC_STATE_VIEWPORT
:
1379 return RADV_DYNAMIC_VIEWPORT
;
1380 case VK_DYNAMIC_STATE_SCISSOR
:
1381 return RADV_DYNAMIC_SCISSOR
;
1382 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1383 return RADV_DYNAMIC_LINE_WIDTH
;
1384 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1385 return RADV_DYNAMIC_DEPTH_BIAS
;
1386 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1387 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1388 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1389 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1390 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1391 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1392 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1393 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1394 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1395 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1396 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1397 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1398 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1399 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1401 unreachable("Unhandled dynamic state");
1405 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1407 uint32_t states
= RADV_DYNAMIC_ALL
;
1409 /* If rasterization is disabled we do not care about any of the dynamic states,
1410 * since they are all rasterization related only. */
1411 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1414 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1415 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1417 if (!pCreateInfo
->pDepthStencilState
||
1418 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1419 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1421 if (!pCreateInfo
->pDepthStencilState
||
1422 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1423 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1424 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1425 RADV_DYNAMIC_STENCIL_REFERENCE
);
1427 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1428 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1430 if (!pCreateInfo
->pMultisampleState
||
1431 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1432 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1433 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1435 /* TODO: blend constants & line width. */
1442 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1443 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1445 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1446 uint32_t states
= needed_states
;
1447 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1448 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1450 pipeline
->dynamic_state
= default_dynamic_state
;
1451 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1453 if (pCreateInfo
->pDynamicState
) {
1454 /* Remove all of the states that are marked as dynamic */
1455 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1456 for (uint32_t s
= 0; s
< count
; s
++)
1457 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1460 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1462 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1463 assert(pCreateInfo
->pViewportState
);
1465 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1466 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1467 typed_memcpy(dynamic
->viewport
.viewports
,
1468 pCreateInfo
->pViewportState
->pViewports
,
1469 pCreateInfo
->pViewportState
->viewportCount
);
1473 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1474 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1475 if (states
& RADV_DYNAMIC_SCISSOR
) {
1476 typed_memcpy(dynamic
->scissor
.scissors
,
1477 pCreateInfo
->pViewportState
->pScissors
,
1478 pCreateInfo
->pViewportState
->scissorCount
);
1482 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1483 assert(pCreateInfo
->pRasterizationState
);
1484 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1487 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1488 assert(pCreateInfo
->pRasterizationState
);
1489 dynamic
->depth_bias
.bias
=
1490 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1491 dynamic
->depth_bias
.clamp
=
1492 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1493 dynamic
->depth_bias
.slope
=
1494 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1497 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1499 * pColorBlendState is [...] NULL if the pipeline has rasterization
1500 * disabled or if the subpass of the render pass the pipeline is
1501 * created against does not use any color attachments.
1503 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1504 assert(pCreateInfo
->pColorBlendState
);
1505 typed_memcpy(dynamic
->blend_constants
,
1506 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1509 /* If there is no depthstencil attachment, then don't read
1510 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1511 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1512 * no need to override the depthstencil defaults in
1513 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1515 * Section 9.2 of the Vulkan 1.0.15 spec says:
1517 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1518 * disabled or if the subpass of the render pass the pipeline is created
1519 * against does not use a depth/stencil attachment.
1521 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1522 assert(pCreateInfo
->pDepthStencilState
);
1524 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1525 dynamic
->depth_bounds
.min
=
1526 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1527 dynamic
->depth_bounds
.max
=
1528 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1531 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1532 dynamic
->stencil_compare_mask
.front
=
1533 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1534 dynamic
->stencil_compare_mask
.back
=
1535 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1538 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1539 dynamic
->stencil_write_mask
.front
=
1540 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1541 dynamic
->stencil_write_mask
.back
=
1542 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1545 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1546 dynamic
->stencil_reference
.front
=
1547 pCreateInfo
->pDepthStencilState
->front
.reference
;
1548 dynamic
->stencil_reference
.back
=
1549 pCreateInfo
->pDepthStencilState
->back
.reference
;
1553 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1554 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1555 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1556 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1557 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1558 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1559 discard_rectangle_info
->pDiscardRectangles
,
1560 discard_rectangle_info
->discardRectangleCount
);
1564 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1565 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1566 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1567 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1568 /* If sampleLocationsEnable is VK_FALSE, the default sample
1569 * locations are used and the values specified in
1570 * sampleLocationsInfo are ignored.
1572 if (sample_location_info
->sampleLocationsEnable
) {
1573 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1574 &sample_location_info
->sampleLocationsInfo
;
1576 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1578 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1579 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1580 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1581 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1582 pSampleLocationsInfo
->pSampleLocations
,
1583 pSampleLocationsInfo
->sampleLocationsCount
);
1587 pipeline
->dynamic_state
.mask
= states
;
1591 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1592 const struct radv_pipeline
*pipeline
,
1594 struct radv_shader_info
*infos
,
1595 struct gfx9_gs_info
*out
)
1597 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1598 struct radv_es_output_info
*es_info
;
1599 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1600 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1602 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1603 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1604 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1606 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1607 bool uses_adjacency
;
1608 switch(key
->topology
) {
1609 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1610 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1611 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1612 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1613 uses_adjacency
= true;
1616 uses_adjacency
= false;
1620 /* All these are in dwords: */
1621 /* We can't allow using the whole LDS, because GS waves compete with
1622 * other shader stages for LDS space. */
1623 const unsigned max_lds_size
= 8 * 1024;
1624 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1625 unsigned esgs_lds_size
;
1627 /* All these are per subgroup: */
1628 const unsigned max_out_prims
= 32 * 1024;
1629 const unsigned max_es_verts
= 255;
1630 const unsigned ideal_gs_prims
= 64;
1631 unsigned max_gs_prims
, gs_prims
;
1632 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1634 if (uses_adjacency
|| gs_num_invocations
> 1)
1635 max_gs_prims
= 127 / gs_num_invocations
;
1639 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1640 * Make sure we don't go over the maximum value.
1642 if (gs_info
->gs
.vertices_out
> 0) {
1643 max_gs_prims
= MIN2(max_gs_prims
,
1645 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1647 assert(max_gs_prims
> 0);
1649 /* If the primitive has adjacency, halve the number of vertices
1650 * that will be reused in multiple primitives.
1652 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1654 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1655 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1657 /* Compute ESGS LDS size based on the worst case number of ES vertices
1658 * needed to create the target number of GS prims per subgroup.
1660 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1662 /* If total LDS usage is too big, refactor partitions based on ratio
1663 * of ESGS item sizes.
1665 if (esgs_lds_size
> max_lds_size
) {
1666 /* Our target GS Prims Per Subgroup was too large. Calculate
1667 * the maximum number of GS Prims Per Subgroup that will fit
1668 * into LDS, capped by the maximum that the hardware can support.
1670 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1672 assert(gs_prims
> 0);
1673 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1676 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1677 assert(esgs_lds_size
<= max_lds_size
);
1680 /* Now calculate remaining ESGS information. */
1682 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1684 es_verts
= max_es_verts
;
1686 /* Vertices for adjacency primitives are not always reused, so restore
1687 * it for ES_VERTS_PER_SUBGRP.
1689 min_es_verts
= gs_info
->gs
.vertices_in
;
1691 /* For normal primitives, the VGT only checks if they are past the ES
1692 * verts per subgroup after allocating a full GS primitive and if they
1693 * are, kick off a new subgroup. But if those additional ES verts are
1694 * unique (e.g. not reused) we need to make sure there is enough LDS
1695 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1697 es_verts
-= min_es_verts
- 1;
1699 uint32_t es_verts_per_subgroup
= es_verts
;
1700 uint32_t gs_prims_per_subgroup
= gs_prims
;
1701 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1702 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1703 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1704 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1705 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1706 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1707 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1708 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1709 assert(max_prims_per_subgroup
<= max_out_prims
);
1712 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1713 unsigned min_verts_per_prim
, bool use_adjacency
)
1715 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1718 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1722 radv_get_num_input_vertices(nir_shader
**nir
)
1724 if (nir
[MESA_SHADER_GEOMETRY
]) {
1725 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1727 return gs
->info
.gs
.vertices_in
;
1730 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1731 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1733 if (tes
->info
.tess
.point_mode
)
1735 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1744 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1745 struct radv_pipeline
*pipeline
,
1747 struct radv_shader_info
*infos
,
1748 struct gfx10_ngg_info
*ngg
)
1750 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1751 struct radv_es_output_info
*es_info
=
1752 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1753 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1754 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1755 unsigned min_verts_per_prim
=
1756 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1757 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1758 bool uses_adjacency
;
1759 switch(key
->topology
) {
1760 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1761 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1762 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1763 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1764 uses_adjacency
= true;
1767 uses_adjacency
= false;
1771 /* All these are in dwords: */
1772 /* We can't allow using the whole LDS, because GS waves compete with
1773 * other shader stages for LDS space.
1775 * TODO: We should really take the shader's internal LDS use into
1776 * account. The linker will fail if the size is greater than
1779 const unsigned max_lds_size
= 8 * 1024 - 768;
1780 const unsigned target_lds_size
= max_lds_size
;
1781 unsigned esvert_lds_size
= 0;
1782 unsigned gsprim_lds_size
= 0;
1784 /* All these are per subgroup: */
1785 bool max_vert_out_per_gs_instance
= false;
1786 unsigned max_esverts_base
= 256;
1787 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1789 /* Hardware has the following non-natural restrictions on the value
1790 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1792 * - at most 252 for any line input primitive type
1793 * - at most 251 for any quad input primitive type
1794 * - at most 251 for triangle strips with adjacency (this happens to
1795 * be the natural limit for triangle *lists* with adjacency)
1797 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1799 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1800 unsigned max_out_verts_per_gsprim
=
1801 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1803 if (max_out_verts_per_gsprim
<= 256) {
1804 if (max_out_verts_per_gsprim
) {
1805 max_gsprims_base
= MIN2(max_gsprims_base
,
1806 256 / max_out_verts_per_gsprim
);
1809 /* Use special multi-cycling mode in which each GS
1810 * instance gets its own subgroup. Does not work with
1812 max_vert_out_per_gs_instance
= true;
1813 max_gsprims_base
= 1;
1814 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1817 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1818 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1821 /* LDS size for passing data from GS to ES. */
1822 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1823 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1824 : &infos
[MESA_SHADER_VERTEX
].so
;
1826 if (so_info
->num_outputs
)
1827 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1829 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1830 * corresponding to the ES thread of the provoking vertex. All
1831 * ES threads load and export PrimitiveID for their thread.
1833 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1834 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1835 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1838 unsigned max_gsprims
= max_gsprims_base
;
1839 unsigned max_esverts
= max_esverts_base
;
1841 if (esvert_lds_size
)
1842 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1843 if (gsprim_lds_size
)
1844 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1846 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1847 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1848 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1850 if (esvert_lds_size
|| gsprim_lds_size
) {
1851 /* Now that we have a rough proportionality between esverts
1852 * and gsprims based on the primitive type, scale both of them
1853 * down simultaneously based on required LDS space.
1855 * We could be smarter about this if we knew how much vertex
1858 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1859 max_gsprims
* gsprim_lds_size
;
1860 if (lds_total
> target_lds_size
) {
1861 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1862 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1864 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1865 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1866 min_verts_per_prim
, uses_adjacency
);
1867 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1871 /* Round up towards full wave sizes for better ALU utilization. */
1872 if (!max_vert_out_per_gs_instance
) {
1873 unsigned orig_max_esverts
;
1874 unsigned orig_max_gsprims
;
1877 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1878 wavesize
= gs_info
->wave_size
;
1880 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1881 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1882 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1886 orig_max_esverts
= max_esverts
;
1887 orig_max_gsprims
= max_gsprims
;
1889 max_esverts
= align(max_esverts
, wavesize
);
1890 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1891 if (esvert_lds_size
)
1892 max_esverts
= MIN2(max_esverts
,
1893 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1895 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1897 max_gsprims
= align(max_gsprims
, wavesize
);
1898 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1899 if (gsprim_lds_size
)
1900 max_gsprims
= MIN2(max_gsprims
,
1901 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1903 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1904 min_verts_per_prim
, uses_adjacency
);
1905 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1906 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1909 /* Hardware restriction: minimum value of max_esverts */
1910 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1912 unsigned max_out_vertices
=
1913 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1914 gs_type
== MESA_SHADER_GEOMETRY
?
1915 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1917 assert(max_out_vertices
<= 256);
1919 unsigned prim_amp_factor
= 1;
1920 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1921 /* Number of output primitives per GS input primitive after
1923 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1926 /* The GE only checks against the maximum number of ES verts after
1927 * allocating a full GS primitive. So we need to ensure that whenever
1928 * this check passes, there is enough space for a full primitive without
1931 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1932 ngg
->max_gsprims
= max_gsprims
;
1933 ngg
->max_out_verts
= max_out_vertices
;
1934 ngg
->prim_amp_factor
= prim_amp_factor
;
1935 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1936 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1937 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1939 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1940 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1942 ngg
->vgt_esgs_ring_itemsize
= 1;
1945 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1947 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1951 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1952 const struct gfx9_gs_info
*gs
)
1954 struct radv_device
*device
= pipeline
->device
;
1955 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1956 unsigned wave_size
= 64;
1957 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1958 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1959 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1961 unsigned gs_vertex_reuse
=
1962 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1963 unsigned alignment
= 256 * num_se
;
1964 /* The maximum size is 63.999 MB per SE. */
1965 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1966 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1968 /* Calculate the minimum size. */
1969 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1970 wave_size
, alignment
);
1971 /* These are recommended sizes, not minimum sizes. */
1972 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1973 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1974 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1975 gs_info
->gs
.max_gsvs_emit_size
;
1977 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1978 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1979 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1981 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1982 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1984 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1987 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1990 /* If tessellation is all offchip and on-chip GS isn't used, this
1991 * workaround is not needed.
1995 /* SPI barrier management bug:
1996 * Make sure we have at least 4k of LDS in use to avoid the bug.
1997 * It applies to workgroup sizes of more than one wavefront.
1999 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
2000 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
2001 *lds_size
= MAX2(*lds_size
, 8);
2004 struct radv_shader_variant
*
2005 radv_get_shader(struct radv_pipeline
*pipeline
,
2006 gl_shader_stage stage
)
2008 if (stage
== MESA_SHADER_VERTEX
) {
2009 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
2010 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
2011 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
2012 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
2013 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2014 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2015 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
2016 if (!radv_pipeline_has_tess(pipeline
))
2018 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
2019 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2020 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2021 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2023 return pipeline
->shaders
[stage
];
2026 static struct radv_tessellation_state
2027 calculate_tess_state(struct radv_pipeline
*pipeline
,
2028 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2030 unsigned num_tcs_input_cp
;
2031 unsigned num_tcs_output_cp
;
2033 unsigned num_patches
;
2034 struct radv_tessellation_state tess
= {0};
2036 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2037 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
2038 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2040 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
2042 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2043 assert(lds_size
<= 65536);
2044 lds_size
= align(lds_size
, 512) / 512;
2046 assert(lds_size
<= 32768);
2047 lds_size
= align(lds_size
, 256) / 256;
2049 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
2051 tess
.lds_size
= lds_size
;
2053 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2054 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2055 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2056 tess
.num_patches
= num_patches
;
2058 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2059 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2061 switch (tes
->info
.tes
.primitive_mode
) {
2063 type
= V_028B6C_TESS_TRIANGLE
;
2066 type
= V_028B6C_TESS_QUAD
;
2069 type
= V_028B6C_TESS_ISOLINE
;
2073 switch (tes
->info
.tes
.spacing
) {
2074 case TESS_SPACING_EQUAL
:
2075 partitioning
= V_028B6C_PART_INTEGER
;
2077 case TESS_SPACING_FRACTIONAL_ODD
:
2078 partitioning
= V_028B6C_PART_FRAC_ODD
;
2080 case TESS_SPACING_FRACTIONAL_EVEN
:
2081 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2087 bool ccw
= tes
->info
.tes
.ccw
;
2088 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2089 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2090 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2092 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2095 if (tes
->info
.tes
.point_mode
)
2096 topology
= V_028B6C_OUTPUT_POINT
;
2097 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2098 topology
= V_028B6C_OUTPUT_LINE
;
2100 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2102 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2104 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2105 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2106 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2107 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2109 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2111 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2113 tess
.tf_param
= S_028B6C_TYPE(type
) |
2114 S_028B6C_PARTITIONING(partitioning
) |
2115 S_028B6C_TOPOLOGY(topology
) |
2116 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2121 static const struct radv_prim_vertex_count prim_size_table
[] = {
2122 [V_008958_DI_PT_NONE
] = {0, 0},
2123 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2124 [V_008958_DI_PT_LINELIST
] = {2, 2},
2125 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2126 [V_008958_DI_PT_TRILIST
] = {3, 3},
2127 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2128 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2129 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2130 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2131 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2132 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2133 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2134 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2135 [V_008958_DI_PT_POLYGON
] = {3, 1},
2136 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2139 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2141 if (radv_pipeline_has_gs(pipeline
))
2142 if (radv_pipeline_has_ngg(pipeline
))
2143 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2145 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2146 else if (radv_pipeline_has_tess(pipeline
))
2147 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2149 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2153 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2155 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2156 int shader_count
= 0;
2158 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2159 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2161 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2162 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2164 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2165 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2167 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2168 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2170 if(shaders
[MESA_SHADER_VERTEX
]) {
2171 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2174 if (shader_count
> 1) {
2175 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2176 unsigned last
= ordered_shaders
[0]->info
.stage
;
2178 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2179 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2180 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2182 for (int i
= 0; i
< shader_count
; ++i
) {
2183 nir_variable_mode mask
= 0;
2185 if (ordered_shaders
[i
]->info
.stage
!= first
)
2186 mask
= mask
| nir_var_shader_in
;
2188 if (ordered_shaders
[i
]->info
.stage
!= last
)
2189 mask
= mask
| nir_var_shader_out
;
2191 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2192 radv_optimize_nir(ordered_shaders
[i
], false, false);
2196 for (int i
= 1; i
< shader_count
; ++i
) {
2197 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2198 ordered_shaders
[i
- 1]);
2200 if (nir_link_opt_varyings(ordered_shaders
[i
],
2201 ordered_shaders
[i
- 1]))
2202 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2204 nir_remove_dead_variables(ordered_shaders
[i
],
2205 nir_var_shader_out
);
2206 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2209 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2210 ordered_shaders
[i
- 1]);
2212 nir_compact_varyings(ordered_shaders
[i
],
2213 ordered_shaders
[i
- 1], true);
2216 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2217 ac_lower_indirect_derefs(ordered_shaders
[i
],
2218 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2220 radv_optimize_nir(ordered_shaders
[i
], false, false);
2222 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2223 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2224 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2226 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2232 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2233 uint32_t attrib_binding
)
2235 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2236 const VkVertexInputBindingDescription
*input_binding
=
2237 &input_state
->pVertexBindingDescriptions
[i
];
2239 if (input_binding
->binding
== attrib_binding
)
2240 return input_binding
->stride
;
2246 static struct radv_pipeline_key
2247 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2248 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2249 const struct radv_blend_state
*blend
,
2250 bool has_view_index
)
2252 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2253 pCreateInfo
->pVertexInputState
;
2254 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2255 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2257 struct radv_pipeline_key key
;
2258 memset(&key
, 0, sizeof(key
));
2260 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2261 key
.optimisations_disabled
= 1;
2263 key
.has_multiview_view_index
= has_view_index
;
2265 uint32_t binding_input_rate
= 0;
2266 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2267 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2268 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2269 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2270 binding_input_rate
|= 1u << binding
;
2271 instance_rate_divisors
[binding
] = 1;
2274 if (divisor_state
) {
2275 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2276 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2277 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2281 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2282 const VkVertexInputAttributeDescription
*desc
=
2283 &input_state
->pVertexAttributeDescriptions
[i
];
2284 const struct vk_format_description
*format_desc
;
2285 unsigned location
= desc
->location
;
2286 unsigned binding
= desc
->binding
;
2287 unsigned num_format
, data_format
;
2290 if (binding_input_rate
& (1u << binding
)) {
2291 key
.instance_rate_inputs
|= 1u << location
;
2292 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2295 format_desc
= vk_format_description(desc
->format
);
2296 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2298 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2299 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2301 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2302 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2303 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2304 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2306 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2307 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2308 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2311 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2312 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2313 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2315 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2316 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2317 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2319 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2320 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2321 adjust
= RADV_ALPHA_ADJUST_SINT
;
2327 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2330 switch (desc
->format
) {
2331 case VK_FORMAT_B8G8R8A8_UNORM
:
2332 case VK_FORMAT_B8G8R8A8_SNORM
:
2333 case VK_FORMAT_B8G8R8A8_USCALED
:
2334 case VK_FORMAT_B8G8R8A8_SSCALED
:
2335 case VK_FORMAT_B8G8R8A8_UINT
:
2336 case VK_FORMAT_B8G8R8A8_SINT
:
2337 case VK_FORMAT_B8G8R8A8_SRGB
:
2338 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2339 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2340 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2341 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2342 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2343 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2344 key
.vertex_post_shuffle
|= 1 << location
;
2351 const VkPipelineTessellationStateCreateInfo
*tess
=
2352 radv_pipeline_get_tessellation_state(pCreateInfo
);
2354 key
.tess_input_vertices
= tess
->patchControlPoints
;
2356 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2357 radv_pipeline_get_multisample_state(pCreateInfo
);
2358 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2359 uint32_t num_samples
= vkms
->rasterizationSamples
;
2360 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2361 key
.num_samples
= num_samples
;
2362 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2365 key
.col_format
= blend
->spi_shader_col_format
;
2366 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2367 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2369 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2370 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2376 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2378 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2379 bool uses_xfb
= !!xfb
;
2386 radv_fill_shader_keys(struct radv_device
*device
,
2387 struct radv_shader_variant_key
*keys
,
2388 const struct radv_pipeline_key
*key
,
2391 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2392 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2393 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2394 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2395 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2396 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2397 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2398 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2399 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2401 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2403 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2404 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2405 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2406 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2407 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2409 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2412 if (nir
[MESA_SHADER_GEOMETRY
]) {
2413 if (nir
[MESA_SHADER_TESS_CTRL
])
2414 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2416 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2419 if (device
->physical_device
->use_ngg
) {
2420 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2421 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2423 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2426 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2427 nir
[MESA_SHADER_GEOMETRY
] &&
2428 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2429 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2430 /* Fallback to the legacy path if tessellation is
2431 * enabled with extreme geometry because
2432 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2435 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2439 * Disable NGG with geometry shaders. There are a bunch of
2441 * * GS primitives in pipeline statistic queries do not get
2442 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2444 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2446 if (nir
[MESA_SHADER_GEOMETRY
]) {
2447 if (nir
[MESA_SHADER_TESS_CTRL
])
2448 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2450 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2453 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2455 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2460 bool uses_xfb
= nir
[last_xfb_stage
] &&
2461 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2463 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2464 if (nir
[MESA_SHADER_TESS_CTRL
])
2465 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2467 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2470 /* Determine if the pipeline is eligible for the NGG passthrough
2471 * mode. It can't be enabled for geometry shaders, for NGG
2472 * streamout or for vertex shaders that export the primitive ID
2473 * (this is checked later because we don't have the info here.)
2475 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2476 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2477 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2478 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2479 } else if (nir
[MESA_SHADER_VERTEX
] &&
2480 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2481 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2486 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2487 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2489 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2490 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2491 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2492 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2493 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2495 if (nir
[MESA_SHADER_COMPUTE
]) {
2496 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2501 radv_get_wave_size(struct radv_device
*device
,
2502 const VkPipelineShaderStageCreateInfo
*pStage
,
2503 gl_shader_stage stage
,
2504 const struct radv_shader_variant_key
*key
)
2506 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2508 else if (stage
== MESA_SHADER_COMPUTE
) {
2509 if (key
->cs
.subgroup_size
) {
2510 /* Return the required subgroup size if specified. */
2511 return key
->cs
.subgroup_size
;
2513 return device
->physical_device
->cs_wave_size
;
2515 else if (stage
== MESA_SHADER_FRAGMENT
)
2516 return device
->physical_device
->ps_wave_size
;
2518 return device
->physical_device
->ge_wave_size
;
2522 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2523 const VkPipelineShaderStageCreateInfo
**pStages
,
2524 struct radv_shader_variant_key
*keys
,
2525 struct radv_shader_info
*infos
,
2528 unsigned active_stages
= 0;
2529 unsigned filled_stages
= 0;
2531 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2533 active_stages
|= (1 << i
);
2536 if (nir
[MESA_SHADER_FRAGMENT
]) {
2537 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2538 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2540 &keys
[MESA_SHADER_FRAGMENT
],
2541 &infos
[MESA_SHADER_FRAGMENT
]);
2543 /* TODO: These are no longer used as keys we should refactor this */
2544 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2545 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2546 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2547 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2548 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2549 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2550 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2551 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2552 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2553 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2554 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2555 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2557 /* NGG passthrough mode can't be enabled for vertex shaders
2558 * that export the primitive ID.
2560 * TODO: I should really refactor the keys logic.
2562 if (nir
[MESA_SHADER_VERTEX
] &&
2563 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2564 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2567 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2570 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2571 nir
[MESA_SHADER_TESS_CTRL
]) {
2572 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2573 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2574 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2576 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2578 for (int i
= 0; i
< 2; i
++) {
2579 radv_nir_shader_info_pass(combined_nir
[i
],
2580 pipeline
->layout
, &key
,
2581 &infos
[MESA_SHADER_TESS_CTRL
]);
2584 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2585 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2586 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2587 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2589 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2590 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2593 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2594 nir
[MESA_SHADER_GEOMETRY
]) {
2595 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2596 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2598 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2600 for (int i
= 0; i
< 2; i
++) {
2601 radv_nir_shader_info_pass(combined_nir
[i
],
2604 &infos
[MESA_SHADER_GEOMETRY
]);
2607 filled_stages
|= (1 << pre_stage
);
2608 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2611 active_stages
^= filled_stages
;
2612 while (active_stages
) {
2613 int i
= u_bit_scan(&active_stages
);
2615 if (i
== MESA_SHADER_TESS_CTRL
) {
2616 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2617 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2620 if (i
== MESA_SHADER_TESS_EVAL
) {
2621 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2622 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2623 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2624 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2627 radv_nir_shader_info_init(&infos
[i
]);
2628 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2629 &keys
[i
], &infos
[i
]);
2632 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2634 infos
[i
].wave_size
=
2635 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2641 merge_tess_info(struct shader_info
*tes_info
,
2642 const struct shader_info
*tcs_info
)
2644 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2646 * "PointMode. Controls generation of points rather than triangles
2647 * or lines. This functionality defaults to disabled, and is
2648 * enabled if either shader stage includes the execution mode.
2650 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2651 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2652 * and OutputVertices, it says:
2654 * "One mode must be set in at least one of the tessellation
2657 * So, the fields can be set in either the TCS or TES, but they must
2658 * agree if set in both. Our backend looks at TES, so bitwise-or in
2659 * the values from the TCS.
2661 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2662 tes_info
->tess
.tcs_vertices_out
== 0 ||
2663 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2664 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2666 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2667 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2668 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2669 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2671 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2672 tes_info
->tess
.primitive_mode
== 0 ||
2673 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2674 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2675 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2676 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2680 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2685 if (ext
->pPipelineCreationFeedback
) {
2686 ext
->pPipelineCreationFeedback
->flags
= 0;
2687 ext
->pPipelineCreationFeedback
->duration
= 0;
2690 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2691 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2692 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2697 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2702 feedback
->duration
-= radv_get_current_time();
2703 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2707 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2712 feedback
->duration
+= radv_get_current_time();
2713 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2714 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2718 bool radv_aco_supported_stage(gl_shader_stage stage
, bool has_ts
)
2720 return (stage
== MESA_SHADER_VERTEX
&& !has_ts
) ||
2721 (stage
== MESA_SHADER_GEOMETRY
&& !has_ts
) ||
2722 stage
== MESA_SHADER_FRAGMENT
||
2723 stage
== MESA_SHADER_COMPUTE
;
2726 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2727 struct radv_device
*device
,
2728 struct radv_pipeline_cache
*cache
,
2729 const struct radv_pipeline_key
*key
,
2730 const VkPipelineShaderStageCreateInfo
**pStages
,
2731 const VkPipelineCreateFlags flags
,
2732 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2733 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2735 struct radv_shader_module fs_m
= {0};
2736 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2737 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2738 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2739 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2740 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2741 unsigned char hash
[20], gs_copy_hash
[20];
2742 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2744 radv_start_feedback(pipeline_feedback
);
2746 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2748 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2749 if (modules
[i
]->nir
)
2750 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2751 strlen(modules
[i
]->nir
->info
.name
),
2754 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2758 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2759 memcpy(gs_copy_hash
, hash
, 20);
2760 gs_copy_hash
[0] ^= 1;
2762 bool found_in_application_cache
= true;
2763 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2764 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2765 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2766 &found_in_application_cache
);
2767 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2770 if (!keep_executable_info
&&
2771 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2772 &found_in_application_cache
) &&
2773 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2774 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2778 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2780 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2781 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2782 fs_m
.nir
= fs_b
.shader
;
2783 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2786 bool has_ts
= modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
];
2787 bool use_aco
= device
->physical_device
->use_aco
;
2789 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2790 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2795 radv_start_feedback(stage_feedbacks
[i
]);
2797 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_ts
);
2798 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2799 stage
? stage
->pName
: "main", i
,
2800 stage
? stage
->pSpecializationInfo
: NULL
,
2801 flags
, pipeline
->layout
, aco
);
2803 /* We don't want to alter meta shaders IR directly so clone it
2806 if (nir
[i
]->info
.name
) {
2807 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2810 radv_stop_feedback(stage_feedbacks
[i
], false);
2813 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2814 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2815 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2818 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2819 radv_link_shaders(pipeline
, nir
);
2821 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2823 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2824 nir_lower_non_uniform_ubo_access
|
2825 nir_lower_non_uniform_ssbo_access
|
2826 nir_lower_non_uniform_texture_access
|
2827 nir_lower_non_uniform_image_access
);
2829 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_ts
);
2831 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2834 if (radv_can_dump_shader(device
, modules
[i
], false))
2835 nir_print_shader(nir
[i
], stderr
);
2838 if (nir
[MESA_SHADER_FRAGMENT
])
2839 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2841 radv_fill_shader_keys(device
, keys
, key
, nir
);
2843 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2845 if ((nir
[MESA_SHADER_VERTEX
] &&
2846 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2847 (nir
[MESA_SHADER_TESS_EVAL
] &&
2848 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2849 struct gfx10_ngg_info
*ngg_info
;
2851 if (nir
[MESA_SHADER_GEOMETRY
])
2852 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2853 else if (nir
[MESA_SHADER_TESS_CTRL
])
2854 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2856 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2858 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2859 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2860 struct gfx9_gs_info
*gs_info
=
2861 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2863 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2866 if(modules
[MESA_SHADER_GEOMETRY
]) {
2867 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2868 if (!pipeline
->gs_copy_shader
&&
2869 !radv_pipeline_has_ngg(pipeline
)) {
2870 struct radv_shader_info info
= {};
2871 struct radv_shader_variant_key key
= {};
2873 key
.has_multiview_view_index
=
2874 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2876 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2877 pipeline
->layout
, &key
,
2879 info
.wave_size
= 64; /* Wave32 not supported. */
2881 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2882 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2883 &gs_copy_binary
, keep_executable_info
,
2884 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
,
2888 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2889 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2890 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2892 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2893 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2895 radv_pipeline_cache_insert_shaders(device
, cache
,
2900 free(gs_copy_binary
);
2903 if (nir
[MESA_SHADER_FRAGMENT
]) {
2904 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2905 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2907 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_FRAGMENT
, has_ts
);
2908 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2909 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2910 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2911 infos
+ MESA_SHADER_FRAGMENT
,
2912 keep_executable_info
, aco
,
2913 &binaries
[MESA_SHADER_FRAGMENT
]);
2915 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2919 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2920 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2921 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2922 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2923 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2925 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2927 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2929 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2930 false, &binaries
[MESA_SHADER_TESS_CTRL
]);
2932 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2934 modules
[MESA_SHADER_VERTEX
] = NULL
;
2935 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2936 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2939 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2940 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2941 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2942 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2944 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2946 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_GEOMETRY
, has_ts
);
2947 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2949 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2950 aco
, &binaries
[MESA_SHADER_GEOMETRY
]);
2952 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2954 modules
[pre_stage
] = NULL
;
2957 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2958 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2959 if (i
== MESA_SHADER_TESS_CTRL
) {
2960 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2962 if (i
== MESA_SHADER_TESS_EVAL
) {
2963 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2964 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2967 radv_start_feedback(stage_feedbacks
[i
]);
2969 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_ts
);
2970 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2972 keys
+ i
, infos
+ i
,keep_executable_info
,
2975 radv_stop_feedback(stage_feedbacks
[i
], false);
2979 if (!keep_executable_info
) {
2980 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2984 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2987 ralloc_free(nir
[i
]);
2989 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2990 radv_shader_dump_stats(device
,
2991 pipeline
->shaders
[i
],
2997 ralloc_free(fs_m
.nir
);
2999 radv_stop_feedback(pipeline_feedback
, false);
3003 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3004 gl_shader_stage stage
, enum chip_class chip_class
)
3006 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3007 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3008 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3011 case MESA_SHADER_FRAGMENT
:
3012 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3013 case MESA_SHADER_VERTEX
:
3015 if (chip_class
>= GFX10
) {
3016 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3017 } else if (chip_class
== GFX9
) {
3018 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3020 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3026 if (chip_class
>= GFX10
) {
3027 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3029 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3034 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3036 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3037 case MESA_SHADER_GEOMETRY
:
3038 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3039 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3040 case MESA_SHADER_COMPUTE
:
3041 return R_00B900_COMPUTE_USER_DATA_0
;
3042 case MESA_SHADER_TESS_CTRL
:
3043 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3044 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3045 case MESA_SHADER_TESS_EVAL
:
3047 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3048 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3049 } else if (has_ngg
) {
3050 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3052 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3055 unreachable("unknown shader");
3059 struct radv_bin_size_entry
{
3065 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3067 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3071 /* One shader engine */
3077 { UINT_MAX
, { 0, 0}},
3080 /* Two shader engines */
3086 { UINT_MAX
, { 0, 0}},
3089 /* Four shader engines */
3094 { UINT_MAX
, { 0, 0}},
3100 /* One shader engine */
3106 { UINT_MAX
, { 0, 0}},
3109 /* Two shader engines */
3115 { UINT_MAX
, { 0, 0}},
3118 /* Four shader engines */
3125 { UINT_MAX
, { 0, 0}},
3131 /* One shader engine */
3138 { UINT_MAX
, { 0, 0}},
3141 /* Two shader engines */
3149 { UINT_MAX
, { 0, 0}},
3152 /* Four shader engines */
3160 { UINT_MAX
, { 0, 0}},
3164 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3168 // One shader engine
3175 { UINT_MAX
, { 0, 0}},
3178 // Two shader engines
3186 { UINT_MAX
, { 0, 0}},
3189 // Four shader engines
3197 { UINT_MAX
, { 0, 0}},
3203 // One shader engine
3211 { UINT_MAX
, { 0, 0}},
3214 // Two shader engines
3223 { UINT_MAX
, { 0, 0}},
3226 // Four shader engines
3235 { UINT_MAX
, { 0, 0}},
3241 // One shader engine
3249 { UINT_MAX
, { 0, 0}},
3252 // Two shader engines
3261 { UINT_MAX
, { 0, 0}},
3264 // Four shader engines
3272 { UINT_MAX
, { 0, 0}},
3277 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3278 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3279 VkExtent2D extent
= {512, 512};
3281 unsigned log_num_rb_per_se
=
3282 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3283 pipeline
->device
->physical_device
->rad_info
.max_se
);
3284 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3286 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3287 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3288 unsigned effective_samples
= total_samples
;
3289 unsigned color_bytes_per_pixel
= 0;
3291 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3292 radv_pipeline_get_color_blend_state(pCreateInfo
);
3294 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3295 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3298 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3301 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3302 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3305 /* MSAA images typically don't use all samples all the time. */
3306 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3307 effective_samples
= 2;
3308 color_bytes_per_pixel
*= effective_samples
;
3311 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3312 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3315 extent
= color_entry
->extent
;
3317 if (subpass
->depth_stencil_attachment
) {
3318 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3320 /* Coefficients taken from AMDVLK */
3321 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3322 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3323 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3325 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3326 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3329 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3330 extent
= ds_entry
->extent
;
3337 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3339 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3340 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3341 VkExtent2D extent
= {512, 512};
3343 const unsigned db_tag_size
= 64;
3344 const unsigned db_tag_count
= 312;
3345 const unsigned color_tag_size
= 1024;
3346 const unsigned color_tag_count
= 31;
3347 const unsigned fmask_tag_size
= 256;
3348 const unsigned fmask_tag_count
= 44;
3350 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3351 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3353 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3354 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3355 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3357 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3358 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3360 unsigned color_bytes_per_pixel
= 0;
3361 unsigned fmask_bytes_per_pixel
= 0;
3363 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3364 radv_pipeline_get_color_blend_state(pCreateInfo
);
3366 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3367 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3370 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3373 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3374 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3376 if (total_samples
> 1) {
3377 assert(samples_log
<= 3);
3378 const unsigned fmask_array
[] = {0, 1, 1, 4};
3379 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3383 color_bytes_per_pixel
*= total_samples
;
3385 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3387 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3388 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3389 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3391 if (fmask_bytes_per_pixel
) {
3392 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3394 const VkExtent2D fmask_extent
= (VkExtent2D
){
3395 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3396 .height
= 1ull << (color_pixel_count_log
/ 2)
3399 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3400 extent
= fmask_extent
;
3403 if (subpass
->depth_stencil_attachment
) {
3404 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3406 /* Coefficients taken from AMDVLK */
3407 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3408 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3409 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3411 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3413 const VkExtent2D db_extent
= (VkExtent2D
){
3414 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3415 .height
= 1ull << (color_pixel_count_log
/ 2)
3418 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3422 extent
.width
= MAX2(extent
.width
, 128);
3423 extent
.height
= MAX2(extent
.width
, 64);
3429 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3430 struct radv_pipeline
*pipeline
,
3431 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3433 uint32_t pa_sc_binner_cntl_0
=
3434 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3435 S_028C44_DISABLE_START_OF_PRIM(1);
3436 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3438 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3439 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3440 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3441 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3442 radv_pipeline_get_color_blend_state(pCreateInfo
);
3443 unsigned min_bytes_per_pixel
= 0;
3446 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3447 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3450 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3453 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3454 unsigned bytes
= vk_format_get_blocksize(format
);
3455 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3456 min_bytes_per_pixel
= bytes
;
3460 pa_sc_binner_cntl_0
=
3461 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3462 S_028C44_BIN_SIZE_X(0) |
3463 S_028C44_BIN_SIZE_Y(0) |
3464 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3465 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3466 S_028C44_DISABLE_START_OF_PRIM(1);
3469 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3470 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3473 struct radv_binning_settings
3474 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3476 struct radv_binning_settings settings
;
3477 if (pdev
->rad_info
.has_dedicated_vram
) {
3478 settings
.context_states_per_bin
= 1;
3479 settings
.persistent_states_per_bin
= 1;
3480 settings
.fpovs_per_batch
= 63;
3482 /* The context states are affected by the scissor bug. */
3483 settings
.context_states_per_bin
= 6;
3484 /* 32 causes hangs for RAVEN. */
3485 settings
.persistent_states_per_bin
= 16;
3486 settings
.fpovs_per_batch
= 63;
3489 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3490 settings
.context_states_per_bin
= 1;
3496 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3497 struct radv_pipeline
*pipeline
,
3498 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3499 const struct radv_blend_state
*blend
)
3501 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3504 VkExtent2D bin_size
;
3505 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3506 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3507 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3508 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3510 unreachable("Unhandled generation for binning bin size calculation");
3512 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3513 struct radv_binning_settings settings
=
3514 radv_get_binning_settings(pipeline
->device
->physical_device
);
3516 bool disable_start_of_prim
= true;
3517 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3519 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3521 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3522 !ps
->info
.ps
.can_discard
&&
3523 !ps
->info
.ps
.writes_memory
&&
3524 blend
->cb_target_enabled_4bit
) {
3525 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3526 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3529 const uint32_t pa_sc_binner_cntl_0
=
3530 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3531 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3532 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3533 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3534 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3535 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3536 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3537 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3538 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3539 S_028C44_OPTIMAL_BIN_SELECTION(1);
3541 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3542 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3544 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3549 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3550 struct radv_pipeline
*pipeline
,
3551 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3552 const struct radv_graphics_pipeline_create_info
*extra
)
3554 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3555 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3556 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3557 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3558 struct radv_render_pass_attachment
*attachment
= NULL
;
3559 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3560 uint32_t db_render_control
= 0, db_render_override2
= 0;
3561 uint32_t db_render_override
= 0;
3563 if (subpass
->depth_stencil_attachment
)
3564 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3566 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3567 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3569 if (vkds
&& has_depth_attachment
) {
3570 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3571 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3572 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3573 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3575 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3576 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3579 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3580 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3581 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3582 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3583 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3584 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3586 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3587 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3588 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3589 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3592 if (attachment
&& extra
) {
3593 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3594 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3596 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3597 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3598 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3599 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3600 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3603 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3604 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3606 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3607 ps
->info
.ps
.writes_z
) {
3608 /* From VK_EXT_depth_range_unrestricted spec:
3610 * "The behavior described in Primitive Clipping still applies.
3611 * If depth clamping is disabled the depth values are still
3612 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3613 * depth clamping is enabled the above equation is ignored and
3614 * the depth values are instead clamped to the VkViewport
3615 * minDepth and maxDepth values, which in the case of this
3616 * extension can be outside of the 0.0 to 1.0 range."
3618 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3621 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3622 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3624 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3625 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3626 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3630 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3631 struct radv_pipeline
*pipeline
,
3632 const struct radv_blend_state
*blend
)
3634 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3635 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3637 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3638 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3640 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3642 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3643 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3646 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3648 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3649 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3651 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3652 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3655 static const VkConservativeRasterizationModeEXT
3656 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3658 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3659 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3661 if (!conservative_raster
)
3662 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3663 return conservative_raster
->conservativeRasterizationMode
;
3667 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3668 struct radv_pipeline
*pipeline
,
3669 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3671 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3672 const VkConservativeRasterizationModeEXT mode
=
3673 radv_get_conservative_raster_mode(vkraster
);
3674 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3675 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3677 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3678 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3679 if (depth_clip_state
) {
3680 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3683 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3684 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3685 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3686 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3687 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3688 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3690 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3691 S_0286D4_FLAT_SHADE_ENA(1) |
3692 S_0286D4_PNT_SPRITE_ENA(1) |
3693 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3694 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3695 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3696 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3697 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3699 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3700 S_028BE4_PIX_CENTER(1) | // TODO verify
3701 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3702 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3704 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3705 S_028814_FACE(vkraster
->frontFace
) |
3706 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3707 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3708 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3709 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3710 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3711 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3712 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3713 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3715 /* Conservative rasterization. */
3716 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3717 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3719 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3720 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3721 S_028804_OVERRASTERIZATION_AMOUNT(4);
3723 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3724 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3725 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3727 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3728 pa_sc_conservative_rast
|=
3729 S_028C4C_OVER_RAST_ENABLE(1) |
3730 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3731 S_028C4C_UNDER_RAST_ENABLE(0) |
3732 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3733 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3735 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3736 pa_sc_conservative_rast
|=
3737 S_028C4C_OVER_RAST_ENABLE(0) |
3738 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3739 S_028C4C_UNDER_RAST_ENABLE(1) |
3740 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3741 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3745 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3746 pa_sc_conservative_rast
);
3751 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3752 struct radv_pipeline
*pipeline
)
3754 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3756 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3757 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3758 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3760 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3761 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3762 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3763 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3764 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3766 /* The exclusion bits can be set to improve rasterization efficiency
3767 * if no sample lies on the pixel boundary (-8 sample offset). It's
3768 * currently always TRUE because the driver doesn't support 16 samples.
3770 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3771 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3772 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3773 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3775 /* GFX9: Flush DFSM when the AA mode changes. */
3776 if (pipeline
->device
->dfsm_allowed
) {
3777 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3778 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3783 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3784 struct radv_pipeline
*pipeline
)
3786 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3787 const struct radv_shader_variant
*vs
=
3788 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3789 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3790 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3791 unsigned vgt_primitiveid_en
= 0;
3792 uint32_t vgt_gs_mode
= 0;
3794 if (radv_pipeline_has_ngg(pipeline
))
3797 if (radv_pipeline_has_gs(pipeline
)) {
3798 const struct radv_shader_variant
*gs
=
3799 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3801 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3802 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3803 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3804 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3805 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3808 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3809 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3813 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3814 struct radeon_cmdbuf
*cs
,
3815 struct radv_pipeline
*pipeline
,
3816 struct radv_shader_variant
*shader
)
3818 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3820 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3821 radeon_emit(cs
, va
>> 8);
3822 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3823 radeon_emit(cs
, shader
->config
.rsrc1
);
3824 radeon_emit(cs
, shader
->config
.rsrc2
);
3826 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3827 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3828 clip_dist_mask
= outinfo
->clip_dist_mask
;
3829 cull_dist_mask
= outinfo
->cull_dist_mask
;
3830 total_mask
= clip_dist_mask
| cull_dist_mask
;
3831 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3832 outinfo
->writes_layer
||
3833 outinfo
->writes_viewport_index
;
3834 unsigned spi_vs_out_config
, nparams
;
3836 /* VS is required to export at least one param. */
3837 nparams
= MAX2(outinfo
->param_exports
, 1);
3838 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3840 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3841 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3844 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3846 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3847 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3848 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3849 V_02870C_SPI_SHADER_4COMP
:
3850 V_02870C_SPI_SHADER_NONE
) |
3851 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3852 V_02870C_SPI_SHADER_4COMP
:
3853 V_02870C_SPI_SHADER_NONE
) |
3854 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3855 V_02870C_SPI_SHADER_4COMP
:
3856 V_02870C_SPI_SHADER_NONE
));
3858 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3859 S_028818_VTX_W0_FMT(1) |
3860 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3861 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3862 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3864 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3865 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3866 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3867 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3868 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3869 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3870 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3871 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3872 cull_dist_mask
<< 8 |
3875 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3876 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3877 outinfo
->writes_viewport_index
);
3881 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3882 struct radv_pipeline
*pipeline
,
3883 struct radv_shader_variant
*shader
)
3885 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3887 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3888 radeon_emit(cs
, va
>> 8);
3889 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3890 radeon_emit(cs
, shader
->config
.rsrc1
);
3891 radeon_emit(cs
, shader
->config
.rsrc2
);
3895 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3896 struct radv_pipeline
*pipeline
,
3897 struct radv_shader_variant
*shader
,
3898 const struct radv_tessellation_state
*tess
)
3900 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3901 uint32_t rsrc2
= shader
->config
.rsrc2
;
3903 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3904 radeon_emit(cs
, va
>> 8);
3905 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3907 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3908 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3909 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3910 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3912 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3913 radeon_emit(cs
, shader
->config
.rsrc1
);
3914 radeon_emit(cs
, rsrc2
);
3918 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3919 struct radeon_cmdbuf
*cs
,
3920 struct radv_pipeline
*pipeline
,
3921 struct radv_shader_variant
*shader
)
3923 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3924 gl_shader_stage es_type
=
3925 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3926 struct radv_shader_variant
*es
=
3927 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3928 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3930 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3931 radeon_emit(cs
, va
>> 8);
3932 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3933 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3934 radeon_emit(cs
, shader
->config
.rsrc1
);
3935 radeon_emit(cs
, shader
->config
.rsrc2
);
3937 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3938 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3939 clip_dist_mask
= outinfo
->clip_dist_mask
;
3940 cull_dist_mask
= outinfo
->cull_dist_mask
;
3941 total_mask
= clip_dist_mask
| cull_dist_mask
;
3942 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3943 outinfo
->writes_layer
||
3944 outinfo
->writes_viewport_index
;
3945 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3946 (es
&& es
->info
.uses_prim_id
);
3947 bool break_wave_at_eoi
= false;
3951 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3952 struct radv_shader_variant
*gs
=
3953 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3955 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3956 break_wave_at_eoi
= true;
3959 nparams
= MAX2(outinfo
->param_exports
, 1);
3960 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3961 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3962 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3964 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3965 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3966 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3967 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3968 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3969 V_02870C_SPI_SHADER_4COMP
:
3970 V_02870C_SPI_SHADER_NONE
) |
3971 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3972 V_02870C_SPI_SHADER_4COMP
:
3973 V_02870C_SPI_SHADER_NONE
) |
3974 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3975 V_02870C_SPI_SHADER_4COMP
:
3976 V_02870C_SPI_SHADER_NONE
));
3978 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3979 S_028818_VTX_W0_FMT(1) |
3980 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3981 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3982 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3983 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3984 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3985 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3986 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3987 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3988 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3989 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3990 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3991 cull_dist_mask
<< 8 |
3994 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3995 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3996 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
3998 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3999 ngg_state
->vgt_esgs_ring_itemsize
);
4001 /* NGG specific registers. */
4002 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4003 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4005 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4006 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4007 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4008 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4009 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4010 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4011 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4012 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4013 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4014 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4015 S_028B90_CNT(gs_num_invocations
) |
4016 S_028B90_ENABLE(gs_num_invocations
> 1) |
4017 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4019 /* User edge flags are set by the pos exports. If user edge flags are
4020 * not used, we must use hw-generated edge flags and pass them via
4021 * the prim export to prevent drawing lines on internal edges of
4022 * decomposed primitives (such as quads) with polygon mode = lines.
4024 * TODO: We should combine hw-generated edge flags with user edge
4025 * flags in the shader.
4027 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4028 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4029 !radv_pipeline_has_gs(pipeline
)));
4031 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4032 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4033 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4035 /* Bug workaround for a possible hang with non-tessellation cases.
4036 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4038 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4040 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
4041 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
4042 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
4043 !radv_pipeline_has_tess(pipeline
) &&
4044 ngg_state
->hw_max_esverts
!= 256) {
4045 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4047 if (ngg_state
->hw_max_esverts
> 5) {
4048 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4052 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4056 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4057 struct radv_pipeline
*pipeline
,
4058 struct radv_shader_variant
*shader
,
4059 const struct radv_tessellation_state
*tess
)
4061 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4063 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4064 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4066 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4067 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4069 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4072 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4073 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4074 radeon_emit(cs
, va
>> 8);
4075 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4077 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4078 radeon_emit(cs
, va
>> 8);
4079 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4082 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4083 radeon_emit(cs
, shader
->config
.rsrc1
);
4084 radeon_emit(cs
, hs_rsrc2
);
4086 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4087 radeon_emit(cs
, va
>> 8);
4088 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4089 radeon_emit(cs
, shader
->config
.rsrc1
);
4090 radeon_emit(cs
, shader
->config
.rsrc2
);
4095 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4096 struct radeon_cmdbuf
*cs
,
4097 struct radv_pipeline
*pipeline
,
4098 const struct radv_tessellation_state
*tess
)
4100 struct radv_shader_variant
*vs
;
4102 /* Skip shaders merged into HS/GS */
4103 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4107 if (vs
->info
.vs
.as_ls
)
4108 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4109 else if (vs
->info
.vs
.as_es
)
4110 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4111 else if (vs
->info
.is_ngg
)
4112 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4114 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4118 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4119 struct radeon_cmdbuf
*cs
,
4120 struct radv_pipeline
*pipeline
,
4121 const struct radv_tessellation_state
*tess
)
4123 if (!radv_pipeline_has_tess(pipeline
))
4126 struct radv_shader_variant
*tes
, *tcs
;
4128 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4129 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4132 if (tes
->info
.is_ngg
) {
4133 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4134 } else if (tes
->info
.tes
.as_es
)
4135 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4137 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4140 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4142 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4145 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4146 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4147 tess
->ls_hs_config
);
4149 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4150 tess
->ls_hs_config
);
4152 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4153 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4154 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4155 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4156 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4157 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4162 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4163 struct radeon_cmdbuf
*cs
,
4164 struct radv_pipeline
*pipeline
,
4165 struct radv_shader_variant
*gs
)
4167 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4168 unsigned gs_max_out_vertices
;
4169 uint8_t *num_components
;
4174 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4175 max_stream
= gs
->info
.gs
.max_stream
;
4176 num_components
= gs
->info
.gs
.num_stream_output_components
;
4178 offset
= num_components
[0] * gs_max_out_vertices
;
4180 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4181 radeon_emit(ctx_cs
, offset
);
4182 if (max_stream
>= 1)
4183 offset
+= num_components
[1] * gs_max_out_vertices
;
4184 radeon_emit(ctx_cs
, offset
);
4185 if (max_stream
>= 2)
4186 offset
+= num_components
[2] * gs_max_out_vertices
;
4187 radeon_emit(ctx_cs
, offset
);
4188 if (max_stream
>= 3)
4189 offset
+= num_components
[3] * gs_max_out_vertices
;
4190 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4192 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4193 radeon_emit(ctx_cs
, num_components
[0]);
4194 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4195 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4196 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4198 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4199 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4200 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4201 S_028B90_ENABLE(gs_num_invocations
> 0));
4203 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4204 gs_state
->vgt_esgs_ring_itemsize
);
4206 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4208 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4209 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4210 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4211 radeon_emit(cs
, va
>> 8);
4212 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4214 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4215 radeon_emit(cs
, va
>> 8);
4216 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4219 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4220 radeon_emit(cs
, gs
->config
.rsrc1
);
4221 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4223 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4224 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4226 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4227 radeon_emit(cs
, va
>> 8);
4228 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4229 radeon_emit(cs
, gs
->config
.rsrc1
);
4230 radeon_emit(cs
, gs
->config
.rsrc2
);
4233 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4237 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4238 struct radeon_cmdbuf
*cs
,
4239 struct radv_pipeline
*pipeline
)
4241 struct radv_shader_variant
*gs
;
4243 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4247 if (gs
->info
.is_ngg
)
4248 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4250 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4252 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4253 gs
->info
.gs
.vertices_out
);
4256 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
4258 uint32_t ps_input_cntl
;
4259 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4260 ps_input_cntl
= S_028644_OFFSET(offset
);
4262 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4264 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4265 S_028644_ATTR0_VALID(1);
4268 /* The input is a DEFAULT_VAL constant. */
4269 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4270 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4271 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4272 ps_input_cntl
= S_028644_OFFSET(0x20) |
4273 S_028644_DEFAULT_VAL(offset
);
4275 return ps_input_cntl
;
4279 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4280 struct radv_pipeline
*pipeline
)
4282 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4283 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4284 uint32_t ps_input_cntl
[32];
4286 unsigned ps_offset
= 0;
4288 if (ps
->info
.ps
.prim_id_input
) {
4289 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4290 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4291 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4296 if (ps
->info
.ps
.layer_input
||
4297 ps
->info
.needs_multiview_view_index
) {
4298 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4299 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4300 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4302 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
4306 if (ps
->info
.ps
.has_pcoord
) {
4308 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4309 ps_input_cntl
[ps_offset
] = val
;
4313 if (ps
->info
.ps
.num_input_clips_culls
) {
4316 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4317 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4318 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4322 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4323 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4324 ps
->info
.ps
.num_input_clips_culls
> 4) {
4325 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4330 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4334 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4337 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4338 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4339 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4344 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4345 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4347 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
4352 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4353 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4354 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4360 radv_compute_db_shader_control(const struct radv_device
*device
,
4361 const struct radv_pipeline
*pipeline
,
4362 const struct radv_shader_variant
*ps
)
4365 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4366 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4368 z_order
= V_02880C_LATE_Z
;
4370 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4371 !device
->physical_device
->rad_info
.rbplus_allowed
;
4373 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4374 * but this appears to break Project Cars (DXVK). See
4375 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4377 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4379 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4380 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4381 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4382 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4383 S_02880C_Z_ORDER(z_order
) |
4384 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4385 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4386 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4387 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4388 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4392 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4393 struct radeon_cmdbuf
*cs
,
4394 struct radv_pipeline
*pipeline
)
4396 struct radv_shader_variant
*ps
;
4398 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4400 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4401 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4403 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4404 radeon_emit(cs
, va
>> 8);
4405 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4406 radeon_emit(cs
, ps
->config
.rsrc1
);
4407 radeon_emit(cs
, ps
->config
.rsrc2
);
4409 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4410 radv_compute_db_shader_control(pipeline
->device
,
4413 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4414 ps
->config
.spi_ps_input_ena
);
4416 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4417 ps
->config
.spi_ps_input_addr
);
4419 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4420 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4421 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4423 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4425 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4426 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4427 ps
->info
.ps
.writes_stencil
,
4428 ps
->info
.ps
.writes_sample_mask
));
4430 if (pipeline
->device
->dfsm_allowed
) {
4431 /* optimise this? */
4432 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4433 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4438 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4439 struct radv_pipeline
*pipeline
)
4441 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4442 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4445 unsigned vtx_reuse_depth
= 30;
4446 if (radv_pipeline_has_tess(pipeline
) &&
4447 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4448 vtx_reuse_depth
= 14;
4450 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4451 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4455 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4457 uint32_t stages
= 0;
4458 if (radv_pipeline_has_tess(pipeline
)) {
4459 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4460 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4462 if (radv_pipeline_has_gs(pipeline
))
4463 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4465 else if (radv_pipeline_has_ngg(pipeline
))
4466 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4468 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4469 } else if (radv_pipeline_has_gs(pipeline
)) {
4470 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4472 } else if (radv_pipeline_has_ngg(pipeline
)) {
4473 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4476 if (radv_pipeline_has_ngg(pipeline
)) {
4477 stages
|= S_028B54_PRIMGEN_EN(1);
4478 if (pipeline
->streamout_shader
)
4479 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4480 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4481 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4482 } else if (radv_pipeline_has_gs(pipeline
)) {
4483 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4486 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4487 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4489 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4490 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4492 if (radv_pipeline_has_tess(pipeline
))
4493 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4495 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4496 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4497 if (pipeline
->gs_copy_shader
)
4498 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4499 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4500 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4501 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4502 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4504 if (radv_pipeline_has_ngg(pipeline
))
4507 /* legacy GS only supports Wave64 */
4508 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4509 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4510 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4517 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4519 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4520 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4522 if (!discard_rectangle_info
)
4527 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4528 /* Interpret i as a bitmask, and then set the bit in the mask if
4529 * that combination of rectangles in which the pixel is contained
4530 * should pass the cliprect test. */
4531 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4533 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4537 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4548 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4549 struct radv_pipeline
*pipeline
,
4550 const struct radv_tessellation_state
*tess
)
4552 bool break_wave_at_eoi
= false;
4553 unsigned primgroup_size
;
4554 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4556 if (radv_pipeline_has_tess(pipeline
)) {
4557 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4558 } else if (radv_pipeline_has_gs(pipeline
)) {
4559 const struct gfx9_gs_info
*gs_state
=
4560 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4561 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4562 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4564 primgroup_size
= 128; /* recommended without a GS and tess */
4567 if (radv_pipeline_has_tess(pipeline
)) {
4568 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4569 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4570 break_wave_at_eoi
= true;
4573 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4574 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4575 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4576 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4577 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4581 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4582 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4583 const struct radv_graphics_pipeline_create_info
*extra
,
4584 const struct radv_blend_state
*blend
,
4585 const struct radv_tessellation_state
*tess
,
4586 unsigned prim
, unsigned gs_out
)
4588 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4589 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4592 ctx_cs
->max_dw
= 256;
4593 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4594 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4596 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4597 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4598 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4599 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4600 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4601 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4602 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4603 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4604 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4605 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4606 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4607 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4609 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4610 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4612 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4614 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4615 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4616 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4618 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4620 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4622 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4624 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4626 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4627 assert(cs
->cdw
<= cs
->max_dw
);
4630 static struct radv_ia_multi_vgt_param_helpers
4631 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4632 const struct radv_tessellation_state
*tess
,
4635 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4636 const struct radv_device
*device
= pipeline
->device
;
4638 if (radv_pipeline_has_tess(pipeline
))
4639 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4640 else if (radv_pipeline_has_gs(pipeline
))
4641 ia_multi_vgt_param
.primgroup_size
= 64;
4643 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4645 /* GS requirement. */
4646 ia_multi_vgt_param
.partial_es_wave
= false;
4647 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4648 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4649 ia_multi_vgt_param
.partial_es_wave
= true;
4651 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4652 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4653 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4654 * 4 shader engines. Set 1 to pass the assertion below.
4655 * The other cases are hardware requirements. */
4656 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4657 prim
== V_008958_DI_PT_POLYGON
||
4658 prim
== V_008958_DI_PT_LINELOOP
||
4659 prim
== V_008958_DI_PT_TRIFAN
||
4660 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4661 (pipeline
->graphics
.prim_restart_enable
&&
4662 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4663 (prim
!= V_008958_DI_PT_POINTLIST
&&
4664 prim
!= V_008958_DI_PT_LINESTRIP
))))
4665 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4668 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4669 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4670 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4671 if (radv_pipeline_has_gs(pipeline
) &&
4672 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4673 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4674 if (radv_pipeline_has_tess(pipeline
)) {
4675 /* SWITCH_ON_EOI must be set if PrimID is used. */
4676 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4677 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4678 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4681 ia_multi_vgt_param
.partial_vs_wave
= false;
4682 if (radv_pipeline_has_tess(pipeline
)) {
4683 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4684 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4685 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4686 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4687 radv_pipeline_has_gs(pipeline
))
4688 ia_multi_vgt_param
.partial_vs_wave
= true;
4689 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4690 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4691 if (radv_pipeline_has_gs(pipeline
)) {
4692 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4693 ia_multi_vgt_param
.partial_es_wave
= true;
4695 ia_multi_vgt_param
.partial_vs_wave
= true;
4700 /* Workaround for a VGT hang when strip primitive types are used with
4701 * primitive restart.
4703 if (pipeline
->graphics
.prim_restart_enable
&&
4704 (prim
== V_008958_DI_PT_LINESTRIP
||
4705 prim
== V_008958_DI_PT_TRISTRIP
||
4706 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4707 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4708 ia_multi_vgt_param
.partial_vs_wave
= true;
4711 if (radv_pipeline_has_gs(pipeline
)) {
4712 /* On these chips there is the possibility of a hang if the
4713 * pipeline uses a GS and partial_vs_wave is not set.
4715 * This mostly does not hit 4-SE chips, as those typically set
4716 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4717 * with GS due to another workaround.
4719 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4721 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4722 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4723 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4724 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4725 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4726 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4727 ia_multi_vgt_param
.partial_vs_wave
= true;
4731 ia_multi_vgt_param
.base
=
4732 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4733 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4734 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4735 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4736 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4738 return ia_multi_vgt_param
;
4743 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4744 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4746 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4747 pCreateInfo
->pVertexInputState
;
4748 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4750 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4751 const VkVertexInputAttributeDescription
*desc
=
4752 &vi_info
->pVertexAttributeDescriptions
[i
];
4753 unsigned loc
= desc
->location
;
4754 const struct vk_format_description
*format_desc
;
4756 format_desc
= vk_format_description(desc
->format
);
4758 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4761 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4762 const VkVertexInputBindingDescription
*desc
=
4763 &vi_info
->pVertexBindingDescriptions
[i
];
4765 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4766 pipeline
->num_vertex_bindings
=
4767 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4771 static struct radv_shader_variant
*
4772 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4776 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4777 struct radv_shader_variant
*shader
=
4778 radv_get_shader(pipeline
, i
);
4780 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4788 radv_secure_compile(struct radv_pipeline
*pipeline
,
4789 struct radv_device
*device
,
4790 const struct radv_pipeline_key
*key
,
4791 const VkPipelineShaderStageCreateInfo
**pStages
,
4792 const VkPipelineCreateFlags flags
,
4793 unsigned num_stages
)
4795 uint8_t allowed_pipeline_hashes
[2][20];
4796 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4797 pipeline
->layout
, key
, get_hash_flags(device
));
4799 /* Generate the GC copy hash */
4800 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4801 allowed_pipeline_hashes
[1][0] ^= 1;
4803 uint8_t allowed_hashes
[2][20];
4804 for (unsigned i
= 0; i
< 2; ++i
) {
4805 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4806 allowed_pipeline_hashes
[i
], 20,
4810 /* Do an early exit if all cache entries are already there. */
4811 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4812 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4813 void *copy_entry
= NULL
;
4814 if (may_need_copy_shader
)
4815 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4817 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4821 if(has_all_cache_entries
)
4824 unsigned process
= 0;
4825 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4827 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4828 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4829 device
->sc_state
->secure_compile_thread_counter
++;
4830 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4831 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4832 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4837 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4840 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4843 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4844 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4846 /* Fork a copy of the slim untainted secure compile process */
4847 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4848 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4850 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4851 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4852 return VK_ERROR_DEVICE_LOST
;
4854 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4855 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4857 /* Write pipeline / shader module out to secure process via pipe */
4858 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4859 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4861 /* Write pipeline layout out to secure process */
4862 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4863 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4864 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4865 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4866 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4867 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4870 /* Write pipeline key out to secure process */
4871 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4873 /* Write pipeline create flags out to secure process */
4874 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4876 /* Write stage and shader information out to secure process */
4877 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4878 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4882 /* Write stage out to secure process */
4883 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4884 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4886 /* Write entry point name out to secure process */
4887 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4888 write(fd_secure_input
, &name_size
, sizeof(size_t));
4889 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4891 /* Write shader module out to secure process */
4892 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4893 assert(!module
->nir
);
4894 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4895 write(fd_secure_input
, &module_size
, sizeof(size_t));
4896 write(fd_secure_input
, module
, module_size
);
4898 /* Write specialization info out to secure process */
4899 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4900 bool has_spec_info
= specInfo
? true : false;
4901 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4903 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4904 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4906 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4907 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4908 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4912 /* Read the data returned from the secure process */
4913 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4914 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4915 return VK_ERROR_DEVICE_LOST
;
4917 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4918 assert(device
->physical_device
->disk_cache
);
4920 uint8_t disk_sha1
[20];
4921 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4922 return VK_ERROR_DEVICE_LOST
;
4924 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4925 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4926 return VK_ERROR_DEVICE_LOST
;
4928 uint32_t entry_size
;
4929 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4930 return VK_ERROR_DEVICE_LOST
;
4932 struct cache_entry
*entry
= malloc(entry_size
);
4933 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4934 return VK_ERROR_DEVICE_LOST
;
4936 disk_cache_put(device
->physical_device
->disk_cache
,
4937 disk_sha1
, entry
, entry_size
,
4941 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4942 uint8_t disk_sha1
[20];
4943 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4944 return VK_ERROR_DEVICE_LOST
;
4946 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4947 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4948 return VK_ERROR_DEVICE_LOST
;
4951 struct cache_entry
*entry
= (struct cache_entry
*)
4952 disk_cache_get(device
->physical_device
->disk_cache
,
4955 uint8_t found
= entry
? 1 : 0;
4956 write(fd_secure_input
, &found
, sizeof(uint8_t));
4959 write(fd_secure_input
, &size
, sizeof(size_t));
4960 write(fd_secure_input
, entry
, size
);
4967 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
4968 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4970 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4971 device
->sc_state
->secure_compile_thread_counter
--;
4972 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
4973 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4979 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4980 struct radv_device
*device
,
4981 struct radv_pipeline_cache
*cache
,
4982 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4983 const struct radv_graphics_pipeline_create_info
*extra
)
4986 bool has_view_index
= false;
4988 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4989 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4990 if (subpass
->view_mask
)
4991 has_view_index
= true;
4993 pipeline
->device
= device
;
4994 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4995 assert(pipeline
->layout
);
4997 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4999 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5000 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5001 radv_init_feedback(creation_feedback
);
5003 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5005 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5006 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5007 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5008 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5009 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5010 if(creation_feedback
)
5011 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5014 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5015 if (radv_device_use_secure_compile(device
->instance
)) {
5016 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5018 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5021 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5022 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5024 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5026 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5028 if (radv_pipeline_has_gs(pipeline
)) {
5029 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5030 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5031 } else if (radv_pipeline_has_tess(pipeline
)) {
5032 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5033 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5035 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5036 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5038 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5040 if (extra
&& extra
->use_rectlist
) {
5041 prim
= V_008958_DI_PT_RECTLIST
;
5042 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5043 pipeline
->graphics
.can_use_guardband
= true;
5044 if (radv_pipeline_has_ngg(pipeline
))
5045 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5047 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5048 /* prim vertex count will need TESS changes */
5049 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5051 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5053 /* Ensure that some export memory is always allocated, for two reasons:
5055 * 1) Correctness: The hardware ignores the EXEC mask if no export
5056 * memory is allocated, so KILL and alpha test do not work correctly
5058 * 2) Performance: Every shader needs at least a NULL export, even when
5059 * it writes no color/depth output. The NULL export instruction
5060 * stalls without this setting.
5062 * Don't add this to CB_SHADER_MASK.
5064 * GFX10 supports pixel shaders without exports by setting both the
5065 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5066 * instructions if any are present.
5068 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5069 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5070 ps
->info
.ps
.can_discard
) &&
5071 !blend
.spi_shader_col_format
) {
5072 if (!ps
->info
.ps
.writes_z
&&
5073 !ps
->info
.ps
.writes_stencil
&&
5074 !ps
->info
.ps
.writes_sample_mask
)
5075 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5078 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5079 if (pipeline
->shaders
[i
]) {
5080 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5084 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5085 struct radv_shader_variant
*gs
=
5086 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5088 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5091 struct radv_tessellation_state tess
= {0};
5092 if (radv_pipeline_has_tess(pipeline
)) {
5093 if (prim
== V_008958_DI_PT_PATCH
) {
5094 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5095 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5097 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5100 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5102 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5104 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5105 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5107 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5108 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5109 if (loc
->sgpr_idx
!= -1) {
5110 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5111 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5112 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5113 pipeline
->graphics
.vtx_emit_num
= 3;
5115 pipeline
->graphics
.vtx_emit_num
= 2;
5118 /* Find the last vertex shader stage that eventually uses streamout. */
5119 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5121 result
= radv_pipeline_scratch_init(device
, pipeline
);
5122 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5128 radv_graphics_pipeline_create(
5130 VkPipelineCache _cache
,
5131 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5132 const struct radv_graphics_pipeline_create_info
*extra
,
5133 const VkAllocationCallbacks
*pAllocator
,
5134 VkPipeline
*pPipeline
)
5136 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5137 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5138 struct radv_pipeline
*pipeline
;
5141 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5142 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5143 if (pipeline
== NULL
)
5144 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5146 result
= radv_pipeline_init(pipeline
, device
, cache
,
5147 pCreateInfo
, extra
);
5148 if (result
!= VK_SUCCESS
) {
5149 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5153 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5158 VkResult
radv_CreateGraphicsPipelines(
5160 VkPipelineCache pipelineCache
,
5162 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5163 const VkAllocationCallbacks
* pAllocator
,
5164 VkPipeline
* pPipelines
)
5166 VkResult result
= VK_SUCCESS
;
5169 for (; i
< count
; i
++) {
5171 r
= radv_graphics_pipeline_create(_device
,
5174 NULL
, pAllocator
, &pPipelines
[i
]);
5175 if (r
!= VK_SUCCESS
) {
5177 pPipelines
[i
] = VK_NULL_HANDLE
;
5186 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5188 struct radv_shader_variant
*compute_shader
;
5189 struct radv_device
*device
= pipeline
->device
;
5190 unsigned threads_per_threadgroup
;
5191 unsigned threadgroups_per_cu
= 1;
5192 unsigned waves_per_threadgroup
;
5193 unsigned max_waves_per_sh
= 0;
5196 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5197 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5199 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5200 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5202 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5203 radeon_emit(&pipeline
->cs
, va
>> 8);
5204 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5206 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5207 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5208 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5209 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5210 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5213 /* Calculate best compute resource limits. */
5214 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5215 compute_shader
->info
.cs
.block_size
[1] *
5216 compute_shader
->info
.cs
.block_size
[2];
5217 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5218 compute_shader
->info
.wave_size
);
5220 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5221 waves_per_threadgroup
== 1)
5222 threadgroups_per_cu
= 2;
5224 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5225 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5226 waves_per_threadgroup
,
5228 threadgroups_per_cu
));
5230 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5231 radeon_emit(&pipeline
->cs
,
5232 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5233 radeon_emit(&pipeline
->cs
,
5234 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5235 radeon_emit(&pipeline
->cs
,
5236 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5238 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5241 static struct radv_pipeline_key
5242 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5243 const VkComputePipelineCreateInfo
*pCreateInfo
)
5245 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5246 struct radv_pipeline_key key
;
5247 memset(&key
, 0, sizeof(key
));
5249 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5250 key
.optimisations_disabled
= 1;
5252 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5253 vk_find_struct_const(stage
->pNext
,
5254 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5256 if (subgroup_size
) {
5257 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5258 subgroup_size
->requiredSubgroupSize
== 64);
5259 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5265 static VkResult
radv_compute_pipeline_create(
5267 VkPipelineCache _cache
,
5268 const VkComputePipelineCreateInfo
* pCreateInfo
,
5269 const VkAllocationCallbacks
* pAllocator
,
5270 VkPipeline
* pPipeline
)
5272 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5273 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5274 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5275 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5276 struct radv_pipeline
*pipeline
;
5279 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5280 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5281 if (pipeline
== NULL
)
5282 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5284 pipeline
->device
= device
;
5285 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5286 assert(pipeline
->layout
);
5288 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5289 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5290 radv_init_feedback(creation_feedback
);
5292 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5293 if (creation_feedback
)
5294 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5296 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5298 struct radv_pipeline_key key
=
5299 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5301 if (radv_device_use_secure_compile(device
->instance
)) {
5302 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5303 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5307 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5310 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5311 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5312 result
= radv_pipeline_scratch_init(device
, pipeline
);
5313 if (result
!= VK_SUCCESS
) {
5314 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5318 radv_compute_generate_pm4(pipeline
);
5320 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5325 VkResult
radv_CreateComputePipelines(
5327 VkPipelineCache pipelineCache
,
5329 const VkComputePipelineCreateInfo
* pCreateInfos
,
5330 const VkAllocationCallbacks
* pAllocator
,
5331 VkPipeline
* pPipelines
)
5333 VkResult result
= VK_SUCCESS
;
5336 for (; i
< count
; i
++) {
5338 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5340 pAllocator
, &pPipelines
[i
]);
5341 if (r
!= VK_SUCCESS
) {
5343 pPipelines
[i
] = VK_NULL_HANDLE
;
5351 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5354 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5355 if (!pipeline
->shaders
[i
])
5358 if (i
== MESA_SHADER_GEOMETRY
&&
5359 !radv_pipeline_has_ngg(pipeline
)) {
5369 static struct radv_shader_variant
*
5370 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5372 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5373 if (!pipeline
->shaders
[i
])
5377 return pipeline
->shaders
[i
];
5382 if (i
== MESA_SHADER_GEOMETRY
&&
5383 !radv_pipeline_has_ngg(pipeline
)) {
5386 return pipeline
->gs_copy_shader
;
5396 /* Basically strlcpy (which does not exist on linux) specialized for
5398 static void desc_copy(char *desc
, const char *src
) {
5399 int len
= strlen(src
);
5400 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5401 memcpy(desc
, src
, len
);
5402 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5405 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5407 const VkPipelineInfoKHR
* pPipelineInfo
,
5408 uint32_t* pExecutableCount
,
5409 VkPipelineExecutablePropertiesKHR
* pProperties
)
5411 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5412 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5415 *pExecutableCount
= total_count
;
5419 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5420 for (unsigned i
= 0, executable_idx
= 0;
5421 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5422 if (!pipeline
->shaders
[i
])
5424 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5425 const char *name
= NULL
;
5426 const char *description
= NULL
;
5428 case MESA_SHADER_VERTEX
:
5429 name
= "Vertex Shader";
5430 description
= "Vulkan Vertex Shader";
5432 case MESA_SHADER_TESS_CTRL
:
5433 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5434 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5435 name
= "Vertex + Tessellation Control Shaders";
5436 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5438 name
= "Tessellation Control Shader";
5439 description
= "Vulkan Tessellation Control Shader";
5442 case MESA_SHADER_TESS_EVAL
:
5443 name
= "Tessellation Evaluation Shader";
5444 description
= "Vulkan Tessellation Evaluation Shader";
5446 case MESA_SHADER_GEOMETRY
:
5447 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5448 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5449 name
= "Tessellation Evaluation + Geometry Shaders";
5450 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5451 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5452 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5453 name
= "Vertex + Geometry Shader";
5454 description
= "Combined Vulkan Vertex and Geometry Shaders";
5456 name
= "Geometry Shader";
5457 description
= "Vulkan Geometry Shader";
5460 case MESA_SHADER_FRAGMENT
:
5461 name
= "Fragment Shader";
5462 description
= "Vulkan Fragment Shader";
5464 case MESA_SHADER_COMPUTE
:
5465 name
= "Compute Shader";
5466 description
= "Vulkan Compute Shader";
5470 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5471 desc_copy(pProperties
[executable_idx
].name
, name
);
5472 desc_copy(pProperties
[executable_idx
].description
, description
);
5475 if (i
== MESA_SHADER_GEOMETRY
&&
5476 !radv_pipeline_has_ngg(pipeline
)) {
5477 assert(pipeline
->gs_copy_shader
);
5478 if (executable_idx
>= count
)
5481 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5482 pProperties
[executable_idx
].subgroupSize
= 64;
5483 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5484 desc_copy(pProperties
[executable_idx
].description
,
5485 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5491 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5492 *pExecutableCount
= count
;
5496 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5498 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5499 uint32_t* pStatisticCount
,
5500 VkPipelineExecutableStatisticKHR
* pStatistics
)
5502 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5503 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5504 gl_shader_stage stage
;
5505 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5507 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5508 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5509 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5511 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5512 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5513 VkResult result
= VK_SUCCESS
;
5516 desc_copy(s
->name
, "SGPRs");
5517 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5518 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5519 s
->value
.u64
= shader
->config
.num_sgprs
;
5524 desc_copy(s
->name
, "VGPRs");
5525 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5526 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5527 s
->value
.u64
= shader
->config
.num_vgprs
;
5532 desc_copy(s
->name
, "Spilled SGPRs");
5533 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5534 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5535 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5540 desc_copy(s
->name
, "Spilled VGPRs");
5541 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5542 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5543 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5548 desc_copy(s
->name
, "PrivMem VGPRs");
5549 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5550 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5551 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5556 desc_copy(s
->name
, "Code size");
5557 desc_copy(s
->description
, "Code size in bytes");
5558 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5559 s
->value
.u64
= shader
->exec_size
;
5564 desc_copy(s
->name
, "LDS size");
5565 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5566 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5567 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5572 desc_copy(s
->name
, "Scratch size");
5573 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5574 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5575 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5580 desc_copy(s
->name
, "Subgroups per SIMD");
5581 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5582 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5583 s
->value
.u64
= max_waves
;
5588 *pStatisticCount
= s
- pStatistics
;
5590 *pStatisticCount
= end
- pStatistics
;
5591 result
= VK_INCOMPLETE
;
5593 *pStatisticCount
= s
- pStatistics
;
5599 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5601 size_t total_size
= strlen(src
) + 1;
5604 *data_size
= total_size
;
5608 size_t size
= MIN2(total_size
, *data_size
);
5610 memcpy(data
, src
, size
);
5612 *((char*)data
+ size
- 1) = 0;
5613 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5616 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5618 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5619 uint32_t* pInternalRepresentationCount
,
5620 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5622 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5623 gl_shader_stage stage
;
5624 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5626 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5627 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5628 VkResult result
= VK_SUCCESS
;
5632 desc_copy(p
->name
, "NIR Shader(s)");
5633 desc_copy(p
->description
, "The optimized NIR shader(s)");
5634 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5635 result
= VK_INCOMPLETE
;
5642 if (shader
->aco_used
) {
5643 desc_copy(p
->name
, "ACO IR");
5644 desc_copy(p
->description
, "The ACO IR after some optimizations");
5646 desc_copy(p
->name
, "LLVM IR");
5647 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5649 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5650 result
= VK_INCOMPLETE
;
5657 desc_copy(p
->name
, "Assembly");
5658 desc_copy(p
->description
, "Final Assembly");
5659 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5660 result
= VK_INCOMPLETE
;
5664 if (!pInternalRepresentations
)
5665 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5667 result
= VK_INCOMPLETE
;
5668 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5670 *pInternalRepresentationCount
= p
- pInternalRepresentations
;