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amd: move r600d_common.h into r600g
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "vk_util.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40
41 #include "sid.h"
42 #include "gfx9d.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49
50 static void
51 radv_pipeline_destroy(struct radv_device *device,
52 struct radv_pipeline *pipeline,
53 const VkAllocationCallbacks* allocator)
54 {
55 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
56 if (pipeline->shaders[i])
57 radv_shader_variant_destroy(device, pipeline->shaders[i]);
58
59 if (pipeline->gs_copy_shader)
60 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
61
62 vk_free2(&device->alloc, allocator, pipeline);
63 }
64
65 void radv_DestroyPipeline(
66 VkDevice _device,
67 VkPipeline _pipeline,
68 const VkAllocationCallbacks* pAllocator)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
72
73 if (!_pipeline)
74 return;
75
76 radv_pipeline_destroy(device, pipeline, pAllocator);
77 }
78
79 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
80 {
81 int i;
82
83 for (i = 0; i < MESA_SHADER_STAGES; i++) {
84 if (!pipeline->shaders[i])
85 continue;
86
87 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
88 }
89 }
90
91 static struct radv_shader_variant *
92 radv_pipeline_compile(struct radv_pipeline *pipeline,
93 struct radv_pipeline_cache *cache,
94 struct radv_shader_module *module,
95 const char *entrypoint,
96 gl_shader_stage stage,
97 const VkSpecializationInfo *spec_info,
98 struct radv_pipeline_layout *layout,
99 const struct ac_shader_variant_key *key)
100 {
101 unsigned char sha1[20];
102 unsigned char gs_copy_sha1[20];
103 struct radv_shader_variant *variant;
104 nir_shader *nir;
105 void *code = NULL;
106 unsigned code_size = 0;
107
108 if (module->nir)
109 _mesa_sha1_compute(module->nir->info.name,
110 strlen(module->nir->info.name),
111 module->sha1);
112
113 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
114 if (stage == MESA_SHADER_GEOMETRY)
115 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
116 layout, key, 1);
117
118 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
119 cache,
120 sha1);
121
122 if (stage == MESA_SHADER_GEOMETRY) {
123 pipeline->gs_copy_shader =
124 radv_create_shader_variant_from_pipeline_cache(
125 pipeline->device,
126 cache,
127 gs_copy_sha1);
128 }
129
130 if (variant &&
131 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
132 return variant;
133
134 nir = radv_shader_compile_to_nir(pipeline->device,
135 module, entrypoint, stage,
136 spec_info);
137 if (nir == NULL)
138 return NULL;
139
140 if (!variant) {
141 variant = radv_shader_variant_create(pipeline->device, module, nir,
142 layout, key, &code,
143 &code_size);
144 }
145
146 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
147 void *gs_copy_code = NULL;
148 unsigned gs_copy_code_size = 0;
149 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
150 pipeline->device, nir, &gs_copy_code,
151 &gs_copy_code_size, key->has_multiview_view_index);
152
153 if (pipeline->gs_copy_shader) {
154 pipeline->gs_copy_shader =
155 radv_pipeline_cache_insert_shader(pipeline->device,
156 cache,
157 gs_copy_sha1,
158 pipeline->gs_copy_shader,
159 gs_copy_code,
160 gs_copy_code_size);
161 }
162
163 free(gs_copy_code);
164 }
165 if (!module->nir && !pipeline->device->trace_bo)
166 ralloc_free(nir);
167
168 if (variant)
169 variant = radv_pipeline_cache_insert_shader(pipeline->device,
170 cache, sha1,
171 variant, code,
172 code_size);
173
174 if (code)
175 free(code);
176 return variant;
177 }
178
179 static struct ac_shader_variant_key
180 radv_compute_tes_key(bool as_es, bool export_prim_id)
181 {
182 struct ac_shader_variant_key key;
183 memset(&key, 0, sizeof(key));
184 key.tes.as_es = as_es;
185 /* export prim id only happens when no geom shader */
186 if (!as_es)
187 key.tes.export_prim_id = export_prim_id;
188 return key;
189 }
190
191 static struct ac_shader_variant_key
192 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
193 {
194 struct ac_shader_variant_key key;
195 memset(&key, 0, sizeof(key));
196 key.tcs.primitive_mode = primitive_mode;
197 key.tcs.input_vertices = input_vertices;
198 return key;
199 }
200
201 static void
202 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
203 struct radv_pipeline_cache *cache,
204 struct radv_shader_module *tcs_module,
205 struct radv_shader_module *tes_module,
206 const char *tcs_entrypoint,
207 const char *tes_entrypoint,
208 const VkSpecializationInfo *tcs_spec_info,
209 const VkSpecializationInfo *tes_spec_info,
210 struct radv_pipeline_layout *layout,
211 unsigned input_vertices,
212 bool has_view_index)
213 {
214 unsigned char tcs_sha1[20], tes_sha1[20];
215 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
216 nir_shader *tes_nir, *tcs_nir;
217 void *tes_code = NULL, *tcs_code = NULL;
218 unsigned tes_code_size = 0, tcs_code_size = 0;
219 struct ac_shader_variant_key tes_key;
220 struct ac_shader_variant_key tcs_key;
221
222 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
223 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
224 tes_key.has_multiview_view_index = has_view_index;
225 if (tes_module->nir)
226 _mesa_sha1_compute(tes_module->nir->info.name,
227 strlen(tes_module->nir->info.name),
228 tes_module->sha1);
229 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
230
231 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
232 cache,
233 tes_sha1);
234
235 if (tes_variant) {
236 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
237
238 if (tcs_module->nir)
239 _mesa_sha1_compute(tcs_module->nir->info.name,
240 strlen(tcs_module->nir->info.name),
241 tcs_module->sha1);
242
243 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
244
245 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
246 cache,
247 tcs_sha1);
248 }
249
250 if (tcs_variant && tes_variant) {
251 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
252 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
253 return;
254 }
255
256 tes_nir = radv_shader_compile_to_nir(pipeline->device,
257 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
258 tes_spec_info);
259 if (tes_nir == NULL)
260 return;
261
262 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
263 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
264 tcs_spec_info);
265 if (tcs_nir == NULL)
266 return;
267
268 nir_lower_tes_patch_vertices(tes_nir,
269 tcs_nir->info.tess.tcs_vertices_out);
270
271 tes_variant = radv_shader_variant_create(pipeline->device, tes_module, tes_nir,
272 layout, &tes_key, &tes_code,
273 &tes_code_size);
274
275 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
276 if (tcs_module->nir)
277 _mesa_sha1_compute(tcs_module->nir->info.name,
278 strlen(tcs_module->nir->info.name),
279 tcs_module->sha1);
280
281 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
282
283 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_module, tcs_nir,
284 layout, &tcs_key, &tcs_code,
285 &tcs_code_size);
286
287 if (!tes_module->nir && !pipeline->device->trace_bo)
288 ralloc_free(tes_nir);
289
290 if (!tcs_module->nir && !pipeline->device->trace_bo)
291 ralloc_free(tcs_nir);
292
293 if (tes_variant)
294 tes_variant = radv_pipeline_cache_insert_shader(pipeline->device, cache, tes_sha1, tes_variant,
295 tes_code, tes_code_size);
296
297 if (tcs_variant)
298 tcs_variant = radv_pipeline_cache_insert_shader(pipeline->device, cache, tcs_sha1, tcs_variant,
299 tcs_code, tcs_code_size);
300
301 if (tes_code)
302 free(tes_code);
303 if (tcs_code)
304 free(tcs_code);
305 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
306 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
307 return;
308 }
309
310 static VkResult
311 radv_pipeline_scratch_init(struct radv_device *device,
312 struct radv_pipeline *pipeline)
313 {
314 unsigned scratch_bytes_per_wave = 0;
315 unsigned max_waves = 0;
316 unsigned min_waves = 1;
317
318 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
319 if (pipeline->shaders[i]) {
320 unsigned max_stage_waves = device->scratch_waves;
321
322 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
323 pipeline->shaders[i]->config.scratch_bytes_per_wave);
324
325 max_stage_waves = MIN2(max_stage_waves,
326 4 * device->physical_device->rad_info.num_good_compute_units *
327 (256 / pipeline->shaders[i]->config.num_vgprs));
328 max_waves = MAX2(max_waves, max_stage_waves);
329 }
330 }
331
332 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
333 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
334 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
335 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
336 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
337 }
338
339 if (scratch_bytes_per_wave)
340 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
341
342 if (scratch_bytes_per_wave && max_waves < min_waves) {
343 /* Not really true at this moment, but will be true on first
344 * execution. Avoid having hanging shaders. */
345 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
346 }
347 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
348 pipeline->max_waves = max_waves;
349 return VK_SUCCESS;
350 }
351
352 static uint32_t si_translate_blend_function(VkBlendOp op)
353 {
354 switch (op) {
355 case VK_BLEND_OP_ADD:
356 return V_028780_COMB_DST_PLUS_SRC;
357 case VK_BLEND_OP_SUBTRACT:
358 return V_028780_COMB_SRC_MINUS_DST;
359 case VK_BLEND_OP_REVERSE_SUBTRACT:
360 return V_028780_COMB_DST_MINUS_SRC;
361 case VK_BLEND_OP_MIN:
362 return V_028780_COMB_MIN_DST_SRC;
363 case VK_BLEND_OP_MAX:
364 return V_028780_COMB_MAX_DST_SRC;
365 default:
366 return 0;
367 }
368 }
369
370 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
371 {
372 switch (factor) {
373 case VK_BLEND_FACTOR_ZERO:
374 return V_028780_BLEND_ZERO;
375 case VK_BLEND_FACTOR_ONE:
376 return V_028780_BLEND_ONE;
377 case VK_BLEND_FACTOR_SRC_COLOR:
378 return V_028780_BLEND_SRC_COLOR;
379 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
380 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
381 case VK_BLEND_FACTOR_DST_COLOR:
382 return V_028780_BLEND_DST_COLOR;
383 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
384 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
385 case VK_BLEND_FACTOR_SRC_ALPHA:
386 return V_028780_BLEND_SRC_ALPHA;
387 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
388 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
389 case VK_BLEND_FACTOR_DST_ALPHA:
390 return V_028780_BLEND_DST_ALPHA;
391 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
392 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
393 case VK_BLEND_FACTOR_CONSTANT_COLOR:
394 return V_028780_BLEND_CONSTANT_COLOR;
395 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
396 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
397 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
398 return V_028780_BLEND_CONSTANT_ALPHA;
399 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
400 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
401 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
402 return V_028780_BLEND_SRC_ALPHA_SATURATE;
403 case VK_BLEND_FACTOR_SRC1_COLOR:
404 return V_028780_BLEND_SRC1_COLOR;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
406 return V_028780_BLEND_INV_SRC1_COLOR;
407 case VK_BLEND_FACTOR_SRC1_ALPHA:
408 return V_028780_BLEND_SRC1_ALPHA;
409 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
410 return V_028780_BLEND_INV_SRC1_ALPHA;
411 default:
412 return 0;
413 }
414 }
415
416 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
417 {
418 switch (op) {
419 case VK_BLEND_OP_ADD:
420 return V_028760_OPT_COMB_ADD;
421 case VK_BLEND_OP_SUBTRACT:
422 return V_028760_OPT_COMB_SUBTRACT;
423 case VK_BLEND_OP_REVERSE_SUBTRACT:
424 return V_028760_OPT_COMB_REVSUBTRACT;
425 case VK_BLEND_OP_MIN:
426 return V_028760_OPT_COMB_MIN;
427 case VK_BLEND_OP_MAX:
428 return V_028760_OPT_COMB_MAX;
429 default:
430 return V_028760_OPT_COMB_BLEND_DISABLED;
431 }
432 }
433
434 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
435 {
436 switch (factor) {
437 case VK_BLEND_FACTOR_ZERO:
438 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
439 case VK_BLEND_FACTOR_ONE:
440 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
441 case VK_BLEND_FACTOR_SRC_COLOR:
442 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
443 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
444 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
445 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
446 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
447 case VK_BLEND_FACTOR_SRC_ALPHA:
448 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
450 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
451 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
452 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
453 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
454 default:
455 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
456 }
457 }
458
459 /**
460 * Get rid of DST in the blend factors by commuting the operands:
461 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
462 */
463 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
464 unsigned *dst_factor, unsigned expected_dst,
465 unsigned replacement_src)
466 {
467 if (*src_factor == expected_dst &&
468 *dst_factor == VK_BLEND_FACTOR_ZERO) {
469 *src_factor = VK_BLEND_FACTOR_ZERO;
470 *dst_factor = replacement_src;
471
472 /* Commuting the operands requires reversing subtractions. */
473 if (*func == VK_BLEND_OP_SUBTRACT)
474 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
475 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
476 *func = VK_BLEND_OP_SUBTRACT;
477 }
478 }
479
480 static bool si_blend_factor_uses_dst(unsigned factor)
481 {
482 return factor == VK_BLEND_FACTOR_DST_COLOR ||
483 factor == VK_BLEND_FACTOR_DST_ALPHA ||
484 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
485 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
486 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
487 }
488
489 static bool is_dual_src(VkBlendFactor factor)
490 {
491 switch (factor) {
492 case VK_BLEND_FACTOR_SRC1_COLOR:
493 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
494 case VK_BLEND_FACTOR_SRC1_ALPHA:
495 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
496 return true;
497 default:
498 return false;
499 }
500 }
501
502 static unsigned si_choose_spi_color_format(VkFormat vk_format,
503 bool blend_enable,
504 bool blend_need_alpha)
505 {
506 const struct vk_format_description *desc = vk_format_description(vk_format);
507 unsigned format, ntype, swap;
508
509 /* Alpha is needed for alpha-to-coverage.
510 * Blending may be with or without alpha.
511 */
512 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
513 unsigned alpha = 0; /* exports alpha, but may not support blending */
514 unsigned blend = 0; /* supports blending, but may not export alpha */
515 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
516
517 format = radv_translate_colorformat(vk_format);
518 ntype = radv_translate_color_numformat(vk_format, desc,
519 vk_format_get_first_non_void_channel(vk_format));
520 swap = radv_translate_colorswap(vk_format, false);
521
522 /* Choose the SPI color formats. These are required values for Stoney/RB+.
523 * Other chips have multiple choices, though they are not necessarily better.
524 */
525 switch (format) {
526 case V_028C70_COLOR_5_6_5:
527 case V_028C70_COLOR_1_5_5_5:
528 case V_028C70_COLOR_5_5_5_1:
529 case V_028C70_COLOR_4_4_4_4:
530 case V_028C70_COLOR_10_11_11:
531 case V_028C70_COLOR_11_11_10:
532 case V_028C70_COLOR_8:
533 case V_028C70_COLOR_8_8:
534 case V_028C70_COLOR_8_8_8_8:
535 case V_028C70_COLOR_10_10_10_2:
536 case V_028C70_COLOR_2_10_10_10:
537 if (ntype == V_028C70_NUMBER_UINT)
538 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
539 else if (ntype == V_028C70_NUMBER_SINT)
540 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
541 else
542 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
543 break;
544
545 case V_028C70_COLOR_16:
546 case V_028C70_COLOR_16_16:
547 case V_028C70_COLOR_16_16_16_16:
548 if (ntype == V_028C70_NUMBER_UNORM ||
549 ntype == V_028C70_NUMBER_SNORM) {
550 /* UNORM16 and SNORM16 don't support blending */
551 if (ntype == V_028C70_NUMBER_UNORM)
552 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
553 else
554 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
555
556 /* Use 32 bits per channel for blending. */
557 if (format == V_028C70_COLOR_16) {
558 if (swap == V_028C70_SWAP_STD) { /* R */
559 blend = V_028714_SPI_SHADER_32_R;
560 blend_alpha = V_028714_SPI_SHADER_32_AR;
561 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
562 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
563 else
564 assert(0);
565 } else if (format == V_028C70_COLOR_16_16) {
566 if (swap == V_028C70_SWAP_STD) { /* RG */
567 blend = V_028714_SPI_SHADER_32_GR;
568 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
569 } else if (swap == V_028C70_SWAP_ALT) /* RA */
570 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
571 else
572 assert(0);
573 } else /* 16_16_16_16 */
574 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
575 } else if (ntype == V_028C70_NUMBER_UINT)
576 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
577 else if (ntype == V_028C70_NUMBER_SINT)
578 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
579 else if (ntype == V_028C70_NUMBER_FLOAT)
580 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
581 else
582 assert(0);
583 break;
584
585 case V_028C70_COLOR_32:
586 if (swap == V_028C70_SWAP_STD) { /* R */
587 blend = normal = V_028714_SPI_SHADER_32_R;
588 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
589 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
590 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
591 else
592 assert(0);
593 break;
594
595 case V_028C70_COLOR_32_32:
596 if (swap == V_028C70_SWAP_STD) { /* RG */
597 blend = normal = V_028714_SPI_SHADER_32_GR;
598 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
599 } else if (swap == V_028C70_SWAP_ALT) /* RA */
600 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
601 else
602 assert(0);
603 break;
604
605 case V_028C70_COLOR_32_32_32_32:
606 case V_028C70_COLOR_8_24:
607 case V_028C70_COLOR_24_8:
608 case V_028C70_COLOR_X24_8_32_FLOAT:
609 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
610 break;
611
612 default:
613 unreachable("unhandled blend format");
614 }
615
616 if (blend_enable && blend_need_alpha)
617 return blend_alpha;
618 else if(blend_need_alpha)
619 return alpha;
620 else if(blend_enable)
621 return blend;
622 else
623 return normal;
624 }
625
626 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
627 {
628 unsigned i, cb_shader_mask = 0;
629
630 for (i = 0; i < 8; i++) {
631 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
632 case V_028714_SPI_SHADER_ZERO:
633 break;
634 case V_028714_SPI_SHADER_32_R:
635 cb_shader_mask |= 0x1 << (i * 4);
636 break;
637 case V_028714_SPI_SHADER_32_GR:
638 cb_shader_mask |= 0x3 << (i * 4);
639 break;
640 case V_028714_SPI_SHADER_32_AR:
641 cb_shader_mask |= 0x9 << (i * 4);
642 break;
643 case V_028714_SPI_SHADER_FP16_ABGR:
644 case V_028714_SPI_SHADER_UNORM16_ABGR:
645 case V_028714_SPI_SHADER_SNORM16_ABGR:
646 case V_028714_SPI_SHADER_UINT16_ABGR:
647 case V_028714_SPI_SHADER_SINT16_ABGR:
648 case V_028714_SPI_SHADER_32_ABGR:
649 cb_shader_mask |= 0xf << (i * 4);
650 break;
651 default:
652 assert(0);
653 }
654 }
655 return cb_shader_mask;
656 }
657
658 static void
659 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
660 const VkGraphicsPipelineCreateInfo *pCreateInfo,
661 uint32_t blend_enable,
662 uint32_t blend_need_alpha,
663 bool single_cb_enable,
664 bool blend_mrt0_is_dual_src)
665 {
666 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
667 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
668 struct radv_blend_state *blend = &pipeline->graphics.blend;
669 unsigned col_format = 0;
670
671 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
672 unsigned cf;
673
674 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
675 cf = V_028714_SPI_SHADER_ZERO;
676 } else {
677 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
678
679 cf = si_choose_spi_color_format(attachment->format,
680 blend_enable & (1 << i),
681 blend_need_alpha & (1 << i));
682 }
683
684 col_format |= cf << (4 * i);
685 }
686
687 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
688
689 if (blend_mrt0_is_dual_src)
690 col_format |= (col_format & 0xf) << 4;
691 blend->spi_shader_col_format = col_format;
692 }
693
694 static bool
695 format_is_int8(VkFormat format)
696 {
697 const struct vk_format_description *desc = vk_format_description(format);
698 int channel = vk_format_get_first_non_void_channel(format);
699
700 return channel >= 0 && desc->channel[channel].pure_integer &&
701 desc->channel[channel].size == 8;
702 }
703
704 static bool
705 format_is_int10(VkFormat format)
706 {
707 const struct vk_format_description *desc = vk_format_description(format);
708
709 if (desc->nr_channels != 4)
710 return false;
711 for (unsigned i = 0; i < 4; i++) {
712 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
713 return true;
714 }
715 return false;
716 }
717
718 unsigned radv_format_meta_fs_key(VkFormat format)
719 {
720 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
721 bool is_int8 = format_is_int8(format);
722 bool is_int10 = format_is_int10(format);
723
724 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
725 }
726
727 static void
728 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
729 unsigned *is_int8, unsigned *is_int10)
730 {
731 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
732 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
733 *is_int8 = 0;
734 *is_int10 = 0;
735
736 for (unsigned i = 0; i < subpass->color_count; ++i) {
737 struct radv_render_pass_attachment *attachment;
738
739 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
740 continue;
741
742 attachment = pass->attachments + subpass->color_attachments[i].attachment;
743
744 if (format_is_int8(attachment->format))
745 *is_int8 |= 1 << i;
746 if (format_is_int10(attachment->format))
747 *is_int10 |= 1 << i;
748 }
749 }
750
751 static void
752 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
753 const VkGraphicsPipelineCreateInfo *pCreateInfo,
754 const struct radv_graphics_pipeline_create_info *extra)
755 {
756 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
757 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
758 struct radv_blend_state *blend = &pipeline->graphics.blend;
759 unsigned mode = V_028808_CB_NORMAL;
760 uint32_t blend_enable = 0, blend_need_alpha = 0;
761 bool blend_mrt0_is_dual_src = false;
762 int i;
763 bool single_cb_enable = false;
764
765 if (!vkblend)
766 return;
767
768 if (extra && extra->custom_blend_mode) {
769 single_cb_enable = true;
770 mode = extra->custom_blend_mode;
771 }
772 blend->cb_color_control = 0;
773 if (vkblend->logicOpEnable)
774 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
775 else
776 blend->cb_color_control |= S_028808_ROP3(0xcc);
777
778 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
779 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
780 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
781 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
782
783 if (vkms && vkms->alphaToCoverageEnable) {
784 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
785 }
786
787 blend->cb_target_mask = 0;
788 for (i = 0; i < vkblend->attachmentCount; i++) {
789 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
790 unsigned blend_cntl = 0;
791 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
792 VkBlendOp eqRGB = att->colorBlendOp;
793 VkBlendFactor srcRGB = att->srcColorBlendFactor;
794 VkBlendFactor dstRGB = att->dstColorBlendFactor;
795 VkBlendOp eqA = att->alphaBlendOp;
796 VkBlendFactor srcA = att->srcAlphaBlendFactor;
797 VkBlendFactor dstA = att->dstAlphaBlendFactor;
798
799 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
800
801 if (!att->colorWriteMask)
802 continue;
803
804 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
805 if (!att->blendEnable) {
806 blend->cb_blend_control[i] = blend_cntl;
807 continue;
808 }
809
810 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
811 if (i == 0)
812 blend_mrt0_is_dual_src = true;
813
814 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
815 srcRGB = VK_BLEND_FACTOR_ONE;
816 dstRGB = VK_BLEND_FACTOR_ONE;
817 }
818 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
819 srcA = VK_BLEND_FACTOR_ONE;
820 dstA = VK_BLEND_FACTOR_ONE;
821 }
822
823 /* Blending optimizations for RB+.
824 * These transformations don't change the behavior.
825 *
826 * First, get rid of DST in the blend factors:
827 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
828 */
829 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
830 VK_BLEND_FACTOR_DST_COLOR,
831 VK_BLEND_FACTOR_SRC_COLOR);
832
833 si_blend_remove_dst(&eqA, &srcA, &dstA,
834 VK_BLEND_FACTOR_DST_COLOR,
835 VK_BLEND_FACTOR_SRC_COLOR);
836
837 si_blend_remove_dst(&eqA, &srcA, &dstA,
838 VK_BLEND_FACTOR_DST_ALPHA,
839 VK_BLEND_FACTOR_SRC_ALPHA);
840
841 /* Look up the ideal settings from tables. */
842 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
843 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
844 srcA_opt = si_translate_blend_opt_factor(srcA, true);
845 dstA_opt = si_translate_blend_opt_factor(dstA, true);
846
847 /* Handle interdependencies. */
848 if (si_blend_factor_uses_dst(srcRGB))
849 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
850 if (si_blend_factor_uses_dst(srcA))
851 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
852
853 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
854 (dstRGB == VK_BLEND_FACTOR_ZERO ||
855 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
856 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
857 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
858
859 /* Set the final value. */
860 blend->sx_mrt_blend_opt[i] =
861 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
862 S_028760_COLOR_DST_OPT(dstRGB_opt) |
863 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
864 S_028760_ALPHA_SRC_OPT(srcA_opt) |
865 S_028760_ALPHA_DST_OPT(dstA_opt) |
866 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
867 blend_cntl |= S_028780_ENABLE(1);
868
869 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
870 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
871 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
872 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
873 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
874 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
875 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
876 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
877 }
878 blend->cb_blend_control[i] = blend_cntl;
879
880 blend_enable |= 1 << i;
881
882 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
883 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
884 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
885 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
886 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
887 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
888 blend_need_alpha |= 1 << i;
889 }
890 for (i = vkblend->attachmentCount; i < 8; i++) {
891 blend->cb_blend_control[i] = 0;
892 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
893 }
894
895 /* disable RB+ for now */
896 if (pipeline->device->physical_device->has_rbplus)
897 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
898
899 if (blend->cb_target_mask)
900 blend->cb_color_control |= S_028808_MODE(mode);
901 else
902 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
903
904 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
905 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
906 }
907
908 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
909 {
910 switch (op) {
911 case VK_STENCIL_OP_KEEP:
912 return V_02842C_STENCIL_KEEP;
913 case VK_STENCIL_OP_ZERO:
914 return V_02842C_STENCIL_ZERO;
915 case VK_STENCIL_OP_REPLACE:
916 return V_02842C_STENCIL_REPLACE_TEST;
917 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
918 return V_02842C_STENCIL_ADD_CLAMP;
919 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
920 return V_02842C_STENCIL_SUB_CLAMP;
921 case VK_STENCIL_OP_INVERT:
922 return V_02842C_STENCIL_INVERT;
923 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
924 return V_02842C_STENCIL_ADD_WRAP;
925 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
926 return V_02842C_STENCIL_SUB_WRAP;
927 default:
928 return 0;
929 }
930 }
931 static void
932 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
933 const VkGraphicsPipelineCreateInfo *pCreateInfo,
934 const struct radv_graphics_pipeline_create_info *extra)
935 {
936 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
937 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
938
939 if (!vkds)
940 return;
941
942 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
943 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
944 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
945 return;
946
947 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
948 bool has_depth_attachment = vk_format_is_depth(attachment->format);
949 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
950
951 if (has_depth_attachment) {
952 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
953 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
954 S_028800_ZFUNC(vkds->depthCompareOp) |
955 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
956 }
957
958 if (has_stencil_attachment && vkds->stencilTestEnable) {
959 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
960 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
961 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
962 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
963 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
964
965 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
966 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
967 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
968 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
969 }
970
971 if (extra) {
972
973 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
974 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
975
976 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
977 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
978 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
979 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
980 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
981 }
982 }
983
984 static uint32_t si_translate_fill(VkPolygonMode func)
985 {
986 switch(func) {
987 case VK_POLYGON_MODE_FILL:
988 return V_028814_X_DRAW_TRIANGLES;
989 case VK_POLYGON_MODE_LINE:
990 return V_028814_X_DRAW_LINES;
991 case VK_POLYGON_MODE_POINT:
992 return V_028814_X_DRAW_POINTS;
993 default:
994 assert(0);
995 return V_028814_X_DRAW_POINTS;
996 }
997 }
998 static void
999 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1000 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1001 {
1002 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1003 struct radv_raster_state *raster = &pipeline->graphics.raster;
1004
1005 raster->spi_interp_control =
1006 S_0286D4_FLAT_SHADE_ENA(1) |
1007 S_0286D4_PNT_SPRITE_ENA(1) |
1008 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1009 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1010 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1011 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1012 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1013
1014
1015 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1016 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1017 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1018 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1019 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1020 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1021
1022 raster->pa_su_vtx_cntl =
1023 S_028BE4_PIX_CENTER(1) | // TODO verify
1024 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1025 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1026
1027 raster->pa_su_sc_mode_cntl =
1028 S_028814_FACE(vkraster->frontFace) |
1029 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1030 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1031 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1032 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1033 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1034 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1035 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1036 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1037
1038 }
1039
1040 static void
1041 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1042 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1043 {
1044 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1045 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1046 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1047 int ps_iter_samples = 1;
1048 uint32_t mask = 0xffff;
1049
1050 if (vkms)
1051 ms->num_samples = vkms->rasterizationSamples;
1052 else
1053 ms->num_samples = 1;
1054
1055 if (vkms && vkms->sampleShadingEnable) {
1056 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1057 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1058 ps_iter_samples = ms->num_samples;
1059 }
1060
1061 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1062 ms->pa_sc_aa_config = 0;
1063 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1064 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1065 ms->pa_sc_mode_cntl_1 =
1066 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1067 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1068 /* always 1: */
1069 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1070 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1071 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1072 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1073 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1074 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1075 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1076
1077 if (ms->num_samples > 1) {
1078 unsigned log_samples = util_logbase2(ms->num_samples);
1079 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1080 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1081 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1082 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1083 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1084 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1085 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1086 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1087 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1088 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1089 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1090 }
1091
1092 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1093 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1094 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1095 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1096 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1097 }
1098
1099 if (vkms && vkms->pSampleMask) {
1100 mask = vkms->pSampleMask[0] & 0xffff;
1101 }
1102
1103 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1104 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1105 }
1106
1107 static bool
1108 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1109 {
1110 switch (topology) {
1111 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1112 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1113 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1114 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1115 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1116 return false;
1117 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1118 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1119 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1120 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1121 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1122 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1123 return true;
1124 default:
1125 unreachable("unhandled primitive type");
1126 }
1127 }
1128
1129 static uint32_t
1130 si_translate_prim(enum VkPrimitiveTopology topology)
1131 {
1132 switch (topology) {
1133 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1134 return V_008958_DI_PT_POINTLIST;
1135 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1136 return V_008958_DI_PT_LINELIST;
1137 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1138 return V_008958_DI_PT_LINESTRIP;
1139 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1140 return V_008958_DI_PT_TRILIST;
1141 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1142 return V_008958_DI_PT_TRISTRIP;
1143 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1144 return V_008958_DI_PT_TRIFAN;
1145 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1146 return V_008958_DI_PT_LINELIST_ADJ;
1147 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1148 return V_008958_DI_PT_LINESTRIP_ADJ;
1149 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1150 return V_008958_DI_PT_TRILIST_ADJ;
1151 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1152 return V_008958_DI_PT_TRISTRIP_ADJ;
1153 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1154 return V_008958_DI_PT_PATCH;
1155 default:
1156 assert(0);
1157 return 0;
1158 }
1159 }
1160
1161 static uint32_t
1162 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1163 {
1164 switch (gl_prim) {
1165 case 0: /* GL_POINTS */
1166 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1167 case 1: /* GL_LINES */
1168 case 3: /* GL_LINE_STRIP */
1169 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1170 case 0x8E7A: /* GL_ISOLINES */
1171 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1172
1173 case 4: /* GL_TRIANGLES */
1174 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1175 case 5: /* GL_TRIANGLE_STRIP */
1176 case 7: /* GL_QUADS */
1177 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1178 default:
1179 assert(0);
1180 return 0;
1181 }
1182 }
1183
1184 static uint32_t
1185 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1186 {
1187 switch (topology) {
1188 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1189 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1190 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1191 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1192 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1193 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1194 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1195 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1196 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1197 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1198 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1199 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1201 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1202 default:
1203 assert(0);
1204 return 0;
1205 }
1206 }
1207
1208 static unsigned si_map_swizzle(unsigned swizzle)
1209 {
1210 switch (swizzle) {
1211 case VK_SWIZZLE_Y:
1212 return V_008F0C_SQ_SEL_Y;
1213 case VK_SWIZZLE_Z:
1214 return V_008F0C_SQ_SEL_Z;
1215 case VK_SWIZZLE_W:
1216 return V_008F0C_SQ_SEL_W;
1217 case VK_SWIZZLE_0:
1218 return V_008F0C_SQ_SEL_0;
1219 case VK_SWIZZLE_1:
1220 return V_008F0C_SQ_SEL_1;
1221 default: /* VK_SWIZZLE_X */
1222 return V_008F0C_SQ_SEL_X;
1223 }
1224 }
1225
1226 static void
1227 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1228 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1229 {
1230 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1231 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1232 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1233
1234 pipeline->dynamic_state = default_dynamic_state;
1235
1236 if (pCreateInfo->pDynamicState) {
1237 /* Remove all of the states that are marked as dynamic */
1238 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1239 for (uint32_t s = 0; s < count; s++)
1240 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1241 }
1242
1243 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1244
1245 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1246 *
1247 * pViewportState is [...] NULL if the pipeline
1248 * has rasterization disabled.
1249 */
1250 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1251 assert(pCreateInfo->pViewportState);
1252
1253 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1254 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1255 typed_memcpy(dynamic->viewport.viewports,
1256 pCreateInfo->pViewportState->pViewports,
1257 pCreateInfo->pViewportState->viewportCount);
1258 }
1259
1260 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1261 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1262 typed_memcpy(dynamic->scissor.scissors,
1263 pCreateInfo->pViewportState->pScissors,
1264 pCreateInfo->pViewportState->scissorCount);
1265 }
1266 }
1267
1268 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1269 assert(pCreateInfo->pRasterizationState);
1270 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1271 }
1272
1273 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1274 assert(pCreateInfo->pRasterizationState);
1275 dynamic->depth_bias.bias =
1276 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1277 dynamic->depth_bias.clamp =
1278 pCreateInfo->pRasterizationState->depthBiasClamp;
1279 dynamic->depth_bias.slope =
1280 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1281 }
1282
1283 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1284 *
1285 * pColorBlendState is [...] NULL if the pipeline has rasterization
1286 * disabled or if the subpass of the render pass the pipeline is
1287 * created against does not use any color attachments.
1288 */
1289 bool uses_color_att = false;
1290 for (unsigned i = 0; i < subpass->color_count; ++i) {
1291 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1292 uses_color_att = true;
1293 break;
1294 }
1295 }
1296
1297 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1298 assert(pCreateInfo->pColorBlendState);
1299 typed_memcpy(dynamic->blend_constants,
1300 pCreateInfo->pColorBlendState->blendConstants, 4);
1301 }
1302
1303 /* If there is no depthstencil attachment, then don't read
1304 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1305 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1306 * no need to override the depthstencil defaults in
1307 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1308 *
1309 * Section 9.2 of the Vulkan 1.0.15 spec says:
1310 *
1311 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1312 * disabled or if the subpass of the render pass the pipeline is created
1313 * against does not use a depth/stencil attachment.
1314 */
1315 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1316 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1317 assert(pCreateInfo->pDepthStencilState);
1318
1319 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1320 dynamic->depth_bounds.min =
1321 pCreateInfo->pDepthStencilState->minDepthBounds;
1322 dynamic->depth_bounds.max =
1323 pCreateInfo->pDepthStencilState->maxDepthBounds;
1324 }
1325
1326 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1327 dynamic->stencil_compare_mask.front =
1328 pCreateInfo->pDepthStencilState->front.compareMask;
1329 dynamic->stencil_compare_mask.back =
1330 pCreateInfo->pDepthStencilState->back.compareMask;
1331 }
1332
1333 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1334 dynamic->stencil_write_mask.front =
1335 pCreateInfo->pDepthStencilState->front.writeMask;
1336 dynamic->stencil_write_mask.back =
1337 pCreateInfo->pDepthStencilState->back.writeMask;
1338 }
1339
1340 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1341 dynamic->stencil_reference.front =
1342 pCreateInfo->pDepthStencilState->front.reference;
1343 dynamic->stencil_reference.back =
1344 pCreateInfo->pDepthStencilState->back.reference;
1345 }
1346 }
1347
1348 pipeline->dynamic_state_mask = states;
1349 }
1350
1351 static struct ac_shader_variant_key
1352 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1353 {
1354 struct ac_shader_variant_key key;
1355 const VkPipelineVertexInputStateCreateInfo *input_state =
1356 pCreateInfo->pVertexInputState;
1357
1358 memset(&key, 0, sizeof(key));
1359 key.vs.instance_rate_inputs = 0;
1360 key.vs.as_es = as_es;
1361 key.vs.as_ls = as_ls;
1362 key.vs.export_prim_id = export_prim_id;
1363
1364 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1365 unsigned binding;
1366 binding = input_state->pVertexAttributeDescriptions[i].binding;
1367 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1368 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1369 }
1370 return key;
1371 }
1372
1373 static void
1374 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1375 {
1376 struct radv_device *device = pipeline->device;
1377 unsigned num_se = device->physical_device->rad_info.max_se;
1378 unsigned wave_size = 64;
1379 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1380 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1381 unsigned alignment = 256 * num_se;
1382 /* The maximum size is 63.999 MB per SE. */
1383 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1384 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1385 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1386 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1387 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1388
1389 /* Calculate the minimum size. */
1390 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1391 wave_size, alignment);
1392 /* These are recommended sizes, not minimum sizes. */
1393 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1394 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1395 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1396 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1397
1398 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1399 esgs_ring_size = align(esgs_ring_size, alignment);
1400 gsvs_ring_size = align(gsvs_ring_size, alignment);
1401
1402 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1403 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1404 }
1405
1406 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1407 unsigned *lds_size)
1408 {
1409 /* SPI barrier management bug:
1410 * Make sure we have at least 4k of LDS in use to avoid the bug.
1411 * It applies to workgroup sizes of more than one wavefront.
1412 */
1413 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1414 device->physical_device->rad_info.family == CHIP_KABINI ||
1415 device->physical_device->rad_info.family == CHIP_MULLINS)
1416 *lds_size = MAX2(*lds_size, 8);
1417 }
1418
1419 static void
1420 calculate_tess_state(struct radv_pipeline *pipeline,
1421 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1422 {
1423 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1424 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1425 unsigned num_tcs_patch_outputs;
1426 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1427 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1428 unsigned lds_size, hardware_lds_size;
1429 unsigned perpatch_output_offset;
1430 unsigned num_patches;
1431 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1432
1433 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1434 * are laid out in LDS. */
1435 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1436
1437 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1438 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1439 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1440
1441 /* Ensure that we only need one wave per SIMD so we don't need to check
1442 * resource usage. Also ensures that the number of tcs in and out
1443 * vertices per threadgroup are at most 256.
1444 */
1445 input_vertex_size = num_tcs_inputs * 16;
1446 output_vertex_size = num_tcs_outputs * 16;
1447
1448 input_patch_size = num_tcs_input_cp * input_vertex_size;
1449
1450 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1451 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1452 /* Ensure that we only need one wave per SIMD so we don't need to check
1453 * resource usage. Also ensures that the number of tcs in and out
1454 * vertices per threadgroup are at most 256.
1455 */
1456 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1457
1458 /* Make sure that the data fits in LDS. This assumes the shaders only
1459 * use LDS for the inputs and outputs.
1460 */
1461 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1462 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1463
1464 /* Make sure the output data fits in the offchip buffer */
1465 num_patches = MIN2(num_patches,
1466 (pipeline->device->tess_offchip_block_dw_size * 4) /
1467 output_patch_size);
1468
1469 /* Not necessary for correctness, but improves performance. The
1470 * specific value is taken from the proprietary driver.
1471 */
1472 num_patches = MIN2(num_patches, 40);
1473
1474 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1475 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1476 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1477 num_patches = MIN2(num_patches, one_wave);
1478 }
1479
1480 output_patch0_offset = input_patch_size * num_patches;
1481 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1482
1483 lds_size = output_patch0_offset + output_patch_size * num_patches;
1484
1485 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1486 assert(lds_size <= 65536);
1487 lds_size = align(lds_size, 512) / 512;
1488 } else {
1489 assert(lds_size <= 32768);
1490 lds_size = align(lds_size, 256) / 256;
1491 }
1492 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1493
1494 tess->lds_size = lds_size;
1495
1496 tess->tcs_in_layout = (input_patch_size / 4) |
1497 ((input_vertex_size / 4) << 13);
1498 tess->tcs_out_layout = (output_patch_size / 4) |
1499 ((output_vertex_size / 4) << 13);
1500 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1501 ((perpatch_output_offset / 16) << 16);
1502 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1503 (num_tcs_output_cp << 9) | num_patches;
1504
1505 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1506 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1507 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1508 tess->num_patches = num_patches;
1509 tess->num_tcs_input_cp = num_tcs_input_cp;
1510
1511 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1512 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1513
1514 switch (tes->info.tes.primitive_mode) {
1515 case GL_TRIANGLES:
1516 type = V_028B6C_TESS_TRIANGLE;
1517 break;
1518 case GL_QUADS:
1519 type = V_028B6C_TESS_QUAD;
1520 break;
1521 case GL_ISOLINES:
1522 type = V_028B6C_TESS_ISOLINE;
1523 break;
1524 }
1525
1526 switch (tes->info.tes.spacing) {
1527 case TESS_SPACING_EQUAL:
1528 partitioning = V_028B6C_PART_INTEGER;
1529 break;
1530 case TESS_SPACING_FRACTIONAL_ODD:
1531 partitioning = V_028B6C_PART_FRAC_ODD;
1532 break;
1533 case TESS_SPACING_FRACTIONAL_EVEN:
1534 partitioning = V_028B6C_PART_FRAC_EVEN;
1535 break;
1536 default:
1537 break;
1538 }
1539
1540 bool ccw = tes->info.tes.ccw;
1541 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1542 vk_find_struct_const(pCreateInfo->pTessellationState,
1543 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1544
1545 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1546 ccw = !ccw;
1547
1548 if (tes->info.tes.point_mode)
1549 topology = V_028B6C_OUTPUT_POINT;
1550 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1551 topology = V_028B6C_OUTPUT_LINE;
1552 else if (ccw)
1553 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1554 else
1555 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1556
1557 if (pipeline->device->has_distributed_tess) {
1558 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1559 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1560 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1561 else
1562 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1563 } else
1564 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1565
1566 tess->tf_param = S_028B6C_TYPE(type) |
1567 S_028B6C_PARTITIONING(partitioning) |
1568 S_028B6C_TOPOLOGY(topology) |
1569 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1570 }
1571
1572 static const struct radv_prim_vertex_count prim_size_table[] = {
1573 [V_008958_DI_PT_NONE] = {0, 0},
1574 [V_008958_DI_PT_POINTLIST] = {1, 1},
1575 [V_008958_DI_PT_LINELIST] = {2, 2},
1576 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1577 [V_008958_DI_PT_TRILIST] = {3, 3},
1578 [V_008958_DI_PT_TRIFAN] = {3, 1},
1579 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1580 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1581 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1582 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1583 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1584 [V_008958_DI_PT_RECTLIST] = {3, 3},
1585 [V_008958_DI_PT_LINELOOP] = {2, 1},
1586 [V_008958_DI_PT_POLYGON] = {3, 1},
1587 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1588 };
1589
1590 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1591 {
1592 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1593 unsigned cut_mode;
1594
1595 if (gs_max_vert_out <= 128) {
1596 cut_mode = V_028A40_GS_CUT_128;
1597 } else if (gs_max_vert_out <= 256) {
1598 cut_mode = V_028A40_GS_CUT_256;
1599 } else if (gs_max_vert_out <= 512) {
1600 cut_mode = V_028A40_GS_CUT_512;
1601 } else {
1602 assert(gs_max_vert_out <= 1024);
1603 cut_mode = V_028A40_GS_CUT_1024;
1604 }
1605
1606 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1607 S_028A40_CUT_MODE(cut_mode)|
1608 S_028A40_ES_WRITE_OPTIMIZE(1) |
1609 S_028A40_GS_WRITE_OPTIMIZE(1);
1610 }
1611
1612 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1613 {
1614 struct radv_shader_variant *vs;
1615 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1616
1617 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1618
1619 pipeline->graphics.vgt_primitiveid_en = false;
1620 pipeline->graphics.vgt_gs_mode = 0;
1621
1622 if (radv_pipeline_has_gs(pipeline)) {
1623 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1624 } else if (outinfo->export_prim_id) {
1625 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1626 pipeline->graphics.vgt_primitiveid_en = true;
1627 }
1628 }
1629
1630 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1631 {
1632 struct radv_shader_variant *vs;
1633 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1634
1635 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1636
1637 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1638 clip_dist_mask = outinfo->clip_dist_mask;
1639 cull_dist_mask = outinfo->cull_dist_mask;
1640 total_mask = clip_dist_mask | cull_dist_mask;
1641
1642 bool misc_vec_ena = outinfo->writes_pointsize ||
1643 outinfo->writes_layer ||
1644 outinfo->writes_viewport_index;
1645 pipeline->graphics.pa_cl_vs_out_cntl =
1646 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1647 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1648 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1649 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1650 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1651 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1652 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1653 cull_dist_mask << 8 |
1654 clip_dist_mask;
1655
1656 }
1657
1658 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1659 {
1660 uint32_t ps_input_cntl;
1661 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1662 ps_input_cntl = S_028644_OFFSET(offset);
1663 if (flat_shade)
1664 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1665 } else {
1666 /* The input is a DEFAULT_VAL constant. */
1667 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1668 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1669 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1670 ps_input_cntl = S_028644_OFFSET(0x20) |
1671 S_028644_DEFAULT_VAL(offset);
1672 }
1673 return ps_input_cntl;
1674 }
1675
1676 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1677 {
1678 struct radv_shader_variant *ps, *vs;
1679 struct ac_vs_output_info *outinfo;
1680
1681 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1682 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1683
1684 outinfo = &vs->info.vs.outinfo;
1685
1686 unsigned ps_offset = 0;
1687
1688 if (ps->info.fs.prim_id_input) {
1689 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1690 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1691 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1692 ++ps_offset;
1693 }
1694 }
1695
1696 if (ps->info.fs.layer_input) {
1697 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1698 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1699 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1700 else
1701 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1702 ++ps_offset;
1703 }
1704
1705 if (ps->info.fs.has_pcoord) {
1706 unsigned val;
1707 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1708 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1709 ps_offset++;
1710 }
1711
1712 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1713 unsigned vs_offset;
1714 bool flat_shade;
1715 if (!(ps->info.fs.input_mask & (1u << i)))
1716 continue;
1717
1718 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1719 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1720 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1721 ++ps_offset;
1722 continue;
1723 }
1724
1725 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1726
1727 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1728 ++ps_offset;
1729 }
1730
1731 pipeline->graphics.ps_input_cntl_num = ps_offset;
1732 }
1733
1734 static VkResult
1735 radv_pipeline_init(struct radv_pipeline *pipeline,
1736 struct radv_device *device,
1737 struct radv_pipeline_cache *cache,
1738 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1739 const struct radv_graphics_pipeline_create_info *extra,
1740 const VkAllocationCallbacks *alloc)
1741 {
1742 struct radv_shader_module fs_m = {0};
1743 VkResult result;
1744 bool has_view_index = false;
1745
1746 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1747 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1748 if (subpass->view_mask)
1749 has_view_index = true;
1750 if (alloc == NULL)
1751 alloc = &device->alloc;
1752
1753 pipeline->device = device;
1754 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1755
1756 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1757 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1758 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1759 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1760 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1761 pStages[stage] = &pCreateInfo->pStages[i];
1762 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1763 }
1764
1765 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1766
1767 if (!modules[MESA_SHADER_FRAGMENT]) {
1768 nir_builder fs_b;
1769 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1770 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1771 fs_m.nir = fs_b.shader;
1772 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1773 }
1774
1775 if (modules[MESA_SHADER_FRAGMENT]) {
1776 struct ac_shader_variant_key key = {0};
1777 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1778 if (pCreateInfo->pMultisampleState &&
1779 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1780 key.fs.multisample = true;
1781
1782 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1783 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
1784
1785 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1786
1787 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1788 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1789 stage ? stage->pName : "main",
1790 MESA_SHADER_FRAGMENT,
1791 stage ? stage->pSpecializationInfo : NULL,
1792 pipeline->layout, &key);
1793 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1794 }
1795
1796 if (fs_m.nir)
1797 ralloc_free(fs_m.nir);
1798
1799 if (modules[MESA_SHADER_VERTEX]) {
1800 bool as_es = false;
1801 bool as_ls = false;
1802 bool export_prim_id = false;
1803 if (modules[MESA_SHADER_TESS_CTRL])
1804 as_ls = true;
1805 else if (modules[MESA_SHADER_GEOMETRY])
1806 as_es = true;
1807 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
1808 export_prim_id = true;
1809 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
1810 key.has_multiview_view_index = has_view_index;
1811
1812 pipeline->shaders[MESA_SHADER_VERTEX] =
1813 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1814 pStages[MESA_SHADER_VERTEX]->pName,
1815 MESA_SHADER_VERTEX,
1816 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1817 pipeline->layout, &key);
1818
1819 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1820 }
1821
1822 if (modules[MESA_SHADER_GEOMETRY]) {
1823 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
1824 key.has_multiview_view_index = has_view_index;
1825
1826 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1827 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1828 pStages[MESA_SHADER_GEOMETRY]->pName,
1829 MESA_SHADER_GEOMETRY,
1830 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1831 pipeline->layout, &key);
1832
1833 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1834 }
1835
1836 if (modules[MESA_SHADER_TESS_EVAL]) {
1837 assert(modules[MESA_SHADER_TESS_CTRL]);
1838
1839 radv_tess_pipeline_compile(pipeline,
1840 cache,
1841 modules[MESA_SHADER_TESS_CTRL],
1842 modules[MESA_SHADER_TESS_EVAL],
1843 pStages[MESA_SHADER_TESS_CTRL]->pName,
1844 pStages[MESA_SHADER_TESS_EVAL]->pName,
1845 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1846 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
1847 pipeline->layout,
1848 pCreateInfo->pTessellationState->patchControlPoints,
1849 has_view_index);
1850 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
1851 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
1852 }
1853
1854 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1855 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1856 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1857 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1858 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
1859
1860 if (radv_pipeline_has_gs(pipeline)) {
1861 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1862 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1863 } else {
1864 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1865 }
1866 if (extra && extra->use_rectlist) {
1867 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1868 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1869 pipeline->graphics.can_use_guardband = true;
1870 }
1871 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1872 /* prim vertex count will need TESS changes */
1873 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1874
1875 /* Ensure that some export memory is always allocated, for two reasons:
1876 *
1877 * 1) Correctness: The hardware ignores the EXEC mask if no export
1878 * memory is allocated, so KILL and alpha test do not work correctly
1879 * without this.
1880 * 2) Performance: Every shader needs at least a NULL export, even when
1881 * it writes no color/depth output. The NULL export instruction
1882 * stalls without this setting.
1883 *
1884 * Don't add this to CB_SHADER_MASK.
1885 */
1886 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1887 if (!pipeline->graphics.blend.spi_shader_col_format) {
1888 if (!ps->info.fs.writes_z &&
1889 !ps->info.fs.writes_stencil &&
1890 !ps->info.fs.writes_sample_mask)
1891 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1892 }
1893
1894 unsigned z_order;
1895 pipeline->graphics.db_shader_control = 0;
1896 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1897 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1898 else
1899 z_order = V_02880C_LATE_Z;
1900
1901 pipeline->graphics.db_shader_control =
1902 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1903 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1904 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1905 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1906 S_02880C_Z_ORDER(z_order) |
1907 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1908 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1909 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1910
1911 if (pipeline->device->physical_device->has_rbplus)
1912 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1913
1914 pipeline->graphics.shader_z_format =
1915 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
1916 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
1917 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
1918 V_028710_SPI_SHADER_ZERO;
1919
1920 calculate_vgt_gs_mode(pipeline);
1921 calculate_pa_cl_vs_out_cntl(pipeline);
1922 calculate_ps_inputs(pipeline);
1923
1924 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1925 if (pipeline->shaders[i]) {
1926 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
1927 }
1928 }
1929
1930 uint32_t stages = 0;
1931 if (radv_pipeline_has_tess(pipeline)) {
1932 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1933 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1934
1935 if (radv_pipeline_has_gs(pipeline))
1936 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1937 S_028B54_GS_EN(1) |
1938 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1939 else
1940 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1941
1942 } else if (radv_pipeline_has_gs(pipeline))
1943 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1944 S_028B54_GS_EN(1) |
1945 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1946
1947 if (device->physical_device->rad_info.chip_class >= GFX9)
1948 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1949
1950 pipeline->graphics.vgt_shader_stages_en = stages;
1951
1952 if (radv_pipeline_has_gs(pipeline))
1953 calculate_gs_ring_sizes(pipeline);
1954
1955 if (radv_pipeline_has_tess(pipeline)) {
1956 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
1957 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
1958 pipeline->graphics.prim_vertex_count.incr = 1;
1959 }
1960 calculate_tess_state(pipeline, pCreateInfo);
1961 }
1962
1963 if (radv_pipeline_has_tess(pipeline))
1964 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
1965 else if (radv_pipeline_has_gs(pipeline))
1966 pipeline->graphics.primgroup_size = 64;
1967 else
1968 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
1969
1970 pipeline->graphics.partial_es_wave = false;
1971 if (pipeline->device->has_distributed_tess) {
1972 if (radv_pipeline_has_gs(pipeline)) {
1973 if (device->physical_device->rad_info.chip_class <= VI)
1974 pipeline->graphics.partial_es_wave = true;
1975 }
1976 }
1977 /* GS requirement. */
1978 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
1979 pipeline->graphics.partial_es_wave = true;
1980
1981 pipeline->graphics.wd_switch_on_eop = false;
1982 if (device->physical_device->rad_info.chip_class >= CIK) {
1983 unsigned prim = pipeline->graphics.prim;
1984 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
1985 * 4 shader engines. Set 1 to pass the assertion below.
1986 * The other cases are hardware requirements. */
1987 if (device->physical_device->rad_info.max_se < 4 ||
1988 prim == V_008958_DI_PT_POLYGON ||
1989 prim == V_008958_DI_PT_LINELOOP ||
1990 prim == V_008958_DI_PT_TRIFAN ||
1991 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
1992 (pipeline->graphics.prim_restart_enable &&
1993 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
1994 (prim != V_008958_DI_PT_POINTLIST &&
1995 prim != V_008958_DI_PT_LINESTRIP &&
1996 prim != V_008958_DI_PT_TRISTRIP))))
1997 pipeline->graphics.wd_switch_on_eop = true;
1998 }
1999
2000 pipeline->graphics.ia_switch_on_eoi = false;
2001 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2002 pipeline->graphics.ia_switch_on_eoi = true;
2003 if (radv_pipeline_has_gs(pipeline) &&
2004 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
2005 pipeline->graphics.ia_switch_on_eoi = true;
2006 if (radv_pipeline_has_tess(pipeline)) {
2007 /* SWITCH_ON_EOI must be set if PrimID is used. */
2008 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
2009 pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
2010 pipeline->graphics.ia_switch_on_eoi = true;
2011 }
2012
2013 pipeline->graphics.partial_vs_wave = false;
2014 if (radv_pipeline_has_tess(pipeline)) {
2015 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2016 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2017 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2018 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2019 radv_pipeline_has_gs(pipeline))
2020 pipeline->graphics.partial_vs_wave = true;
2021 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2022 if (device->has_distributed_tess) {
2023 if (radv_pipeline_has_gs(pipeline)) {
2024 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2025 device->physical_device->rad_info.family == CHIP_FIJI ||
2026 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2027 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2028 device->physical_device->rad_info.family == CHIP_POLARIS12)
2029 pipeline->graphics.partial_vs_wave = true;
2030 } else {
2031 pipeline->graphics.partial_vs_wave = true;
2032 }
2033 }
2034 }
2035
2036 pipeline->graphics.base_ia_multi_vgt_param =
2037 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
2038 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
2039 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
2040 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
2041 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
2042
2043 const VkPipelineVertexInputStateCreateInfo *vi_info =
2044 pCreateInfo->pVertexInputState;
2045 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2046
2047 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2048 const VkVertexInputAttributeDescription *desc =
2049 &vi_info->pVertexAttributeDescriptions[i];
2050 unsigned loc = desc->location;
2051 const struct vk_format_description *format_desc;
2052 int first_non_void;
2053 uint32_t num_format, data_format;
2054 format_desc = vk_format_description(desc->format);
2055 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2056
2057 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2058 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2059
2060 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2061 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2062 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2063 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2064 S_008F0C_NUM_FORMAT(num_format) |
2065 S_008F0C_DATA_FORMAT(data_format);
2066 velems->format_size[loc] = format_desc->block.bits / 8;
2067 velems->offset[loc] = desc->offset;
2068 velems->binding[loc] = desc->binding;
2069 velems->count = MAX2(velems->count, loc + 1);
2070 }
2071
2072 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2073 const VkVertexInputBindingDescription *desc =
2074 &vi_info->pVertexBindingDescriptions[i];
2075
2076 pipeline->binding_stride[desc->binding] = desc->stride;
2077 }
2078
2079 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2080 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2081 if (loc->sgpr_idx != -1) {
2082 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2083 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2084 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2085 pipeline->graphics.vtx_emit_num = 3;
2086 else
2087 pipeline->graphics.vtx_emit_num = 2;
2088 }
2089
2090 pipeline->graphics.vtx_reuse_depth = 30;
2091 if (radv_pipeline_has_tess(pipeline) &&
2092 pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2093 pipeline->graphics.vtx_reuse_depth = 14;
2094 }
2095
2096 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2097 radv_dump_pipeline_stats(device, pipeline);
2098 }
2099
2100 result = radv_pipeline_scratch_init(device, pipeline);
2101 return result;
2102 }
2103
2104 VkResult
2105 radv_graphics_pipeline_create(
2106 VkDevice _device,
2107 VkPipelineCache _cache,
2108 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2109 const struct radv_graphics_pipeline_create_info *extra,
2110 const VkAllocationCallbacks *pAllocator,
2111 VkPipeline *pPipeline)
2112 {
2113 RADV_FROM_HANDLE(radv_device, device, _device);
2114 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2115 struct radv_pipeline *pipeline;
2116 VkResult result;
2117
2118 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2119 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2120 if (pipeline == NULL)
2121 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2122
2123 memset(pipeline, 0, sizeof(*pipeline));
2124 result = radv_pipeline_init(pipeline, device, cache,
2125 pCreateInfo, extra, pAllocator);
2126 if (result != VK_SUCCESS) {
2127 radv_pipeline_destroy(device, pipeline, pAllocator);
2128 return result;
2129 }
2130
2131 *pPipeline = radv_pipeline_to_handle(pipeline);
2132
2133 return VK_SUCCESS;
2134 }
2135
2136 VkResult radv_CreateGraphicsPipelines(
2137 VkDevice _device,
2138 VkPipelineCache pipelineCache,
2139 uint32_t count,
2140 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2141 const VkAllocationCallbacks* pAllocator,
2142 VkPipeline* pPipelines)
2143 {
2144 VkResult result = VK_SUCCESS;
2145 unsigned i = 0;
2146
2147 for (; i < count; i++) {
2148 VkResult r;
2149 r = radv_graphics_pipeline_create(_device,
2150 pipelineCache,
2151 &pCreateInfos[i],
2152 NULL, pAllocator, &pPipelines[i]);
2153 if (r != VK_SUCCESS) {
2154 result = r;
2155 pPipelines[i] = VK_NULL_HANDLE;
2156 }
2157 }
2158
2159 return result;
2160 }
2161
2162 static VkResult radv_compute_pipeline_create(
2163 VkDevice _device,
2164 VkPipelineCache _cache,
2165 const VkComputePipelineCreateInfo* pCreateInfo,
2166 const VkAllocationCallbacks* pAllocator,
2167 VkPipeline* pPipeline)
2168 {
2169 RADV_FROM_HANDLE(radv_device, device, _device);
2170 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2171 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2172 struct radv_pipeline *pipeline;
2173 VkResult result;
2174
2175 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2176 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2177 if (pipeline == NULL)
2178 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2179
2180 memset(pipeline, 0, sizeof(*pipeline));
2181 pipeline->device = device;
2182 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2183
2184 pipeline->shaders[MESA_SHADER_COMPUTE] =
2185 radv_pipeline_compile(pipeline, cache, module,
2186 pCreateInfo->stage.pName,
2187 MESA_SHADER_COMPUTE,
2188 pCreateInfo->stage.pSpecializationInfo,
2189 pipeline->layout, NULL);
2190
2191
2192 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2193 result = radv_pipeline_scratch_init(device, pipeline);
2194 if (result != VK_SUCCESS) {
2195 radv_pipeline_destroy(device, pipeline, pAllocator);
2196 return result;
2197 }
2198
2199 *pPipeline = radv_pipeline_to_handle(pipeline);
2200
2201 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2202 radv_dump_pipeline_stats(device, pipeline);
2203 }
2204 return VK_SUCCESS;
2205 }
2206 VkResult radv_CreateComputePipelines(
2207 VkDevice _device,
2208 VkPipelineCache pipelineCache,
2209 uint32_t count,
2210 const VkComputePipelineCreateInfo* pCreateInfos,
2211 const VkAllocationCallbacks* pAllocator,
2212 VkPipeline* pPipelines)
2213 {
2214 VkResult result = VK_SUCCESS;
2215
2216 unsigned i = 0;
2217 for (; i < count; i++) {
2218 VkResult r;
2219 r = radv_compute_pipeline_create(_device, pipelineCache,
2220 &pCreateInfos[i],
2221 pAllocator, &pPipelines[i]);
2222 if (r != VK_SUCCESS) {
2223 result = r;
2224 pPipelines[i] = VK_NULL_HANDLE;
2225 }
2226 }
2227
2228 return result;
2229 }