2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device
*device
,
45 struct radv_shader_variant
*variant
);
47 static const struct nir_shader_compiler_options nir_options
= {
48 .vertex_id_zero_based
= true,
52 .lower_pack_snorm_2x16
= true,
53 .lower_pack_snorm_4x8
= true,
54 .lower_pack_unorm_2x16
= true,
55 .lower_pack_unorm_4x8
= true,
56 .lower_unpack_snorm_2x16
= true,
57 .lower_unpack_snorm_4x8
= true,
58 .lower_unpack_unorm_2x16
= true,
59 .lower_unpack_unorm_4x8
= true,
60 .lower_extract_byte
= true,
61 .lower_extract_word
= true,
64 VkResult
radv_CreateShaderModule(
66 const VkShaderModuleCreateInfo
* pCreateInfo
,
67 const VkAllocationCallbacks
* pAllocator
,
68 VkShaderModule
* pShaderModule
)
70 RADV_FROM_HANDLE(radv_device
, device
, _device
);
71 struct radv_shader_module
*module
;
73 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
74 assert(pCreateInfo
->flags
== 0);
76 module
= vk_alloc2(&device
->alloc
, pAllocator
,
77 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
83 module
->size
= pCreateInfo
->codeSize
;
84 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
86 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
88 *pShaderModule
= radv_shader_module_to_handle(module
);
93 void radv_DestroyShaderModule(
95 VkShaderModule _module
,
96 const VkAllocationCallbacks
* pAllocator
)
98 RADV_FROM_HANDLE(radv_device
, device
, _device
);
99 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
104 vk_free2(&device
->alloc
, pAllocator
, module
);
107 void radv_DestroyPipeline(
109 VkPipeline _pipeline
,
110 const VkAllocationCallbacks
* pAllocator
)
112 RADV_FROM_HANDLE(radv_device
, device
, _device
);
113 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
118 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
119 if (pipeline
->shaders
[i
])
120 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
122 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
127 radv_optimize_nir(struct nir_shader
*shader
)
134 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
135 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
136 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
138 NIR_PASS(progress
, shader
, nir_copy_prop
);
139 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
140 NIR_PASS(progress
, shader
, nir_opt_dce
);
141 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
142 NIR_PASS(progress
, shader
, nir_opt_cse
);
143 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
144 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
145 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
146 NIR_PASS(progress
, shader
, nir_opt_undef
);
147 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
152 radv_shader_compile_to_nir(struct radv_device
*device
,
153 struct radv_shader_module
*module
,
154 const char *entrypoint_name
,
155 gl_shader_stage stage
,
156 const VkSpecializationInfo
*spec_info
,
159 if (strcmp(entrypoint_name
, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
164 nir_function
*entry_point
;
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
170 nir
->options
= &nir_options
;
171 nir_validate_shader(nir
);
173 assert(exec_list_length(&nir
->functions
) == 1);
174 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
175 entry_point
= exec_node_data(nir_function
, node
, node
);
177 uint32_t *spirv
= (uint32_t *) module
->data
;
178 assert(module
->size
% 4 == 0);
180 uint32_t num_spec_entries
= 0;
181 struct nir_spirv_specialization
*spec_entries
= NULL
;
182 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
183 num_spec_entries
= spec_info
->mapEntryCount
;
184 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
185 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
186 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
187 const void *data
= spec_info
->pData
+ entry
.offset
;
188 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
190 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
191 if (spec_info
->dataSize
== 8)
192 spec_entries
[i
].data64
= *(const uint64_t *)data
;
194 spec_entries
[i
].data32
= *(const uint32_t *)data
;
197 const struct nir_spirv_supported_extensions supported_ext
= {
199 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
200 spec_entries
, num_spec_entries
,
201 stage
, entrypoint_name
, &supported_ext
, &nir_options
);
202 nir
= entry_point
->shader
;
203 assert(nir
->stage
== stage
);
204 nir_validate_shader(nir
);
208 nir_lower_returns(nir
);
209 nir_validate_shader(nir
);
211 nir_inline_functions(nir
);
212 nir_validate_shader(nir
);
214 /* Pick off the single entrypoint that we want */
215 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
216 if (func
!= entry_point
)
217 exec_node_remove(&func
->node
);
219 assert(exec_list_length(&nir
->functions
) == 1);
220 entry_point
->name
= ralloc_strdup(entry_point
, "main");
222 nir_remove_dead_variables(nir
, nir_var_shader_in
);
223 nir_remove_dead_variables(nir
, nir_var_shader_out
);
224 nir_remove_dead_variables(nir
, nir_var_system_value
);
225 nir_validate_shader(nir
);
227 nir_lower_system_values(nir
);
228 nir_validate_shader(nir
);
231 /* Vulkan uses the separate-shader linking model */
232 nir
->info
->separate_shader
= true;
234 // nir = brw_preprocess_nir(compiler, nir);
236 nir_shader_gather_info(nir
, entry_point
->impl
);
238 nir_variable_mode indirect_mask
= 0;
239 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
240 indirect_mask
|= nir_var_shader_in
;
241 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
242 indirect_mask
|= nir_var_local
;
244 nir_lower_indirect_derefs(nir
, indirect_mask
);
246 static const nir_lower_tex_options tex_options
= {
250 nir_lower_tex(nir
, &tex_options
);
252 nir_lower_vars_to_ssa(nir
);
253 nir_lower_var_copies(nir
);
254 nir_lower_global_vars_to_local(nir
);
255 nir_remove_dead_variables(nir
, nir_var_local
);
256 radv_optimize_nir(nir
);
259 nir_print_shader(nir
, stderr
);
264 static const char *radv_get_shader_name(struct radv_shader_variant
*var
,
265 gl_shader_stage stage
)
268 case MESA_SHADER_VERTEX
: return "Vertex Shader as VS";
269 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
270 case MESA_SHADER_COMPUTE
: return "Compute Shader";
272 return "Unknown shader";
276 static void radv_dump_pipeline_stats(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
278 unsigned lds_increment
= device
->instance
->physicalDevice
.rad_info
.chip_class
>= CIK
? 512 : 256;
279 struct radv_shader_variant
*var
;
280 struct ac_shader_config
*conf
;
283 unsigned max_simd_waves
= 10;
284 unsigned lds_per_wave
= 0;
286 for (i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
287 if (!pipeline
->shaders
[i
])
289 var
= pipeline
->shaders
[i
];
293 if (i
== MESA_SHADER_FRAGMENT
) {
294 lds_per_wave
= conf
->lds_size
* lds_increment
+
295 align(var
->info
.fs
.num_interp
* 48, lds_increment
);
298 if (conf
->num_sgprs
) {
299 if (device
->instance
->physicalDevice
.rad_info
.chip_class
>= VI
)
300 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
302 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
306 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
308 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
312 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
314 fprintf(file
, "\n%s:\n",
315 radv_get_shader_name(var
, i
));
316 if (i
== MESA_SHADER_FRAGMENT
) {
317 fprintf(file
, "*** SHADER CONFIG ***\n"
318 "SPI_PS_INPUT_ADDR = 0x%04x\n"
319 "SPI_PS_INPUT_ENA = 0x%04x\n",
320 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
322 fprintf(file
, "*** SHADER STATS ***\n"
325 "Spilled SGPRs: %d\n"
326 "Spilled VGPRs: %d\n"
327 "Code Size: %d bytes\n"
329 "Scratch: %d bytes per wave\n"
331 "********************\n\n\n",
332 conf
->num_sgprs
, conf
->num_vgprs
,
333 conf
->spilled_sgprs
, conf
->spilled_vgprs
, var
->code_size
,
334 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
339 void radv_shader_variant_destroy(struct radv_device
*device
,
340 struct radv_shader_variant
*variant
)
342 if (__sync_fetch_and_sub(&variant
->ref_count
, 1) != 1)
345 device
->ws
->buffer_destroy(variant
->bo
);
349 static void radv_fill_shader_variant(struct radv_device
*device
,
350 struct radv_shader_variant
*variant
,
351 struct ac_shader_binary
*binary
,
352 gl_shader_stage stage
)
354 variant
->code_size
= binary
->code_size
;
355 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
356 unsigned vgpr_comp_cnt
= 0;
359 radv_finishme("shader scratch space");
362 case MESA_SHADER_VERTEX
:
363 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
364 S_00B12C_SCRATCH_EN(scratch_enabled
);
365 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
367 case MESA_SHADER_FRAGMENT
:
368 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
369 S_00B12C_SCRATCH_EN(scratch_enabled
);
371 case MESA_SHADER_COMPUTE
:
372 variant
->rsrc2
= S_00B84C_USER_SGPR(variant
->info
.num_user_sgprs
) |
373 S_00B84C_SCRATCH_EN(scratch_enabled
) |
374 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
375 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
376 S_00B84C_TG_SIZE_EN(1) |
377 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
380 unreachable("unsupported shader type");
384 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
385 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
386 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
387 S_00B848_DX10_CLAMP(1) |
388 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
390 variant
->bo
= device
->ws
->buffer_create(device
->ws
, binary
->code_size
, 256,
391 RADEON_DOMAIN_GTT
, RADEON_FLAG_CPU_ACCESS
);
393 void *ptr
= device
->ws
->buffer_map(variant
->bo
);
394 memcpy(ptr
, binary
->code
, binary
->code_size
);
395 device
->ws
->buffer_unmap(variant
->bo
);
400 static struct radv_shader_variant
*radv_shader_variant_create(struct radv_device
*device
,
401 struct nir_shader
*shader
,
402 struct radv_pipeline_layout
*layout
,
403 const union ac_shader_variant_key
*key
,
405 unsigned *code_size_out
,
408 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
409 enum radeon_family chip_family
= device
->instance
->physicalDevice
.rad_info
.family
;
410 LLVMTargetMachineRef tm
;
414 struct ac_nir_compiler_options options
= {0};
415 options
.layout
= layout
;
419 struct ac_shader_binary binary
;
421 options
.unsafe_math
= !!(device
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
422 options
.family
= chip_family
;
423 options
.chip_class
= device
->instance
->physicalDevice
.rad_info
.chip_class
;
424 tm
= ac_create_target_machine(chip_family
);
425 ac_compile_nir_shader(tm
, &binary
, &variant
->config
,
426 &variant
->info
, shader
, &options
, dump
);
427 LLVMDisposeTargetMachine(tm
);
429 radv_fill_shader_variant(device
, variant
, &binary
, shader
->stage
);
432 *code_out
= binary
.code
;
433 *code_size_out
= binary
.code_size
;
438 free(binary
.global_symbol_offsets
);
440 free(binary
.disasm_string
);
441 variant
->ref_count
= 1;
446 static struct radv_shader_variant
*
447 radv_pipeline_compile(struct radv_pipeline
*pipeline
,
448 struct radv_pipeline_cache
*cache
,
449 struct radv_shader_module
*module
,
450 const char *entrypoint
,
451 gl_shader_stage stage
,
452 const VkSpecializationInfo
*spec_info
,
453 struct radv_pipeline_layout
*layout
,
454 const union ac_shader_variant_key
*key
)
456 unsigned char sha1
[20];
457 struct radv_shader_variant
*variant
;
460 unsigned code_size
= 0;
461 bool dump
= (pipeline
->device
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
);
464 _mesa_sha1_compute(module
->nir
->info
->name
,
465 strlen(module
->nir
->info
->name
),
468 radv_hash_shader(sha1
, module
, entrypoint
, spec_info
, layout
, key
);
471 variant
= radv_create_shader_variant_from_pipeline_cache(pipeline
->device
,
478 nir
= radv_shader_compile_to_nir(pipeline
->device
,
479 module
, entrypoint
, stage
,
484 variant
= radv_shader_variant_create(pipeline
->device
, nir
, layout
, key
,
485 &code
, &code_size
, dump
);
489 if (variant
&& cache
)
490 variant
= radv_pipeline_cache_insert_shader(cache
, sha1
, variant
,
498 static uint32_t si_translate_blend_function(VkBlendOp op
)
501 case VK_BLEND_OP_ADD
:
502 return V_028780_COMB_DST_PLUS_SRC
;
503 case VK_BLEND_OP_SUBTRACT
:
504 return V_028780_COMB_SRC_MINUS_DST
;
505 case VK_BLEND_OP_REVERSE_SUBTRACT
:
506 return V_028780_COMB_DST_MINUS_SRC
;
507 case VK_BLEND_OP_MIN
:
508 return V_028780_COMB_MIN_DST_SRC
;
509 case VK_BLEND_OP_MAX
:
510 return V_028780_COMB_MAX_DST_SRC
;
516 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
519 case VK_BLEND_FACTOR_ZERO
:
520 return V_028780_BLEND_ZERO
;
521 case VK_BLEND_FACTOR_ONE
:
522 return V_028780_BLEND_ONE
;
523 case VK_BLEND_FACTOR_SRC_COLOR
:
524 return V_028780_BLEND_SRC_COLOR
;
525 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
526 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
527 case VK_BLEND_FACTOR_DST_COLOR
:
528 return V_028780_BLEND_DST_COLOR
;
529 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
530 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
531 case VK_BLEND_FACTOR_SRC_ALPHA
:
532 return V_028780_BLEND_SRC_ALPHA
;
533 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
534 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
535 case VK_BLEND_FACTOR_DST_ALPHA
:
536 return V_028780_BLEND_DST_ALPHA
;
537 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
538 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
539 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
540 return V_028780_BLEND_CONSTANT_COLOR
;
541 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
542 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
543 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
544 return V_028780_BLEND_CONSTANT_ALPHA
;
545 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
546 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
547 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
548 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
549 case VK_BLEND_FACTOR_SRC1_COLOR
:
550 return V_028780_BLEND_SRC1_COLOR
;
551 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
552 return V_028780_BLEND_INV_SRC1_COLOR
;
553 case VK_BLEND_FACTOR_SRC1_ALPHA
:
554 return V_028780_BLEND_SRC1_ALPHA
;
555 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
556 return V_028780_BLEND_INV_SRC1_ALPHA
;
562 static bool is_dual_src(VkBlendFactor factor
)
565 case VK_BLEND_FACTOR_SRC1_COLOR
:
566 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
567 case VK_BLEND_FACTOR_SRC1_ALPHA
:
568 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
575 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
577 bool blend_need_alpha
)
579 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
580 unsigned format
, ntype
, swap
;
582 /* Alpha is needed for alpha-to-coverage.
583 * Blending may be with or without alpha.
585 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
586 unsigned alpha
= 0; /* exports alpha, but may not support blending */
587 unsigned blend
= 0; /* supports blending, but may not export alpha */
588 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
590 format
= radv_translate_colorformat(vk_format
);
591 ntype
= radv_translate_color_numformat(vk_format
, desc
,
592 vk_format_get_first_non_void_channel(vk_format
));
593 swap
= radv_translate_colorswap(vk_format
, false);
595 /* Choose the SPI color formats. These are required values for Stoney/RB+.
596 * Other chips have multiple choices, though they are not necessarily better.
599 case V_028C70_COLOR_5_6_5
:
600 case V_028C70_COLOR_1_5_5_5
:
601 case V_028C70_COLOR_5_5_5_1
:
602 case V_028C70_COLOR_4_4_4_4
:
603 case V_028C70_COLOR_10_11_11
:
604 case V_028C70_COLOR_11_11_10
:
605 case V_028C70_COLOR_8
:
606 case V_028C70_COLOR_8_8
:
607 case V_028C70_COLOR_8_8_8_8
:
608 case V_028C70_COLOR_10_10_10_2
:
609 case V_028C70_COLOR_2_10_10_10
:
610 if (ntype
== V_028C70_NUMBER_UINT
)
611 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
612 else if (ntype
== V_028C70_NUMBER_SINT
)
613 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
615 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
618 case V_028C70_COLOR_16
:
619 case V_028C70_COLOR_16_16
:
620 case V_028C70_COLOR_16_16_16_16
:
621 if (ntype
== V_028C70_NUMBER_UNORM
||
622 ntype
== V_028C70_NUMBER_SNORM
) {
623 /* UNORM16 and SNORM16 don't support blending */
624 if (ntype
== V_028C70_NUMBER_UNORM
)
625 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
627 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
629 /* Use 32 bits per channel for blending. */
630 if (format
== V_028C70_COLOR_16
) {
631 if (swap
== V_028C70_SWAP_STD
) { /* R */
632 blend
= V_028714_SPI_SHADER_32_R
;
633 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
634 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
635 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
638 } else if (format
== V_028C70_COLOR_16_16
) {
639 if (swap
== V_028C70_SWAP_STD
) { /* RG */
640 blend
= V_028714_SPI_SHADER_32_GR
;
641 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
642 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
643 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
646 } else /* 16_16_16_16 */
647 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
648 } else if (ntype
== V_028C70_NUMBER_UINT
)
649 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
650 else if (ntype
== V_028C70_NUMBER_SINT
)
651 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
652 else if (ntype
== V_028C70_NUMBER_FLOAT
)
653 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
658 case V_028C70_COLOR_32
:
659 if (swap
== V_028C70_SWAP_STD
) { /* R */
660 blend
= normal
= V_028714_SPI_SHADER_32_R
;
661 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
662 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
663 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
668 case V_028C70_COLOR_32_32
:
669 if (swap
== V_028C70_SWAP_STD
) { /* RG */
670 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
671 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
672 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
673 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
678 case V_028C70_COLOR_32_32_32_32
:
679 case V_028C70_COLOR_8_24
:
680 case V_028C70_COLOR_24_8
:
681 case V_028C70_COLOR_X24_8_32_FLOAT
:
682 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
686 unreachable("unhandled blend format");
689 if (blend_enable
&& blend_need_alpha
)
691 else if(blend_need_alpha
)
693 else if(blend_enable
)
699 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
701 unsigned i
, cb_shader_mask
= 0;
703 for (i
= 0; i
< 8; i
++) {
704 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
705 case V_028714_SPI_SHADER_ZERO
:
707 case V_028714_SPI_SHADER_32_R
:
708 cb_shader_mask
|= 0x1 << (i
* 4);
710 case V_028714_SPI_SHADER_32_GR
:
711 cb_shader_mask
|= 0x3 << (i
* 4);
713 case V_028714_SPI_SHADER_32_AR
:
714 cb_shader_mask
|= 0x9 << (i
* 4);
716 case V_028714_SPI_SHADER_FP16_ABGR
:
717 case V_028714_SPI_SHADER_UNORM16_ABGR
:
718 case V_028714_SPI_SHADER_SNORM16_ABGR
:
719 case V_028714_SPI_SHADER_UINT16_ABGR
:
720 case V_028714_SPI_SHADER_SINT16_ABGR
:
721 case V_028714_SPI_SHADER_32_ABGR
:
722 cb_shader_mask
|= 0xf << (i
* 4);
728 return cb_shader_mask
;
732 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
733 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
734 uint32_t blend_enable
,
735 uint32_t blend_need_alpha
,
736 bool single_cb_enable
,
737 bool blend_mrt0_is_dual_src
)
739 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
740 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
741 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
742 unsigned col_format
= 0;
744 for (unsigned i
= 0; i
< (single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
745 struct radv_render_pass_attachment
*attachment
;
748 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
750 cf
= si_choose_spi_color_format(attachment
->format
,
751 blend_enable
& (1 << i
),
752 blend_need_alpha
& (1 << i
));
754 col_format
|= cf
<< (4 * i
);
757 blend
->cb_shader_mask
= si_get_cb_shader_mask(col_format
);
759 if (blend_mrt0_is_dual_src
)
760 col_format
|= (col_format
& 0xf) << 4;
762 col_format
|= V_028714_SPI_SHADER_32_R
;
763 blend
->spi_shader_col_format
= col_format
;
767 format_is_int8(VkFormat format
)
769 const struct vk_format_description
*desc
= vk_format_description(format
);
770 int channel
= vk_format_get_first_non_void_channel(format
);
772 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
773 desc
->channel
[channel
].size
== 8;
776 unsigned radv_format_meta_fs_key(VkFormat format
)
778 unsigned col_format
= si_choose_spi_color_format(format
, false, false) - 1;
779 bool is_int8
= format_is_int8(format
);
781 return col_format
+ (is_int8
? 3 : 0);
785 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
787 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
788 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
789 unsigned is_int8
= 0;
791 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
792 struct radv_render_pass_attachment
*attachment
;
794 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
796 if (format_is_int8(attachment
->format
))
804 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
805 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
806 const struct radv_graphics_pipeline_create_info
*extra
)
808 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
809 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
810 unsigned mode
= V_028808_CB_NORMAL
;
811 uint32_t blend_enable
= 0, blend_need_alpha
= 0;
812 bool blend_mrt0_is_dual_src
= false;
814 bool single_cb_enable
= false;
819 if (extra
&& extra
->custom_blend_mode
) {
820 single_cb_enable
= true;
821 mode
= extra
->custom_blend_mode
;
823 blend
->cb_color_control
= 0;
824 if (vkblend
->logicOpEnable
)
825 blend
->cb_color_control
|= S_028808_ROP3(vkblend
->logicOp
| (vkblend
->logicOp
<< 4));
827 blend
->cb_color_control
|= S_028808_ROP3(0xcc);
829 blend
->db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
830 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
831 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
832 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
834 blend
->cb_target_mask
= 0;
835 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
836 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
837 unsigned blend_cntl
= 0;
838 VkBlendOp eqRGB
= att
->colorBlendOp
;
839 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
840 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
841 VkBlendOp eqA
= att
->alphaBlendOp
;
842 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
843 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
845 blend
->sx_mrt0_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
847 if (!att
->colorWriteMask
)
850 blend
->cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
851 if (!att
->blendEnable
) {
852 blend
->cb_blend_control
[i
] = blend_cntl
;
856 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
858 blend_mrt0_is_dual_src
= true;
860 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
861 srcRGB
= VK_BLEND_FACTOR_ONE
;
862 dstRGB
= VK_BLEND_FACTOR_ONE
;
864 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
865 srcA
= VK_BLEND_FACTOR_ONE
;
866 dstA
= VK_BLEND_FACTOR_ONE
;
869 blend_cntl
|= S_028780_ENABLE(1);
871 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
872 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
873 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
874 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
875 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
876 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
877 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
878 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
880 blend
->cb_blend_control
[i
] = blend_cntl
;
882 blend_enable
|= 1 << i
;
884 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
885 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
886 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
887 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
888 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
889 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
890 blend_need_alpha
|= 1 << i
;
892 for (i
= vkblend
->attachmentCount
; i
< 8; i
++)
893 blend
->cb_blend_control
[i
] = 0;
895 if (blend
->cb_target_mask
)
896 blend
->cb_color_control
|= S_028808_MODE(mode
);
898 blend
->cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
900 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
,
901 blend_enable
, blend_need_alpha
, single_cb_enable
, blend_mrt0_is_dual_src
);
904 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
907 case VK_STENCIL_OP_KEEP
:
908 return V_02842C_STENCIL_KEEP
;
909 case VK_STENCIL_OP_ZERO
:
910 return V_02842C_STENCIL_ZERO
;
911 case VK_STENCIL_OP_REPLACE
:
912 return V_02842C_STENCIL_REPLACE_TEST
;
913 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
914 return V_02842C_STENCIL_ADD_CLAMP
;
915 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
916 return V_02842C_STENCIL_SUB_CLAMP
;
917 case VK_STENCIL_OP_INVERT
:
918 return V_02842C_STENCIL_INVERT
;
919 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
920 return V_02842C_STENCIL_ADD_WRAP
;
921 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
922 return V_02842C_STENCIL_SUB_WRAP
;
928 radv_pipeline_init_depth_stencil_state(struct radv_pipeline
*pipeline
,
929 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
930 const struct radv_graphics_pipeline_create_info
*extra
)
932 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
933 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
935 memset(ds
, 0, sizeof(*ds
));
938 ds
->db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
939 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
940 S_028800_ZFUNC(vkds
->depthCompareOp
) |
941 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
943 if (vkds
->stencilTestEnable
) {
944 ds
->db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
945 ds
->db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
946 ds
->db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
947 ds
->db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
948 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
950 ds
->db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
951 ds
->db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
952 ds
->db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
953 ds
->db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
958 ds
->db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
959 ds
->db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
961 ds
->db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
962 ds
->db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
963 ds
->db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
964 ds
->db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
965 ds
->db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
969 static uint32_t si_translate_fill(VkPolygonMode func
)
972 case VK_POLYGON_MODE_FILL
:
973 return V_028814_X_DRAW_TRIANGLES
;
974 case VK_POLYGON_MODE_LINE
:
975 return V_028814_X_DRAW_LINES
;
976 case VK_POLYGON_MODE_POINT
:
977 return V_028814_X_DRAW_POINTS
;
980 return V_028814_X_DRAW_POINTS
;
984 radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline
,
985 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
987 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
988 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
990 memset(raster
, 0, sizeof(*raster
));
992 raster
->spi_interp_control
=
993 S_0286D4_FLAT_SHADE_ENA(1) |
994 S_0286D4_PNT_SPRITE_ENA(1) |
995 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
996 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
997 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
998 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
999 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1001 raster
->pa_cl_vs_out_cntl
= S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
1002 raster
->pa_cl_clip_cntl
= S_028810_PS_UCP_MODE(3) |
1003 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1004 S_028810_ZCLIP_NEAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
1005 S_028810_ZCLIP_FAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
1006 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
1007 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1009 raster
->pa_su_vtx_cntl
=
1010 S_028BE4_PIX_CENTER(1) | // TODO verify
1011 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
1012 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
);
1014 raster
->pa_su_sc_mode_cntl
=
1015 S_028814_FACE(vkraster
->frontFace
) |
1016 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
1017 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
1018 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
1019 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
1020 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
1021 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
1022 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
1023 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
1028 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1029 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1031 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1032 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
1033 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1034 unsigned num_tile_pipes
= pipeline
->device
->instance
->physicalDevice
.rad_info
.num_tile_pipes
;
1035 int ps_iter_samples
= 1;
1036 uint32_t mask
= 0xffff;
1038 ms
->num_samples
= vkms
->rasterizationSamples
;
1040 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.force_persample
) {
1041 ps_iter_samples
= vkms
->rasterizationSamples
;
1044 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1045 ms
->pa_sc_aa_config
= 0;
1046 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1047 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1048 ms
->pa_sc_mode_cntl_1
=
1049 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1050 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1052 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1053 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1054 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1055 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1056 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1057 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1059 if (vkms
->rasterizationSamples
> 1) {
1060 unsigned log_samples
= util_logbase2(vkms
->rasterizationSamples
);
1061 unsigned log_ps_iter_samples
= util_logbase2(util_next_power_of_two(ps_iter_samples
));
1062 ms
->pa_sc_mode_cntl_0
= S_028A48_MSAA_ENABLE(1);
1063 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1064 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1065 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1066 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1067 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1068 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1069 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
1070 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1071 ms
->pa_sc_mode_cntl_1
|= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1074 if (vkms
->alphaToCoverageEnable
)
1075 blend
->db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1077 if (vkms
->pSampleMask
) {
1078 mask
= vkms
->pSampleMask
[0] & 0xffff;
1081 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1082 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1086 si_translate_prim(enum VkPrimitiveTopology topology
)
1089 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1090 return V_008958_DI_PT_POINTLIST
;
1091 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1092 return V_008958_DI_PT_LINELIST
;
1093 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1094 return V_008958_DI_PT_LINESTRIP
;
1095 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1096 return V_008958_DI_PT_TRILIST
;
1097 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1098 return V_008958_DI_PT_TRISTRIP
;
1099 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1100 return V_008958_DI_PT_TRIFAN
;
1101 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1102 return V_008958_DI_PT_LINELIST_ADJ
;
1103 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1104 return V_008958_DI_PT_LINESTRIP_ADJ
;
1105 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1106 return V_008958_DI_PT_TRILIST_ADJ
;
1107 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1108 return V_008958_DI_PT_TRISTRIP_ADJ
;
1109 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1110 return V_008958_DI_PT_PATCH
;
1118 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1121 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1122 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1123 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1124 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1125 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1126 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1127 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1128 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1129 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1130 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1131 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1132 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1133 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1134 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1141 static unsigned si_map_swizzle(unsigned swizzle
)
1145 return V_008F0C_SQ_SEL_Y
;
1147 return V_008F0C_SQ_SEL_Z
;
1149 return V_008F0C_SQ_SEL_W
;
1151 return V_008F0C_SQ_SEL_0
;
1153 return V_008F0C_SQ_SEL_1
;
1154 default: /* VK_SWIZZLE_X */
1155 return V_008F0C_SQ_SEL_X
;
1160 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1161 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1163 radv_cmd_dirty_mask_t states
= RADV_CMD_DIRTY_DYNAMIC_ALL
;
1164 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1165 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1167 pipeline
->dynamic_state
= default_dynamic_state
;
1169 if (pCreateInfo
->pDynamicState
) {
1170 /* Remove all of the states that are marked as dynamic */
1171 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1172 for (uint32_t s
= 0; s
< count
; s
++)
1173 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1176 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1178 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1180 * pViewportState is [...] NULL if the pipeline
1181 * has rasterization disabled.
1183 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1184 assert(pCreateInfo
->pViewportState
);
1186 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1187 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1188 typed_memcpy(dynamic
->viewport
.viewports
,
1189 pCreateInfo
->pViewportState
->pViewports
,
1190 pCreateInfo
->pViewportState
->viewportCount
);
1193 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1194 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1195 typed_memcpy(dynamic
->scissor
.scissors
,
1196 pCreateInfo
->pViewportState
->pScissors
,
1197 pCreateInfo
->pViewportState
->scissorCount
);
1201 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1202 assert(pCreateInfo
->pRasterizationState
);
1203 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1206 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1207 assert(pCreateInfo
->pRasterizationState
);
1208 dynamic
->depth_bias
.bias
=
1209 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1210 dynamic
->depth_bias
.clamp
=
1211 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1212 dynamic
->depth_bias
.slope
=
1213 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1216 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1218 * pColorBlendState is [...] NULL if the pipeline has rasterization
1219 * disabled or if the subpass of the render pass the pipeline is
1220 * created against does not use any color attachments.
1222 bool uses_color_att
= false;
1223 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1224 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1225 uses_color_att
= true;
1230 if (uses_color_att
&& states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
1231 assert(pCreateInfo
->pColorBlendState
);
1232 typed_memcpy(dynamic
->blend_constants
,
1233 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1236 /* If there is no depthstencil attachment, then don't read
1237 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1238 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1239 * no need to override the depthstencil defaults in
1240 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1242 * Section 9.2 of the Vulkan 1.0.15 spec says:
1244 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1245 * disabled or if the subpass of the render pass the pipeline is created
1246 * against does not use a depth/stencil attachment.
1248 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1249 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1250 assert(pCreateInfo
->pDepthStencilState
);
1252 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1253 dynamic
->depth_bounds
.min
=
1254 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1255 dynamic
->depth_bounds
.max
=
1256 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1259 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1260 dynamic
->stencil_compare_mask
.front
=
1261 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1262 dynamic
->stencil_compare_mask
.back
=
1263 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1266 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1267 dynamic
->stencil_write_mask
.front
=
1268 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1269 dynamic
->stencil_write_mask
.back
=
1270 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1273 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1274 dynamic
->stencil_reference
.front
=
1275 pCreateInfo
->pDepthStencilState
->front
.reference
;
1276 dynamic
->stencil_reference
.back
=
1277 pCreateInfo
->pDepthStencilState
->back
.reference
;
1281 pipeline
->dynamic_state_mask
= states
;
1284 static union ac_shader_variant_key
1285 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1287 union ac_shader_variant_key key
;
1288 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1289 pCreateInfo
->pVertexInputState
;
1291 memset(&key
, 0, sizeof(key
));
1292 key
.vs
.instance_rate_inputs
= 0;
1294 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1296 binding
= input_state
->pVertexAttributeDescriptions
[i
].binding
;
1297 if (input_state
->pVertexBindingDescriptions
[binding
].inputRate
)
1298 key
.vs
.instance_rate_inputs
|= 1u << input_state
->pVertexAttributeDescriptions
[i
].location
;
1304 radv_pipeline_init(struct radv_pipeline
*pipeline
,
1305 struct radv_device
*device
,
1306 struct radv_pipeline_cache
*cache
,
1307 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1308 const struct radv_graphics_pipeline_create_info
*extra
,
1309 const VkAllocationCallbacks
*alloc
)
1311 struct radv_shader_module fs_m
= {0};
1314 alloc
= &device
->alloc
;
1316 pipeline
->device
= device
;
1317 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1319 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
1320 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1321 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1322 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1323 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1324 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1325 modules
[stage
] = radv_shader_module_from_handle(pStages
[stage
]->module
);
1328 radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
1331 if (modules
[MESA_SHADER_VERTEX
]) {
1332 union ac_shader_variant_key key
= radv_compute_vs_key(pCreateInfo
);
1334 pipeline
->shaders
[MESA_SHADER_VERTEX
] =
1335 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_VERTEX
],
1336 pStages
[MESA_SHADER_VERTEX
]->pName
,
1338 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
,
1339 pipeline
->layout
, &key
);
1341 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX
);
1344 if (!modules
[MESA_SHADER_FRAGMENT
]) {
1346 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
1347 fs_b
.shader
->info
->name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
1348 fs_m
.nir
= fs_b
.shader
;
1349 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
1352 if (modules
[MESA_SHADER_FRAGMENT
]) {
1353 union ac_shader_variant_key key
;
1354 key
.fs
.col_format
= pipeline
->graphics
.blend
.spi_shader_col_format
;
1355 key
.fs
.is_int8
= radv_pipeline_compute_is_int8(pCreateInfo
);
1357 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[MESA_SHADER_FRAGMENT
];
1359 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
1360 radv_pipeline_compile(pipeline
, cache
, modules
[MESA_SHADER_FRAGMENT
],
1361 stage
? stage
->pName
: "main",
1362 MESA_SHADER_FRAGMENT
,
1363 stage
? stage
->pSpecializationInfo
: NULL
,
1364 pipeline
->layout
, &key
);
1365 pipeline
->active_stages
|= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT
);
1369 ralloc_free(fs_m
.nir
);
1371 radv_pipeline_init_depth_stencil_state(pipeline
, pCreateInfo
, extra
);
1372 radv_pipeline_init_raster_state(pipeline
, pCreateInfo
);
1373 radv_pipeline_init_multisample_state(pipeline
, pCreateInfo
);
1374 pipeline
->graphics
.prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1375 pipeline
->graphics
.gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
1376 if (extra
&& extra
->use_rectlist
) {
1377 pipeline
->graphics
.prim
= V_008958_DI_PT_RECTLIST
;
1378 pipeline
->graphics
.gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1380 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
1382 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1383 pCreateInfo
->pVertexInputState
;
1384 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1385 const VkVertexInputAttributeDescription
*desc
=
1386 &vi_info
->pVertexAttributeDescriptions
[i
];
1387 unsigned loc
= desc
->location
;
1388 const struct vk_format_description
*format_desc
;
1390 uint32_t num_format
, data_format
;
1391 format_desc
= vk_format_description(desc
->format
);
1392 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
1394 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
1395 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
1397 pipeline
->va_rsrc_word3
[loc
] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc
->swizzle
[0])) |
1398 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc
->swizzle
[1])) |
1399 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc
->swizzle
[2])) |
1400 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc
->swizzle
[3])) |
1401 S_008F0C_NUM_FORMAT(num_format
) |
1402 S_008F0C_DATA_FORMAT(data_format
);
1403 pipeline
->va_format_size
[loc
] = format_desc
->block
.bits
/ 8;
1404 pipeline
->va_offset
[loc
] = desc
->offset
;
1405 pipeline
->va_binding
[loc
] = desc
->binding
;
1406 pipeline
->num_vertex_attribs
= MAX2(pipeline
->num_vertex_attribs
, loc
+ 1);
1409 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1410 const VkVertexInputBindingDescription
*desc
=
1411 &vi_info
->pVertexBindingDescriptions
[i
];
1413 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1416 if (device
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
1417 radv_dump_pipeline_stats(device
, pipeline
);
1424 radv_graphics_pipeline_create(
1426 VkPipelineCache _cache
,
1427 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1428 const struct radv_graphics_pipeline_create_info
*extra
,
1429 const VkAllocationCallbacks
*pAllocator
,
1430 VkPipeline
*pPipeline
)
1432 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1433 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
1434 struct radv_pipeline
*pipeline
;
1437 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1438 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1439 if (pipeline
== NULL
)
1440 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1442 memset(pipeline
, 0, sizeof(*pipeline
));
1443 result
= radv_pipeline_init(pipeline
, device
, cache
,
1444 pCreateInfo
, extra
, pAllocator
);
1445 if (result
!= VK_SUCCESS
) {
1446 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1450 *pPipeline
= radv_pipeline_to_handle(pipeline
);
1455 VkResult
radv_CreateGraphicsPipelines(
1457 VkPipelineCache pipelineCache
,
1459 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1460 const VkAllocationCallbacks
* pAllocator
,
1461 VkPipeline
* pPipelines
)
1463 VkResult result
= VK_SUCCESS
;
1466 for (; i
< count
; i
++) {
1468 r
= radv_graphics_pipeline_create(_device
,
1471 NULL
, pAllocator
, &pPipelines
[i
]);
1472 if (r
!= VK_SUCCESS
) {
1474 pPipelines
[i
] = VK_NULL_HANDLE
;
1481 static VkResult
radv_compute_pipeline_create(
1483 VkPipelineCache _cache
,
1484 const VkComputePipelineCreateInfo
* pCreateInfo
,
1485 const VkAllocationCallbacks
* pAllocator
,
1486 VkPipeline
* pPipeline
)
1488 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1489 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
1490 RADV_FROM_HANDLE(radv_shader_module
, module
, pCreateInfo
->stage
.module
);
1491 struct radv_pipeline
*pipeline
;
1493 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1494 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1495 if (pipeline
== NULL
)
1496 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1498 memset(pipeline
, 0, sizeof(*pipeline
));
1499 pipeline
->device
= device
;
1500 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1502 pipeline
->shaders
[MESA_SHADER_COMPUTE
] =
1503 radv_pipeline_compile(pipeline
, cache
, module
,
1504 pCreateInfo
->stage
.pName
,
1505 MESA_SHADER_COMPUTE
,
1506 pCreateInfo
->stage
.pSpecializationInfo
,
1507 pipeline
->layout
, NULL
);
1509 *pPipeline
= radv_pipeline_to_handle(pipeline
);
1511 if (device
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
1512 radv_dump_pipeline_stats(device
, pipeline
);
1516 VkResult
radv_CreateComputePipelines(
1518 VkPipelineCache pipelineCache
,
1520 const VkComputePipelineCreateInfo
* pCreateInfos
,
1521 const VkAllocationCallbacks
* pAllocator
,
1522 VkPipeline
* pPipelines
)
1524 VkResult result
= VK_SUCCESS
;
1527 for (; i
< count
; i
++) {
1529 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
1531 pAllocator
, &pPipelines
[i
]);
1532 if (r
!= VK_SUCCESS
) {
1534 pPipelines
[i
] = VK_NULL_HANDLE
;