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radv: implement out-of-order rasterization when it's safe on VI+
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t blend_enable_4bit;
54 uint32_t need_src_alpha;
55
56 uint32_t cb_color_control;
57 uint32_t cb_target_mask;
58 uint32_t cb_target_enabled_4bit;
59 uint32_t sx_mrt_blend_opt[8];
60 uint32_t cb_blend_control[8];
61
62 uint32_t spi_shader_col_format;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 struct radv_gs_state {
93 uint32_t vgt_gs_onchip_cntl;
94 uint32_t vgt_gs_max_prims_per_subgroup;
95 uint32_t vgt_esgs_ring_itemsize;
96 uint32_t lds_size;
97 };
98
99 static void
100 radv_pipeline_destroy(struct radv_device *device,
101 struct radv_pipeline *pipeline,
102 const VkAllocationCallbacks* allocator)
103 {
104 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
105 if (pipeline->shaders[i])
106 radv_shader_variant_destroy(device, pipeline->shaders[i]);
107
108 if (pipeline->gs_copy_shader)
109 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
110
111 if(pipeline->cs.buf)
112 free(pipeline->cs.buf);
113 vk_free2(&device->alloc, allocator, pipeline);
114 }
115
116 void radv_DestroyPipeline(
117 VkDevice _device,
118 VkPipeline _pipeline,
119 const VkAllocationCallbacks* pAllocator)
120 {
121 RADV_FROM_HANDLE(radv_device, device, _device);
122 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
123
124 if (!_pipeline)
125 return;
126
127 radv_pipeline_destroy(device, pipeline, pAllocator);
128 }
129
130 static uint32_t get_hash_flags(struct radv_device *device)
131 {
132 uint32_t hash_flags = 0;
133
134 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
135 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
136 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
137 hash_flags |= RADV_HASH_SHADER_SISCHED;
138 return hash_flags;
139 }
140
141 static VkResult
142 radv_pipeline_scratch_init(struct radv_device *device,
143 struct radv_pipeline *pipeline)
144 {
145 unsigned scratch_bytes_per_wave = 0;
146 unsigned max_waves = 0;
147 unsigned min_waves = 1;
148
149 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
150 if (pipeline->shaders[i]) {
151 unsigned max_stage_waves = device->scratch_waves;
152
153 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
154 pipeline->shaders[i]->config.scratch_bytes_per_wave);
155
156 max_stage_waves = MIN2(max_stage_waves,
157 4 * device->physical_device->rad_info.num_good_compute_units *
158 (256 / pipeline->shaders[i]->config.num_vgprs));
159 max_waves = MAX2(max_waves, max_stage_waves);
160 }
161 }
162
163 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
164 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
165 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
167 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
168 }
169
170 if (scratch_bytes_per_wave)
171 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
172
173 if (scratch_bytes_per_wave && max_waves < min_waves) {
174 /* Not really true at this moment, but will be true on first
175 * execution. Avoid having hanging shaders. */
176 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
177 }
178 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
179 pipeline->max_waves = max_waves;
180 return VK_SUCCESS;
181 }
182
183 static uint32_t si_translate_blend_function(VkBlendOp op)
184 {
185 switch (op) {
186 case VK_BLEND_OP_ADD:
187 return V_028780_COMB_DST_PLUS_SRC;
188 case VK_BLEND_OP_SUBTRACT:
189 return V_028780_COMB_SRC_MINUS_DST;
190 case VK_BLEND_OP_REVERSE_SUBTRACT:
191 return V_028780_COMB_DST_MINUS_SRC;
192 case VK_BLEND_OP_MIN:
193 return V_028780_COMB_MIN_DST_SRC;
194 case VK_BLEND_OP_MAX:
195 return V_028780_COMB_MAX_DST_SRC;
196 default:
197 return 0;
198 }
199 }
200
201 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
202 {
203 switch (factor) {
204 case VK_BLEND_FACTOR_ZERO:
205 return V_028780_BLEND_ZERO;
206 case VK_BLEND_FACTOR_ONE:
207 return V_028780_BLEND_ONE;
208 case VK_BLEND_FACTOR_SRC_COLOR:
209 return V_028780_BLEND_SRC_COLOR;
210 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
211 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
212 case VK_BLEND_FACTOR_DST_COLOR:
213 return V_028780_BLEND_DST_COLOR;
214 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
215 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
216 case VK_BLEND_FACTOR_SRC_ALPHA:
217 return V_028780_BLEND_SRC_ALPHA;
218 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
219 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
220 case VK_BLEND_FACTOR_DST_ALPHA:
221 return V_028780_BLEND_DST_ALPHA;
222 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
223 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
224 case VK_BLEND_FACTOR_CONSTANT_COLOR:
225 return V_028780_BLEND_CONSTANT_COLOR;
226 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
227 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
228 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
229 return V_028780_BLEND_CONSTANT_ALPHA;
230 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
231 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
232 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
233 return V_028780_BLEND_SRC_ALPHA_SATURATE;
234 case VK_BLEND_FACTOR_SRC1_COLOR:
235 return V_028780_BLEND_SRC1_COLOR;
236 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
237 return V_028780_BLEND_INV_SRC1_COLOR;
238 case VK_BLEND_FACTOR_SRC1_ALPHA:
239 return V_028780_BLEND_SRC1_ALPHA;
240 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
241 return V_028780_BLEND_INV_SRC1_ALPHA;
242 default:
243 return 0;
244 }
245 }
246
247 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
248 {
249 switch (op) {
250 case VK_BLEND_OP_ADD:
251 return V_028760_OPT_COMB_ADD;
252 case VK_BLEND_OP_SUBTRACT:
253 return V_028760_OPT_COMB_SUBTRACT;
254 case VK_BLEND_OP_REVERSE_SUBTRACT:
255 return V_028760_OPT_COMB_REVSUBTRACT;
256 case VK_BLEND_OP_MIN:
257 return V_028760_OPT_COMB_MIN;
258 case VK_BLEND_OP_MAX:
259 return V_028760_OPT_COMB_MAX;
260 default:
261 return V_028760_OPT_COMB_BLEND_DISABLED;
262 }
263 }
264
265 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
266 {
267 switch (factor) {
268 case VK_BLEND_FACTOR_ZERO:
269 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
270 case VK_BLEND_FACTOR_ONE:
271 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
272 case VK_BLEND_FACTOR_SRC_COLOR:
273 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
274 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
275 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
276 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
277 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
278 case VK_BLEND_FACTOR_SRC_ALPHA:
279 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
280 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
281 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
282 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
283 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
284 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
285 default:
286 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
287 }
288 }
289
290 /**
291 * Get rid of DST in the blend factors by commuting the operands:
292 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
293 */
294 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
295 unsigned *dst_factor, unsigned expected_dst,
296 unsigned replacement_src)
297 {
298 if (*src_factor == expected_dst &&
299 *dst_factor == VK_BLEND_FACTOR_ZERO) {
300 *src_factor = VK_BLEND_FACTOR_ZERO;
301 *dst_factor = replacement_src;
302
303 /* Commuting the operands requires reversing subtractions. */
304 if (*func == VK_BLEND_OP_SUBTRACT)
305 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
306 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
307 *func = VK_BLEND_OP_SUBTRACT;
308 }
309 }
310
311 static bool si_blend_factor_uses_dst(unsigned factor)
312 {
313 return factor == VK_BLEND_FACTOR_DST_COLOR ||
314 factor == VK_BLEND_FACTOR_DST_ALPHA ||
315 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
316 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
317 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
318 }
319
320 static bool is_dual_src(VkBlendFactor factor)
321 {
322 switch (factor) {
323 case VK_BLEND_FACTOR_SRC1_COLOR:
324 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
325 case VK_BLEND_FACTOR_SRC1_ALPHA:
326 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
327 return true;
328 default:
329 return false;
330 }
331 }
332
333 static unsigned si_choose_spi_color_format(VkFormat vk_format,
334 bool blend_enable,
335 bool blend_need_alpha)
336 {
337 const struct vk_format_description *desc = vk_format_description(vk_format);
338 unsigned format, ntype, swap;
339
340 /* Alpha is needed for alpha-to-coverage.
341 * Blending may be with or without alpha.
342 */
343 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
344 unsigned alpha = 0; /* exports alpha, but may not support blending */
345 unsigned blend = 0; /* supports blending, but may not export alpha */
346 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
347
348 format = radv_translate_colorformat(vk_format);
349 ntype = radv_translate_color_numformat(vk_format, desc,
350 vk_format_get_first_non_void_channel(vk_format));
351 swap = radv_translate_colorswap(vk_format, false);
352
353 /* Choose the SPI color formats. These are required values for Stoney/RB+.
354 * Other chips have multiple choices, though they are not necessarily better.
355 */
356 switch (format) {
357 case V_028C70_COLOR_5_6_5:
358 case V_028C70_COLOR_1_5_5_5:
359 case V_028C70_COLOR_5_5_5_1:
360 case V_028C70_COLOR_4_4_4_4:
361 case V_028C70_COLOR_10_11_11:
362 case V_028C70_COLOR_11_11_10:
363 case V_028C70_COLOR_8:
364 case V_028C70_COLOR_8_8:
365 case V_028C70_COLOR_8_8_8_8:
366 case V_028C70_COLOR_10_10_10_2:
367 case V_028C70_COLOR_2_10_10_10:
368 if (ntype == V_028C70_NUMBER_UINT)
369 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
370 else if (ntype == V_028C70_NUMBER_SINT)
371 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
372 else
373 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
374 break;
375
376 case V_028C70_COLOR_16:
377 case V_028C70_COLOR_16_16:
378 case V_028C70_COLOR_16_16_16_16:
379 if (ntype == V_028C70_NUMBER_UNORM ||
380 ntype == V_028C70_NUMBER_SNORM) {
381 /* UNORM16 and SNORM16 don't support blending */
382 if (ntype == V_028C70_NUMBER_UNORM)
383 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
384 else
385 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
386
387 /* Use 32 bits per channel for blending. */
388 if (format == V_028C70_COLOR_16) {
389 if (swap == V_028C70_SWAP_STD) { /* R */
390 blend = V_028714_SPI_SHADER_32_R;
391 blend_alpha = V_028714_SPI_SHADER_32_AR;
392 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
393 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
394 else
395 assert(0);
396 } else if (format == V_028C70_COLOR_16_16) {
397 if (swap == V_028C70_SWAP_STD) { /* RG */
398 blend = V_028714_SPI_SHADER_32_GR;
399 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
400 } else if (swap == V_028C70_SWAP_ALT) /* RA */
401 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
402 else
403 assert(0);
404 } else /* 16_16_16_16 */
405 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
406 } else if (ntype == V_028C70_NUMBER_UINT)
407 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
408 else if (ntype == V_028C70_NUMBER_SINT)
409 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
410 else if (ntype == V_028C70_NUMBER_FLOAT)
411 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
412 else
413 assert(0);
414 break;
415
416 case V_028C70_COLOR_32:
417 if (swap == V_028C70_SWAP_STD) { /* R */
418 blend = normal = V_028714_SPI_SHADER_32_R;
419 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
420 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
421 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
422 else
423 assert(0);
424 break;
425
426 case V_028C70_COLOR_32_32:
427 if (swap == V_028C70_SWAP_STD) { /* RG */
428 blend = normal = V_028714_SPI_SHADER_32_GR;
429 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
430 } else if (swap == V_028C70_SWAP_ALT) /* RA */
431 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
432 else
433 assert(0);
434 break;
435
436 case V_028C70_COLOR_32_32_32_32:
437 case V_028C70_COLOR_8_24:
438 case V_028C70_COLOR_24_8:
439 case V_028C70_COLOR_X24_8_32_FLOAT:
440 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
441 break;
442
443 default:
444 unreachable("unhandled blend format");
445 }
446
447 if (blend_enable && blend_need_alpha)
448 return blend_alpha;
449 else if(blend_need_alpha)
450 return alpha;
451 else if(blend_enable)
452 return blend;
453 else
454 return normal;
455 }
456
457 static void
458 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
459 const VkGraphicsPipelineCreateInfo *pCreateInfo,
460 struct radv_blend_state *blend)
461 {
462 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
463 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
464 unsigned col_format = 0;
465
466 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
467 unsigned cf;
468
469 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
470 cf = V_028714_SPI_SHADER_ZERO;
471 } else {
472 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
473 bool blend_enable =
474 blend->blend_enable_4bit & (0xfu << (i * 4));
475
476 cf = si_choose_spi_color_format(attachment->format,
477 blend_enable,
478 blend->need_src_alpha & (1 << i));
479 }
480
481 col_format |= cf << (4 * i);
482 }
483
484 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
485
486 if (blend->mrt0_is_dual_src)
487 col_format |= (col_format & 0xf) << 4;
488 blend->spi_shader_col_format = col_format;
489 }
490
491 static bool
492 format_is_int8(VkFormat format)
493 {
494 const struct vk_format_description *desc = vk_format_description(format);
495 int channel = vk_format_get_first_non_void_channel(format);
496
497 return channel >= 0 && desc->channel[channel].pure_integer &&
498 desc->channel[channel].size == 8;
499 }
500
501 static bool
502 format_is_int10(VkFormat format)
503 {
504 const struct vk_format_description *desc = vk_format_description(format);
505
506 if (desc->nr_channels != 4)
507 return false;
508 for (unsigned i = 0; i < 4; i++) {
509 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
510 return true;
511 }
512 return false;
513 }
514
515 unsigned radv_format_meta_fs_key(VkFormat format)
516 {
517 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
518 bool is_int8 = format_is_int8(format);
519 bool is_int10 = format_is_int10(format);
520
521 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
522 }
523
524 static void
525 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
526 unsigned *is_int8, unsigned *is_int10)
527 {
528 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
529 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
530 *is_int8 = 0;
531 *is_int10 = 0;
532
533 for (unsigned i = 0; i < subpass->color_count; ++i) {
534 struct radv_render_pass_attachment *attachment;
535
536 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
537 continue;
538
539 attachment = pass->attachments + subpass->color_attachments[i].attachment;
540
541 if (format_is_int8(attachment->format))
542 *is_int8 |= 1 << i;
543 if (format_is_int10(attachment->format))
544 *is_int10 |= 1 << i;
545 }
546 }
547
548 static void
549 radv_blend_check_commutativity(struct radv_blend_state *blend,
550 VkBlendOp op, VkBlendFactor src,
551 VkBlendFactor dst, unsigned chanmask)
552 {
553 /* Src factor is allowed when it does not depend on Dst. */
554 static const uint32_t src_allowed =
555 (1u << VK_BLEND_FACTOR_ONE) |
556 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
557 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
558 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
559 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
560 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
561 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
562 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
563 (1u << VK_BLEND_FACTOR_ZERO) |
564 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
565 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
566 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
567 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
568 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
569 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
570
571 if (dst == VK_BLEND_FACTOR_ONE &&
572 (src_allowed && (1u << src))) {
573 /* Addition is commutative, but floating point addition isn't
574 * associative: subtle changes can be introduced via different
575 * rounding. Be conservative, only enable for min and max.
576 */
577 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
578 blend->commutative_4bit |= chanmask;
579 }
580 }
581
582 static struct radv_blend_state
583 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
584 const VkGraphicsPipelineCreateInfo *pCreateInfo,
585 const struct radv_graphics_pipeline_create_info *extra)
586 {
587 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
588 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
589 struct radv_blend_state blend = {0};
590 unsigned mode = V_028808_CB_NORMAL;
591 int i;
592
593 if (!vkblend)
594 return blend;
595
596 if (extra && extra->custom_blend_mode) {
597 blend.single_cb_enable = true;
598 mode = extra->custom_blend_mode;
599 }
600 blend.cb_color_control = 0;
601 if (vkblend->logicOpEnable)
602 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
603 else
604 blend.cb_color_control |= S_028808_ROP3(0xcc);
605
606 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
607 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
608 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
609 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
610
611 if (vkms && vkms->alphaToCoverageEnable) {
612 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
613 }
614
615 blend.cb_target_mask = 0;
616 for (i = 0; i < vkblend->attachmentCount; i++) {
617 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
618 unsigned blend_cntl = 0;
619 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
620 VkBlendOp eqRGB = att->colorBlendOp;
621 VkBlendFactor srcRGB = att->srcColorBlendFactor;
622 VkBlendFactor dstRGB = att->dstColorBlendFactor;
623 VkBlendOp eqA = att->alphaBlendOp;
624 VkBlendFactor srcA = att->srcAlphaBlendFactor;
625 VkBlendFactor dstA = att->dstAlphaBlendFactor;
626
627 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
628
629 if (!att->colorWriteMask)
630 continue;
631
632 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
633 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
634 if (!att->blendEnable) {
635 blend.cb_blend_control[i] = blend_cntl;
636 continue;
637 }
638
639 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
640 if (i == 0)
641 blend.mrt0_is_dual_src = true;
642
643 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
644 srcRGB = VK_BLEND_FACTOR_ONE;
645 dstRGB = VK_BLEND_FACTOR_ONE;
646 }
647 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
648 srcA = VK_BLEND_FACTOR_ONE;
649 dstA = VK_BLEND_FACTOR_ONE;
650 }
651
652 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
653 0x7 << (4 * i));
654 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
655 0x8 << (4 * i));
656
657 /* Blending optimizations for RB+.
658 * These transformations don't change the behavior.
659 *
660 * First, get rid of DST in the blend factors:
661 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
662 */
663 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
664 VK_BLEND_FACTOR_DST_COLOR,
665 VK_BLEND_FACTOR_SRC_COLOR);
666
667 si_blend_remove_dst(&eqA, &srcA, &dstA,
668 VK_BLEND_FACTOR_DST_COLOR,
669 VK_BLEND_FACTOR_SRC_COLOR);
670
671 si_blend_remove_dst(&eqA, &srcA, &dstA,
672 VK_BLEND_FACTOR_DST_ALPHA,
673 VK_BLEND_FACTOR_SRC_ALPHA);
674
675 /* Look up the ideal settings from tables. */
676 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
677 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
678 srcA_opt = si_translate_blend_opt_factor(srcA, true);
679 dstA_opt = si_translate_blend_opt_factor(dstA, true);
680
681 /* Handle interdependencies. */
682 if (si_blend_factor_uses_dst(srcRGB))
683 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
684 if (si_blend_factor_uses_dst(srcA))
685 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
686
687 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
688 (dstRGB == VK_BLEND_FACTOR_ZERO ||
689 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
690 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
691 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
692
693 /* Set the final value. */
694 blend.sx_mrt_blend_opt[i] =
695 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
696 S_028760_COLOR_DST_OPT(dstRGB_opt) |
697 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
698 S_028760_ALPHA_SRC_OPT(srcA_opt) |
699 S_028760_ALPHA_DST_OPT(dstA_opt) |
700 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
701 blend_cntl |= S_028780_ENABLE(1);
702
703 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
704 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
705 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
706 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
707 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
708 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
709 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
710 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
711 }
712 blend.cb_blend_control[i] = blend_cntl;
713
714 blend.blend_enable_4bit |= 0xfu << (i * 4);
715
716 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
717 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
718 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
719 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
720 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
721 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
722 blend.need_src_alpha |= 1 << i;
723 }
724 for (i = vkblend->attachmentCount; i < 8; i++) {
725 blend.cb_blend_control[i] = 0;
726 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
727 }
728
729 if (pipeline->device->physical_device->has_rbplus) {
730 /* Disable RB+ blend optimizations for dual source blending. */
731 if (blend.mrt0_is_dual_src) {
732 for (i = 0; i < 8; i++) {
733 blend.sx_mrt_blend_opt[i] =
734 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
735 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
736 }
737 }
738
739 /* RB+ doesn't work with dual source blending, logic op and
740 * RESOLVE.
741 */
742 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
743 mode == V_028808_CB_RESOLVE)
744 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
745 }
746
747 if (blend.cb_target_mask)
748 blend.cb_color_control |= S_028808_MODE(mode);
749 else
750 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
751
752 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
753 return blend;
754 }
755
756 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
757 {
758 switch (op) {
759 case VK_STENCIL_OP_KEEP:
760 return V_02842C_STENCIL_KEEP;
761 case VK_STENCIL_OP_ZERO:
762 return V_02842C_STENCIL_ZERO;
763 case VK_STENCIL_OP_REPLACE:
764 return V_02842C_STENCIL_REPLACE_TEST;
765 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
766 return V_02842C_STENCIL_ADD_CLAMP;
767 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
768 return V_02842C_STENCIL_SUB_CLAMP;
769 case VK_STENCIL_OP_INVERT:
770 return V_02842C_STENCIL_INVERT;
771 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
772 return V_02842C_STENCIL_ADD_WRAP;
773 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
774 return V_02842C_STENCIL_SUB_WRAP;
775 default:
776 return 0;
777 }
778 }
779
780 static uint32_t si_translate_fill(VkPolygonMode func)
781 {
782 switch(func) {
783 case VK_POLYGON_MODE_FILL:
784 return V_028814_X_DRAW_TRIANGLES;
785 case VK_POLYGON_MODE_LINE:
786 return V_028814_X_DRAW_LINES;
787 case VK_POLYGON_MODE_POINT:
788 return V_028814_X_DRAW_POINTS;
789 default:
790 assert(0);
791 return V_028814_X_DRAW_POINTS;
792 }
793 }
794
795 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
796 {
797 uint32_t num_samples = vkms->rasterizationSamples;
798 uint32_t ps_iter_samples = 1;
799
800 if (vkms->sampleShadingEnable) {
801 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
802 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
803 }
804 return ps_iter_samples;
805 }
806
807 static bool
808 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
809 {
810 return pCreateInfo->depthTestEnable &&
811 pCreateInfo->depthWriteEnable &&
812 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
813 }
814
815 static bool
816 radv_writes_stencil(const VkStencilOpState *state)
817 {
818 return state->writeMask &&
819 (state->failOp != VK_STENCIL_OP_KEEP ||
820 state->passOp != VK_STENCIL_OP_KEEP ||
821 state->depthFailOp != VK_STENCIL_OP_KEEP);
822 }
823
824 static bool
825 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
826 {
827 return pCreateInfo->stencilTestEnable &&
828 (radv_writes_stencil(&pCreateInfo->front) ||
829 radv_writes_stencil(&pCreateInfo->back));
830 }
831
832 static bool
833 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
834 {
835 return radv_is_depth_write_enabled(pCreateInfo) ||
836 radv_is_stencil_write_enabled(pCreateInfo);
837 }
838
839 static bool
840 radv_order_invariant_stencil_op(VkStencilOp op)
841 {
842 /* REPLACE is normally order invariant, except when the stencil
843 * reference value is written by the fragment shader. Tracking this
844 * interaction does not seem worth the effort, so be conservative.
845 */
846 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
847 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
848 op != VK_STENCIL_OP_REPLACE;
849 }
850
851 static bool
852 radv_order_invariant_stencil_state(const VkStencilOpState *state)
853 {
854 /* Compute whether, assuming Z writes are disabled, this stencil state
855 * is order invariant in the sense that the set of passing fragments as
856 * well as the final stencil buffer result does not depend on the order
857 * of fragments.
858 */
859 return !state->writeMask ||
860 /* The following assumes that Z writes are disabled. */
861 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
862 radv_order_invariant_stencil_op(state->passOp) &&
863 radv_order_invariant_stencil_op(state->depthFailOp)) ||
864 (state->compareOp == VK_COMPARE_OP_NEVER &&
865 radv_order_invariant_stencil_op(state->failOp));
866 }
867
868 static bool
869 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
870 struct radv_blend_state *blend,
871 const VkGraphicsPipelineCreateInfo *pCreateInfo)
872 {
873 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
874 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
875 unsigned colormask = blend->cb_target_enabled_4bit;
876
877 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
878 return false;
879
880 /* Be conservative if a logic operation is enabled with color buffers. */
881 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
882 return false;
883
884 /* Default depth/stencil invariance when no attachment is bound. */
885 struct radv_dsa_order_invariance dsa_order_invariant = {
886 .zs = true, .pass_set = true
887 };
888
889 if (pCreateInfo->pDepthStencilState &&
890 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
891 const VkPipelineDepthStencilStateCreateInfo *vkds =
892 pCreateInfo->pDepthStencilState;
893 struct radv_render_pass_attachment *attachment =
894 pass->attachments + subpass->depth_stencil_attachment.attachment;
895 bool has_stencil = vk_format_is_stencil(attachment->format);
896 struct radv_dsa_order_invariance order_invariance[2];
897 struct radv_shader_variant *ps =
898 pipeline->shaders[MESA_SHADER_FRAGMENT];
899
900 /* Compute depth/stencil order invariance in order to know if
901 * it's safe to enable out-of-order.
902 */
903 bool zfunc_is_ordered =
904 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
905 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
906 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
907 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
908 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
909
910 bool nozwrite_and_order_invariant_stencil =
911 !radv_is_ds_write_enabled(vkds) ||
912 (!radv_is_depth_write_enabled(vkds) &&
913 radv_order_invariant_stencil_state(&vkds->front) &&
914 radv_order_invariant_stencil_state(&vkds->back));
915
916 order_invariance[1].zs =
917 nozwrite_and_order_invariant_stencil ||
918 (!radv_is_stencil_write_enabled(vkds) &&
919 zfunc_is_ordered);
920 order_invariance[0].zs =
921 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
922
923 order_invariance[1].pass_set =
924 nozwrite_and_order_invariant_stencil ||
925 (!radv_is_stencil_write_enabled(vkds) &&
926 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
927 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
928 order_invariance[0].pass_set =
929 !radv_is_depth_write_enabled(vkds) ||
930 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
931 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
932
933 dsa_order_invariant = order_invariance[has_stencil];
934 if (!dsa_order_invariant.zs)
935 return false;
936
937 /* The set of PS invocations is always order invariant,
938 * except when early Z/S tests are requested.
939 */
940 if (ps &&
941 ps->info.info.ps.writes_memory &&
942 ps->info.fs.early_fragment_test &&
943 !dsa_order_invariant.pass_set)
944 return false;
945
946 /* Determine if out-of-order rasterization should be disabled
947 * when occlusion queries are used.
948 */
949 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
950 !dsa_order_invariant.pass_set;
951 }
952
953 /* No color buffers are enabled for writing. */
954 if (!colormask)
955 return true;
956
957 unsigned blendmask = colormask & blend->blend_enable_4bit;
958
959 if (blendmask) {
960 /* Only commutative blending. */
961 if (blendmask & ~blend->commutative_4bit)
962 return false;
963
964 if (!dsa_order_invariant.pass_set)
965 return false;
966 }
967
968 if (colormask & ~blendmask)
969 return false;
970
971 return true;
972 }
973
974 static void
975 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
976 struct radv_blend_state *blend,
977 const VkGraphicsPipelineCreateInfo *pCreateInfo)
978 {
979 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
980 struct radv_multisample_state *ms = &pipeline->graphics.ms;
981 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
982 bool out_of_order_rast = false;
983 int ps_iter_samples = 1;
984 uint32_t mask = 0xffff;
985
986 if (vkms)
987 ms->num_samples = vkms->rasterizationSamples;
988 else
989 ms->num_samples = 1;
990
991 if (vkms)
992 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
993 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
994 ps_iter_samples = ms->num_samples;
995 }
996
997 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
998 ms->pa_sc_aa_config = 0;
999 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1000 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1001 ms->pa_sc_mode_cntl_1 =
1002 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1003 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1004 /* always 1: */
1005 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1006 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1007 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1008 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1009 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1010 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1011 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1012 S_028A48_VPORT_SCISSOR_ENABLE(1);
1013
1014 if (ms->num_samples > 1) {
1015 unsigned log_samples = util_logbase2(ms->num_samples);
1016 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1017 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1018 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1019 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1020 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1021 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1022 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1023 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1024 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1025 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1026 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1027 if (ps_iter_samples > 1)
1028 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1029 }
1030
1031 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1032 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1033 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1034 /* Out-of-order rasterization is explicitly enabled by the
1035 * application.
1036 */
1037 out_of_order_rast = true;
1038 } else {
1039 /* Determine if the driver can enable out-of-order
1040 * rasterization internally.
1041 */
1042 out_of_order_rast =
1043 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1044 }
1045
1046 if (out_of_order_rast) {
1047 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1048 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1049 }
1050
1051 if (vkms && vkms->pSampleMask) {
1052 mask = vkms->pSampleMask[0] & 0xffff;
1053 }
1054
1055 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1056 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1057 }
1058
1059 static bool
1060 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1061 {
1062 switch (topology) {
1063 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1064 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1065 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1066 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1067 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1068 return false;
1069 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1070 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1071 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1072 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1073 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1074 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1075 return true;
1076 default:
1077 unreachable("unhandled primitive type");
1078 }
1079 }
1080
1081 static uint32_t
1082 si_translate_prim(enum VkPrimitiveTopology topology)
1083 {
1084 switch (topology) {
1085 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1086 return V_008958_DI_PT_POINTLIST;
1087 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1088 return V_008958_DI_PT_LINELIST;
1089 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1090 return V_008958_DI_PT_LINESTRIP;
1091 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1092 return V_008958_DI_PT_TRILIST;
1093 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1094 return V_008958_DI_PT_TRISTRIP;
1095 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1096 return V_008958_DI_PT_TRIFAN;
1097 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1098 return V_008958_DI_PT_LINELIST_ADJ;
1099 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1100 return V_008958_DI_PT_LINESTRIP_ADJ;
1101 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1102 return V_008958_DI_PT_TRILIST_ADJ;
1103 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1104 return V_008958_DI_PT_TRISTRIP_ADJ;
1105 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1106 return V_008958_DI_PT_PATCH;
1107 default:
1108 assert(0);
1109 return 0;
1110 }
1111 }
1112
1113 static uint32_t
1114 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1115 {
1116 switch (gl_prim) {
1117 case 0: /* GL_POINTS */
1118 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1119 case 1: /* GL_LINES */
1120 case 3: /* GL_LINE_STRIP */
1121 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1122 case 0x8E7A: /* GL_ISOLINES */
1123 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1124
1125 case 4: /* GL_TRIANGLES */
1126 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1127 case 5: /* GL_TRIANGLE_STRIP */
1128 case 7: /* GL_QUADS */
1129 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1130 default:
1131 assert(0);
1132 return 0;
1133 }
1134 }
1135
1136 static uint32_t
1137 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1138 {
1139 switch (topology) {
1140 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1141 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1142 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1143 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1144 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1145 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1146 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1147 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1148 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1149 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1150 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1151 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1152 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1153 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1154 default:
1155 assert(0);
1156 return 0;
1157 }
1158 }
1159
1160 static unsigned si_map_swizzle(unsigned swizzle)
1161 {
1162 switch (swizzle) {
1163 case VK_SWIZZLE_Y:
1164 return V_008F0C_SQ_SEL_Y;
1165 case VK_SWIZZLE_Z:
1166 return V_008F0C_SQ_SEL_Z;
1167 case VK_SWIZZLE_W:
1168 return V_008F0C_SQ_SEL_W;
1169 case VK_SWIZZLE_0:
1170 return V_008F0C_SQ_SEL_0;
1171 case VK_SWIZZLE_1:
1172 return V_008F0C_SQ_SEL_1;
1173 default: /* VK_SWIZZLE_X */
1174 return V_008F0C_SQ_SEL_X;
1175 }
1176 }
1177
1178
1179 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1180 {
1181 switch(state) {
1182 case VK_DYNAMIC_STATE_VIEWPORT:
1183 return RADV_DYNAMIC_VIEWPORT;
1184 case VK_DYNAMIC_STATE_SCISSOR:
1185 return RADV_DYNAMIC_SCISSOR;
1186 case VK_DYNAMIC_STATE_LINE_WIDTH:
1187 return RADV_DYNAMIC_LINE_WIDTH;
1188 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1189 return RADV_DYNAMIC_DEPTH_BIAS;
1190 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1191 return RADV_DYNAMIC_BLEND_CONSTANTS;
1192 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1193 return RADV_DYNAMIC_DEPTH_BOUNDS;
1194 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1195 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1196 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1197 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1198 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1199 return RADV_DYNAMIC_STENCIL_REFERENCE;
1200 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1201 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1202 default:
1203 unreachable("Unhandled dynamic state");
1204 }
1205 }
1206
1207 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1208 {
1209 uint32_t states = RADV_DYNAMIC_ALL;
1210
1211 /* If rasterization is disabled we do not care about any of the dynamic states,
1212 * since they are all rasterization related only. */
1213 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1214 return 0;
1215
1216 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1217 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1218
1219 if (!pCreateInfo->pDepthStencilState ||
1220 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1221 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1222
1223 if (!pCreateInfo->pDepthStencilState ||
1224 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1225 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1226 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1227 RADV_DYNAMIC_STENCIL_REFERENCE);
1228
1229 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1230 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1231
1232 /* TODO: blend constants & line width. */
1233
1234 return states;
1235 }
1236
1237
1238 static void
1239 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1240 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1241 {
1242 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1243 uint32_t states = needed_states;
1244 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1245 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1246
1247 pipeline->dynamic_state = default_dynamic_state;
1248 pipeline->graphics.needed_dynamic_state = needed_states;
1249
1250 if (pCreateInfo->pDynamicState) {
1251 /* Remove all of the states that are marked as dynamic */
1252 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1253 for (uint32_t s = 0; s < count; s++)
1254 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1255 }
1256
1257 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1258
1259 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1260 assert(pCreateInfo->pViewportState);
1261
1262 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1263 if (states & RADV_DYNAMIC_VIEWPORT) {
1264 typed_memcpy(dynamic->viewport.viewports,
1265 pCreateInfo->pViewportState->pViewports,
1266 pCreateInfo->pViewportState->viewportCount);
1267 }
1268 }
1269
1270 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1271 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1272 if (states & RADV_DYNAMIC_SCISSOR) {
1273 typed_memcpy(dynamic->scissor.scissors,
1274 pCreateInfo->pViewportState->pScissors,
1275 pCreateInfo->pViewportState->scissorCount);
1276 }
1277 }
1278
1279 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1280 assert(pCreateInfo->pRasterizationState);
1281 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1282 }
1283
1284 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1285 assert(pCreateInfo->pRasterizationState);
1286 dynamic->depth_bias.bias =
1287 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1288 dynamic->depth_bias.clamp =
1289 pCreateInfo->pRasterizationState->depthBiasClamp;
1290 dynamic->depth_bias.slope =
1291 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1292 }
1293
1294 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1295 *
1296 * pColorBlendState is [...] NULL if the pipeline has rasterization
1297 * disabled or if the subpass of the render pass the pipeline is
1298 * created against does not use any color attachments.
1299 */
1300 bool uses_color_att = false;
1301 for (unsigned i = 0; i < subpass->color_count; ++i) {
1302 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1303 uses_color_att = true;
1304 break;
1305 }
1306 }
1307
1308 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1309 assert(pCreateInfo->pColorBlendState);
1310 typed_memcpy(dynamic->blend_constants,
1311 pCreateInfo->pColorBlendState->blendConstants, 4);
1312 }
1313
1314 /* If there is no depthstencil attachment, then don't read
1315 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1316 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1317 * no need to override the depthstencil defaults in
1318 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1319 *
1320 * Section 9.2 of the Vulkan 1.0.15 spec says:
1321 *
1322 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1323 * disabled or if the subpass of the render pass the pipeline is created
1324 * against does not use a depth/stencil attachment.
1325 */
1326 if (needed_states &&
1327 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1328 assert(pCreateInfo->pDepthStencilState);
1329
1330 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1331 dynamic->depth_bounds.min =
1332 pCreateInfo->pDepthStencilState->minDepthBounds;
1333 dynamic->depth_bounds.max =
1334 pCreateInfo->pDepthStencilState->maxDepthBounds;
1335 }
1336
1337 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1338 dynamic->stencil_compare_mask.front =
1339 pCreateInfo->pDepthStencilState->front.compareMask;
1340 dynamic->stencil_compare_mask.back =
1341 pCreateInfo->pDepthStencilState->back.compareMask;
1342 }
1343
1344 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1345 dynamic->stencil_write_mask.front =
1346 pCreateInfo->pDepthStencilState->front.writeMask;
1347 dynamic->stencil_write_mask.back =
1348 pCreateInfo->pDepthStencilState->back.writeMask;
1349 }
1350
1351 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1352 dynamic->stencil_reference.front =
1353 pCreateInfo->pDepthStencilState->front.reference;
1354 dynamic->stencil_reference.back =
1355 pCreateInfo->pDepthStencilState->back.reference;
1356 }
1357 }
1358
1359 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1360 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1361 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1362 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1363 typed_memcpy(dynamic->discard_rectangle.rectangles,
1364 discard_rectangle_info->pDiscardRectangles,
1365 discard_rectangle_info->discardRectangleCount);
1366 }
1367
1368 pipeline->dynamic_state.mask = states;
1369 }
1370
1371 static struct radv_gs_state
1372 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1373 const struct radv_pipeline *pipeline)
1374 {
1375 struct radv_gs_state gs = {0};
1376 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1377 struct radv_es_output_info *es_info;
1378 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1379 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1380 else
1381 es_info = radv_pipeline_has_tess(pipeline) ?
1382 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1383 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1384
1385 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1386 bool uses_adjacency;
1387 switch(pCreateInfo->pInputAssemblyState->topology) {
1388 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1389 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1390 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1391 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1392 uses_adjacency = true;
1393 break;
1394 default:
1395 uses_adjacency = false;
1396 break;
1397 }
1398
1399 /* All these are in dwords: */
1400 /* We can't allow using the whole LDS, because GS waves compete with
1401 * other shader stages for LDS space. */
1402 const unsigned max_lds_size = 8 * 1024;
1403 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1404 unsigned esgs_lds_size;
1405
1406 /* All these are per subgroup: */
1407 const unsigned max_out_prims = 32 * 1024;
1408 const unsigned max_es_verts = 255;
1409 const unsigned ideal_gs_prims = 64;
1410 unsigned max_gs_prims, gs_prims;
1411 unsigned min_es_verts, es_verts, worst_case_es_verts;
1412
1413 if (uses_adjacency || gs_num_invocations > 1)
1414 max_gs_prims = 127 / gs_num_invocations;
1415 else
1416 max_gs_prims = 255;
1417
1418 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1419 * Make sure we don't go over the maximum value.
1420 */
1421 if (gs_info->gs.vertices_out > 0) {
1422 max_gs_prims = MIN2(max_gs_prims,
1423 max_out_prims /
1424 (gs_info->gs.vertices_out * gs_num_invocations));
1425 }
1426 assert(max_gs_prims > 0);
1427
1428 /* If the primitive has adjacency, halve the number of vertices
1429 * that will be reused in multiple primitives.
1430 */
1431 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1432
1433 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1434 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1435
1436 /* Compute ESGS LDS size based on the worst case number of ES vertices
1437 * needed to create the target number of GS prims per subgroup.
1438 */
1439 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1440
1441 /* If total LDS usage is too big, refactor partitions based on ratio
1442 * of ESGS item sizes.
1443 */
1444 if (esgs_lds_size > max_lds_size) {
1445 /* Our target GS Prims Per Subgroup was too large. Calculate
1446 * the maximum number of GS Prims Per Subgroup that will fit
1447 * into LDS, capped by the maximum that the hardware can support.
1448 */
1449 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1450 max_gs_prims);
1451 assert(gs_prims > 0);
1452 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1453 max_es_verts);
1454
1455 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1456 assert(esgs_lds_size <= max_lds_size);
1457 }
1458
1459 /* Now calculate remaining ESGS information. */
1460 if (esgs_lds_size)
1461 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1462 else
1463 es_verts = max_es_verts;
1464
1465 /* Vertices for adjacency primitives are not always reused, so restore
1466 * it for ES_VERTS_PER_SUBGRP.
1467 */
1468 min_es_verts = gs_info->gs.vertices_in;
1469
1470 /* For normal primitives, the VGT only checks if they are past the ES
1471 * verts per subgroup after allocating a full GS primitive and if they
1472 * are, kick off a new subgroup. But if those additional ES verts are
1473 * unique (e.g. not reused) we need to make sure there is enough LDS
1474 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1475 */
1476 es_verts -= min_es_verts - 1;
1477
1478 uint32_t es_verts_per_subgroup = es_verts;
1479 uint32_t gs_prims_per_subgroup = gs_prims;
1480 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1481 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1482 gs.lds_size = align(esgs_lds_size, 128) / 128;
1483 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1484 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1485 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1486 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1487 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1488 assert(max_prims_per_subgroup <= max_out_prims);
1489
1490 return gs;
1491 }
1492
1493 static void
1494 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1495 {
1496 struct radv_device *device = pipeline->device;
1497 unsigned num_se = device->physical_device->rad_info.max_se;
1498 unsigned wave_size = 64;
1499 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1500 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1501 unsigned alignment = 256 * num_se;
1502 /* The maximum size is 63.999 MB per SE. */
1503 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1504 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1505
1506 /* Calculate the minimum size. */
1507 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1508 wave_size, alignment);
1509 /* These are recommended sizes, not minimum sizes. */
1510 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1511 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1512 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1513 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1514
1515 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1516 esgs_ring_size = align(esgs_ring_size, alignment);
1517 gsvs_ring_size = align(gsvs_ring_size, alignment);
1518
1519 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1520 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1521
1522 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1523 }
1524
1525 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1526 unsigned *lds_size)
1527 {
1528 /* If tessellation is all offchip and on-chip GS isn't used, this
1529 * workaround is not needed.
1530 */
1531 return;
1532
1533 /* SPI barrier management bug:
1534 * Make sure we have at least 4k of LDS in use to avoid the bug.
1535 * It applies to workgroup sizes of more than one wavefront.
1536 */
1537 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1538 device->physical_device->rad_info.family == CHIP_KABINI ||
1539 device->physical_device->rad_info.family == CHIP_MULLINS)
1540 *lds_size = MAX2(*lds_size, 8);
1541 }
1542
1543 struct radv_shader_variant *
1544 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1545 {
1546 if (pipeline->shaders[MESA_SHADER_VERTEX])
1547 return pipeline->shaders[MESA_SHADER_VERTEX];
1548 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1549 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1550 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1551 }
1552
1553 static struct radv_shader_variant *
1554 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1555 {
1556 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1557 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1558 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1559 }
1560
1561 static struct radv_tessellation_state
1562 calculate_tess_state(struct radv_pipeline *pipeline,
1563 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1564 {
1565 unsigned num_tcs_input_cp;
1566 unsigned num_tcs_output_cp;
1567 unsigned lds_size;
1568 unsigned num_patches;
1569 struct radv_tessellation_state tess = {0};
1570
1571 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1572 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1573 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1574
1575 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1576
1577 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1578 assert(lds_size <= 65536);
1579 lds_size = align(lds_size, 512) / 512;
1580 } else {
1581 assert(lds_size <= 32768);
1582 lds_size = align(lds_size, 256) / 256;
1583 }
1584 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1585
1586 tess.lds_size = lds_size;
1587
1588 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1589 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1590 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1591 tess.num_patches = num_patches;
1592
1593 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1594 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1595
1596 switch (tes->info.tes.primitive_mode) {
1597 case GL_TRIANGLES:
1598 type = V_028B6C_TESS_TRIANGLE;
1599 break;
1600 case GL_QUADS:
1601 type = V_028B6C_TESS_QUAD;
1602 break;
1603 case GL_ISOLINES:
1604 type = V_028B6C_TESS_ISOLINE;
1605 break;
1606 }
1607
1608 switch (tes->info.tes.spacing) {
1609 case TESS_SPACING_EQUAL:
1610 partitioning = V_028B6C_PART_INTEGER;
1611 break;
1612 case TESS_SPACING_FRACTIONAL_ODD:
1613 partitioning = V_028B6C_PART_FRAC_ODD;
1614 break;
1615 case TESS_SPACING_FRACTIONAL_EVEN:
1616 partitioning = V_028B6C_PART_FRAC_EVEN;
1617 break;
1618 default:
1619 break;
1620 }
1621
1622 bool ccw = tes->info.tes.ccw;
1623 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1624 vk_find_struct_const(pCreateInfo->pTessellationState,
1625 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1626
1627 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1628 ccw = !ccw;
1629
1630 if (tes->info.tes.point_mode)
1631 topology = V_028B6C_OUTPUT_POINT;
1632 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1633 topology = V_028B6C_OUTPUT_LINE;
1634 else if (ccw)
1635 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1636 else
1637 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1638
1639 if (pipeline->device->has_distributed_tess) {
1640 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1641 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1642 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1643 else
1644 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1645 } else
1646 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1647
1648 tess.tf_param = S_028B6C_TYPE(type) |
1649 S_028B6C_PARTITIONING(partitioning) |
1650 S_028B6C_TOPOLOGY(topology) |
1651 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1652
1653 return tess;
1654 }
1655
1656 static const struct radv_prim_vertex_count prim_size_table[] = {
1657 [V_008958_DI_PT_NONE] = {0, 0},
1658 [V_008958_DI_PT_POINTLIST] = {1, 1},
1659 [V_008958_DI_PT_LINELIST] = {2, 2},
1660 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1661 [V_008958_DI_PT_TRILIST] = {3, 3},
1662 [V_008958_DI_PT_TRIFAN] = {3, 1},
1663 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1664 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1665 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1666 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1667 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1668 [V_008958_DI_PT_RECTLIST] = {3, 3},
1669 [V_008958_DI_PT_LINELOOP] = {2, 1},
1670 [V_008958_DI_PT_POLYGON] = {3, 1},
1671 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1672 };
1673
1674 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1675 {
1676 if (radv_pipeline_has_gs(pipeline))
1677 return &pipeline->gs_copy_shader->info.vs.outinfo;
1678 else if (radv_pipeline_has_tess(pipeline))
1679 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1680 else
1681 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1682 }
1683
1684 static void
1685 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1686 {
1687 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1688 int shader_count = 0;
1689
1690 if(shaders[MESA_SHADER_FRAGMENT]) {
1691 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1692 }
1693 if(shaders[MESA_SHADER_GEOMETRY]) {
1694 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1695 }
1696 if(shaders[MESA_SHADER_TESS_EVAL]) {
1697 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1698 }
1699 if(shaders[MESA_SHADER_TESS_CTRL]) {
1700 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1701 }
1702 if(shaders[MESA_SHADER_VERTEX]) {
1703 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1704 }
1705
1706 for (int i = 1; i < shader_count; ++i) {
1707 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1708 ordered_shaders[i - 1]);
1709
1710 nir_remove_dead_variables(ordered_shaders[i],
1711 nir_var_shader_out);
1712 nir_remove_dead_variables(ordered_shaders[i - 1],
1713 nir_var_shader_in);
1714
1715 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1716 ordered_shaders[i - 1]);
1717
1718 nir_compact_varyings(ordered_shaders[i],
1719 ordered_shaders[i - 1], true);
1720
1721 if (progress) {
1722 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1723 ac_lower_indirect_derefs(ordered_shaders[i],
1724 pipeline->device->physical_device->rad_info.chip_class);
1725 }
1726 radv_optimize_nir(ordered_shaders[i]);
1727
1728 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1729 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1730 pipeline->device->physical_device->rad_info.chip_class);
1731 }
1732 radv_optimize_nir(ordered_shaders[i - 1]);
1733 }
1734 }
1735 }
1736
1737
1738 static struct radv_pipeline_key
1739 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1740 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1741 const struct radv_blend_state *blend,
1742 bool has_view_index)
1743 {
1744 const VkPipelineVertexInputStateCreateInfo *input_state =
1745 pCreateInfo->pVertexInputState;
1746 struct radv_pipeline_key key;
1747 memset(&key, 0, sizeof(key));
1748
1749 key.has_multiview_view_index = has_view_index;
1750
1751 uint32_t binding_input_rate = 0;
1752 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1753 if (input_state->pVertexBindingDescriptions[i].inputRate)
1754 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1755 }
1756
1757 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1758 unsigned binding;
1759 binding = input_state->pVertexAttributeDescriptions[i].binding;
1760 if (binding_input_rate & (1u << binding))
1761 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1762 }
1763
1764 if (pCreateInfo->pTessellationState)
1765 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1766
1767
1768 if (pCreateInfo->pMultisampleState &&
1769 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1770 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1771 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1772 key.multisample = true;
1773 key.log2_num_samples = util_logbase2(num_samples);
1774 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1775 }
1776
1777 key.col_format = blend->spi_shader_col_format;
1778 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1779 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1780
1781 return key;
1782 }
1783
1784 static void
1785 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1786 const struct radv_pipeline_key *key,
1787 nir_shader **nir)
1788 {
1789 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1790
1791 if (nir[MESA_SHADER_TESS_CTRL]) {
1792 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1793 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1794 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1795 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1796
1797 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1798 }
1799
1800 if (nir[MESA_SHADER_GEOMETRY]) {
1801 if (nir[MESA_SHADER_TESS_CTRL])
1802 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1803 else
1804 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1805 }
1806
1807 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1808 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1809
1810 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1811 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1812 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1813 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1814 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1815 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1816 }
1817
1818 static void
1819 merge_tess_info(struct shader_info *tes_info,
1820 const struct shader_info *tcs_info)
1821 {
1822 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1823 *
1824 * "PointMode. Controls generation of points rather than triangles
1825 * or lines. This functionality defaults to disabled, and is
1826 * enabled if either shader stage includes the execution mode.
1827 *
1828 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1829 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1830 * and OutputVertices, it says:
1831 *
1832 * "One mode must be set in at least one of the tessellation
1833 * shader stages."
1834 *
1835 * So, the fields can be set in either the TCS or TES, but they must
1836 * agree if set in both. Our backend looks at TES, so bitwise-or in
1837 * the values from the TCS.
1838 */
1839 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1840 tes_info->tess.tcs_vertices_out == 0 ||
1841 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1842 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1843
1844 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1845 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1846 tcs_info->tess.spacing == tes_info->tess.spacing);
1847 tes_info->tess.spacing |= tcs_info->tess.spacing;
1848
1849 assert(tcs_info->tess.primitive_mode == 0 ||
1850 tes_info->tess.primitive_mode == 0 ||
1851 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1852 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1853 tes_info->tess.ccw |= tcs_info->tess.ccw;
1854 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1855 }
1856
1857 static
1858 void radv_create_shaders(struct radv_pipeline *pipeline,
1859 struct radv_device *device,
1860 struct radv_pipeline_cache *cache,
1861 struct radv_pipeline_key key,
1862 const VkPipelineShaderStageCreateInfo **pStages)
1863 {
1864 struct radv_shader_module fs_m = {0};
1865 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1866 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1867 void *codes[MESA_SHADER_STAGES] = {0};
1868 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1869 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1870 unsigned char hash[20], gs_copy_hash[20];
1871
1872 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1873 if (pStages[i]) {
1874 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1875 if (modules[i]->nir)
1876 _mesa_sha1_compute(modules[i]->nir->info.name,
1877 strlen(modules[i]->nir->info.name),
1878 modules[i]->sha1);
1879 }
1880 }
1881
1882 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1883 memcpy(gs_copy_hash, hash, 20);
1884 gs_copy_hash[0] ^= 1;
1885
1886 if (modules[MESA_SHADER_GEOMETRY]) {
1887 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1888 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1889 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1890 }
1891
1892 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1893 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1894 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1895 if (pipeline->shaders[i])
1896 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1897 }
1898 return;
1899 }
1900
1901 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1902 nir_builder fs_b;
1903 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1904 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1905 fs_m.nir = fs_b.shader;
1906 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1907 }
1908
1909 /* Determine first and last stage. */
1910 unsigned first = MESA_SHADER_STAGES;
1911 unsigned last = 0;
1912 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1913 if (!pStages[i])
1914 continue;
1915 if (first == MESA_SHADER_STAGES)
1916 first = i;
1917 last = i;
1918 }
1919
1920 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1921 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1922
1923 if (!modules[i])
1924 continue;
1925
1926 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1927 stage ? stage->pName : "main", i,
1928 stage ? stage->pSpecializationInfo : NULL);
1929 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1930
1931 /* We don't want to alter meta shaders IR directly so clone it
1932 * first.
1933 */
1934 if (nir[i]->info.name) {
1935 nir[i] = nir_shader_clone(NULL, nir[i]);
1936 }
1937
1938 if (first != last) {
1939 nir_variable_mode mask = 0;
1940
1941 if (i != first)
1942 mask = mask | nir_var_shader_in;
1943
1944 if (i != last)
1945 mask = mask | nir_var_shader_out;
1946
1947 nir_lower_io_to_scalar_early(nir[i], mask);
1948 radv_optimize_nir(nir[i]);
1949 }
1950 }
1951
1952 if (nir[MESA_SHADER_TESS_CTRL]) {
1953 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1954 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1955 }
1956
1957 radv_link_shaders(pipeline, nir);
1958
1959 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1960 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1961 nir_print_shader(nir[i], stderr);
1962 }
1963
1964 radv_fill_shader_keys(keys, &key, nir);
1965
1966 if (nir[MESA_SHADER_FRAGMENT]) {
1967 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1968 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1969 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1970 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1971 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1972 }
1973
1974 /* TODO: These are no longer used as keys we should refactor this */
1975 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1976 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1977 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
1978 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1979 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1980 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1981 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
1982 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1983 }
1984
1985 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1986 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1987 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1988 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1989 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1990 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1991 pipeline->layout,
1992 &key, &codes[MESA_SHADER_TESS_CTRL],
1993 &code_sizes[MESA_SHADER_TESS_CTRL]);
1994 }
1995 modules[MESA_SHADER_VERTEX] = NULL;
1996 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1997 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1998 }
1999
2000 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2001 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2002 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2003 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2004 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2005 pipeline->layout,
2006 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
2007 &code_sizes[MESA_SHADER_GEOMETRY]);
2008 }
2009 modules[pre_stage] = NULL;
2010 }
2011
2012 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2013 if(modules[i] && !pipeline->shaders[i]) {
2014 if (i == MESA_SHADER_TESS_CTRL) {
2015 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2016 }
2017 if (i == MESA_SHADER_TESS_EVAL) {
2018 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2019 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2020 }
2021 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2022 pipeline->layout,
2023 keys + i, &codes[i],
2024 &code_sizes[i]);
2025 }
2026 }
2027
2028 if(modules[MESA_SHADER_GEOMETRY]) {
2029 void *gs_copy_code = NULL;
2030 unsigned gs_copy_code_size = 0;
2031 if (!pipeline->gs_copy_shader) {
2032 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2033 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2034 &gs_copy_code_size,
2035 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2036 }
2037
2038 if (pipeline->gs_copy_shader) {
2039 void *code[MESA_SHADER_STAGES] = {0};
2040 unsigned code_size[MESA_SHADER_STAGES] = {0};
2041 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2042
2043 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2044 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2045 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2046
2047 radv_pipeline_cache_insert_shaders(device, cache,
2048 gs_copy_hash,
2049 variants,
2050 (const void**)code,
2051 code_size);
2052 }
2053 free(gs_copy_code);
2054 }
2055
2056 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2057 (const void**)codes, code_sizes);
2058
2059 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2060 free(codes[i]);
2061 if (modules[i]) {
2062 if (!pipeline->device->keep_shader_info)
2063 ralloc_free(nir[i]);
2064
2065 if (radv_can_dump_shader_stats(device, modules[i]))
2066 radv_shader_dump_stats(device,
2067 pipeline->shaders[i],
2068 i, stderr);
2069 }
2070 }
2071
2072 if (fs_m.nir)
2073 ralloc_free(fs_m.nir);
2074 }
2075
2076 static uint32_t
2077 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2078 gl_shader_stage stage, enum chip_class chip_class)
2079 {
2080 bool has_gs = radv_pipeline_has_gs(pipeline);
2081 bool has_tess = radv_pipeline_has_tess(pipeline);
2082 switch (stage) {
2083 case MESA_SHADER_FRAGMENT:
2084 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2085 case MESA_SHADER_VERTEX:
2086 if (chip_class >= GFX9) {
2087 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2088 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2089 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2090 }
2091 if (has_tess)
2092 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2093 else
2094 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2095 case MESA_SHADER_GEOMETRY:
2096 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2097 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2098 case MESA_SHADER_COMPUTE:
2099 return R_00B900_COMPUTE_USER_DATA_0;
2100 case MESA_SHADER_TESS_CTRL:
2101 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2102 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2103 case MESA_SHADER_TESS_EVAL:
2104 if (chip_class >= GFX9) {
2105 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2106 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2107 }
2108 if (has_gs)
2109 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2110 else
2111 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2112 default:
2113 unreachable("unknown shader");
2114 }
2115 }
2116
2117 struct radv_bin_size_entry {
2118 unsigned bpp;
2119 VkExtent2D extent;
2120 };
2121
2122 static VkExtent2D
2123 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2124 {
2125 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2126 {
2127 /* One RB / SE */
2128 {
2129 /* One shader engine */
2130 { 0, {128, 128}},
2131 { 1, { 64, 128}},
2132 { 2, { 32, 128}},
2133 { 3, { 16, 128}},
2134 { 17, { 0, 0}},
2135 { UINT_MAX, { 0, 0}},
2136 },
2137 {
2138 /* Two shader engines */
2139 { 0, {128, 128}},
2140 { 2, { 64, 128}},
2141 { 3, { 32, 128}},
2142 { 5, { 16, 128}},
2143 { 17, { 0, 0}},
2144 { UINT_MAX, { 0, 0}},
2145 },
2146 {
2147 /* Four shader engines */
2148 { 0, {128, 128}},
2149 { 3, { 64, 128}},
2150 { 5, { 16, 128}},
2151 { 17, { 0, 0}},
2152 { UINT_MAX, { 0, 0}},
2153 },
2154 },
2155 {
2156 /* Two RB / SE */
2157 {
2158 /* One shader engine */
2159 { 0, {128, 128}},
2160 { 2, { 64, 128}},
2161 { 3, { 32, 128}},
2162 { 5, { 16, 128}},
2163 { 33, { 0, 0}},
2164 { UINT_MAX, { 0, 0}},
2165 },
2166 {
2167 /* Two shader engines */
2168 { 0, {128, 128}},
2169 { 3, { 64, 128}},
2170 { 5, { 32, 128}},
2171 { 9, { 16, 128}},
2172 { 33, { 0, 0}},
2173 { UINT_MAX, { 0, 0}},
2174 },
2175 {
2176 /* Four shader engines */
2177 { 0, {256, 256}},
2178 { 2, {128, 256}},
2179 { 3, {128, 128}},
2180 { 5, { 64, 128}},
2181 { 9, { 16, 128}},
2182 { 33, { 0, 0}},
2183 { UINT_MAX, { 0, 0}},
2184 },
2185 },
2186 {
2187 /* Four RB / SE */
2188 {
2189 /* One shader engine */
2190 { 0, {128, 256}},
2191 { 2, {128, 128}},
2192 { 3, { 64, 128}},
2193 { 5, { 32, 128}},
2194 { 9, { 16, 128}},
2195 { 33, { 0, 0}},
2196 { UINT_MAX, { 0, 0}},
2197 },
2198 {
2199 /* Two shader engines */
2200 { 0, {256, 256}},
2201 { 2, {128, 256}},
2202 { 3, {128, 128}},
2203 { 5, { 64, 128}},
2204 { 9, { 32, 128}},
2205 { 17, { 16, 128}},
2206 { 33, { 0, 0}},
2207 { UINT_MAX, { 0, 0}},
2208 },
2209 {
2210 /* Four shader engines */
2211 { 0, {256, 512}},
2212 { 2, {256, 256}},
2213 { 3, {128, 256}},
2214 { 5, {128, 128}},
2215 { 9, { 64, 128}},
2216 { 17, { 16, 128}},
2217 { 33, { 0, 0}},
2218 { UINT_MAX, { 0, 0}},
2219 },
2220 },
2221 };
2222 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2223 {
2224 // One RB / SE
2225 {
2226 // One shader engine
2227 { 0, {128, 256}},
2228 { 2, {128, 128}},
2229 { 4, { 64, 128}},
2230 { 7, { 32, 128}},
2231 { 13, { 16, 128}},
2232 { 49, { 0, 0}},
2233 { UINT_MAX, { 0, 0}},
2234 },
2235 {
2236 // Two shader engines
2237 { 0, {256, 256}},
2238 { 2, {128, 256}},
2239 { 4, {128, 128}},
2240 { 7, { 64, 128}},
2241 { 13, { 32, 128}},
2242 { 25, { 16, 128}},
2243 { 49, { 0, 0}},
2244 { UINT_MAX, { 0, 0}},
2245 },
2246 {
2247 // Four shader engines
2248 { 0, {256, 512}},
2249 { 2, {256, 256}},
2250 { 4, {128, 256}},
2251 { 7, {128, 128}},
2252 { 13, { 64, 128}},
2253 { 25, { 16, 128}},
2254 { 49, { 0, 0}},
2255 { UINT_MAX, { 0, 0}},
2256 },
2257 },
2258 {
2259 // Two RB / SE
2260 {
2261 // One shader engine
2262 { 0, {256, 256}},
2263 { 2, {128, 256}},
2264 { 4, {128, 128}},
2265 { 7, { 64, 128}},
2266 { 13, { 32, 128}},
2267 { 25, { 16, 128}},
2268 { 97, { 0, 0}},
2269 { UINT_MAX, { 0, 0}},
2270 },
2271 {
2272 // Two shader engines
2273 { 0, {256, 512}},
2274 { 2, {256, 256}},
2275 { 4, {128, 256}},
2276 { 7, {128, 128}},
2277 { 13, { 64, 128}},
2278 { 25, { 32, 128}},
2279 { 49, { 16, 128}},
2280 { 97, { 0, 0}},
2281 { UINT_MAX, { 0, 0}},
2282 },
2283 {
2284 // Four shader engines
2285 { 0, {512, 512}},
2286 { 2, {256, 512}},
2287 { 4, {256, 256}},
2288 { 7, {128, 256}},
2289 { 13, {128, 128}},
2290 { 25, { 64, 128}},
2291 { 49, { 16, 128}},
2292 { 97, { 0, 0}},
2293 { UINT_MAX, { 0, 0}},
2294 },
2295 },
2296 {
2297 // Four RB / SE
2298 {
2299 // One shader engine
2300 { 0, {256, 512}},
2301 { 2, {256, 256}},
2302 { 4, {128, 256}},
2303 { 7, {128, 128}},
2304 { 13, { 64, 128}},
2305 { 25, { 32, 128}},
2306 { 49, { 16, 128}},
2307 { UINT_MAX, { 0, 0}},
2308 },
2309 {
2310 // Two shader engines
2311 { 0, {512, 512}},
2312 { 2, {256, 512}},
2313 { 4, {256, 256}},
2314 { 7, {128, 256}},
2315 { 13, {128, 128}},
2316 { 25, { 64, 128}},
2317 { 49, { 32, 128}},
2318 { 97, { 16, 128}},
2319 { UINT_MAX, { 0, 0}},
2320 },
2321 {
2322 // Four shader engines
2323 { 0, {512, 512}},
2324 { 4, {256, 512}},
2325 { 7, {256, 256}},
2326 { 13, {128, 256}},
2327 { 25, {128, 128}},
2328 { 49, { 64, 128}},
2329 { 97, { 16, 128}},
2330 { UINT_MAX, { 0, 0}},
2331 },
2332 },
2333 };
2334
2335 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2336 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2337 VkExtent2D extent = {512, 512};
2338
2339 unsigned log_num_rb_per_se =
2340 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2341 pipeline->device->physical_device->rad_info.max_se);
2342 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2343
2344 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2345 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2346 unsigned effective_samples = total_samples;
2347 unsigned color_bytes_per_pixel = 0;
2348
2349 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2350 if (vkblend) {
2351 for (unsigned i = 0; i < subpass->color_count; i++) {
2352 if (!vkblend->pAttachments[i].colorWriteMask)
2353 continue;
2354
2355 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2356 continue;
2357
2358 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2359 color_bytes_per_pixel += vk_format_get_blocksize(format);
2360 }
2361
2362 /* MSAA images typically don't use all samples all the time. */
2363 if (effective_samples >= 2 && ps_iter_samples <= 1)
2364 effective_samples = 2;
2365 color_bytes_per_pixel *= effective_samples;
2366 }
2367
2368 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2369 while(color_entry->bpp <= color_bytes_per_pixel)
2370 ++color_entry;
2371
2372 extent = color_entry->extent;
2373
2374 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2375 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2376
2377 /* Coefficients taken from AMDVLK */
2378 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2379 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2380 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2381
2382 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2383 while(ds_entry->bpp <= ds_bytes_per_pixel)
2384 ++ds_entry;
2385
2386 extent.width = MIN2(extent.width, ds_entry->extent.width);
2387 extent.height = MIN2(extent.height, ds_entry->extent.height);
2388 }
2389
2390 return extent;
2391 }
2392
2393 static void
2394 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2395 struct radv_pipeline *pipeline,
2396 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2397 {
2398 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2399 return;
2400
2401 uint32_t pa_sc_binner_cntl_0 =
2402 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2403 S_028C44_DISABLE_START_OF_PRIM(1);
2404 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2405
2406 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2407
2408 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2409 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2410 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2411
2412 switch (pipeline->device->physical_device->rad_info.family) {
2413 case CHIP_VEGA10:
2414 case CHIP_VEGA12:
2415 context_states_per_bin = 1;
2416 persistent_states_per_bin = 1;
2417 fpovs_per_batch = 63;
2418 break;
2419 case CHIP_RAVEN:
2420 context_states_per_bin = 6;
2421 persistent_states_per_bin = 32;
2422 fpovs_per_batch = 63;
2423 break;
2424 default:
2425 unreachable("unhandled family while determining binning state.");
2426 }
2427
2428 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2429 pa_sc_binner_cntl_0 =
2430 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2431 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2432 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2433 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2434 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2435 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2436 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2437 S_028C44_DISABLE_START_OF_PRIM(1) |
2438 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2439 S_028C44_OPTIMAL_BIN_SELECTION(1);
2440 }
2441
2442 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2443 pa_sc_binner_cntl_0);
2444 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2445 db_dfsm_control);
2446 }
2447
2448
2449 static void
2450 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2451 struct radv_pipeline *pipeline,
2452 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2453 const struct radv_graphics_pipeline_create_info *extra)
2454 {
2455 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2456 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2457 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2458 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2459 struct radv_render_pass_attachment *attachment = NULL;
2460 uint32_t db_depth_control = 0, db_stencil_control = 0;
2461 uint32_t db_render_control = 0, db_render_override2 = 0;
2462 uint32_t db_render_override = 0;
2463
2464 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2465 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2466
2467 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2468 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2469
2470 if (vkds && has_depth_attachment) {
2471 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2472 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2473 S_028800_ZFUNC(vkds->depthCompareOp) |
2474 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2475
2476 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2477 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2478 }
2479
2480 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2481 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2482 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2483 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2484 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2485 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2486
2487 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2488 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2489 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2490 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2491 }
2492
2493 if (attachment && extra) {
2494 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2495 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2496
2497 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2498 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2499 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2500 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2501 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2502 }
2503
2504 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2505 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2506
2507 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2508 !pCreateInfo->pRasterizationState->depthClampEnable &&
2509 ps->info.info.ps.writes_z) {
2510 /* From VK_EXT_depth_range_unrestricted spec:
2511 *
2512 * "The behavior described in Primitive Clipping still applies.
2513 * If depth clamping is disabled the depth values are still
2514 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2515 * depth clamping is enabled the above equation is ignored and
2516 * the depth values are instead clamped to the VkViewport
2517 * minDepth and maxDepth values, which in the case of this
2518 * extension can be outside of the 0.0 to 1.0 range."
2519 */
2520 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2521 }
2522
2523 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2524 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2525
2526 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2527 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2528 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2529 }
2530
2531 static void
2532 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2533 struct radv_pipeline *pipeline,
2534 const struct radv_blend_state *blend)
2535 {
2536 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2537 radeon_emit_array(cs, blend->cb_blend_control,
2538 8);
2539 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2540 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2541
2542 if (pipeline->device->physical_device->has_rbplus) {
2543
2544 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2545 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2546
2547 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2548 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2549 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2550 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2551 }
2552
2553 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2554
2555 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2556 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2557 }
2558
2559
2560 static void
2561 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2562 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2563 {
2564 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2565
2566 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2567 S_028810_PS_UCP_MODE(3) |
2568 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2569 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2570 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2571 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2572 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2573
2574 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2575 S_0286D4_FLAT_SHADE_ENA(1) |
2576 S_0286D4_PNT_SPRITE_ENA(1) |
2577 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2578 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2579 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2580 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2581 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2582
2583 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2584 S_028BE4_PIX_CENTER(1) | // TODO verify
2585 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2586 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2587
2588 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2589 S_028814_FACE(vkraster->frontFace) |
2590 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2591 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2592 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2593 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2594 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2595 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2596 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2597 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2598 }
2599
2600
2601 static void
2602 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2603 struct radv_pipeline *pipeline)
2604 {
2605 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2606
2607 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2608 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2609 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2610
2611 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2612 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2613
2614 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2615 uint32_t offset;
2616 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2617 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2618 if (loc->sgpr_idx == -1)
2619 return;
2620 assert(loc->num_sgprs == 1);
2621 assert(!loc->indirect);
2622 switch (pipeline->graphics.ms.num_samples) {
2623 default:
2624 offset = 0;
2625 break;
2626 case 2:
2627 offset = 1;
2628 break;
2629 case 4:
2630 offset = 3;
2631 break;
2632 case 8:
2633 offset = 7;
2634 break;
2635 case 16:
2636 offset = 15;
2637 break;
2638 }
2639
2640 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2641 }
2642 }
2643
2644 static void
2645 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2646 const struct radv_pipeline *pipeline)
2647 {
2648 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2649
2650 uint32_t vgt_primitiveid_en = false;
2651 uint32_t vgt_gs_mode = 0;
2652
2653 if (radv_pipeline_has_gs(pipeline)) {
2654 const struct radv_shader_variant *gs =
2655 pipeline->shaders[MESA_SHADER_GEOMETRY];
2656
2657 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2658 pipeline->device->physical_device->rad_info.chip_class);
2659 } else if (outinfo->export_prim_id) {
2660 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2661 vgt_primitiveid_en = true;
2662 }
2663
2664 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2665 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2666 }
2667
2668 static void
2669 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2670 struct radv_pipeline *pipeline,
2671 struct radv_shader_variant *shader)
2672 {
2673 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2674
2675 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2676 radeon_emit(cs, va >> 8);
2677 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2678 radeon_emit(cs, shader->rsrc1);
2679 radeon_emit(cs, shader->rsrc2);
2680
2681 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2682 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2683 clip_dist_mask = outinfo->clip_dist_mask;
2684 cull_dist_mask = outinfo->cull_dist_mask;
2685 total_mask = clip_dist_mask | cull_dist_mask;
2686 bool misc_vec_ena = outinfo->writes_pointsize ||
2687 outinfo->writes_layer ||
2688 outinfo->writes_viewport_index;
2689
2690 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2691 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2692
2693 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2694 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2695 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2696 V_02870C_SPI_SHADER_4COMP :
2697 V_02870C_SPI_SHADER_NONE) |
2698 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2699 V_02870C_SPI_SHADER_4COMP :
2700 V_02870C_SPI_SHADER_NONE) |
2701 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2702 V_02870C_SPI_SHADER_4COMP :
2703 V_02870C_SPI_SHADER_NONE));
2704
2705 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2706 S_028818_VTX_W0_FMT(1) |
2707 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2708 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2709 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2710
2711 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2712 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2713 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2714 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2715 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2716 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2717 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2718 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2719 cull_dist_mask << 8 |
2720 clip_dist_mask);
2721
2722 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2723 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2724 outinfo->writes_viewport_index);
2725 }
2726
2727 static void
2728 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2729 struct radv_pipeline *pipeline,
2730 struct radv_shader_variant *shader)
2731 {
2732 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2733
2734 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2735 radeon_emit(cs, va >> 8);
2736 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2737 radeon_emit(cs, shader->rsrc1);
2738 radeon_emit(cs, shader->rsrc2);
2739 }
2740
2741 static void
2742 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2743 struct radv_pipeline *pipeline,
2744 struct radv_shader_variant *shader,
2745 const struct radv_tessellation_state *tess)
2746 {
2747 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2748 uint32_t rsrc2 = shader->rsrc2;
2749
2750 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2751 radeon_emit(cs, va >> 8);
2752 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2753
2754 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2755 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2756 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2757 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2758
2759 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2760 radeon_emit(cs, shader->rsrc1);
2761 radeon_emit(cs, rsrc2);
2762 }
2763
2764 static void
2765 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2766 struct radv_pipeline *pipeline,
2767 struct radv_shader_variant *shader,
2768 const struct radv_tessellation_state *tess)
2769 {
2770 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2771
2772 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2773 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2774 radeon_emit(cs, va >> 8);
2775 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2776
2777 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2778 radeon_emit(cs, shader->rsrc1);
2779 radeon_emit(cs, shader->rsrc2 |
2780 S_00B42C_LDS_SIZE(tess->lds_size));
2781 } else {
2782 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2783 radeon_emit(cs, va >> 8);
2784 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2785 radeon_emit(cs, shader->rsrc1);
2786 radeon_emit(cs, shader->rsrc2);
2787 }
2788 }
2789
2790 static void
2791 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2792 struct radv_pipeline *pipeline,
2793 const struct radv_tessellation_state *tess)
2794 {
2795 struct radv_shader_variant *vs;
2796
2797 /* Skip shaders merged into HS/GS */
2798 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2799 if (!vs)
2800 return;
2801
2802 if (vs->info.vs.as_ls)
2803 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2804 else if (vs->info.vs.as_es)
2805 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2806 else
2807 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2808 }
2809
2810 static void
2811 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2812 struct radv_pipeline *pipeline,
2813 const struct radv_tessellation_state *tess)
2814 {
2815 if (!radv_pipeline_has_tess(pipeline))
2816 return;
2817
2818 struct radv_shader_variant *tes, *tcs;
2819
2820 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2821 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2822
2823 if (tes) {
2824 if (tes->info.tes.as_es)
2825 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2826 else
2827 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2828 }
2829
2830 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2831
2832 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2833 tess->tf_param);
2834
2835 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2836 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2837 tess->ls_hs_config);
2838 else
2839 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2840 tess->ls_hs_config);
2841 }
2842
2843 static void
2844 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2845 struct radv_pipeline *pipeline,
2846 const struct radv_gs_state *gs_state)
2847 {
2848 struct radv_shader_variant *gs;
2849 uint64_t va;
2850
2851 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2852 if (!gs)
2853 return;
2854
2855 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2856
2857 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2858 radeon_emit(cs, gsvs_itemsize);
2859 radeon_emit(cs, gsvs_itemsize);
2860 radeon_emit(cs, gsvs_itemsize);
2861
2862 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2863
2864 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2865
2866 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2867 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2868 radeon_emit(cs, gs_vert_itemsize >> 2);
2869 radeon_emit(cs, 0);
2870 radeon_emit(cs, 0);
2871 radeon_emit(cs, 0);
2872
2873 uint32_t gs_num_invocations = gs->info.gs.invocations;
2874 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2875 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2876 S_028B90_ENABLE(gs_num_invocations > 0));
2877
2878 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2879 gs_state->vgt_esgs_ring_itemsize);
2880
2881 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2882
2883 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2884 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2885 radeon_emit(cs, va >> 8);
2886 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
2887
2888 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2889 radeon_emit(cs, gs->rsrc1);
2890 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2891
2892 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2893 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2894 } else {
2895 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2896 radeon_emit(cs, va >> 8);
2897 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
2898 radeon_emit(cs, gs->rsrc1);
2899 radeon_emit(cs, gs->rsrc2);
2900 }
2901
2902 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2903 }
2904
2905 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2906 {
2907 uint32_t ps_input_cntl;
2908 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2909 ps_input_cntl = S_028644_OFFSET(offset);
2910 if (flat_shade)
2911 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2912 } else {
2913 /* The input is a DEFAULT_VAL constant. */
2914 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2915 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2916 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2917 ps_input_cntl = S_028644_OFFSET(0x20) |
2918 S_028644_DEFAULT_VAL(offset);
2919 }
2920 return ps_input_cntl;
2921 }
2922
2923 static void
2924 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2925 struct radv_pipeline *pipeline)
2926 {
2927 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2928 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2929 uint32_t ps_input_cntl[32];
2930
2931 unsigned ps_offset = 0;
2932
2933 if (ps->info.info.ps.prim_id_input) {
2934 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2935 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2936 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2937 ++ps_offset;
2938 }
2939 }
2940
2941 if (ps->info.info.ps.layer_input ||
2942 ps->info.info.ps.uses_input_attachments ||
2943 ps->info.info.needs_multiview_view_index) {
2944 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2945 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2946 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2947 else
2948 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2949 ++ps_offset;
2950 }
2951
2952 if (ps->info.info.ps.has_pcoord) {
2953 unsigned val;
2954 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2955 ps_input_cntl[ps_offset] = val;
2956 ps_offset++;
2957 }
2958
2959 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2960 unsigned vs_offset;
2961 bool flat_shade;
2962 if (!(ps->info.fs.input_mask & (1u << i)))
2963 continue;
2964
2965 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2966 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2967 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2968 ++ps_offset;
2969 continue;
2970 }
2971
2972 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2973
2974 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2975 ++ps_offset;
2976 }
2977
2978 if (ps_offset) {
2979 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2980 for (unsigned i = 0; i < ps_offset; i++) {
2981 radeon_emit(cs, ps_input_cntl[i]);
2982 }
2983 }
2984 }
2985
2986 static uint32_t
2987 radv_compute_db_shader_control(const struct radv_device *device,
2988 const struct radv_shader_variant *ps)
2989 {
2990 unsigned z_order;
2991 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2992 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2993 else
2994 z_order = V_02880C_LATE_Z;
2995
2996 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
2997 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
2998 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2999 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
3000 S_02880C_Z_ORDER(z_order) |
3001 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3002 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3003 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3004 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
3005 }
3006
3007 static void
3008 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
3009 struct radv_pipeline *pipeline)
3010 {
3011 struct radv_shader_variant *ps;
3012 uint64_t va;
3013 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3014
3015 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3016 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3017
3018 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3019 radeon_emit(cs, va >> 8);
3020 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3021 radeon_emit(cs, ps->rsrc1);
3022 radeon_emit(cs, ps->rsrc2);
3023
3024 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
3025 radv_compute_db_shader_control(pipeline->device, ps));
3026
3027 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
3028 ps->config.spi_ps_input_ena);
3029
3030 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
3031 ps->config.spi_ps_input_addr);
3032
3033 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
3034 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3035
3036 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3037
3038 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
3039 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3040 ps->info.info.ps.writes_stencil,
3041 ps->info.info.ps.writes_sample_mask));
3042
3043 if (pipeline->device->dfsm_allowed) {
3044 /* optimise this? */
3045 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3046 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3047 }
3048 }
3049
3050 static void
3051 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
3052 struct radv_pipeline *pipeline)
3053 {
3054 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
3055 return;
3056
3057 unsigned vtx_reuse_depth = 30;
3058 if (radv_pipeline_has_tess(pipeline) &&
3059 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3060 vtx_reuse_depth = 14;
3061 }
3062 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3063 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3064 }
3065
3066 static uint32_t
3067 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3068 {
3069 uint32_t stages = 0;
3070 if (radv_pipeline_has_tess(pipeline)) {
3071 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3072 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3073
3074 if (radv_pipeline_has_gs(pipeline))
3075 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3076 S_028B54_GS_EN(1) |
3077 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3078 else
3079 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3080
3081 } else if (radv_pipeline_has_gs(pipeline))
3082 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3083 S_028B54_GS_EN(1) |
3084 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3085
3086 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3087 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3088
3089 return stages;
3090 }
3091
3092 static uint32_t
3093 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3094 {
3095 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3096 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3097
3098 if (!discard_rectangle_info)
3099 return 0xffff;
3100
3101 unsigned mask = 0;
3102
3103 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3104 /* Interpret i as a bitmask, and then set the bit in the mask if
3105 * that combination of rectangles in which the pixel is contained
3106 * should pass the cliprect test. */
3107 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3108
3109 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3110 !relevant_subset)
3111 continue;
3112
3113 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3114 relevant_subset)
3115 continue;
3116
3117 mask |= 1u << i;
3118 }
3119
3120 return mask;
3121 }
3122
3123 static void
3124 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
3125 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3126 const struct radv_graphics_pipeline_create_info *extra,
3127 const struct radv_blend_state *blend,
3128 const struct radv_tessellation_state *tess,
3129 const struct radv_gs_state *gs,
3130 unsigned prim, unsigned gs_out)
3131 {
3132 pipeline->cs.buf = malloc(4 * 256);
3133 pipeline->cs.max_dw = 256;
3134
3135 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
3136 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
3137 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
3138 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
3139 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
3140 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
3141 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
3142 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
3143 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
3144 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
3145 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
3146 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
3147
3148 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
3149 S_0286E8_WAVES(pipeline->max_waves) |
3150 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3151
3152 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
3153
3154 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
3155 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
3156 } else {
3157 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
3158 }
3159 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
3160
3161 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
3162
3163 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3164 }
3165
3166 static struct radv_ia_multi_vgt_param_helpers
3167 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
3168 const struct radv_tessellation_state *tess,
3169 uint32_t prim)
3170 {
3171 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
3172 const struct radv_device *device = pipeline->device;
3173
3174 if (radv_pipeline_has_tess(pipeline))
3175 ia_multi_vgt_param.primgroup_size = tess->num_patches;
3176 else if (radv_pipeline_has_gs(pipeline))
3177 ia_multi_vgt_param.primgroup_size = 64;
3178 else
3179 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3180
3181 ia_multi_vgt_param.partial_es_wave = false;
3182 if (pipeline->device->has_distributed_tess) {
3183 if (radv_pipeline_has_gs(pipeline)) {
3184 if (device->physical_device->rad_info.chip_class <= VI)
3185 ia_multi_vgt_param.partial_es_wave = true;
3186 }
3187 }
3188 /* GS requirement. */
3189 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3190 ia_multi_vgt_param.partial_es_wave = true;
3191
3192 ia_multi_vgt_param.wd_switch_on_eop = false;
3193 if (device->physical_device->rad_info.chip_class >= CIK) {
3194 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3195 * 4 shader engines. Set 1 to pass the assertion below.
3196 * The other cases are hardware requirements. */
3197 if (device->physical_device->rad_info.max_se < 4 ||
3198 prim == V_008958_DI_PT_POLYGON ||
3199 prim == V_008958_DI_PT_LINELOOP ||
3200 prim == V_008958_DI_PT_TRIFAN ||
3201 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3202 (pipeline->graphics.prim_restart_enable &&
3203 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3204 (prim != V_008958_DI_PT_POINTLIST &&
3205 prim != V_008958_DI_PT_LINESTRIP &&
3206 prim != V_008958_DI_PT_TRISTRIP))))
3207 ia_multi_vgt_param.wd_switch_on_eop = true;
3208 }
3209
3210 ia_multi_vgt_param.ia_switch_on_eoi = false;
3211 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3212 ia_multi_vgt_param.ia_switch_on_eoi = true;
3213 if (radv_pipeline_has_gs(pipeline) &&
3214 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3215 ia_multi_vgt_param.ia_switch_on_eoi = true;
3216 if (radv_pipeline_has_tess(pipeline)) {
3217 /* SWITCH_ON_EOI must be set if PrimID is used. */
3218 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3219 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3220 ia_multi_vgt_param.ia_switch_on_eoi = true;
3221 }
3222
3223 ia_multi_vgt_param.partial_vs_wave = false;
3224 if (radv_pipeline_has_tess(pipeline)) {
3225 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3226 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3227 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3228 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3229 radv_pipeline_has_gs(pipeline))
3230 ia_multi_vgt_param.partial_vs_wave = true;
3231 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3232 if (device->has_distributed_tess) {
3233 if (radv_pipeline_has_gs(pipeline)) {
3234 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3235 device->physical_device->rad_info.family == CHIP_FIJI ||
3236 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3237 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3238 device->physical_device->rad_info.family == CHIP_POLARIS12)
3239 ia_multi_vgt_param.partial_vs_wave = true;
3240 } else {
3241 ia_multi_vgt_param.partial_vs_wave = true;
3242 }
3243 }
3244 }
3245
3246 ia_multi_vgt_param.base =
3247 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3248 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3249 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3250 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3251 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3252
3253 return ia_multi_vgt_param;
3254 }
3255
3256
3257 static void
3258 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3259 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3260 {
3261 const VkPipelineVertexInputStateCreateInfo *vi_info =
3262 pCreateInfo->pVertexInputState;
3263 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3264
3265 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3266 const VkVertexInputAttributeDescription *desc =
3267 &vi_info->pVertexAttributeDescriptions[i];
3268 unsigned loc = desc->location;
3269 const struct vk_format_description *format_desc;
3270 int first_non_void;
3271 uint32_t num_format, data_format;
3272 format_desc = vk_format_description(desc->format);
3273 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3274
3275 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3276 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3277
3278 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3279 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3280 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3281 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3282 S_008F0C_NUM_FORMAT(num_format) |
3283 S_008F0C_DATA_FORMAT(data_format);
3284 velems->format_size[loc] = format_desc->block.bits / 8;
3285 velems->offset[loc] = desc->offset;
3286 velems->binding[loc] = desc->binding;
3287 velems->count = MAX2(velems->count, loc + 1);
3288 }
3289
3290 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3291 const VkVertexInputBindingDescription *desc =
3292 &vi_info->pVertexBindingDescriptions[i];
3293
3294 pipeline->binding_stride[desc->binding] = desc->stride;
3295 }
3296 }
3297
3298 static VkResult
3299 radv_pipeline_init(struct radv_pipeline *pipeline,
3300 struct radv_device *device,
3301 struct radv_pipeline_cache *cache,
3302 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3303 const struct radv_graphics_pipeline_create_info *extra,
3304 const VkAllocationCallbacks *alloc)
3305 {
3306 VkResult result;
3307 bool has_view_index = false;
3308
3309 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3310 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3311 if (subpass->view_mask)
3312 has_view_index = true;
3313 if (alloc == NULL)
3314 alloc = &device->alloc;
3315
3316 pipeline->device = device;
3317 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3318 assert(pipeline->layout);
3319
3320 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3321
3322 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3323 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3324 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3325 pStages[stage] = &pCreateInfo->pStages[i];
3326 }
3327
3328 radv_create_shaders(pipeline, device, cache,
3329 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3330 pStages);
3331
3332 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3333 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
3334 uint32_t gs_out;
3335 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3336
3337 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3338
3339 if (radv_pipeline_has_gs(pipeline)) {
3340 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3341 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3342 } else {
3343 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3344 }
3345 if (extra && extra->use_rectlist) {
3346 prim = V_008958_DI_PT_RECTLIST;
3347 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3348 pipeline->graphics.can_use_guardband = true;
3349 }
3350 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3351 /* prim vertex count will need TESS changes */
3352 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3353
3354 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3355
3356 /* Ensure that some export memory is always allocated, for two reasons:
3357 *
3358 * 1) Correctness: The hardware ignores the EXEC mask if no export
3359 * memory is allocated, so KILL and alpha test do not work correctly
3360 * without this.
3361 * 2) Performance: Every shader needs at least a NULL export, even when
3362 * it writes no color/depth output. The NULL export instruction
3363 * stalls without this setting.
3364 *
3365 * Don't add this to CB_SHADER_MASK.
3366 */
3367 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3368 if (!blend.spi_shader_col_format) {
3369 if (!ps->info.info.ps.writes_z &&
3370 !ps->info.info.ps.writes_stencil &&
3371 !ps->info.info.ps.writes_sample_mask)
3372 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3373 }
3374
3375 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3376 if (pipeline->shaders[i]) {
3377 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3378 }
3379 }
3380
3381 struct radv_gs_state gs = {0};
3382 if (radv_pipeline_has_gs(pipeline)) {
3383 gs = calculate_gs_info(pCreateInfo, pipeline);
3384 calculate_gs_ring_sizes(pipeline, &gs);
3385 }
3386
3387 struct radv_tessellation_state tess = {0};
3388 if (radv_pipeline_has_tess(pipeline)) {
3389 if (prim == V_008958_DI_PT_PATCH) {
3390 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3391 pipeline->graphics.prim_vertex_count.incr = 1;
3392 }
3393 tess = calculate_tess_state(pipeline, pCreateInfo);
3394 }
3395
3396 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3397
3398 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3399
3400 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3401 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3402
3403 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3404 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3405 if (loc->sgpr_idx != -1) {
3406 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3407 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3408 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3409 pipeline->graphics.vtx_emit_num = 3;
3410 else
3411 pipeline->graphics.vtx_emit_num = 2;
3412 }
3413
3414 result = radv_pipeline_scratch_init(device, pipeline);
3415 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3416
3417 return result;
3418 }
3419
3420 VkResult
3421 radv_graphics_pipeline_create(
3422 VkDevice _device,
3423 VkPipelineCache _cache,
3424 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3425 const struct radv_graphics_pipeline_create_info *extra,
3426 const VkAllocationCallbacks *pAllocator,
3427 VkPipeline *pPipeline)
3428 {
3429 RADV_FROM_HANDLE(radv_device, device, _device);
3430 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3431 struct radv_pipeline *pipeline;
3432 VkResult result;
3433
3434 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3435 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3436 if (pipeline == NULL)
3437 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3438
3439 result = radv_pipeline_init(pipeline, device, cache,
3440 pCreateInfo, extra, pAllocator);
3441 if (result != VK_SUCCESS) {
3442 radv_pipeline_destroy(device, pipeline, pAllocator);
3443 return result;
3444 }
3445
3446 *pPipeline = radv_pipeline_to_handle(pipeline);
3447
3448 return VK_SUCCESS;
3449 }
3450
3451 VkResult radv_CreateGraphicsPipelines(
3452 VkDevice _device,
3453 VkPipelineCache pipelineCache,
3454 uint32_t count,
3455 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3456 const VkAllocationCallbacks* pAllocator,
3457 VkPipeline* pPipelines)
3458 {
3459 VkResult result = VK_SUCCESS;
3460 unsigned i = 0;
3461
3462 for (; i < count; i++) {
3463 VkResult r;
3464 r = radv_graphics_pipeline_create(_device,
3465 pipelineCache,
3466 &pCreateInfos[i],
3467 NULL, pAllocator, &pPipelines[i]);
3468 if (r != VK_SUCCESS) {
3469 result = r;
3470 pPipelines[i] = VK_NULL_HANDLE;
3471 }
3472 }
3473
3474 return result;
3475 }
3476
3477
3478 static void
3479 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3480 {
3481 struct radv_shader_variant *compute_shader;
3482 struct radv_device *device = pipeline->device;
3483 unsigned compute_resource_limits;
3484 unsigned waves_per_threadgroup;
3485 uint64_t va;
3486
3487 pipeline->cs.buf = malloc(20 * 4);
3488 pipeline->cs.max_dw = 20;
3489
3490 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3491 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3492
3493 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3494 radeon_emit(&pipeline->cs, va >> 8);
3495 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3496
3497 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3498 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3499 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3500
3501 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3502 S_00B860_WAVES(pipeline->max_waves) |
3503 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3504
3505 /* Calculate best compute resource limits. */
3506 waves_per_threadgroup =
3507 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3508 compute_shader->info.cs.block_size[1] *
3509 compute_shader->info.cs.block_size[2], 64);
3510 compute_resource_limits =
3511 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3512
3513 if (device->physical_device->rad_info.chip_class >= CIK) {
3514 unsigned num_cu_per_se =
3515 device->physical_device->rad_info.num_good_compute_units /
3516 device->physical_device->rad_info.max_se;
3517
3518 /* Force even distribution on all SIMDs in CU if the workgroup
3519 * size is 64. This has shown some good improvements if # of
3520 * CUs per SE is not a multiple of 4.
3521 */
3522 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3523 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3524 }
3525
3526 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3527 compute_resource_limits);
3528
3529 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3530 radeon_emit(&pipeline->cs,
3531 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3532 radeon_emit(&pipeline->cs,
3533 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3534 radeon_emit(&pipeline->cs,
3535 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3536
3537 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3538 }
3539
3540 static VkResult radv_compute_pipeline_create(
3541 VkDevice _device,
3542 VkPipelineCache _cache,
3543 const VkComputePipelineCreateInfo* pCreateInfo,
3544 const VkAllocationCallbacks* pAllocator,
3545 VkPipeline* pPipeline)
3546 {
3547 RADV_FROM_HANDLE(radv_device, device, _device);
3548 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3549 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3550 struct radv_pipeline *pipeline;
3551 VkResult result;
3552
3553 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3554 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3555 if (pipeline == NULL)
3556 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3557
3558 pipeline->device = device;
3559 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3560 assert(pipeline->layout);
3561
3562 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3563 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3564
3565 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3566 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3567 result = radv_pipeline_scratch_init(device, pipeline);
3568 if (result != VK_SUCCESS) {
3569 radv_pipeline_destroy(device, pipeline, pAllocator);
3570 return result;
3571 }
3572
3573 radv_compute_generate_pm4(pipeline);
3574
3575 *pPipeline = radv_pipeline_to_handle(pipeline);
3576
3577 return VK_SUCCESS;
3578 }
3579
3580 VkResult radv_CreateComputePipelines(
3581 VkDevice _device,
3582 VkPipelineCache pipelineCache,
3583 uint32_t count,
3584 const VkComputePipelineCreateInfo* pCreateInfos,
3585 const VkAllocationCallbacks* pAllocator,
3586 VkPipeline* pPipelines)
3587 {
3588 VkResult result = VK_SUCCESS;
3589
3590 unsigned i = 0;
3591 for (; i < count; i++) {
3592 VkResult r;
3593 r = radv_compute_pipeline_create(_device, pipelineCache,
3594 &pCreateInfos[i],
3595 pAllocator, &pPipelines[i]);
3596 if (r != VK_SUCCESS) {
3597 result = r;
3598 pPipelines[i] = VK_NULL_HANDLE;
3599 }
3600 }
3601
3602 return result;
3603 }