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radv/tess: don't need to look in constant for vertices_per_patch
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t cb_color_control;
54 uint32_t cb_target_mask;
55 uint32_t sx_mrt_blend_opt[8];
56 uint32_t cb_blend_control[8];
57
58 uint32_t spi_shader_col_format;
59 uint32_t cb_shader_mask;
60 uint32_t db_alpha_to_mask;
61 };
62
63 struct radv_tessellation_state {
64 uint32_t ls_hs_config;
65 uint32_t tcs_in_layout;
66 uint32_t tcs_out_layout;
67 uint32_t tcs_out_offsets;
68 uint32_t offchip_layout;
69 unsigned num_patches;
70 unsigned lds_size;
71 unsigned num_tcs_input_cp;
72 uint32_t tf_param;
73 };
74
75 struct radv_gs_state {
76 uint32_t vgt_gs_onchip_cntl;
77 uint32_t vgt_gs_max_prims_per_subgroup;
78 uint32_t vgt_esgs_ring_itemsize;
79 uint32_t lds_size;
80 };
81
82 static void
83 radv_pipeline_destroy(struct radv_device *device,
84 struct radv_pipeline *pipeline,
85 const VkAllocationCallbacks* allocator)
86 {
87 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
88 if (pipeline->shaders[i])
89 radv_shader_variant_destroy(device, pipeline->shaders[i]);
90
91 if (pipeline->gs_copy_shader)
92 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
93
94 if(pipeline->cs.buf)
95 free(pipeline->cs.buf);
96 vk_free2(&device->alloc, allocator, pipeline);
97 }
98
99 void radv_DestroyPipeline(
100 VkDevice _device,
101 VkPipeline _pipeline,
102 const VkAllocationCallbacks* pAllocator)
103 {
104 RADV_FROM_HANDLE(radv_device, device, _device);
105 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
106
107 if (!_pipeline)
108 return;
109
110 radv_pipeline_destroy(device, pipeline, pAllocator);
111 }
112
113 static uint32_t get_hash_flags(struct radv_device *device)
114 {
115 uint32_t hash_flags = 0;
116
117 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
118 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
119 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
120 hash_flags |= RADV_HASH_SHADER_SISCHED;
121 return hash_flags;
122 }
123
124 static VkResult
125 radv_pipeline_scratch_init(struct radv_device *device,
126 struct radv_pipeline *pipeline)
127 {
128 unsigned scratch_bytes_per_wave = 0;
129 unsigned max_waves = 0;
130 unsigned min_waves = 1;
131
132 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
133 if (pipeline->shaders[i]) {
134 unsigned max_stage_waves = device->scratch_waves;
135
136 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
137 pipeline->shaders[i]->config.scratch_bytes_per_wave);
138
139 max_stage_waves = MIN2(max_stage_waves,
140 4 * device->physical_device->rad_info.num_good_compute_units *
141 (256 / pipeline->shaders[i]->config.num_vgprs));
142 max_waves = MAX2(max_waves, max_stage_waves);
143 }
144 }
145
146 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
147 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
148 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
149 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
150 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
151 }
152
153 if (scratch_bytes_per_wave)
154 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
155
156 if (scratch_bytes_per_wave && max_waves < min_waves) {
157 /* Not really true at this moment, but will be true on first
158 * execution. Avoid having hanging shaders. */
159 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
160 }
161 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
162 pipeline->max_waves = max_waves;
163 return VK_SUCCESS;
164 }
165
166 static uint32_t si_translate_blend_function(VkBlendOp op)
167 {
168 switch (op) {
169 case VK_BLEND_OP_ADD:
170 return V_028780_COMB_DST_PLUS_SRC;
171 case VK_BLEND_OP_SUBTRACT:
172 return V_028780_COMB_SRC_MINUS_DST;
173 case VK_BLEND_OP_REVERSE_SUBTRACT:
174 return V_028780_COMB_DST_MINUS_SRC;
175 case VK_BLEND_OP_MIN:
176 return V_028780_COMB_MIN_DST_SRC;
177 case VK_BLEND_OP_MAX:
178 return V_028780_COMB_MAX_DST_SRC;
179 default:
180 return 0;
181 }
182 }
183
184 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
185 {
186 switch (factor) {
187 case VK_BLEND_FACTOR_ZERO:
188 return V_028780_BLEND_ZERO;
189 case VK_BLEND_FACTOR_ONE:
190 return V_028780_BLEND_ONE;
191 case VK_BLEND_FACTOR_SRC_COLOR:
192 return V_028780_BLEND_SRC_COLOR;
193 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
194 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
195 case VK_BLEND_FACTOR_DST_COLOR:
196 return V_028780_BLEND_DST_COLOR;
197 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
198 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
199 case VK_BLEND_FACTOR_SRC_ALPHA:
200 return V_028780_BLEND_SRC_ALPHA;
201 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
202 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
203 case VK_BLEND_FACTOR_DST_ALPHA:
204 return V_028780_BLEND_DST_ALPHA;
205 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
206 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
207 case VK_BLEND_FACTOR_CONSTANT_COLOR:
208 return V_028780_BLEND_CONSTANT_COLOR;
209 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
210 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
211 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
212 return V_028780_BLEND_CONSTANT_ALPHA;
213 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
214 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
215 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
216 return V_028780_BLEND_SRC_ALPHA_SATURATE;
217 case VK_BLEND_FACTOR_SRC1_COLOR:
218 return V_028780_BLEND_SRC1_COLOR;
219 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
220 return V_028780_BLEND_INV_SRC1_COLOR;
221 case VK_BLEND_FACTOR_SRC1_ALPHA:
222 return V_028780_BLEND_SRC1_ALPHA;
223 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
224 return V_028780_BLEND_INV_SRC1_ALPHA;
225 default:
226 return 0;
227 }
228 }
229
230 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
231 {
232 switch (op) {
233 case VK_BLEND_OP_ADD:
234 return V_028760_OPT_COMB_ADD;
235 case VK_BLEND_OP_SUBTRACT:
236 return V_028760_OPT_COMB_SUBTRACT;
237 case VK_BLEND_OP_REVERSE_SUBTRACT:
238 return V_028760_OPT_COMB_REVSUBTRACT;
239 case VK_BLEND_OP_MIN:
240 return V_028760_OPT_COMB_MIN;
241 case VK_BLEND_OP_MAX:
242 return V_028760_OPT_COMB_MAX;
243 default:
244 return V_028760_OPT_COMB_BLEND_DISABLED;
245 }
246 }
247
248 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
249 {
250 switch (factor) {
251 case VK_BLEND_FACTOR_ZERO:
252 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
253 case VK_BLEND_FACTOR_ONE:
254 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
255 case VK_BLEND_FACTOR_SRC_COLOR:
256 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
257 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
258 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
259 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
260 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
261 case VK_BLEND_FACTOR_SRC_ALPHA:
262 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
263 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
264 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
265 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
266 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
267 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
268 default:
269 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
270 }
271 }
272
273 /**
274 * Get rid of DST in the blend factors by commuting the operands:
275 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
276 */
277 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
278 unsigned *dst_factor, unsigned expected_dst,
279 unsigned replacement_src)
280 {
281 if (*src_factor == expected_dst &&
282 *dst_factor == VK_BLEND_FACTOR_ZERO) {
283 *src_factor = VK_BLEND_FACTOR_ZERO;
284 *dst_factor = replacement_src;
285
286 /* Commuting the operands requires reversing subtractions. */
287 if (*func == VK_BLEND_OP_SUBTRACT)
288 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
289 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
290 *func = VK_BLEND_OP_SUBTRACT;
291 }
292 }
293
294 static bool si_blend_factor_uses_dst(unsigned factor)
295 {
296 return factor == VK_BLEND_FACTOR_DST_COLOR ||
297 factor == VK_BLEND_FACTOR_DST_ALPHA ||
298 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
299 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
300 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
301 }
302
303 static bool is_dual_src(VkBlendFactor factor)
304 {
305 switch (factor) {
306 case VK_BLEND_FACTOR_SRC1_COLOR:
307 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
308 case VK_BLEND_FACTOR_SRC1_ALPHA:
309 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
310 return true;
311 default:
312 return false;
313 }
314 }
315
316 static unsigned si_choose_spi_color_format(VkFormat vk_format,
317 bool blend_enable,
318 bool blend_need_alpha)
319 {
320 const struct vk_format_description *desc = vk_format_description(vk_format);
321 unsigned format, ntype, swap;
322
323 /* Alpha is needed for alpha-to-coverage.
324 * Blending may be with or without alpha.
325 */
326 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
327 unsigned alpha = 0; /* exports alpha, but may not support blending */
328 unsigned blend = 0; /* supports blending, but may not export alpha */
329 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
330
331 format = radv_translate_colorformat(vk_format);
332 ntype = radv_translate_color_numformat(vk_format, desc,
333 vk_format_get_first_non_void_channel(vk_format));
334 swap = radv_translate_colorswap(vk_format, false);
335
336 /* Choose the SPI color formats. These are required values for Stoney/RB+.
337 * Other chips have multiple choices, though they are not necessarily better.
338 */
339 switch (format) {
340 case V_028C70_COLOR_5_6_5:
341 case V_028C70_COLOR_1_5_5_5:
342 case V_028C70_COLOR_5_5_5_1:
343 case V_028C70_COLOR_4_4_4_4:
344 case V_028C70_COLOR_10_11_11:
345 case V_028C70_COLOR_11_11_10:
346 case V_028C70_COLOR_8:
347 case V_028C70_COLOR_8_8:
348 case V_028C70_COLOR_8_8_8_8:
349 case V_028C70_COLOR_10_10_10_2:
350 case V_028C70_COLOR_2_10_10_10:
351 if (ntype == V_028C70_NUMBER_UINT)
352 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
353 else if (ntype == V_028C70_NUMBER_SINT)
354 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
355 else
356 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
357 break;
358
359 case V_028C70_COLOR_16:
360 case V_028C70_COLOR_16_16:
361 case V_028C70_COLOR_16_16_16_16:
362 if (ntype == V_028C70_NUMBER_UNORM ||
363 ntype == V_028C70_NUMBER_SNORM) {
364 /* UNORM16 and SNORM16 don't support blending */
365 if (ntype == V_028C70_NUMBER_UNORM)
366 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
367 else
368 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
369
370 /* Use 32 bits per channel for blending. */
371 if (format == V_028C70_COLOR_16) {
372 if (swap == V_028C70_SWAP_STD) { /* R */
373 blend = V_028714_SPI_SHADER_32_R;
374 blend_alpha = V_028714_SPI_SHADER_32_AR;
375 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
376 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
377 else
378 assert(0);
379 } else if (format == V_028C70_COLOR_16_16) {
380 if (swap == V_028C70_SWAP_STD) { /* RG */
381 blend = V_028714_SPI_SHADER_32_GR;
382 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
383 } else if (swap == V_028C70_SWAP_ALT) /* RA */
384 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
385 else
386 assert(0);
387 } else /* 16_16_16_16 */
388 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
389 } else if (ntype == V_028C70_NUMBER_UINT)
390 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
391 else if (ntype == V_028C70_NUMBER_SINT)
392 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
393 else if (ntype == V_028C70_NUMBER_FLOAT)
394 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
395 else
396 assert(0);
397 break;
398
399 case V_028C70_COLOR_32:
400 if (swap == V_028C70_SWAP_STD) { /* R */
401 blend = normal = V_028714_SPI_SHADER_32_R;
402 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
403 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
404 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
405 else
406 assert(0);
407 break;
408
409 case V_028C70_COLOR_32_32:
410 if (swap == V_028C70_SWAP_STD) { /* RG */
411 blend = normal = V_028714_SPI_SHADER_32_GR;
412 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
413 } else if (swap == V_028C70_SWAP_ALT) /* RA */
414 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
415 else
416 assert(0);
417 break;
418
419 case V_028C70_COLOR_32_32_32_32:
420 case V_028C70_COLOR_8_24:
421 case V_028C70_COLOR_24_8:
422 case V_028C70_COLOR_X24_8_32_FLOAT:
423 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
424 break;
425
426 default:
427 unreachable("unhandled blend format");
428 }
429
430 if (blend_enable && blend_need_alpha)
431 return blend_alpha;
432 else if(blend_need_alpha)
433 return alpha;
434 else if(blend_enable)
435 return blend;
436 else
437 return normal;
438 }
439
440 static void
441 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
442 const VkGraphicsPipelineCreateInfo *pCreateInfo,
443 uint32_t blend_enable,
444 uint32_t blend_need_alpha,
445 bool single_cb_enable,
446 bool blend_mrt0_is_dual_src,
447 struct radv_blend_state *blend)
448 {
449 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
450 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
451 unsigned col_format = 0;
452
453 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
454 unsigned cf;
455
456 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
457 cf = V_028714_SPI_SHADER_ZERO;
458 } else {
459 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
460
461 cf = si_choose_spi_color_format(attachment->format,
462 blend_enable & (1 << i),
463 blend_need_alpha & (1 << i));
464 }
465
466 col_format |= cf << (4 * i);
467 }
468
469 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
470
471 if (blend_mrt0_is_dual_src)
472 col_format |= (col_format & 0xf) << 4;
473 blend->spi_shader_col_format = col_format;
474 }
475
476 static bool
477 format_is_int8(VkFormat format)
478 {
479 const struct vk_format_description *desc = vk_format_description(format);
480 int channel = vk_format_get_first_non_void_channel(format);
481
482 return channel >= 0 && desc->channel[channel].pure_integer &&
483 desc->channel[channel].size == 8;
484 }
485
486 static bool
487 format_is_int10(VkFormat format)
488 {
489 const struct vk_format_description *desc = vk_format_description(format);
490
491 if (desc->nr_channels != 4)
492 return false;
493 for (unsigned i = 0; i < 4; i++) {
494 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
495 return true;
496 }
497 return false;
498 }
499
500 unsigned radv_format_meta_fs_key(VkFormat format)
501 {
502 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
503 bool is_int8 = format_is_int8(format);
504 bool is_int10 = format_is_int10(format);
505
506 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
507 }
508
509 static void
510 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
511 unsigned *is_int8, unsigned *is_int10)
512 {
513 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
514 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
515 *is_int8 = 0;
516 *is_int10 = 0;
517
518 for (unsigned i = 0; i < subpass->color_count; ++i) {
519 struct radv_render_pass_attachment *attachment;
520
521 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
522 continue;
523
524 attachment = pass->attachments + subpass->color_attachments[i].attachment;
525
526 if (format_is_int8(attachment->format))
527 *is_int8 |= 1 << i;
528 if (format_is_int10(attachment->format))
529 *is_int10 |= 1 << i;
530 }
531 }
532
533 static struct radv_blend_state
534 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
535 const VkGraphicsPipelineCreateInfo *pCreateInfo,
536 const struct radv_graphics_pipeline_create_info *extra)
537 {
538 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
539 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
540 struct radv_blend_state blend = {0};
541 unsigned mode = V_028808_CB_NORMAL;
542 uint32_t blend_enable = 0, blend_need_alpha = 0;
543 bool blend_mrt0_is_dual_src = false;
544 int i;
545 bool single_cb_enable = false;
546
547 if (!vkblend)
548 return blend;
549
550 if (extra && extra->custom_blend_mode) {
551 single_cb_enable = true;
552 mode = extra->custom_blend_mode;
553 }
554 blend.cb_color_control = 0;
555 if (vkblend->logicOpEnable)
556 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
557 else
558 blend.cb_color_control |= S_028808_ROP3(0xcc);
559
560 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
561 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
562 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
563 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
564
565 if (vkms && vkms->alphaToCoverageEnable) {
566 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
567 }
568
569 blend.cb_target_mask = 0;
570 for (i = 0; i < vkblend->attachmentCount; i++) {
571 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
572 unsigned blend_cntl = 0;
573 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
574 VkBlendOp eqRGB = att->colorBlendOp;
575 VkBlendFactor srcRGB = att->srcColorBlendFactor;
576 VkBlendFactor dstRGB = att->dstColorBlendFactor;
577 VkBlendOp eqA = att->alphaBlendOp;
578 VkBlendFactor srcA = att->srcAlphaBlendFactor;
579 VkBlendFactor dstA = att->dstAlphaBlendFactor;
580
581 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
582
583 if (!att->colorWriteMask)
584 continue;
585
586 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
587 if (!att->blendEnable) {
588 blend.cb_blend_control[i] = blend_cntl;
589 continue;
590 }
591
592 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
593 if (i == 0)
594 blend_mrt0_is_dual_src = true;
595
596 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
597 srcRGB = VK_BLEND_FACTOR_ONE;
598 dstRGB = VK_BLEND_FACTOR_ONE;
599 }
600 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
601 srcA = VK_BLEND_FACTOR_ONE;
602 dstA = VK_BLEND_FACTOR_ONE;
603 }
604
605 /* Blending optimizations for RB+.
606 * These transformations don't change the behavior.
607 *
608 * First, get rid of DST in the blend factors:
609 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
610 */
611 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
612 VK_BLEND_FACTOR_DST_COLOR,
613 VK_BLEND_FACTOR_SRC_COLOR);
614
615 si_blend_remove_dst(&eqA, &srcA, &dstA,
616 VK_BLEND_FACTOR_DST_COLOR,
617 VK_BLEND_FACTOR_SRC_COLOR);
618
619 si_blend_remove_dst(&eqA, &srcA, &dstA,
620 VK_BLEND_FACTOR_DST_ALPHA,
621 VK_BLEND_FACTOR_SRC_ALPHA);
622
623 /* Look up the ideal settings from tables. */
624 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
625 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
626 srcA_opt = si_translate_blend_opt_factor(srcA, true);
627 dstA_opt = si_translate_blend_opt_factor(dstA, true);
628
629 /* Handle interdependencies. */
630 if (si_blend_factor_uses_dst(srcRGB))
631 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
632 if (si_blend_factor_uses_dst(srcA))
633 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
634
635 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
636 (dstRGB == VK_BLEND_FACTOR_ZERO ||
637 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
638 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
639 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
640
641 /* Set the final value. */
642 blend.sx_mrt_blend_opt[i] =
643 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
644 S_028760_COLOR_DST_OPT(dstRGB_opt) |
645 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
646 S_028760_ALPHA_SRC_OPT(srcA_opt) |
647 S_028760_ALPHA_DST_OPT(dstA_opt) |
648 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
649 blend_cntl |= S_028780_ENABLE(1);
650
651 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
652 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
653 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
654 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
655 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
656 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
657 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
658 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
659 }
660 blend.cb_blend_control[i] = blend_cntl;
661
662 blend_enable |= 1 << i;
663
664 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
665 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
666 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
667 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
668 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
669 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
670 blend_need_alpha |= 1 << i;
671 }
672 for (i = vkblend->attachmentCount; i < 8; i++) {
673 blend.cb_blend_control[i] = 0;
674 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
675 }
676
677 /* disable RB+ for now */
678 if (pipeline->device->physical_device->has_rbplus)
679 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
680
681 if (blend.cb_target_mask)
682 blend.cb_color_control |= S_028808_MODE(mode);
683 else
684 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
685
686 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
687 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src,
688 &blend);
689 return blend;
690 }
691
692 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
693 {
694 switch (op) {
695 case VK_STENCIL_OP_KEEP:
696 return V_02842C_STENCIL_KEEP;
697 case VK_STENCIL_OP_ZERO:
698 return V_02842C_STENCIL_ZERO;
699 case VK_STENCIL_OP_REPLACE:
700 return V_02842C_STENCIL_REPLACE_TEST;
701 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
702 return V_02842C_STENCIL_ADD_CLAMP;
703 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
704 return V_02842C_STENCIL_SUB_CLAMP;
705 case VK_STENCIL_OP_INVERT:
706 return V_02842C_STENCIL_INVERT;
707 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
708 return V_02842C_STENCIL_ADD_WRAP;
709 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
710 return V_02842C_STENCIL_SUB_WRAP;
711 default:
712 return 0;
713 }
714 }
715
716 static uint32_t si_translate_fill(VkPolygonMode func)
717 {
718 switch(func) {
719 case VK_POLYGON_MODE_FILL:
720 return V_028814_X_DRAW_TRIANGLES;
721 case VK_POLYGON_MODE_LINE:
722 return V_028814_X_DRAW_LINES;
723 case VK_POLYGON_MODE_POINT:
724 return V_028814_X_DRAW_POINTS;
725 default:
726 assert(0);
727 return V_028814_X_DRAW_POINTS;
728 }
729 }
730
731 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
732 {
733 uint32_t num_samples = vkms->rasterizationSamples;
734 uint32_t ps_iter_samples = 1;
735
736 if (vkms->sampleShadingEnable) {
737 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
738 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
739 }
740 return ps_iter_samples;
741 }
742
743 static void
744 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
745 const VkGraphicsPipelineCreateInfo *pCreateInfo)
746 {
747 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
748 struct radv_multisample_state *ms = &pipeline->graphics.ms;
749 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
750 int ps_iter_samples = 1;
751 uint32_t mask = 0xffff;
752
753 if (vkms)
754 ms->num_samples = vkms->rasterizationSamples;
755 else
756 ms->num_samples = 1;
757
758 if (vkms)
759 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
760 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
761 ps_iter_samples = ms->num_samples;
762 }
763
764 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
765 ms->pa_sc_aa_config = 0;
766 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
767 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
768 ms->pa_sc_mode_cntl_1 =
769 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
770 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
771 /* always 1: */
772 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
773 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
774 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
775 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
776 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
777 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
778 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
779 S_028A48_VPORT_SCISSOR_ENABLE(1);
780
781 if (ms->num_samples > 1) {
782 unsigned log_samples = util_logbase2(ms->num_samples);
783 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
784 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
785 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
786 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
787 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
788 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
789 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
790 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
791 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
792 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
793 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
794 if (ps_iter_samples > 1)
795 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
796 }
797
798 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
799 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
800 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
801 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
802 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
803 }
804
805 if (vkms && vkms->pSampleMask) {
806 mask = vkms->pSampleMask[0] & 0xffff;
807 }
808
809 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
810 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
811 }
812
813 static bool
814 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
815 {
816 switch (topology) {
817 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
818 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
819 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
820 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
821 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
822 return false;
823 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
824 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
825 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
826 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
827 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
828 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
829 return true;
830 default:
831 unreachable("unhandled primitive type");
832 }
833 }
834
835 static uint32_t
836 si_translate_prim(enum VkPrimitiveTopology topology)
837 {
838 switch (topology) {
839 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
840 return V_008958_DI_PT_POINTLIST;
841 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
842 return V_008958_DI_PT_LINELIST;
843 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
844 return V_008958_DI_PT_LINESTRIP;
845 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
846 return V_008958_DI_PT_TRILIST;
847 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
848 return V_008958_DI_PT_TRISTRIP;
849 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
850 return V_008958_DI_PT_TRIFAN;
851 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
852 return V_008958_DI_PT_LINELIST_ADJ;
853 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
854 return V_008958_DI_PT_LINESTRIP_ADJ;
855 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
856 return V_008958_DI_PT_TRILIST_ADJ;
857 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
858 return V_008958_DI_PT_TRISTRIP_ADJ;
859 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
860 return V_008958_DI_PT_PATCH;
861 default:
862 assert(0);
863 return 0;
864 }
865 }
866
867 static uint32_t
868 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
869 {
870 switch (gl_prim) {
871 case 0: /* GL_POINTS */
872 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
873 case 1: /* GL_LINES */
874 case 3: /* GL_LINE_STRIP */
875 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
876 case 0x8E7A: /* GL_ISOLINES */
877 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
878
879 case 4: /* GL_TRIANGLES */
880 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
881 case 5: /* GL_TRIANGLE_STRIP */
882 case 7: /* GL_QUADS */
883 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
884 default:
885 assert(0);
886 return 0;
887 }
888 }
889
890 static uint32_t
891 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
892 {
893 switch (topology) {
894 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
895 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
896 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
897 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
898 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
899 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
900 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
901 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
902 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
903 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
904 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
905 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
906 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
907 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
908 default:
909 assert(0);
910 return 0;
911 }
912 }
913
914 static unsigned si_map_swizzle(unsigned swizzle)
915 {
916 switch (swizzle) {
917 case VK_SWIZZLE_Y:
918 return V_008F0C_SQ_SEL_Y;
919 case VK_SWIZZLE_Z:
920 return V_008F0C_SQ_SEL_Z;
921 case VK_SWIZZLE_W:
922 return V_008F0C_SQ_SEL_W;
923 case VK_SWIZZLE_0:
924 return V_008F0C_SQ_SEL_0;
925 case VK_SWIZZLE_1:
926 return V_008F0C_SQ_SEL_1;
927 default: /* VK_SWIZZLE_X */
928 return V_008F0C_SQ_SEL_X;
929 }
930 }
931
932
933 static unsigned radv_dynamic_state_mask(VkDynamicState state)
934 {
935 switch(state) {
936 case VK_DYNAMIC_STATE_VIEWPORT:
937 return RADV_DYNAMIC_VIEWPORT;
938 case VK_DYNAMIC_STATE_SCISSOR:
939 return RADV_DYNAMIC_SCISSOR;
940 case VK_DYNAMIC_STATE_LINE_WIDTH:
941 return RADV_DYNAMIC_LINE_WIDTH;
942 case VK_DYNAMIC_STATE_DEPTH_BIAS:
943 return RADV_DYNAMIC_DEPTH_BIAS;
944 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
945 return RADV_DYNAMIC_BLEND_CONSTANTS;
946 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
947 return RADV_DYNAMIC_DEPTH_BOUNDS;
948 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
949 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
950 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
951 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
952 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
953 return RADV_DYNAMIC_STENCIL_REFERENCE;
954 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
955 return RADV_DYNAMIC_DISCARD_RECTANGLE;
956 default:
957 unreachable("Unhandled dynamic state");
958 }
959 }
960
961 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
962 {
963 uint32_t states = RADV_DYNAMIC_ALL;
964
965 /* If rasterization is disabled we do not care about any of the dynamic states,
966 * since they are all rasterization related only. */
967 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
968 return 0;
969
970 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
971 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
972
973 if (!pCreateInfo->pDepthStencilState ||
974 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
975 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
976
977 if (!pCreateInfo->pDepthStencilState ||
978 !pCreateInfo->pDepthStencilState->stencilTestEnable)
979 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
980 RADV_DYNAMIC_STENCIL_WRITE_MASK |
981 RADV_DYNAMIC_STENCIL_REFERENCE);
982
983 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
984 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
985
986 /* TODO: blend constants & line width. */
987
988 return states;
989 }
990
991
992 static void
993 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
994 const VkGraphicsPipelineCreateInfo *pCreateInfo)
995 {
996 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
997 uint32_t states = needed_states;
998 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
999 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1000
1001 pipeline->dynamic_state = default_dynamic_state;
1002 pipeline->graphics.needed_dynamic_state = needed_states;
1003
1004 if (pCreateInfo->pDynamicState) {
1005 /* Remove all of the states that are marked as dynamic */
1006 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1007 for (uint32_t s = 0; s < count; s++)
1008 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1009 }
1010
1011 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1012
1013 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1014 assert(pCreateInfo->pViewportState);
1015
1016 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1017 if (states & RADV_DYNAMIC_VIEWPORT) {
1018 typed_memcpy(dynamic->viewport.viewports,
1019 pCreateInfo->pViewportState->pViewports,
1020 pCreateInfo->pViewportState->viewportCount);
1021 }
1022 }
1023
1024 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1025 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1026 if (states & RADV_DYNAMIC_SCISSOR) {
1027 typed_memcpy(dynamic->scissor.scissors,
1028 pCreateInfo->pViewportState->pScissors,
1029 pCreateInfo->pViewportState->scissorCount);
1030 }
1031 }
1032
1033 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1034 assert(pCreateInfo->pRasterizationState);
1035 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1036 }
1037
1038 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1039 assert(pCreateInfo->pRasterizationState);
1040 dynamic->depth_bias.bias =
1041 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1042 dynamic->depth_bias.clamp =
1043 pCreateInfo->pRasterizationState->depthBiasClamp;
1044 dynamic->depth_bias.slope =
1045 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1046 }
1047
1048 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1049 *
1050 * pColorBlendState is [...] NULL if the pipeline has rasterization
1051 * disabled or if the subpass of the render pass the pipeline is
1052 * created against does not use any color attachments.
1053 */
1054 bool uses_color_att = false;
1055 for (unsigned i = 0; i < subpass->color_count; ++i) {
1056 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1057 uses_color_att = true;
1058 break;
1059 }
1060 }
1061
1062 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1063 assert(pCreateInfo->pColorBlendState);
1064 typed_memcpy(dynamic->blend_constants,
1065 pCreateInfo->pColorBlendState->blendConstants, 4);
1066 }
1067
1068 /* If there is no depthstencil attachment, then don't read
1069 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1070 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1071 * no need to override the depthstencil defaults in
1072 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1073 *
1074 * Section 9.2 of the Vulkan 1.0.15 spec says:
1075 *
1076 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1077 * disabled or if the subpass of the render pass the pipeline is created
1078 * against does not use a depth/stencil attachment.
1079 */
1080 if (needed_states &&
1081 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1082 assert(pCreateInfo->pDepthStencilState);
1083
1084 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1085 dynamic->depth_bounds.min =
1086 pCreateInfo->pDepthStencilState->minDepthBounds;
1087 dynamic->depth_bounds.max =
1088 pCreateInfo->pDepthStencilState->maxDepthBounds;
1089 }
1090
1091 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1092 dynamic->stencil_compare_mask.front =
1093 pCreateInfo->pDepthStencilState->front.compareMask;
1094 dynamic->stencil_compare_mask.back =
1095 pCreateInfo->pDepthStencilState->back.compareMask;
1096 }
1097
1098 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1099 dynamic->stencil_write_mask.front =
1100 pCreateInfo->pDepthStencilState->front.writeMask;
1101 dynamic->stencil_write_mask.back =
1102 pCreateInfo->pDepthStencilState->back.writeMask;
1103 }
1104
1105 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1106 dynamic->stencil_reference.front =
1107 pCreateInfo->pDepthStencilState->front.reference;
1108 dynamic->stencil_reference.back =
1109 pCreateInfo->pDepthStencilState->back.reference;
1110 }
1111 }
1112
1113 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1114 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1115 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1116 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1117 typed_memcpy(dynamic->discard_rectangle.rectangles,
1118 discard_rectangle_info->pDiscardRectangles,
1119 discard_rectangle_info->discardRectangleCount);
1120 }
1121
1122 pipeline->dynamic_state.mask = states;
1123 }
1124
1125 static struct radv_gs_state
1126 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1127 const struct radv_pipeline *pipeline)
1128 {
1129 struct radv_gs_state gs = {0};
1130 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1131 struct ac_es_output_info *es_info;
1132 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1133 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1134 else
1135 es_info = radv_pipeline_has_tess(pipeline) ?
1136 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1137 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1138
1139 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1140 bool uses_adjacency;
1141 switch(pCreateInfo->pInputAssemblyState->topology) {
1142 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1143 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1144 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1145 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1146 uses_adjacency = true;
1147 break;
1148 default:
1149 uses_adjacency = false;
1150 break;
1151 }
1152
1153 /* All these are in dwords: */
1154 /* We can't allow using the whole LDS, because GS waves compete with
1155 * other shader stages for LDS space. */
1156 const unsigned max_lds_size = 8 * 1024;
1157 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1158 unsigned esgs_lds_size;
1159
1160 /* All these are per subgroup: */
1161 const unsigned max_out_prims = 32 * 1024;
1162 const unsigned max_es_verts = 255;
1163 const unsigned ideal_gs_prims = 64;
1164 unsigned max_gs_prims, gs_prims;
1165 unsigned min_es_verts, es_verts, worst_case_es_verts;
1166
1167 if (uses_adjacency || gs_num_invocations > 1)
1168 max_gs_prims = 127 / gs_num_invocations;
1169 else
1170 max_gs_prims = 255;
1171
1172 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1173 * Make sure we don't go over the maximum value.
1174 */
1175 if (gs_info->gs.vertices_out > 0) {
1176 max_gs_prims = MIN2(max_gs_prims,
1177 max_out_prims /
1178 (gs_info->gs.vertices_out * gs_num_invocations));
1179 }
1180 assert(max_gs_prims > 0);
1181
1182 /* If the primitive has adjacency, halve the number of vertices
1183 * that will be reused in multiple primitives.
1184 */
1185 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1186
1187 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1188 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1189
1190 /* Compute ESGS LDS size based on the worst case number of ES vertices
1191 * needed to create the target number of GS prims per subgroup.
1192 */
1193 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1194
1195 /* If total LDS usage is too big, refactor partitions based on ratio
1196 * of ESGS item sizes.
1197 */
1198 if (esgs_lds_size > max_lds_size) {
1199 /* Our target GS Prims Per Subgroup was too large. Calculate
1200 * the maximum number of GS Prims Per Subgroup that will fit
1201 * into LDS, capped by the maximum that the hardware can support.
1202 */
1203 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1204 max_gs_prims);
1205 assert(gs_prims > 0);
1206 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1207 max_es_verts);
1208
1209 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1210 assert(esgs_lds_size <= max_lds_size);
1211 }
1212
1213 /* Now calculate remaining ESGS information. */
1214 if (esgs_lds_size)
1215 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1216 else
1217 es_verts = max_es_verts;
1218
1219 /* Vertices for adjacency primitives are not always reused, so restore
1220 * it for ES_VERTS_PER_SUBGRP.
1221 */
1222 min_es_verts = gs_info->gs.vertices_in;
1223
1224 /* For normal primitives, the VGT only checks if they are past the ES
1225 * verts per subgroup after allocating a full GS primitive and if they
1226 * are, kick off a new subgroup. But if those additional ES verts are
1227 * unique (e.g. not reused) we need to make sure there is enough LDS
1228 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1229 */
1230 es_verts -= min_es_verts - 1;
1231
1232 uint32_t es_verts_per_subgroup = es_verts;
1233 uint32_t gs_prims_per_subgroup = gs_prims;
1234 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1235 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1236 gs.lds_size = align(esgs_lds_size, 128) / 128;
1237 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1238 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1239 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1240 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1241 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1242 assert(max_prims_per_subgroup <= max_out_prims);
1243
1244 return gs;
1245 }
1246
1247 static void
1248 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1249 {
1250 struct radv_device *device = pipeline->device;
1251 unsigned num_se = device->physical_device->rad_info.max_se;
1252 unsigned wave_size = 64;
1253 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1254 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1255 unsigned alignment = 256 * num_se;
1256 /* The maximum size is 63.999 MB per SE. */
1257 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1258 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1259
1260 /* Calculate the minimum size. */
1261 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1262 wave_size, alignment);
1263 /* These are recommended sizes, not minimum sizes. */
1264 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1265 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1266 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1267 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1268
1269 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1270 esgs_ring_size = align(esgs_ring_size, alignment);
1271 gsvs_ring_size = align(gsvs_ring_size, alignment);
1272
1273 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1274 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1275
1276 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1277 }
1278
1279 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1280 unsigned *lds_size)
1281 {
1282 /* SPI barrier management bug:
1283 * Make sure we have at least 4k of LDS in use to avoid the bug.
1284 * It applies to workgroup sizes of more than one wavefront.
1285 */
1286 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1287 device->physical_device->rad_info.family == CHIP_KABINI ||
1288 device->physical_device->rad_info.family == CHIP_MULLINS)
1289 *lds_size = MAX2(*lds_size, 8);
1290 }
1291
1292 struct radv_shader_variant *
1293 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1294 {
1295 if (pipeline->shaders[MESA_SHADER_VERTEX])
1296 return pipeline->shaders[MESA_SHADER_VERTEX];
1297 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1298 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1299 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1300 }
1301
1302 static struct radv_shader_variant *
1303 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1304 {
1305 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1306 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1307 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1308 }
1309
1310 static struct radv_tessellation_state
1311 calculate_tess_state(struct radv_pipeline *pipeline,
1312 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1313 {
1314 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1315 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1316 unsigned num_tcs_patch_outputs;
1317 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1318 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1319 unsigned lds_size, hardware_lds_size;
1320 unsigned perpatch_output_offset;
1321 unsigned num_patches;
1322 struct radv_tessellation_state tess = {0};
1323
1324 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1325 * are laid out in LDS. */
1326 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1327
1328 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1329 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1330 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1331
1332 /* Ensure that we only need one wave per SIMD so we don't need to check
1333 * resource usage. Also ensures that the number of tcs in and out
1334 * vertices per threadgroup are at most 256.
1335 */
1336 input_vertex_size = num_tcs_inputs * 16;
1337 output_vertex_size = num_tcs_outputs * 16;
1338
1339 input_patch_size = num_tcs_input_cp * input_vertex_size;
1340
1341 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1342 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1343 /* Ensure that we only need one wave per SIMD so we don't need to check
1344 * resource usage. Also ensures that the number of tcs in and out
1345 * vertices per threadgroup are at most 256.
1346 */
1347 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1348
1349 /* Make sure that the data fits in LDS. This assumes the shaders only
1350 * use LDS for the inputs and outputs.
1351 */
1352 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1353 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1354
1355 /* Make sure the output data fits in the offchip buffer */
1356 num_patches = MIN2(num_patches,
1357 (pipeline->device->tess_offchip_block_dw_size * 4) /
1358 output_patch_size);
1359
1360 /* Not necessary for correctness, but improves performance. The
1361 * specific value is taken from the proprietary driver.
1362 */
1363 num_patches = MIN2(num_patches, 40);
1364
1365 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1366 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1367 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1368 num_patches = MIN2(num_patches, one_wave);
1369 }
1370
1371 output_patch0_offset = input_patch_size * num_patches;
1372 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1373
1374 lds_size = output_patch0_offset + output_patch_size * num_patches;
1375
1376 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1377 assert(lds_size <= 65536);
1378 lds_size = align(lds_size, 512) / 512;
1379 } else {
1380 assert(lds_size <= 32768);
1381 lds_size = align(lds_size, 256) / 256;
1382 }
1383 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1384
1385 tess.lds_size = lds_size;
1386
1387 tess.tcs_in_layout = (input_patch_size / 4) |
1388 ((input_vertex_size / 4) << 13);
1389 tess.tcs_out_layout = (output_patch_size / 4) |
1390 ((output_vertex_size / 4) << 13);
1391 tess.tcs_out_offsets = (output_patch0_offset / 16) |
1392 ((perpatch_output_offset / 16) << 16);
1393 tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1394 num_patches;
1395
1396 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1397 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1398 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1399 tess.num_patches = num_patches;
1400 tess.num_tcs_input_cp = num_tcs_input_cp;
1401
1402 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1403 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1404
1405 switch (tes->info.tes.primitive_mode) {
1406 case GL_TRIANGLES:
1407 type = V_028B6C_TESS_TRIANGLE;
1408 break;
1409 case GL_QUADS:
1410 type = V_028B6C_TESS_QUAD;
1411 break;
1412 case GL_ISOLINES:
1413 type = V_028B6C_TESS_ISOLINE;
1414 break;
1415 }
1416
1417 switch (tes->info.tes.spacing) {
1418 case TESS_SPACING_EQUAL:
1419 partitioning = V_028B6C_PART_INTEGER;
1420 break;
1421 case TESS_SPACING_FRACTIONAL_ODD:
1422 partitioning = V_028B6C_PART_FRAC_ODD;
1423 break;
1424 case TESS_SPACING_FRACTIONAL_EVEN:
1425 partitioning = V_028B6C_PART_FRAC_EVEN;
1426 break;
1427 default:
1428 break;
1429 }
1430
1431 bool ccw = tes->info.tes.ccw;
1432 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1433 vk_find_struct_const(pCreateInfo->pTessellationState,
1434 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1435
1436 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1437 ccw = !ccw;
1438
1439 if (tes->info.tes.point_mode)
1440 topology = V_028B6C_OUTPUT_POINT;
1441 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1442 topology = V_028B6C_OUTPUT_LINE;
1443 else if (ccw)
1444 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1445 else
1446 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1447
1448 if (pipeline->device->has_distributed_tess) {
1449 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1450 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1451 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1452 else
1453 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1454 } else
1455 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1456
1457 tess.tf_param = S_028B6C_TYPE(type) |
1458 S_028B6C_PARTITIONING(partitioning) |
1459 S_028B6C_TOPOLOGY(topology) |
1460 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1461
1462 return tess;
1463 }
1464
1465 static const struct radv_prim_vertex_count prim_size_table[] = {
1466 [V_008958_DI_PT_NONE] = {0, 0},
1467 [V_008958_DI_PT_POINTLIST] = {1, 1},
1468 [V_008958_DI_PT_LINELIST] = {2, 2},
1469 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1470 [V_008958_DI_PT_TRILIST] = {3, 3},
1471 [V_008958_DI_PT_TRIFAN] = {3, 1},
1472 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1473 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1474 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1475 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1476 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1477 [V_008958_DI_PT_RECTLIST] = {3, 3},
1478 [V_008958_DI_PT_LINELOOP] = {2, 1},
1479 [V_008958_DI_PT_POLYGON] = {3, 1},
1480 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1481 };
1482
1483 static const struct ac_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1484 {
1485 if (radv_pipeline_has_gs(pipeline))
1486 return &pipeline->gs_copy_shader->info.vs.outinfo;
1487 else if (radv_pipeline_has_tess(pipeline))
1488 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1489 else
1490 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1491 }
1492
1493 static void
1494 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1495 {
1496 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1497 int shader_count = 0;
1498
1499 if(shaders[MESA_SHADER_FRAGMENT]) {
1500 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1501 }
1502 if(shaders[MESA_SHADER_GEOMETRY]) {
1503 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1504 }
1505 if(shaders[MESA_SHADER_TESS_EVAL]) {
1506 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1507 }
1508 if(shaders[MESA_SHADER_TESS_CTRL]) {
1509 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1510 }
1511 if(shaders[MESA_SHADER_VERTEX]) {
1512 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1513 }
1514
1515 for (int i = 1; i < shader_count; ++i) {
1516 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1517 ordered_shaders[i - 1]);
1518
1519 nir_remove_dead_variables(ordered_shaders[i],
1520 nir_var_shader_out);
1521 nir_remove_dead_variables(ordered_shaders[i - 1],
1522 nir_var_shader_in);
1523
1524 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1525 ordered_shaders[i - 1]);
1526
1527 nir_compact_varyings(ordered_shaders[i],
1528 ordered_shaders[i - 1], true);
1529
1530 if (progress) {
1531 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1532 radv_lower_indirect_derefs(ordered_shaders[i],
1533 pipeline->device->physical_device);
1534 }
1535 radv_optimize_nir(ordered_shaders[i]);
1536
1537 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1538 radv_lower_indirect_derefs(ordered_shaders[i - 1],
1539 pipeline->device->physical_device);
1540 }
1541 radv_optimize_nir(ordered_shaders[i - 1]);
1542 }
1543 }
1544 }
1545
1546
1547 static struct radv_pipeline_key
1548 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1549 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1550 const struct radv_blend_state *blend,
1551 bool has_view_index)
1552 {
1553 const VkPipelineVertexInputStateCreateInfo *input_state =
1554 pCreateInfo->pVertexInputState;
1555 struct radv_pipeline_key key;
1556 memset(&key, 0, sizeof(key));
1557
1558 key.has_multiview_view_index = has_view_index;
1559
1560 uint32_t binding_input_rate = 0;
1561 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1562 if (input_state->pVertexBindingDescriptions[i].inputRate)
1563 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1564 }
1565
1566 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1567 unsigned binding;
1568 binding = input_state->pVertexAttributeDescriptions[i].binding;
1569 if (binding_input_rate & (1u << binding))
1570 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1571 }
1572
1573 if (pCreateInfo->pTessellationState)
1574 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1575
1576
1577 if (pCreateInfo->pMultisampleState &&
1578 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1579 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1580 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1581 key.multisample = true;
1582 key.log2_num_samples = util_logbase2(num_samples);
1583 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1584 }
1585
1586 key.col_format = blend->spi_shader_col_format;
1587 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1588 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1589
1590 return key;
1591 }
1592
1593 static void
1594 radv_fill_shader_keys(struct ac_shader_variant_key *keys,
1595 const struct radv_pipeline_key *key,
1596 nir_shader **nir)
1597 {
1598 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1599
1600 if (nir[MESA_SHADER_TESS_CTRL]) {
1601 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1602 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1603 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1604
1605 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1606 }
1607
1608 if (nir[MESA_SHADER_GEOMETRY]) {
1609 if (nir[MESA_SHADER_TESS_CTRL])
1610 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1611 else
1612 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1613 }
1614
1615 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1616 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1617
1618 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1619 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1620 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1621 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1622 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1623 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1624 }
1625
1626 static void
1627 merge_tess_info(struct shader_info *tes_info,
1628 const struct shader_info *tcs_info)
1629 {
1630 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1631 *
1632 * "PointMode. Controls generation of points rather than triangles
1633 * or lines. This functionality defaults to disabled, and is
1634 * enabled if either shader stage includes the execution mode.
1635 *
1636 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1637 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1638 * and OutputVertices, it says:
1639 *
1640 * "One mode must be set in at least one of the tessellation
1641 * shader stages."
1642 *
1643 * So, the fields can be set in either the TCS or TES, but they must
1644 * agree if set in both. Our backend looks at TES, so bitwise-or in
1645 * the values from the TCS.
1646 */
1647 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1648 tes_info->tess.tcs_vertices_out == 0 ||
1649 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1650 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1651
1652 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1653 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1654 tcs_info->tess.spacing == tes_info->tess.spacing);
1655 tes_info->tess.spacing |= tcs_info->tess.spacing;
1656
1657 assert(tcs_info->tess.primitive_mode == 0 ||
1658 tes_info->tess.primitive_mode == 0 ||
1659 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1660 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1661 tes_info->tess.ccw |= tcs_info->tess.ccw;
1662 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1663 }
1664
1665 static
1666 void radv_create_shaders(struct radv_pipeline *pipeline,
1667 struct radv_device *device,
1668 struct radv_pipeline_cache *cache,
1669 struct radv_pipeline_key key,
1670 const VkPipelineShaderStageCreateInfo **pStages)
1671 {
1672 struct radv_shader_module fs_m = {0};
1673 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1674 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1675 void *codes[MESA_SHADER_STAGES] = {0};
1676 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1677 struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1678 unsigned char hash[20], gs_copy_hash[20];
1679
1680 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1681 if (pStages[i]) {
1682 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1683 if (modules[i]->nir)
1684 _mesa_sha1_compute(modules[i]->nir->info.name,
1685 strlen(modules[i]->nir->info.name),
1686 modules[i]->sha1);
1687 }
1688 }
1689
1690 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1691 memcpy(gs_copy_hash, hash, 20);
1692 gs_copy_hash[0] ^= 1;
1693
1694 if (modules[MESA_SHADER_GEOMETRY]) {
1695 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1696 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1697 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1698 }
1699
1700 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1701 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1702 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1703 if (pipeline->shaders[i])
1704 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1705 }
1706 return;
1707 }
1708
1709 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1710 nir_builder fs_b;
1711 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1712 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1713 fs_m.nir = fs_b.shader;
1714 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1715 }
1716
1717 /* Determine first and last stage. */
1718 unsigned first = MESA_SHADER_STAGES;
1719 unsigned last = 0;
1720 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1721 if (!pStages[i])
1722 continue;
1723 if (first == MESA_SHADER_STAGES)
1724 first = i;
1725 last = i;
1726 }
1727
1728 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1729 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1730
1731 if (!modules[i])
1732 continue;
1733
1734 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1735 stage ? stage->pName : "main", i,
1736 stage ? stage->pSpecializationInfo : NULL);
1737 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1738
1739 /* We don't want to alter meta shaders IR directly so clone it
1740 * first.
1741 */
1742 if (nir[i]->info.name) {
1743 nir[i] = nir_shader_clone(NULL, nir[i]);
1744 }
1745
1746 if (first != last) {
1747 nir_variable_mode mask = 0;
1748
1749 if (i != first)
1750 mask = mask | nir_var_shader_in;
1751
1752 if (i != last)
1753 mask = mask | nir_var_shader_out;
1754
1755 nir_lower_io_to_scalar_early(nir[i], mask);
1756 radv_optimize_nir(nir[i]);
1757 }
1758 }
1759
1760 if (nir[MESA_SHADER_TESS_CTRL]) {
1761 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1762 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1763 }
1764
1765 radv_link_shaders(pipeline, nir);
1766
1767 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1768 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1769 nir_print_shader(nir[i], stderr);
1770 }
1771
1772 radv_fill_shader_keys(keys, &key, nir);
1773
1774 if (nir[MESA_SHADER_FRAGMENT]) {
1775 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1776 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1777 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1778 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1779 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1780 }
1781
1782 /* TODO: These are no longer used as keys we should refactor this */
1783 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1784 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1785 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1786 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1787 }
1788
1789 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1790 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1791 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1792 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1793 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1794 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1795 pipeline->layout,
1796 &key, &codes[MESA_SHADER_TESS_CTRL],
1797 &code_sizes[MESA_SHADER_TESS_CTRL]);
1798 }
1799 modules[MESA_SHADER_VERTEX] = NULL;
1800 }
1801
1802 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1803 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1804 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1805 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1806 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1807 pipeline->layout,
1808 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1809 &code_sizes[MESA_SHADER_GEOMETRY]);
1810 }
1811 modules[pre_stage] = NULL;
1812 }
1813
1814 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1815 if(modules[i] && !pipeline->shaders[i]) {
1816 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1817 pipeline->layout,
1818 keys + i, &codes[i],
1819 &code_sizes[i]);
1820 }
1821 }
1822
1823 if(modules[MESA_SHADER_GEOMETRY]) {
1824 void *gs_copy_code = NULL;
1825 unsigned gs_copy_code_size = 0;
1826 if (!pipeline->gs_copy_shader) {
1827 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1828 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1829 &gs_copy_code_size,
1830 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1831 }
1832
1833 if (pipeline->gs_copy_shader) {
1834 void *code[MESA_SHADER_STAGES] = {0};
1835 unsigned code_size[MESA_SHADER_STAGES] = {0};
1836 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1837
1838 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1839 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1840 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1841
1842 radv_pipeline_cache_insert_shaders(device, cache,
1843 gs_copy_hash,
1844 variants,
1845 (const void**)code,
1846 code_size);
1847 }
1848 free(gs_copy_code);
1849 }
1850
1851 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1852 (const void**)codes, code_sizes);
1853
1854 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1855 free(codes[i]);
1856 if (modules[i]) {
1857 if (!pipeline->device->keep_shader_info)
1858 ralloc_free(nir[i]);
1859
1860 if (radv_can_dump_shader_stats(device, modules[i]))
1861 radv_shader_dump_stats(device,
1862 pipeline->shaders[i],
1863 i, stderr);
1864 }
1865 }
1866
1867 if (fs_m.nir)
1868 ralloc_free(fs_m.nir);
1869 }
1870
1871 static uint32_t
1872 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1873 gl_shader_stage stage, enum chip_class chip_class)
1874 {
1875 bool has_gs = radv_pipeline_has_gs(pipeline);
1876 bool has_tess = radv_pipeline_has_tess(pipeline);
1877 switch (stage) {
1878 case MESA_SHADER_FRAGMENT:
1879 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1880 case MESA_SHADER_VERTEX:
1881 if (chip_class >= GFX9) {
1882 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1883 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1884 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1885 }
1886 if (has_tess)
1887 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1888 else
1889 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1890 case MESA_SHADER_GEOMETRY:
1891 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1892 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1893 case MESA_SHADER_COMPUTE:
1894 return R_00B900_COMPUTE_USER_DATA_0;
1895 case MESA_SHADER_TESS_CTRL:
1896 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1897 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1898 case MESA_SHADER_TESS_EVAL:
1899 if (chip_class >= GFX9) {
1900 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1901 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1902 }
1903 if (has_gs)
1904 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1905 else
1906 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1907 default:
1908 unreachable("unknown shader");
1909 }
1910 }
1911
1912 struct radv_bin_size_entry {
1913 unsigned bpp;
1914 VkExtent2D extent;
1915 };
1916
1917 static VkExtent2D
1918 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1919 {
1920 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1921 {
1922 /* One RB / SE */
1923 {
1924 /* One shader engine */
1925 { 0, {128, 128}},
1926 { 1, { 64, 128}},
1927 { 2, { 32, 128}},
1928 { 3, { 16, 128}},
1929 { 17, { 0, 0}},
1930 { UINT_MAX, { 0, 0}},
1931 },
1932 {
1933 /* Two shader engines */
1934 { 0, {128, 128}},
1935 { 2, { 64, 128}},
1936 { 3, { 32, 128}},
1937 { 5, { 16, 128}},
1938 { 17, { 0, 0}},
1939 { UINT_MAX, { 0, 0}},
1940 },
1941 {
1942 /* Four shader engines */
1943 { 0, {128, 128}},
1944 { 3, { 64, 128}},
1945 { 5, { 16, 128}},
1946 { 17, { 0, 0}},
1947 { UINT_MAX, { 0, 0}},
1948 },
1949 },
1950 {
1951 /* Two RB / SE */
1952 {
1953 /* One shader engine */
1954 { 0, {128, 128}},
1955 { 2, { 64, 128}},
1956 { 3, { 32, 128}},
1957 { 5, { 16, 128}},
1958 { 33, { 0, 0}},
1959 { UINT_MAX, { 0, 0}},
1960 },
1961 {
1962 /* Two shader engines */
1963 { 0, {128, 128}},
1964 { 3, { 64, 128}},
1965 { 5, { 32, 128}},
1966 { 9, { 16, 128}},
1967 { 33, { 0, 0}},
1968 { UINT_MAX, { 0, 0}},
1969 },
1970 {
1971 /* Four shader engines */
1972 { 0, {256, 256}},
1973 { 2, {128, 256}},
1974 { 3, {128, 128}},
1975 { 5, { 64, 128}},
1976 { 9, { 16, 128}},
1977 { 33, { 0, 0}},
1978 { UINT_MAX, { 0, 0}},
1979 },
1980 },
1981 {
1982 /* Four RB / SE */
1983 {
1984 /* One shader engine */
1985 { 0, {128, 256}},
1986 { 2, {128, 128}},
1987 { 3, { 64, 128}},
1988 { 5, { 32, 128}},
1989 { 9, { 16, 128}},
1990 { 33, { 0, 0}},
1991 { UINT_MAX, { 0, 0}},
1992 },
1993 {
1994 /* Two shader engines */
1995 { 0, {256, 256}},
1996 { 2, {128, 256}},
1997 { 3, {128, 128}},
1998 { 5, { 64, 128}},
1999 { 9, { 32, 128}},
2000 { 17, { 16, 128}},
2001 { 33, { 0, 0}},
2002 { UINT_MAX, { 0, 0}},
2003 },
2004 {
2005 /* Four shader engines */
2006 { 0, {256, 512}},
2007 { 2, {256, 256}},
2008 { 3, {128, 256}},
2009 { 5, {128, 128}},
2010 { 9, { 64, 128}},
2011 { 17, { 16, 128}},
2012 { 33, { 0, 0}},
2013 { UINT_MAX, { 0, 0}},
2014 },
2015 },
2016 };
2017 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2018 {
2019 // One RB / SE
2020 {
2021 // One shader engine
2022 { 0, {128, 256}},
2023 { 2, {128, 128}},
2024 { 4, { 64, 128}},
2025 { 7, { 32, 128}},
2026 { 13, { 16, 128}},
2027 { 49, { 0, 0}},
2028 { UINT_MAX, { 0, 0}},
2029 },
2030 {
2031 // Two shader engines
2032 { 0, {256, 256}},
2033 { 2, {128, 256}},
2034 { 4, {128, 128}},
2035 { 7, { 64, 128}},
2036 { 13, { 32, 128}},
2037 { 25, { 16, 128}},
2038 { 49, { 0, 0}},
2039 { UINT_MAX, { 0, 0}},
2040 },
2041 {
2042 // Four shader engines
2043 { 0, {256, 512}},
2044 { 2, {256, 256}},
2045 { 4, {128, 256}},
2046 { 7, {128, 128}},
2047 { 13, { 64, 128}},
2048 { 25, { 16, 128}},
2049 { 49, { 0, 0}},
2050 { UINT_MAX, { 0, 0}},
2051 },
2052 },
2053 {
2054 // Two RB / SE
2055 {
2056 // One shader engine
2057 { 0, {256, 256}},
2058 { 2, {128, 256}},
2059 { 4, {128, 128}},
2060 { 7, { 64, 128}},
2061 { 13, { 32, 128}},
2062 { 25, { 16, 128}},
2063 { 97, { 0, 0}},
2064 { UINT_MAX, { 0, 0}},
2065 },
2066 {
2067 // Two shader engines
2068 { 0, {256, 512}},
2069 { 2, {256, 256}},
2070 { 4, {128, 256}},
2071 { 7, {128, 128}},
2072 { 13, { 64, 128}},
2073 { 25, { 32, 128}},
2074 { 49, { 16, 128}},
2075 { 97, { 0, 0}},
2076 { UINT_MAX, { 0, 0}},
2077 },
2078 {
2079 // Four shader engines
2080 { 0, {512, 512}},
2081 { 2, {256, 512}},
2082 { 4, {256, 256}},
2083 { 7, {128, 256}},
2084 { 13, {128, 128}},
2085 { 25, { 64, 128}},
2086 { 49, { 16, 128}},
2087 { 97, { 0, 0}},
2088 { UINT_MAX, { 0, 0}},
2089 },
2090 },
2091 {
2092 // Four RB / SE
2093 {
2094 // One shader engine
2095 { 0, {256, 512}},
2096 { 2, {256, 256}},
2097 { 4, {128, 256}},
2098 { 7, {128, 128}},
2099 { 13, { 64, 128}},
2100 { 25, { 32, 128}},
2101 { 49, { 16, 128}},
2102 { UINT_MAX, { 0, 0}},
2103 },
2104 {
2105 // Two shader engines
2106 { 0, {512, 512}},
2107 { 2, {256, 512}},
2108 { 4, {256, 256}},
2109 { 7, {128, 256}},
2110 { 13, {128, 128}},
2111 { 25, { 64, 128}},
2112 { 49, { 32, 128}},
2113 { 97, { 16, 128}},
2114 { UINT_MAX, { 0, 0}},
2115 },
2116 {
2117 // Four shader engines
2118 { 0, {512, 512}},
2119 { 4, {256, 512}},
2120 { 7, {256, 256}},
2121 { 13, {128, 256}},
2122 { 25, {128, 128}},
2123 { 49, { 64, 128}},
2124 { 97, { 16, 128}},
2125 { UINT_MAX, { 0, 0}},
2126 },
2127 },
2128 };
2129
2130 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2131 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2132 VkExtent2D extent = {512, 512};
2133
2134 unsigned log_num_rb_per_se =
2135 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2136 pipeline->device->physical_device->rad_info.max_se);
2137 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2138
2139 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2140 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2141 unsigned effective_samples = total_samples;
2142 unsigned color_bytes_per_pixel = 0;
2143
2144 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2145 if (vkblend) {
2146 for (unsigned i = 0; i < subpass->color_count; i++) {
2147 if (!vkblend->pAttachments[i].colorWriteMask)
2148 continue;
2149
2150 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2151 continue;
2152
2153 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2154 color_bytes_per_pixel += vk_format_get_blocksize(format);
2155 }
2156
2157 /* MSAA images typically don't use all samples all the time. */
2158 if (effective_samples >= 2 && ps_iter_samples <= 1)
2159 effective_samples = 2;
2160 color_bytes_per_pixel *= effective_samples;
2161 }
2162
2163 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2164 while(color_entry->bpp <= color_bytes_per_pixel)
2165 ++color_entry;
2166
2167 extent = color_entry->extent;
2168
2169 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2170 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2171
2172 /* Coefficients taken from AMDVLK */
2173 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2174 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2175 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2176
2177 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2178 while(ds_entry->bpp <= ds_bytes_per_pixel)
2179 ++ds_entry;
2180
2181 extent.width = MIN2(extent.width, ds_entry->extent.width);
2182 extent.height = MIN2(extent.height, ds_entry->extent.height);
2183 }
2184
2185 return extent;
2186 }
2187
2188 static void
2189 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2190 struct radv_pipeline *pipeline,
2191 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2192 {
2193 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2194 return;
2195
2196 uint32_t pa_sc_binner_cntl_0 =
2197 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2198 S_028C44_DISABLE_START_OF_PRIM(1);
2199 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2200
2201 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2202
2203 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2204 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2205 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2206
2207 switch (pipeline->device->physical_device->rad_info.family) {
2208 case CHIP_VEGA10:
2209 context_states_per_bin = 1;
2210 persistent_states_per_bin = 1;
2211 fpovs_per_batch = 63;
2212 break;
2213 case CHIP_RAVEN:
2214 context_states_per_bin = 6;
2215 persistent_states_per_bin = 32;
2216 fpovs_per_batch = 63;
2217 break;
2218 default:
2219 unreachable("unhandled family while determining binning state.");
2220 }
2221
2222 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2223 pa_sc_binner_cntl_0 =
2224 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2225 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2226 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2227 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2228 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2229 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2230 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2231 S_028C44_DISABLE_START_OF_PRIM(1) |
2232 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2233 S_028C44_OPTIMAL_BIN_SELECTION(1);
2234 }
2235
2236 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2237 pa_sc_binner_cntl_0);
2238 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2239 db_dfsm_control);
2240 }
2241
2242
2243 static void
2244 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2245 struct radv_pipeline *pipeline,
2246 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2247 const struct radv_graphics_pipeline_create_info *extra)
2248 {
2249 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2250 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2251 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2252 struct radv_render_pass_attachment *attachment = NULL;
2253 uint32_t db_depth_control = 0, db_stencil_control = 0;
2254 uint32_t db_render_control = 0, db_render_override2 = 0;
2255
2256 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2257 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2258
2259 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2260 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2261
2262 if (vkds && has_depth_attachment) {
2263 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2264 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2265 S_028800_ZFUNC(vkds->depthCompareOp) |
2266 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2267
2268 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2269 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2270 }
2271
2272 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2273 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2274 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2275 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2276 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2277 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2278
2279 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2280 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2281 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2282 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2283 }
2284
2285 if (attachment && extra) {
2286 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2287 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2288
2289 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2290 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2291 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2292 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2293 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2294 }
2295
2296 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2297 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2298
2299 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2300 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2301 }
2302
2303 static void
2304 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2305 struct radv_pipeline *pipeline,
2306 const struct radv_blend_state *blend)
2307 {
2308 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2309 radeon_emit_array(cs, blend->cb_blend_control,
2310 8);
2311 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2312 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2313
2314 if (pipeline->device->physical_device->has_rbplus) {
2315
2316 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2317 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2318
2319 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2320 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2321 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2322 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2323 }
2324
2325 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2326
2327 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2328 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2329 }
2330
2331
2332 static void
2333 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2334 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2335 {
2336 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2337
2338 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2339 S_028810_PS_UCP_MODE(3) |
2340 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2341 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2342 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2343 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2344 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2345
2346 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2347 S_0286D4_FLAT_SHADE_ENA(1) |
2348 S_0286D4_PNT_SPRITE_ENA(1) |
2349 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2350 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2351 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2352 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2353 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2354
2355 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2356 S_028BE4_PIX_CENTER(1) | // TODO verify
2357 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2358 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2359
2360 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2361 S_028814_FACE(vkraster->frontFace) |
2362 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2363 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2364 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2365 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2366 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2367 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2368 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2369 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2370 }
2371
2372
2373 static void
2374 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2375 struct radv_pipeline *pipeline)
2376 {
2377 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2378
2379 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2380 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2381 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2382
2383 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2384 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2385
2386 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2387 uint32_t offset;
2388 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2389 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2390 if (loc->sgpr_idx == -1)
2391 return;
2392 assert(loc->num_sgprs == 1);
2393 assert(!loc->indirect);
2394 switch (pipeline->graphics.ms.num_samples) {
2395 default:
2396 offset = 0;
2397 break;
2398 case 2:
2399 offset = 1;
2400 break;
2401 case 4:
2402 offset = 3;
2403 break;
2404 case 8:
2405 offset = 7;
2406 break;
2407 case 16:
2408 offset = 15;
2409 break;
2410 }
2411
2412 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2413 }
2414 }
2415
2416 static void
2417 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2418 const struct radv_pipeline *pipeline)
2419 {
2420 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
2421
2422 uint32_t vgt_primitiveid_en = false;
2423 uint32_t vgt_gs_mode = 0;
2424
2425 if (radv_pipeline_has_gs(pipeline)) {
2426 const struct radv_shader_variant *gs =
2427 pipeline->shaders[MESA_SHADER_GEOMETRY];
2428
2429 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2430 pipeline->device->physical_device->rad_info.chip_class);
2431 } else if (outinfo->export_prim_id) {
2432 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2433 vgt_primitiveid_en = true;
2434 }
2435
2436 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2437 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2438 }
2439
2440 static void
2441 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2442 struct radv_pipeline *pipeline,
2443 struct radv_shader_variant *shader)
2444 {
2445 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2446
2447 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2448 radeon_emit(cs, va >> 8);
2449 radeon_emit(cs, va >> 40);
2450 radeon_emit(cs, shader->rsrc1);
2451 radeon_emit(cs, shader->rsrc2);
2452
2453 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
2454 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2455 clip_dist_mask = outinfo->clip_dist_mask;
2456 cull_dist_mask = outinfo->cull_dist_mask;
2457 total_mask = clip_dist_mask | cull_dist_mask;
2458 bool misc_vec_ena = outinfo->writes_pointsize ||
2459 outinfo->writes_layer ||
2460 outinfo->writes_viewport_index;
2461
2462 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2463 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2464
2465 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2466 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2467 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2468 V_02870C_SPI_SHADER_4COMP :
2469 V_02870C_SPI_SHADER_NONE) |
2470 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2471 V_02870C_SPI_SHADER_4COMP :
2472 V_02870C_SPI_SHADER_NONE) |
2473 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2474 V_02870C_SPI_SHADER_4COMP :
2475 V_02870C_SPI_SHADER_NONE));
2476
2477 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2478 S_028818_VTX_W0_FMT(1) |
2479 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2480 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2481 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2482
2483 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2484 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2485 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2486 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2487 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2488 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2489 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2490 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2491 cull_dist_mask << 8 |
2492 clip_dist_mask);
2493
2494 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2495 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2496 outinfo->writes_viewport_index);
2497 }
2498
2499 static void
2500 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2501 struct radv_pipeline *pipeline,
2502 struct radv_shader_variant *shader)
2503 {
2504 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2505
2506 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2507 radeon_emit(cs, va >> 8);
2508 radeon_emit(cs, va >> 40);
2509 radeon_emit(cs, shader->rsrc1);
2510 radeon_emit(cs, shader->rsrc2);
2511 }
2512
2513 static void
2514 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2515 struct radv_pipeline *pipeline,
2516 struct radv_shader_variant *shader,
2517 const struct radv_tessellation_state *tess)
2518 {
2519 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2520 uint32_t rsrc2 = shader->rsrc2;
2521
2522 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2523 radeon_emit(cs, va >> 8);
2524 radeon_emit(cs, va >> 40);
2525
2526 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2527 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2528 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2529 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2530
2531 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2532 radeon_emit(cs, shader->rsrc1);
2533 radeon_emit(cs, rsrc2);
2534 }
2535
2536 static void
2537 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2538 struct radv_pipeline *pipeline,
2539 struct radv_shader_variant *shader,
2540 const struct radv_tessellation_state *tess)
2541 {
2542 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2543
2544 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2545 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2546 radeon_emit(cs, va >> 8);
2547 radeon_emit(cs, va >> 40);
2548
2549 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2550 radeon_emit(cs, shader->rsrc1);
2551 radeon_emit(cs, shader->rsrc2 |
2552 S_00B42C_LDS_SIZE(tess->lds_size));
2553 } else {
2554 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2555 radeon_emit(cs, va >> 8);
2556 radeon_emit(cs, va >> 40);
2557 radeon_emit(cs, shader->rsrc1);
2558 radeon_emit(cs, shader->rsrc2);
2559 }
2560 }
2561
2562 static void
2563 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2564 struct radv_pipeline *pipeline,
2565 const struct radv_tessellation_state *tess)
2566 {
2567 struct radv_shader_variant *vs;
2568
2569 /* Skip shaders merged into HS/GS */
2570 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2571 if (!vs)
2572 return;
2573
2574 if (vs->info.vs.as_ls)
2575 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2576 else if (vs->info.vs.as_es)
2577 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2578 else
2579 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2580 }
2581
2582 static void
2583 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2584 struct radv_pipeline *pipeline,
2585 const struct radv_tessellation_state *tess)
2586 {
2587 if (!radv_pipeline_has_tess(pipeline))
2588 return;
2589
2590 struct radv_shader_variant *tes, *tcs;
2591
2592 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2593 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2594
2595 if (tes) {
2596 if (tes->info.tes.as_es)
2597 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2598 else
2599 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2600 }
2601
2602 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2603
2604 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2605 tess->tf_param);
2606
2607 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2608 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2609 tess->ls_hs_config);
2610 else
2611 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2612 tess->ls_hs_config);
2613
2614 struct ac_userdata_info *loc;
2615
2616 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
2617 if (loc->sgpr_idx != -1) {
2618 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
2619 assert(loc->num_sgprs == 4);
2620 assert(!loc->indirect);
2621 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
2622 radeon_emit(cs, tess->offchip_layout);
2623 radeon_emit(cs, tess->tcs_out_offsets);
2624 radeon_emit(cs, tess->tcs_out_layout |
2625 tess->num_tcs_input_cp << 26);
2626 radeon_emit(cs, tess->tcs_in_layout);
2627 }
2628
2629 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
2630 if (loc->sgpr_idx != -1) {
2631 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
2632 assert(loc->num_sgprs == 1);
2633 assert(!loc->indirect);
2634
2635 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2636 tess->offchip_layout);
2637 }
2638
2639 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
2640 if (loc->sgpr_idx != -1) {
2641 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
2642 assert(loc->num_sgprs == 1);
2643 assert(!loc->indirect);
2644
2645 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2646 tess->tcs_in_layout);
2647 }
2648 }
2649
2650 static void
2651 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2652 struct radv_pipeline *pipeline,
2653 const struct radv_gs_state *gs_state)
2654 {
2655 struct radv_shader_variant *gs;
2656 uint64_t va;
2657
2658 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2659 if (!gs)
2660 return;
2661
2662 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2663
2664 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2665 radeon_emit(cs, gsvs_itemsize);
2666 radeon_emit(cs, gsvs_itemsize);
2667 radeon_emit(cs, gsvs_itemsize);
2668
2669 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2670
2671 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2672
2673 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2674 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2675 radeon_emit(cs, gs_vert_itemsize >> 2);
2676 radeon_emit(cs, 0);
2677 radeon_emit(cs, 0);
2678 radeon_emit(cs, 0);
2679
2680 uint32_t gs_num_invocations = gs->info.gs.invocations;
2681 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2682 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2683 S_028B90_ENABLE(gs_num_invocations > 0));
2684
2685 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2686 gs_state->vgt_esgs_ring_itemsize);
2687
2688 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2689
2690 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2691 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2692 radeon_emit(cs, va >> 8);
2693 radeon_emit(cs, va >> 40);
2694
2695 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2696 radeon_emit(cs, gs->rsrc1);
2697 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2698
2699 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2700 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2701 } else {
2702 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2703 radeon_emit(cs, va >> 8);
2704 radeon_emit(cs, va >> 40);
2705 radeon_emit(cs, gs->rsrc1);
2706 radeon_emit(cs, gs->rsrc2);
2707 }
2708
2709 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2710
2711 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2712 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
2713 if (loc->sgpr_idx != -1) {
2714 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
2715 uint32_t num_entries = 64;
2716 bool is_vi = pipeline->device->physical_device->rad_info.chip_class >= VI;
2717
2718 if (is_vi)
2719 num_entries *= stride;
2720
2721 stride = S_008F04_STRIDE(stride);
2722 radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
2723 radeon_emit(cs, stride);
2724 radeon_emit(cs, num_entries);
2725 }
2726 }
2727
2728 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2729 {
2730 uint32_t ps_input_cntl;
2731 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2732 ps_input_cntl = S_028644_OFFSET(offset);
2733 if (flat_shade)
2734 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2735 } else {
2736 /* The input is a DEFAULT_VAL constant. */
2737 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2738 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2739 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2740 ps_input_cntl = S_028644_OFFSET(0x20) |
2741 S_028644_DEFAULT_VAL(offset);
2742 }
2743 return ps_input_cntl;
2744 }
2745
2746 static void
2747 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2748 struct radv_pipeline *pipeline)
2749 {
2750 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2751 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
2752 uint32_t ps_input_cntl[32];
2753
2754 unsigned ps_offset = 0;
2755
2756 if (ps->info.fs.prim_id_input) {
2757 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2758 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2759 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2760 ++ps_offset;
2761 }
2762 }
2763
2764 if (ps->info.fs.layer_input) {
2765 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2766 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2767 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2768 else
2769 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2770 ++ps_offset;
2771 }
2772
2773 if (ps->info.fs.has_pcoord) {
2774 unsigned val;
2775 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2776 ps_input_cntl[ps_offset] = val;
2777 ps_offset++;
2778 }
2779
2780 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2781 unsigned vs_offset;
2782 bool flat_shade;
2783 if (!(ps->info.fs.input_mask & (1u << i)))
2784 continue;
2785
2786 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2787 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2788 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2789 ++ps_offset;
2790 continue;
2791 }
2792
2793 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2794
2795 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2796 ++ps_offset;
2797 }
2798
2799 if (ps_offset) {
2800 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2801 for (unsigned i = 0; i < ps_offset; i++) {
2802 radeon_emit(cs, ps_input_cntl[i]);
2803 }
2804 }
2805 }
2806
2807 static uint32_t
2808 radv_compute_db_shader_control(const struct radv_device *device,
2809 const struct radv_shader_variant *ps)
2810 {
2811 unsigned z_order;
2812 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2813 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2814 else
2815 z_order = V_02880C_LATE_Z;
2816
2817 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
2818 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
2819 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2820 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
2821 S_02880C_Z_ORDER(z_order) |
2822 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2823 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2824 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
2825 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
2826 }
2827
2828 static void
2829 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2830 struct radv_pipeline *pipeline)
2831 {
2832 struct radv_shader_variant *ps;
2833 uint64_t va;
2834 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2835
2836 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2837 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2838
2839 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2840 radeon_emit(cs, va >> 8);
2841 radeon_emit(cs, va >> 40);
2842 radeon_emit(cs, ps->rsrc1);
2843 radeon_emit(cs, ps->rsrc2);
2844
2845 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2846 radv_compute_db_shader_control(pipeline->device, ps));
2847
2848 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2849 ps->config.spi_ps_input_ena);
2850
2851 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2852 ps->config.spi_ps_input_addr);
2853
2854 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2855 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2856
2857 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2858
2859 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2860 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
2861 ps->info.info.ps.writes_stencil,
2862 ps->info.info.ps.writes_sample_mask));
2863
2864 if (pipeline->device->dfsm_allowed) {
2865 /* optimise this? */
2866 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2867 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2868 }
2869 }
2870
2871 static void
2872 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2873 struct radv_pipeline *pipeline)
2874 {
2875 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2876 return;
2877
2878 unsigned vtx_reuse_depth = 30;
2879 if (radv_pipeline_has_tess(pipeline) &&
2880 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2881 vtx_reuse_depth = 14;
2882 }
2883 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2884 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2885 }
2886
2887 static uint32_t
2888 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
2889 {
2890 uint32_t stages = 0;
2891 if (radv_pipeline_has_tess(pipeline)) {
2892 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2893 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2894
2895 if (radv_pipeline_has_gs(pipeline))
2896 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2897 S_028B54_GS_EN(1) |
2898 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2899 else
2900 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2901
2902 } else if (radv_pipeline_has_gs(pipeline))
2903 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2904 S_028B54_GS_EN(1) |
2905 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2906
2907 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
2908 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2909
2910 return stages;
2911 }
2912
2913 static uint32_t
2914 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
2915 {
2916 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
2917 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
2918
2919 if (!discard_rectangle_info)
2920 return 0xffff;
2921
2922 unsigned mask = 0;
2923
2924 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
2925 /* Interpret i as a bitmask, and then set the bit in the mask if
2926 * that combination of rectangles in which the pixel is contained
2927 * should pass the cliprect test. */
2928 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
2929
2930 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
2931 !relevant_subset)
2932 continue;
2933
2934 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
2935 relevant_subset)
2936 continue;
2937
2938 mask |= 1u << i;
2939 }
2940
2941 return mask;
2942 }
2943
2944 static void
2945 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2946 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2947 const struct radv_graphics_pipeline_create_info *extra,
2948 const struct radv_blend_state *blend,
2949 const struct radv_tessellation_state *tess,
2950 const struct radv_gs_state *gs,
2951 unsigned prim, unsigned gs_out)
2952 {
2953 pipeline->cs.buf = malloc(4 * 256);
2954 pipeline->cs.max_dw = 256;
2955
2956 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2957 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
2958 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
2959 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2960 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
2961 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
2962 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
2963 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
2964 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2965 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2966 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2967 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2968
2969 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2970 S_0286E8_WAVES(pipeline->max_waves) |
2971 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2972
2973 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
2974
2975 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2976 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
2977 } else {
2978 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
2979 }
2980 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
2981
2982 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
2983
2984 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2985 }
2986
2987 static struct radv_ia_multi_vgt_param_helpers
2988 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
2989 const struct radv_tessellation_state *tess,
2990 uint32_t prim)
2991 {
2992 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
2993 const struct radv_device *device = pipeline->device;
2994
2995 if (radv_pipeline_has_tess(pipeline))
2996 ia_multi_vgt_param.primgroup_size = tess->num_patches;
2997 else if (radv_pipeline_has_gs(pipeline))
2998 ia_multi_vgt_param.primgroup_size = 64;
2999 else
3000 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3001
3002 ia_multi_vgt_param.partial_es_wave = false;
3003 if (pipeline->device->has_distributed_tess) {
3004 if (radv_pipeline_has_gs(pipeline)) {
3005 if (device->physical_device->rad_info.chip_class <= VI)
3006 ia_multi_vgt_param.partial_es_wave = true;
3007 }
3008 }
3009 /* GS requirement. */
3010 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3011 ia_multi_vgt_param.partial_es_wave = true;
3012
3013 ia_multi_vgt_param.wd_switch_on_eop = false;
3014 if (device->physical_device->rad_info.chip_class >= CIK) {
3015 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3016 * 4 shader engines. Set 1 to pass the assertion below.
3017 * The other cases are hardware requirements. */
3018 if (device->physical_device->rad_info.max_se < 4 ||
3019 prim == V_008958_DI_PT_POLYGON ||
3020 prim == V_008958_DI_PT_LINELOOP ||
3021 prim == V_008958_DI_PT_TRIFAN ||
3022 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3023 (pipeline->graphics.prim_restart_enable &&
3024 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3025 (prim != V_008958_DI_PT_POINTLIST &&
3026 prim != V_008958_DI_PT_LINESTRIP &&
3027 prim != V_008958_DI_PT_TRISTRIP))))
3028 ia_multi_vgt_param.wd_switch_on_eop = true;
3029 }
3030
3031 ia_multi_vgt_param.ia_switch_on_eoi = false;
3032 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
3033 ia_multi_vgt_param.ia_switch_on_eoi = true;
3034 if (radv_pipeline_has_gs(pipeline) &&
3035 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3036 ia_multi_vgt_param.ia_switch_on_eoi = true;
3037 if (radv_pipeline_has_tess(pipeline)) {
3038 /* SWITCH_ON_EOI must be set if PrimID is used. */
3039 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3040 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3041 ia_multi_vgt_param.ia_switch_on_eoi = true;
3042 }
3043
3044 ia_multi_vgt_param.partial_vs_wave = false;
3045 if (radv_pipeline_has_tess(pipeline)) {
3046 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3047 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3048 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3049 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3050 radv_pipeline_has_gs(pipeline))
3051 ia_multi_vgt_param.partial_vs_wave = true;
3052 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3053 if (device->has_distributed_tess) {
3054 if (radv_pipeline_has_gs(pipeline)) {
3055 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3056 device->physical_device->rad_info.family == CHIP_FIJI ||
3057 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3058 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3059 device->physical_device->rad_info.family == CHIP_POLARIS12)
3060 ia_multi_vgt_param.partial_vs_wave = true;
3061 } else {
3062 ia_multi_vgt_param.partial_vs_wave = true;
3063 }
3064 }
3065 }
3066
3067 ia_multi_vgt_param.base =
3068 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3069 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3070 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3071 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3072 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3073
3074 return ia_multi_vgt_param;
3075 }
3076
3077
3078 static void
3079 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3080 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3081 {
3082 const VkPipelineVertexInputStateCreateInfo *vi_info =
3083 pCreateInfo->pVertexInputState;
3084 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3085
3086 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3087 const VkVertexInputAttributeDescription *desc =
3088 &vi_info->pVertexAttributeDescriptions[i];
3089 unsigned loc = desc->location;
3090 const struct vk_format_description *format_desc;
3091 int first_non_void;
3092 uint32_t num_format, data_format;
3093 format_desc = vk_format_description(desc->format);
3094 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3095
3096 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3097 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3098
3099 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3100 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3101 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3102 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3103 S_008F0C_NUM_FORMAT(num_format) |
3104 S_008F0C_DATA_FORMAT(data_format);
3105 velems->format_size[loc] = format_desc->block.bits / 8;
3106 velems->offset[loc] = desc->offset;
3107 velems->binding[loc] = desc->binding;
3108 velems->count = MAX2(velems->count, loc + 1);
3109 }
3110
3111 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3112 const VkVertexInputBindingDescription *desc =
3113 &vi_info->pVertexBindingDescriptions[i];
3114
3115 pipeline->binding_stride[desc->binding] = desc->stride;
3116 }
3117 }
3118
3119 static VkResult
3120 radv_pipeline_init(struct radv_pipeline *pipeline,
3121 struct radv_device *device,
3122 struct radv_pipeline_cache *cache,
3123 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3124 const struct radv_graphics_pipeline_create_info *extra,
3125 const VkAllocationCallbacks *alloc)
3126 {
3127 VkResult result;
3128 bool has_view_index = false;
3129
3130 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3131 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3132 if (subpass->view_mask)
3133 has_view_index = true;
3134 if (alloc == NULL)
3135 alloc = &device->alloc;
3136
3137 pipeline->device = device;
3138 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3139 assert(pipeline->layout);
3140
3141 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3142
3143 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3144 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3145 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3146 pStages[stage] = &pCreateInfo->pStages[i];
3147 }
3148
3149 radv_create_shaders(pipeline, device, cache,
3150 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3151 pStages);
3152
3153 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3154 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
3155 uint32_t gs_out;
3156 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3157
3158 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3159
3160 if (radv_pipeline_has_gs(pipeline)) {
3161 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3162 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3163 } else {
3164 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3165 }
3166 if (extra && extra->use_rectlist) {
3167 prim = V_008958_DI_PT_RECTLIST;
3168 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3169 pipeline->graphics.can_use_guardband = true;
3170 }
3171 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3172 /* prim vertex count will need TESS changes */
3173 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3174
3175 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3176
3177 /* Ensure that some export memory is always allocated, for two reasons:
3178 *
3179 * 1) Correctness: The hardware ignores the EXEC mask if no export
3180 * memory is allocated, so KILL and alpha test do not work correctly
3181 * without this.
3182 * 2) Performance: Every shader needs at least a NULL export, even when
3183 * it writes no color/depth output. The NULL export instruction
3184 * stalls without this setting.
3185 *
3186 * Don't add this to CB_SHADER_MASK.
3187 */
3188 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3189 if (!blend.spi_shader_col_format) {
3190 if (!ps->info.info.ps.writes_z &&
3191 !ps->info.info.ps.writes_stencil &&
3192 !ps->info.info.ps.writes_sample_mask)
3193 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3194 }
3195
3196 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3197 if (pipeline->shaders[i]) {
3198 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3199 }
3200 }
3201
3202 struct radv_gs_state gs = {0};
3203 if (radv_pipeline_has_gs(pipeline)) {
3204 gs = calculate_gs_info(pCreateInfo, pipeline);
3205 calculate_gs_ring_sizes(pipeline, &gs);
3206 }
3207
3208 struct radv_tessellation_state tess = {0};
3209 if (radv_pipeline_has_tess(pipeline)) {
3210 if (prim == V_008958_DI_PT_PATCH) {
3211 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3212 pipeline->graphics.prim_vertex_count.incr = 1;
3213 }
3214 tess = calculate_tess_state(pipeline, pCreateInfo);
3215 }
3216
3217 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3218
3219 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3220
3221 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3222 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3223
3224 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3225 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3226 if (loc->sgpr_idx != -1) {
3227 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3228 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3229 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3230 pipeline->graphics.vtx_emit_num = 3;
3231 else
3232 pipeline->graphics.vtx_emit_num = 2;
3233 }
3234
3235 result = radv_pipeline_scratch_init(device, pipeline);
3236 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3237
3238 return result;
3239 }
3240
3241 VkResult
3242 radv_graphics_pipeline_create(
3243 VkDevice _device,
3244 VkPipelineCache _cache,
3245 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3246 const struct radv_graphics_pipeline_create_info *extra,
3247 const VkAllocationCallbacks *pAllocator,
3248 VkPipeline *pPipeline)
3249 {
3250 RADV_FROM_HANDLE(radv_device, device, _device);
3251 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3252 struct radv_pipeline *pipeline;
3253 VkResult result;
3254
3255 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3256 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3257 if (pipeline == NULL)
3258 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3259
3260 result = radv_pipeline_init(pipeline, device, cache,
3261 pCreateInfo, extra, pAllocator);
3262 if (result != VK_SUCCESS) {
3263 radv_pipeline_destroy(device, pipeline, pAllocator);
3264 return result;
3265 }
3266
3267 *pPipeline = radv_pipeline_to_handle(pipeline);
3268
3269 return VK_SUCCESS;
3270 }
3271
3272 VkResult radv_CreateGraphicsPipelines(
3273 VkDevice _device,
3274 VkPipelineCache pipelineCache,
3275 uint32_t count,
3276 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3277 const VkAllocationCallbacks* pAllocator,
3278 VkPipeline* pPipelines)
3279 {
3280 VkResult result = VK_SUCCESS;
3281 unsigned i = 0;
3282
3283 for (; i < count; i++) {
3284 VkResult r;
3285 r = radv_graphics_pipeline_create(_device,
3286 pipelineCache,
3287 &pCreateInfos[i],
3288 NULL, pAllocator, &pPipelines[i]);
3289 if (r != VK_SUCCESS) {
3290 result = r;
3291 pPipelines[i] = VK_NULL_HANDLE;
3292 }
3293 }
3294
3295 return result;
3296 }
3297
3298
3299 static void
3300 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3301 {
3302 struct radv_shader_variant *compute_shader;
3303 struct radv_device *device = pipeline->device;
3304 unsigned compute_resource_limits;
3305 unsigned waves_per_threadgroup;
3306 uint64_t va;
3307
3308 pipeline->cs.buf = malloc(20 * 4);
3309 pipeline->cs.max_dw = 20;
3310
3311 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3312 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3313
3314 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3315 radeon_emit(&pipeline->cs, va >> 8);
3316 radeon_emit(&pipeline->cs, va >> 40);
3317
3318 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3319 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3320 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3321
3322 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3323 S_00B860_WAVES(pipeline->max_waves) |
3324 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3325
3326 /* Calculate best compute resource limits. */
3327 waves_per_threadgroup =
3328 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3329 compute_shader->info.cs.block_size[1] *
3330 compute_shader->info.cs.block_size[2], 64);
3331 compute_resource_limits =
3332 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3333
3334 if (device->physical_device->rad_info.chip_class >= CIK) {
3335 unsigned num_cu_per_se =
3336 device->physical_device->rad_info.num_good_compute_units /
3337 device->physical_device->rad_info.max_se;
3338
3339 /* Force even distribution on all SIMDs in CU if the workgroup
3340 * size is 64. This has shown some good improvements if # of
3341 * CUs per SE is not a multiple of 4.
3342 */
3343 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3344 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3345 }
3346
3347 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3348 compute_resource_limits);
3349
3350 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3351 radeon_emit(&pipeline->cs,
3352 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3353 radeon_emit(&pipeline->cs,
3354 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3355 radeon_emit(&pipeline->cs,
3356 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3357
3358 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3359 }
3360
3361 static VkResult radv_compute_pipeline_create(
3362 VkDevice _device,
3363 VkPipelineCache _cache,
3364 const VkComputePipelineCreateInfo* pCreateInfo,
3365 const VkAllocationCallbacks* pAllocator,
3366 VkPipeline* pPipeline)
3367 {
3368 RADV_FROM_HANDLE(radv_device, device, _device);
3369 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3370 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3371 struct radv_pipeline *pipeline;
3372 VkResult result;
3373
3374 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3375 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3376 if (pipeline == NULL)
3377 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3378
3379 pipeline->device = device;
3380 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3381 assert(pipeline->layout);
3382
3383 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3384 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3385
3386 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3387 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3388 result = radv_pipeline_scratch_init(device, pipeline);
3389 if (result != VK_SUCCESS) {
3390 radv_pipeline_destroy(device, pipeline, pAllocator);
3391 return result;
3392 }
3393
3394 radv_compute_generate_pm4(pipeline);
3395
3396 *pPipeline = radv_pipeline_to_handle(pipeline);
3397
3398 return VK_SUCCESS;
3399 }
3400
3401 VkResult radv_CreateComputePipelines(
3402 VkDevice _device,
3403 VkPipelineCache pipelineCache,
3404 uint32_t count,
3405 const VkComputePipelineCreateInfo* pCreateInfos,
3406 const VkAllocationCallbacks* pAllocator,
3407 VkPipeline* pPipelines)
3408 {
3409 VkResult result = VK_SUCCESS;
3410
3411 unsigned i = 0;
3412 for (; i < count; i++) {
3413 VkResult r;
3414 r = radv_compute_pipeline_create(_device, pipelineCache,
3415 &pCreateInfos[i],
3416 pAllocator, &pPipelines[i]);
3417 if (r != VK_SUCCESS) {
3418 result = r;
3419 pPipelines[i] = VK_NULL_HANDLE;
3420 }
3421 }
3422
3423 return result;
3424 }