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radv: make use of nir_move_out_const_to_consumer()
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 static void
101 radv_pipeline_destroy(struct radv_device *device,
102 struct radv_pipeline *pipeline,
103 const VkAllocationCallbacks* allocator)
104 {
105 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
106 if (pipeline->shaders[i])
107 radv_shader_variant_destroy(device, pipeline->shaders[i]);
108
109 if (pipeline->gs_copy_shader)
110 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
111
112 if(pipeline->cs.buf)
113 free(pipeline->cs.buf);
114 vk_free2(&device->alloc, allocator, pipeline);
115 }
116
117 void radv_DestroyPipeline(
118 VkDevice _device,
119 VkPipeline _pipeline,
120 const VkAllocationCallbacks* pAllocator)
121 {
122 RADV_FROM_HANDLE(radv_device, device, _device);
123 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
124
125 if (!_pipeline)
126 return;
127
128 radv_pipeline_destroy(device, pipeline, pAllocator);
129 }
130
131 static uint32_t get_hash_flags(struct radv_device *device)
132 {
133 uint32_t hash_flags = 0;
134
135 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
136 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
137 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
138 hash_flags |= RADV_HASH_SHADER_SISCHED;
139 return hash_flags;
140 }
141
142 static VkResult
143 radv_pipeline_scratch_init(struct radv_device *device,
144 struct radv_pipeline *pipeline)
145 {
146 unsigned scratch_bytes_per_wave = 0;
147 unsigned max_waves = 0;
148 unsigned min_waves = 1;
149
150 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
151 if (pipeline->shaders[i]) {
152 unsigned max_stage_waves = device->scratch_waves;
153
154 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
155 pipeline->shaders[i]->config.scratch_bytes_per_wave);
156
157 max_stage_waves = MIN2(max_stage_waves,
158 4 * device->physical_device->rad_info.num_good_compute_units *
159 (256 / pipeline->shaders[i]->config.num_vgprs));
160 max_waves = MAX2(max_waves, max_stage_waves);
161 }
162 }
163
164 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
165 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
167 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
168 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
169 }
170
171 if (scratch_bytes_per_wave)
172 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
173
174 if (scratch_bytes_per_wave && max_waves < min_waves) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
178 }
179 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
180 pipeline->max_waves = max_waves;
181 return VK_SUCCESS;
182 }
183
184 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
185 {
186 switch (op) {
187 case VK_LOGIC_OP_CLEAR:
188 return V_028808_ROP3_CLEAR;
189 case VK_LOGIC_OP_AND:
190 return V_028808_ROP3_AND;
191 case VK_LOGIC_OP_AND_REVERSE:
192 return V_028808_ROP3_AND_REVERSE;
193 case VK_LOGIC_OP_COPY:
194 return V_028808_ROP3_COPY;
195 case VK_LOGIC_OP_AND_INVERTED:
196 return V_028808_ROP3_AND_INVERTED;
197 case VK_LOGIC_OP_NO_OP:
198 return V_028808_ROP3_NO_OP;
199 case VK_LOGIC_OP_XOR:
200 return V_028808_ROP3_XOR;
201 case VK_LOGIC_OP_OR:
202 return V_028808_ROP3_OR;
203 case VK_LOGIC_OP_NOR:
204 return V_028808_ROP3_NOR;
205 case VK_LOGIC_OP_EQUIVALENT:
206 return V_028808_ROP3_EQUIVALENT;
207 case VK_LOGIC_OP_INVERT:
208 return V_028808_ROP3_INVERT;
209 case VK_LOGIC_OP_OR_REVERSE:
210 return V_028808_ROP3_OR_REVERSE;
211 case VK_LOGIC_OP_COPY_INVERTED:
212 return V_028808_ROP3_COPY_INVERTED;
213 case VK_LOGIC_OP_OR_INVERTED:
214 return V_028808_ROP3_OR_INVERTED;
215 case VK_LOGIC_OP_NAND:
216 return V_028808_ROP3_NAND;
217 case VK_LOGIC_OP_SET:
218 return V_028808_ROP3_SET;
219 default:
220 unreachable("Unhandled logic op");
221 }
222 }
223
224
225 static uint32_t si_translate_blend_function(VkBlendOp op)
226 {
227 switch (op) {
228 case VK_BLEND_OP_ADD:
229 return V_028780_COMB_DST_PLUS_SRC;
230 case VK_BLEND_OP_SUBTRACT:
231 return V_028780_COMB_SRC_MINUS_DST;
232 case VK_BLEND_OP_REVERSE_SUBTRACT:
233 return V_028780_COMB_DST_MINUS_SRC;
234 case VK_BLEND_OP_MIN:
235 return V_028780_COMB_MIN_DST_SRC;
236 case VK_BLEND_OP_MAX:
237 return V_028780_COMB_MAX_DST_SRC;
238 default:
239 return 0;
240 }
241 }
242
243 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
244 {
245 switch (factor) {
246 case VK_BLEND_FACTOR_ZERO:
247 return V_028780_BLEND_ZERO;
248 case VK_BLEND_FACTOR_ONE:
249 return V_028780_BLEND_ONE;
250 case VK_BLEND_FACTOR_SRC_COLOR:
251 return V_028780_BLEND_SRC_COLOR;
252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
254 case VK_BLEND_FACTOR_DST_COLOR:
255 return V_028780_BLEND_DST_COLOR;
256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
257 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
258 case VK_BLEND_FACTOR_SRC_ALPHA:
259 return V_028780_BLEND_SRC_ALPHA;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
262 case VK_BLEND_FACTOR_DST_ALPHA:
263 return V_028780_BLEND_DST_ALPHA;
264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
266 case VK_BLEND_FACTOR_CONSTANT_COLOR:
267 return V_028780_BLEND_CONSTANT_COLOR;
268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
270 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
271 return V_028780_BLEND_CONSTANT_ALPHA;
272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
275 return V_028780_BLEND_SRC_ALPHA_SATURATE;
276 case VK_BLEND_FACTOR_SRC1_COLOR:
277 return V_028780_BLEND_SRC1_COLOR;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
279 return V_028780_BLEND_INV_SRC1_COLOR;
280 case VK_BLEND_FACTOR_SRC1_ALPHA:
281 return V_028780_BLEND_SRC1_ALPHA;
282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
283 return V_028780_BLEND_INV_SRC1_ALPHA;
284 default:
285 return 0;
286 }
287 }
288
289 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
290 {
291 switch (op) {
292 case VK_BLEND_OP_ADD:
293 return V_028760_OPT_COMB_ADD;
294 case VK_BLEND_OP_SUBTRACT:
295 return V_028760_OPT_COMB_SUBTRACT;
296 case VK_BLEND_OP_REVERSE_SUBTRACT:
297 return V_028760_OPT_COMB_REVSUBTRACT;
298 case VK_BLEND_OP_MIN:
299 return V_028760_OPT_COMB_MIN;
300 case VK_BLEND_OP_MAX:
301 return V_028760_OPT_COMB_MAX;
302 default:
303 return V_028760_OPT_COMB_BLEND_DISABLED;
304 }
305 }
306
307 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
308 {
309 switch (factor) {
310 case VK_BLEND_FACTOR_ZERO:
311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
312 case VK_BLEND_FACTOR_ONE:
313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
314 case VK_BLEND_FACTOR_SRC_COLOR:
315 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
318 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
320 case VK_BLEND_FACTOR_SRC_ALPHA:
321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
327 default:
328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
329 }
330 }
331
332 /**
333 * Get rid of DST in the blend factors by commuting the operands:
334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
335 */
336 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
337 unsigned *dst_factor, unsigned expected_dst,
338 unsigned replacement_src)
339 {
340 if (*src_factor == expected_dst &&
341 *dst_factor == VK_BLEND_FACTOR_ZERO) {
342 *src_factor = VK_BLEND_FACTOR_ZERO;
343 *dst_factor = replacement_src;
344
345 /* Commuting the operands requires reversing subtractions. */
346 if (*func == VK_BLEND_OP_SUBTRACT)
347 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
348 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
349 *func = VK_BLEND_OP_SUBTRACT;
350 }
351 }
352
353 static bool si_blend_factor_uses_dst(unsigned factor)
354 {
355 return factor == VK_BLEND_FACTOR_DST_COLOR ||
356 factor == VK_BLEND_FACTOR_DST_ALPHA ||
357 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
358 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
359 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
360 }
361
362 static bool is_dual_src(VkBlendFactor factor)
363 {
364 switch (factor) {
365 case VK_BLEND_FACTOR_SRC1_COLOR:
366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
367 case VK_BLEND_FACTOR_SRC1_ALPHA:
368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
369 return true;
370 default:
371 return false;
372 }
373 }
374
375 static unsigned si_choose_spi_color_format(VkFormat vk_format,
376 bool blend_enable,
377 bool blend_need_alpha)
378 {
379 const struct vk_format_description *desc = vk_format_description(vk_format);
380 unsigned format, ntype, swap;
381
382 /* Alpha is needed for alpha-to-coverage.
383 * Blending may be with or without alpha.
384 */
385 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
386 unsigned alpha = 0; /* exports alpha, but may not support blending */
387 unsigned blend = 0; /* supports blending, but may not export alpha */
388 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
389
390 format = radv_translate_colorformat(vk_format);
391 ntype = radv_translate_color_numformat(vk_format, desc,
392 vk_format_get_first_non_void_channel(vk_format));
393 swap = radv_translate_colorswap(vk_format, false);
394
395 /* Choose the SPI color formats. These are required values for Stoney/RB+.
396 * Other chips have multiple choices, though they are not necessarily better.
397 */
398 switch (format) {
399 case V_028C70_COLOR_5_6_5:
400 case V_028C70_COLOR_1_5_5_5:
401 case V_028C70_COLOR_5_5_5_1:
402 case V_028C70_COLOR_4_4_4_4:
403 case V_028C70_COLOR_10_11_11:
404 case V_028C70_COLOR_11_11_10:
405 case V_028C70_COLOR_8:
406 case V_028C70_COLOR_8_8:
407 case V_028C70_COLOR_8_8_8_8:
408 case V_028C70_COLOR_10_10_10_2:
409 case V_028C70_COLOR_2_10_10_10:
410 if (ntype == V_028C70_NUMBER_UINT)
411 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
412 else if (ntype == V_028C70_NUMBER_SINT)
413 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
414 else
415 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
416 break;
417
418 case V_028C70_COLOR_16:
419 case V_028C70_COLOR_16_16:
420 case V_028C70_COLOR_16_16_16_16:
421 if (ntype == V_028C70_NUMBER_UNORM ||
422 ntype == V_028C70_NUMBER_SNORM) {
423 /* UNORM16 and SNORM16 don't support blending */
424 if (ntype == V_028C70_NUMBER_UNORM)
425 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
426 else
427 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
428
429 /* Use 32 bits per channel for blending. */
430 if (format == V_028C70_COLOR_16) {
431 if (swap == V_028C70_SWAP_STD) { /* R */
432 blend = V_028714_SPI_SHADER_32_R;
433 blend_alpha = V_028714_SPI_SHADER_32_AR;
434 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
435 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
436 else
437 assert(0);
438 } else if (format == V_028C70_COLOR_16_16) {
439 if (swap == V_028C70_SWAP_STD) { /* RG */
440 blend = V_028714_SPI_SHADER_32_GR;
441 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
442 } else if (swap == V_028C70_SWAP_ALT) /* RA */
443 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
444 else
445 assert(0);
446 } else /* 16_16_16_16 */
447 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
448 } else if (ntype == V_028C70_NUMBER_UINT)
449 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
450 else if (ntype == V_028C70_NUMBER_SINT)
451 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
452 else if (ntype == V_028C70_NUMBER_FLOAT)
453 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
454 else
455 assert(0);
456 break;
457
458 case V_028C70_COLOR_32:
459 if (swap == V_028C70_SWAP_STD) { /* R */
460 blend = normal = V_028714_SPI_SHADER_32_R;
461 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
462 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
463 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
464 else
465 assert(0);
466 break;
467
468 case V_028C70_COLOR_32_32:
469 if (swap == V_028C70_SWAP_STD) { /* RG */
470 blend = normal = V_028714_SPI_SHADER_32_GR;
471 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
472 } else if (swap == V_028C70_SWAP_ALT) /* RA */
473 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
474 else
475 assert(0);
476 break;
477
478 case V_028C70_COLOR_32_32_32_32:
479 case V_028C70_COLOR_8_24:
480 case V_028C70_COLOR_24_8:
481 case V_028C70_COLOR_X24_8_32_FLOAT:
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
483 break;
484
485 default:
486 unreachable("unhandled blend format");
487 }
488
489 if (blend_enable && blend_need_alpha)
490 return blend_alpha;
491 else if(blend_need_alpha)
492 return alpha;
493 else if(blend_enable)
494 return blend;
495 else
496 return normal;
497 }
498
499 static void
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
502 struct radv_blend_state *blend)
503 {
504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
506 unsigned col_format = 0;
507 unsigned num_targets;
508
509 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
510 unsigned cf;
511
512 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
513 cf = V_028714_SPI_SHADER_ZERO;
514 } else {
515 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
516 bool blend_enable =
517 blend->blend_enable_4bit & (0xfu << (i * 4));
518
519 cf = si_choose_spi_color_format(attachment->format,
520 blend_enable,
521 blend->need_src_alpha & (1 << i));
522 }
523
524 col_format |= cf << (4 * i);
525 }
526
527 /* If the i-th target format is set, all previous target formats must
528 * be non-zero to avoid hangs.
529 */
530 num_targets = (util_last_bit(col_format) + 3) / 4;
531 for (unsigned i = 0; i < num_targets; i++) {
532 if (!(col_format & (0xf << (i * 4)))) {
533 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
534 }
535 }
536
537 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
538
539 if (blend->mrt0_is_dual_src)
540 col_format |= (col_format & 0xf) << 4;
541 blend->spi_shader_col_format = col_format;
542 }
543
544 static bool
545 format_is_int8(VkFormat format)
546 {
547 const struct vk_format_description *desc = vk_format_description(format);
548 int channel = vk_format_get_first_non_void_channel(format);
549
550 return channel >= 0 && desc->channel[channel].pure_integer &&
551 desc->channel[channel].size == 8;
552 }
553
554 static bool
555 format_is_int10(VkFormat format)
556 {
557 const struct vk_format_description *desc = vk_format_description(format);
558
559 if (desc->nr_channels != 4)
560 return false;
561 for (unsigned i = 0; i < 4; i++) {
562 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
563 return true;
564 }
565 return false;
566 }
567
568 /*
569 * Ordered so that for each i,
570 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
571 */
572 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
573 VK_FORMAT_R32_SFLOAT,
574 VK_FORMAT_R32G32_SFLOAT,
575 VK_FORMAT_R8G8B8A8_UNORM,
576 VK_FORMAT_R16G16B16A16_UNORM,
577 VK_FORMAT_R16G16B16A16_SNORM,
578 VK_FORMAT_R16G16B16A16_UINT,
579 VK_FORMAT_R16G16B16A16_SINT,
580 VK_FORMAT_R32G32B32A32_SFLOAT,
581 VK_FORMAT_R8G8B8A8_UINT,
582 VK_FORMAT_R8G8B8A8_SINT,
583 VK_FORMAT_A2R10G10B10_UINT_PACK32,
584 VK_FORMAT_A2R10G10B10_SINT_PACK32,
585 };
586
587 unsigned radv_format_meta_fs_key(VkFormat format)
588 {
589 unsigned col_format = si_choose_spi_color_format(format, false, false);
590
591 assert(col_format != V_028714_SPI_SHADER_32_AR);
592 if (col_format >= V_028714_SPI_SHADER_32_AR)
593 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
594
595 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
596 bool is_int8 = format_is_int8(format);
597 bool is_int10 = format_is_int10(format);
598
599 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
600 }
601
602 static void
603 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
604 unsigned *is_int8, unsigned *is_int10)
605 {
606 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
607 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
608 *is_int8 = 0;
609 *is_int10 = 0;
610
611 for (unsigned i = 0; i < subpass->color_count; ++i) {
612 struct radv_render_pass_attachment *attachment;
613
614 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
615 continue;
616
617 attachment = pass->attachments + subpass->color_attachments[i].attachment;
618
619 if (format_is_int8(attachment->format))
620 *is_int8 |= 1 << i;
621 if (format_is_int10(attachment->format))
622 *is_int10 |= 1 << i;
623 }
624 }
625
626 static void
627 radv_blend_check_commutativity(struct radv_blend_state *blend,
628 VkBlendOp op, VkBlendFactor src,
629 VkBlendFactor dst, unsigned chanmask)
630 {
631 /* Src factor is allowed when it does not depend on Dst. */
632 static const uint32_t src_allowed =
633 (1u << VK_BLEND_FACTOR_ONE) |
634 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
635 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
636 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
637 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
638 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
639 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
640 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
641 (1u << VK_BLEND_FACTOR_ZERO) |
642 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
643 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
644 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
645 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
646 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
647 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
648
649 if (dst == VK_BLEND_FACTOR_ONE &&
650 (src_allowed & (1u << src))) {
651 /* Addition is commutative, but floating point addition isn't
652 * associative: subtle changes can be introduced via different
653 * rounding. Be conservative, only enable for min and max.
654 */
655 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
656 blend->commutative_4bit |= chanmask;
657 }
658 }
659
660 static struct radv_blend_state
661 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
662 const VkGraphicsPipelineCreateInfo *pCreateInfo,
663 const struct radv_graphics_pipeline_create_info *extra)
664 {
665 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
666 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
667 struct radv_blend_state blend = {0};
668 unsigned mode = V_028808_CB_NORMAL;
669 int i;
670
671 if (!vkblend)
672 return blend;
673
674 if (extra && extra->custom_blend_mode) {
675 blend.single_cb_enable = true;
676 mode = extra->custom_blend_mode;
677 }
678 blend.cb_color_control = 0;
679 if (vkblend->logicOpEnable)
680 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
681 else
682 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
683
684 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
685 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
686 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
687 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
688
689 if (vkms && vkms->alphaToCoverageEnable) {
690 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
691 }
692
693 blend.cb_target_mask = 0;
694 for (i = 0; i < vkblend->attachmentCount; i++) {
695 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
696 unsigned blend_cntl = 0;
697 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
698 VkBlendOp eqRGB = att->colorBlendOp;
699 VkBlendFactor srcRGB = att->srcColorBlendFactor;
700 VkBlendFactor dstRGB = att->dstColorBlendFactor;
701 VkBlendOp eqA = att->alphaBlendOp;
702 VkBlendFactor srcA = att->srcAlphaBlendFactor;
703 VkBlendFactor dstA = att->dstAlphaBlendFactor;
704
705 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
706
707 if (!att->colorWriteMask)
708 continue;
709
710 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
711 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
712 if (!att->blendEnable) {
713 blend.cb_blend_control[i] = blend_cntl;
714 continue;
715 }
716
717 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
718 if (i == 0)
719 blend.mrt0_is_dual_src = true;
720
721 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
722 srcRGB = VK_BLEND_FACTOR_ONE;
723 dstRGB = VK_BLEND_FACTOR_ONE;
724 }
725 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
726 srcA = VK_BLEND_FACTOR_ONE;
727 dstA = VK_BLEND_FACTOR_ONE;
728 }
729
730 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
731 0x7 << (4 * i));
732 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
733 0x8 << (4 * i));
734
735 /* Blending optimizations for RB+.
736 * These transformations don't change the behavior.
737 *
738 * First, get rid of DST in the blend factors:
739 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
740 */
741 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
742 VK_BLEND_FACTOR_DST_COLOR,
743 VK_BLEND_FACTOR_SRC_COLOR);
744
745 si_blend_remove_dst(&eqA, &srcA, &dstA,
746 VK_BLEND_FACTOR_DST_COLOR,
747 VK_BLEND_FACTOR_SRC_COLOR);
748
749 si_blend_remove_dst(&eqA, &srcA, &dstA,
750 VK_BLEND_FACTOR_DST_ALPHA,
751 VK_BLEND_FACTOR_SRC_ALPHA);
752
753 /* Look up the ideal settings from tables. */
754 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
755 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
756 srcA_opt = si_translate_blend_opt_factor(srcA, true);
757 dstA_opt = si_translate_blend_opt_factor(dstA, true);
758
759 /* Handle interdependencies. */
760 if (si_blend_factor_uses_dst(srcRGB))
761 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
762 if (si_blend_factor_uses_dst(srcA))
763 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
764
765 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
766 (dstRGB == VK_BLEND_FACTOR_ZERO ||
767 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
768 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
769 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
770
771 /* Set the final value. */
772 blend.sx_mrt_blend_opt[i] =
773 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
774 S_028760_COLOR_DST_OPT(dstRGB_opt) |
775 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
776 S_028760_ALPHA_SRC_OPT(srcA_opt) |
777 S_028760_ALPHA_DST_OPT(dstA_opt) |
778 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
779 blend_cntl |= S_028780_ENABLE(1);
780
781 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
782 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
783 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
784 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
785 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
786 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
787 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
788 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
789 }
790 blend.cb_blend_control[i] = blend_cntl;
791
792 blend.blend_enable_4bit |= 0xfu << (i * 4);
793
794 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
795 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
796 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
797 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
798 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
799 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
800 blend.need_src_alpha |= 1 << i;
801 }
802 for (i = vkblend->attachmentCount; i < 8; i++) {
803 blend.cb_blend_control[i] = 0;
804 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
805 }
806
807 if (pipeline->device->physical_device->has_rbplus) {
808 /* Disable RB+ blend optimizations for dual source blending. */
809 if (blend.mrt0_is_dual_src) {
810 for (i = 0; i < 8; i++) {
811 blend.sx_mrt_blend_opt[i] =
812 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
813 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
814 }
815 }
816
817 /* RB+ doesn't work with dual source blending, logic op and
818 * RESOLVE.
819 */
820 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
821 mode == V_028808_CB_RESOLVE)
822 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
823 }
824
825 if (blend.cb_target_mask)
826 blend.cb_color_control |= S_028808_MODE(mode);
827 else
828 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
829
830 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
831 return blend;
832 }
833
834 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
835 {
836 switch (op) {
837 case VK_STENCIL_OP_KEEP:
838 return V_02842C_STENCIL_KEEP;
839 case VK_STENCIL_OP_ZERO:
840 return V_02842C_STENCIL_ZERO;
841 case VK_STENCIL_OP_REPLACE:
842 return V_02842C_STENCIL_REPLACE_TEST;
843 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
844 return V_02842C_STENCIL_ADD_CLAMP;
845 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
846 return V_02842C_STENCIL_SUB_CLAMP;
847 case VK_STENCIL_OP_INVERT:
848 return V_02842C_STENCIL_INVERT;
849 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
850 return V_02842C_STENCIL_ADD_WRAP;
851 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
852 return V_02842C_STENCIL_SUB_WRAP;
853 default:
854 return 0;
855 }
856 }
857
858 static uint32_t si_translate_fill(VkPolygonMode func)
859 {
860 switch(func) {
861 case VK_POLYGON_MODE_FILL:
862 return V_028814_X_DRAW_TRIANGLES;
863 case VK_POLYGON_MODE_LINE:
864 return V_028814_X_DRAW_LINES;
865 case VK_POLYGON_MODE_POINT:
866 return V_028814_X_DRAW_POINTS;
867 default:
868 assert(0);
869 return V_028814_X_DRAW_POINTS;
870 }
871 }
872
873 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
874 {
875 uint32_t num_samples = vkms->rasterizationSamples;
876 uint32_t ps_iter_samples = 1;
877
878 if (vkms->sampleShadingEnable) {
879 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
880 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
881 }
882 return ps_iter_samples;
883 }
884
885 static bool
886 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
887 {
888 return pCreateInfo->depthTestEnable &&
889 pCreateInfo->depthWriteEnable &&
890 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
891 }
892
893 static bool
894 radv_writes_stencil(const VkStencilOpState *state)
895 {
896 return state->writeMask &&
897 (state->failOp != VK_STENCIL_OP_KEEP ||
898 state->passOp != VK_STENCIL_OP_KEEP ||
899 state->depthFailOp != VK_STENCIL_OP_KEEP);
900 }
901
902 static bool
903 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
904 {
905 return pCreateInfo->stencilTestEnable &&
906 (radv_writes_stencil(&pCreateInfo->front) ||
907 radv_writes_stencil(&pCreateInfo->back));
908 }
909
910 static bool
911 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
912 {
913 return radv_is_depth_write_enabled(pCreateInfo) ||
914 radv_is_stencil_write_enabled(pCreateInfo);
915 }
916
917 static bool
918 radv_order_invariant_stencil_op(VkStencilOp op)
919 {
920 /* REPLACE is normally order invariant, except when the stencil
921 * reference value is written by the fragment shader. Tracking this
922 * interaction does not seem worth the effort, so be conservative.
923 */
924 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
925 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
926 op != VK_STENCIL_OP_REPLACE;
927 }
928
929 static bool
930 radv_order_invariant_stencil_state(const VkStencilOpState *state)
931 {
932 /* Compute whether, assuming Z writes are disabled, this stencil state
933 * is order invariant in the sense that the set of passing fragments as
934 * well as the final stencil buffer result does not depend on the order
935 * of fragments.
936 */
937 return !state->writeMask ||
938 /* The following assumes that Z writes are disabled. */
939 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
940 radv_order_invariant_stencil_op(state->passOp) &&
941 radv_order_invariant_stencil_op(state->depthFailOp)) ||
942 (state->compareOp == VK_COMPARE_OP_NEVER &&
943 radv_order_invariant_stencil_op(state->failOp));
944 }
945
946 static bool
947 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
948 struct radv_blend_state *blend,
949 const VkGraphicsPipelineCreateInfo *pCreateInfo)
950 {
951 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
952 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
953 unsigned colormask = blend->cb_target_enabled_4bit;
954
955 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
956 return false;
957
958 /* Be conservative if a logic operation is enabled with color buffers. */
959 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
960 return false;
961
962 /* Default depth/stencil invariance when no attachment is bound. */
963 struct radv_dsa_order_invariance dsa_order_invariant = {
964 .zs = true, .pass_set = true
965 };
966
967 if (pCreateInfo->pDepthStencilState &&
968 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
969 const VkPipelineDepthStencilStateCreateInfo *vkds =
970 pCreateInfo->pDepthStencilState;
971 struct radv_render_pass_attachment *attachment =
972 pass->attachments + subpass->depth_stencil_attachment.attachment;
973 bool has_stencil = vk_format_is_stencil(attachment->format);
974 struct radv_dsa_order_invariance order_invariance[2];
975 struct radv_shader_variant *ps =
976 pipeline->shaders[MESA_SHADER_FRAGMENT];
977
978 /* Compute depth/stencil order invariance in order to know if
979 * it's safe to enable out-of-order.
980 */
981 bool zfunc_is_ordered =
982 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
983 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
984 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
985 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
986 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
987
988 bool nozwrite_and_order_invariant_stencil =
989 !radv_is_ds_write_enabled(vkds) ||
990 (!radv_is_depth_write_enabled(vkds) &&
991 radv_order_invariant_stencil_state(&vkds->front) &&
992 radv_order_invariant_stencil_state(&vkds->back));
993
994 order_invariance[1].zs =
995 nozwrite_and_order_invariant_stencil ||
996 (!radv_is_stencil_write_enabled(vkds) &&
997 zfunc_is_ordered);
998 order_invariance[0].zs =
999 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1000
1001 order_invariance[1].pass_set =
1002 nozwrite_and_order_invariant_stencil ||
1003 (!radv_is_stencil_write_enabled(vkds) &&
1004 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1005 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1006 order_invariance[0].pass_set =
1007 !radv_is_depth_write_enabled(vkds) ||
1008 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1009 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1010
1011 dsa_order_invariant = order_invariance[has_stencil];
1012 if (!dsa_order_invariant.zs)
1013 return false;
1014
1015 /* The set of PS invocations is always order invariant,
1016 * except when early Z/S tests are requested.
1017 */
1018 if (ps &&
1019 ps->info.info.ps.writes_memory &&
1020 ps->info.fs.early_fragment_test &&
1021 !dsa_order_invariant.pass_set)
1022 return false;
1023
1024 /* Determine if out-of-order rasterization should be disabled
1025 * when occlusion queries are used.
1026 */
1027 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1028 !dsa_order_invariant.pass_set;
1029 }
1030
1031 /* No color buffers are enabled for writing. */
1032 if (!colormask)
1033 return true;
1034
1035 unsigned blendmask = colormask & blend->blend_enable_4bit;
1036
1037 if (blendmask) {
1038 /* Only commutative blending. */
1039 if (blendmask & ~blend->commutative_4bit)
1040 return false;
1041
1042 if (!dsa_order_invariant.pass_set)
1043 return false;
1044 }
1045
1046 if (colormask & ~blendmask)
1047 return false;
1048
1049 return true;
1050 }
1051
1052 static void
1053 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1054 struct radv_blend_state *blend,
1055 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1056 {
1057 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1058 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1059 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1060 bool out_of_order_rast = false;
1061 int ps_iter_samples = 1;
1062 uint32_t mask = 0xffff;
1063
1064 if (vkms)
1065 ms->num_samples = vkms->rasterizationSamples;
1066 else
1067 ms->num_samples = 1;
1068
1069 if (vkms)
1070 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1071 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1072 ps_iter_samples = ms->num_samples;
1073 }
1074
1075 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1076 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1077 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1078 /* Out-of-order rasterization is explicitly enabled by the
1079 * application.
1080 */
1081 out_of_order_rast = true;
1082 } else {
1083 /* Determine if the driver can enable out-of-order
1084 * rasterization internally.
1085 */
1086 out_of_order_rast =
1087 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1088 }
1089
1090 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1091 ms->pa_sc_aa_config = 0;
1092 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1093 S_028804_INCOHERENT_EQAA_READS(1) |
1094 S_028804_INTERPOLATE_COMP_Z(1) |
1095 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1096 ms->pa_sc_mode_cntl_1 =
1097 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1098 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1099 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1100 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1101 /* always 1: */
1102 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1103 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1104 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1105 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1106 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1107 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1108 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1109 S_028A48_VPORT_SCISSOR_ENABLE(1);
1110
1111 if (ms->num_samples > 1) {
1112 unsigned log_samples = util_logbase2(ms->num_samples);
1113 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1114 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1115 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1116 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1117 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1118 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1119 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1120 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1121 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1122 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1123 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1124 if (ps_iter_samples > 1)
1125 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1126 }
1127
1128 if (vkms && vkms->pSampleMask) {
1129 mask = vkms->pSampleMask[0] & 0xffff;
1130 }
1131
1132 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1133 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1134 }
1135
1136 static bool
1137 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1138 {
1139 switch (topology) {
1140 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1141 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1142 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1143 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1144 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1145 return false;
1146 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1147 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1148 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1149 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1150 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1151 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1152 return true;
1153 default:
1154 unreachable("unhandled primitive type");
1155 }
1156 }
1157
1158 static uint32_t
1159 si_translate_prim(enum VkPrimitiveTopology topology)
1160 {
1161 switch (topology) {
1162 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1163 return V_008958_DI_PT_POINTLIST;
1164 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1165 return V_008958_DI_PT_LINELIST;
1166 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1167 return V_008958_DI_PT_LINESTRIP;
1168 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1169 return V_008958_DI_PT_TRILIST;
1170 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1171 return V_008958_DI_PT_TRISTRIP;
1172 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1173 return V_008958_DI_PT_TRIFAN;
1174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1175 return V_008958_DI_PT_LINELIST_ADJ;
1176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1177 return V_008958_DI_PT_LINESTRIP_ADJ;
1178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1179 return V_008958_DI_PT_TRILIST_ADJ;
1180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1181 return V_008958_DI_PT_TRISTRIP_ADJ;
1182 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1183 return V_008958_DI_PT_PATCH;
1184 default:
1185 assert(0);
1186 return 0;
1187 }
1188 }
1189
1190 static uint32_t
1191 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1192 {
1193 switch (gl_prim) {
1194 case 0: /* GL_POINTS */
1195 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1196 case 1: /* GL_LINES */
1197 case 3: /* GL_LINE_STRIP */
1198 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1199 case 0x8E7A: /* GL_ISOLINES */
1200 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1201
1202 case 4: /* GL_TRIANGLES */
1203 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1204 case 5: /* GL_TRIANGLE_STRIP */
1205 case 7: /* GL_QUADS */
1206 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1207 default:
1208 assert(0);
1209 return 0;
1210 }
1211 }
1212
1213 static uint32_t
1214 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1215 {
1216 switch (topology) {
1217 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1218 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1219 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1221 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1222 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1223 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1224 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1225 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1228 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1230 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1231 default:
1232 assert(0);
1233 return 0;
1234 }
1235 }
1236
1237 static unsigned si_map_swizzle(unsigned swizzle)
1238 {
1239 switch (swizzle) {
1240 case VK_SWIZZLE_Y:
1241 return V_008F0C_SQ_SEL_Y;
1242 case VK_SWIZZLE_Z:
1243 return V_008F0C_SQ_SEL_Z;
1244 case VK_SWIZZLE_W:
1245 return V_008F0C_SQ_SEL_W;
1246 case VK_SWIZZLE_0:
1247 return V_008F0C_SQ_SEL_0;
1248 case VK_SWIZZLE_1:
1249 return V_008F0C_SQ_SEL_1;
1250 default: /* VK_SWIZZLE_X */
1251 return V_008F0C_SQ_SEL_X;
1252 }
1253 }
1254
1255
1256 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1257 {
1258 switch(state) {
1259 case VK_DYNAMIC_STATE_VIEWPORT:
1260 return RADV_DYNAMIC_VIEWPORT;
1261 case VK_DYNAMIC_STATE_SCISSOR:
1262 return RADV_DYNAMIC_SCISSOR;
1263 case VK_DYNAMIC_STATE_LINE_WIDTH:
1264 return RADV_DYNAMIC_LINE_WIDTH;
1265 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1266 return RADV_DYNAMIC_DEPTH_BIAS;
1267 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1268 return RADV_DYNAMIC_BLEND_CONSTANTS;
1269 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1270 return RADV_DYNAMIC_DEPTH_BOUNDS;
1271 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1272 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1273 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1274 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1275 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1276 return RADV_DYNAMIC_STENCIL_REFERENCE;
1277 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1278 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1279 default:
1280 unreachable("Unhandled dynamic state");
1281 }
1282 }
1283
1284 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1285 {
1286 uint32_t states = RADV_DYNAMIC_ALL;
1287
1288 /* If rasterization is disabled we do not care about any of the dynamic states,
1289 * since they are all rasterization related only. */
1290 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1291 return 0;
1292
1293 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1294 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1295
1296 if (!pCreateInfo->pDepthStencilState ||
1297 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1298 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1299
1300 if (!pCreateInfo->pDepthStencilState ||
1301 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1302 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1303 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1304 RADV_DYNAMIC_STENCIL_REFERENCE);
1305
1306 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1307 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1308
1309 /* TODO: blend constants & line width. */
1310
1311 return states;
1312 }
1313
1314
1315 static void
1316 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1317 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1318 {
1319 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1320 uint32_t states = needed_states;
1321 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1322 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1323
1324 pipeline->dynamic_state = default_dynamic_state;
1325 pipeline->graphics.needed_dynamic_state = needed_states;
1326
1327 if (pCreateInfo->pDynamicState) {
1328 /* Remove all of the states that are marked as dynamic */
1329 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1330 for (uint32_t s = 0; s < count; s++)
1331 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1332 }
1333
1334 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1335
1336 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1337 assert(pCreateInfo->pViewportState);
1338
1339 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1340 if (states & RADV_DYNAMIC_VIEWPORT) {
1341 typed_memcpy(dynamic->viewport.viewports,
1342 pCreateInfo->pViewportState->pViewports,
1343 pCreateInfo->pViewportState->viewportCount);
1344 }
1345 }
1346
1347 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1348 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1349 if (states & RADV_DYNAMIC_SCISSOR) {
1350 typed_memcpy(dynamic->scissor.scissors,
1351 pCreateInfo->pViewportState->pScissors,
1352 pCreateInfo->pViewportState->scissorCount);
1353 }
1354 }
1355
1356 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1357 assert(pCreateInfo->pRasterizationState);
1358 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1359 }
1360
1361 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1362 assert(pCreateInfo->pRasterizationState);
1363 dynamic->depth_bias.bias =
1364 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1365 dynamic->depth_bias.clamp =
1366 pCreateInfo->pRasterizationState->depthBiasClamp;
1367 dynamic->depth_bias.slope =
1368 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1369 }
1370
1371 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1372 *
1373 * pColorBlendState is [...] NULL if the pipeline has rasterization
1374 * disabled or if the subpass of the render pass the pipeline is
1375 * created against does not use any color attachments.
1376 */
1377 bool uses_color_att = false;
1378 for (unsigned i = 0; i < subpass->color_count; ++i) {
1379 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1380 uses_color_att = true;
1381 break;
1382 }
1383 }
1384
1385 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1386 assert(pCreateInfo->pColorBlendState);
1387 typed_memcpy(dynamic->blend_constants,
1388 pCreateInfo->pColorBlendState->blendConstants, 4);
1389 }
1390
1391 /* If there is no depthstencil attachment, then don't read
1392 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1393 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1394 * no need to override the depthstencil defaults in
1395 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1396 *
1397 * Section 9.2 of the Vulkan 1.0.15 spec says:
1398 *
1399 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1400 * disabled or if the subpass of the render pass the pipeline is created
1401 * against does not use a depth/stencil attachment.
1402 */
1403 if (needed_states &&
1404 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1405 assert(pCreateInfo->pDepthStencilState);
1406
1407 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1408 dynamic->depth_bounds.min =
1409 pCreateInfo->pDepthStencilState->minDepthBounds;
1410 dynamic->depth_bounds.max =
1411 pCreateInfo->pDepthStencilState->maxDepthBounds;
1412 }
1413
1414 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1415 dynamic->stencil_compare_mask.front =
1416 pCreateInfo->pDepthStencilState->front.compareMask;
1417 dynamic->stencil_compare_mask.back =
1418 pCreateInfo->pDepthStencilState->back.compareMask;
1419 }
1420
1421 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1422 dynamic->stencil_write_mask.front =
1423 pCreateInfo->pDepthStencilState->front.writeMask;
1424 dynamic->stencil_write_mask.back =
1425 pCreateInfo->pDepthStencilState->back.writeMask;
1426 }
1427
1428 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1429 dynamic->stencil_reference.front =
1430 pCreateInfo->pDepthStencilState->front.reference;
1431 dynamic->stencil_reference.back =
1432 pCreateInfo->pDepthStencilState->back.reference;
1433 }
1434 }
1435
1436 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1437 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1438 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1439 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1440 typed_memcpy(dynamic->discard_rectangle.rectangles,
1441 discard_rectangle_info->pDiscardRectangles,
1442 discard_rectangle_info->discardRectangleCount);
1443 }
1444
1445 pipeline->dynamic_state.mask = states;
1446 }
1447
1448 static struct radv_gs_state
1449 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1450 const struct radv_pipeline *pipeline)
1451 {
1452 struct radv_gs_state gs = {0};
1453 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1454 struct radv_es_output_info *es_info;
1455 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1456 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1457 else
1458 es_info = radv_pipeline_has_tess(pipeline) ?
1459 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1460 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1461
1462 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1463 bool uses_adjacency;
1464 switch(pCreateInfo->pInputAssemblyState->topology) {
1465 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1466 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1467 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1468 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1469 uses_adjacency = true;
1470 break;
1471 default:
1472 uses_adjacency = false;
1473 break;
1474 }
1475
1476 /* All these are in dwords: */
1477 /* We can't allow using the whole LDS, because GS waves compete with
1478 * other shader stages for LDS space. */
1479 const unsigned max_lds_size = 8 * 1024;
1480 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1481 unsigned esgs_lds_size;
1482
1483 /* All these are per subgroup: */
1484 const unsigned max_out_prims = 32 * 1024;
1485 const unsigned max_es_verts = 255;
1486 const unsigned ideal_gs_prims = 64;
1487 unsigned max_gs_prims, gs_prims;
1488 unsigned min_es_verts, es_verts, worst_case_es_verts;
1489
1490 if (uses_adjacency || gs_num_invocations > 1)
1491 max_gs_prims = 127 / gs_num_invocations;
1492 else
1493 max_gs_prims = 255;
1494
1495 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1496 * Make sure we don't go over the maximum value.
1497 */
1498 if (gs_info->gs.vertices_out > 0) {
1499 max_gs_prims = MIN2(max_gs_prims,
1500 max_out_prims /
1501 (gs_info->gs.vertices_out * gs_num_invocations));
1502 }
1503 assert(max_gs_prims > 0);
1504
1505 /* If the primitive has adjacency, halve the number of vertices
1506 * that will be reused in multiple primitives.
1507 */
1508 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1509
1510 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1511 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1512
1513 /* Compute ESGS LDS size based on the worst case number of ES vertices
1514 * needed to create the target number of GS prims per subgroup.
1515 */
1516 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1517
1518 /* If total LDS usage is too big, refactor partitions based on ratio
1519 * of ESGS item sizes.
1520 */
1521 if (esgs_lds_size > max_lds_size) {
1522 /* Our target GS Prims Per Subgroup was too large. Calculate
1523 * the maximum number of GS Prims Per Subgroup that will fit
1524 * into LDS, capped by the maximum that the hardware can support.
1525 */
1526 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1527 max_gs_prims);
1528 assert(gs_prims > 0);
1529 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1530 max_es_verts);
1531
1532 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1533 assert(esgs_lds_size <= max_lds_size);
1534 }
1535
1536 /* Now calculate remaining ESGS information. */
1537 if (esgs_lds_size)
1538 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1539 else
1540 es_verts = max_es_verts;
1541
1542 /* Vertices for adjacency primitives are not always reused, so restore
1543 * it for ES_VERTS_PER_SUBGRP.
1544 */
1545 min_es_verts = gs_info->gs.vertices_in;
1546
1547 /* For normal primitives, the VGT only checks if they are past the ES
1548 * verts per subgroup after allocating a full GS primitive and if they
1549 * are, kick off a new subgroup. But if those additional ES verts are
1550 * unique (e.g. not reused) we need to make sure there is enough LDS
1551 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1552 */
1553 es_verts -= min_es_verts - 1;
1554
1555 uint32_t es_verts_per_subgroup = es_verts;
1556 uint32_t gs_prims_per_subgroup = gs_prims;
1557 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1558 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1559 gs.lds_size = align(esgs_lds_size, 128) / 128;
1560 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1561 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1562 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1563 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1564 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1565 assert(max_prims_per_subgroup <= max_out_prims);
1566
1567 return gs;
1568 }
1569
1570 static void
1571 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1572 {
1573 struct radv_device *device = pipeline->device;
1574 unsigned num_se = device->physical_device->rad_info.max_se;
1575 unsigned wave_size = 64;
1576 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1577 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
1578 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1579 */
1580 unsigned gs_vertex_reuse =
1581 (device->physical_device->rad_info.chip_class >= VI ? 32 : 16) * num_se;
1582 unsigned alignment = 256 * num_se;
1583 /* The maximum size is 63.999 MB per SE. */
1584 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1585 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1586
1587 /* Calculate the minimum size. */
1588 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1589 wave_size, alignment);
1590 /* These are recommended sizes, not minimum sizes. */
1591 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1592 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1593 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1594 gs_info->gs.max_gsvs_emit_size;
1595
1596 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1597 esgs_ring_size = align(esgs_ring_size, alignment);
1598 gsvs_ring_size = align(gsvs_ring_size, alignment);
1599
1600 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1601 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1602
1603 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1604 }
1605
1606 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1607 unsigned *lds_size)
1608 {
1609 /* If tessellation is all offchip and on-chip GS isn't used, this
1610 * workaround is not needed.
1611 */
1612 return;
1613
1614 /* SPI barrier management bug:
1615 * Make sure we have at least 4k of LDS in use to avoid the bug.
1616 * It applies to workgroup sizes of more than one wavefront.
1617 */
1618 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1619 device->physical_device->rad_info.family == CHIP_KABINI ||
1620 device->physical_device->rad_info.family == CHIP_MULLINS)
1621 *lds_size = MAX2(*lds_size, 8);
1622 }
1623
1624 struct radv_shader_variant *
1625 radv_get_shader(struct radv_pipeline *pipeline,
1626 gl_shader_stage stage)
1627 {
1628 if (stage == MESA_SHADER_VERTEX) {
1629 if (pipeline->shaders[MESA_SHADER_VERTEX])
1630 return pipeline->shaders[MESA_SHADER_VERTEX];
1631 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1632 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1633 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1634 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1635 } else if (stage == MESA_SHADER_TESS_EVAL) {
1636 if (!radv_pipeline_has_tess(pipeline))
1637 return NULL;
1638 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1639 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1640 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1641 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1642 }
1643 return pipeline->shaders[stage];
1644 }
1645
1646 static struct radv_tessellation_state
1647 calculate_tess_state(struct radv_pipeline *pipeline,
1648 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1649 {
1650 unsigned num_tcs_input_cp;
1651 unsigned num_tcs_output_cp;
1652 unsigned lds_size;
1653 unsigned num_patches;
1654 struct radv_tessellation_state tess = {0};
1655
1656 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1657 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1658 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1659
1660 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1661
1662 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1663 assert(lds_size <= 65536);
1664 lds_size = align(lds_size, 512) / 512;
1665 } else {
1666 assert(lds_size <= 32768);
1667 lds_size = align(lds_size, 256) / 256;
1668 }
1669 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1670
1671 tess.lds_size = lds_size;
1672
1673 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1674 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1675 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1676 tess.num_patches = num_patches;
1677
1678 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1679 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1680
1681 switch (tes->info.tes.primitive_mode) {
1682 case GL_TRIANGLES:
1683 type = V_028B6C_TESS_TRIANGLE;
1684 break;
1685 case GL_QUADS:
1686 type = V_028B6C_TESS_QUAD;
1687 break;
1688 case GL_ISOLINES:
1689 type = V_028B6C_TESS_ISOLINE;
1690 break;
1691 }
1692
1693 switch (tes->info.tes.spacing) {
1694 case TESS_SPACING_EQUAL:
1695 partitioning = V_028B6C_PART_INTEGER;
1696 break;
1697 case TESS_SPACING_FRACTIONAL_ODD:
1698 partitioning = V_028B6C_PART_FRAC_ODD;
1699 break;
1700 case TESS_SPACING_FRACTIONAL_EVEN:
1701 partitioning = V_028B6C_PART_FRAC_EVEN;
1702 break;
1703 default:
1704 break;
1705 }
1706
1707 bool ccw = tes->info.tes.ccw;
1708 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1709 vk_find_struct_const(pCreateInfo->pTessellationState,
1710 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1711
1712 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1713 ccw = !ccw;
1714
1715 if (tes->info.tes.point_mode)
1716 topology = V_028B6C_OUTPUT_POINT;
1717 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1718 topology = V_028B6C_OUTPUT_LINE;
1719 else if (ccw)
1720 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1721 else
1722 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1723
1724 if (pipeline->device->has_distributed_tess) {
1725 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1726 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1727 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1728 else
1729 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1730 } else
1731 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1732
1733 tess.tf_param = S_028B6C_TYPE(type) |
1734 S_028B6C_PARTITIONING(partitioning) |
1735 S_028B6C_TOPOLOGY(topology) |
1736 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1737
1738 return tess;
1739 }
1740
1741 static const struct radv_prim_vertex_count prim_size_table[] = {
1742 [V_008958_DI_PT_NONE] = {0, 0},
1743 [V_008958_DI_PT_POINTLIST] = {1, 1},
1744 [V_008958_DI_PT_LINELIST] = {2, 2},
1745 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1746 [V_008958_DI_PT_TRILIST] = {3, 3},
1747 [V_008958_DI_PT_TRIFAN] = {3, 1},
1748 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1749 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1750 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1751 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1752 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1753 [V_008958_DI_PT_RECTLIST] = {3, 3},
1754 [V_008958_DI_PT_LINELOOP] = {2, 1},
1755 [V_008958_DI_PT_POLYGON] = {3, 1},
1756 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1757 };
1758
1759 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1760 {
1761 if (radv_pipeline_has_gs(pipeline))
1762 return &pipeline->gs_copy_shader->info.vs.outinfo;
1763 else if (radv_pipeline_has_tess(pipeline))
1764 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1765 else
1766 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1767 }
1768
1769 static void
1770 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1771 {
1772 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1773 int shader_count = 0;
1774
1775 if(shaders[MESA_SHADER_FRAGMENT]) {
1776 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1777 }
1778 if(shaders[MESA_SHADER_GEOMETRY]) {
1779 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1780 }
1781 if(shaders[MESA_SHADER_TESS_EVAL]) {
1782 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1783 }
1784 if(shaders[MESA_SHADER_TESS_CTRL]) {
1785 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1786 }
1787 if(shaders[MESA_SHADER_VERTEX]) {
1788 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1789 }
1790
1791 if (shader_count > 1) {
1792 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
1793 unsigned last = ordered_shaders[0]->info.stage;
1794
1795 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
1796 ordered_shaders[1]->info.has_transform_feedback_varyings)
1797 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
1798
1799 for (int i = 0; i < shader_count; ++i) {
1800 nir_variable_mode mask = 0;
1801
1802 if (ordered_shaders[i]->info.stage != first)
1803 mask = mask | nir_var_shader_in;
1804
1805 if (ordered_shaders[i]->info.stage != last)
1806 mask = mask | nir_var_shader_out;
1807
1808 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
1809 radv_optimize_nir(ordered_shaders[i], false, false);
1810 }
1811 }
1812
1813 for (int i = 1; i < shader_count; ++i) {
1814 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1815 ordered_shaders[i - 1]);
1816
1817 if (nir_link_constant_varyings(ordered_shaders[i],
1818 ordered_shaders[i - 1]))
1819 radv_optimize_nir(ordered_shaders[i - 1], false, false);
1820
1821 nir_remove_dead_variables(ordered_shaders[i],
1822 nir_var_shader_out);
1823 nir_remove_dead_variables(ordered_shaders[i - 1],
1824 nir_var_shader_in);
1825
1826 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1827 ordered_shaders[i - 1]);
1828
1829 nir_compact_varyings(ordered_shaders[i],
1830 ordered_shaders[i - 1], true);
1831
1832 if (progress) {
1833 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1834 ac_lower_indirect_derefs(ordered_shaders[i],
1835 pipeline->device->physical_device->rad_info.chip_class);
1836 }
1837 radv_optimize_nir(ordered_shaders[i], false, false);
1838
1839 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1840 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1841 pipeline->device->physical_device->rad_info.chip_class);
1842 }
1843 radv_optimize_nir(ordered_shaders[i - 1], false, false);
1844 }
1845 }
1846 }
1847
1848
1849 static struct radv_pipeline_key
1850 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1851 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1852 const struct radv_blend_state *blend,
1853 bool has_view_index)
1854 {
1855 const VkPipelineVertexInputStateCreateInfo *input_state =
1856 pCreateInfo->pVertexInputState;
1857 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
1858 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1859
1860 struct radv_pipeline_key key;
1861 memset(&key, 0, sizeof(key));
1862
1863 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
1864 key.optimisations_disabled = 1;
1865
1866 key.has_multiview_view_index = has_view_index;
1867
1868 uint32_t binding_input_rate = 0;
1869 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
1870 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1871 if (input_state->pVertexBindingDescriptions[i].inputRate) {
1872 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
1873 binding_input_rate |= 1u << binding;
1874 instance_rate_divisors[binding] = 1;
1875 }
1876 }
1877 if (divisor_state) {
1878 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
1879 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
1880 divisor_state->pVertexBindingDivisors[i].divisor;
1881 }
1882 }
1883
1884 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1885 unsigned location = input_state->pVertexAttributeDescriptions[i].location;
1886 unsigned binding = input_state->pVertexAttributeDescriptions[i].binding;
1887 if (binding_input_rate & (1u << binding)) {
1888 key.instance_rate_inputs |= 1u << location;
1889 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
1890 }
1891
1892 if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
1893 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
1894 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
1895 uint64_t adjust;
1896 switch(format) {
1897 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
1898 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
1899 adjust = RADV_ALPHA_ADJUST_SNORM;
1900 break;
1901 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
1902 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
1903 adjust = RADV_ALPHA_ADJUST_SSCALED;
1904 break;
1905 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
1906 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
1907 adjust = RADV_ALPHA_ADJUST_SINT;
1908 break;
1909 default:
1910 adjust = 0;
1911 break;
1912 }
1913 key.vertex_alpha_adjust |= adjust << (2 * location);
1914 }
1915 }
1916
1917 if (pCreateInfo->pTessellationState)
1918 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1919
1920
1921 if (pCreateInfo->pMultisampleState &&
1922 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1923 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1924 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1925 key.num_samples = num_samples;
1926 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1927 }
1928
1929 key.col_format = blend->spi_shader_col_format;
1930 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1931 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1932
1933 return key;
1934 }
1935
1936 static void
1937 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1938 const struct radv_pipeline_key *key,
1939 nir_shader **nir)
1940 {
1941 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1942 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
1943 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
1944 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
1945
1946 if (nir[MESA_SHADER_TESS_CTRL]) {
1947 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1948 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1949 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1950 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1951
1952 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1953 }
1954
1955 if (nir[MESA_SHADER_GEOMETRY]) {
1956 if (nir[MESA_SHADER_TESS_CTRL])
1957 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1958 else
1959 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1960 }
1961
1962 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1963 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1964
1965 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1966 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1967 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1968 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1969 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
1970 }
1971
1972 static void
1973 merge_tess_info(struct shader_info *tes_info,
1974 const struct shader_info *tcs_info)
1975 {
1976 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1977 *
1978 * "PointMode. Controls generation of points rather than triangles
1979 * or lines. This functionality defaults to disabled, and is
1980 * enabled if either shader stage includes the execution mode.
1981 *
1982 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1983 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1984 * and OutputVertices, it says:
1985 *
1986 * "One mode must be set in at least one of the tessellation
1987 * shader stages."
1988 *
1989 * So, the fields can be set in either the TCS or TES, but they must
1990 * agree if set in both. Our backend looks at TES, so bitwise-or in
1991 * the values from the TCS.
1992 */
1993 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1994 tes_info->tess.tcs_vertices_out == 0 ||
1995 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1996 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1997
1998 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1999 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2000 tcs_info->tess.spacing == tes_info->tess.spacing);
2001 tes_info->tess.spacing |= tcs_info->tess.spacing;
2002
2003 assert(tcs_info->tess.primitive_mode == 0 ||
2004 tes_info->tess.primitive_mode == 0 ||
2005 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2006 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2007 tes_info->tess.ccw |= tcs_info->tess.ccw;
2008 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2009 }
2010
2011 static
2012 void radv_create_shaders(struct radv_pipeline *pipeline,
2013 struct radv_device *device,
2014 struct radv_pipeline_cache *cache,
2015 const struct radv_pipeline_key *key,
2016 const VkPipelineShaderStageCreateInfo **pStages,
2017 const VkPipelineCreateFlags flags)
2018 {
2019 struct radv_shader_module fs_m = {0};
2020 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2021 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2022 void *codes[MESA_SHADER_STAGES] = {0};
2023 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
2024 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
2025 unsigned char hash[20], gs_copy_hash[20];
2026
2027 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2028 if (pStages[i]) {
2029 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2030 if (modules[i]->nir)
2031 _mesa_sha1_compute(modules[i]->nir->info.name,
2032 strlen(modules[i]->nir->info.name),
2033 modules[i]->sha1);
2034
2035 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2036 }
2037 }
2038
2039 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2040 memcpy(gs_copy_hash, hash, 20);
2041 gs_copy_hash[0] ^= 1;
2042
2043 if (modules[MESA_SHADER_GEOMETRY]) {
2044 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2045 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
2046 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2047 }
2048
2049 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
2050 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2051 return;
2052 }
2053
2054 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2055 nir_builder fs_b;
2056 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2057 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2058 fs_m.nir = fs_b.shader;
2059 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2060 }
2061
2062 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2063 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2064
2065 if (!modules[i])
2066 continue;
2067
2068 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2069 stage ? stage->pName : "main", i,
2070 stage ? stage->pSpecializationInfo : NULL,
2071 flags);
2072
2073 /* We don't want to alter meta shaders IR directly so clone it
2074 * first.
2075 */
2076 if (nir[i]->info.name) {
2077 nir[i] = nir_shader_clone(NULL, nir[i]);
2078 }
2079 }
2080
2081 if (nir[MESA_SHADER_TESS_CTRL]) {
2082 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2083 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2084 }
2085
2086 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2087 radv_link_shaders(pipeline, nir);
2088
2089 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2090 if (radv_can_dump_shader(device, modules[i], false))
2091 nir_print_shader(nir[i], stderr);
2092 }
2093
2094 radv_fill_shader_keys(keys, key, nir);
2095
2096 if (nir[MESA_SHADER_FRAGMENT]) {
2097 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2098 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2099 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2100 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2101 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
2102 }
2103
2104 /* TODO: These are no longer used as keys we should refactor this */
2105 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
2106 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2107 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
2108 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2109 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
2110 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2111 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
2112 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2113 }
2114
2115 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2116 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2117 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2118 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2119 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2120 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2121 pipeline->layout,
2122 &key, &codes[MESA_SHADER_TESS_CTRL],
2123 &code_sizes[MESA_SHADER_TESS_CTRL]);
2124 }
2125 modules[MESA_SHADER_VERTEX] = NULL;
2126 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2127 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2128 }
2129
2130 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2131 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2132 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2133 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2134 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2135 pipeline->layout,
2136 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
2137 &code_sizes[MESA_SHADER_GEOMETRY]);
2138 }
2139 modules[pre_stage] = NULL;
2140 }
2141
2142 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2143 if(modules[i] && !pipeline->shaders[i]) {
2144 if (i == MESA_SHADER_TESS_CTRL) {
2145 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2146 }
2147 if (i == MESA_SHADER_TESS_EVAL) {
2148 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2149 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2150 }
2151 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2152 pipeline->layout,
2153 keys + i, &codes[i],
2154 &code_sizes[i]);
2155 }
2156 }
2157
2158 if(modules[MESA_SHADER_GEOMETRY]) {
2159 void *gs_copy_code = NULL;
2160 unsigned gs_copy_code_size = 0;
2161 if (!pipeline->gs_copy_shader) {
2162 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2163 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2164 &gs_copy_code_size,
2165 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2166 }
2167
2168 if (pipeline->gs_copy_shader) {
2169 void *code[MESA_SHADER_STAGES] = {0};
2170 unsigned code_size[MESA_SHADER_STAGES] = {0};
2171 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2172
2173 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2174 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2175 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2176
2177 radv_pipeline_cache_insert_shaders(device, cache,
2178 gs_copy_hash,
2179 variants,
2180 (const void**)code,
2181 code_size);
2182 }
2183 free(gs_copy_code);
2184 }
2185
2186 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2187 (const void**)codes, code_sizes);
2188
2189 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2190 free(codes[i]);
2191 if (nir[i]) {
2192 if (!pipeline->device->keep_shader_info)
2193 ralloc_free(nir[i]);
2194
2195 if (radv_can_dump_shader_stats(device, modules[i]))
2196 radv_shader_dump_stats(device,
2197 pipeline->shaders[i],
2198 i, stderr);
2199 }
2200 }
2201
2202 if (fs_m.nir)
2203 ralloc_free(fs_m.nir);
2204 }
2205
2206 static uint32_t
2207 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2208 gl_shader_stage stage, enum chip_class chip_class)
2209 {
2210 bool has_gs = radv_pipeline_has_gs(pipeline);
2211 bool has_tess = radv_pipeline_has_tess(pipeline);
2212 switch (stage) {
2213 case MESA_SHADER_FRAGMENT:
2214 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2215 case MESA_SHADER_VERTEX:
2216 if (chip_class >= GFX9) {
2217 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2218 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2219 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2220 }
2221 if (has_tess)
2222 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2223 else
2224 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2225 case MESA_SHADER_GEOMETRY:
2226 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2227 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2228 case MESA_SHADER_COMPUTE:
2229 return R_00B900_COMPUTE_USER_DATA_0;
2230 case MESA_SHADER_TESS_CTRL:
2231 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2232 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2233 case MESA_SHADER_TESS_EVAL:
2234 if (chip_class >= GFX9) {
2235 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2236 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2237 }
2238 if (has_gs)
2239 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2240 else
2241 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2242 default:
2243 unreachable("unknown shader");
2244 }
2245 }
2246
2247 struct radv_bin_size_entry {
2248 unsigned bpp;
2249 VkExtent2D extent;
2250 };
2251
2252 static VkExtent2D
2253 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2254 {
2255 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2256 {
2257 /* One RB / SE */
2258 {
2259 /* One shader engine */
2260 { 0, {128, 128}},
2261 { 1, { 64, 128}},
2262 { 2, { 32, 128}},
2263 { 3, { 16, 128}},
2264 { 17, { 0, 0}},
2265 { UINT_MAX, { 0, 0}},
2266 },
2267 {
2268 /* Two shader engines */
2269 { 0, {128, 128}},
2270 { 2, { 64, 128}},
2271 { 3, { 32, 128}},
2272 { 5, { 16, 128}},
2273 { 17, { 0, 0}},
2274 { UINT_MAX, { 0, 0}},
2275 },
2276 {
2277 /* Four shader engines */
2278 { 0, {128, 128}},
2279 { 3, { 64, 128}},
2280 { 5, { 16, 128}},
2281 { 17, { 0, 0}},
2282 { UINT_MAX, { 0, 0}},
2283 },
2284 },
2285 {
2286 /* Two RB / SE */
2287 {
2288 /* One shader engine */
2289 { 0, {128, 128}},
2290 { 2, { 64, 128}},
2291 { 3, { 32, 128}},
2292 { 5, { 16, 128}},
2293 { 33, { 0, 0}},
2294 { UINT_MAX, { 0, 0}},
2295 },
2296 {
2297 /* Two shader engines */
2298 { 0, {128, 128}},
2299 { 3, { 64, 128}},
2300 { 5, { 32, 128}},
2301 { 9, { 16, 128}},
2302 { 33, { 0, 0}},
2303 { UINT_MAX, { 0, 0}},
2304 },
2305 {
2306 /* Four shader engines */
2307 { 0, {256, 256}},
2308 { 2, {128, 256}},
2309 { 3, {128, 128}},
2310 { 5, { 64, 128}},
2311 { 9, { 16, 128}},
2312 { 33, { 0, 0}},
2313 { UINT_MAX, { 0, 0}},
2314 },
2315 },
2316 {
2317 /* Four RB / SE */
2318 {
2319 /* One shader engine */
2320 { 0, {128, 256}},
2321 { 2, {128, 128}},
2322 { 3, { 64, 128}},
2323 { 5, { 32, 128}},
2324 { 9, { 16, 128}},
2325 { 33, { 0, 0}},
2326 { UINT_MAX, { 0, 0}},
2327 },
2328 {
2329 /* Two shader engines */
2330 { 0, {256, 256}},
2331 { 2, {128, 256}},
2332 { 3, {128, 128}},
2333 { 5, { 64, 128}},
2334 { 9, { 32, 128}},
2335 { 17, { 16, 128}},
2336 { 33, { 0, 0}},
2337 { UINT_MAX, { 0, 0}},
2338 },
2339 {
2340 /* Four shader engines */
2341 { 0, {256, 512}},
2342 { 2, {256, 256}},
2343 { 3, {128, 256}},
2344 { 5, {128, 128}},
2345 { 9, { 64, 128}},
2346 { 17, { 16, 128}},
2347 { 33, { 0, 0}},
2348 { UINT_MAX, { 0, 0}},
2349 },
2350 },
2351 };
2352 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2353 {
2354 // One RB / SE
2355 {
2356 // One shader engine
2357 { 0, {128, 256}},
2358 { 2, {128, 128}},
2359 { 4, { 64, 128}},
2360 { 7, { 32, 128}},
2361 { 13, { 16, 128}},
2362 { 49, { 0, 0}},
2363 { UINT_MAX, { 0, 0}},
2364 },
2365 {
2366 // Two shader engines
2367 { 0, {256, 256}},
2368 { 2, {128, 256}},
2369 { 4, {128, 128}},
2370 { 7, { 64, 128}},
2371 { 13, { 32, 128}},
2372 { 25, { 16, 128}},
2373 { 49, { 0, 0}},
2374 { UINT_MAX, { 0, 0}},
2375 },
2376 {
2377 // Four shader engines
2378 { 0, {256, 512}},
2379 { 2, {256, 256}},
2380 { 4, {128, 256}},
2381 { 7, {128, 128}},
2382 { 13, { 64, 128}},
2383 { 25, { 16, 128}},
2384 { 49, { 0, 0}},
2385 { UINT_MAX, { 0, 0}},
2386 },
2387 },
2388 {
2389 // Two RB / SE
2390 {
2391 // One shader engine
2392 { 0, {256, 256}},
2393 { 2, {128, 256}},
2394 { 4, {128, 128}},
2395 { 7, { 64, 128}},
2396 { 13, { 32, 128}},
2397 { 25, { 16, 128}},
2398 { 97, { 0, 0}},
2399 { UINT_MAX, { 0, 0}},
2400 },
2401 {
2402 // Two shader engines
2403 { 0, {256, 512}},
2404 { 2, {256, 256}},
2405 { 4, {128, 256}},
2406 { 7, {128, 128}},
2407 { 13, { 64, 128}},
2408 { 25, { 32, 128}},
2409 { 49, { 16, 128}},
2410 { 97, { 0, 0}},
2411 { UINT_MAX, { 0, 0}},
2412 },
2413 {
2414 // Four shader engines
2415 { 0, {512, 512}},
2416 { 2, {256, 512}},
2417 { 4, {256, 256}},
2418 { 7, {128, 256}},
2419 { 13, {128, 128}},
2420 { 25, { 64, 128}},
2421 { 49, { 16, 128}},
2422 { 97, { 0, 0}},
2423 { UINT_MAX, { 0, 0}},
2424 },
2425 },
2426 {
2427 // Four RB / SE
2428 {
2429 // One shader engine
2430 { 0, {256, 512}},
2431 { 2, {256, 256}},
2432 { 4, {128, 256}},
2433 { 7, {128, 128}},
2434 { 13, { 64, 128}},
2435 { 25, { 32, 128}},
2436 { 49, { 16, 128}},
2437 { UINT_MAX, { 0, 0}},
2438 },
2439 {
2440 // Two shader engines
2441 { 0, {512, 512}},
2442 { 2, {256, 512}},
2443 { 4, {256, 256}},
2444 { 7, {128, 256}},
2445 { 13, {128, 128}},
2446 { 25, { 64, 128}},
2447 { 49, { 32, 128}},
2448 { 97, { 16, 128}},
2449 { UINT_MAX, { 0, 0}},
2450 },
2451 {
2452 // Four shader engines
2453 { 0, {512, 512}},
2454 { 4, {256, 512}},
2455 { 7, {256, 256}},
2456 { 13, {128, 256}},
2457 { 25, {128, 128}},
2458 { 49, { 64, 128}},
2459 { 97, { 16, 128}},
2460 { UINT_MAX, { 0, 0}},
2461 },
2462 },
2463 };
2464
2465 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2466 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2467 VkExtent2D extent = {512, 512};
2468
2469 unsigned log_num_rb_per_se =
2470 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2471 pipeline->device->physical_device->rad_info.max_se);
2472 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2473
2474 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
2475 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2476 unsigned effective_samples = total_samples;
2477 unsigned color_bytes_per_pixel = 0;
2478
2479 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2480 if (vkblend) {
2481 for (unsigned i = 0; i < subpass->color_count; i++) {
2482 if (!vkblend->pAttachments[i].colorWriteMask)
2483 continue;
2484
2485 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2486 continue;
2487
2488 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2489 color_bytes_per_pixel += vk_format_get_blocksize(format);
2490 }
2491
2492 /* MSAA images typically don't use all samples all the time. */
2493 if (effective_samples >= 2 && ps_iter_samples <= 1)
2494 effective_samples = 2;
2495 color_bytes_per_pixel *= effective_samples;
2496 }
2497
2498 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2499 while(color_entry[1].bpp <= color_bytes_per_pixel)
2500 ++color_entry;
2501
2502 extent = color_entry->extent;
2503
2504 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2505 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2506
2507 /* Coefficients taken from AMDVLK */
2508 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2509 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2510 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2511
2512 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2513 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
2514 ++ds_entry;
2515
2516 extent.width = MIN2(extent.width, ds_entry->extent.width);
2517 extent.height = MIN2(extent.height, ds_entry->extent.height);
2518 }
2519
2520 return extent;
2521 }
2522
2523 static void
2524 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *cs,
2525 struct radv_pipeline *pipeline,
2526 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2527 {
2528 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2529 return;
2530
2531 uint32_t pa_sc_binner_cntl_0 =
2532 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2533 S_028C44_DISABLE_START_OF_PRIM(1);
2534 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2535
2536 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2537
2538 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2539 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2540 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2541
2542 switch (pipeline->device->physical_device->rad_info.family) {
2543 case CHIP_VEGA10:
2544 case CHIP_VEGA12:
2545 case CHIP_VEGA20:
2546 context_states_per_bin = 1;
2547 persistent_states_per_bin = 1;
2548 fpovs_per_batch = 63;
2549 break;
2550 case CHIP_RAVEN:
2551 case CHIP_RAVEN2:
2552 context_states_per_bin = 6;
2553 persistent_states_per_bin = 32;
2554 fpovs_per_batch = 63;
2555 break;
2556 default:
2557 unreachable("unhandled family while determining binning state.");
2558 }
2559
2560 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2561 pa_sc_binner_cntl_0 =
2562 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2563 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2564 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2565 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2566 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2567 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2568 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2569 S_028C44_DISABLE_START_OF_PRIM(1) |
2570 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2571 S_028C44_OPTIMAL_BIN_SELECTION(1);
2572 }
2573
2574 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2575 pa_sc_binner_cntl_0);
2576 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2577 db_dfsm_control);
2578 }
2579
2580
2581 static void
2582 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *cs,
2583 struct radv_pipeline *pipeline,
2584 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2585 const struct radv_graphics_pipeline_create_info *extra)
2586 {
2587 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2588 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2589 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2590 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2591 struct radv_render_pass_attachment *attachment = NULL;
2592 uint32_t db_depth_control = 0, db_stencil_control = 0;
2593 uint32_t db_render_control = 0, db_render_override2 = 0;
2594 uint32_t db_render_override = 0;
2595
2596 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2597 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2598
2599 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2600 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2601
2602 if (vkds && has_depth_attachment) {
2603 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2604 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2605 S_028800_ZFUNC(vkds->depthCompareOp) |
2606 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2607
2608 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2609 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2610 }
2611
2612 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2613 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2614 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2615 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2616 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2617 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2618
2619 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2620 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2621 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2622 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2623 }
2624
2625 if (attachment && extra) {
2626 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2627 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2628
2629 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2630 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2631 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2632 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2633 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2634 }
2635
2636 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2637 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2638
2639 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2640 !pCreateInfo->pRasterizationState->depthClampEnable &&
2641 ps->info.info.ps.writes_z) {
2642 /* From VK_EXT_depth_range_unrestricted spec:
2643 *
2644 * "The behavior described in Primitive Clipping still applies.
2645 * If depth clamping is disabled the depth values are still
2646 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2647 * depth clamping is enabled the above equation is ignored and
2648 * the depth values are instead clamped to the VkViewport
2649 * minDepth and maxDepth values, which in the case of this
2650 * extension can be outside of the 0.0 to 1.0 range."
2651 */
2652 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2653 }
2654
2655 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2656 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2657
2658 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2659 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2660 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2661 }
2662
2663 static void
2664 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *cs,
2665 struct radv_pipeline *pipeline,
2666 const struct radv_blend_state *blend)
2667 {
2668 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2669 radeon_emit_array(cs, blend->cb_blend_control,
2670 8);
2671 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2672 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2673
2674 if (pipeline->device->physical_device->has_rbplus) {
2675
2676 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2677 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2678 }
2679
2680 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2681
2682 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2683 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2684
2685 pipeline->graphics.col_format = blend->spi_shader_col_format;
2686 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
2687 }
2688
2689 static const VkConservativeRasterizationModeEXT
2690 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
2691 {
2692 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
2693 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
2694
2695 if (!conservative_raster)
2696 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
2697 return conservative_raster->conservativeRasterizationMode;
2698 }
2699
2700 static void
2701 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *cs,
2702 struct radv_pipeline *pipeline,
2703 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2704 {
2705 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2706 const VkConservativeRasterizationModeEXT mode =
2707 radv_get_conservative_raster_mode(vkraster);
2708 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
2709
2710 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2711 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2712 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2713 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2714 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2715 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2716
2717 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2718 S_0286D4_FLAT_SHADE_ENA(1) |
2719 S_0286D4_PNT_SPRITE_ENA(1) |
2720 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2721 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2722 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2723 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2724 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2725
2726 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2727 S_028BE4_PIX_CENTER(1) | // TODO verify
2728 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2729 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2730
2731 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2732 S_028814_FACE(vkraster->frontFace) |
2733 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2734 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2735 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2736 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2737 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2738 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2739 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2740 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2741
2742 /* Conservative rasterization. */
2743 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
2744 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2745
2746 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
2747 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
2748 S_028804_OVERRASTERIZATION_AMOUNT(4);
2749
2750 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
2751 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
2752 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
2753
2754 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
2755 pa_sc_conservative_rast |=
2756 S_028C4C_OVER_RAST_ENABLE(1) |
2757 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
2758 S_028C4C_UNDER_RAST_ENABLE(0) |
2759 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
2760 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
2761 } else {
2762 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
2763 pa_sc_conservative_rast |=
2764 S_028C4C_OVER_RAST_ENABLE(0) |
2765 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
2766 S_028C4C_UNDER_RAST_ENABLE(1) |
2767 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
2768 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
2769 }
2770 }
2771
2772 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
2773 pa_sc_conservative_rast);
2774 }
2775
2776
2777 static void
2778 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs,
2779 struct radv_pipeline *pipeline)
2780 {
2781 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2782
2783 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2784 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2785 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2786
2787 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2788 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2789
2790 /* The exclusion bits can be set to improve rasterization efficiency
2791 * if no sample lies on the pixel boundary (-8 sample offset). It's
2792 * currently always TRUE because the driver doesn't support 16 samples.
2793 */
2794 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= CIK;
2795 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
2796 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
2797 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
2798 }
2799
2800 static void
2801 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *cs,
2802 const struct radv_pipeline *pipeline)
2803 {
2804 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2805
2806 uint32_t vgt_primitiveid_en = false;
2807 uint32_t vgt_gs_mode = 0;
2808
2809 if (radv_pipeline_has_gs(pipeline)) {
2810 const struct radv_shader_variant *gs =
2811 pipeline->shaders[MESA_SHADER_GEOMETRY];
2812
2813 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2814 pipeline->device->physical_device->rad_info.chip_class);
2815 } else if (outinfo->export_prim_id) {
2816 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2817 vgt_primitiveid_en = true;
2818 }
2819
2820 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2821 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2822 }
2823
2824 static void
2825 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *cs,
2826 struct radv_pipeline *pipeline,
2827 struct radv_shader_variant *shader)
2828 {
2829 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2830
2831 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2832 radeon_emit(cs, va >> 8);
2833 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2834 radeon_emit(cs, shader->rsrc1);
2835 radeon_emit(cs, shader->rsrc2);
2836
2837 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2838 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2839 clip_dist_mask = outinfo->clip_dist_mask;
2840 cull_dist_mask = outinfo->cull_dist_mask;
2841 total_mask = clip_dist_mask | cull_dist_mask;
2842 bool misc_vec_ena = outinfo->writes_pointsize ||
2843 outinfo->writes_layer ||
2844 outinfo->writes_viewport_index;
2845
2846 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2847 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2848
2849 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2850 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2851 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2852 V_02870C_SPI_SHADER_4COMP :
2853 V_02870C_SPI_SHADER_NONE) |
2854 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2855 V_02870C_SPI_SHADER_4COMP :
2856 V_02870C_SPI_SHADER_NONE) |
2857 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2858 V_02870C_SPI_SHADER_4COMP :
2859 V_02870C_SPI_SHADER_NONE));
2860
2861 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2862 S_028818_VTX_W0_FMT(1) |
2863 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2864 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2865 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2866
2867 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2868 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2869 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2870 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2871 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2872 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2873 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2874 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2875 cull_dist_mask << 8 |
2876 clip_dist_mask);
2877
2878 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2879 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2880 outinfo->writes_viewport_index);
2881 }
2882
2883 static void
2884 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
2885 struct radv_pipeline *pipeline,
2886 struct radv_shader_variant *shader)
2887 {
2888 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2889
2890 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2891 radeon_emit(cs, va >> 8);
2892 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2893 radeon_emit(cs, shader->rsrc1);
2894 radeon_emit(cs, shader->rsrc2);
2895 }
2896
2897 static void
2898 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
2899 struct radv_pipeline *pipeline,
2900 struct radv_shader_variant *shader,
2901 const struct radv_tessellation_state *tess)
2902 {
2903 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2904 uint32_t rsrc2 = shader->rsrc2;
2905
2906 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2907 radeon_emit(cs, va >> 8);
2908 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2909
2910 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2911 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2912 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2913 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2914
2915 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2916 radeon_emit(cs, shader->rsrc1);
2917 radeon_emit(cs, rsrc2);
2918 }
2919
2920 static void
2921 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
2922 struct radv_pipeline *pipeline,
2923 struct radv_shader_variant *shader,
2924 const struct radv_tessellation_state *tess)
2925 {
2926 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2927
2928 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2929 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2930 radeon_emit(cs, va >> 8);
2931 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2932
2933 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2934 radeon_emit(cs, shader->rsrc1);
2935 radeon_emit(cs, shader->rsrc2 |
2936 S_00B42C_LDS_SIZE(tess->lds_size));
2937 } else {
2938 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2939 radeon_emit(cs, va >> 8);
2940 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2941 radeon_emit(cs, shader->rsrc1);
2942 radeon_emit(cs, shader->rsrc2);
2943 }
2944 }
2945
2946 static void
2947 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *cs,
2948 struct radv_pipeline *pipeline,
2949 const struct radv_tessellation_state *tess)
2950 {
2951 struct radv_shader_variant *vs;
2952
2953 /* Skip shaders merged into HS/GS */
2954 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2955 if (!vs)
2956 return;
2957
2958 if (vs->info.vs.as_ls)
2959 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2960 else if (vs->info.vs.as_es)
2961 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2962 else
2963 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2964 }
2965
2966 static void
2967 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *cs,
2968 struct radv_pipeline *pipeline,
2969 const struct radv_tessellation_state *tess)
2970 {
2971 if (!radv_pipeline_has_tess(pipeline))
2972 return;
2973
2974 struct radv_shader_variant *tes, *tcs;
2975
2976 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2977 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2978
2979 if (tes) {
2980 if (tes->info.tes.as_es)
2981 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2982 else
2983 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2984 }
2985
2986 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2987
2988 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2989 tess->tf_param);
2990
2991 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2992 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2993 tess->ls_hs_config);
2994 else
2995 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2996 tess->ls_hs_config);
2997 }
2998
2999 static void
3000 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *cs,
3001 struct radv_pipeline *pipeline,
3002 const struct radv_gs_state *gs_state)
3003 {
3004 struct radv_shader_variant *gs;
3005 unsigned gs_max_out_vertices;
3006 uint8_t *num_components;
3007 uint8_t max_stream;
3008 unsigned offset;
3009 uint64_t va;
3010
3011 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3012 if (!gs)
3013 return;
3014
3015 gs_max_out_vertices = gs->info.gs.vertices_out;
3016 max_stream = gs->info.info.gs.max_stream;
3017 num_components = gs->info.info.gs.num_stream_output_components;
3018
3019 offset = num_components[0] * gs_max_out_vertices;
3020
3021 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3022 radeon_emit(cs, offset);
3023 if (max_stream >= 1)
3024 offset += num_components[1] * gs_max_out_vertices;
3025 radeon_emit(cs, offset);
3026 if (max_stream >= 2)
3027 offset += num_components[2] * gs_max_out_vertices;
3028 radeon_emit(cs, offset);
3029 if (max_stream >= 3)
3030 offset += num_components[3] * gs_max_out_vertices;
3031 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3032
3033 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
3034
3035 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3036 radeon_emit(cs, num_components[0]);
3037 radeon_emit(cs, (max_stream >= 1) ? num_components[1] : 0);
3038 radeon_emit(cs, (max_stream >= 2) ? num_components[2] : 0);
3039 radeon_emit(cs, (max_stream >= 3) ? num_components[3] : 0);
3040
3041 uint32_t gs_num_invocations = gs->info.gs.invocations;
3042 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
3043 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3044 S_028B90_ENABLE(gs_num_invocations > 0));
3045
3046 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3047 gs_state->vgt_esgs_ring_itemsize);
3048
3049 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
3050
3051 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3052 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
3053 radeon_emit(cs, va >> 8);
3054 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
3055
3056 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3057 radeon_emit(cs, gs->rsrc1);
3058 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
3059
3060 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
3061 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
3062 } else {
3063 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
3064 radeon_emit(cs, va >> 8);
3065 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
3066 radeon_emit(cs, gs->rsrc1);
3067 radeon_emit(cs, gs->rsrc2);
3068 }
3069
3070 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
3071 }
3072
3073 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
3074 {
3075 uint32_t ps_input_cntl;
3076 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3077 ps_input_cntl = S_028644_OFFSET(offset);
3078 if (flat_shade)
3079 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3080 } else {
3081 /* The input is a DEFAULT_VAL constant. */
3082 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3083 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3084 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3085 ps_input_cntl = S_028644_OFFSET(0x20) |
3086 S_028644_DEFAULT_VAL(offset);
3087 }
3088 return ps_input_cntl;
3089 }
3090
3091 static void
3092 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *cs,
3093 struct radv_pipeline *pipeline)
3094 {
3095 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3096 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3097 uint32_t ps_input_cntl[32];
3098
3099 unsigned ps_offset = 0;
3100
3101 if (ps->info.info.ps.prim_id_input) {
3102 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3103 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3104 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3105 ++ps_offset;
3106 }
3107 }
3108
3109 if (ps->info.info.ps.layer_input ||
3110 ps->info.info.ps.uses_input_attachments ||
3111 ps->info.info.needs_multiview_view_index) {
3112 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3113 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3114 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
3115 else
3116 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
3117 ++ps_offset;
3118 }
3119
3120 if (ps->info.info.ps.has_pcoord) {
3121 unsigned val;
3122 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3123 ps_input_cntl[ps_offset] = val;
3124 ps_offset++;
3125 }
3126
3127 if (ps->info.info.ps.num_input_clips_culls) {
3128 unsigned vs_offset;
3129
3130 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
3131 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3132 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
3133 ++ps_offset;
3134 }
3135
3136 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
3137 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
3138 ps->info.info.ps.num_input_clips_culls > 4) {
3139 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false);
3140 ++ps_offset;
3141 }
3142 }
3143
3144 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3145 unsigned vs_offset;
3146 bool flat_shade;
3147 if (!(ps->info.fs.input_mask & (1u << i)))
3148 continue;
3149
3150 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3151 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3152 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3153 ++ps_offset;
3154 continue;
3155 }
3156
3157 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
3158
3159 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
3160 ++ps_offset;
3161 }
3162
3163 if (ps_offset) {
3164 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
3165 for (unsigned i = 0; i < ps_offset; i++) {
3166 radeon_emit(cs, ps_input_cntl[i]);
3167 }
3168 }
3169 }
3170
3171 static uint32_t
3172 radv_compute_db_shader_control(const struct radv_device *device,
3173 const struct radv_pipeline *pipeline,
3174 const struct radv_shader_variant *ps)
3175 {
3176 const struct radv_multisample_state *ms = &pipeline->graphics.ms;
3177 unsigned z_order;
3178 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3179 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3180 else
3181 z_order = V_02880C_LATE_Z;
3182
3183 bool disable_rbplus = device->physical_device->has_rbplus &&
3184 !device->physical_device->rbplus_allowed;
3185
3186 /* Do not enable the gl_SampleMask fragment shader output if MSAA is
3187 * disabled.
3188 */
3189 bool mask_export_enable = ms->num_samples > 1 &&
3190 ps->info.info.ps.writes_sample_mask;
3191
3192 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
3193 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
3194 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
3195 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
3196 S_02880C_Z_ORDER(z_order) |
3197 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3198 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3199 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3200 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
3201 }
3202
3203 static void
3204 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *cs,
3205 struct radv_pipeline *pipeline)
3206 {
3207 struct radv_shader_variant *ps;
3208 uint64_t va;
3209 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3210
3211 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3212 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3213
3214 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3215 radeon_emit(cs, va >> 8);
3216 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3217 radeon_emit(cs, ps->rsrc1);
3218 radeon_emit(cs, ps->rsrc2);
3219
3220 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
3221 radv_compute_db_shader_control(pipeline->device,
3222 pipeline, ps));
3223
3224 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
3225 ps->config.spi_ps_input_ena);
3226
3227 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
3228 ps->config.spi_ps_input_addr);
3229
3230 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
3231 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3232
3233 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3234
3235 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
3236 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3237 ps->info.info.ps.writes_stencil,
3238 ps->info.info.ps.writes_sample_mask));
3239
3240 if (pipeline->device->dfsm_allowed) {
3241 /* optimise this? */
3242 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3243 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3244 }
3245 }
3246
3247 static void
3248 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *cs,
3249 struct radv_pipeline *pipeline)
3250 {
3251 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
3252 return;
3253
3254 unsigned vtx_reuse_depth = 30;
3255 if (radv_pipeline_has_tess(pipeline) &&
3256 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3257 vtx_reuse_depth = 14;
3258 }
3259 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3260 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3261 }
3262
3263 static uint32_t
3264 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3265 {
3266 uint32_t stages = 0;
3267 if (radv_pipeline_has_tess(pipeline)) {
3268 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3269 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3270
3271 if (radv_pipeline_has_gs(pipeline))
3272 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3273 S_028B54_GS_EN(1) |
3274 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3275 else
3276 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3277
3278 } else if (radv_pipeline_has_gs(pipeline))
3279 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3280 S_028B54_GS_EN(1) |
3281 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3282
3283 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3284 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3285
3286 return stages;
3287 }
3288
3289 static uint32_t
3290 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3291 {
3292 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3293 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3294
3295 if (!discard_rectangle_info)
3296 return 0xffff;
3297
3298 unsigned mask = 0;
3299
3300 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3301 /* Interpret i as a bitmask, and then set the bit in the mask if
3302 * that combination of rectangles in which the pixel is contained
3303 * should pass the cliprect test. */
3304 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3305
3306 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3307 !relevant_subset)
3308 continue;
3309
3310 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3311 relevant_subset)
3312 continue;
3313
3314 mask |= 1u << i;
3315 }
3316
3317 return mask;
3318 }
3319
3320 static void
3321 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
3322 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3323 const struct radv_graphics_pipeline_create_info *extra,
3324 const struct radv_blend_state *blend,
3325 const struct radv_tessellation_state *tess,
3326 const struct radv_gs_state *gs,
3327 unsigned prim, unsigned gs_out)
3328 {
3329 pipeline->cs.buf = malloc(4 * 256);
3330 pipeline->cs.max_dw = 256;
3331
3332 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
3333 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
3334 radv_pipeline_generate_raster_state(&pipeline->cs, pipeline, pCreateInfo);
3335 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
3336 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
3337 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
3338 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
3339 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
3340 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
3341 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
3342 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
3343 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
3344
3345 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
3346 S_0286E8_WAVES(pipeline->max_waves) |
3347 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3348
3349 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
3350
3351 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
3352 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
3353 } else {
3354 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
3355 }
3356 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
3357
3358 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
3359
3360 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3361 }
3362
3363 static struct radv_ia_multi_vgt_param_helpers
3364 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
3365 const struct radv_tessellation_state *tess,
3366 uint32_t prim)
3367 {
3368 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
3369 const struct radv_device *device = pipeline->device;
3370
3371 if (radv_pipeline_has_tess(pipeline))
3372 ia_multi_vgt_param.primgroup_size = tess->num_patches;
3373 else if (radv_pipeline_has_gs(pipeline))
3374 ia_multi_vgt_param.primgroup_size = 64;
3375 else
3376 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3377
3378 /* GS requirement. */
3379 ia_multi_vgt_param.partial_es_wave = false;
3380 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
3381 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3382 ia_multi_vgt_param.partial_es_wave = true;
3383
3384 ia_multi_vgt_param.wd_switch_on_eop = false;
3385 if (device->physical_device->rad_info.chip_class >= CIK) {
3386 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3387 * 4 shader engines. Set 1 to pass the assertion below.
3388 * The other cases are hardware requirements. */
3389 if (device->physical_device->rad_info.max_se < 4 ||
3390 prim == V_008958_DI_PT_POLYGON ||
3391 prim == V_008958_DI_PT_LINELOOP ||
3392 prim == V_008958_DI_PT_TRIFAN ||
3393 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3394 (pipeline->graphics.prim_restart_enable &&
3395 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3396 (prim != V_008958_DI_PT_POINTLIST &&
3397 prim != V_008958_DI_PT_LINESTRIP &&
3398 prim != V_008958_DI_PT_TRISTRIP))))
3399 ia_multi_vgt_param.wd_switch_on_eop = true;
3400 }
3401
3402 ia_multi_vgt_param.ia_switch_on_eoi = false;
3403 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3404 ia_multi_vgt_param.ia_switch_on_eoi = true;
3405 if (radv_pipeline_has_gs(pipeline) &&
3406 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3407 ia_multi_vgt_param.ia_switch_on_eoi = true;
3408 if (radv_pipeline_has_tess(pipeline)) {
3409 /* SWITCH_ON_EOI must be set if PrimID is used. */
3410 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3411 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
3412 ia_multi_vgt_param.ia_switch_on_eoi = true;
3413 }
3414
3415 ia_multi_vgt_param.partial_vs_wave = false;
3416 if (radv_pipeline_has_tess(pipeline)) {
3417 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3418 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3419 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3420 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3421 radv_pipeline_has_gs(pipeline))
3422 ia_multi_vgt_param.partial_vs_wave = true;
3423 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3424 if (device->has_distributed_tess) {
3425 if (radv_pipeline_has_gs(pipeline)) {
3426 if (device->physical_device->rad_info.chip_class <= VI)
3427 ia_multi_vgt_param.partial_es_wave = true;
3428
3429 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3430 device->physical_device->rad_info.family == CHIP_FIJI ||
3431 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3432 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3433 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
3434 device->physical_device->rad_info.family == CHIP_VEGAM)
3435 ia_multi_vgt_param.partial_vs_wave = true;
3436 } else {
3437 ia_multi_vgt_param.partial_vs_wave = true;
3438 }
3439 }
3440 }
3441
3442 /* Workaround for a VGT hang when strip primitive types are used with
3443 * primitive restart.
3444 */
3445 if (pipeline->graphics.prim_restart_enable &&
3446 (prim == V_008958_DI_PT_LINESTRIP ||
3447 prim == V_008958_DI_PT_TRISTRIP ||
3448 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
3449 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
3450 ia_multi_vgt_param.partial_vs_wave = true;
3451 }
3452
3453 ia_multi_vgt_param.base =
3454 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3455 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3456 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3457 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3458 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3459
3460 return ia_multi_vgt_param;
3461 }
3462
3463
3464 static void
3465 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3466 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3467 {
3468 const VkPipelineVertexInputStateCreateInfo *vi_info =
3469 pCreateInfo->pVertexInputState;
3470 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3471
3472 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3473 const VkVertexInputAttributeDescription *desc =
3474 &vi_info->pVertexAttributeDescriptions[i];
3475 unsigned loc = desc->location;
3476 const struct vk_format_description *format_desc;
3477 int first_non_void;
3478 uint32_t num_format, data_format;
3479 format_desc = vk_format_description(desc->format);
3480 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3481
3482 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3483 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3484
3485 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3486 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3487 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3488 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3489 S_008F0C_NUM_FORMAT(num_format) |
3490 S_008F0C_DATA_FORMAT(data_format);
3491 velems->format_size[loc] = format_desc->block.bits / 8;
3492 velems->offset[loc] = desc->offset;
3493 velems->binding[loc] = desc->binding;
3494 velems->count = MAX2(velems->count, loc + 1);
3495 }
3496
3497 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3498 const VkVertexInputBindingDescription *desc =
3499 &vi_info->pVertexBindingDescriptions[i];
3500
3501 pipeline->binding_stride[desc->binding] = desc->stride;
3502 }
3503 }
3504
3505 static struct radv_shader_variant *
3506 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
3507 {
3508 int i;
3509
3510 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
3511 struct radv_shader_variant *shader =
3512 radv_get_shader(pipeline, i);
3513
3514 if (shader && shader->info.info.so.num_outputs > 0)
3515 return shader;
3516 }
3517
3518 return NULL;
3519 }
3520
3521 static VkResult
3522 radv_pipeline_init(struct radv_pipeline *pipeline,
3523 struct radv_device *device,
3524 struct radv_pipeline_cache *cache,
3525 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3526 const struct radv_graphics_pipeline_create_info *extra,
3527 const VkAllocationCallbacks *alloc)
3528 {
3529 VkResult result;
3530 bool has_view_index = false;
3531
3532 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3533 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3534 if (subpass->view_mask)
3535 has_view_index = true;
3536 if (alloc == NULL)
3537 alloc = &device->alloc;
3538
3539 pipeline->device = device;
3540 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3541 assert(pipeline->layout);
3542
3543 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3544
3545 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3546 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3547 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3548 pStages[stage] = &pCreateInfo->pStages[i];
3549 }
3550
3551 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
3552 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags);
3553
3554 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3555 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
3556 uint32_t gs_out;
3557 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3558
3559 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3560
3561 if (radv_pipeline_has_gs(pipeline)) {
3562 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3563 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3564 } else {
3565 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3566 }
3567 if (extra && extra->use_rectlist) {
3568 prim = V_008958_DI_PT_RECTLIST;
3569 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3570 pipeline->graphics.can_use_guardband = true;
3571 }
3572 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3573 /* prim vertex count will need TESS changes */
3574 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3575
3576 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3577
3578 /* Ensure that some export memory is always allocated, for two reasons:
3579 *
3580 * 1) Correctness: The hardware ignores the EXEC mask if no export
3581 * memory is allocated, so KILL and alpha test do not work correctly
3582 * without this.
3583 * 2) Performance: Every shader needs at least a NULL export, even when
3584 * it writes no color/depth output. The NULL export instruction
3585 * stalls without this setting.
3586 *
3587 * Don't add this to CB_SHADER_MASK.
3588 */
3589 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3590 if (!blend.spi_shader_col_format) {
3591 if (!ps->info.info.ps.writes_z &&
3592 !ps->info.info.ps.writes_stencil &&
3593 !ps->info.info.ps.writes_sample_mask)
3594 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3595 }
3596
3597 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3598 if (pipeline->shaders[i]) {
3599 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3600 }
3601 }
3602
3603 struct radv_gs_state gs = {0};
3604 if (radv_pipeline_has_gs(pipeline)) {
3605 gs = calculate_gs_info(pCreateInfo, pipeline);
3606 calculate_gs_ring_sizes(pipeline, &gs);
3607 }
3608
3609 struct radv_tessellation_state tess = {0};
3610 if (radv_pipeline_has_tess(pipeline)) {
3611 if (prim == V_008958_DI_PT_PATCH) {
3612 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3613 pipeline->graphics.prim_vertex_count.incr = 1;
3614 }
3615 tess = calculate_tess_state(pipeline, pCreateInfo);
3616 }
3617
3618 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3619
3620 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3621
3622 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3623 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3624
3625 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3626 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3627 if (loc->sgpr_idx != -1) {
3628 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3629 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3630 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
3631 pipeline->graphics.vtx_emit_num = 3;
3632 else
3633 pipeline->graphics.vtx_emit_num = 2;
3634 }
3635
3636 /* Find the last vertex shader stage that eventually uses streamout. */
3637 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
3638
3639 result = radv_pipeline_scratch_init(device, pipeline);
3640 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3641
3642 return result;
3643 }
3644
3645 VkResult
3646 radv_graphics_pipeline_create(
3647 VkDevice _device,
3648 VkPipelineCache _cache,
3649 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3650 const struct radv_graphics_pipeline_create_info *extra,
3651 const VkAllocationCallbacks *pAllocator,
3652 VkPipeline *pPipeline)
3653 {
3654 RADV_FROM_HANDLE(radv_device, device, _device);
3655 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3656 struct radv_pipeline *pipeline;
3657 VkResult result;
3658
3659 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3660 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3661 if (pipeline == NULL)
3662 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3663
3664 result = radv_pipeline_init(pipeline, device, cache,
3665 pCreateInfo, extra, pAllocator);
3666 if (result != VK_SUCCESS) {
3667 radv_pipeline_destroy(device, pipeline, pAllocator);
3668 return result;
3669 }
3670
3671 *pPipeline = radv_pipeline_to_handle(pipeline);
3672
3673 return VK_SUCCESS;
3674 }
3675
3676 VkResult radv_CreateGraphicsPipelines(
3677 VkDevice _device,
3678 VkPipelineCache pipelineCache,
3679 uint32_t count,
3680 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3681 const VkAllocationCallbacks* pAllocator,
3682 VkPipeline* pPipelines)
3683 {
3684 VkResult result = VK_SUCCESS;
3685 unsigned i = 0;
3686
3687 for (; i < count; i++) {
3688 VkResult r;
3689 r = radv_graphics_pipeline_create(_device,
3690 pipelineCache,
3691 &pCreateInfos[i],
3692 NULL, pAllocator, &pPipelines[i]);
3693 if (r != VK_SUCCESS) {
3694 result = r;
3695 pPipelines[i] = VK_NULL_HANDLE;
3696 }
3697 }
3698
3699 return result;
3700 }
3701
3702
3703 static void
3704 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3705 {
3706 struct radv_shader_variant *compute_shader;
3707 struct radv_device *device = pipeline->device;
3708 unsigned compute_resource_limits;
3709 unsigned waves_per_threadgroup;
3710 uint64_t va;
3711
3712 pipeline->cs.buf = malloc(20 * 4);
3713 pipeline->cs.max_dw = 20;
3714
3715 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3716 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3717
3718 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3719 radeon_emit(&pipeline->cs, va >> 8);
3720 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3721
3722 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3723 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3724 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3725
3726 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3727 S_00B860_WAVES(pipeline->max_waves) |
3728 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3729
3730 /* Calculate best compute resource limits. */
3731 waves_per_threadgroup =
3732 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3733 compute_shader->info.cs.block_size[1] *
3734 compute_shader->info.cs.block_size[2], 64);
3735 compute_resource_limits =
3736 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3737
3738 if (device->physical_device->rad_info.chip_class >= CIK) {
3739 unsigned num_cu_per_se =
3740 device->physical_device->rad_info.num_good_compute_units /
3741 device->physical_device->rad_info.max_se;
3742
3743 /* Force even distribution on all SIMDs in CU if the workgroup
3744 * size is 64. This has shown some good improvements if # of
3745 * CUs per SE is not a multiple of 4.
3746 */
3747 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3748 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3749 }
3750
3751 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3752 compute_resource_limits);
3753
3754 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3755 radeon_emit(&pipeline->cs,
3756 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3757 radeon_emit(&pipeline->cs,
3758 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3759 radeon_emit(&pipeline->cs,
3760 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3761
3762 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3763 }
3764
3765 static VkResult radv_compute_pipeline_create(
3766 VkDevice _device,
3767 VkPipelineCache _cache,
3768 const VkComputePipelineCreateInfo* pCreateInfo,
3769 const VkAllocationCallbacks* pAllocator,
3770 VkPipeline* pPipeline)
3771 {
3772 RADV_FROM_HANDLE(radv_device, device, _device);
3773 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3774 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3775 struct radv_pipeline *pipeline;
3776 VkResult result;
3777
3778 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3779 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3780 if (pipeline == NULL)
3781 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3782
3783 pipeline->device = device;
3784 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3785 assert(pipeline->layout);
3786
3787 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3788 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags);
3789
3790 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3791 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3792 result = radv_pipeline_scratch_init(device, pipeline);
3793 if (result != VK_SUCCESS) {
3794 radv_pipeline_destroy(device, pipeline, pAllocator);
3795 return result;
3796 }
3797
3798 radv_compute_generate_pm4(pipeline);
3799
3800 *pPipeline = radv_pipeline_to_handle(pipeline);
3801
3802 return VK_SUCCESS;
3803 }
3804
3805 VkResult radv_CreateComputePipelines(
3806 VkDevice _device,
3807 VkPipelineCache pipelineCache,
3808 uint32_t count,
3809 const VkComputePipelineCreateInfo* pCreateInfos,
3810 const VkAllocationCallbacks* pAllocator,
3811 VkPipeline* pPipelines)
3812 {
3813 VkResult result = VK_SUCCESS;
3814
3815 unsigned i = 0;
3816 for (; i < count; i++) {
3817 VkResult r;
3818 r = radv_compute_pipeline_create(_device, pipelineCache,
3819 &pCreateInfos[i],
3820 pAllocator, &pPipelines[i]);
3821 if (r != VK_SUCCESS) {
3822 result = r;
3823 pPipelines[i] = VK_NULL_HANDLE;
3824 }
3825 }
3826
3827 return result;
3828 }