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radv: dump NIR when a GPU hang is detected
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "vk_util.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40
41 #include "sid.h"
42 #include "gfx9d.h"
43 #include "r600d_common.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 static void
52 radv_pipeline_destroy(struct radv_device *device,
53 struct radv_pipeline *pipeline,
54 const VkAllocationCallbacks* allocator)
55 {
56 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
57 if (pipeline->shaders[i])
58 radv_shader_variant_destroy(device, pipeline->shaders[i]);
59
60 if (pipeline->gs_copy_shader)
61 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
62
63 vk_free2(&device->alloc, allocator, pipeline);
64 }
65
66 void radv_DestroyPipeline(
67 VkDevice _device,
68 VkPipeline _pipeline,
69 const VkAllocationCallbacks* pAllocator)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
73
74 if (!_pipeline)
75 return;
76
77 radv_pipeline_destroy(device, pipeline, pAllocator);
78 }
79
80 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
81 {
82 int i;
83
84 for (i = 0; i < MESA_SHADER_STAGES; i++) {
85 if (!pipeline->shaders[i])
86 continue;
87
88 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
89 }
90 }
91
92 static struct radv_shader_variant *
93 radv_pipeline_compile(struct radv_pipeline *pipeline,
94 struct radv_pipeline_cache *cache,
95 struct radv_shader_module *module,
96 const char *entrypoint,
97 gl_shader_stage stage,
98 const VkSpecializationInfo *spec_info,
99 struct radv_pipeline_layout *layout,
100 const struct ac_shader_variant_key *key)
101 {
102 unsigned char sha1[20];
103 unsigned char gs_copy_sha1[20];
104 struct radv_shader_variant *variant;
105 nir_shader *nir;
106 void *code = NULL;
107 unsigned code_size = 0;
108
109 if (module->nir)
110 _mesa_sha1_compute(module->nir->info.name,
111 strlen(module->nir->info.name),
112 module->sha1);
113
114 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
115 if (stage == MESA_SHADER_GEOMETRY)
116 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
117 layout, key, 1);
118
119 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
120 cache,
121 sha1);
122
123 if (stage == MESA_SHADER_GEOMETRY) {
124 pipeline->gs_copy_shader =
125 radv_create_shader_variant_from_pipeline_cache(
126 pipeline->device,
127 cache,
128 gs_copy_sha1);
129 }
130
131 if (variant &&
132 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
133 return variant;
134
135 nir = radv_shader_compile_to_nir(pipeline->device,
136 module, entrypoint, stage,
137 spec_info);
138 if (nir == NULL)
139 return NULL;
140
141 if (!variant) {
142 variant = radv_shader_variant_create(pipeline->device, module, nir,
143 layout, key, &code,
144 &code_size);
145 }
146
147 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
148 void *gs_copy_code = NULL;
149 unsigned gs_copy_code_size = 0;
150 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
151 pipeline->device, nir, &gs_copy_code,
152 &gs_copy_code_size, key->has_multiview_view_index);
153
154 if (pipeline->gs_copy_shader) {
155 pipeline->gs_copy_shader =
156 radv_pipeline_cache_insert_shader(pipeline->device,
157 cache,
158 gs_copy_sha1,
159 pipeline->gs_copy_shader,
160 gs_copy_code,
161 gs_copy_code_size);
162 }
163
164 free(gs_copy_code);
165 }
166 if (!module->nir && !pipeline->device->trace_bo)
167 ralloc_free(nir);
168
169 if (variant)
170 variant = radv_pipeline_cache_insert_shader(pipeline->device,
171 cache, sha1,
172 variant, code,
173 code_size);
174
175 if (code)
176 free(code);
177 return variant;
178 }
179
180 static struct ac_shader_variant_key
181 radv_compute_tes_key(bool as_es, bool export_prim_id)
182 {
183 struct ac_shader_variant_key key;
184 memset(&key, 0, sizeof(key));
185 key.tes.as_es = as_es;
186 /* export prim id only happens when no geom shader */
187 if (!as_es)
188 key.tes.export_prim_id = export_prim_id;
189 return key;
190 }
191
192 static struct ac_shader_variant_key
193 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
194 {
195 struct ac_shader_variant_key key;
196 memset(&key, 0, sizeof(key));
197 key.tcs.primitive_mode = primitive_mode;
198 key.tcs.input_vertices = input_vertices;
199 return key;
200 }
201
202 static void
203 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
204 struct radv_pipeline_cache *cache,
205 struct radv_shader_module *tcs_module,
206 struct radv_shader_module *tes_module,
207 const char *tcs_entrypoint,
208 const char *tes_entrypoint,
209 const VkSpecializationInfo *tcs_spec_info,
210 const VkSpecializationInfo *tes_spec_info,
211 struct radv_pipeline_layout *layout,
212 unsigned input_vertices,
213 bool has_view_index)
214 {
215 unsigned char tcs_sha1[20], tes_sha1[20];
216 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
217 nir_shader *tes_nir, *tcs_nir;
218 void *tes_code = NULL, *tcs_code = NULL;
219 unsigned tes_code_size = 0, tcs_code_size = 0;
220 struct ac_shader_variant_key tes_key;
221 struct ac_shader_variant_key tcs_key;
222
223 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
224 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
225 tes_key.has_multiview_view_index = has_view_index;
226 if (tes_module->nir)
227 _mesa_sha1_compute(tes_module->nir->info.name,
228 strlen(tes_module->nir->info.name),
229 tes_module->sha1);
230 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
231
232 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
233 cache,
234 tes_sha1);
235
236 if (tes_variant) {
237 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
238
239 if (tcs_module->nir)
240 _mesa_sha1_compute(tcs_module->nir->info.name,
241 strlen(tcs_module->nir->info.name),
242 tcs_module->sha1);
243
244 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
245
246 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
247 cache,
248 tcs_sha1);
249 }
250
251 if (tcs_variant && tes_variant) {
252 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
253 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
254 return;
255 }
256
257 tes_nir = radv_shader_compile_to_nir(pipeline->device,
258 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
259 tes_spec_info);
260 if (tes_nir == NULL)
261 return;
262
263 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
264 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
265 tcs_spec_info);
266 if (tcs_nir == NULL)
267 return;
268
269 tes_nir->info.tess.ccw = !tes_nir->info.tess.ccw;
270 nir_lower_tes_patch_vertices(tes_nir,
271 tcs_nir->info.tess.tcs_vertices_out);
272
273 tes_variant = radv_shader_variant_create(pipeline->device, tes_module, tes_nir,
274 layout, &tes_key, &tes_code,
275 &tes_code_size);
276
277 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
278 if (tcs_module->nir)
279 _mesa_sha1_compute(tcs_module->nir->info.name,
280 strlen(tcs_module->nir->info.name),
281 tcs_module->sha1);
282
283 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
284
285 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_module, tcs_nir,
286 layout, &tcs_key, &tcs_code,
287 &tcs_code_size);
288
289 if (!tes_module->nir && !pipeline->device->trace_bo)
290 ralloc_free(tes_nir);
291
292 if (!tcs_module->nir && !pipeline->device->trace_bo)
293 ralloc_free(tcs_nir);
294
295 if (tes_variant)
296 tes_variant = radv_pipeline_cache_insert_shader(pipeline->device, cache, tes_sha1, tes_variant,
297 tes_code, tes_code_size);
298
299 if (tcs_variant)
300 tcs_variant = radv_pipeline_cache_insert_shader(pipeline->device, cache, tcs_sha1, tcs_variant,
301 tcs_code, tcs_code_size);
302
303 if (tes_code)
304 free(tes_code);
305 if (tcs_code)
306 free(tcs_code);
307 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
308 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
309 return;
310 }
311
312 static VkResult
313 radv_pipeline_scratch_init(struct radv_device *device,
314 struct radv_pipeline *pipeline)
315 {
316 unsigned scratch_bytes_per_wave = 0;
317 unsigned max_waves = 0;
318 unsigned min_waves = 1;
319
320 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
321 if (pipeline->shaders[i]) {
322 unsigned max_stage_waves = device->scratch_waves;
323
324 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
325 pipeline->shaders[i]->config.scratch_bytes_per_wave);
326
327 max_stage_waves = MIN2(max_stage_waves,
328 4 * device->physical_device->rad_info.num_good_compute_units *
329 (256 / pipeline->shaders[i]->config.num_vgprs));
330 max_waves = MAX2(max_waves, max_stage_waves);
331 }
332 }
333
334 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
335 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
336 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
337 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
338 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
339 }
340
341 if (scratch_bytes_per_wave)
342 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
343
344 if (scratch_bytes_per_wave && max_waves < min_waves) {
345 /* Not really true at this moment, but will be true on first
346 * execution. Avoid having hanging shaders. */
347 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
348 }
349 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
350 pipeline->max_waves = max_waves;
351 return VK_SUCCESS;
352 }
353
354 static uint32_t si_translate_blend_function(VkBlendOp op)
355 {
356 switch (op) {
357 case VK_BLEND_OP_ADD:
358 return V_028780_COMB_DST_PLUS_SRC;
359 case VK_BLEND_OP_SUBTRACT:
360 return V_028780_COMB_SRC_MINUS_DST;
361 case VK_BLEND_OP_REVERSE_SUBTRACT:
362 return V_028780_COMB_DST_MINUS_SRC;
363 case VK_BLEND_OP_MIN:
364 return V_028780_COMB_MIN_DST_SRC;
365 case VK_BLEND_OP_MAX:
366 return V_028780_COMB_MAX_DST_SRC;
367 default:
368 return 0;
369 }
370 }
371
372 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
373 {
374 switch (factor) {
375 case VK_BLEND_FACTOR_ZERO:
376 return V_028780_BLEND_ZERO;
377 case VK_BLEND_FACTOR_ONE:
378 return V_028780_BLEND_ONE;
379 case VK_BLEND_FACTOR_SRC_COLOR:
380 return V_028780_BLEND_SRC_COLOR;
381 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
382 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
383 case VK_BLEND_FACTOR_DST_COLOR:
384 return V_028780_BLEND_DST_COLOR;
385 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
386 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
387 case VK_BLEND_FACTOR_SRC_ALPHA:
388 return V_028780_BLEND_SRC_ALPHA;
389 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
390 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
391 case VK_BLEND_FACTOR_DST_ALPHA:
392 return V_028780_BLEND_DST_ALPHA;
393 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
394 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
395 case VK_BLEND_FACTOR_CONSTANT_COLOR:
396 return V_028780_BLEND_CONSTANT_COLOR;
397 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
398 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
399 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
400 return V_028780_BLEND_CONSTANT_ALPHA;
401 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
402 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
403 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
404 return V_028780_BLEND_SRC_ALPHA_SATURATE;
405 case VK_BLEND_FACTOR_SRC1_COLOR:
406 return V_028780_BLEND_SRC1_COLOR;
407 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
408 return V_028780_BLEND_INV_SRC1_COLOR;
409 case VK_BLEND_FACTOR_SRC1_ALPHA:
410 return V_028780_BLEND_SRC1_ALPHA;
411 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
412 return V_028780_BLEND_INV_SRC1_ALPHA;
413 default:
414 return 0;
415 }
416 }
417
418 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
419 {
420 switch (op) {
421 case VK_BLEND_OP_ADD:
422 return V_028760_OPT_COMB_ADD;
423 case VK_BLEND_OP_SUBTRACT:
424 return V_028760_OPT_COMB_SUBTRACT;
425 case VK_BLEND_OP_REVERSE_SUBTRACT:
426 return V_028760_OPT_COMB_REVSUBTRACT;
427 case VK_BLEND_OP_MIN:
428 return V_028760_OPT_COMB_MIN;
429 case VK_BLEND_OP_MAX:
430 return V_028760_OPT_COMB_MAX;
431 default:
432 return V_028760_OPT_COMB_BLEND_DISABLED;
433 }
434 }
435
436 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
437 {
438 switch (factor) {
439 case VK_BLEND_FACTOR_ZERO:
440 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
441 case VK_BLEND_FACTOR_ONE:
442 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
443 case VK_BLEND_FACTOR_SRC_COLOR:
444 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
445 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
446 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
447 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
448 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
449 case VK_BLEND_FACTOR_SRC_ALPHA:
450 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
452 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
453 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
454 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
455 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
456 default:
457 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
458 }
459 }
460
461 /**
462 * Get rid of DST in the blend factors by commuting the operands:
463 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
464 */
465 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
466 unsigned *dst_factor, unsigned expected_dst,
467 unsigned replacement_src)
468 {
469 if (*src_factor == expected_dst &&
470 *dst_factor == VK_BLEND_FACTOR_ZERO) {
471 *src_factor = VK_BLEND_FACTOR_ZERO;
472 *dst_factor = replacement_src;
473
474 /* Commuting the operands requires reversing subtractions. */
475 if (*func == VK_BLEND_OP_SUBTRACT)
476 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
477 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
478 *func = VK_BLEND_OP_SUBTRACT;
479 }
480 }
481
482 static bool si_blend_factor_uses_dst(unsigned factor)
483 {
484 return factor == VK_BLEND_FACTOR_DST_COLOR ||
485 factor == VK_BLEND_FACTOR_DST_ALPHA ||
486 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
487 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
488 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
489 }
490
491 static bool is_dual_src(VkBlendFactor factor)
492 {
493 switch (factor) {
494 case VK_BLEND_FACTOR_SRC1_COLOR:
495 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
496 case VK_BLEND_FACTOR_SRC1_ALPHA:
497 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
498 return true;
499 default:
500 return false;
501 }
502 }
503
504 static unsigned si_choose_spi_color_format(VkFormat vk_format,
505 bool blend_enable,
506 bool blend_need_alpha)
507 {
508 const struct vk_format_description *desc = vk_format_description(vk_format);
509 unsigned format, ntype, swap;
510
511 /* Alpha is needed for alpha-to-coverage.
512 * Blending may be with or without alpha.
513 */
514 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
515 unsigned alpha = 0; /* exports alpha, but may not support blending */
516 unsigned blend = 0; /* supports blending, but may not export alpha */
517 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
518
519 format = radv_translate_colorformat(vk_format);
520 ntype = radv_translate_color_numformat(vk_format, desc,
521 vk_format_get_first_non_void_channel(vk_format));
522 swap = radv_translate_colorswap(vk_format, false);
523
524 /* Choose the SPI color formats. These are required values for Stoney/RB+.
525 * Other chips have multiple choices, though they are not necessarily better.
526 */
527 switch (format) {
528 case V_028C70_COLOR_5_6_5:
529 case V_028C70_COLOR_1_5_5_5:
530 case V_028C70_COLOR_5_5_5_1:
531 case V_028C70_COLOR_4_4_4_4:
532 case V_028C70_COLOR_10_11_11:
533 case V_028C70_COLOR_11_11_10:
534 case V_028C70_COLOR_8:
535 case V_028C70_COLOR_8_8:
536 case V_028C70_COLOR_8_8_8_8:
537 case V_028C70_COLOR_10_10_10_2:
538 case V_028C70_COLOR_2_10_10_10:
539 if (ntype == V_028C70_NUMBER_UINT)
540 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
541 else if (ntype == V_028C70_NUMBER_SINT)
542 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
543 else
544 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
545 break;
546
547 case V_028C70_COLOR_16:
548 case V_028C70_COLOR_16_16:
549 case V_028C70_COLOR_16_16_16_16:
550 if (ntype == V_028C70_NUMBER_UNORM ||
551 ntype == V_028C70_NUMBER_SNORM) {
552 /* UNORM16 and SNORM16 don't support blending */
553 if (ntype == V_028C70_NUMBER_UNORM)
554 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
555 else
556 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
557
558 /* Use 32 bits per channel for blending. */
559 if (format == V_028C70_COLOR_16) {
560 if (swap == V_028C70_SWAP_STD) { /* R */
561 blend = V_028714_SPI_SHADER_32_R;
562 blend_alpha = V_028714_SPI_SHADER_32_AR;
563 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
564 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
565 else
566 assert(0);
567 } else if (format == V_028C70_COLOR_16_16) {
568 if (swap == V_028C70_SWAP_STD) { /* RG */
569 blend = V_028714_SPI_SHADER_32_GR;
570 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
571 } else if (swap == V_028C70_SWAP_ALT) /* RA */
572 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
573 else
574 assert(0);
575 } else /* 16_16_16_16 */
576 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
577 } else if (ntype == V_028C70_NUMBER_UINT)
578 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
579 else if (ntype == V_028C70_NUMBER_SINT)
580 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
581 else if (ntype == V_028C70_NUMBER_FLOAT)
582 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
583 else
584 assert(0);
585 break;
586
587 case V_028C70_COLOR_32:
588 if (swap == V_028C70_SWAP_STD) { /* R */
589 blend = normal = V_028714_SPI_SHADER_32_R;
590 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
591 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
592 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
593 else
594 assert(0);
595 break;
596
597 case V_028C70_COLOR_32_32:
598 if (swap == V_028C70_SWAP_STD) { /* RG */
599 blend = normal = V_028714_SPI_SHADER_32_GR;
600 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
601 } else if (swap == V_028C70_SWAP_ALT) /* RA */
602 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
603 else
604 assert(0);
605 break;
606
607 case V_028C70_COLOR_32_32_32_32:
608 case V_028C70_COLOR_8_24:
609 case V_028C70_COLOR_24_8:
610 case V_028C70_COLOR_X24_8_32_FLOAT:
611 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
612 break;
613
614 default:
615 unreachable("unhandled blend format");
616 }
617
618 if (blend_enable && blend_need_alpha)
619 return blend_alpha;
620 else if(blend_need_alpha)
621 return alpha;
622 else if(blend_enable)
623 return blend;
624 else
625 return normal;
626 }
627
628 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
629 {
630 unsigned i, cb_shader_mask = 0;
631
632 for (i = 0; i < 8; i++) {
633 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
634 case V_028714_SPI_SHADER_ZERO:
635 break;
636 case V_028714_SPI_SHADER_32_R:
637 cb_shader_mask |= 0x1 << (i * 4);
638 break;
639 case V_028714_SPI_SHADER_32_GR:
640 cb_shader_mask |= 0x3 << (i * 4);
641 break;
642 case V_028714_SPI_SHADER_32_AR:
643 cb_shader_mask |= 0x9 << (i * 4);
644 break;
645 case V_028714_SPI_SHADER_FP16_ABGR:
646 case V_028714_SPI_SHADER_UNORM16_ABGR:
647 case V_028714_SPI_SHADER_SNORM16_ABGR:
648 case V_028714_SPI_SHADER_UINT16_ABGR:
649 case V_028714_SPI_SHADER_SINT16_ABGR:
650 case V_028714_SPI_SHADER_32_ABGR:
651 cb_shader_mask |= 0xf << (i * 4);
652 break;
653 default:
654 assert(0);
655 }
656 }
657 return cb_shader_mask;
658 }
659
660 static void
661 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
662 const VkGraphicsPipelineCreateInfo *pCreateInfo,
663 uint32_t blend_enable,
664 uint32_t blend_need_alpha,
665 bool single_cb_enable,
666 bool blend_mrt0_is_dual_src)
667 {
668 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
669 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
670 struct radv_blend_state *blend = &pipeline->graphics.blend;
671 unsigned col_format = 0;
672
673 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
674 unsigned cf;
675
676 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
677 cf = V_028714_SPI_SHADER_ZERO;
678 } else {
679 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
680
681 cf = si_choose_spi_color_format(attachment->format,
682 blend_enable & (1 << i),
683 blend_need_alpha & (1 << i));
684 }
685
686 col_format |= cf << (4 * i);
687 }
688
689 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
690
691 if (blend_mrt0_is_dual_src)
692 col_format |= (col_format & 0xf) << 4;
693 blend->spi_shader_col_format = col_format;
694 }
695
696 static bool
697 format_is_int8(VkFormat format)
698 {
699 const struct vk_format_description *desc = vk_format_description(format);
700 int channel = vk_format_get_first_non_void_channel(format);
701
702 return channel >= 0 && desc->channel[channel].pure_integer &&
703 desc->channel[channel].size == 8;
704 }
705
706 static bool
707 format_is_int10(VkFormat format)
708 {
709 const struct vk_format_description *desc = vk_format_description(format);
710
711 if (desc->nr_channels != 4)
712 return false;
713 for (unsigned i = 0; i < 4; i++) {
714 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
715 return true;
716 }
717 return false;
718 }
719
720 unsigned radv_format_meta_fs_key(VkFormat format)
721 {
722 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
723 bool is_int8 = format_is_int8(format);
724 bool is_int10 = format_is_int10(format);
725
726 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
727 }
728
729 static void
730 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
731 unsigned *is_int8, unsigned *is_int10)
732 {
733 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
734 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
735 *is_int8 = 0;
736 *is_int10 = 0;
737
738 for (unsigned i = 0; i < subpass->color_count; ++i) {
739 struct radv_render_pass_attachment *attachment;
740
741 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
742 continue;
743
744 attachment = pass->attachments + subpass->color_attachments[i].attachment;
745
746 if (format_is_int8(attachment->format))
747 *is_int8 |= 1 << i;
748 if (format_is_int10(attachment->format))
749 *is_int10 |= 1 << i;
750 }
751 }
752
753 static void
754 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
755 const VkGraphicsPipelineCreateInfo *pCreateInfo,
756 const struct radv_graphics_pipeline_create_info *extra)
757 {
758 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
759 struct radv_blend_state *blend = &pipeline->graphics.blend;
760 unsigned mode = V_028808_CB_NORMAL;
761 uint32_t blend_enable = 0, blend_need_alpha = 0;
762 bool blend_mrt0_is_dual_src = false;
763 int i;
764 bool single_cb_enable = false;
765
766 if (!vkblend)
767 return;
768
769 if (extra && extra->custom_blend_mode) {
770 single_cb_enable = true;
771 mode = extra->custom_blend_mode;
772 }
773 blend->cb_color_control = 0;
774 if (vkblend->logicOpEnable)
775 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
776 else
777 blend->cb_color_control |= S_028808_ROP3(0xcc);
778
779 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
780 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
781 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
782 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
783
784 blend->cb_target_mask = 0;
785 for (i = 0; i < vkblend->attachmentCount; i++) {
786 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
787 unsigned blend_cntl = 0;
788 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
789 VkBlendOp eqRGB = att->colorBlendOp;
790 VkBlendFactor srcRGB = att->srcColorBlendFactor;
791 VkBlendFactor dstRGB = att->dstColorBlendFactor;
792 VkBlendOp eqA = att->alphaBlendOp;
793 VkBlendFactor srcA = att->srcAlphaBlendFactor;
794 VkBlendFactor dstA = att->dstAlphaBlendFactor;
795
796 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
797
798 if (!att->colorWriteMask)
799 continue;
800
801 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
802 if (!att->blendEnable) {
803 blend->cb_blend_control[i] = blend_cntl;
804 continue;
805 }
806
807 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
808 if (i == 0)
809 blend_mrt0_is_dual_src = true;
810
811 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
812 srcRGB = VK_BLEND_FACTOR_ONE;
813 dstRGB = VK_BLEND_FACTOR_ONE;
814 }
815 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
816 srcA = VK_BLEND_FACTOR_ONE;
817 dstA = VK_BLEND_FACTOR_ONE;
818 }
819
820 /* Blending optimizations for RB+.
821 * These transformations don't change the behavior.
822 *
823 * First, get rid of DST in the blend factors:
824 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
825 */
826 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
827 VK_BLEND_FACTOR_DST_COLOR,
828 VK_BLEND_FACTOR_SRC_COLOR);
829
830 si_blend_remove_dst(&eqA, &srcA, &dstA,
831 VK_BLEND_FACTOR_DST_COLOR,
832 VK_BLEND_FACTOR_SRC_COLOR);
833
834 si_blend_remove_dst(&eqA, &srcA, &dstA,
835 VK_BLEND_FACTOR_DST_ALPHA,
836 VK_BLEND_FACTOR_SRC_ALPHA);
837
838 /* Look up the ideal settings from tables. */
839 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
840 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
841 srcA_opt = si_translate_blend_opt_factor(srcA, true);
842 dstA_opt = si_translate_blend_opt_factor(dstA, true);
843
844 /* Handle interdependencies. */
845 if (si_blend_factor_uses_dst(srcRGB))
846 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
847 if (si_blend_factor_uses_dst(srcA))
848 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
849
850 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
851 (dstRGB == VK_BLEND_FACTOR_ZERO ||
852 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
853 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
854 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
855
856 /* Set the final value. */
857 blend->sx_mrt_blend_opt[i] =
858 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
859 S_028760_COLOR_DST_OPT(dstRGB_opt) |
860 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
861 S_028760_ALPHA_SRC_OPT(srcA_opt) |
862 S_028760_ALPHA_DST_OPT(dstA_opt) |
863 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
864 blend_cntl |= S_028780_ENABLE(1);
865
866 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
867 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
868 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
869 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
870 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
871 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
872 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
873 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
874 }
875 blend->cb_blend_control[i] = blend_cntl;
876
877 blend_enable |= 1 << i;
878
879 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
880 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
881 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
882 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
883 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
884 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
885 blend_need_alpha |= 1 << i;
886 }
887 for (i = vkblend->attachmentCount; i < 8; i++) {
888 blend->cb_blend_control[i] = 0;
889 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
890 }
891
892 /* disable RB+ for now */
893 if (pipeline->device->physical_device->has_rbplus)
894 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
895
896 if (blend->cb_target_mask)
897 blend->cb_color_control |= S_028808_MODE(mode);
898 else
899 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
900
901 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
902 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
903 }
904
905 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
906 {
907 switch (op) {
908 case VK_STENCIL_OP_KEEP:
909 return V_02842C_STENCIL_KEEP;
910 case VK_STENCIL_OP_ZERO:
911 return V_02842C_STENCIL_ZERO;
912 case VK_STENCIL_OP_REPLACE:
913 return V_02842C_STENCIL_REPLACE_TEST;
914 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
915 return V_02842C_STENCIL_ADD_CLAMP;
916 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
917 return V_02842C_STENCIL_SUB_CLAMP;
918 case VK_STENCIL_OP_INVERT:
919 return V_02842C_STENCIL_INVERT;
920 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
921 return V_02842C_STENCIL_ADD_WRAP;
922 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
923 return V_02842C_STENCIL_SUB_WRAP;
924 default:
925 return 0;
926 }
927 }
928 static void
929 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
930 const VkGraphicsPipelineCreateInfo *pCreateInfo,
931 const struct radv_graphics_pipeline_create_info *extra)
932 {
933 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
934 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
935
936 memset(ds, 0, sizeof(*ds));
937 if (!vkds)
938 return;
939
940 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
941 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
942 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
943 return;
944
945 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
946 bool has_depth_attachment = vk_format_is_depth(attachment->format);
947 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
948
949 if (has_depth_attachment) {
950 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
951 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
952 S_028800_ZFUNC(vkds->depthCompareOp) |
953 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
954 }
955
956 if (has_stencil_attachment && vkds->stencilTestEnable) {
957 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
958 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
959 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
960 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
961 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
962
963 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
964 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
965 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
966 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
967 }
968
969 if (extra) {
970
971 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
972 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
973
974 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
975 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
976 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
977 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
978 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
979 }
980 }
981
982 static uint32_t si_translate_fill(VkPolygonMode func)
983 {
984 switch(func) {
985 case VK_POLYGON_MODE_FILL:
986 return V_028814_X_DRAW_TRIANGLES;
987 case VK_POLYGON_MODE_LINE:
988 return V_028814_X_DRAW_LINES;
989 case VK_POLYGON_MODE_POINT:
990 return V_028814_X_DRAW_POINTS;
991 default:
992 assert(0);
993 return V_028814_X_DRAW_POINTS;
994 }
995 }
996 static void
997 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
998 const VkGraphicsPipelineCreateInfo *pCreateInfo)
999 {
1000 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1001 struct radv_raster_state *raster = &pipeline->graphics.raster;
1002
1003 memset(raster, 0, sizeof(*raster));
1004
1005 raster->spi_interp_control =
1006 S_0286D4_FLAT_SHADE_ENA(1) |
1007 S_0286D4_PNT_SPRITE_ENA(1) |
1008 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1009 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1010 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1011 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1012 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1013
1014
1015 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1016 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1017 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1018 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1019 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1020 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1021
1022 raster->pa_su_vtx_cntl =
1023 S_028BE4_PIX_CENTER(1) | // TODO verify
1024 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1025 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1026
1027 raster->pa_su_sc_mode_cntl =
1028 S_028814_FACE(vkraster->frontFace) |
1029 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1030 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1031 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1032 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1033 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1034 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1035 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1036 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1037
1038 }
1039
1040 static void
1041 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1042 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1043 {
1044 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1045 struct radv_blend_state *blend = &pipeline->graphics.blend;
1046 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1047 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1048 int ps_iter_samples = 1;
1049 uint32_t mask = 0xffff;
1050
1051 if (vkms)
1052 ms->num_samples = vkms->rasterizationSamples;
1053 else
1054 ms->num_samples = 1;
1055
1056 if (vkms && vkms->sampleShadingEnable) {
1057 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1058 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1059 ps_iter_samples = ms->num_samples;
1060 }
1061
1062 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1063 ms->pa_sc_aa_config = 0;
1064 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1065 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1066 ms->pa_sc_mode_cntl_1 =
1067 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1068 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1069 /* always 1: */
1070 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1071 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1072 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1073 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1074 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1075 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1076 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1077
1078 if (ms->num_samples > 1) {
1079 unsigned log_samples = util_logbase2(ms->num_samples);
1080 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1081 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1082 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1083 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1084 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1085 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1086 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1087 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1088 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1089 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1090 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1091 }
1092
1093 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1094 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1095 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1096 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1097 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1098 }
1099
1100 if (vkms) {
1101 if (vkms->alphaToCoverageEnable)
1102 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1103
1104 if (vkms->pSampleMask)
1105 mask = vkms->pSampleMask[0] & 0xffff;
1106 }
1107
1108 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1109 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1110 }
1111
1112 static bool
1113 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1114 {
1115 switch (topology) {
1116 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1117 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1118 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1119 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1120 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1121 return false;
1122 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1123 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1124 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1125 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1126 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1127 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1128 return true;
1129 default:
1130 unreachable("unhandled primitive type");
1131 }
1132 }
1133
1134 static uint32_t
1135 si_translate_prim(enum VkPrimitiveTopology topology)
1136 {
1137 switch (topology) {
1138 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1139 return V_008958_DI_PT_POINTLIST;
1140 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1141 return V_008958_DI_PT_LINELIST;
1142 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1143 return V_008958_DI_PT_LINESTRIP;
1144 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1145 return V_008958_DI_PT_TRILIST;
1146 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1147 return V_008958_DI_PT_TRISTRIP;
1148 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1149 return V_008958_DI_PT_TRIFAN;
1150 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1151 return V_008958_DI_PT_LINELIST_ADJ;
1152 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1153 return V_008958_DI_PT_LINESTRIP_ADJ;
1154 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1155 return V_008958_DI_PT_TRILIST_ADJ;
1156 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1157 return V_008958_DI_PT_TRISTRIP_ADJ;
1158 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1159 return V_008958_DI_PT_PATCH;
1160 default:
1161 assert(0);
1162 return 0;
1163 }
1164 }
1165
1166 static uint32_t
1167 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1168 {
1169 switch (gl_prim) {
1170 case 0: /* GL_POINTS */
1171 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1172 case 1: /* GL_LINES */
1173 case 3: /* GL_LINE_STRIP */
1174 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1175 case 0x8E7A: /* GL_ISOLINES */
1176 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1177
1178 case 4: /* GL_TRIANGLES */
1179 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1180 case 5: /* GL_TRIANGLE_STRIP */
1181 case 7: /* GL_QUADS */
1182 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1183 default:
1184 assert(0);
1185 return 0;
1186 }
1187 }
1188
1189 static uint32_t
1190 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1191 {
1192 switch (topology) {
1193 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1194 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1195 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1200 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1206 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1207 default:
1208 assert(0);
1209 return 0;
1210 }
1211 }
1212
1213 static unsigned si_map_swizzle(unsigned swizzle)
1214 {
1215 switch (swizzle) {
1216 case VK_SWIZZLE_Y:
1217 return V_008F0C_SQ_SEL_Y;
1218 case VK_SWIZZLE_Z:
1219 return V_008F0C_SQ_SEL_Z;
1220 case VK_SWIZZLE_W:
1221 return V_008F0C_SQ_SEL_W;
1222 case VK_SWIZZLE_0:
1223 return V_008F0C_SQ_SEL_0;
1224 case VK_SWIZZLE_1:
1225 return V_008F0C_SQ_SEL_1;
1226 default: /* VK_SWIZZLE_X */
1227 return V_008F0C_SQ_SEL_X;
1228 }
1229 }
1230
1231 static void
1232 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1233 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1234 {
1235 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1236 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1237 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1238
1239 pipeline->dynamic_state = default_dynamic_state;
1240
1241 if (pCreateInfo->pDynamicState) {
1242 /* Remove all of the states that are marked as dynamic */
1243 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1244 for (uint32_t s = 0; s < count; s++)
1245 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1246 }
1247
1248 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1249
1250 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1251 *
1252 * pViewportState is [...] NULL if the pipeline
1253 * has rasterization disabled.
1254 */
1255 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1256 assert(pCreateInfo->pViewportState);
1257
1258 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1259 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1260 typed_memcpy(dynamic->viewport.viewports,
1261 pCreateInfo->pViewportState->pViewports,
1262 pCreateInfo->pViewportState->viewportCount);
1263 }
1264
1265 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1266 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1267 typed_memcpy(dynamic->scissor.scissors,
1268 pCreateInfo->pViewportState->pScissors,
1269 pCreateInfo->pViewportState->scissorCount);
1270 }
1271 }
1272
1273 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1274 assert(pCreateInfo->pRasterizationState);
1275 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1276 }
1277
1278 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1279 assert(pCreateInfo->pRasterizationState);
1280 dynamic->depth_bias.bias =
1281 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1282 dynamic->depth_bias.clamp =
1283 pCreateInfo->pRasterizationState->depthBiasClamp;
1284 dynamic->depth_bias.slope =
1285 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1286 }
1287
1288 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1289 *
1290 * pColorBlendState is [...] NULL if the pipeline has rasterization
1291 * disabled or if the subpass of the render pass the pipeline is
1292 * created against does not use any color attachments.
1293 */
1294 bool uses_color_att = false;
1295 for (unsigned i = 0; i < subpass->color_count; ++i) {
1296 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1297 uses_color_att = true;
1298 break;
1299 }
1300 }
1301
1302 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1303 assert(pCreateInfo->pColorBlendState);
1304 typed_memcpy(dynamic->blend_constants,
1305 pCreateInfo->pColorBlendState->blendConstants, 4);
1306 }
1307
1308 /* If there is no depthstencil attachment, then don't read
1309 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1310 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1311 * no need to override the depthstencil defaults in
1312 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1313 *
1314 * Section 9.2 of the Vulkan 1.0.15 spec says:
1315 *
1316 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1317 * disabled or if the subpass of the render pass the pipeline is created
1318 * against does not use a depth/stencil attachment.
1319 */
1320 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1321 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1322 assert(pCreateInfo->pDepthStencilState);
1323
1324 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1325 dynamic->depth_bounds.min =
1326 pCreateInfo->pDepthStencilState->minDepthBounds;
1327 dynamic->depth_bounds.max =
1328 pCreateInfo->pDepthStencilState->maxDepthBounds;
1329 }
1330
1331 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1332 dynamic->stencil_compare_mask.front =
1333 pCreateInfo->pDepthStencilState->front.compareMask;
1334 dynamic->stencil_compare_mask.back =
1335 pCreateInfo->pDepthStencilState->back.compareMask;
1336 }
1337
1338 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1339 dynamic->stencil_write_mask.front =
1340 pCreateInfo->pDepthStencilState->front.writeMask;
1341 dynamic->stencil_write_mask.back =
1342 pCreateInfo->pDepthStencilState->back.writeMask;
1343 }
1344
1345 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1346 dynamic->stencil_reference.front =
1347 pCreateInfo->pDepthStencilState->front.reference;
1348 dynamic->stencil_reference.back =
1349 pCreateInfo->pDepthStencilState->back.reference;
1350 }
1351 }
1352
1353 pipeline->dynamic_state_mask = states;
1354 }
1355
1356 static struct ac_shader_variant_key
1357 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1358 {
1359 struct ac_shader_variant_key key;
1360 const VkPipelineVertexInputStateCreateInfo *input_state =
1361 pCreateInfo->pVertexInputState;
1362
1363 memset(&key, 0, sizeof(key));
1364 key.vs.instance_rate_inputs = 0;
1365 key.vs.as_es = as_es;
1366 key.vs.as_ls = as_ls;
1367 key.vs.export_prim_id = export_prim_id;
1368
1369 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1370 unsigned binding;
1371 binding = input_state->pVertexAttributeDescriptions[i].binding;
1372 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1373 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1374 }
1375 return key;
1376 }
1377
1378 static void
1379 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1380 {
1381 struct radv_device *device = pipeline->device;
1382 unsigned num_se = device->physical_device->rad_info.max_se;
1383 unsigned wave_size = 64;
1384 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1385 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1386 unsigned alignment = 256 * num_se;
1387 /* The maximum size is 63.999 MB per SE. */
1388 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1389 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1390 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1391 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1392 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1393
1394 /* Calculate the minimum size. */
1395 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1396 wave_size, alignment);
1397 /* These are recommended sizes, not minimum sizes. */
1398 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1399 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1400 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1401 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1402
1403 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1404 esgs_ring_size = align(esgs_ring_size, alignment);
1405 gsvs_ring_size = align(gsvs_ring_size, alignment);
1406
1407 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1408 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1409 }
1410
1411 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1412 unsigned *lds_size)
1413 {
1414 /* SPI barrier management bug:
1415 * Make sure we have at least 4k of LDS in use to avoid the bug.
1416 * It applies to workgroup sizes of more than one wavefront.
1417 */
1418 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1419 device->physical_device->rad_info.family == CHIP_KABINI ||
1420 device->physical_device->rad_info.family == CHIP_MULLINS)
1421 *lds_size = MAX2(*lds_size, 8);
1422 }
1423
1424 static void
1425 calculate_tess_state(struct radv_pipeline *pipeline,
1426 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1427 {
1428 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1429 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1430 unsigned num_tcs_patch_outputs;
1431 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1432 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1433 unsigned lds_size, hardware_lds_size;
1434 unsigned perpatch_output_offset;
1435 unsigned num_patches;
1436 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1437
1438 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1439 * are laid out in LDS. */
1440 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1441
1442 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1443 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1444 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1445
1446 /* Ensure that we only need one wave per SIMD so we don't need to check
1447 * resource usage. Also ensures that the number of tcs in and out
1448 * vertices per threadgroup are at most 256.
1449 */
1450 input_vertex_size = num_tcs_inputs * 16;
1451 output_vertex_size = num_tcs_outputs * 16;
1452
1453 input_patch_size = num_tcs_input_cp * input_vertex_size;
1454
1455 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1456 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1457 /* Ensure that we only need one wave per SIMD so we don't need to check
1458 * resource usage. Also ensures that the number of tcs in and out
1459 * vertices per threadgroup are at most 256.
1460 */
1461 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1462
1463 /* Make sure that the data fits in LDS. This assumes the shaders only
1464 * use LDS for the inputs and outputs.
1465 */
1466 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1467 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1468
1469 /* Make sure the output data fits in the offchip buffer */
1470 num_patches = MIN2(num_patches,
1471 (pipeline->device->tess_offchip_block_dw_size * 4) /
1472 output_patch_size);
1473
1474 /* Not necessary for correctness, but improves performance. The
1475 * specific value is taken from the proprietary driver.
1476 */
1477 num_patches = MIN2(num_patches, 40);
1478
1479 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1480 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1481 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1482 num_patches = MIN2(num_patches, one_wave);
1483 }
1484
1485 output_patch0_offset = input_patch_size * num_patches;
1486 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1487
1488 lds_size = output_patch0_offset + output_patch_size * num_patches;
1489
1490 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1491 assert(lds_size <= 65536);
1492 lds_size = align(lds_size, 512) / 512;
1493 } else {
1494 assert(lds_size <= 32768);
1495 lds_size = align(lds_size, 256) / 256;
1496 }
1497 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1498
1499 tess->lds_size = lds_size;
1500
1501 tess->tcs_in_layout = (input_patch_size / 4) |
1502 ((input_vertex_size / 4) << 13);
1503 tess->tcs_out_layout = (output_patch_size / 4) |
1504 ((output_vertex_size / 4) << 13);
1505 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1506 ((perpatch_output_offset / 16) << 16);
1507 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1508 (num_tcs_output_cp << 9) | num_patches;
1509
1510 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1511 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1512 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1513 tess->num_patches = num_patches;
1514 tess->num_tcs_input_cp = num_tcs_input_cp;
1515
1516 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1517 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1518
1519 switch (tes->info.tes.primitive_mode) {
1520 case GL_TRIANGLES:
1521 type = V_028B6C_TESS_TRIANGLE;
1522 break;
1523 case GL_QUADS:
1524 type = V_028B6C_TESS_QUAD;
1525 break;
1526 case GL_ISOLINES:
1527 type = V_028B6C_TESS_ISOLINE;
1528 break;
1529 }
1530
1531 switch (tes->info.tes.spacing) {
1532 case TESS_SPACING_EQUAL:
1533 partitioning = V_028B6C_PART_INTEGER;
1534 break;
1535 case TESS_SPACING_FRACTIONAL_ODD:
1536 partitioning = V_028B6C_PART_FRAC_ODD;
1537 break;
1538 case TESS_SPACING_FRACTIONAL_EVEN:
1539 partitioning = V_028B6C_PART_FRAC_EVEN;
1540 break;
1541 default:
1542 break;
1543 }
1544
1545 if (tes->info.tes.point_mode)
1546 topology = V_028B6C_OUTPUT_POINT;
1547 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1548 topology = V_028B6C_OUTPUT_LINE;
1549 else if (tes->info.tes.ccw)
1550 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1551 else
1552 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1553
1554 if (pipeline->device->has_distributed_tess) {
1555 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1556 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1557 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1558 else
1559 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1560 } else
1561 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1562
1563 tess->tf_param = S_028B6C_TYPE(type) |
1564 S_028B6C_PARTITIONING(partitioning) |
1565 S_028B6C_TOPOLOGY(topology) |
1566 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1567 }
1568
1569 static const struct radv_prim_vertex_count prim_size_table[] = {
1570 [V_008958_DI_PT_NONE] = {0, 0},
1571 [V_008958_DI_PT_POINTLIST] = {1, 1},
1572 [V_008958_DI_PT_LINELIST] = {2, 2},
1573 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1574 [V_008958_DI_PT_TRILIST] = {3, 3},
1575 [V_008958_DI_PT_TRIFAN] = {3, 1},
1576 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1577 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1578 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1579 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1580 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1581 [V_008958_DI_PT_RECTLIST] = {3, 3},
1582 [V_008958_DI_PT_LINELOOP] = {2, 1},
1583 [V_008958_DI_PT_POLYGON] = {3, 1},
1584 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1585 };
1586
1587 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1588 {
1589 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1590 unsigned cut_mode;
1591
1592 if (gs_max_vert_out <= 128) {
1593 cut_mode = V_028A40_GS_CUT_128;
1594 } else if (gs_max_vert_out <= 256) {
1595 cut_mode = V_028A40_GS_CUT_256;
1596 } else if (gs_max_vert_out <= 512) {
1597 cut_mode = V_028A40_GS_CUT_512;
1598 } else {
1599 assert(gs_max_vert_out <= 1024);
1600 cut_mode = V_028A40_GS_CUT_1024;
1601 }
1602
1603 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1604 S_028A40_CUT_MODE(cut_mode)|
1605 S_028A40_ES_WRITE_OPTIMIZE(1) |
1606 S_028A40_GS_WRITE_OPTIMIZE(1);
1607 }
1608
1609 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1610 {
1611 struct radv_shader_variant *vs;
1612 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1613
1614 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1615
1616 pipeline->graphics.vgt_primitiveid_en = false;
1617 pipeline->graphics.vgt_gs_mode = 0;
1618
1619 if (radv_pipeline_has_gs(pipeline)) {
1620 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1621 } else if (outinfo->export_prim_id) {
1622 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1623 pipeline->graphics.vgt_primitiveid_en = true;
1624 }
1625 }
1626
1627 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1628 {
1629 struct radv_shader_variant *vs;
1630 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1631
1632 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1633
1634 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1635 clip_dist_mask = outinfo->clip_dist_mask;
1636 cull_dist_mask = outinfo->cull_dist_mask;
1637 total_mask = clip_dist_mask | cull_dist_mask;
1638
1639 bool misc_vec_ena = outinfo->writes_pointsize ||
1640 outinfo->writes_layer ||
1641 outinfo->writes_viewport_index;
1642 pipeline->graphics.pa_cl_vs_out_cntl =
1643 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1644 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1645 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1646 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1647 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1648 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1649 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1650 cull_dist_mask << 8 |
1651 clip_dist_mask;
1652
1653 }
1654
1655 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1656 {
1657 uint32_t ps_input_cntl;
1658 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1659 ps_input_cntl = S_028644_OFFSET(offset);
1660 if (flat_shade)
1661 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1662 } else {
1663 /* The input is a DEFAULT_VAL constant. */
1664 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1665 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1666 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1667 ps_input_cntl = S_028644_OFFSET(0x20) |
1668 S_028644_DEFAULT_VAL(offset);
1669 }
1670 return ps_input_cntl;
1671 }
1672
1673 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1674 {
1675 struct radv_shader_variant *ps, *vs;
1676 struct ac_vs_output_info *outinfo;
1677
1678 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1679 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1680
1681 outinfo = &vs->info.vs.outinfo;
1682
1683 unsigned ps_offset = 0;
1684
1685 if (ps->info.fs.prim_id_input) {
1686 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1687 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1688 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1689 ++ps_offset;
1690 }
1691 }
1692
1693 if (ps->info.fs.layer_input) {
1694 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1695 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1696 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1697 else
1698 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1699 ++ps_offset;
1700 }
1701
1702 if (ps->info.fs.has_pcoord) {
1703 unsigned val;
1704 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1705 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1706 ps_offset++;
1707 }
1708
1709 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1710 unsigned vs_offset;
1711 bool flat_shade;
1712 if (!(ps->info.fs.input_mask & (1u << i)))
1713 continue;
1714
1715 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1716 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1717 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1718 ++ps_offset;
1719 continue;
1720 }
1721
1722 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1723
1724 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1725 ++ps_offset;
1726 }
1727
1728 pipeline->graphics.ps_input_cntl_num = ps_offset;
1729 }
1730
1731 static VkResult
1732 radv_pipeline_init(struct radv_pipeline *pipeline,
1733 struct radv_device *device,
1734 struct radv_pipeline_cache *cache,
1735 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1736 const struct radv_graphics_pipeline_create_info *extra,
1737 const VkAllocationCallbacks *alloc)
1738 {
1739 struct radv_shader_module fs_m = {0};
1740 VkResult result;
1741 bool has_view_index = false;
1742
1743 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1744 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1745 if (subpass->view_mask)
1746 has_view_index = true;
1747 if (alloc == NULL)
1748 alloc = &device->alloc;
1749
1750 pipeline->device = device;
1751 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1752
1753 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1754 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1755 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1756 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1757 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1758 pStages[stage] = &pCreateInfo->pStages[i];
1759 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1760 }
1761
1762 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1763
1764 if (!modules[MESA_SHADER_FRAGMENT]) {
1765 nir_builder fs_b;
1766 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1767 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1768 fs_m.nir = fs_b.shader;
1769 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1770 }
1771
1772 if (modules[MESA_SHADER_FRAGMENT]) {
1773 struct ac_shader_variant_key key = {0};
1774 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1775 if (pCreateInfo->pMultisampleState &&
1776 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1777 key.fs.multisample = true;
1778
1779 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1780 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
1781
1782 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1783
1784 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1785 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1786 stage ? stage->pName : "main",
1787 MESA_SHADER_FRAGMENT,
1788 stage ? stage->pSpecializationInfo : NULL,
1789 pipeline->layout, &key);
1790 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1791 }
1792
1793 if (fs_m.nir)
1794 ralloc_free(fs_m.nir);
1795
1796 if (modules[MESA_SHADER_VERTEX]) {
1797 bool as_es = false;
1798 bool as_ls = false;
1799 bool export_prim_id = false;
1800 if (modules[MESA_SHADER_TESS_CTRL])
1801 as_ls = true;
1802 else if (modules[MESA_SHADER_GEOMETRY])
1803 as_es = true;
1804 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
1805 export_prim_id = true;
1806 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
1807 key.has_multiview_view_index = has_view_index;
1808
1809 pipeline->shaders[MESA_SHADER_VERTEX] =
1810 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1811 pStages[MESA_SHADER_VERTEX]->pName,
1812 MESA_SHADER_VERTEX,
1813 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1814 pipeline->layout, &key);
1815
1816 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1817 }
1818
1819 if (modules[MESA_SHADER_GEOMETRY]) {
1820 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
1821 key.has_multiview_view_index = has_view_index;
1822
1823 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1824 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1825 pStages[MESA_SHADER_GEOMETRY]->pName,
1826 MESA_SHADER_GEOMETRY,
1827 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1828 pipeline->layout, &key);
1829
1830 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1831 }
1832
1833 if (modules[MESA_SHADER_TESS_EVAL]) {
1834 assert(modules[MESA_SHADER_TESS_CTRL]);
1835
1836 radv_tess_pipeline_compile(pipeline,
1837 cache,
1838 modules[MESA_SHADER_TESS_CTRL],
1839 modules[MESA_SHADER_TESS_EVAL],
1840 pStages[MESA_SHADER_TESS_CTRL]->pName,
1841 pStages[MESA_SHADER_TESS_EVAL]->pName,
1842 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1843 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
1844 pipeline->layout,
1845 pCreateInfo->pTessellationState->patchControlPoints,
1846 has_view_index);
1847 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
1848 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
1849 }
1850
1851 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1852 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1853 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1854 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1855 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
1856
1857 if (radv_pipeline_has_gs(pipeline)) {
1858 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1859 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1860 } else {
1861 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1862 }
1863 if (extra && extra->use_rectlist) {
1864 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1865 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1866 pipeline->graphics.can_use_guardband = true;
1867 }
1868 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1869 /* prim vertex count will need TESS changes */
1870 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1871
1872 /* Ensure that some export memory is always allocated, for two reasons:
1873 *
1874 * 1) Correctness: The hardware ignores the EXEC mask if no export
1875 * memory is allocated, so KILL and alpha test do not work correctly
1876 * without this.
1877 * 2) Performance: Every shader needs at least a NULL export, even when
1878 * it writes no color/depth output. The NULL export instruction
1879 * stalls without this setting.
1880 *
1881 * Don't add this to CB_SHADER_MASK.
1882 */
1883 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1884 if (!pipeline->graphics.blend.spi_shader_col_format) {
1885 if (!ps->info.fs.writes_z &&
1886 !ps->info.fs.writes_stencil &&
1887 !ps->info.fs.writes_sample_mask)
1888 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1889 }
1890
1891 unsigned z_order;
1892 pipeline->graphics.db_shader_control = 0;
1893 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1894 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1895 else
1896 z_order = V_02880C_LATE_Z;
1897
1898 pipeline->graphics.db_shader_control =
1899 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1900 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1901 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1902 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1903 S_02880C_Z_ORDER(z_order) |
1904 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1905 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1906 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1907
1908 if (pipeline->device->physical_device->has_rbplus)
1909 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1910
1911 pipeline->graphics.shader_z_format =
1912 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
1913 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
1914 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
1915 V_028710_SPI_SHADER_ZERO;
1916
1917 calculate_vgt_gs_mode(pipeline);
1918 calculate_pa_cl_vs_out_cntl(pipeline);
1919 calculate_ps_inputs(pipeline);
1920
1921 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1922 if (pipeline->shaders[i]) {
1923 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
1924 }
1925 }
1926
1927 uint32_t stages = 0;
1928 if (radv_pipeline_has_tess(pipeline)) {
1929 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1930 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1931
1932 if (radv_pipeline_has_gs(pipeline))
1933 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1934 S_028B54_GS_EN(1) |
1935 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1936 else
1937 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1938
1939 } else if (radv_pipeline_has_gs(pipeline))
1940 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1941 S_028B54_GS_EN(1) |
1942 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1943
1944 if (device->physical_device->rad_info.chip_class >= GFX9)
1945 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1946
1947 pipeline->graphics.vgt_shader_stages_en = stages;
1948
1949 if (radv_pipeline_has_gs(pipeline))
1950 calculate_gs_ring_sizes(pipeline);
1951
1952 if (radv_pipeline_has_tess(pipeline)) {
1953 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
1954 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
1955 pipeline->graphics.prim_vertex_count.incr = 1;
1956 }
1957 calculate_tess_state(pipeline, pCreateInfo);
1958 }
1959
1960 if (radv_pipeline_has_tess(pipeline))
1961 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
1962 else if (radv_pipeline_has_gs(pipeline))
1963 pipeline->graphics.primgroup_size = 64;
1964 else
1965 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
1966
1967 pipeline->graphics.partial_es_wave = false;
1968 if (pipeline->device->has_distributed_tess) {
1969 if (radv_pipeline_has_gs(pipeline)) {
1970 if (device->physical_device->rad_info.chip_class <= VI)
1971 pipeline->graphics.partial_es_wave = true;
1972 }
1973 }
1974 /* GS requirement. */
1975 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
1976 pipeline->graphics.partial_es_wave = true;
1977
1978 pipeline->graphics.wd_switch_on_eop = false;
1979 if (device->physical_device->rad_info.chip_class >= CIK) {
1980 unsigned prim = pipeline->graphics.prim;
1981 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
1982 * 4 shader engines. Set 1 to pass the assertion below.
1983 * The other cases are hardware requirements. */
1984 if (device->physical_device->rad_info.max_se < 4 ||
1985 prim == V_008958_DI_PT_POLYGON ||
1986 prim == V_008958_DI_PT_LINELOOP ||
1987 prim == V_008958_DI_PT_TRIFAN ||
1988 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
1989 (pipeline->graphics.prim_restart_enable &&
1990 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
1991 (prim != V_008958_DI_PT_POINTLIST &&
1992 prim != V_008958_DI_PT_LINESTRIP &&
1993 prim != V_008958_DI_PT_TRISTRIP))))
1994 pipeline->graphics.wd_switch_on_eop = true;
1995 }
1996
1997 pipeline->graphics.ia_switch_on_eoi = false;
1998 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
1999 pipeline->graphics.ia_switch_on_eoi = true;
2000 if (radv_pipeline_has_gs(pipeline) &&
2001 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
2002 pipeline->graphics.ia_switch_on_eoi = true;
2003 if (radv_pipeline_has_tess(pipeline)) {
2004 /* SWITCH_ON_EOI must be set if PrimID is used. */
2005 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
2006 pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
2007 pipeline->graphics.ia_switch_on_eoi = true;
2008 }
2009
2010 pipeline->graphics.partial_vs_wave = false;
2011 if (radv_pipeline_has_tess(pipeline)) {
2012 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2013 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2014 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2015 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2016 radv_pipeline_has_gs(pipeline))
2017 pipeline->graphics.partial_vs_wave = true;
2018 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2019 if (device->has_distributed_tess) {
2020 if (radv_pipeline_has_gs(pipeline)) {
2021 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2022 device->physical_device->rad_info.family == CHIP_FIJI ||
2023 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2024 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2025 device->physical_device->rad_info.family == CHIP_POLARIS12)
2026 pipeline->graphics.partial_vs_wave = true;
2027 } else {
2028 pipeline->graphics.partial_vs_wave = true;
2029 }
2030 }
2031 }
2032
2033 pipeline->graphics.base_ia_multi_vgt_param =
2034 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
2035 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
2036 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
2037 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
2038 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
2039
2040 const VkPipelineVertexInputStateCreateInfo *vi_info =
2041 pCreateInfo->pVertexInputState;
2042 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2043
2044 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2045 const VkVertexInputAttributeDescription *desc =
2046 &vi_info->pVertexAttributeDescriptions[i];
2047 unsigned loc = desc->location;
2048 const struct vk_format_description *format_desc;
2049 int first_non_void;
2050 uint32_t num_format, data_format;
2051 format_desc = vk_format_description(desc->format);
2052 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2053
2054 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2055 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2056
2057 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2058 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2059 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2060 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2061 S_008F0C_NUM_FORMAT(num_format) |
2062 S_008F0C_DATA_FORMAT(data_format);
2063 velems->format_size[loc] = format_desc->block.bits / 8;
2064 velems->offset[loc] = desc->offset;
2065 velems->binding[loc] = desc->binding;
2066 velems->count = MAX2(velems->count, loc + 1);
2067 }
2068
2069 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2070 const VkVertexInputBindingDescription *desc =
2071 &vi_info->pVertexBindingDescriptions[i];
2072
2073 pipeline->binding_stride[desc->binding] = desc->stride;
2074 }
2075
2076 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2077 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2078 if (loc->sgpr_idx != -1) {
2079 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2080 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2081 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2082 pipeline->graphics.vtx_emit_num = 3;
2083 else
2084 pipeline->graphics.vtx_emit_num = 2;
2085 }
2086 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2087 radv_dump_pipeline_stats(device, pipeline);
2088 }
2089
2090 result = radv_pipeline_scratch_init(device, pipeline);
2091 return result;
2092 }
2093
2094 VkResult
2095 radv_graphics_pipeline_create(
2096 VkDevice _device,
2097 VkPipelineCache _cache,
2098 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2099 const struct radv_graphics_pipeline_create_info *extra,
2100 const VkAllocationCallbacks *pAllocator,
2101 VkPipeline *pPipeline)
2102 {
2103 RADV_FROM_HANDLE(radv_device, device, _device);
2104 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2105 struct radv_pipeline *pipeline;
2106 VkResult result;
2107
2108 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2109 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2110 if (pipeline == NULL)
2111 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2112
2113 memset(pipeline, 0, sizeof(*pipeline));
2114 result = radv_pipeline_init(pipeline, device, cache,
2115 pCreateInfo, extra, pAllocator);
2116 if (result != VK_SUCCESS) {
2117 radv_pipeline_destroy(device, pipeline, pAllocator);
2118 return result;
2119 }
2120
2121 *pPipeline = radv_pipeline_to_handle(pipeline);
2122
2123 return VK_SUCCESS;
2124 }
2125
2126 VkResult radv_CreateGraphicsPipelines(
2127 VkDevice _device,
2128 VkPipelineCache pipelineCache,
2129 uint32_t count,
2130 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2131 const VkAllocationCallbacks* pAllocator,
2132 VkPipeline* pPipelines)
2133 {
2134 VkResult result = VK_SUCCESS;
2135 unsigned i = 0;
2136
2137 for (; i < count; i++) {
2138 VkResult r;
2139 r = radv_graphics_pipeline_create(_device,
2140 pipelineCache,
2141 &pCreateInfos[i],
2142 NULL, pAllocator, &pPipelines[i]);
2143 if (r != VK_SUCCESS) {
2144 result = r;
2145 pPipelines[i] = VK_NULL_HANDLE;
2146 }
2147 }
2148
2149 return result;
2150 }
2151
2152 static VkResult radv_compute_pipeline_create(
2153 VkDevice _device,
2154 VkPipelineCache _cache,
2155 const VkComputePipelineCreateInfo* pCreateInfo,
2156 const VkAllocationCallbacks* pAllocator,
2157 VkPipeline* pPipeline)
2158 {
2159 RADV_FROM_HANDLE(radv_device, device, _device);
2160 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2161 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2162 struct radv_pipeline *pipeline;
2163 VkResult result;
2164
2165 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2166 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2167 if (pipeline == NULL)
2168 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2169
2170 memset(pipeline, 0, sizeof(*pipeline));
2171 pipeline->device = device;
2172 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2173
2174 pipeline->shaders[MESA_SHADER_COMPUTE] =
2175 radv_pipeline_compile(pipeline, cache, module,
2176 pCreateInfo->stage.pName,
2177 MESA_SHADER_COMPUTE,
2178 pCreateInfo->stage.pSpecializationInfo,
2179 pipeline->layout, NULL);
2180
2181
2182 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2183 result = radv_pipeline_scratch_init(device, pipeline);
2184 if (result != VK_SUCCESS) {
2185 radv_pipeline_destroy(device, pipeline, pAllocator);
2186 return result;
2187 }
2188
2189 *pPipeline = radv_pipeline_to_handle(pipeline);
2190
2191 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2192 radv_dump_pipeline_stats(device, pipeline);
2193 }
2194 return VK_SUCCESS;
2195 }
2196 VkResult radv_CreateComputePipelines(
2197 VkDevice _device,
2198 VkPipelineCache pipelineCache,
2199 uint32_t count,
2200 const VkComputePipelineCreateInfo* pCreateInfos,
2201 const VkAllocationCallbacks* pAllocator,
2202 VkPipeline* pPipelines)
2203 {
2204 VkResult result = VK_SUCCESS;
2205
2206 unsigned i = 0;
2207 for (; i < count; i++) {
2208 VkResult r;
2209 r = radv_compute_pipeline_create(_device, pipelineCache,
2210 &pCreateInfos[i],
2211 pAllocator, &pPipelines[i]);
2212 if (r != VK_SUCCESS) {
2213 result = r;
2214 pPipelines[i] = VK_NULL_HANDLE;
2215 }
2216 }
2217
2218 return result;
2219 }