projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: scan which color blend attachments are enabled
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t blend_enable;
54 uint32_t need_src_alpha;
55
56 uint32_t cb_color_control;
57 uint32_t cb_target_mask;
58 uint32_t cb_target_enabled_4bit;
59 uint32_t sx_mrt_blend_opt[8];
60 uint32_t cb_blend_control[8];
61
62 uint32_t spi_shader_col_format;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 bool single_cb_enable;
67 bool mrt0_is_dual_src;
68 };
69
70 struct radv_tessellation_state {
71 uint32_t ls_hs_config;
72 unsigned num_patches;
73 unsigned lds_size;
74 uint32_t tf_param;
75 };
76
77 struct radv_gs_state {
78 uint32_t vgt_gs_onchip_cntl;
79 uint32_t vgt_gs_max_prims_per_subgroup;
80 uint32_t vgt_esgs_ring_itemsize;
81 uint32_t lds_size;
82 };
83
84 static void
85 radv_pipeline_destroy(struct radv_device *device,
86 struct radv_pipeline *pipeline,
87 const VkAllocationCallbacks* allocator)
88 {
89 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
90 if (pipeline->shaders[i])
91 radv_shader_variant_destroy(device, pipeline->shaders[i]);
92
93 if (pipeline->gs_copy_shader)
94 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
95
96 if(pipeline->cs.buf)
97 free(pipeline->cs.buf);
98 vk_free2(&device->alloc, allocator, pipeline);
99 }
100
101 void radv_DestroyPipeline(
102 VkDevice _device,
103 VkPipeline _pipeline,
104 const VkAllocationCallbacks* pAllocator)
105 {
106 RADV_FROM_HANDLE(radv_device, device, _device);
107 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
108
109 if (!_pipeline)
110 return;
111
112 radv_pipeline_destroy(device, pipeline, pAllocator);
113 }
114
115 static uint32_t get_hash_flags(struct radv_device *device)
116 {
117 uint32_t hash_flags = 0;
118
119 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
120 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
121 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
122 hash_flags |= RADV_HASH_SHADER_SISCHED;
123 return hash_flags;
124 }
125
126 static VkResult
127 radv_pipeline_scratch_init(struct radv_device *device,
128 struct radv_pipeline *pipeline)
129 {
130 unsigned scratch_bytes_per_wave = 0;
131 unsigned max_waves = 0;
132 unsigned min_waves = 1;
133
134 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
135 if (pipeline->shaders[i]) {
136 unsigned max_stage_waves = device->scratch_waves;
137
138 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
139 pipeline->shaders[i]->config.scratch_bytes_per_wave);
140
141 max_stage_waves = MIN2(max_stage_waves,
142 4 * device->physical_device->rad_info.num_good_compute_units *
143 (256 / pipeline->shaders[i]->config.num_vgprs));
144 max_waves = MAX2(max_waves, max_stage_waves);
145 }
146 }
147
148 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
149 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
150 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
151 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
152 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
153 }
154
155 if (scratch_bytes_per_wave)
156 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
157
158 if (scratch_bytes_per_wave && max_waves < min_waves) {
159 /* Not really true at this moment, but will be true on first
160 * execution. Avoid having hanging shaders. */
161 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
162 }
163 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
164 pipeline->max_waves = max_waves;
165 return VK_SUCCESS;
166 }
167
168 static uint32_t si_translate_blend_function(VkBlendOp op)
169 {
170 switch (op) {
171 case VK_BLEND_OP_ADD:
172 return V_028780_COMB_DST_PLUS_SRC;
173 case VK_BLEND_OP_SUBTRACT:
174 return V_028780_COMB_SRC_MINUS_DST;
175 case VK_BLEND_OP_REVERSE_SUBTRACT:
176 return V_028780_COMB_DST_MINUS_SRC;
177 case VK_BLEND_OP_MIN:
178 return V_028780_COMB_MIN_DST_SRC;
179 case VK_BLEND_OP_MAX:
180 return V_028780_COMB_MAX_DST_SRC;
181 default:
182 return 0;
183 }
184 }
185
186 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
187 {
188 switch (factor) {
189 case VK_BLEND_FACTOR_ZERO:
190 return V_028780_BLEND_ZERO;
191 case VK_BLEND_FACTOR_ONE:
192 return V_028780_BLEND_ONE;
193 case VK_BLEND_FACTOR_SRC_COLOR:
194 return V_028780_BLEND_SRC_COLOR;
195 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
196 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
197 case VK_BLEND_FACTOR_DST_COLOR:
198 return V_028780_BLEND_DST_COLOR;
199 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
200 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
201 case VK_BLEND_FACTOR_SRC_ALPHA:
202 return V_028780_BLEND_SRC_ALPHA;
203 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
204 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
205 case VK_BLEND_FACTOR_DST_ALPHA:
206 return V_028780_BLEND_DST_ALPHA;
207 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
208 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
209 case VK_BLEND_FACTOR_CONSTANT_COLOR:
210 return V_028780_BLEND_CONSTANT_COLOR;
211 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
212 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
213 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
214 return V_028780_BLEND_CONSTANT_ALPHA;
215 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
216 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
217 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
218 return V_028780_BLEND_SRC_ALPHA_SATURATE;
219 case VK_BLEND_FACTOR_SRC1_COLOR:
220 return V_028780_BLEND_SRC1_COLOR;
221 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
222 return V_028780_BLEND_INV_SRC1_COLOR;
223 case VK_BLEND_FACTOR_SRC1_ALPHA:
224 return V_028780_BLEND_SRC1_ALPHA;
225 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
226 return V_028780_BLEND_INV_SRC1_ALPHA;
227 default:
228 return 0;
229 }
230 }
231
232 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
233 {
234 switch (op) {
235 case VK_BLEND_OP_ADD:
236 return V_028760_OPT_COMB_ADD;
237 case VK_BLEND_OP_SUBTRACT:
238 return V_028760_OPT_COMB_SUBTRACT;
239 case VK_BLEND_OP_REVERSE_SUBTRACT:
240 return V_028760_OPT_COMB_REVSUBTRACT;
241 case VK_BLEND_OP_MIN:
242 return V_028760_OPT_COMB_MIN;
243 case VK_BLEND_OP_MAX:
244 return V_028760_OPT_COMB_MAX;
245 default:
246 return V_028760_OPT_COMB_BLEND_DISABLED;
247 }
248 }
249
250 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
251 {
252 switch (factor) {
253 case VK_BLEND_FACTOR_ZERO:
254 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
255 case VK_BLEND_FACTOR_ONE:
256 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
257 case VK_BLEND_FACTOR_SRC_COLOR:
258 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
259 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
261 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
262 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
263 case VK_BLEND_FACTOR_SRC_ALPHA:
264 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
265 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
266 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
267 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
268 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
269 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
270 default:
271 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
272 }
273 }
274
275 /**
276 * Get rid of DST in the blend factors by commuting the operands:
277 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
278 */
279 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
280 unsigned *dst_factor, unsigned expected_dst,
281 unsigned replacement_src)
282 {
283 if (*src_factor == expected_dst &&
284 *dst_factor == VK_BLEND_FACTOR_ZERO) {
285 *src_factor = VK_BLEND_FACTOR_ZERO;
286 *dst_factor = replacement_src;
287
288 /* Commuting the operands requires reversing subtractions. */
289 if (*func == VK_BLEND_OP_SUBTRACT)
290 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
291 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
292 *func = VK_BLEND_OP_SUBTRACT;
293 }
294 }
295
296 static bool si_blend_factor_uses_dst(unsigned factor)
297 {
298 return factor == VK_BLEND_FACTOR_DST_COLOR ||
299 factor == VK_BLEND_FACTOR_DST_ALPHA ||
300 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
301 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
302 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
303 }
304
305 static bool is_dual_src(VkBlendFactor factor)
306 {
307 switch (factor) {
308 case VK_BLEND_FACTOR_SRC1_COLOR:
309 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
310 case VK_BLEND_FACTOR_SRC1_ALPHA:
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
312 return true;
313 default:
314 return false;
315 }
316 }
317
318 static unsigned si_choose_spi_color_format(VkFormat vk_format,
319 bool blend_enable,
320 bool blend_need_alpha)
321 {
322 const struct vk_format_description *desc = vk_format_description(vk_format);
323 unsigned format, ntype, swap;
324
325 /* Alpha is needed for alpha-to-coverage.
326 * Blending may be with or without alpha.
327 */
328 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
329 unsigned alpha = 0; /* exports alpha, but may not support blending */
330 unsigned blend = 0; /* supports blending, but may not export alpha */
331 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
332
333 format = radv_translate_colorformat(vk_format);
334 ntype = radv_translate_color_numformat(vk_format, desc,
335 vk_format_get_first_non_void_channel(vk_format));
336 swap = radv_translate_colorswap(vk_format, false);
337
338 /* Choose the SPI color formats. These are required values for Stoney/RB+.
339 * Other chips have multiple choices, though they are not necessarily better.
340 */
341 switch (format) {
342 case V_028C70_COLOR_5_6_5:
343 case V_028C70_COLOR_1_5_5_5:
344 case V_028C70_COLOR_5_5_5_1:
345 case V_028C70_COLOR_4_4_4_4:
346 case V_028C70_COLOR_10_11_11:
347 case V_028C70_COLOR_11_11_10:
348 case V_028C70_COLOR_8:
349 case V_028C70_COLOR_8_8:
350 case V_028C70_COLOR_8_8_8_8:
351 case V_028C70_COLOR_10_10_10_2:
352 case V_028C70_COLOR_2_10_10_10:
353 if (ntype == V_028C70_NUMBER_UINT)
354 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
355 else if (ntype == V_028C70_NUMBER_SINT)
356 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
357 else
358 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
359 break;
360
361 case V_028C70_COLOR_16:
362 case V_028C70_COLOR_16_16:
363 case V_028C70_COLOR_16_16_16_16:
364 if (ntype == V_028C70_NUMBER_UNORM ||
365 ntype == V_028C70_NUMBER_SNORM) {
366 /* UNORM16 and SNORM16 don't support blending */
367 if (ntype == V_028C70_NUMBER_UNORM)
368 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
369 else
370 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
371
372 /* Use 32 bits per channel for blending. */
373 if (format == V_028C70_COLOR_16) {
374 if (swap == V_028C70_SWAP_STD) { /* R */
375 blend = V_028714_SPI_SHADER_32_R;
376 blend_alpha = V_028714_SPI_SHADER_32_AR;
377 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
378 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
379 else
380 assert(0);
381 } else if (format == V_028C70_COLOR_16_16) {
382 if (swap == V_028C70_SWAP_STD) { /* RG */
383 blend = V_028714_SPI_SHADER_32_GR;
384 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
385 } else if (swap == V_028C70_SWAP_ALT) /* RA */
386 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
387 else
388 assert(0);
389 } else /* 16_16_16_16 */
390 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
391 } else if (ntype == V_028C70_NUMBER_UINT)
392 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
393 else if (ntype == V_028C70_NUMBER_SINT)
394 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
395 else if (ntype == V_028C70_NUMBER_FLOAT)
396 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
397 else
398 assert(0);
399 break;
400
401 case V_028C70_COLOR_32:
402 if (swap == V_028C70_SWAP_STD) { /* R */
403 blend = normal = V_028714_SPI_SHADER_32_R;
404 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
405 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
406 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
407 else
408 assert(0);
409 break;
410
411 case V_028C70_COLOR_32_32:
412 if (swap == V_028C70_SWAP_STD) { /* RG */
413 blend = normal = V_028714_SPI_SHADER_32_GR;
414 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
415 } else if (swap == V_028C70_SWAP_ALT) /* RA */
416 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
417 else
418 assert(0);
419 break;
420
421 case V_028C70_COLOR_32_32_32_32:
422 case V_028C70_COLOR_8_24:
423 case V_028C70_COLOR_24_8:
424 case V_028C70_COLOR_X24_8_32_FLOAT:
425 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
426 break;
427
428 default:
429 unreachable("unhandled blend format");
430 }
431
432 if (blend_enable && blend_need_alpha)
433 return blend_alpha;
434 else if(blend_need_alpha)
435 return alpha;
436 else if(blend_enable)
437 return blend;
438 else
439 return normal;
440 }
441
442 static void
443 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
444 const VkGraphicsPipelineCreateInfo *pCreateInfo,
445 struct radv_blend_state *blend)
446 {
447 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
448 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
449 unsigned col_format = 0;
450
451 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
452 unsigned cf;
453
454 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
455 cf = V_028714_SPI_SHADER_ZERO;
456 } else {
457 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
458
459 cf = si_choose_spi_color_format(attachment->format,
460 blend->blend_enable & (1 << i),
461 blend->need_src_alpha & (1 << i));
462 }
463
464 col_format |= cf << (4 * i);
465 }
466
467 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
468
469 if (blend->mrt0_is_dual_src)
470 col_format |= (col_format & 0xf) << 4;
471 blend->spi_shader_col_format = col_format;
472 }
473
474 static bool
475 format_is_int8(VkFormat format)
476 {
477 const struct vk_format_description *desc = vk_format_description(format);
478 int channel = vk_format_get_first_non_void_channel(format);
479
480 return channel >= 0 && desc->channel[channel].pure_integer &&
481 desc->channel[channel].size == 8;
482 }
483
484 static bool
485 format_is_int10(VkFormat format)
486 {
487 const struct vk_format_description *desc = vk_format_description(format);
488
489 if (desc->nr_channels != 4)
490 return false;
491 for (unsigned i = 0; i < 4; i++) {
492 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
493 return true;
494 }
495 return false;
496 }
497
498 unsigned radv_format_meta_fs_key(VkFormat format)
499 {
500 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
501 bool is_int8 = format_is_int8(format);
502 bool is_int10 = format_is_int10(format);
503
504 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
505 }
506
507 static void
508 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
509 unsigned *is_int8, unsigned *is_int10)
510 {
511 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
512 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
513 *is_int8 = 0;
514 *is_int10 = 0;
515
516 for (unsigned i = 0; i < subpass->color_count; ++i) {
517 struct radv_render_pass_attachment *attachment;
518
519 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
520 continue;
521
522 attachment = pass->attachments + subpass->color_attachments[i].attachment;
523
524 if (format_is_int8(attachment->format))
525 *is_int8 |= 1 << i;
526 if (format_is_int10(attachment->format))
527 *is_int10 |= 1 << i;
528 }
529 }
530
531 static struct radv_blend_state
532 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
533 const VkGraphicsPipelineCreateInfo *pCreateInfo,
534 const struct radv_graphics_pipeline_create_info *extra)
535 {
536 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
537 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
538 struct radv_blend_state blend = {0};
539 unsigned mode = V_028808_CB_NORMAL;
540 int i;
541
542 if (!vkblend)
543 return blend;
544
545 if (extra && extra->custom_blend_mode) {
546 blend.single_cb_enable = true;
547 mode = extra->custom_blend_mode;
548 }
549 blend.cb_color_control = 0;
550 if (vkblend->logicOpEnable)
551 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
552 else
553 blend.cb_color_control |= S_028808_ROP3(0xcc);
554
555 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
556 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
557 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
558 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
559
560 if (vkms && vkms->alphaToCoverageEnable) {
561 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
562 }
563
564 blend.cb_target_mask = 0;
565 for (i = 0; i < vkblend->attachmentCount; i++) {
566 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
567 unsigned blend_cntl = 0;
568 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
569 VkBlendOp eqRGB = att->colorBlendOp;
570 VkBlendFactor srcRGB = att->srcColorBlendFactor;
571 VkBlendFactor dstRGB = att->dstColorBlendFactor;
572 VkBlendOp eqA = att->alphaBlendOp;
573 VkBlendFactor srcA = att->srcAlphaBlendFactor;
574 VkBlendFactor dstA = att->dstAlphaBlendFactor;
575
576 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
577
578 if (!att->colorWriteMask)
579 continue;
580
581 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
582 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
583 if (!att->blendEnable) {
584 blend.cb_blend_control[i] = blend_cntl;
585 continue;
586 }
587
588 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
589 if (i == 0)
590 blend.mrt0_is_dual_src = true;
591
592 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
593 srcRGB = VK_BLEND_FACTOR_ONE;
594 dstRGB = VK_BLEND_FACTOR_ONE;
595 }
596 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
597 srcA = VK_BLEND_FACTOR_ONE;
598 dstA = VK_BLEND_FACTOR_ONE;
599 }
600
601 /* Blending optimizations for RB+.
602 * These transformations don't change the behavior.
603 *
604 * First, get rid of DST in the blend factors:
605 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
606 */
607 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
608 VK_BLEND_FACTOR_DST_COLOR,
609 VK_BLEND_FACTOR_SRC_COLOR);
610
611 si_blend_remove_dst(&eqA, &srcA, &dstA,
612 VK_BLEND_FACTOR_DST_COLOR,
613 VK_BLEND_FACTOR_SRC_COLOR);
614
615 si_blend_remove_dst(&eqA, &srcA, &dstA,
616 VK_BLEND_FACTOR_DST_ALPHA,
617 VK_BLEND_FACTOR_SRC_ALPHA);
618
619 /* Look up the ideal settings from tables. */
620 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
621 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
622 srcA_opt = si_translate_blend_opt_factor(srcA, true);
623 dstA_opt = si_translate_blend_opt_factor(dstA, true);
624
625 /* Handle interdependencies. */
626 if (si_blend_factor_uses_dst(srcRGB))
627 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
628 if (si_blend_factor_uses_dst(srcA))
629 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
630
631 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
632 (dstRGB == VK_BLEND_FACTOR_ZERO ||
633 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
634 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
635 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
636
637 /* Set the final value. */
638 blend.sx_mrt_blend_opt[i] =
639 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
640 S_028760_COLOR_DST_OPT(dstRGB_opt) |
641 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
642 S_028760_ALPHA_SRC_OPT(srcA_opt) |
643 S_028760_ALPHA_DST_OPT(dstA_opt) |
644 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
645 blend_cntl |= S_028780_ENABLE(1);
646
647 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
648 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
649 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
650 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
651 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
652 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
653 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
654 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
655 }
656 blend.cb_blend_control[i] = blend_cntl;
657
658 blend.blend_enable |= 1 << i;
659
660 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
661 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
662 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
663 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
664 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
665 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
666 blend.need_src_alpha |= 1 << i;
667 }
668 for (i = vkblend->attachmentCount; i < 8; i++) {
669 blend.cb_blend_control[i] = 0;
670 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
671 }
672
673 if (pipeline->device->physical_device->has_rbplus) {
674 /* Disable RB+ blend optimizations for dual source blending. */
675 if (blend.mrt0_is_dual_src) {
676 for (i = 0; i < 8; i++) {
677 blend.sx_mrt_blend_opt[i] =
678 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
679 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
680 }
681 }
682
683 /* RB+ doesn't work with dual source blending, logic op and
684 * RESOLVE.
685 */
686 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
687 mode == V_028808_CB_RESOLVE)
688 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
689 }
690
691 if (blend.cb_target_mask)
692 blend.cb_color_control |= S_028808_MODE(mode);
693 else
694 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
695
696 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
697 return blend;
698 }
699
700 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
701 {
702 switch (op) {
703 case VK_STENCIL_OP_KEEP:
704 return V_02842C_STENCIL_KEEP;
705 case VK_STENCIL_OP_ZERO:
706 return V_02842C_STENCIL_ZERO;
707 case VK_STENCIL_OP_REPLACE:
708 return V_02842C_STENCIL_REPLACE_TEST;
709 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
710 return V_02842C_STENCIL_ADD_CLAMP;
711 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
712 return V_02842C_STENCIL_SUB_CLAMP;
713 case VK_STENCIL_OP_INVERT:
714 return V_02842C_STENCIL_INVERT;
715 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
716 return V_02842C_STENCIL_ADD_WRAP;
717 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
718 return V_02842C_STENCIL_SUB_WRAP;
719 default:
720 return 0;
721 }
722 }
723
724 static uint32_t si_translate_fill(VkPolygonMode func)
725 {
726 switch(func) {
727 case VK_POLYGON_MODE_FILL:
728 return V_028814_X_DRAW_TRIANGLES;
729 case VK_POLYGON_MODE_LINE:
730 return V_028814_X_DRAW_LINES;
731 case VK_POLYGON_MODE_POINT:
732 return V_028814_X_DRAW_POINTS;
733 default:
734 assert(0);
735 return V_028814_X_DRAW_POINTS;
736 }
737 }
738
739 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
740 {
741 uint32_t num_samples = vkms->rasterizationSamples;
742 uint32_t ps_iter_samples = 1;
743
744 if (vkms->sampleShadingEnable) {
745 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
746 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
747 }
748 return ps_iter_samples;
749 }
750
751 static void
752 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
753 const VkGraphicsPipelineCreateInfo *pCreateInfo)
754 {
755 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
756 struct radv_multisample_state *ms = &pipeline->graphics.ms;
757 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
758 int ps_iter_samples = 1;
759 uint32_t mask = 0xffff;
760
761 if (vkms)
762 ms->num_samples = vkms->rasterizationSamples;
763 else
764 ms->num_samples = 1;
765
766 if (vkms)
767 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
768 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
769 ps_iter_samples = ms->num_samples;
770 }
771
772 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
773 ms->pa_sc_aa_config = 0;
774 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
775 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
776 ms->pa_sc_mode_cntl_1 =
777 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
778 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
779 /* always 1: */
780 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
781 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
782 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
783 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
784 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
785 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
786 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
787 S_028A48_VPORT_SCISSOR_ENABLE(1);
788
789 if (ms->num_samples > 1) {
790 unsigned log_samples = util_logbase2(ms->num_samples);
791 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
792 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
793 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
794 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
795 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
796 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
797 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
798 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
799 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
800 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
801 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
802 if (ps_iter_samples > 1)
803 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
804 }
805
806 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
807 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
808 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
809 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
810 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
811 }
812
813 if (vkms && vkms->pSampleMask) {
814 mask = vkms->pSampleMask[0] & 0xffff;
815 }
816
817 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
818 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
819 }
820
821 static bool
822 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
823 {
824 switch (topology) {
825 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
826 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
827 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
828 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
829 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
830 return false;
831 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
832 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
833 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
834 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
835 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
836 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
837 return true;
838 default:
839 unreachable("unhandled primitive type");
840 }
841 }
842
843 static uint32_t
844 si_translate_prim(enum VkPrimitiveTopology topology)
845 {
846 switch (topology) {
847 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
848 return V_008958_DI_PT_POINTLIST;
849 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
850 return V_008958_DI_PT_LINELIST;
851 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
852 return V_008958_DI_PT_LINESTRIP;
853 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
854 return V_008958_DI_PT_TRILIST;
855 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
856 return V_008958_DI_PT_TRISTRIP;
857 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
858 return V_008958_DI_PT_TRIFAN;
859 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
860 return V_008958_DI_PT_LINELIST_ADJ;
861 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
862 return V_008958_DI_PT_LINESTRIP_ADJ;
863 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
864 return V_008958_DI_PT_TRILIST_ADJ;
865 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
866 return V_008958_DI_PT_TRISTRIP_ADJ;
867 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
868 return V_008958_DI_PT_PATCH;
869 default:
870 assert(0);
871 return 0;
872 }
873 }
874
875 static uint32_t
876 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
877 {
878 switch (gl_prim) {
879 case 0: /* GL_POINTS */
880 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
881 case 1: /* GL_LINES */
882 case 3: /* GL_LINE_STRIP */
883 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
884 case 0x8E7A: /* GL_ISOLINES */
885 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
886
887 case 4: /* GL_TRIANGLES */
888 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
889 case 5: /* GL_TRIANGLE_STRIP */
890 case 7: /* GL_QUADS */
891 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
892 default:
893 assert(0);
894 return 0;
895 }
896 }
897
898 static uint32_t
899 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
900 {
901 switch (topology) {
902 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
903 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
904 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
905 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
906 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
907 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
908 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
909 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
910 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
911 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
912 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
913 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
914 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
915 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
916 default:
917 assert(0);
918 return 0;
919 }
920 }
921
922 static unsigned si_map_swizzle(unsigned swizzle)
923 {
924 switch (swizzle) {
925 case VK_SWIZZLE_Y:
926 return V_008F0C_SQ_SEL_Y;
927 case VK_SWIZZLE_Z:
928 return V_008F0C_SQ_SEL_Z;
929 case VK_SWIZZLE_W:
930 return V_008F0C_SQ_SEL_W;
931 case VK_SWIZZLE_0:
932 return V_008F0C_SQ_SEL_0;
933 case VK_SWIZZLE_1:
934 return V_008F0C_SQ_SEL_1;
935 default: /* VK_SWIZZLE_X */
936 return V_008F0C_SQ_SEL_X;
937 }
938 }
939
940
941 static unsigned radv_dynamic_state_mask(VkDynamicState state)
942 {
943 switch(state) {
944 case VK_DYNAMIC_STATE_VIEWPORT:
945 return RADV_DYNAMIC_VIEWPORT;
946 case VK_DYNAMIC_STATE_SCISSOR:
947 return RADV_DYNAMIC_SCISSOR;
948 case VK_DYNAMIC_STATE_LINE_WIDTH:
949 return RADV_DYNAMIC_LINE_WIDTH;
950 case VK_DYNAMIC_STATE_DEPTH_BIAS:
951 return RADV_DYNAMIC_DEPTH_BIAS;
952 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
953 return RADV_DYNAMIC_BLEND_CONSTANTS;
954 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
955 return RADV_DYNAMIC_DEPTH_BOUNDS;
956 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
957 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
958 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
959 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
960 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
961 return RADV_DYNAMIC_STENCIL_REFERENCE;
962 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
963 return RADV_DYNAMIC_DISCARD_RECTANGLE;
964 default:
965 unreachable("Unhandled dynamic state");
966 }
967 }
968
969 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
970 {
971 uint32_t states = RADV_DYNAMIC_ALL;
972
973 /* If rasterization is disabled we do not care about any of the dynamic states,
974 * since they are all rasterization related only. */
975 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
976 return 0;
977
978 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
979 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
980
981 if (!pCreateInfo->pDepthStencilState ||
982 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
983 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
984
985 if (!pCreateInfo->pDepthStencilState ||
986 !pCreateInfo->pDepthStencilState->stencilTestEnable)
987 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
988 RADV_DYNAMIC_STENCIL_WRITE_MASK |
989 RADV_DYNAMIC_STENCIL_REFERENCE);
990
991 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
992 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
993
994 /* TODO: blend constants & line width. */
995
996 return states;
997 }
998
999
1000 static void
1001 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1002 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1003 {
1004 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1005 uint32_t states = needed_states;
1006 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1007 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1008
1009 pipeline->dynamic_state = default_dynamic_state;
1010 pipeline->graphics.needed_dynamic_state = needed_states;
1011
1012 if (pCreateInfo->pDynamicState) {
1013 /* Remove all of the states that are marked as dynamic */
1014 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1015 for (uint32_t s = 0; s < count; s++)
1016 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1017 }
1018
1019 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1020
1021 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1022 assert(pCreateInfo->pViewportState);
1023
1024 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1025 if (states & RADV_DYNAMIC_VIEWPORT) {
1026 typed_memcpy(dynamic->viewport.viewports,
1027 pCreateInfo->pViewportState->pViewports,
1028 pCreateInfo->pViewportState->viewportCount);
1029 }
1030 }
1031
1032 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1033 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1034 if (states & RADV_DYNAMIC_SCISSOR) {
1035 typed_memcpy(dynamic->scissor.scissors,
1036 pCreateInfo->pViewportState->pScissors,
1037 pCreateInfo->pViewportState->scissorCount);
1038 }
1039 }
1040
1041 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1042 assert(pCreateInfo->pRasterizationState);
1043 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1044 }
1045
1046 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1047 assert(pCreateInfo->pRasterizationState);
1048 dynamic->depth_bias.bias =
1049 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1050 dynamic->depth_bias.clamp =
1051 pCreateInfo->pRasterizationState->depthBiasClamp;
1052 dynamic->depth_bias.slope =
1053 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1054 }
1055
1056 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1057 *
1058 * pColorBlendState is [...] NULL if the pipeline has rasterization
1059 * disabled or if the subpass of the render pass the pipeline is
1060 * created against does not use any color attachments.
1061 */
1062 bool uses_color_att = false;
1063 for (unsigned i = 0; i < subpass->color_count; ++i) {
1064 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1065 uses_color_att = true;
1066 break;
1067 }
1068 }
1069
1070 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1071 assert(pCreateInfo->pColorBlendState);
1072 typed_memcpy(dynamic->blend_constants,
1073 pCreateInfo->pColorBlendState->blendConstants, 4);
1074 }
1075
1076 /* If there is no depthstencil attachment, then don't read
1077 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1078 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1079 * no need to override the depthstencil defaults in
1080 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1081 *
1082 * Section 9.2 of the Vulkan 1.0.15 spec says:
1083 *
1084 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1085 * disabled or if the subpass of the render pass the pipeline is created
1086 * against does not use a depth/stencil attachment.
1087 */
1088 if (needed_states &&
1089 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1090 assert(pCreateInfo->pDepthStencilState);
1091
1092 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1093 dynamic->depth_bounds.min =
1094 pCreateInfo->pDepthStencilState->minDepthBounds;
1095 dynamic->depth_bounds.max =
1096 pCreateInfo->pDepthStencilState->maxDepthBounds;
1097 }
1098
1099 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1100 dynamic->stencil_compare_mask.front =
1101 pCreateInfo->pDepthStencilState->front.compareMask;
1102 dynamic->stencil_compare_mask.back =
1103 pCreateInfo->pDepthStencilState->back.compareMask;
1104 }
1105
1106 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1107 dynamic->stencil_write_mask.front =
1108 pCreateInfo->pDepthStencilState->front.writeMask;
1109 dynamic->stencil_write_mask.back =
1110 pCreateInfo->pDepthStencilState->back.writeMask;
1111 }
1112
1113 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1114 dynamic->stencil_reference.front =
1115 pCreateInfo->pDepthStencilState->front.reference;
1116 dynamic->stencil_reference.back =
1117 pCreateInfo->pDepthStencilState->back.reference;
1118 }
1119 }
1120
1121 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1122 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1123 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1124 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1125 typed_memcpy(dynamic->discard_rectangle.rectangles,
1126 discard_rectangle_info->pDiscardRectangles,
1127 discard_rectangle_info->discardRectangleCount);
1128 }
1129
1130 pipeline->dynamic_state.mask = states;
1131 }
1132
1133 static struct radv_gs_state
1134 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1135 const struct radv_pipeline *pipeline)
1136 {
1137 struct radv_gs_state gs = {0};
1138 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1139 struct radv_es_output_info *es_info;
1140 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1141 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1142 else
1143 es_info = radv_pipeline_has_tess(pipeline) ?
1144 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1145 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1146
1147 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1148 bool uses_adjacency;
1149 switch(pCreateInfo->pInputAssemblyState->topology) {
1150 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1151 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1152 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1153 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1154 uses_adjacency = true;
1155 break;
1156 default:
1157 uses_adjacency = false;
1158 break;
1159 }
1160
1161 /* All these are in dwords: */
1162 /* We can't allow using the whole LDS, because GS waves compete with
1163 * other shader stages for LDS space. */
1164 const unsigned max_lds_size = 8 * 1024;
1165 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1166 unsigned esgs_lds_size;
1167
1168 /* All these are per subgroup: */
1169 const unsigned max_out_prims = 32 * 1024;
1170 const unsigned max_es_verts = 255;
1171 const unsigned ideal_gs_prims = 64;
1172 unsigned max_gs_prims, gs_prims;
1173 unsigned min_es_verts, es_verts, worst_case_es_verts;
1174
1175 if (uses_adjacency || gs_num_invocations > 1)
1176 max_gs_prims = 127 / gs_num_invocations;
1177 else
1178 max_gs_prims = 255;
1179
1180 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1181 * Make sure we don't go over the maximum value.
1182 */
1183 if (gs_info->gs.vertices_out > 0) {
1184 max_gs_prims = MIN2(max_gs_prims,
1185 max_out_prims /
1186 (gs_info->gs.vertices_out * gs_num_invocations));
1187 }
1188 assert(max_gs_prims > 0);
1189
1190 /* If the primitive has adjacency, halve the number of vertices
1191 * that will be reused in multiple primitives.
1192 */
1193 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1194
1195 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1196 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1197
1198 /* Compute ESGS LDS size based on the worst case number of ES vertices
1199 * needed to create the target number of GS prims per subgroup.
1200 */
1201 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1202
1203 /* If total LDS usage is too big, refactor partitions based on ratio
1204 * of ESGS item sizes.
1205 */
1206 if (esgs_lds_size > max_lds_size) {
1207 /* Our target GS Prims Per Subgroup was too large. Calculate
1208 * the maximum number of GS Prims Per Subgroup that will fit
1209 * into LDS, capped by the maximum that the hardware can support.
1210 */
1211 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1212 max_gs_prims);
1213 assert(gs_prims > 0);
1214 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1215 max_es_verts);
1216
1217 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1218 assert(esgs_lds_size <= max_lds_size);
1219 }
1220
1221 /* Now calculate remaining ESGS information. */
1222 if (esgs_lds_size)
1223 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1224 else
1225 es_verts = max_es_verts;
1226
1227 /* Vertices for adjacency primitives are not always reused, so restore
1228 * it for ES_VERTS_PER_SUBGRP.
1229 */
1230 min_es_verts = gs_info->gs.vertices_in;
1231
1232 /* For normal primitives, the VGT only checks if they are past the ES
1233 * verts per subgroup after allocating a full GS primitive and if they
1234 * are, kick off a new subgroup. But if those additional ES verts are
1235 * unique (e.g. not reused) we need to make sure there is enough LDS
1236 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1237 */
1238 es_verts -= min_es_verts - 1;
1239
1240 uint32_t es_verts_per_subgroup = es_verts;
1241 uint32_t gs_prims_per_subgroup = gs_prims;
1242 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1243 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1244 gs.lds_size = align(esgs_lds_size, 128) / 128;
1245 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1246 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1247 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1248 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1249 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1250 assert(max_prims_per_subgroup <= max_out_prims);
1251
1252 return gs;
1253 }
1254
1255 static void
1256 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1257 {
1258 struct radv_device *device = pipeline->device;
1259 unsigned num_se = device->physical_device->rad_info.max_se;
1260 unsigned wave_size = 64;
1261 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1262 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1263 unsigned alignment = 256 * num_se;
1264 /* The maximum size is 63.999 MB per SE. */
1265 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1266 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1267
1268 /* Calculate the minimum size. */
1269 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1270 wave_size, alignment);
1271 /* These are recommended sizes, not minimum sizes. */
1272 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1273 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1274 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1275 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1276
1277 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1278 esgs_ring_size = align(esgs_ring_size, alignment);
1279 gsvs_ring_size = align(gsvs_ring_size, alignment);
1280
1281 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1282 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1283
1284 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1285 }
1286
1287 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1288 unsigned *lds_size)
1289 {
1290 /* If tessellation is all offchip and on-chip GS isn't used, this
1291 * workaround is not needed.
1292 */
1293 return;
1294
1295 /* SPI barrier management bug:
1296 * Make sure we have at least 4k of LDS in use to avoid the bug.
1297 * It applies to workgroup sizes of more than one wavefront.
1298 */
1299 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1300 device->physical_device->rad_info.family == CHIP_KABINI ||
1301 device->physical_device->rad_info.family == CHIP_MULLINS)
1302 *lds_size = MAX2(*lds_size, 8);
1303 }
1304
1305 struct radv_shader_variant *
1306 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1307 {
1308 if (pipeline->shaders[MESA_SHADER_VERTEX])
1309 return pipeline->shaders[MESA_SHADER_VERTEX];
1310 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1311 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1312 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1313 }
1314
1315 static struct radv_shader_variant *
1316 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1317 {
1318 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1319 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1320 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1321 }
1322
1323 static struct radv_tessellation_state
1324 calculate_tess_state(struct radv_pipeline *pipeline,
1325 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1326 {
1327 unsigned num_tcs_input_cp;
1328 unsigned num_tcs_output_cp;
1329 unsigned lds_size;
1330 unsigned num_patches;
1331 struct radv_tessellation_state tess = {0};
1332
1333 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1334 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1335 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1336
1337 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1338
1339 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1340 assert(lds_size <= 65536);
1341 lds_size = align(lds_size, 512) / 512;
1342 } else {
1343 assert(lds_size <= 32768);
1344 lds_size = align(lds_size, 256) / 256;
1345 }
1346 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1347
1348 tess.lds_size = lds_size;
1349
1350 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1351 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1352 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1353 tess.num_patches = num_patches;
1354
1355 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1356 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1357
1358 switch (tes->info.tes.primitive_mode) {
1359 case GL_TRIANGLES:
1360 type = V_028B6C_TESS_TRIANGLE;
1361 break;
1362 case GL_QUADS:
1363 type = V_028B6C_TESS_QUAD;
1364 break;
1365 case GL_ISOLINES:
1366 type = V_028B6C_TESS_ISOLINE;
1367 break;
1368 }
1369
1370 switch (tes->info.tes.spacing) {
1371 case TESS_SPACING_EQUAL:
1372 partitioning = V_028B6C_PART_INTEGER;
1373 break;
1374 case TESS_SPACING_FRACTIONAL_ODD:
1375 partitioning = V_028B6C_PART_FRAC_ODD;
1376 break;
1377 case TESS_SPACING_FRACTIONAL_EVEN:
1378 partitioning = V_028B6C_PART_FRAC_EVEN;
1379 break;
1380 default:
1381 break;
1382 }
1383
1384 bool ccw = tes->info.tes.ccw;
1385 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1386 vk_find_struct_const(pCreateInfo->pTessellationState,
1387 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1388
1389 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1390 ccw = !ccw;
1391
1392 if (tes->info.tes.point_mode)
1393 topology = V_028B6C_OUTPUT_POINT;
1394 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1395 topology = V_028B6C_OUTPUT_LINE;
1396 else if (ccw)
1397 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1398 else
1399 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1400
1401 if (pipeline->device->has_distributed_tess) {
1402 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1403 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1404 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1405 else
1406 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1407 } else
1408 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1409
1410 tess.tf_param = S_028B6C_TYPE(type) |
1411 S_028B6C_PARTITIONING(partitioning) |
1412 S_028B6C_TOPOLOGY(topology) |
1413 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1414
1415 return tess;
1416 }
1417
1418 static const struct radv_prim_vertex_count prim_size_table[] = {
1419 [V_008958_DI_PT_NONE] = {0, 0},
1420 [V_008958_DI_PT_POINTLIST] = {1, 1},
1421 [V_008958_DI_PT_LINELIST] = {2, 2},
1422 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1423 [V_008958_DI_PT_TRILIST] = {3, 3},
1424 [V_008958_DI_PT_TRIFAN] = {3, 1},
1425 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1426 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1427 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1428 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1429 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1430 [V_008958_DI_PT_RECTLIST] = {3, 3},
1431 [V_008958_DI_PT_LINELOOP] = {2, 1},
1432 [V_008958_DI_PT_POLYGON] = {3, 1},
1433 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1434 };
1435
1436 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1437 {
1438 if (radv_pipeline_has_gs(pipeline))
1439 return &pipeline->gs_copy_shader->info.vs.outinfo;
1440 else if (radv_pipeline_has_tess(pipeline))
1441 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1442 else
1443 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1444 }
1445
1446 static void
1447 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1448 {
1449 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1450 int shader_count = 0;
1451
1452 if(shaders[MESA_SHADER_FRAGMENT]) {
1453 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1454 }
1455 if(shaders[MESA_SHADER_GEOMETRY]) {
1456 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1457 }
1458 if(shaders[MESA_SHADER_TESS_EVAL]) {
1459 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1460 }
1461 if(shaders[MESA_SHADER_TESS_CTRL]) {
1462 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1463 }
1464 if(shaders[MESA_SHADER_VERTEX]) {
1465 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1466 }
1467
1468 for (int i = 1; i < shader_count; ++i) {
1469 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1470 ordered_shaders[i - 1]);
1471
1472 nir_remove_dead_variables(ordered_shaders[i],
1473 nir_var_shader_out);
1474 nir_remove_dead_variables(ordered_shaders[i - 1],
1475 nir_var_shader_in);
1476
1477 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1478 ordered_shaders[i - 1]);
1479
1480 nir_compact_varyings(ordered_shaders[i],
1481 ordered_shaders[i - 1], true);
1482
1483 if (progress) {
1484 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1485 ac_lower_indirect_derefs(ordered_shaders[i],
1486 pipeline->device->physical_device->rad_info.chip_class);
1487 }
1488 radv_optimize_nir(ordered_shaders[i]);
1489
1490 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1491 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1492 pipeline->device->physical_device->rad_info.chip_class);
1493 }
1494 radv_optimize_nir(ordered_shaders[i - 1]);
1495 }
1496 }
1497 }
1498
1499
1500 static struct radv_pipeline_key
1501 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1502 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1503 const struct radv_blend_state *blend,
1504 bool has_view_index)
1505 {
1506 const VkPipelineVertexInputStateCreateInfo *input_state =
1507 pCreateInfo->pVertexInputState;
1508 struct radv_pipeline_key key;
1509 memset(&key, 0, sizeof(key));
1510
1511 key.has_multiview_view_index = has_view_index;
1512
1513 uint32_t binding_input_rate = 0;
1514 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1515 if (input_state->pVertexBindingDescriptions[i].inputRate)
1516 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1517 }
1518
1519 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1520 unsigned binding;
1521 binding = input_state->pVertexAttributeDescriptions[i].binding;
1522 if (binding_input_rate & (1u << binding))
1523 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1524 }
1525
1526 if (pCreateInfo->pTessellationState)
1527 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1528
1529
1530 if (pCreateInfo->pMultisampleState &&
1531 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1532 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1533 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1534 key.multisample = true;
1535 key.log2_num_samples = util_logbase2(num_samples);
1536 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1537 }
1538
1539 key.col_format = blend->spi_shader_col_format;
1540 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1541 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1542
1543 return key;
1544 }
1545
1546 static void
1547 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1548 const struct radv_pipeline_key *key,
1549 nir_shader **nir)
1550 {
1551 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1552
1553 if (nir[MESA_SHADER_TESS_CTRL]) {
1554 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1555 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1556 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1557 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1558
1559 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1560 }
1561
1562 if (nir[MESA_SHADER_GEOMETRY]) {
1563 if (nir[MESA_SHADER_TESS_CTRL])
1564 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1565 else
1566 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1567 }
1568
1569 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1570 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1571
1572 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1573 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1574 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1575 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1576 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1577 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1578 }
1579
1580 static void
1581 merge_tess_info(struct shader_info *tes_info,
1582 const struct shader_info *tcs_info)
1583 {
1584 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1585 *
1586 * "PointMode. Controls generation of points rather than triangles
1587 * or lines. This functionality defaults to disabled, and is
1588 * enabled if either shader stage includes the execution mode.
1589 *
1590 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1591 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1592 * and OutputVertices, it says:
1593 *
1594 * "One mode must be set in at least one of the tessellation
1595 * shader stages."
1596 *
1597 * So, the fields can be set in either the TCS or TES, but they must
1598 * agree if set in both. Our backend looks at TES, so bitwise-or in
1599 * the values from the TCS.
1600 */
1601 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1602 tes_info->tess.tcs_vertices_out == 0 ||
1603 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1604 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1605
1606 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1607 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1608 tcs_info->tess.spacing == tes_info->tess.spacing);
1609 tes_info->tess.spacing |= tcs_info->tess.spacing;
1610
1611 assert(tcs_info->tess.primitive_mode == 0 ||
1612 tes_info->tess.primitive_mode == 0 ||
1613 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1614 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1615 tes_info->tess.ccw |= tcs_info->tess.ccw;
1616 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1617 }
1618
1619 static
1620 void radv_create_shaders(struct radv_pipeline *pipeline,
1621 struct radv_device *device,
1622 struct radv_pipeline_cache *cache,
1623 struct radv_pipeline_key key,
1624 const VkPipelineShaderStageCreateInfo **pStages)
1625 {
1626 struct radv_shader_module fs_m = {0};
1627 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1628 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1629 void *codes[MESA_SHADER_STAGES] = {0};
1630 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1631 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1632 unsigned char hash[20], gs_copy_hash[20];
1633
1634 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1635 if (pStages[i]) {
1636 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1637 if (modules[i]->nir)
1638 _mesa_sha1_compute(modules[i]->nir->info.name,
1639 strlen(modules[i]->nir->info.name),
1640 modules[i]->sha1);
1641 }
1642 }
1643
1644 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1645 memcpy(gs_copy_hash, hash, 20);
1646 gs_copy_hash[0] ^= 1;
1647
1648 if (modules[MESA_SHADER_GEOMETRY]) {
1649 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1650 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1651 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1652 }
1653
1654 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1655 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1656 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1657 if (pipeline->shaders[i])
1658 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1659 }
1660 return;
1661 }
1662
1663 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1664 nir_builder fs_b;
1665 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1666 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1667 fs_m.nir = fs_b.shader;
1668 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1669 }
1670
1671 /* Determine first and last stage. */
1672 unsigned first = MESA_SHADER_STAGES;
1673 unsigned last = 0;
1674 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1675 if (!pStages[i])
1676 continue;
1677 if (first == MESA_SHADER_STAGES)
1678 first = i;
1679 last = i;
1680 }
1681
1682 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1683 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1684
1685 if (!modules[i])
1686 continue;
1687
1688 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1689 stage ? stage->pName : "main", i,
1690 stage ? stage->pSpecializationInfo : NULL);
1691 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1692
1693 /* We don't want to alter meta shaders IR directly so clone it
1694 * first.
1695 */
1696 if (nir[i]->info.name) {
1697 nir[i] = nir_shader_clone(NULL, nir[i]);
1698 }
1699
1700 if (first != last) {
1701 nir_variable_mode mask = 0;
1702
1703 if (i != first)
1704 mask = mask | nir_var_shader_in;
1705
1706 if (i != last)
1707 mask = mask | nir_var_shader_out;
1708
1709 nir_lower_io_to_scalar_early(nir[i], mask);
1710 radv_optimize_nir(nir[i]);
1711 }
1712 }
1713
1714 if (nir[MESA_SHADER_TESS_CTRL]) {
1715 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1716 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1717 }
1718
1719 radv_link_shaders(pipeline, nir);
1720
1721 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1722 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1723 nir_print_shader(nir[i], stderr);
1724 }
1725
1726 radv_fill_shader_keys(keys, &key, nir);
1727
1728 if (nir[MESA_SHADER_FRAGMENT]) {
1729 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1730 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1731 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1732 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1733 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1734 }
1735
1736 /* TODO: These are no longer used as keys we should refactor this */
1737 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1738 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1739 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
1740 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1741 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1742 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1743 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
1744 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1745 }
1746
1747 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1748 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1749 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1750 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1751 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1752 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1753 pipeline->layout,
1754 &key, &codes[MESA_SHADER_TESS_CTRL],
1755 &code_sizes[MESA_SHADER_TESS_CTRL]);
1756 }
1757 modules[MESA_SHADER_VERTEX] = NULL;
1758 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1759 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1760 }
1761
1762 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1763 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1764 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1765 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1766 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1767 pipeline->layout,
1768 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1769 &code_sizes[MESA_SHADER_GEOMETRY]);
1770 }
1771 modules[pre_stage] = NULL;
1772 }
1773
1774 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1775 if(modules[i] && !pipeline->shaders[i]) {
1776 if (i == MESA_SHADER_TESS_CTRL) {
1777 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
1778 }
1779 if (i == MESA_SHADER_TESS_EVAL) {
1780 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1781 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1782 }
1783 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1784 pipeline->layout,
1785 keys + i, &codes[i],
1786 &code_sizes[i]);
1787 }
1788 }
1789
1790 if(modules[MESA_SHADER_GEOMETRY]) {
1791 void *gs_copy_code = NULL;
1792 unsigned gs_copy_code_size = 0;
1793 if (!pipeline->gs_copy_shader) {
1794 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1795 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1796 &gs_copy_code_size,
1797 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1798 }
1799
1800 if (pipeline->gs_copy_shader) {
1801 void *code[MESA_SHADER_STAGES] = {0};
1802 unsigned code_size[MESA_SHADER_STAGES] = {0};
1803 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1804
1805 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1806 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1807 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1808
1809 radv_pipeline_cache_insert_shaders(device, cache,
1810 gs_copy_hash,
1811 variants,
1812 (const void**)code,
1813 code_size);
1814 }
1815 free(gs_copy_code);
1816 }
1817
1818 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1819 (const void**)codes, code_sizes);
1820
1821 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1822 free(codes[i]);
1823 if (modules[i]) {
1824 if (!pipeline->device->keep_shader_info)
1825 ralloc_free(nir[i]);
1826
1827 if (radv_can_dump_shader_stats(device, modules[i]))
1828 radv_shader_dump_stats(device,
1829 pipeline->shaders[i],
1830 i, stderr);
1831 }
1832 }
1833
1834 if (fs_m.nir)
1835 ralloc_free(fs_m.nir);
1836 }
1837
1838 static uint32_t
1839 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1840 gl_shader_stage stage, enum chip_class chip_class)
1841 {
1842 bool has_gs = radv_pipeline_has_gs(pipeline);
1843 bool has_tess = radv_pipeline_has_tess(pipeline);
1844 switch (stage) {
1845 case MESA_SHADER_FRAGMENT:
1846 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1847 case MESA_SHADER_VERTEX:
1848 if (chip_class >= GFX9) {
1849 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1850 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1851 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1852 }
1853 if (has_tess)
1854 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1855 else
1856 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1857 case MESA_SHADER_GEOMETRY:
1858 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1859 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1860 case MESA_SHADER_COMPUTE:
1861 return R_00B900_COMPUTE_USER_DATA_0;
1862 case MESA_SHADER_TESS_CTRL:
1863 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1864 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1865 case MESA_SHADER_TESS_EVAL:
1866 if (chip_class >= GFX9) {
1867 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1868 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1869 }
1870 if (has_gs)
1871 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1872 else
1873 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1874 default:
1875 unreachable("unknown shader");
1876 }
1877 }
1878
1879 struct radv_bin_size_entry {
1880 unsigned bpp;
1881 VkExtent2D extent;
1882 };
1883
1884 static VkExtent2D
1885 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1886 {
1887 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1888 {
1889 /* One RB / SE */
1890 {
1891 /* One shader engine */
1892 { 0, {128, 128}},
1893 { 1, { 64, 128}},
1894 { 2, { 32, 128}},
1895 { 3, { 16, 128}},
1896 { 17, { 0, 0}},
1897 { UINT_MAX, { 0, 0}},
1898 },
1899 {
1900 /* Two shader engines */
1901 { 0, {128, 128}},
1902 { 2, { 64, 128}},
1903 { 3, { 32, 128}},
1904 { 5, { 16, 128}},
1905 { 17, { 0, 0}},
1906 { UINT_MAX, { 0, 0}},
1907 },
1908 {
1909 /* Four shader engines */
1910 { 0, {128, 128}},
1911 { 3, { 64, 128}},
1912 { 5, { 16, 128}},
1913 { 17, { 0, 0}},
1914 { UINT_MAX, { 0, 0}},
1915 },
1916 },
1917 {
1918 /* Two RB / SE */
1919 {
1920 /* One shader engine */
1921 { 0, {128, 128}},
1922 { 2, { 64, 128}},
1923 { 3, { 32, 128}},
1924 { 5, { 16, 128}},
1925 { 33, { 0, 0}},
1926 { UINT_MAX, { 0, 0}},
1927 },
1928 {
1929 /* Two shader engines */
1930 { 0, {128, 128}},
1931 { 3, { 64, 128}},
1932 { 5, { 32, 128}},
1933 { 9, { 16, 128}},
1934 { 33, { 0, 0}},
1935 { UINT_MAX, { 0, 0}},
1936 },
1937 {
1938 /* Four shader engines */
1939 { 0, {256, 256}},
1940 { 2, {128, 256}},
1941 { 3, {128, 128}},
1942 { 5, { 64, 128}},
1943 { 9, { 16, 128}},
1944 { 33, { 0, 0}},
1945 { UINT_MAX, { 0, 0}},
1946 },
1947 },
1948 {
1949 /* Four RB / SE */
1950 {
1951 /* One shader engine */
1952 { 0, {128, 256}},
1953 { 2, {128, 128}},
1954 { 3, { 64, 128}},
1955 { 5, { 32, 128}},
1956 { 9, { 16, 128}},
1957 { 33, { 0, 0}},
1958 { UINT_MAX, { 0, 0}},
1959 },
1960 {
1961 /* Two shader engines */
1962 { 0, {256, 256}},
1963 { 2, {128, 256}},
1964 { 3, {128, 128}},
1965 { 5, { 64, 128}},
1966 { 9, { 32, 128}},
1967 { 17, { 16, 128}},
1968 { 33, { 0, 0}},
1969 { UINT_MAX, { 0, 0}},
1970 },
1971 {
1972 /* Four shader engines */
1973 { 0, {256, 512}},
1974 { 2, {256, 256}},
1975 { 3, {128, 256}},
1976 { 5, {128, 128}},
1977 { 9, { 64, 128}},
1978 { 17, { 16, 128}},
1979 { 33, { 0, 0}},
1980 { UINT_MAX, { 0, 0}},
1981 },
1982 },
1983 };
1984 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
1985 {
1986 // One RB / SE
1987 {
1988 // One shader engine
1989 { 0, {128, 256}},
1990 { 2, {128, 128}},
1991 { 4, { 64, 128}},
1992 { 7, { 32, 128}},
1993 { 13, { 16, 128}},
1994 { 49, { 0, 0}},
1995 { UINT_MAX, { 0, 0}},
1996 },
1997 {
1998 // Two shader engines
1999 { 0, {256, 256}},
2000 { 2, {128, 256}},
2001 { 4, {128, 128}},
2002 { 7, { 64, 128}},
2003 { 13, { 32, 128}},
2004 { 25, { 16, 128}},
2005 { 49, { 0, 0}},
2006 { UINT_MAX, { 0, 0}},
2007 },
2008 {
2009 // Four shader engines
2010 { 0, {256, 512}},
2011 { 2, {256, 256}},
2012 { 4, {128, 256}},
2013 { 7, {128, 128}},
2014 { 13, { 64, 128}},
2015 { 25, { 16, 128}},
2016 { 49, { 0, 0}},
2017 { UINT_MAX, { 0, 0}},
2018 },
2019 },
2020 {
2021 // Two RB / SE
2022 {
2023 // One shader engine
2024 { 0, {256, 256}},
2025 { 2, {128, 256}},
2026 { 4, {128, 128}},
2027 { 7, { 64, 128}},
2028 { 13, { 32, 128}},
2029 { 25, { 16, 128}},
2030 { 97, { 0, 0}},
2031 { UINT_MAX, { 0, 0}},
2032 },
2033 {
2034 // Two shader engines
2035 { 0, {256, 512}},
2036 { 2, {256, 256}},
2037 { 4, {128, 256}},
2038 { 7, {128, 128}},
2039 { 13, { 64, 128}},
2040 { 25, { 32, 128}},
2041 { 49, { 16, 128}},
2042 { 97, { 0, 0}},
2043 { UINT_MAX, { 0, 0}},
2044 },
2045 {
2046 // Four shader engines
2047 { 0, {512, 512}},
2048 { 2, {256, 512}},
2049 { 4, {256, 256}},
2050 { 7, {128, 256}},
2051 { 13, {128, 128}},
2052 { 25, { 64, 128}},
2053 { 49, { 16, 128}},
2054 { 97, { 0, 0}},
2055 { UINT_MAX, { 0, 0}},
2056 },
2057 },
2058 {
2059 // Four RB / SE
2060 {
2061 // One shader engine
2062 { 0, {256, 512}},
2063 { 2, {256, 256}},
2064 { 4, {128, 256}},
2065 { 7, {128, 128}},
2066 { 13, { 64, 128}},
2067 { 25, { 32, 128}},
2068 { 49, { 16, 128}},
2069 { UINT_MAX, { 0, 0}},
2070 },
2071 {
2072 // Two shader engines
2073 { 0, {512, 512}},
2074 { 2, {256, 512}},
2075 { 4, {256, 256}},
2076 { 7, {128, 256}},
2077 { 13, {128, 128}},
2078 { 25, { 64, 128}},
2079 { 49, { 32, 128}},
2080 { 97, { 16, 128}},
2081 { UINT_MAX, { 0, 0}},
2082 },
2083 {
2084 // Four shader engines
2085 { 0, {512, 512}},
2086 { 4, {256, 512}},
2087 { 7, {256, 256}},
2088 { 13, {128, 256}},
2089 { 25, {128, 128}},
2090 { 49, { 64, 128}},
2091 { 97, { 16, 128}},
2092 { UINT_MAX, { 0, 0}},
2093 },
2094 },
2095 };
2096
2097 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2098 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2099 VkExtent2D extent = {512, 512};
2100
2101 unsigned log_num_rb_per_se =
2102 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2103 pipeline->device->physical_device->rad_info.max_se);
2104 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2105
2106 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2107 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2108 unsigned effective_samples = total_samples;
2109 unsigned color_bytes_per_pixel = 0;
2110
2111 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2112 if (vkblend) {
2113 for (unsigned i = 0; i < subpass->color_count; i++) {
2114 if (!vkblend->pAttachments[i].colorWriteMask)
2115 continue;
2116
2117 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2118 continue;
2119
2120 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2121 color_bytes_per_pixel += vk_format_get_blocksize(format);
2122 }
2123
2124 /* MSAA images typically don't use all samples all the time. */
2125 if (effective_samples >= 2 && ps_iter_samples <= 1)
2126 effective_samples = 2;
2127 color_bytes_per_pixel *= effective_samples;
2128 }
2129
2130 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2131 while(color_entry->bpp <= color_bytes_per_pixel)
2132 ++color_entry;
2133
2134 extent = color_entry->extent;
2135
2136 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2137 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2138
2139 /* Coefficients taken from AMDVLK */
2140 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2141 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2142 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2143
2144 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2145 while(ds_entry->bpp <= ds_bytes_per_pixel)
2146 ++ds_entry;
2147
2148 extent.width = MIN2(extent.width, ds_entry->extent.width);
2149 extent.height = MIN2(extent.height, ds_entry->extent.height);
2150 }
2151
2152 return extent;
2153 }
2154
2155 static void
2156 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2157 struct radv_pipeline *pipeline,
2158 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2159 {
2160 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2161 return;
2162
2163 uint32_t pa_sc_binner_cntl_0 =
2164 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2165 S_028C44_DISABLE_START_OF_PRIM(1);
2166 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2167
2168 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2169
2170 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2171 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2172 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2173
2174 switch (pipeline->device->physical_device->rad_info.family) {
2175 case CHIP_VEGA10:
2176 case CHIP_VEGA12:
2177 context_states_per_bin = 1;
2178 persistent_states_per_bin = 1;
2179 fpovs_per_batch = 63;
2180 break;
2181 case CHIP_RAVEN:
2182 context_states_per_bin = 6;
2183 persistent_states_per_bin = 32;
2184 fpovs_per_batch = 63;
2185 break;
2186 default:
2187 unreachable("unhandled family while determining binning state.");
2188 }
2189
2190 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2191 pa_sc_binner_cntl_0 =
2192 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2193 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2194 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2195 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2196 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2197 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2198 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2199 S_028C44_DISABLE_START_OF_PRIM(1) |
2200 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2201 S_028C44_OPTIMAL_BIN_SELECTION(1);
2202 }
2203
2204 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2205 pa_sc_binner_cntl_0);
2206 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2207 db_dfsm_control);
2208 }
2209
2210
2211 static void
2212 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2213 struct radv_pipeline *pipeline,
2214 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2215 const struct radv_graphics_pipeline_create_info *extra)
2216 {
2217 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2218 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2219 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2220 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2221 struct radv_render_pass_attachment *attachment = NULL;
2222 uint32_t db_depth_control = 0, db_stencil_control = 0;
2223 uint32_t db_render_control = 0, db_render_override2 = 0;
2224 uint32_t db_render_override = 0;
2225
2226 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2227 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2228
2229 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2230 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2231
2232 if (vkds && has_depth_attachment) {
2233 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2234 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2235 S_028800_ZFUNC(vkds->depthCompareOp) |
2236 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2237
2238 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2239 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2240 }
2241
2242 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2243 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2244 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2245 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2246 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2247 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2248
2249 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2250 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2251 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2252 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2253 }
2254
2255 if (attachment && extra) {
2256 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2257 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2258
2259 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2260 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2261 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2262 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2263 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2264 }
2265
2266 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2267 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2268
2269 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2270 !pCreateInfo->pRasterizationState->depthClampEnable &&
2271 ps->info.info.ps.writes_z) {
2272 /* From VK_EXT_depth_range_unrestricted spec:
2273 *
2274 * "The behavior described in Primitive Clipping still applies.
2275 * If depth clamping is disabled the depth values are still
2276 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2277 * depth clamping is enabled the above equation is ignored and
2278 * the depth values are instead clamped to the VkViewport
2279 * minDepth and maxDepth values, which in the case of this
2280 * extension can be outside of the 0.0 to 1.0 range."
2281 */
2282 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2283 }
2284
2285 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2286 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2287
2288 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2289 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2290 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2291 }
2292
2293 static void
2294 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2295 struct radv_pipeline *pipeline,
2296 const struct radv_blend_state *blend)
2297 {
2298 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2299 radeon_emit_array(cs, blend->cb_blend_control,
2300 8);
2301 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2302 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2303
2304 if (pipeline->device->physical_device->has_rbplus) {
2305
2306 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2307 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2308
2309 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2310 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2311 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2312 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2313 }
2314
2315 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2316
2317 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2318 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2319 }
2320
2321
2322 static void
2323 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2324 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2325 {
2326 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2327
2328 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2329 S_028810_PS_UCP_MODE(3) |
2330 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2331 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2332 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2333 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2334 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2335
2336 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2337 S_0286D4_FLAT_SHADE_ENA(1) |
2338 S_0286D4_PNT_SPRITE_ENA(1) |
2339 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2340 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2341 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2342 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2343 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2344
2345 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2346 S_028BE4_PIX_CENTER(1) | // TODO verify
2347 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2348 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2349
2350 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2351 S_028814_FACE(vkraster->frontFace) |
2352 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2353 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2354 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2355 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2356 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2357 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2358 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2359 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2360 }
2361
2362
2363 static void
2364 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2365 struct radv_pipeline *pipeline)
2366 {
2367 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2368
2369 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2370 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2371 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2372
2373 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2374 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2375
2376 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2377 uint32_t offset;
2378 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2379 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2380 if (loc->sgpr_idx == -1)
2381 return;
2382 assert(loc->num_sgprs == 1);
2383 assert(!loc->indirect);
2384 switch (pipeline->graphics.ms.num_samples) {
2385 default:
2386 offset = 0;
2387 break;
2388 case 2:
2389 offset = 1;
2390 break;
2391 case 4:
2392 offset = 3;
2393 break;
2394 case 8:
2395 offset = 7;
2396 break;
2397 case 16:
2398 offset = 15;
2399 break;
2400 }
2401
2402 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2403 }
2404 }
2405
2406 static void
2407 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2408 const struct radv_pipeline *pipeline)
2409 {
2410 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2411
2412 uint32_t vgt_primitiveid_en = false;
2413 uint32_t vgt_gs_mode = 0;
2414
2415 if (radv_pipeline_has_gs(pipeline)) {
2416 const struct radv_shader_variant *gs =
2417 pipeline->shaders[MESA_SHADER_GEOMETRY];
2418
2419 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2420 pipeline->device->physical_device->rad_info.chip_class);
2421 } else if (outinfo->export_prim_id) {
2422 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2423 vgt_primitiveid_en = true;
2424 }
2425
2426 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2427 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2428 }
2429
2430 static void
2431 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2432 struct radv_pipeline *pipeline,
2433 struct radv_shader_variant *shader)
2434 {
2435 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2436
2437 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2438 radeon_emit(cs, va >> 8);
2439 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2440 radeon_emit(cs, shader->rsrc1);
2441 radeon_emit(cs, shader->rsrc2);
2442
2443 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2444 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2445 clip_dist_mask = outinfo->clip_dist_mask;
2446 cull_dist_mask = outinfo->cull_dist_mask;
2447 total_mask = clip_dist_mask | cull_dist_mask;
2448 bool misc_vec_ena = outinfo->writes_pointsize ||
2449 outinfo->writes_layer ||
2450 outinfo->writes_viewport_index;
2451
2452 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2453 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2454
2455 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2456 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2457 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2458 V_02870C_SPI_SHADER_4COMP :
2459 V_02870C_SPI_SHADER_NONE) |
2460 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2461 V_02870C_SPI_SHADER_4COMP :
2462 V_02870C_SPI_SHADER_NONE) |
2463 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2464 V_02870C_SPI_SHADER_4COMP :
2465 V_02870C_SPI_SHADER_NONE));
2466
2467 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2468 S_028818_VTX_W0_FMT(1) |
2469 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2470 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2471 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2472
2473 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2474 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2475 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2476 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2477 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2478 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2479 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2480 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2481 cull_dist_mask << 8 |
2482 clip_dist_mask);
2483
2484 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2485 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2486 outinfo->writes_viewport_index);
2487 }
2488
2489 static void
2490 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2491 struct radv_pipeline *pipeline,
2492 struct radv_shader_variant *shader)
2493 {
2494 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2495
2496 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2497 radeon_emit(cs, va >> 8);
2498 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2499 radeon_emit(cs, shader->rsrc1);
2500 radeon_emit(cs, shader->rsrc2);
2501 }
2502
2503 static void
2504 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2505 struct radv_pipeline *pipeline,
2506 struct radv_shader_variant *shader,
2507 const struct radv_tessellation_state *tess)
2508 {
2509 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2510 uint32_t rsrc2 = shader->rsrc2;
2511
2512 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2513 radeon_emit(cs, va >> 8);
2514 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2515
2516 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2517 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2518 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2519 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2520
2521 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2522 radeon_emit(cs, shader->rsrc1);
2523 radeon_emit(cs, rsrc2);
2524 }
2525
2526 static void
2527 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2528 struct radv_pipeline *pipeline,
2529 struct radv_shader_variant *shader,
2530 const struct radv_tessellation_state *tess)
2531 {
2532 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2533
2534 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2535 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2536 radeon_emit(cs, va >> 8);
2537 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2538
2539 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2540 radeon_emit(cs, shader->rsrc1);
2541 radeon_emit(cs, shader->rsrc2 |
2542 S_00B42C_LDS_SIZE(tess->lds_size));
2543 } else {
2544 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2545 radeon_emit(cs, va >> 8);
2546 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2547 radeon_emit(cs, shader->rsrc1);
2548 radeon_emit(cs, shader->rsrc2);
2549 }
2550 }
2551
2552 static void
2553 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2554 struct radv_pipeline *pipeline,
2555 const struct radv_tessellation_state *tess)
2556 {
2557 struct radv_shader_variant *vs;
2558
2559 /* Skip shaders merged into HS/GS */
2560 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2561 if (!vs)
2562 return;
2563
2564 if (vs->info.vs.as_ls)
2565 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2566 else if (vs->info.vs.as_es)
2567 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2568 else
2569 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2570 }
2571
2572 static void
2573 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2574 struct radv_pipeline *pipeline,
2575 const struct radv_tessellation_state *tess)
2576 {
2577 if (!radv_pipeline_has_tess(pipeline))
2578 return;
2579
2580 struct radv_shader_variant *tes, *tcs;
2581
2582 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2583 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2584
2585 if (tes) {
2586 if (tes->info.tes.as_es)
2587 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2588 else
2589 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2590 }
2591
2592 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2593
2594 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2595 tess->tf_param);
2596
2597 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2598 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2599 tess->ls_hs_config);
2600 else
2601 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2602 tess->ls_hs_config);
2603 }
2604
2605 static void
2606 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2607 struct radv_pipeline *pipeline,
2608 const struct radv_gs_state *gs_state)
2609 {
2610 struct radv_shader_variant *gs;
2611 uint64_t va;
2612
2613 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2614 if (!gs)
2615 return;
2616
2617 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2618
2619 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2620 radeon_emit(cs, gsvs_itemsize);
2621 radeon_emit(cs, gsvs_itemsize);
2622 radeon_emit(cs, gsvs_itemsize);
2623
2624 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2625
2626 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2627
2628 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2629 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2630 radeon_emit(cs, gs_vert_itemsize >> 2);
2631 radeon_emit(cs, 0);
2632 radeon_emit(cs, 0);
2633 radeon_emit(cs, 0);
2634
2635 uint32_t gs_num_invocations = gs->info.gs.invocations;
2636 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2637 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2638 S_028B90_ENABLE(gs_num_invocations > 0));
2639
2640 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2641 gs_state->vgt_esgs_ring_itemsize);
2642
2643 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2644
2645 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2646 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2647 radeon_emit(cs, va >> 8);
2648 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
2649
2650 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2651 radeon_emit(cs, gs->rsrc1);
2652 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2653
2654 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2655 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2656 } else {
2657 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2658 radeon_emit(cs, va >> 8);
2659 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
2660 radeon_emit(cs, gs->rsrc1);
2661 radeon_emit(cs, gs->rsrc2);
2662 }
2663
2664 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2665 }
2666
2667 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2668 {
2669 uint32_t ps_input_cntl;
2670 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2671 ps_input_cntl = S_028644_OFFSET(offset);
2672 if (flat_shade)
2673 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2674 } else {
2675 /* The input is a DEFAULT_VAL constant. */
2676 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2677 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2678 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2679 ps_input_cntl = S_028644_OFFSET(0x20) |
2680 S_028644_DEFAULT_VAL(offset);
2681 }
2682 return ps_input_cntl;
2683 }
2684
2685 static void
2686 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2687 struct radv_pipeline *pipeline)
2688 {
2689 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2690 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2691 uint32_t ps_input_cntl[32];
2692
2693 unsigned ps_offset = 0;
2694
2695 if (ps->info.info.ps.prim_id_input) {
2696 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2697 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2698 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2699 ++ps_offset;
2700 }
2701 }
2702
2703 if (ps->info.info.ps.layer_input ||
2704 ps->info.info.ps.uses_input_attachments ||
2705 ps->info.info.needs_multiview_view_index) {
2706 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2707 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2708 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2709 else
2710 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2711 ++ps_offset;
2712 }
2713
2714 if (ps->info.info.ps.has_pcoord) {
2715 unsigned val;
2716 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2717 ps_input_cntl[ps_offset] = val;
2718 ps_offset++;
2719 }
2720
2721 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2722 unsigned vs_offset;
2723 bool flat_shade;
2724 if (!(ps->info.fs.input_mask & (1u << i)))
2725 continue;
2726
2727 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2728 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2729 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2730 ++ps_offset;
2731 continue;
2732 }
2733
2734 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2735
2736 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2737 ++ps_offset;
2738 }
2739
2740 if (ps_offset) {
2741 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2742 for (unsigned i = 0; i < ps_offset; i++) {
2743 radeon_emit(cs, ps_input_cntl[i]);
2744 }
2745 }
2746 }
2747
2748 static uint32_t
2749 radv_compute_db_shader_control(const struct radv_device *device,
2750 const struct radv_shader_variant *ps)
2751 {
2752 unsigned z_order;
2753 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2754 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2755 else
2756 z_order = V_02880C_LATE_Z;
2757
2758 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
2759 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
2760 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2761 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
2762 S_02880C_Z_ORDER(z_order) |
2763 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2764 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2765 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
2766 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
2767 }
2768
2769 static void
2770 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2771 struct radv_pipeline *pipeline)
2772 {
2773 struct radv_shader_variant *ps;
2774 uint64_t va;
2775 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2776
2777 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2778 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2779
2780 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2781 radeon_emit(cs, va >> 8);
2782 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
2783 radeon_emit(cs, ps->rsrc1);
2784 radeon_emit(cs, ps->rsrc2);
2785
2786 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2787 radv_compute_db_shader_control(pipeline->device, ps));
2788
2789 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2790 ps->config.spi_ps_input_ena);
2791
2792 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2793 ps->config.spi_ps_input_addr);
2794
2795 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2796 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2797
2798 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2799
2800 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2801 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
2802 ps->info.info.ps.writes_stencil,
2803 ps->info.info.ps.writes_sample_mask));
2804
2805 if (pipeline->device->dfsm_allowed) {
2806 /* optimise this? */
2807 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2808 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2809 }
2810 }
2811
2812 static void
2813 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2814 struct radv_pipeline *pipeline)
2815 {
2816 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2817 return;
2818
2819 unsigned vtx_reuse_depth = 30;
2820 if (radv_pipeline_has_tess(pipeline) &&
2821 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2822 vtx_reuse_depth = 14;
2823 }
2824 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2825 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2826 }
2827
2828 static uint32_t
2829 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
2830 {
2831 uint32_t stages = 0;
2832 if (radv_pipeline_has_tess(pipeline)) {
2833 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2834 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2835
2836 if (radv_pipeline_has_gs(pipeline))
2837 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2838 S_028B54_GS_EN(1) |
2839 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2840 else
2841 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2842
2843 } else if (radv_pipeline_has_gs(pipeline))
2844 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2845 S_028B54_GS_EN(1) |
2846 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2847
2848 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
2849 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2850
2851 return stages;
2852 }
2853
2854 static uint32_t
2855 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
2856 {
2857 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
2858 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
2859
2860 if (!discard_rectangle_info)
2861 return 0xffff;
2862
2863 unsigned mask = 0;
2864
2865 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
2866 /* Interpret i as a bitmask, and then set the bit in the mask if
2867 * that combination of rectangles in which the pixel is contained
2868 * should pass the cliprect test. */
2869 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
2870
2871 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
2872 !relevant_subset)
2873 continue;
2874
2875 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
2876 relevant_subset)
2877 continue;
2878
2879 mask |= 1u << i;
2880 }
2881
2882 return mask;
2883 }
2884
2885 static void
2886 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2887 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2888 const struct radv_graphics_pipeline_create_info *extra,
2889 const struct radv_blend_state *blend,
2890 const struct radv_tessellation_state *tess,
2891 const struct radv_gs_state *gs,
2892 unsigned prim, unsigned gs_out)
2893 {
2894 pipeline->cs.buf = malloc(4 * 256);
2895 pipeline->cs.max_dw = 256;
2896
2897 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2898 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
2899 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
2900 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2901 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
2902 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
2903 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
2904 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
2905 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2906 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2907 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2908 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2909
2910 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2911 S_0286E8_WAVES(pipeline->max_waves) |
2912 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2913
2914 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
2915
2916 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2917 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
2918 } else {
2919 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
2920 }
2921 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
2922
2923 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
2924
2925 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2926 }
2927
2928 static struct radv_ia_multi_vgt_param_helpers
2929 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
2930 const struct radv_tessellation_state *tess,
2931 uint32_t prim)
2932 {
2933 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
2934 const struct radv_device *device = pipeline->device;
2935
2936 if (radv_pipeline_has_tess(pipeline))
2937 ia_multi_vgt_param.primgroup_size = tess->num_patches;
2938 else if (radv_pipeline_has_gs(pipeline))
2939 ia_multi_vgt_param.primgroup_size = 64;
2940 else
2941 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
2942
2943 ia_multi_vgt_param.partial_es_wave = false;
2944 if (pipeline->device->has_distributed_tess) {
2945 if (radv_pipeline_has_gs(pipeline)) {
2946 if (device->physical_device->rad_info.chip_class <= VI)
2947 ia_multi_vgt_param.partial_es_wave = true;
2948 }
2949 }
2950 /* GS requirement. */
2951 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
2952 ia_multi_vgt_param.partial_es_wave = true;
2953
2954 ia_multi_vgt_param.wd_switch_on_eop = false;
2955 if (device->physical_device->rad_info.chip_class >= CIK) {
2956 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2957 * 4 shader engines. Set 1 to pass the assertion below.
2958 * The other cases are hardware requirements. */
2959 if (device->physical_device->rad_info.max_se < 4 ||
2960 prim == V_008958_DI_PT_POLYGON ||
2961 prim == V_008958_DI_PT_LINELOOP ||
2962 prim == V_008958_DI_PT_TRIFAN ||
2963 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
2964 (pipeline->graphics.prim_restart_enable &&
2965 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
2966 (prim != V_008958_DI_PT_POINTLIST &&
2967 prim != V_008958_DI_PT_LINESTRIP &&
2968 prim != V_008958_DI_PT_TRISTRIP))))
2969 ia_multi_vgt_param.wd_switch_on_eop = true;
2970 }
2971
2972 ia_multi_vgt_param.ia_switch_on_eoi = false;
2973 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
2974 ia_multi_vgt_param.ia_switch_on_eoi = true;
2975 if (radv_pipeline_has_gs(pipeline) &&
2976 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
2977 ia_multi_vgt_param.ia_switch_on_eoi = true;
2978 if (radv_pipeline_has_tess(pipeline)) {
2979 /* SWITCH_ON_EOI must be set if PrimID is used. */
2980 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
2981 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
2982 ia_multi_vgt_param.ia_switch_on_eoi = true;
2983 }
2984
2985 ia_multi_vgt_param.partial_vs_wave = false;
2986 if (radv_pipeline_has_tess(pipeline)) {
2987 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2988 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2989 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2990 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2991 radv_pipeline_has_gs(pipeline))
2992 ia_multi_vgt_param.partial_vs_wave = true;
2993 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2994 if (device->has_distributed_tess) {
2995 if (radv_pipeline_has_gs(pipeline)) {
2996 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2997 device->physical_device->rad_info.family == CHIP_FIJI ||
2998 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2999 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3000 device->physical_device->rad_info.family == CHIP_POLARIS12)
3001 ia_multi_vgt_param.partial_vs_wave = true;
3002 } else {
3003 ia_multi_vgt_param.partial_vs_wave = true;
3004 }
3005 }
3006 }
3007
3008 ia_multi_vgt_param.base =
3009 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3010 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3011 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3012 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3013 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3014
3015 return ia_multi_vgt_param;
3016 }
3017
3018
3019 static void
3020 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3021 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3022 {
3023 const VkPipelineVertexInputStateCreateInfo *vi_info =
3024 pCreateInfo->pVertexInputState;
3025 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3026
3027 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3028 const VkVertexInputAttributeDescription *desc =
3029 &vi_info->pVertexAttributeDescriptions[i];
3030 unsigned loc = desc->location;
3031 const struct vk_format_description *format_desc;
3032 int first_non_void;
3033 uint32_t num_format, data_format;
3034 format_desc = vk_format_description(desc->format);
3035 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3036
3037 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3038 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3039
3040 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3041 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3042 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3043 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3044 S_008F0C_NUM_FORMAT(num_format) |
3045 S_008F0C_DATA_FORMAT(data_format);
3046 velems->format_size[loc] = format_desc->block.bits / 8;
3047 velems->offset[loc] = desc->offset;
3048 velems->binding[loc] = desc->binding;
3049 velems->count = MAX2(velems->count, loc + 1);
3050 }
3051
3052 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3053 const VkVertexInputBindingDescription *desc =
3054 &vi_info->pVertexBindingDescriptions[i];
3055
3056 pipeline->binding_stride[desc->binding] = desc->stride;
3057 }
3058 }
3059
3060 static VkResult
3061 radv_pipeline_init(struct radv_pipeline *pipeline,
3062 struct radv_device *device,
3063 struct radv_pipeline_cache *cache,
3064 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3065 const struct radv_graphics_pipeline_create_info *extra,
3066 const VkAllocationCallbacks *alloc)
3067 {
3068 VkResult result;
3069 bool has_view_index = false;
3070
3071 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3072 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3073 if (subpass->view_mask)
3074 has_view_index = true;
3075 if (alloc == NULL)
3076 alloc = &device->alloc;
3077
3078 pipeline->device = device;
3079 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3080 assert(pipeline->layout);
3081
3082 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3083
3084 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3085 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3086 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3087 pStages[stage] = &pCreateInfo->pStages[i];
3088 }
3089
3090 radv_create_shaders(pipeline, device, cache,
3091 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3092 pStages);
3093
3094 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3095 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
3096 uint32_t gs_out;
3097 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3098
3099 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3100
3101 if (radv_pipeline_has_gs(pipeline)) {
3102 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3103 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3104 } else {
3105 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3106 }
3107 if (extra && extra->use_rectlist) {
3108 prim = V_008958_DI_PT_RECTLIST;
3109 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3110 pipeline->graphics.can_use_guardband = true;
3111 }
3112 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3113 /* prim vertex count will need TESS changes */
3114 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3115
3116 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3117
3118 /* Ensure that some export memory is always allocated, for two reasons:
3119 *
3120 * 1) Correctness: The hardware ignores the EXEC mask if no export
3121 * memory is allocated, so KILL and alpha test do not work correctly
3122 * without this.
3123 * 2) Performance: Every shader needs at least a NULL export, even when
3124 * it writes no color/depth output. The NULL export instruction
3125 * stalls without this setting.
3126 *
3127 * Don't add this to CB_SHADER_MASK.
3128 */
3129 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3130 if (!blend.spi_shader_col_format) {
3131 if (!ps->info.info.ps.writes_z &&
3132 !ps->info.info.ps.writes_stencil &&
3133 !ps->info.info.ps.writes_sample_mask)
3134 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3135 }
3136
3137 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3138 if (pipeline->shaders[i]) {
3139 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3140 }
3141 }
3142
3143 struct radv_gs_state gs = {0};
3144 if (radv_pipeline_has_gs(pipeline)) {
3145 gs = calculate_gs_info(pCreateInfo, pipeline);
3146 calculate_gs_ring_sizes(pipeline, &gs);
3147 }
3148
3149 struct radv_tessellation_state tess = {0};
3150 if (radv_pipeline_has_tess(pipeline)) {
3151 if (prim == V_008958_DI_PT_PATCH) {
3152 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3153 pipeline->graphics.prim_vertex_count.incr = 1;
3154 }
3155 tess = calculate_tess_state(pipeline, pCreateInfo);
3156 }
3157
3158 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3159
3160 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3161
3162 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3163 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3164
3165 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3166 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3167 if (loc->sgpr_idx != -1) {
3168 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3169 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3170 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3171 pipeline->graphics.vtx_emit_num = 3;
3172 else
3173 pipeline->graphics.vtx_emit_num = 2;
3174 }
3175
3176 result = radv_pipeline_scratch_init(device, pipeline);
3177 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3178
3179 return result;
3180 }
3181
3182 VkResult
3183 radv_graphics_pipeline_create(
3184 VkDevice _device,
3185 VkPipelineCache _cache,
3186 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3187 const struct radv_graphics_pipeline_create_info *extra,
3188 const VkAllocationCallbacks *pAllocator,
3189 VkPipeline *pPipeline)
3190 {
3191 RADV_FROM_HANDLE(radv_device, device, _device);
3192 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3193 struct radv_pipeline *pipeline;
3194 VkResult result;
3195
3196 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3197 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3198 if (pipeline == NULL)
3199 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3200
3201 result = radv_pipeline_init(pipeline, device, cache,
3202 pCreateInfo, extra, pAllocator);
3203 if (result != VK_SUCCESS) {
3204 radv_pipeline_destroy(device, pipeline, pAllocator);
3205 return result;
3206 }
3207
3208 *pPipeline = radv_pipeline_to_handle(pipeline);
3209
3210 return VK_SUCCESS;
3211 }
3212
3213 VkResult radv_CreateGraphicsPipelines(
3214 VkDevice _device,
3215 VkPipelineCache pipelineCache,
3216 uint32_t count,
3217 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3218 const VkAllocationCallbacks* pAllocator,
3219 VkPipeline* pPipelines)
3220 {
3221 VkResult result = VK_SUCCESS;
3222 unsigned i = 0;
3223
3224 for (; i < count; i++) {
3225 VkResult r;
3226 r = radv_graphics_pipeline_create(_device,
3227 pipelineCache,
3228 &pCreateInfos[i],
3229 NULL, pAllocator, &pPipelines[i]);
3230 if (r != VK_SUCCESS) {
3231 result = r;
3232 pPipelines[i] = VK_NULL_HANDLE;
3233 }
3234 }
3235
3236 return result;
3237 }
3238
3239
3240 static void
3241 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3242 {
3243 struct radv_shader_variant *compute_shader;
3244 struct radv_device *device = pipeline->device;
3245 unsigned compute_resource_limits;
3246 unsigned waves_per_threadgroup;
3247 uint64_t va;
3248
3249 pipeline->cs.buf = malloc(20 * 4);
3250 pipeline->cs.max_dw = 20;
3251
3252 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3253 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3254
3255 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3256 radeon_emit(&pipeline->cs, va >> 8);
3257 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3258
3259 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3260 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3261 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3262
3263 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3264 S_00B860_WAVES(pipeline->max_waves) |
3265 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3266
3267 /* Calculate best compute resource limits. */
3268 waves_per_threadgroup =
3269 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3270 compute_shader->info.cs.block_size[1] *
3271 compute_shader->info.cs.block_size[2], 64);
3272 compute_resource_limits =
3273 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3274
3275 if (device->physical_device->rad_info.chip_class >= CIK) {
3276 unsigned num_cu_per_se =
3277 device->physical_device->rad_info.num_good_compute_units /
3278 device->physical_device->rad_info.max_se;
3279
3280 /* Force even distribution on all SIMDs in CU if the workgroup
3281 * size is 64. This has shown some good improvements if # of
3282 * CUs per SE is not a multiple of 4.
3283 */
3284 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3285 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3286 }
3287
3288 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3289 compute_resource_limits);
3290
3291 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3292 radeon_emit(&pipeline->cs,
3293 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3294 radeon_emit(&pipeline->cs,
3295 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3296 radeon_emit(&pipeline->cs,
3297 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3298
3299 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3300 }
3301
3302 static VkResult radv_compute_pipeline_create(
3303 VkDevice _device,
3304 VkPipelineCache _cache,
3305 const VkComputePipelineCreateInfo* pCreateInfo,
3306 const VkAllocationCallbacks* pAllocator,
3307 VkPipeline* pPipeline)
3308 {
3309 RADV_FROM_HANDLE(radv_device, device, _device);
3310 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3311 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3312 struct radv_pipeline *pipeline;
3313 VkResult result;
3314
3315 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3316 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3317 if (pipeline == NULL)
3318 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3319
3320 pipeline->device = device;
3321 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3322 assert(pipeline->layout);
3323
3324 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3325 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3326
3327 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3328 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3329 result = radv_pipeline_scratch_init(device, pipeline);
3330 if (result != VK_SUCCESS) {
3331 radv_pipeline_destroy(device, pipeline, pAllocator);
3332 return result;
3333 }
3334
3335 radv_compute_generate_pm4(pipeline);
3336
3337 *pPipeline = radv_pipeline_to_handle(pipeline);
3338
3339 return VK_SUCCESS;
3340 }
3341
3342 VkResult radv_CreateComputePipelines(
3343 VkDevice _device,
3344 VkPipelineCache pipelineCache,
3345 uint32_t count,
3346 const VkComputePipelineCreateInfo* pCreateInfos,
3347 const VkAllocationCallbacks* pAllocator,
3348 VkPipeline* pPipelines)
3349 {
3350 VkResult result = VK_SUCCESS;
3351
3352 unsigned i = 0;
3353 for (; i < count; i++) {
3354 VkResult r;
3355 r = radv_compute_pipeline_create(_device, pipelineCache,
3356 &pCreateInfos[i],
3357 pAllocator, &pPipelines[i]);
3358 if (r != VK_SUCCESS) {
3359 result = r;
3360 pPipelines[i] = VK_NULL_HANDLE;
3361 }
3362 }
3363
3364 return result;
3365 }