2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
33 #include "radv_shader.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
52 struct radv_blend_state
{
53 uint32_t cb_color_control
;
54 uint32_t cb_target_mask
;
55 uint32_t sx_mrt_blend_opt
[8];
56 uint32_t cb_blend_control
[8];
58 uint32_t spi_shader_col_format
;
59 uint32_t cb_shader_mask
;
60 uint32_t db_alpha_to_mask
;
63 struct radv_tessellation_state
{
64 uint32_t ls_hs_config
;
65 uint32_t tcs_in_layout
;
66 uint32_t tcs_out_layout
;
67 uint32_t tcs_out_offsets
;
68 uint32_t offchip_layout
;
71 unsigned num_tcs_input_cp
;
76 radv_pipeline_destroy(struct radv_device
*device
,
77 struct radv_pipeline
*pipeline
,
78 const VkAllocationCallbacks
* allocator
)
80 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
81 if (pipeline
->shaders
[i
])
82 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
84 if (pipeline
->gs_copy_shader
)
85 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
88 free(pipeline
->cs
.buf
);
89 vk_free2(&device
->alloc
, allocator
, pipeline
);
92 void radv_DestroyPipeline(
95 const VkAllocationCallbacks
* pAllocator
)
97 RADV_FROM_HANDLE(radv_device
, device
, _device
);
98 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
103 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
106 static void radv_dump_pipeline_stats(struct radv_device
*device
, struct radv_pipeline
*pipeline
)
110 for (i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
111 if (!pipeline
->shaders
[i
])
114 radv_shader_dump_stats(device
, pipeline
->shaders
[i
], i
, stderr
);
118 static uint32_t get_hash_flags(struct radv_device
*device
)
120 uint32_t hash_flags
= 0;
122 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
123 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
124 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
125 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
130 radv_pipeline_scratch_init(struct radv_device
*device
,
131 struct radv_pipeline
*pipeline
)
133 unsigned scratch_bytes_per_wave
= 0;
134 unsigned max_waves
= 0;
135 unsigned min_waves
= 1;
137 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
138 if (pipeline
->shaders
[i
]) {
139 unsigned max_stage_waves
= device
->scratch_waves
;
141 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
142 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
144 max_stage_waves
= MIN2(max_stage_waves
,
145 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
146 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
147 max_waves
= MAX2(max_waves
, max_stage_waves
);
151 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
152 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
153 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
154 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
155 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
158 if (scratch_bytes_per_wave
)
159 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
161 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
162 /* Not really true at this moment, but will be true on first
163 * execution. Avoid having hanging shaders. */
164 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
166 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
167 pipeline
->max_waves
= max_waves
;
171 static uint32_t si_translate_blend_function(VkBlendOp op
)
174 case VK_BLEND_OP_ADD
:
175 return V_028780_COMB_DST_PLUS_SRC
;
176 case VK_BLEND_OP_SUBTRACT
:
177 return V_028780_COMB_SRC_MINUS_DST
;
178 case VK_BLEND_OP_REVERSE_SUBTRACT
:
179 return V_028780_COMB_DST_MINUS_SRC
;
180 case VK_BLEND_OP_MIN
:
181 return V_028780_COMB_MIN_DST_SRC
;
182 case VK_BLEND_OP_MAX
:
183 return V_028780_COMB_MAX_DST_SRC
;
189 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
192 case VK_BLEND_FACTOR_ZERO
:
193 return V_028780_BLEND_ZERO
;
194 case VK_BLEND_FACTOR_ONE
:
195 return V_028780_BLEND_ONE
;
196 case VK_BLEND_FACTOR_SRC_COLOR
:
197 return V_028780_BLEND_SRC_COLOR
;
198 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
199 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
200 case VK_BLEND_FACTOR_DST_COLOR
:
201 return V_028780_BLEND_DST_COLOR
;
202 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
203 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
204 case VK_BLEND_FACTOR_SRC_ALPHA
:
205 return V_028780_BLEND_SRC_ALPHA
;
206 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
207 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
208 case VK_BLEND_FACTOR_DST_ALPHA
:
209 return V_028780_BLEND_DST_ALPHA
;
210 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
211 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
212 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
213 return V_028780_BLEND_CONSTANT_COLOR
;
214 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
215 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
216 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
217 return V_028780_BLEND_CONSTANT_ALPHA
;
218 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
219 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
220 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
221 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
222 case VK_BLEND_FACTOR_SRC1_COLOR
:
223 return V_028780_BLEND_SRC1_COLOR
;
224 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
225 return V_028780_BLEND_INV_SRC1_COLOR
;
226 case VK_BLEND_FACTOR_SRC1_ALPHA
:
227 return V_028780_BLEND_SRC1_ALPHA
;
228 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
229 return V_028780_BLEND_INV_SRC1_ALPHA
;
235 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
238 case VK_BLEND_OP_ADD
:
239 return V_028760_OPT_COMB_ADD
;
240 case VK_BLEND_OP_SUBTRACT
:
241 return V_028760_OPT_COMB_SUBTRACT
;
242 case VK_BLEND_OP_REVERSE_SUBTRACT
:
243 return V_028760_OPT_COMB_REVSUBTRACT
;
244 case VK_BLEND_OP_MIN
:
245 return V_028760_OPT_COMB_MIN
;
246 case VK_BLEND_OP_MAX
:
247 return V_028760_OPT_COMB_MAX
;
249 return V_028760_OPT_COMB_BLEND_DISABLED
;
253 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
256 case VK_BLEND_FACTOR_ZERO
:
257 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
258 case VK_BLEND_FACTOR_ONE
:
259 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
260 case VK_BLEND_FACTOR_SRC_COLOR
:
261 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
262 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
263 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
264 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
265 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
266 case VK_BLEND_FACTOR_SRC_ALPHA
:
267 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
268 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
269 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
270 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
271 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
272 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
274 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
279 * Get rid of DST in the blend factors by commuting the operands:
280 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
282 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
283 unsigned *dst_factor
, unsigned expected_dst
,
284 unsigned replacement_src
)
286 if (*src_factor
== expected_dst
&&
287 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
288 *src_factor
= VK_BLEND_FACTOR_ZERO
;
289 *dst_factor
= replacement_src
;
291 /* Commuting the operands requires reversing subtractions. */
292 if (*func
== VK_BLEND_OP_SUBTRACT
)
293 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
294 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
295 *func
= VK_BLEND_OP_SUBTRACT
;
299 static bool si_blend_factor_uses_dst(unsigned factor
)
301 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
302 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
303 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
304 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
305 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
308 static bool is_dual_src(VkBlendFactor factor
)
311 case VK_BLEND_FACTOR_SRC1_COLOR
:
312 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
313 case VK_BLEND_FACTOR_SRC1_ALPHA
:
314 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
321 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
323 bool blend_need_alpha
)
325 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
326 unsigned format
, ntype
, swap
;
328 /* Alpha is needed for alpha-to-coverage.
329 * Blending may be with or without alpha.
331 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
332 unsigned alpha
= 0; /* exports alpha, but may not support blending */
333 unsigned blend
= 0; /* supports blending, but may not export alpha */
334 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
336 format
= radv_translate_colorformat(vk_format
);
337 ntype
= radv_translate_color_numformat(vk_format
, desc
,
338 vk_format_get_first_non_void_channel(vk_format
));
339 swap
= radv_translate_colorswap(vk_format
, false);
341 /* Choose the SPI color formats. These are required values for Stoney/RB+.
342 * Other chips have multiple choices, though they are not necessarily better.
345 case V_028C70_COLOR_5_6_5
:
346 case V_028C70_COLOR_1_5_5_5
:
347 case V_028C70_COLOR_5_5_5_1
:
348 case V_028C70_COLOR_4_4_4_4
:
349 case V_028C70_COLOR_10_11_11
:
350 case V_028C70_COLOR_11_11_10
:
351 case V_028C70_COLOR_8
:
352 case V_028C70_COLOR_8_8
:
353 case V_028C70_COLOR_8_8_8_8
:
354 case V_028C70_COLOR_10_10_10_2
:
355 case V_028C70_COLOR_2_10_10_10
:
356 if (ntype
== V_028C70_NUMBER_UINT
)
357 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
358 else if (ntype
== V_028C70_NUMBER_SINT
)
359 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
361 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
364 case V_028C70_COLOR_16
:
365 case V_028C70_COLOR_16_16
:
366 case V_028C70_COLOR_16_16_16_16
:
367 if (ntype
== V_028C70_NUMBER_UNORM
||
368 ntype
== V_028C70_NUMBER_SNORM
) {
369 /* UNORM16 and SNORM16 don't support blending */
370 if (ntype
== V_028C70_NUMBER_UNORM
)
371 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
373 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
375 /* Use 32 bits per channel for blending. */
376 if (format
== V_028C70_COLOR_16
) {
377 if (swap
== V_028C70_SWAP_STD
) { /* R */
378 blend
= V_028714_SPI_SHADER_32_R
;
379 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
380 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
381 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
384 } else if (format
== V_028C70_COLOR_16_16
) {
385 if (swap
== V_028C70_SWAP_STD
) { /* RG */
386 blend
= V_028714_SPI_SHADER_32_GR
;
387 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
388 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
389 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
392 } else /* 16_16_16_16 */
393 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
394 } else if (ntype
== V_028C70_NUMBER_UINT
)
395 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
396 else if (ntype
== V_028C70_NUMBER_SINT
)
397 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
398 else if (ntype
== V_028C70_NUMBER_FLOAT
)
399 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
404 case V_028C70_COLOR_32
:
405 if (swap
== V_028C70_SWAP_STD
) { /* R */
406 blend
= normal
= V_028714_SPI_SHADER_32_R
;
407 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
408 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
409 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
414 case V_028C70_COLOR_32_32
:
415 if (swap
== V_028C70_SWAP_STD
) { /* RG */
416 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
417 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
418 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
419 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
424 case V_028C70_COLOR_32_32_32_32
:
425 case V_028C70_COLOR_8_24
:
426 case V_028C70_COLOR_24_8
:
427 case V_028C70_COLOR_X24_8_32_FLOAT
:
428 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
432 unreachable("unhandled blend format");
435 if (blend_enable
&& blend_need_alpha
)
437 else if(blend_need_alpha
)
439 else if(blend_enable
)
446 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
447 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
448 uint32_t blend_enable
,
449 uint32_t blend_need_alpha
,
450 bool single_cb_enable
,
451 bool blend_mrt0_is_dual_src
,
452 struct radv_blend_state
*blend
)
454 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
455 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
456 unsigned col_format
= 0;
458 for (unsigned i
= 0; i
< (single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
461 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
462 cf
= V_028714_SPI_SHADER_ZERO
;
464 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
466 cf
= si_choose_spi_color_format(attachment
->format
,
467 blend_enable
& (1 << i
),
468 blend_need_alpha
& (1 << i
));
471 col_format
|= cf
<< (4 * i
);
474 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
476 if (blend_mrt0_is_dual_src
)
477 col_format
|= (col_format
& 0xf) << 4;
478 blend
->spi_shader_col_format
= col_format
;
482 format_is_int8(VkFormat format
)
484 const struct vk_format_description
*desc
= vk_format_description(format
);
485 int channel
= vk_format_get_first_non_void_channel(format
);
487 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
488 desc
->channel
[channel
].size
== 8;
492 format_is_int10(VkFormat format
)
494 const struct vk_format_description
*desc
= vk_format_description(format
);
496 if (desc
->nr_channels
!= 4)
498 for (unsigned i
= 0; i
< 4; i
++) {
499 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
505 unsigned radv_format_meta_fs_key(VkFormat format
)
507 unsigned col_format
= si_choose_spi_color_format(format
, false, false) - 1;
508 bool is_int8
= format_is_int8(format
);
509 bool is_int10
= format_is_int10(format
);
511 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
515 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
516 unsigned *is_int8
, unsigned *is_int10
)
518 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
519 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
523 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
524 struct radv_render_pass_attachment
*attachment
;
526 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
529 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
531 if (format_is_int8(attachment
->format
))
533 if (format_is_int10(attachment
->format
))
538 static struct radv_blend_state
539 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
540 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
541 const struct radv_graphics_pipeline_create_info
*extra
)
543 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
544 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
545 struct radv_blend_state blend
= {0};
546 unsigned mode
= V_028808_CB_NORMAL
;
547 uint32_t blend_enable
= 0, blend_need_alpha
= 0;
548 bool blend_mrt0_is_dual_src
= false;
550 bool single_cb_enable
= false;
555 if (extra
&& extra
->custom_blend_mode
) {
556 single_cb_enable
= true;
557 mode
= extra
->custom_blend_mode
;
559 blend
.cb_color_control
= 0;
560 if (vkblend
->logicOpEnable
)
561 blend
.cb_color_control
|= S_028808_ROP3(vkblend
->logicOp
| (vkblend
->logicOp
<< 4));
563 blend
.cb_color_control
|= S_028808_ROP3(0xcc);
565 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
566 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
567 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
568 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
570 if (vkms
&& vkms
->alphaToCoverageEnable
) {
571 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
574 blend
.cb_target_mask
= 0;
575 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
576 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
577 unsigned blend_cntl
= 0;
578 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
579 VkBlendOp eqRGB
= att
->colorBlendOp
;
580 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
581 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
582 VkBlendOp eqA
= att
->alphaBlendOp
;
583 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
584 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
586 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
588 if (!att
->colorWriteMask
)
591 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
592 if (!att
->blendEnable
) {
593 blend
.cb_blend_control
[i
] = blend_cntl
;
597 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
599 blend_mrt0_is_dual_src
= true;
601 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
602 srcRGB
= VK_BLEND_FACTOR_ONE
;
603 dstRGB
= VK_BLEND_FACTOR_ONE
;
605 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
606 srcA
= VK_BLEND_FACTOR_ONE
;
607 dstA
= VK_BLEND_FACTOR_ONE
;
610 /* Blending optimizations for RB+.
611 * These transformations don't change the behavior.
613 * First, get rid of DST in the blend factors:
614 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
616 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
617 VK_BLEND_FACTOR_DST_COLOR
,
618 VK_BLEND_FACTOR_SRC_COLOR
);
620 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
621 VK_BLEND_FACTOR_DST_COLOR
,
622 VK_BLEND_FACTOR_SRC_COLOR
);
624 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
625 VK_BLEND_FACTOR_DST_ALPHA
,
626 VK_BLEND_FACTOR_SRC_ALPHA
);
628 /* Look up the ideal settings from tables. */
629 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
630 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
631 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
632 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
634 /* Handle interdependencies. */
635 if (si_blend_factor_uses_dst(srcRGB
))
636 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
637 if (si_blend_factor_uses_dst(srcA
))
638 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
640 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
641 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
642 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
643 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
644 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
646 /* Set the final value. */
647 blend
.sx_mrt_blend_opt
[i
] =
648 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
649 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
650 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
651 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
652 S_028760_ALPHA_DST_OPT(dstA_opt
) |
653 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
654 blend_cntl
|= S_028780_ENABLE(1);
656 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
657 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
658 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
659 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
660 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
661 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
662 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
663 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
665 blend
.cb_blend_control
[i
] = blend_cntl
;
667 blend_enable
|= 1 << i
;
669 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
670 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
671 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
672 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
673 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
674 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
675 blend_need_alpha
|= 1 << i
;
677 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
678 blend
.cb_blend_control
[i
] = 0;
679 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
682 /* disable RB+ for now */
683 if (pipeline
->device
->physical_device
->has_rbplus
)
684 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
686 if (blend
.cb_target_mask
)
687 blend
.cb_color_control
|= S_028808_MODE(mode
);
689 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
691 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
,
692 blend_enable
, blend_need_alpha
, single_cb_enable
, blend_mrt0_is_dual_src
,
697 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
700 case VK_STENCIL_OP_KEEP
:
701 return V_02842C_STENCIL_KEEP
;
702 case VK_STENCIL_OP_ZERO
:
703 return V_02842C_STENCIL_ZERO
;
704 case VK_STENCIL_OP_REPLACE
:
705 return V_02842C_STENCIL_REPLACE_TEST
;
706 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
707 return V_02842C_STENCIL_ADD_CLAMP
;
708 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
709 return V_02842C_STENCIL_SUB_CLAMP
;
710 case VK_STENCIL_OP_INVERT
:
711 return V_02842C_STENCIL_INVERT
;
712 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
713 return V_02842C_STENCIL_ADD_WRAP
;
714 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
715 return V_02842C_STENCIL_SUB_WRAP
;
721 static uint32_t si_translate_fill(VkPolygonMode func
)
724 case VK_POLYGON_MODE_FILL
:
725 return V_028814_X_DRAW_TRIANGLES
;
726 case VK_POLYGON_MODE_LINE
:
727 return V_028814_X_DRAW_LINES
;
728 case VK_POLYGON_MODE_POINT
:
729 return V_028814_X_DRAW_POINTS
;
732 return V_028814_X_DRAW_POINTS
;
736 radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline
,
737 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
739 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
740 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
742 raster
->spi_interp_control
=
743 S_0286D4_FLAT_SHADE_ENA(1) |
744 S_0286D4_PNT_SPRITE_ENA(1) |
745 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
746 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
747 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
748 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
749 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
752 raster
->pa_cl_clip_cntl
= S_028810_PS_UCP_MODE(3) |
753 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
754 S_028810_ZCLIP_NEAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
755 S_028810_ZCLIP_FAR_DISABLE(vkraster
->depthClampEnable
? 1 : 0) |
756 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
757 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
759 raster
->pa_su_vtx_cntl
=
760 S_028BE4_PIX_CENTER(1) | // TODO verify
761 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
762 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
);
764 raster
->pa_su_sc_mode_cntl
=
765 S_028814_FACE(vkraster
->frontFace
) |
766 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
767 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
768 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
769 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
770 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
771 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
772 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
773 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
777 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
779 uint32_t num_samples
= vkms
->rasterizationSamples
;
780 uint32_t ps_iter_samples
= 1;
782 if (vkms
->sampleShadingEnable
) {
783 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
784 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
786 return ps_iter_samples
;
790 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
791 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
793 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
794 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
795 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
796 int ps_iter_samples
= 1;
797 uint32_t mask
= 0xffff;
800 ms
->num_samples
= vkms
->rasterizationSamples
;
805 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
806 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.force_persample
) {
807 ps_iter_samples
= ms
->num_samples
;
810 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
811 ms
->pa_sc_aa_config
= 0;
812 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
813 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
814 ms
->pa_sc_mode_cntl_1
=
815 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
816 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
818 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
819 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
820 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
821 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
822 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
823 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
824 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
825 S_028A48_VPORT_SCISSOR_ENABLE(1);
827 if (ms
->num_samples
> 1) {
828 unsigned log_samples
= util_logbase2(ms
->num_samples
);
829 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
830 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
831 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
832 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
833 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
834 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
835 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
836 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
837 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples
)) |
838 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
839 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
840 if (ps_iter_samples
> 1)
841 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
844 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
845 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
846 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
847 ms
->pa_sc_mode_cntl_1
|= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
848 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
851 if (vkms
&& vkms
->pSampleMask
) {
852 mask
= vkms
->pSampleMask
[0] & 0xffff;
855 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
856 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
860 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
863 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
864 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
865 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
866 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
867 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
869 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
870 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
871 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
872 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
873 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
874 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
877 unreachable("unhandled primitive type");
882 si_translate_prim(enum VkPrimitiveTopology topology
)
885 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
886 return V_008958_DI_PT_POINTLIST
;
887 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
888 return V_008958_DI_PT_LINELIST
;
889 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
890 return V_008958_DI_PT_LINESTRIP
;
891 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
892 return V_008958_DI_PT_TRILIST
;
893 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
894 return V_008958_DI_PT_TRISTRIP
;
895 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
896 return V_008958_DI_PT_TRIFAN
;
897 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
898 return V_008958_DI_PT_LINELIST_ADJ
;
899 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
900 return V_008958_DI_PT_LINESTRIP_ADJ
;
901 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
902 return V_008958_DI_PT_TRILIST_ADJ
;
903 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
904 return V_008958_DI_PT_TRISTRIP_ADJ
;
905 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
906 return V_008958_DI_PT_PATCH
;
914 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
917 case 0: /* GL_POINTS */
918 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
919 case 1: /* GL_LINES */
920 case 3: /* GL_LINE_STRIP */
921 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
922 case 0x8E7A: /* GL_ISOLINES */
923 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
925 case 4: /* GL_TRIANGLES */
926 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
927 case 5: /* GL_TRIANGLE_STRIP */
928 case 7: /* GL_QUADS */
929 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
937 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
940 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
941 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
942 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
943 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
944 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
945 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
946 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
947 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
948 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
949 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
950 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
951 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
952 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
953 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
960 static unsigned si_map_swizzle(unsigned swizzle
)
964 return V_008F0C_SQ_SEL_Y
;
966 return V_008F0C_SQ_SEL_Z
;
968 return V_008F0C_SQ_SEL_W
;
970 return V_008F0C_SQ_SEL_0
;
972 return V_008F0C_SQ_SEL_1
;
973 default: /* VK_SWIZZLE_X */
974 return V_008F0C_SQ_SEL_X
;
979 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
982 case VK_DYNAMIC_STATE_VIEWPORT
:
983 return RADV_DYNAMIC_VIEWPORT
;
984 case VK_DYNAMIC_STATE_SCISSOR
:
985 return RADV_DYNAMIC_SCISSOR
;
986 case VK_DYNAMIC_STATE_LINE_WIDTH
:
987 return RADV_DYNAMIC_LINE_WIDTH
;
988 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
989 return RADV_DYNAMIC_DEPTH_BIAS
;
990 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
991 return RADV_DYNAMIC_BLEND_CONSTANTS
;
992 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
993 return RADV_DYNAMIC_DEPTH_BOUNDS
;
994 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
995 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
996 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
997 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
998 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
999 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1000 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1001 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1003 unreachable("Unhandled dynamic state");
1007 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1009 uint32_t states
= RADV_DYNAMIC_ALL
;
1011 /* If rasterization is disabled we do not care about any of the dynamic states,
1012 * since they are all rasterization related only. */
1013 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1016 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1017 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1019 if (!pCreateInfo
->pDepthStencilState
||
1020 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1021 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1023 if (!pCreateInfo
->pDepthStencilState
||
1024 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1025 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1026 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1027 RADV_DYNAMIC_STENCIL_REFERENCE
);
1029 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1030 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1032 /* TODO: blend constants & line width. */
1039 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1040 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1042 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1043 uint32_t states
= needed_states
;
1044 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1045 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1047 pipeline
->dynamic_state
= default_dynamic_state
;
1048 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1050 if (pCreateInfo
->pDynamicState
) {
1051 /* Remove all of the states that are marked as dynamic */
1052 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1053 for (uint32_t s
= 0; s
< count
; s
++)
1054 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1057 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1059 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1060 assert(pCreateInfo
->pViewportState
);
1062 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1063 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1064 typed_memcpy(dynamic
->viewport
.viewports
,
1065 pCreateInfo
->pViewportState
->pViewports
,
1066 pCreateInfo
->pViewportState
->viewportCount
);
1070 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1071 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1072 if (states
& RADV_DYNAMIC_SCISSOR
) {
1073 typed_memcpy(dynamic
->scissor
.scissors
,
1074 pCreateInfo
->pViewportState
->pScissors
,
1075 pCreateInfo
->pViewportState
->scissorCount
);
1079 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1080 assert(pCreateInfo
->pRasterizationState
);
1081 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1084 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1085 assert(pCreateInfo
->pRasterizationState
);
1086 dynamic
->depth_bias
.bias
=
1087 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1088 dynamic
->depth_bias
.clamp
=
1089 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1090 dynamic
->depth_bias
.slope
=
1091 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1094 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1096 * pColorBlendState is [...] NULL if the pipeline has rasterization
1097 * disabled or if the subpass of the render pass the pipeline is
1098 * created against does not use any color attachments.
1100 bool uses_color_att
= false;
1101 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1102 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1103 uses_color_att
= true;
1108 if (uses_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1109 assert(pCreateInfo
->pColorBlendState
);
1110 typed_memcpy(dynamic
->blend_constants
,
1111 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1114 /* If there is no depthstencil attachment, then don't read
1115 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1116 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1117 * no need to override the depthstencil defaults in
1118 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1120 * Section 9.2 of the Vulkan 1.0.15 spec says:
1122 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1123 * disabled or if the subpass of the render pass the pipeline is created
1124 * against does not use a depth/stencil attachment.
1126 if (needed_states
&&
1127 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1128 assert(pCreateInfo
->pDepthStencilState
);
1130 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1131 dynamic
->depth_bounds
.min
=
1132 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1133 dynamic
->depth_bounds
.max
=
1134 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1137 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1138 dynamic
->stencil_compare_mask
.front
=
1139 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1140 dynamic
->stencil_compare_mask
.back
=
1141 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1144 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1145 dynamic
->stencil_write_mask
.front
=
1146 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1147 dynamic
->stencil_write_mask
.back
=
1148 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1151 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1152 dynamic
->stencil_reference
.front
=
1153 pCreateInfo
->pDepthStencilState
->front
.reference
;
1154 dynamic
->stencil_reference
.back
=
1155 pCreateInfo
->pDepthStencilState
->back
.reference
;
1159 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1160 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1161 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1162 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1163 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1164 discard_rectangle_info
->pDiscardRectangles
,
1165 discard_rectangle_info
->discardRectangleCount
);
1169 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
1170 /* Interpret i as a bitmask, and then set the bit in the mask if
1171 * that combination of rectangles in which the pixel is contained
1172 * should pass the cliprect test. */
1173 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
1175 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
1179 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
1185 pipeline
->graphics
.pa_sc_cliprect_rule
= mask
;
1187 /* Allow from all rectangle combinations */
1188 pipeline
->graphics
.pa_sc_cliprect_rule
= 0xffff;
1190 pipeline
->dynamic_state
.mask
= states
;
1193 static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1194 struct radv_pipeline
*pipeline
)
1196 struct ac_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1197 struct ac_es_output_info
*es_info
= radv_pipeline_has_tess(pipeline
) ?
1198 &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1199 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1200 bool uses_adjacency
;
1201 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1203 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1206 uses_adjacency
= true;
1209 uses_adjacency
= false;
1213 /* All these are in dwords: */
1214 /* We can't allow using the whole LDS, because GS waves compete with
1215 * other shader stages for LDS space. */
1216 const unsigned max_lds_size
= 8 * 1024;
1217 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1218 unsigned esgs_lds_size
;
1220 /* All these are per subgroup: */
1221 const unsigned max_out_prims
= 32 * 1024;
1222 const unsigned max_es_verts
= 255;
1223 const unsigned ideal_gs_prims
= 64;
1224 unsigned max_gs_prims
, gs_prims
;
1225 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1227 if (uses_adjacency
|| gs_num_invocations
> 1)
1228 max_gs_prims
= 127 / gs_num_invocations
;
1232 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1233 * Make sure we don't go over the maximum value.
1235 if (gs_info
->gs
.vertices_out
> 0) {
1236 max_gs_prims
= MIN2(max_gs_prims
,
1238 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1240 assert(max_gs_prims
> 0);
1242 /* If the primitive has adjacency, halve the number of vertices
1243 * that will be reused in multiple primitives.
1245 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1247 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1248 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1250 /* Compute ESGS LDS size based on the worst case number of ES vertices
1251 * needed to create the target number of GS prims per subgroup.
1253 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1255 /* If total LDS usage is too big, refactor partitions based on ratio
1256 * of ESGS item sizes.
1258 if (esgs_lds_size
> max_lds_size
) {
1259 /* Our target GS Prims Per Subgroup was too large. Calculate
1260 * the maximum number of GS Prims Per Subgroup that will fit
1261 * into LDS, capped by the maximum that the hardware can support.
1263 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1265 assert(gs_prims
> 0);
1266 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1269 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1270 assert(esgs_lds_size
<= max_lds_size
);
1273 /* Now calculate remaining ESGS information. */
1275 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1277 es_verts
= max_es_verts
;
1279 /* Vertices for adjacency primitives are not always reused, so restore
1280 * it for ES_VERTS_PER_SUBGRP.
1282 min_es_verts
= gs_info
->gs
.vertices_in
;
1284 /* For normal primitives, the VGT only checks if they are past the ES
1285 * verts per subgroup after allocating a full GS primitive and if they
1286 * are, kick off a new subgroup. But if those additional ES verts are
1287 * unique (e.g. not reused) we need to make sure there is enough LDS
1288 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1290 es_verts
-= min_es_verts
- 1;
1292 uint32_t es_verts_per_subgroup
= es_verts
;
1293 uint32_t gs_prims_per_subgroup
= gs_prims
;
1294 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1295 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1296 pipeline
->graphics
.gs
.lds_size
= align(esgs_lds_size
, 128) / 128;
1297 pipeline
->graphics
.gs
.vgt_gs_onchip_cntl
=
1298 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1299 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1300 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1301 pipeline
->graphics
.gs
.vgt_gs_max_prims_per_subgroup
=
1302 S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1303 pipeline
->graphics
.gs
.vgt_esgs_ring_itemsize
= esgs_itemsize
;
1304 assert(max_prims_per_subgroup
<= max_out_prims
);
1308 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
)
1310 struct radv_device
*device
= pipeline
->device
;
1311 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1312 unsigned wave_size
= 64;
1313 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1314 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1315 unsigned alignment
= 256 * num_se
;
1316 /* The maximum size is 63.999 MB per SE. */
1317 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1318 struct ac_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1319 struct ac_es_output_info
*es_info
;
1320 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1321 es_info
= radv_pipeline_has_tess(pipeline
) ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1323 es_info
= radv_pipeline_has_tess(pipeline
) ?
1324 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1325 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1327 /* Calculate the minimum size. */
1328 unsigned min_esgs_ring_size
= align(es_info
->esgs_itemsize
* gs_vertex_reuse
*
1329 wave_size
, alignment
);
1330 /* These are recommended sizes, not minimum sizes. */
1331 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1332 es_info
->esgs_itemsize
* gs_info
->gs
.vertices_in
;
1333 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1334 gs_info
->gs
.max_gsvs_emit_size
* 1; // no streams in VK (gs->max_gs_stream + 1);
1336 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1337 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1338 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1340 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= VI
)
1341 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1343 pipeline
->graphics
.gs
.vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1344 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1347 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1350 /* SPI barrier management bug:
1351 * Make sure we have at least 4k of LDS in use to avoid the bug.
1352 * It applies to workgroup sizes of more than one wavefront.
1354 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1355 device
->physical_device
->rad_info
.family
== CHIP_KABINI
||
1356 device
->physical_device
->rad_info
.family
== CHIP_MULLINS
)
1357 *lds_size
= MAX2(*lds_size
, 8);
1360 struct radv_shader_variant
*
1361 radv_get_vertex_shader(struct radv_pipeline
*pipeline
)
1363 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1364 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1365 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1366 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1367 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1370 static struct radv_shader_variant
*
1371 radv_get_tess_eval_shader(struct radv_pipeline
*pipeline
)
1373 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1374 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1375 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1378 static struct radv_tessellation_state
1379 calculate_tess_state(struct radv_pipeline
*pipeline
,
1380 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1382 unsigned num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1383 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
1384 unsigned num_tcs_patch_outputs
;
1385 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
1386 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
1387 unsigned lds_size
, hardware_lds_size
;
1388 unsigned perpatch_output_offset
;
1389 unsigned num_patches
;
1390 struct radv_tessellation_state tess
= {0};
1392 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1393 * are laid out in LDS. */
1394 num_tcs_inputs
= util_last_bit64(radv_get_vertex_shader(pipeline
)->info
.vs
.outputs_written
);
1396 num_tcs_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
); //tcs->outputs_written
1397 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1398 num_tcs_patch_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.patch_outputs_written
);
1400 /* Ensure that we only need one wave per SIMD so we don't need to check
1401 * resource usage. Also ensures that the number of tcs in and out
1402 * vertices per threadgroup are at most 256.
1404 input_vertex_size
= num_tcs_inputs
* 16;
1405 output_vertex_size
= num_tcs_outputs
* 16;
1407 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
1409 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
1410 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
1411 /* Ensure that we only need one wave per SIMD so we don't need to check
1412 * resource usage. Also ensures that the number of tcs in and out
1413 * vertices per threadgroup are at most 256.
1415 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
1417 /* Make sure that the data fits in LDS. This assumes the shaders only
1418 * use LDS for the inputs and outputs.
1420 hardware_lds_size
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
? 65536 : 32768;
1421 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
1423 /* Make sure the output data fits in the offchip buffer */
1424 num_patches
= MIN2(num_patches
,
1425 (pipeline
->device
->tess_offchip_block_dw_size
* 4) /
1428 /* Not necessary for correctness, but improves performance. The
1429 * specific value is taken from the proprietary driver.
1431 num_patches
= MIN2(num_patches
, 40);
1433 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1434 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== SI
) {
1435 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
1436 num_patches
= MIN2(num_patches
, one_wave
);
1439 output_patch0_offset
= input_patch_size
* num_patches
;
1440 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
1442 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
1444 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1445 assert(lds_size
<= 65536);
1446 lds_size
= align(lds_size
, 512) / 512;
1448 assert(lds_size
<= 32768);
1449 lds_size
= align(lds_size
, 256) / 256;
1451 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1453 tess
.lds_size
= lds_size
;
1455 tess
.tcs_in_layout
= (input_patch_size
/ 4) |
1456 ((input_vertex_size
/ 4) << 13);
1457 tess
.tcs_out_layout
= (output_patch_size
/ 4) |
1458 ((output_vertex_size
/ 4) << 13);
1459 tess
.tcs_out_offsets
= (output_patch0_offset
/ 16) |
1460 ((perpatch_output_offset
/ 16) << 16);
1461 tess
.offchip_layout
= (pervertex_output_patch_size
* num_patches
<< 16) |
1462 (num_tcs_output_cp
<< 9) | num_patches
;
1464 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1465 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1466 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1467 tess
.num_patches
= num_patches
;
1468 tess
.num_tcs_input_cp
= num_tcs_input_cp
;
1470 struct radv_shader_variant
*tes
= radv_get_tess_eval_shader(pipeline
);
1471 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1473 switch (tes
->info
.tes
.primitive_mode
) {
1475 type
= V_028B6C_TESS_TRIANGLE
;
1478 type
= V_028B6C_TESS_QUAD
;
1481 type
= V_028B6C_TESS_ISOLINE
;
1485 switch (tes
->info
.tes
.spacing
) {
1486 case TESS_SPACING_EQUAL
:
1487 partitioning
= V_028B6C_PART_INTEGER
;
1489 case TESS_SPACING_FRACTIONAL_ODD
:
1490 partitioning
= V_028B6C_PART_FRAC_ODD
;
1492 case TESS_SPACING_FRACTIONAL_EVEN
:
1493 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1499 bool ccw
= tes
->info
.tes
.ccw
;
1500 const VkPipelineTessellationDomainOriginStateCreateInfoKHR
*domain_origin_state
=
1501 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1502 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR
);
1504 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR
)
1507 if (tes
->info
.tes
.point_mode
)
1508 topology
= V_028B6C_OUTPUT_POINT
;
1509 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1510 topology
= V_028B6C_OUTPUT_LINE
;
1512 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1514 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
1516 if (pipeline
->device
->has_distributed_tess
) {
1517 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1518 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
1519 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
1521 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
1523 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
1525 tess
.tf_param
= S_028B6C_TYPE(type
) |
1526 S_028B6C_PARTITIONING(partitioning
) |
1527 S_028B6C_TOPOLOGY(topology
) |
1528 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
1533 static const struct radv_prim_vertex_count prim_size_table
[] = {
1534 [V_008958_DI_PT_NONE
] = {0, 0},
1535 [V_008958_DI_PT_POINTLIST
] = {1, 1},
1536 [V_008958_DI_PT_LINELIST
] = {2, 2},
1537 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
1538 [V_008958_DI_PT_TRILIST
] = {3, 3},
1539 [V_008958_DI_PT_TRIFAN
] = {3, 1},
1540 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
1541 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
1542 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
1543 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
1544 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
1545 [V_008958_DI_PT_RECTLIST
] = {3, 3},
1546 [V_008958_DI_PT_LINELOOP
] = {2, 1},
1547 [V_008958_DI_PT_POLYGON
] = {3, 1},
1548 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
1551 static const struct ac_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
1553 if (radv_pipeline_has_gs(pipeline
))
1554 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
1555 else if (radv_pipeline_has_tess(pipeline
))
1556 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
1558 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
1562 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
1564 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
1565 int shader_count
= 0;
1567 if(shaders
[MESA_SHADER_FRAGMENT
]) {
1568 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
1570 if(shaders
[MESA_SHADER_GEOMETRY
]) {
1571 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
1573 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
1574 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
1576 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
1577 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
1579 if(shaders
[MESA_SHADER_VERTEX
]) {
1580 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
1583 for (int i
= 1; i
< shader_count
; ++i
) {
1584 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
1585 ordered_shaders
[i
- 1]);
1587 nir_remove_dead_variables(ordered_shaders
[i
],
1588 nir_var_shader_out
);
1589 nir_remove_dead_variables(ordered_shaders
[i
- 1],
1592 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
1593 ordered_shaders
[i
- 1]);
1596 nir_lower_global_vars_to_local(ordered_shaders
[i
]);
1597 radv_optimize_nir(ordered_shaders
[i
]);
1598 nir_lower_global_vars_to_local(ordered_shaders
[i
- 1]);
1599 radv_optimize_nir(ordered_shaders
[i
- 1]);
1605 static struct radv_pipeline_key
1606 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
1607 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1608 const struct radv_blend_state
*blend
,
1609 bool has_view_index
)
1611 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1612 pCreateInfo
->pVertexInputState
;
1613 struct radv_pipeline_key key
;
1614 memset(&key
, 0, sizeof(key
));
1616 key
.has_multiview_view_index
= has_view_index
;
1618 uint32_t binding_input_rate
= 0;
1619 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
1620 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
)
1621 binding_input_rate
|= 1u << input_state
->pVertexBindingDescriptions
[i
].binding
;
1624 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1626 binding
= input_state
->pVertexAttributeDescriptions
[i
].binding
;
1627 if (binding_input_rate
& (1u << binding
))
1628 key
.instance_rate_inputs
|= 1u << input_state
->pVertexAttributeDescriptions
[i
].location
;
1631 if (pCreateInfo
->pTessellationState
)
1632 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1635 if (pCreateInfo
->pMultisampleState
&&
1636 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
1637 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
1638 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
1639 key
.multisample
= true;
1640 key
.log2_num_samples
= util_logbase2(num_samples
);
1641 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1644 key
.col_format
= blend
->spi_shader_col_format
;
1645 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< VI
)
1646 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
1652 radv_fill_shader_keys(struct ac_shader_variant_key
*keys
,
1653 const struct radv_pipeline_key
*key
,
1656 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
1658 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1659 keys
[MESA_SHADER_VERTEX
].vs
.as_ls
= true;
1660 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
1661 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
1663 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
1666 if (nir
[MESA_SHADER_GEOMETRY
]) {
1667 if (nir
[MESA_SHADER_TESS_CTRL
])
1668 keys
[MESA_SHADER_TESS_EVAL
].tes
.as_es
= true;
1670 keys
[MESA_SHADER_VERTEX
].vs
.as_es
= true;
1673 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
1674 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
1676 keys
[MESA_SHADER_FRAGMENT
].fs
.multisample
= key
->multisample
;
1677 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
1678 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
1679 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
1680 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
1681 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_num_samples
= key
->log2_num_samples
;
1685 merge_tess_info(struct shader_info
*tes_info
,
1686 const struct shader_info
*tcs_info
)
1688 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1690 * "PointMode. Controls generation of points rather than triangles
1691 * or lines. This functionality defaults to disabled, and is
1692 * enabled if either shader stage includes the execution mode.
1694 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1695 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1696 * and OutputVertices, it says:
1698 * "One mode must be set in at least one of the tessellation
1701 * So, the fields can be set in either the TCS or TES, but they must
1702 * agree if set in both. Our backend looks at TES, so bitwise-or in
1703 * the values from the TCS.
1705 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
1706 tes_info
->tess
.tcs_vertices_out
== 0 ||
1707 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
1708 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
1710 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
1711 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
1712 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
1713 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
1715 assert(tcs_info
->tess
.primitive_mode
== 0 ||
1716 tes_info
->tess
.primitive_mode
== 0 ||
1717 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
1718 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
1719 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
1720 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
1724 void radv_create_shaders(struct radv_pipeline
*pipeline
,
1725 struct radv_device
*device
,
1726 struct radv_pipeline_cache
*cache
,
1727 struct radv_pipeline_key key
,
1728 const VkPipelineShaderStageCreateInfo
**pStages
)
1730 struct radv_shader_module fs_m
= {0};
1731 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1732 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
1733 void *codes
[MESA_SHADER_STAGES
] = {0};
1734 unsigned code_sizes
[MESA_SHADER_STAGES
] = {0};
1735 struct ac_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{0}}}};
1736 unsigned char hash
[20], gs_copy_hash
[20];
1738 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1740 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
1741 if (modules
[i
]->nir
)
1742 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
1743 strlen(modules
[i
]->nir
->info
.name
),
1748 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, &key
, get_hash_flags(device
));
1749 memcpy(gs_copy_hash
, hash
, 20);
1750 gs_copy_hash
[0] ^= 1;
1752 if (modules
[MESA_SHADER_GEOMETRY
]) {
1753 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
1754 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
);
1755 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
1758 if (radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
) &&
1759 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
1760 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1761 if (pipeline
->shaders
[i
])
1762 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
1767 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
1769 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
1770 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
1771 fs_m
.nir
= fs_b
.shader
;
1772 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
1775 /* Determine first and last stage. */
1776 unsigned first
= MESA_SHADER_STAGES
;
1778 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1781 if (first
== MESA_SHADER_STAGES
)
1787 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1788 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
1793 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
1794 stage
? stage
->pName
: "main", i
,
1795 stage
? stage
->pSpecializationInfo
: NULL
);
1796 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
1798 /* We don't want to alter meta shaders IR directly so clone it
1801 if (nir
[i
]->info
.name
) {
1802 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
1805 if (first
!= last
) {
1806 nir_variable_mode mask
= 0;
1809 mask
= mask
| nir_var_shader_in
;
1812 mask
= mask
| nir_var_shader_out
;
1814 nir_lower_io_to_scalar_early(nir
[i
], mask
);
1815 radv_optimize_nir(nir
[i
]);
1819 nir_compact_varyings(nir
[prev
], nir
[i
], true);
1824 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1825 nir_lower_tes_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
);
1826 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
1829 radv_link_shaders(pipeline
, nir
);
1831 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1832 if (modules
[i
] && radv_can_dump_shader(device
, modules
[i
]))
1833 nir_print_shader(nir
[i
], stderr
);
1836 radv_fill_shader_keys(keys
, &key
, nir
);
1838 if (nir
[MESA_SHADER_FRAGMENT
]) {
1839 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
1840 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
1841 radv_shader_variant_create(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
1842 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
1843 &codes
[MESA_SHADER_FRAGMENT
], &code_sizes
[MESA_SHADER_FRAGMENT
]);
1846 /* TODO: These are no longer used as keys we should refactor this */
1847 keys
[MESA_SHADER_VERTEX
].vs
.export_prim_id
=
1848 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
;
1849 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_prim_id
=
1850 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
;
1853 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
1854 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
1855 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
1856 struct ac_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
1857 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
1858 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
1860 &key
, &codes
[MESA_SHADER_TESS_CTRL
],
1861 &code_sizes
[MESA_SHADER_TESS_CTRL
]);
1863 modules
[MESA_SHADER_VERTEX
] = NULL
;
1866 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
1867 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
1868 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
1869 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
1870 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
1872 &keys
[pre_stage
] , &codes
[MESA_SHADER_GEOMETRY
],
1873 &code_sizes
[MESA_SHADER_GEOMETRY
]);
1875 modules
[pre_stage
] = NULL
;
1878 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1879 if(modules
[i
] && !pipeline
->shaders
[i
]) {
1880 pipeline
->shaders
[i
] = radv_shader_variant_create(device
, modules
[i
], &nir
[i
], 1,
1882 keys
+ i
, &codes
[i
],
1887 if(modules
[MESA_SHADER_GEOMETRY
]) {
1888 void *gs_copy_code
= NULL
;
1889 unsigned gs_copy_code_size
= 0;
1890 if (!pipeline
->gs_copy_shader
) {
1891 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
1892 device
, nir
[MESA_SHADER_GEOMETRY
], &gs_copy_code
,
1894 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
1897 if (pipeline
->gs_copy_shader
) {
1898 void *code
[MESA_SHADER_STAGES
] = {0};
1899 unsigned code_size
[MESA_SHADER_STAGES
] = {0};
1900 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
1902 code
[MESA_SHADER_GEOMETRY
] = gs_copy_code
;
1903 code_size
[MESA_SHADER_GEOMETRY
] = gs_copy_code_size
;
1904 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
1906 radv_pipeline_cache_insert_shaders(device
, cache
,
1915 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
1916 (const void**)codes
, code_sizes
);
1918 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
1920 if (modules
[i
] && !pipeline
->device
->keep_shader_info
)
1921 ralloc_free(nir
[i
]);
1925 ralloc_free(fs_m
.nir
);
1929 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
1930 gl_shader_stage stage
, enum chip_class chip_class
)
1932 bool has_gs
= radv_pipeline_has_gs(pipeline
);
1933 bool has_tess
= radv_pipeline_has_tess(pipeline
);
1935 case MESA_SHADER_FRAGMENT
:
1936 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
1937 case MESA_SHADER_VERTEX
:
1938 if (chip_class
>= GFX9
) {
1939 return has_tess
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
1940 has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
1941 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
1944 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
1946 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
1947 case MESA_SHADER_GEOMETRY
:
1948 return chip_class
>= GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
1949 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
1950 case MESA_SHADER_COMPUTE
:
1951 return R_00B900_COMPUTE_USER_DATA_0
;
1952 case MESA_SHADER_TESS_CTRL
:
1953 return chip_class
>= GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
1954 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
1955 case MESA_SHADER_TESS_EVAL
:
1956 if (chip_class
>= GFX9
) {
1957 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
1958 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
1961 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
1963 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
1965 unreachable("unknown shader");
1969 struct radv_bin_size_entry
{
1975 radv_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1977 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
1981 /* One shader engine */
1987 { UINT_MAX
, { 0, 0}},
1990 /* Two shader engines */
1996 { UINT_MAX
, { 0, 0}},
1999 /* Four shader engines */
2004 { UINT_MAX
, { 0, 0}},
2010 /* One shader engine */
2016 { UINT_MAX
, { 0, 0}},
2019 /* Two shader engines */
2025 { UINT_MAX
, { 0, 0}},
2028 /* Four shader engines */
2035 { UINT_MAX
, { 0, 0}},
2041 /* One shader engine */
2048 { UINT_MAX
, { 0, 0}},
2051 /* Two shader engines */
2059 { UINT_MAX
, { 0, 0}},
2062 /* Four shader engines */
2070 { UINT_MAX
, { 0, 0}},
2074 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
2078 // One shader engine
2085 { UINT_MAX
, { 0, 0}},
2088 // Two shader engines
2096 { UINT_MAX
, { 0, 0}},
2099 // Four shader engines
2107 { UINT_MAX
, { 0, 0}},
2113 // One shader engine
2121 { UINT_MAX
, { 0, 0}},
2124 // Two shader engines
2133 { UINT_MAX
, { 0, 0}},
2136 // Four shader engines
2145 { UINT_MAX
, { 0, 0}},
2151 // One shader engine
2159 { UINT_MAX
, { 0, 0}},
2162 // Two shader engines
2171 { UINT_MAX
, { 0, 0}},
2174 // Four shader engines
2182 { UINT_MAX
, { 0, 0}},
2187 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2188 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2189 VkExtent2D extent
= {512, 512};
2191 unsigned log_num_rb_per_se
=
2192 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
2193 pipeline
->device
->physical_device
->rad_info
.max_se
);
2194 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
2196 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
);
2197 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
2198 unsigned effective_samples
= total_samples
;
2199 unsigned color_bytes_per_pixel
= 0;
2201 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
2203 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2204 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
2207 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
2210 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
2211 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
2214 /* MSAA images typically don't use all samples all the time. */
2215 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
2216 effective_samples
= 2;
2217 color_bytes_per_pixel
*= effective_samples
;
2220 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
2221 while(color_entry
->bpp
<= color_bytes_per_pixel
)
2224 extent
= color_entry
->extent
;
2226 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2227 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
.attachment
;
2229 /* Coefficients taken from AMDVLK */
2230 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
2231 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
2232 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
2234 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
2235 while(ds_entry
->bpp
<= ds_bytes_per_pixel
)
2238 extent
.width
= MIN2(extent
.width
, ds_entry
->extent
.width
);
2239 extent
.height
= MIN2(extent
.height
, ds_entry
->extent
.height
);
2246 radv_pipeline_generate_binning_state(struct radeon_winsys_cs
*cs
,
2247 struct radv_pipeline
*pipeline
,
2248 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2250 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
2253 uint32_t pa_sc_binner_cntl_0
=
2254 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
2255 S_028C44_DISABLE_START_OF_PRIM(1);
2256 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
2258 VkExtent2D bin_size
= radv_compute_bin_size(pipeline
, pCreateInfo
);
2260 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
2261 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
2262 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
2264 switch (pipeline
->device
->physical_device
->rad_info
.family
) {
2266 context_states_per_bin
= 1;
2267 persistent_states_per_bin
= 1;
2268 fpovs_per_batch
= 63;
2271 context_states_per_bin
= 6;
2272 persistent_states_per_bin
= 32;
2273 fpovs_per_batch
= 63;
2276 unreachable("unhandled family while determining binning state.");
2279 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
2280 pa_sc_binner_cntl_0
=
2281 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
2282 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
2283 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
2284 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
2285 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
2286 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
2287 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
2288 S_028C44_DISABLE_START_OF_PRIM(1) |
2289 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
2290 S_028C44_OPTIMAL_BIN_SELECTION(1);
2293 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
2294 pa_sc_binner_cntl_0
);
2295 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
2301 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs
*cs
,
2302 struct radv_pipeline
*pipeline
,
2303 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2304 const struct radv_graphics_pipeline_create_info
*extra
)
2306 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
2307 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2308 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2309 struct radv_render_pass_attachment
*attachment
= NULL
;
2310 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
2311 uint32_t db_render_control
= 0, db_render_override2
= 0;
2313 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
2314 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
.attachment
;
2316 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
2317 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
2319 if (vkds
&& has_depth_attachment
) {
2320 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
2321 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
2322 S_028800_ZFUNC(vkds
->depthCompareOp
) |
2323 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
2325 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2326 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
2329 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
2330 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2331 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
2332 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
2333 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
2334 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
2336 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
2337 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
2338 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
2339 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
2342 if (attachment
&& extra
) {
2343 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
2344 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
2346 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
2347 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
2348 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
2349 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
2350 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
2353 radeon_set_context_reg(cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
2354 radeon_set_context_reg(cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
2356 radeon_set_context_reg(cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
2357 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
2361 radv_pipeline_generate_blend_state(struct radeon_winsys_cs
*cs
,
2362 struct radv_pipeline
*pipeline
,
2363 const struct radv_blend_state
*blend
)
2365 radeon_set_context_reg_seq(cs
, R_028780_CB_BLEND0_CONTROL
, 8);
2366 radeon_emit_array(cs
, blend
->cb_blend_control
,
2368 radeon_set_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
2369 radeon_set_context_reg(cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
2371 if (pipeline
->device
->physical_device
->has_rbplus
) {
2373 radeon_set_context_reg_seq(cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
2374 radeon_emit_array(cs
, blend
->sx_mrt_blend_opt
, 8);
2376 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
2377 radeon_emit(cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
2378 radeon_emit(cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2379 radeon_emit(cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2382 radeon_set_context_reg(cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
2384 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
2385 radeon_set_context_reg(cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
2390 radv_pipeline_generate_raster_state(struct radeon_winsys_cs
*cs
,
2391 struct radv_pipeline
*pipeline
)
2393 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
2395 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
2396 raster
->pa_cl_clip_cntl
);
2397 radeon_set_context_reg(cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
2398 raster
->spi_interp_control
);
2399 radeon_set_context_reg(cs
, R_028BE4_PA_SU_VTX_CNTL
,
2400 raster
->pa_su_vtx_cntl
);
2401 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
,
2402 raster
->pa_su_sc_mode_cntl
);
2407 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs
*cs
,
2408 struct radv_pipeline
*pipeline
)
2410 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
2412 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2413 radeon_emit(cs
, ms
->pa_sc_aa_mask
[0]);
2414 radeon_emit(cs
, ms
->pa_sc_aa_mask
[1]);
2416 radeon_set_context_reg(cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
2417 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
2419 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
2421 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
2422 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_FRAGMENT
];
2423 if (loc
->sgpr_idx
== -1)
2425 assert(loc
->num_sgprs
== 1);
2426 assert(!loc
->indirect
);
2427 switch (pipeline
->graphics
.ms
.num_samples
) {
2445 radeon_set_sh_reg(cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
2450 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs
*cs
,
2451 const struct radv_pipeline
*pipeline
)
2453 const struct ac_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2455 uint32_t vgt_primitiveid_en
= false;
2456 uint32_t vgt_gs_mode
= 0;
2458 if (radv_pipeline_has_gs(pipeline
)) {
2459 const struct radv_shader_variant
*gs
=
2460 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2462 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
2463 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2464 } else if (outinfo
->export_prim_id
) {
2465 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2466 vgt_primitiveid_en
= true;
2469 radeon_set_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
2470 radeon_set_context_reg(cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
2474 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs
*cs
,
2475 struct radv_pipeline
*pipeline
,
2476 struct radv_shader_variant
*shader
)
2478 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2480 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
2481 radeon_emit(cs
, va
>> 8);
2482 radeon_emit(cs
, va
>> 40);
2483 radeon_emit(cs
, shader
->rsrc1
);
2484 radeon_emit(cs
, shader
->rsrc2
);
2486 const struct ac_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2487 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
2488 clip_dist_mask
= outinfo
->clip_dist_mask
;
2489 cull_dist_mask
= outinfo
->cull_dist_mask
;
2490 total_mask
= clip_dist_mask
| cull_dist_mask
;
2491 bool misc_vec_ena
= outinfo
->writes_pointsize
||
2492 outinfo
->writes_layer
||
2493 outinfo
->writes_viewport_index
;
2495 radeon_set_context_reg(cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
2496 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo
->param_exports
) - 1));
2498 radeon_set_context_reg(cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
2499 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
2500 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
2501 V_02870C_SPI_SHADER_4COMP
:
2502 V_02870C_SPI_SHADER_NONE
) |
2503 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
2504 V_02870C_SPI_SHADER_4COMP
:
2505 V_02870C_SPI_SHADER_NONE
) |
2506 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
2507 V_02870C_SPI_SHADER_4COMP
:
2508 V_02870C_SPI_SHADER_NONE
));
2510 radeon_set_context_reg(cs
, R_028818_PA_CL_VTE_CNTL
,
2511 S_028818_VTX_W0_FMT(1) |
2512 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2513 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2514 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2516 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
2517 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
2518 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
2519 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
2520 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2521 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
2522 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
2523 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
2524 cull_dist_mask
<< 8 |
2527 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= VI
)
2528 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
2529 outinfo
->writes_viewport_index
);
2533 radv_pipeline_generate_hw_es(struct radeon_winsys_cs
*cs
,
2534 struct radv_pipeline
*pipeline
,
2535 struct radv_shader_variant
*shader
)
2537 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2539 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
2540 radeon_emit(cs
, va
>> 8);
2541 radeon_emit(cs
, va
>> 40);
2542 radeon_emit(cs
, shader
->rsrc1
);
2543 radeon_emit(cs
, shader
->rsrc2
);
2547 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs
*cs
,
2548 struct radv_pipeline
*pipeline
,
2549 struct radv_shader_variant
*shader
,
2550 const struct radv_tessellation_state
*tess
)
2552 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2553 uint32_t rsrc2
= shader
->rsrc2
;
2555 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
2556 radeon_emit(cs
, va
>> 8);
2557 radeon_emit(cs
, va
>> 40);
2559 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
2560 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
2561 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
2562 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
2564 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
2565 radeon_emit(cs
, shader
->rsrc1
);
2566 radeon_emit(cs
, rsrc2
);
2570 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs
*cs
,
2571 struct radv_pipeline
*pipeline
,
2572 struct radv_shader_variant
*shader
,
2573 const struct radv_tessellation_state
*tess
)
2575 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2577 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2578 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
2579 radeon_emit(cs
, va
>> 8);
2580 radeon_emit(cs
, va
>> 40);
2582 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
2583 radeon_emit(cs
, shader
->rsrc1
);
2584 radeon_emit(cs
, shader
->rsrc2
|
2585 S_00B42C_LDS_SIZE(tess
->lds_size
));
2587 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
2588 radeon_emit(cs
, va
>> 8);
2589 radeon_emit(cs
, va
>> 40);
2590 radeon_emit(cs
, shader
->rsrc1
);
2591 radeon_emit(cs
, shader
->rsrc2
);
2596 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs
*cs
,
2597 struct radv_pipeline
*pipeline
,
2598 const struct radv_tessellation_state
*tess
)
2600 struct radv_shader_variant
*vs
;
2602 /* Skip shaders merged into HS/GS */
2603 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
2607 if (vs
->info
.vs
.as_ls
)
2608 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
2609 else if (vs
->info
.vs
.as_es
)
2610 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
2612 radv_pipeline_generate_hw_vs(cs
, pipeline
, vs
);
2616 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs
*cs
,
2617 struct radv_pipeline
*pipeline
,
2618 const struct radv_tessellation_state
*tess
)
2620 if (!radv_pipeline_has_tess(pipeline
))
2623 struct radv_shader_variant
*tes
, *tcs
;
2625 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
2626 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2629 if (tes
->info
.tes
.as_es
)
2630 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
2632 radv_pipeline_generate_hw_vs(cs
, pipeline
, tes
);
2635 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
2637 radeon_set_context_reg(cs
, R_028B6C_VGT_TF_PARAM
,
2640 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
2641 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
2642 tess
->ls_hs_config
);
2644 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
2645 tess
->ls_hs_config
);
2647 struct ac_userdata_info
*loc
;
2649 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
2650 if (loc
->sgpr_idx
!= -1) {
2651 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_TESS_CTRL
];
2652 assert(loc
->num_sgprs
== 4);
2653 assert(!loc
->indirect
);
2654 radeon_set_sh_reg_seq(cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
2655 radeon_emit(cs
, tess
->offchip_layout
);
2656 radeon_emit(cs
, tess
->tcs_out_offsets
);
2657 radeon_emit(cs
, tess
->tcs_out_layout
|
2658 tess
->num_tcs_input_cp
<< 26);
2659 radeon_emit(cs
, tess
->tcs_in_layout
);
2662 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
2663 if (loc
->sgpr_idx
!= -1) {
2664 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_TESS_EVAL
];
2665 assert(loc
->num_sgprs
== 1);
2666 assert(!loc
->indirect
);
2668 radeon_set_sh_reg(cs
, base_reg
+ loc
->sgpr_idx
* 4,
2669 tess
->offchip_layout
);
2672 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
2673 if (loc
->sgpr_idx
!= -1) {
2674 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
2675 assert(loc
->num_sgprs
== 1);
2676 assert(!loc
->indirect
);
2678 radeon_set_sh_reg(cs
, base_reg
+ loc
->sgpr_idx
* 4,
2679 tess
->tcs_in_layout
);
2684 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs
*cs
,
2685 struct radv_pipeline
*pipeline
)
2687 struct radv_shader_variant
*gs
;
2690 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2694 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
2696 radeon_set_context_reg_seq(cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
2697 radeon_emit(cs
, gsvs_itemsize
);
2698 radeon_emit(cs
, gsvs_itemsize
);
2699 radeon_emit(cs
, gsvs_itemsize
);
2701 radeon_set_context_reg(cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
2703 radeon_set_context_reg(cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
2705 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
2706 radeon_set_context_reg_seq(cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
2707 radeon_emit(cs
, gs_vert_itemsize
>> 2);
2712 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
2713 radeon_set_context_reg(cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
2714 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
2715 S_028B90_ENABLE(gs_num_invocations
> 0));
2717 radeon_set_context_reg(cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
2718 pipeline
->graphics
.gs
.vgt_esgs_ring_itemsize
);
2720 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
2722 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2723 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
2724 radeon_emit(cs
, va
>> 8);
2725 radeon_emit(cs
, va
>> 40);
2727 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
2728 radeon_emit(cs
, gs
->rsrc1
);
2729 radeon_emit(cs
, gs
->rsrc2
|
2730 S_00B22C_LDS_SIZE(pipeline
->graphics
.gs
.lds_size
));
2732 radeon_set_context_reg(cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, pipeline
->graphics
.gs
.vgt_gs_onchip_cntl
);
2733 radeon_set_context_reg(cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, pipeline
->graphics
.gs
.vgt_gs_max_prims_per_subgroup
);
2735 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
2736 radeon_emit(cs
, va
>> 8);
2737 radeon_emit(cs
, va
>> 40);
2738 radeon_emit(cs
, gs
->rsrc1
);
2739 radeon_emit(cs
, gs
->rsrc2
);
2742 radv_pipeline_generate_hw_vs(cs
, pipeline
, pipeline
->gs_copy_shader
);
2744 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_GEOMETRY
,
2745 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
2746 if (loc
->sgpr_idx
!= -1) {
2747 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
2748 uint32_t num_entries
= 64;
2749 bool is_vi
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= VI
;
2752 num_entries
*= stride
;
2754 stride
= S_008F04_STRIDE(stride
);
2755 radeon_set_sh_reg_seq(cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
2756 radeon_emit(cs
, stride
);
2757 radeon_emit(cs
, num_entries
);
2761 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
)
2763 uint32_t ps_input_cntl
;
2764 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2765 ps_input_cntl
= S_028644_OFFSET(offset
);
2767 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2769 /* The input is a DEFAULT_VAL constant. */
2770 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2771 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2772 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2773 ps_input_cntl
= S_028644_OFFSET(0x20) |
2774 S_028644_DEFAULT_VAL(offset
);
2776 return ps_input_cntl
;
2780 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs
*cs
,
2781 struct radv_pipeline
*pipeline
)
2783 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
2784 const struct ac_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2785 uint32_t ps_input_cntl
[32];
2787 unsigned ps_offset
= 0;
2789 if (ps
->info
.fs
.prim_id_input
) {
2790 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
2791 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
2792 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
2797 if (ps
->info
.fs
.layer_input
) {
2798 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
2799 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
2800 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true);
2802 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true);
2806 if (ps
->info
.fs
.has_pcoord
) {
2808 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2809 ps_input_cntl
[ps_offset
] = val
;
2813 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
2816 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
2819 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
2820 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
2821 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
2826 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
2828 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
);
2833 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
2834 for (unsigned i
= 0; i
< ps_offset
; i
++) {
2835 radeon_emit(cs
, ps_input_cntl
[i
]);
2841 radv_compute_db_shader_control(const struct radv_device
*device
,
2842 const struct radv_shader_variant
*ps
)
2845 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.info
.ps
.writes_memory
)
2846 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
2848 z_order
= V_02880C_LATE_Z
;
2850 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.fs
.writes_z
) |
2851 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.fs
.writes_stencil
) |
2852 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
2853 S_02880C_MASK_EXPORT_ENABLE(ps
->info
.fs
.writes_sample_mask
) |
2854 S_02880C_Z_ORDER(z_order
) |
2855 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
2856 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.info
.ps
.writes_memory
) |
2857 S_02880C_EXEC_ON_NOOP(ps
->info
.info
.ps
.writes_memory
) |
2858 S_02880C_DUAL_QUAD_DISABLE(!!device
->physical_device
->has_rbplus
);
2862 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs
*cs
,
2863 struct radv_pipeline
*pipeline
)
2865 struct radv_shader_variant
*ps
;
2867 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
2869 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
2870 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
2872 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
2873 radeon_emit(cs
, va
>> 8);
2874 radeon_emit(cs
, va
>> 40);
2875 radeon_emit(cs
, ps
->rsrc1
);
2876 radeon_emit(cs
, ps
->rsrc2
);
2878 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
2879 radv_compute_db_shader_control(pipeline
->device
, ps
));
2881 radeon_set_context_reg(cs
, R_0286CC_SPI_PS_INPUT_ENA
,
2882 ps
->config
.spi_ps_input_ena
);
2884 radeon_set_context_reg(cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
2885 ps
->config
.spi_ps_input_addr
);
2887 radeon_set_context_reg(cs
, R_0286D8_SPI_PS_IN_CONTROL
,
2888 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
2890 radeon_set_context_reg(cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
2892 radeon_set_context_reg(cs
, R_028710_SPI_SHADER_Z_FORMAT
,
2893 ac_get_spi_shader_z_format(ps
->info
.fs
.writes_z
,
2894 ps
->info
.fs
.writes_stencil
,
2895 ps
->info
.fs
.writes_sample_mask
));
2897 if (pipeline
->device
->dfsm_allowed
) {
2898 /* optimise this? */
2899 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2900 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
2905 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs
*cs
,
2906 struct radv_pipeline
*pipeline
)
2908 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
2911 unsigned vtx_reuse_depth
= 30;
2912 if (radv_pipeline_has_tess(pipeline
) &&
2913 radv_get_tess_eval_shader(pipeline
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
2914 vtx_reuse_depth
= 14;
2916 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
2917 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
2921 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
2923 uint32_t stages
= 0;
2924 if (radv_pipeline_has_tess(pipeline
)) {
2925 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2926 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2928 if (radv_pipeline_has_gs(pipeline
))
2929 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2931 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2933 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2935 } else if (radv_pipeline_has_gs(pipeline
))
2936 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2938 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2940 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
2941 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2947 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
2948 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2949 const struct radv_graphics_pipeline_create_info
*extra
,
2950 const struct radv_blend_state
*blend
,
2951 const struct radv_tessellation_state
*tess
)
2953 pipeline
->cs
.buf
= malloc(4 * 256);
2954 pipeline
->cs
.max_dw
= 256;
2956 radv_pipeline_generate_depth_stencil_state(&pipeline
->cs
, pipeline
, pCreateInfo
, extra
);
2957 radv_pipeline_generate_blend_state(&pipeline
->cs
, pipeline
, blend
);
2958 radv_pipeline_generate_raster_state(&pipeline
->cs
, pipeline
);
2959 radv_pipeline_generate_multisample_state(&pipeline
->cs
, pipeline
);
2960 radv_pipeline_generate_vgt_gs_mode(&pipeline
->cs
, pipeline
);
2961 radv_pipeline_generate_vertex_shader(&pipeline
->cs
, pipeline
, tess
);
2962 radv_pipeline_generate_tess_shaders(&pipeline
->cs
, pipeline
, tess
);
2963 radv_pipeline_generate_geometry_shader(&pipeline
->cs
, pipeline
);
2964 radv_pipeline_generate_fragment_shader(&pipeline
->cs
, pipeline
);
2965 radv_pipeline_generate_ps_inputs(&pipeline
->cs
, pipeline
);
2966 radv_pipeline_generate_vgt_vertex_reuse(&pipeline
->cs
, pipeline
);
2967 radv_pipeline_generate_binning_state(&pipeline
->cs
, pipeline
, pCreateInfo
);
2969 radeon_set_context_reg(&pipeline
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
2970 S_0286E8_WAVES(pipeline
->max_waves
) |
2971 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2973 radeon_set_context_reg(&pipeline
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
2975 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2976 radeon_set_uconfig_reg_idx(&pipeline
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
2978 radeon_set_config_reg(&pipeline
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
2980 radeon_set_context_reg(&pipeline
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
2982 radeon_set_context_reg(&pipeline
->cs
, R_02820C_PA_SC_CLIPRECT_RULE
, pipeline
->graphics
.pa_sc_cliprect_rule
);
2984 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
2987 static struct radv_ia_multi_vgt_param_helpers
2988 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
2989 const struct radv_tessellation_state
*tess
)
2991 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
2992 const struct radv_device
*device
= pipeline
->device
;
2994 if (radv_pipeline_has_tess(pipeline
))
2995 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
2996 else if (radv_pipeline_has_gs(pipeline
))
2997 ia_multi_vgt_param
.primgroup_size
= 64;
2999 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
3001 ia_multi_vgt_param
.partial_es_wave
= false;
3002 if (pipeline
->device
->has_distributed_tess
) {
3003 if (radv_pipeline_has_gs(pipeline
)) {
3004 if (device
->physical_device
->rad_info
.chip_class
<= VI
)
3005 ia_multi_vgt_param
.partial_es_wave
= true;
3008 /* GS requirement. */
3009 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
3010 ia_multi_vgt_param
.partial_es_wave
= true;
3012 ia_multi_vgt_param
.wd_switch_on_eop
= false;
3013 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3014 unsigned prim
= pipeline
->graphics
.prim
;
3015 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3016 * 4 shader engines. Set 1 to pass the assertion below.
3017 * The other cases are hardware requirements. */
3018 if (device
->physical_device
->rad_info
.max_se
< 4 ||
3019 prim
== V_008958_DI_PT_POLYGON
||
3020 prim
== V_008958_DI_PT_LINELOOP
||
3021 prim
== V_008958_DI_PT_TRIFAN
||
3022 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
3023 (pipeline
->graphics
.prim_restart_enable
&&
3024 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
3025 (prim
!= V_008958_DI_PT_POINTLIST
&&
3026 prim
!= V_008958_DI_PT_LINESTRIP
&&
3027 prim
!= V_008958_DI_PT_TRISTRIP
))))
3028 ia_multi_vgt_param
.wd_switch_on_eop
= true;
3031 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
3032 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.fs
.prim_id_input
)
3033 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3034 if (radv_pipeline_has_gs(pipeline
) &&
3035 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.info
.uses_prim_id
)
3036 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3037 if (radv_pipeline_has_tess(pipeline
)) {
3038 /* SWITCH_ON_EOI must be set if PrimID is used. */
3039 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.uses_prim_id
||
3040 radv_get_tess_eval_shader(pipeline
)->info
.info
.uses_prim_id
)
3041 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3044 ia_multi_vgt_param
.partial_vs_wave
= false;
3045 if (radv_pipeline_has_tess(pipeline
)) {
3046 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3047 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
3048 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
3049 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
3050 radv_pipeline_has_gs(pipeline
))
3051 ia_multi_vgt_param
.partial_vs_wave
= true;
3052 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3053 if (device
->has_distributed_tess
) {
3054 if (radv_pipeline_has_gs(pipeline
)) {
3055 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
3056 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
3057 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
3058 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
3059 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
)
3060 ia_multi_vgt_param
.partial_vs_wave
= true;
3062 ia_multi_vgt_param
.partial_vs_wave
= true;
3067 ia_multi_vgt_param
.base
=
3068 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
3069 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3070 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== VI
? 2 : 0) |
3071 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
3072 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
3074 return ia_multi_vgt_param
;
3079 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
3080 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3082 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
3083 pCreateInfo
->pVertexInputState
;
3084 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
3086 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
3087 const VkVertexInputAttributeDescription
*desc
=
3088 &vi_info
->pVertexAttributeDescriptions
[i
];
3089 unsigned loc
= desc
->location
;
3090 const struct vk_format_description
*format_desc
;
3092 uint32_t num_format
, data_format
;
3093 format_desc
= vk_format_description(desc
->format
);
3094 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
3096 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
3097 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
3099 velems
->rsrc_word3
[loc
] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc
->swizzle
[0])) |
3100 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc
->swizzle
[1])) |
3101 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc
->swizzle
[2])) |
3102 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc
->swizzle
[3])) |
3103 S_008F0C_NUM_FORMAT(num_format
) |
3104 S_008F0C_DATA_FORMAT(data_format
);
3105 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
3106 velems
->offset
[loc
] = desc
->offset
;
3107 velems
->binding
[loc
] = desc
->binding
;
3108 velems
->count
= MAX2(velems
->count
, loc
+ 1);
3111 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
3112 const VkVertexInputBindingDescription
*desc
=
3113 &vi_info
->pVertexBindingDescriptions
[i
];
3115 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
3120 radv_pipeline_init(struct radv_pipeline
*pipeline
,
3121 struct radv_device
*device
,
3122 struct radv_pipeline_cache
*cache
,
3123 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3124 const struct radv_graphics_pipeline_create_info
*extra
,
3125 const VkAllocationCallbacks
*alloc
)
3128 bool has_view_index
= false;
3130 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3131 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3132 if (subpass
->view_mask
)
3133 has_view_index
= true;
3135 alloc
= &device
->alloc
;
3137 pipeline
->device
= device
;
3138 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3139 assert(pipeline
->layout
);
3141 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
3143 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3144 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
3145 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
3146 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
3149 radv_create_shaders(pipeline
, device
, cache
,
3150 radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
),
3153 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
3154 radv_pipeline_init_raster_state(pipeline
, pCreateInfo
);
3155 radv_pipeline_init_multisample_state(pipeline
, pCreateInfo
);
3156 pipeline
->graphics
.prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
3157 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
3159 if (radv_pipeline_has_gs(pipeline
)) {
3160 pipeline
->graphics
.gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
3161 pipeline
->graphics
.can_use_guardband
= pipeline
->graphics
.gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3163 pipeline
->graphics
.gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
3165 if (extra
&& extra
->use_rectlist
) {
3166 pipeline
->graphics
.prim
= V_008958_DI_PT_RECTLIST
;
3167 pipeline
->graphics
.gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3168 pipeline
->graphics
.can_use_guardband
= true;
3170 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
3171 /* prim vertex count will need TESS changes */
3172 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[pipeline
->graphics
.prim
];
3174 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
3176 /* Ensure that some export memory is always allocated, for two reasons:
3178 * 1) Correctness: The hardware ignores the EXEC mask if no export
3179 * memory is allocated, so KILL and alpha test do not work correctly
3181 * 2) Performance: Every shader needs at least a NULL export, even when
3182 * it writes no color/depth output. The NULL export instruction
3183 * stalls without this setting.
3185 * Don't add this to CB_SHADER_MASK.
3187 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3188 if (!blend
.spi_shader_col_format
) {
3189 if (!ps
->info
.fs
.writes_z
&&
3190 !ps
->info
.fs
.writes_stencil
&&
3191 !ps
->info
.fs
.writes_sample_mask
)
3192 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
3195 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
3196 if (pipeline
->shaders
[i
]) {
3197 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
3201 if (radv_pipeline_has_gs(pipeline
)) {
3202 calculate_gs_ring_sizes(pipeline
);
3203 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
3204 calculate_gfx9_gs_info(pCreateInfo
, pipeline
);
3207 struct radv_tessellation_state tess
= {0};
3208 if (radv_pipeline_has_tess(pipeline
)) {
3209 if (pipeline
->graphics
.prim
== V_008958_DI_PT_PATCH
) {
3210 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
3211 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
3213 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
3216 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
);
3218 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
3220 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
3221 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
3223 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
3224 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
3225 if (loc
->sgpr_idx
!= -1) {
3226 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
3227 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
3228 if (radv_get_vertex_shader(pipeline
)->info
.info
.vs
.needs_draw_id
)
3229 pipeline
->graphics
.vtx_emit_num
= 3;
3231 pipeline
->graphics
.vtx_emit_num
= 2;
3234 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
3235 radv_dump_pipeline_stats(device
, pipeline
);
3238 result
= radv_pipeline_scratch_init(device
, pipeline
);
3239 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
);
3245 radv_graphics_pipeline_create(
3247 VkPipelineCache _cache
,
3248 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3249 const struct radv_graphics_pipeline_create_info
*extra
,
3250 const VkAllocationCallbacks
*pAllocator
,
3251 VkPipeline
*pPipeline
)
3253 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3254 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3255 struct radv_pipeline
*pipeline
;
3258 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3259 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3260 if (pipeline
== NULL
)
3261 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3263 result
= radv_pipeline_init(pipeline
, device
, cache
,
3264 pCreateInfo
, extra
, pAllocator
);
3265 if (result
!= VK_SUCCESS
) {
3266 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3270 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3275 VkResult
radv_CreateGraphicsPipelines(
3277 VkPipelineCache pipelineCache
,
3279 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
3280 const VkAllocationCallbacks
* pAllocator
,
3281 VkPipeline
* pPipelines
)
3283 VkResult result
= VK_SUCCESS
;
3286 for (; i
< count
; i
++) {
3288 r
= radv_graphics_pipeline_create(_device
,
3291 NULL
, pAllocator
, &pPipelines
[i
]);
3292 if (r
!= VK_SUCCESS
) {
3294 pPipelines
[i
] = VK_NULL_HANDLE
;
3303 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
3305 struct radv_shader_variant
*compute_shader
;
3306 struct radv_device
*device
= pipeline
->device
;
3307 unsigned compute_resource_limits
;
3308 unsigned waves_per_threadgroup
;
3311 pipeline
->cs
.buf
= malloc(20 * 4);
3312 pipeline
->cs
.max_dw
= 20;
3314 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3315 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
3317 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
3318 radeon_emit(&pipeline
->cs
, va
>> 8);
3319 radeon_emit(&pipeline
->cs
, va
>> 40);
3321 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
3322 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc1
);
3323 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc2
);
3325 radeon_set_sh_reg(&pipeline
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3326 S_00B860_WAVES(pipeline
->max_waves
) |
3327 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3329 /* Calculate best compute resource limits. */
3330 waves_per_threadgroup
=
3331 DIV_ROUND_UP(compute_shader
->info
.cs
.block_size
[0] *
3332 compute_shader
->info
.cs
.block_size
[1] *
3333 compute_shader
->info
.cs
.block_size
[2], 64);
3334 compute_resource_limits
=
3335 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
3337 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3338 unsigned num_cu_per_se
=
3339 device
->physical_device
->rad_info
.num_good_compute_units
/
3340 device
->physical_device
->rad_info
.max_se
;
3342 /* Force even distribution on all SIMDs in CU if the workgroup
3343 * size is 64. This has shown some good improvements if # of
3344 * CUs per SE is not a multiple of 4.
3346 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
3347 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
3350 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
3351 compute_resource_limits
);
3353 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3354 radeon_emit(&pipeline
->cs
,
3355 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
3356 radeon_emit(&pipeline
->cs
,
3357 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
3358 radeon_emit(&pipeline
->cs
,
3359 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
3361 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
3364 static VkResult
radv_compute_pipeline_create(
3366 VkPipelineCache _cache
,
3367 const VkComputePipelineCreateInfo
* pCreateInfo
,
3368 const VkAllocationCallbacks
* pAllocator
,
3369 VkPipeline
* pPipeline
)
3371 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3372 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3373 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3374 struct radv_pipeline
*pipeline
;
3377 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3378 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3379 if (pipeline
== NULL
)
3380 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3382 pipeline
->device
= device
;
3383 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3384 assert(pipeline
->layout
);
3386 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
3387 radv_create_shaders(pipeline
, device
, cache
, (struct radv_pipeline_key
) {0}, pStages
);
3389 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
3390 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
3391 result
= radv_pipeline_scratch_init(device
, pipeline
);
3392 if (result
!= VK_SUCCESS
) {
3393 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3397 radv_compute_generate_pm4(pipeline
);
3399 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3401 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) {
3402 radv_dump_pipeline_stats(device
, pipeline
);
3407 VkResult
radv_CreateComputePipelines(
3409 VkPipelineCache pipelineCache
,
3411 const VkComputePipelineCreateInfo
* pCreateInfos
,
3412 const VkAllocationCallbacks
* pAllocator
,
3413 VkPipeline
* pPipelines
)
3415 VkResult result
= VK_SUCCESS
;
3418 for (; i
< count
; i
++) {
3420 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
3422 pAllocator
, &pPipelines
[i
]);
3423 if (r
!= VK_SUCCESS
) {
3425 pPipelines
[i
] = VK_NULL_HANDLE
;