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radv/tess: remove last chunk of tess sgprs
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t cb_color_control;
54 uint32_t cb_target_mask;
55 uint32_t sx_mrt_blend_opt[8];
56 uint32_t cb_blend_control[8];
57
58 uint32_t spi_shader_col_format;
59 uint32_t cb_shader_mask;
60 uint32_t db_alpha_to_mask;
61 };
62
63 struct radv_tessellation_state {
64 uint32_t ls_hs_config;
65 unsigned num_patches;
66 unsigned lds_size;
67 uint32_t tf_param;
68 };
69
70 struct radv_gs_state {
71 uint32_t vgt_gs_onchip_cntl;
72 uint32_t vgt_gs_max_prims_per_subgroup;
73 uint32_t vgt_esgs_ring_itemsize;
74 uint32_t lds_size;
75 };
76
77 static void
78 radv_pipeline_destroy(struct radv_device *device,
79 struct radv_pipeline *pipeline,
80 const VkAllocationCallbacks* allocator)
81 {
82 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
83 if (pipeline->shaders[i])
84 radv_shader_variant_destroy(device, pipeline->shaders[i]);
85
86 if (pipeline->gs_copy_shader)
87 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
88
89 if(pipeline->cs.buf)
90 free(pipeline->cs.buf);
91 vk_free2(&device->alloc, allocator, pipeline);
92 }
93
94 void radv_DestroyPipeline(
95 VkDevice _device,
96 VkPipeline _pipeline,
97 const VkAllocationCallbacks* pAllocator)
98 {
99 RADV_FROM_HANDLE(radv_device, device, _device);
100 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
101
102 if (!_pipeline)
103 return;
104
105 radv_pipeline_destroy(device, pipeline, pAllocator);
106 }
107
108 static uint32_t get_hash_flags(struct radv_device *device)
109 {
110 uint32_t hash_flags = 0;
111
112 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
113 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
114 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
115 hash_flags |= RADV_HASH_SHADER_SISCHED;
116 return hash_flags;
117 }
118
119 static VkResult
120 radv_pipeline_scratch_init(struct radv_device *device,
121 struct radv_pipeline *pipeline)
122 {
123 unsigned scratch_bytes_per_wave = 0;
124 unsigned max_waves = 0;
125 unsigned min_waves = 1;
126
127 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
128 if (pipeline->shaders[i]) {
129 unsigned max_stage_waves = device->scratch_waves;
130
131 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
132 pipeline->shaders[i]->config.scratch_bytes_per_wave);
133
134 max_stage_waves = MIN2(max_stage_waves,
135 4 * device->physical_device->rad_info.num_good_compute_units *
136 (256 / pipeline->shaders[i]->config.num_vgprs));
137 max_waves = MAX2(max_waves, max_stage_waves);
138 }
139 }
140
141 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
142 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
143 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
144 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
145 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
146 }
147
148 if (scratch_bytes_per_wave)
149 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
150
151 if (scratch_bytes_per_wave && max_waves < min_waves) {
152 /* Not really true at this moment, but will be true on first
153 * execution. Avoid having hanging shaders. */
154 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
155 }
156 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
157 pipeline->max_waves = max_waves;
158 return VK_SUCCESS;
159 }
160
161 static uint32_t si_translate_blend_function(VkBlendOp op)
162 {
163 switch (op) {
164 case VK_BLEND_OP_ADD:
165 return V_028780_COMB_DST_PLUS_SRC;
166 case VK_BLEND_OP_SUBTRACT:
167 return V_028780_COMB_SRC_MINUS_DST;
168 case VK_BLEND_OP_REVERSE_SUBTRACT:
169 return V_028780_COMB_DST_MINUS_SRC;
170 case VK_BLEND_OP_MIN:
171 return V_028780_COMB_MIN_DST_SRC;
172 case VK_BLEND_OP_MAX:
173 return V_028780_COMB_MAX_DST_SRC;
174 default:
175 return 0;
176 }
177 }
178
179 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
180 {
181 switch (factor) {
182 case VK_BLEND_FACTOR_ZERO:
183 return V_028780_BLEND_ZERO;
184 case VK_BLEND_FACTOR_ONE:
185 return V_028780_BLEND_ONE;
186 case VK_BLEND_FACTOR_SRC_COLOR:
187 return V_028780_BLEND_SRC_COLOR;
188 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
189 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
190 case VK_BLEND_FACTOR_DST_COLOR:
191 return V_028780_BLEND_DST_COLOR;
192 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
193 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
194 case VK_BLEND_FACTOR_SRC_ALPHA:
195 return V_028780_BLEND_SRC_ALPHA;
196 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
197 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
198 case VK_BLEND_FACTOR_DST_ALPHA:
199 return V_028780_BLEND_DST_ALPHA;
200 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
201 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
202 case VK_BLEND_FACTOR_CONSTANT_COLOR:
203 return V_028780_BLEND_CONSTANT_COLOR;
204 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
205 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
206 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
207 return V_028780_BLEND_CONSTANT_ALPHA;
208 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
209 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
210 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
211 return V_028780_BLEND_SRC_ALPHA_SATURATE;
212 case VK_BLEND_FACTOR_SRC1_COLOR:
213 return V_028780_BLEND_SRC1_COLOR;
214 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
215 return V_028780_BLEND_INV_SRC1_COLOR;
216 case VK_BLEND_FACTOR_SRC1_ALPHA:
217 return V_028780_BLEND_SRC1_ALPHA;
218 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
219 return V_028780_BLEND_INV_SRC1_ALPHA;
220 default:
221 return 0;
222 }
223 }
224
225 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
226 {
227 switch (op) {
228 case VK_BLEND_OP_ADD:
229 return V_028760_OPT_COMB_ADD;
230 case VK_BLEND_OP_SUBTRACT:
231 return V_028760_OPT_COMB_SUBTRACT;
232 case VK_BLEND_OP_REVERSE_SUBTRACT:
233 return V_028760_OPT_COMB_REVSUBTRACT;
234 case VK_BLEND_OP_MIN:
235 return V_028760_OPT_COMB_MIN;
236 case VK_BLEND_OP_MAX:
237 return V_028760_OPT_COMB_MAX;
238 default:
239 return V_028760_OPT_COMB_BLEND_DISABLED;
240 }
241 }
242
243 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
244 {
245 switch (factor) {
246 case VK_BLEND_FACTOR_ZERO:
247 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
248 case VK_BLEND_FACTOR_ONE:
249 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
250 case VK_BLEND_FACTOR_SRC_COLOR:
251 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
252 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
253 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
254 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
255 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
256 case VK_BLEND_FACTOR_SRC_ALPHA:
257 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
258 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
259 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
260 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
261 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
262 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
263 default:
264 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
265 }
266 }
267
268 /**
269 * Get rid of DST in the blend factors by commuting the operands:
270 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
271 */
272 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
273 unsigned *dst_factor, unsigned expected_dst,
274 unsigned replacement_src)
275 {
276 if (*src_factor == expected_dst &&
277 *dst_factor == VK_BLEND_FACTOR_ZERO) {
278 *src_factor = VK_BLEND_FACTOR_ZERO;
279 *dst_factor = replacement_src;
280
281 /* Commuting the operands requires reversing subtractions. */
282 if (*func == VK_BLEND_OP_SUBTRACT)
283 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
284 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
285 *func = VK_BLEND_OP_SUBTRACT;
286 }
287 }
288
289 static bool si_blend_factor_uses_dst(unsigned factor)
290 {
291 return factor == VK_BLEND_FACTOR_DST_COLOR ||
292 factor == VK_BLEND_FACTOR_DST_ALPHA ||
293 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
294 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
295 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
296 }
297
298 static bool is_dual_src(VkBlendFactor factor)
299 {
300 switch (factor) {
301 case VK_BLEND_FACTOR_SRC1_COLOR:
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
303 case VK_BLEND_FACTOR_SRC1_ALPHA:
304 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
305 return true;
306 default:
307 return false;
308 }
309 }
310
311 static unsigned si_choose_spi_color_format(VkFormat vk_format,
312 bool blend_enable,
313 bool blend_need_alpha)
314 {
315 const struct vk_format_description *desc = vk_format_description(vk_format);
316 unsigned format, ntype, swap;
317
318 /* Alpha is needed for alpha-to-coverage.
319 * Blending may be with or without alpha.
320 */
321 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
322 unsigned alpha = 0; /* exports alpha, but may not support blending */
323 unsigned blend = 0; /* supports blending, but may not export alpha */
324 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
325
326 format = radv_translate_colorformat(vk_format);
327 ntype = radv_translate_color_numformat(vk_format, desc,
328 vk_format_get_first_non_void_channel(vk_format));
329 swap = radv_translate_colorswap(vk_format, false);
330
331 /* Choose the SPI color formats. These are required values for Stoney/RB+.
332 * Other chips have multiple choices, though they are not necessarily better.
333 */
334 switch (format) {
335 case V_028C70_COLOR_5_6_5:
336 case V_028C70_COLOR_1_5_5_5:
337 case V_028C70_COLOR_5_5_5_1:
338 case V_028C70_COLOR_4_4_4_4:
339 case V_028C70_COLOR_10_11_11:
340 case V_028C70_COLOR_11_11_10:
341 case V_028C70_COLOR_8:
342 case V_028C70_COLOR_8_8:
343 case V_028C70_COLOR_8_8_8_8:
344 case V_028C70_COLOR_10_10_10_2:
345 case V_028C70_COLOR_2_10_10_10:
346 if (ntype == V_028C70_NUMBER_UINT)
347 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
348 else if (ntype == V_028C70_NUMBER_SINT)
349 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
350 else
351 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
352 break;
353
354 case V_028C70_COLOR_16:
355 case V_028C70_COLOR_16_16:
356 case V_028C70_COLOR_16_16_16_16:
357 if (ntype == V_028C70_NUMBER_UNORM ||
358 ntype == V_028C70_NUMBER_SNORM) {
359 /* UNORM16 and SNORM16 don't support blending */
360 if (ntype == V_028C70_NUMBER_UNORM)
361 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
362 else
363 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
364
365 /* Use 32 bits per channel for blending. */
366 if (format == V_028C70_COLOR_16) {
367 if (swap == V_028C70_SWAP_STD) { /* R */
368 blend = V_028714_SPI_SHADER_32_R;
369 blend_alpha = V_028714_SPI_SHADER_32_AR;
370 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
371 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
372 else
373 assert(0);
374 } else if (format == V_028C70_COLOR_16_16) {
375 if (swap == V_028C70_SWAP_STD) { /* RG */
376 blend = V_028714_SPI_SHADER_32_GR;
377 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
378 } else if (swap == V_028C70_SWAP_ALT) /* RA */
379 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
380 else
381 assert(0);
382 } else /* 16_16_16_16 */
383 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
384 } else if (ntype == V_028C70_NUMBER_UINT)
385 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
386 else if (ntype == V_028C70_NUMBER_SINT)
387 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
388 else if (ntype == V_028C70_NUMBER_FLOAT)
389 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
390 else
391 assert(0);
392 break;
393
394 case V_028C70_COLOR_32:
395 if (swap == V_028C70_SWAP_STD) { /* R */
396 blend = normal = V_028714_SPI_SHADER_32_R;
397 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
398 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
399 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
400 else
401 assert(0);
402 break;
403
404 case V_028C70_COLOR_32_32:
405 if (swap == V_028C70_SWAP_STD) { /* RG */
406 blend = normal = V_028714_SPI_SHADER_32_GR;
407 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
408 } else if (swap == V_028C70_SWAP_ALT) /* RA */
409 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
410 else
411 assert(0);
412 break;
413
414 case V_028C70_COLOR_32_32_32_32:
415 case V_028C70_COLOR_8_24:
416 case V_028C70_COLOR_24_8:
417 case V_028C70_COLOR_X24_8_32_FLOAT:
418 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
419 break;
420
421 default:
422 unreachable("unhandled blend format");
423 }
424
425 if (blend_enable && blend_need_alpha)
426 return blend_alpha;
427 else if(blend_need_alpha)
428 return alpha;
429 else if(blend_enable)
430 return blend;
431 else
432 return normal;
433 }
434
435 static void
436 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
437 const VkGraphicsPipelineCreateInfo *pCreateInfo,
438 uint32_t blend_enable,
439 uint32_t blend_need_alpha,
440 bool single_cb_enable,
441 bool blend_mrt0_is_dual_src,
442 struct radv_blend_state *blend)
443 {
444 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
445 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
446 unsigned col_format = 0;
447
448 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
449 unsigned cf;
450
451 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
452 cf = V_028714_SPI_SHADER_ZERO;
453 } else {
454 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
455
456 cf = si_choose_spi_color_format(attachment->format,
457 blend_enable & (1 << i),
458 blend_need_alpha & (1 << i));
459 }
460
461 col_format |= cf << (4 * i);
462 }
463
464 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
465
466 if (blend_mrt0_is_dual_src)
467 col_format |= (col_format & 0xf) << 4;
468 blend->spi_shader_col_format = col_format;
469 }
470
471 static bool
472 format_is_int8(VkFormat format)
473 {
474 const struct vk_format_description *desc = vk_format_description(format);
475 int channel = vk_format_get_first_non_void_channel(format);
476
477 return channel >= 0 && desc->channel[channel].pure_integer &&
478 desc->channel[channel].size == 8;
479 }
480
481 static bool
482 format_is_int10(VkFormat format)
483 {
484 const struct vk_format_description *desc = vk_format_description(format);
485
486 if (desc->nr_channels != 4)
487 return false;
488 for (unsigned i = 0; i < 4; i++) {
489 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
490 return true;
491 }
492 return false;
493 }
494
495 unsigned radv_format_meta_fs_key(VkFormat format)
496 {
497 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
498 bool is_int8 = format_is_int8(format);
499 bool is_int10 = format_is_int10(format);
500
501 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
502 }
503
504 static void
505 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
506 unsigned *is_int8, unsigned *is_int10)
507 {
508 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
509 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
510 *is_int8 = 0;
511 *is_int10 = 0;
512
513 for (unsigned i = 0; i < subpass->color_count; ++i) {
514 struct radv_render_pass_attachment *attachment;
515
516 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
517 continue;
518
519 attachment = pass->attachments + subpass->color_attachments[i].attachment;
520
521 if (format_is_int8(attachment->format))
522 *is_int8 |= 1 << i;
523 if (format_is_int10(attachment->format))
524 *is_int10 |= 1 << i;
525 }
526 }
527
528 static struct radv_blend_state
529 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
530 const VkGraphicsPipelineCreateInfo *pCreateInfo,
531 const struct radv_graphics_pipeline_create_info *extra)
532 {
533 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
534 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
535 struct radv_blend_state blend = {0};
536 unsigned mode = V_028808_CB_NORMAL;
537 uint32_t blend_enable = 0, blend_need_alpha = 0;
538 bool blend_mrt0_is_dual_src = false;
539 int i;
540 bool single_cb_enable = false;
541
542 if (!vkblend)
543 return blend;
544
545 if (extra && extra->custom_blend_mode) {
546 single_cb_enable = true;
547 mode = extra->custom_blend_mode;
548 }
549 blend.cb_color_control = 0;
550 if (vkblend->logicOpEnable)
551 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
552 else
553 blend.cb_color_control |= S_028808_ROP3(0xcc);
554
555 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
556 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
557 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
558 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
559
560 if (vkms && vkms->alphaToCoverageEnable) {
561 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
562 }
563
564 blend.cb_target_mask = 0;
565 for (i = 0; i < vkblend->attachmentCount; i++) {
566 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
567 unsigned blend_cntl = 0;
568 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
569 VkBlendOp eqRGB = att->colorBlendOp;
570 VkBlendFactor srcRGB = att->srcColorBlendFactor;
571 VkBlendFactor dstRGB = att->dstColorBlendFactor;
572 VkBlendOp eqA = att->alphaBlendOp;
573 VkBlendFactor srcA = att->srcAlphaBlendFactor;
574 VkBlendFactor dstA = att->dstAlphaBlendFactor;
575
576 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
577
578 if (!att->colorWriteMask)
579 continue;
580
581 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
582 if (!att->blendEnable) {
583 blend.cb_blend_control[i] = blend_cntl;
584 continue;
585 }
586
587 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
588 if (i == 0)
589 blend_mrt0_is_dual_src = true;
590
591 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
592 srcRGB = VK_BLEND_FACTOR_ONE;
593 dstRGB = VK_BLEND_FACTOR_ONE;
594 }
595 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
596 srcA = VK_BLEND_FACTOR_ONE;
597 dstA = VK_BLEND_FACTOR_ONE;
598 }
599
600 /* Blending optimizations for RB+.
601 * These transformations don't change the behavior.
602 *
603 * First, get rid of DST in the blend factors:
604 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
605 */
606 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
607 VK_BLEND_FACTOR_DST_COLOR,
608 VK_BLEND_FACTOR_SRC_COLOR);
609
610 si_blend_remove_dst(&eqA, &srcA, &dstA,
611 VK_BLEND_FACTOR_DST_COLOR,
612 VK_BLEND_FACTOR_SRC_COLOR);
613
614 si_blend_remove_dst(&eqA, &srcA, &dstA,
615 VK_BLEND_FACTOR_DST_ALPHA,
616 VK_BLEND_FACTOR_SRC_ALPHA);
617
618 /* Look up the ideal settings from tables. */
619 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
620 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
621 srcA_opt = si_translate_blend_opt_factor(srcA, true);
622 dstA_opt = si_translate_blend_opt_factor(dstA, true);
623
624 /* Handle interdependencies. */
625 if (si_blend_factor_uses_dst(srcRGB))
626 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
627 if (si_blend_factor_uses_dst(srcA))
628 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
629
630 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
631 (dstRGB == VK_BLEND_FACTOR_ZERO ||
632 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
633 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
634 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
635
636 /* Set the final value. */
637 blend.sx_mrt_blend_opt[i] =
638 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
639 S_028760_COLOR_DST_OPT(dstRGB_opt) |
640 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
641 S_028760_ALPHA_SRC_OPT(srcA_opt) |
642 S_028760_ALPHA_DST_OPT(dstA_opt) |
643 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
644 blend_cntl |= S_028780_ENABLE(1);
645
646 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
647 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
648 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
649 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
650 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
651 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
652 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
653 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
654 }
655 blend.cb_blend_control[i] = blend_cntl;
656
657 blend_enable |= 1 << i;
658
659 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
660 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
661 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
662 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
663 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
664 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
665 blend_need_alpha |= 1 << i;
666 }
667 for (i = vkblend->attachmentCount; i < 8; i++) {
668 blend.cb_blend_control[i] = 0;
669 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
670 }
671
672 /* disable RB+ for now */
673 if (pipeline->device->physical_device->has_rbplus)
674 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
675
676 if (blend.cb_target_mask)
677 blend.cb_color_control |= S_028808_MODE(mode);
678 else
679 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
680
681 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
682 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src,
683 &blend);
684 return blend;
685 }
686
687 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
688 {
689 switch (op) {
690 case VK_STENCIL_OP_KEEP:
691 return V_02842C_STENCIL_KEEP;
692 case VK_STENCIL_OP_ZERO:
693 return V_02842C_STENCIL_ZERO;
694 case VK_STENCIL_OP_REPLACE:
695 return V_02842C_STENCIL_REPLACE_TEST;
696 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
697 return V_02842C_STENCIL_ADD_CLAMP;
698 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
699 return V_02842C_STENCIL_SUB_CLAMP;
700 case VK_STENCIL_OP_INVERT:
701 return V_02842C_STENCIL_INVERT;
702 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
703 return V_02842C_STENCIL_ADD_WRAP;
704 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
705 return V_02842C_STENCIL_SUB_WRAP;
706 default:
707 return 0;
708 }
709 }
710
711 static uint32_t si_translate_fill(VkPolygonMode func)
712 {
713 switch(func) {
714 case VK_POLYGON_MODE_FILL:
715 return V_028814_X_DRAW_TRIANGLES;
716 case VK_POLYGON_MODE_LINE:
717 return V_028814_X_DRAW_LINES;
718 case VK_POLYGON_MODE_POINT:
719 return V_028814_X_DRAW_POINTS;
720 default:
721 assert(0);
722 return V_028814_X_DRAW_POINTS;
723 }
724 }
725
726 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
727 {
728 uint32_t num_samples = vkms->rasterizationSamples;
729 uint32_t ps_iter_samples = 1;
730
731 if (vkms->sampleShadingEnable) {
732 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
733 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
734 }
735 return ps_iter_samples;
736 }
737
738 static void
739 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
740 const VkGraphicsPipelineCreateInfo *pCreateInfo)
741 {
742 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
743 struct radv_multisample_state *ms = &pipeline->graphics.ms;
744 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
745 int ps_iter_samples = 1;
746 uint32_t mask = 0xffff;
747
748 if (vkms)
749 ms->num_samples = vkms->rasterizationSamples;
750 else
751 ms->num_samples = 1;
752
753 if (vkms)
754 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
755 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
756 ps_iter_samples = ms->num_samples;
757 }
758
759 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
760 ms->pa_sc_aa_config = 0;
761 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
762 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
763 ms->pa_sc_mode_cntl_1 =
764 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
765 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
766 /* always 1: */
767 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
768 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
769 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
770 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
771 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
772 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
773 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
774 S_028A48_VPORT_SCISSOR_ENABLE(1);
775
776 if (ms->num_samples > 1) {
777 unsigned log_samples = util_logbase2(ms->num_samples);
778 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
779 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
780 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
781 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
782 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
783 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
784 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
785 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
786 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
787 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
788 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
789 if (ps_iter_samples > 1)
790 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
791 }
792
793 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
794 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
795 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
796 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
797 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
798 }
799
800 if (vkms && vkms->pSampleMask) {
801 mask = vkms->pSampleMask[0] & 0xffff;
802 }
803
804 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
805 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
806 }
807
808 static bool
809 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
810 {
811 switch (topology) {
812 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
813 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
814 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
815 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
816 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
817 return false;
818 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
819 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
820 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
821 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
822 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
823 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
824 return true;
825 default:
826 unreachable("unhandled primitive type");
827 }
828 }
829
830 static uint32_t
831 si_translate_prim(enum VkPrimitiveTopology topology)
832 {
833 switch (topology) {
834 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
835 return V_008958_DI_PT_POINTLIST;
836 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
837 return V_008958_DI_PT_LINELIST;
838 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
839 return V_008958_DI_PT_LINESTRIP;
840 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
841 return V_008958_DI_PT_TRILIST;
842 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
843 return V_008958_DI_PT_TRISTRIP;
844 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
845 return V_008958_DI_PT_TRIFAN;
846 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
847 return V_008958_DI_PT_LINELIST_ADJ;
848 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
849 return V_008958_DI_PT_LINESTRIP_ADJ;
850 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
851 return V_008958_DI_PT_TRILIST_ADJ;
852 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
853 return V_008958_DI_PT_TRISTRIP_ADJ;
854 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
855 return V_008958_DI_PT_PATCH;
856 default:
857 assert(0);
858 return 0;
859 }
860 }
861
862 static uint32_t
863 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
864 {
865 switch (gl_prim) {
866 case 0: /* GL_POINTS */
867 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
868 case 1: /* GL_LINES */
869 case 3: /* GL_LINE_STRIP */
870 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
871 case 0x8E7A: /* GL_ISOLINES */
872 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
873
874 case 4: /* GL_TRIANGLES */
875 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
876 case 5: /* GL_TRIANGLE_STRIP */
877 case 7: /* GL_QUADS */
878 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
879 default:
880 assert(0);
881 return 0;
882 }
883 }
884
885 static uint32_t
886 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
887 {
888 switch (topology) {
889 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
890 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
891 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
892 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
893 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
894 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
895 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
896 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
897 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
898 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
899 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
900 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
901 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
902 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
903 default:
904 assert(0);
905 return 0;
906 }
907 }
908
909 static unsigned si_map_swizzle(unsigned swizzle)
910 {
911 switch (swizzle) {
912 case VK_SWIZZLE_Y:
913 return V_008F0C_SQ_SEL_Y;
914 case VK_SWIZZLE_Z:
915 return V_008F0C_SQ_SEL_Z;
916 case VK_SWIZZLE_W:
917 return V_008F0C_SQ_SEL_W;
918 case VK_SWIZZLE_0:
919 return V_008F0C_SQ_SEL_0;
920 case VK_SWIZZLE_1:
921 return V_008F0C_SQ_SEL_1;
922 default: /* VK_SWIZZLE_X */
923 return V_008F0C_SQ_SEL_X;
924 }
925 }
926
927
928 static unsigned radv_dynamic_state_mask(VkDynamicState state)
929 {
930 switch(state) {
931 case VK_DYNAMIC_STATE_VIEWPORT:
932 return RADV_DYNAMIC_VIEWPORT;
933 case VK_DYNAMIC_STATE_SCISSOR:
934 return RADV_DYNAMIC_SCISSOR;
935 case VK_DYNAMIC_STATE_LINE_WIDTH:
936 return RADV_DYNAMIC_LINE_WIDTH;
937 case VK_DYNAMIC_STATE_DEPTH_BIAS:
938 return RADV_DYNAMIC_DEPTH_BIAS;
939 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
940 return RADV_DYNAMIC_BLEND_CONSTANTS;
941 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
942 return RADV_DYNAMIC_DEPTH_BOUNDS;
943 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
944 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
945 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
946 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
947 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
948 return RADV_DYNAMIC_STENCIL_REFERENCE;
949 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
950 return RADV_DYNAMIC_DISCARD_RECTANGLE;
951 default:
952 unreachable("Unhandled dynamic state");
953 }
954 }
955
956 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
957 {
958 uint32_t states = RADV_DYNAMIC_ALL;
959
960 /* If rasterization is disabled we do not care about any of the dynamic states,
961 * since they are all rasterization related only. */
962 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
963 return 0;
964
965 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
966 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
967
968 if (!pCreateInfo->pDepthStencilState ||
969 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
970 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
971
972 if (!pCreateInfo->pDepthStencilState ||
973 !pCreateInfo->pDepthStencilState->stencilTestEnable)
974 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
975 RADV_DYNAMIC_STENCIL_WRITE_MASK |
976 RADV_DYNAMIC_STENCIL_REFERENCE);
977
978 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
979 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
980
981 /* TODO: blend constants & line width. */
982
983 return states;
984 }
985
986
987 static void
988 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
989 const VkGraphicsPipelineCreateInfo *pCreateInfo)
990 {
991 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
992 uint32_t states = needed_states;
993 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
994 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
995
996 pipeline->dynamic_state = default_dynamic_state;
997 pipeline->graphics.needed_dynamic_state = needed_states;
998
999 if (pCreateInfo->pDynamicState) {
1000 /* Remove all of the states that are marked as dynamic */
1001 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1002 for (uint32_t s = 0; s < count; s++)
1003 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1004 }
1005
1006 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1007
1008 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1009 assert(pCreateInfo->pViewportState);
1010
1011 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1012 if (states & RADV_DYNAMIC_VIEWPORT) {
1013 typed_memcpy(dynamic->viewport.viewports,
1014 pCreateInfo->pViewportState->pViewports,
1015 pCreateInfo->pViewportState->viewportCount);
1016 }
1017 }
1018
1019 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1020 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1021 if (states & RADV_DYNAMIC_SCISSOR) {
1022 typed_memcpy(dynamic->scissor.scissors,
1023 pCreateInfo->pViewportState->pScissors,
1024 pCreateInfo->pViewportState->scissorCount);
1025 }
1026 }
1027
1028 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1029 assert(pCreateInfo->pRasterizationState);
1030 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1031 }
1032
1033 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1034 assert(pCreateInfo->pRasterizationState);
1035 dynamic->depth_bias.bias =
1036 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1037 dynamic->depth_bias.clamp =
1038 pCreateInfo->pRasterizationState->depthBiasClamp;
1039 dynamic->depth_bias.slope =
1040 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1041 }
1042
1043 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1044 *
1045 * pColorBlendState is [...] NULL if the pipeline has rasterization
1046 * disabled or if the subpass of the render pass the pipeline is
1047 * created against does not use any color attachments.
1048 */
1049 bool uses_color_att = false;
1050 for (unsigned i = 0; i < subpass->color_count; ++i) {
1051 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1052 uses_color_att = true;
1053 break;
1054 }
1055 }
1056
1057 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1058 assert(pCreateInfo->pColorBlendState);
1059 typed_memcpy(dynamic->blend_constants,
1060 pCreateInfo->pColorBlendState->blendConstants, 4);
1061 }
1062
1063 /* If there is no depthstencil attachment, then don't read
1064 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1065 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1066 * no need to override the depthstencil defaults in
1067 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1068 *
1069 * Section 9.2 of the Vulkan 1.0.15 spec says:
1070 *
1071 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1072 * disabled or if the subpass of the render pass the pipeline is created
1073 * against does not use a depth/stencil attachment.
1074 */
1075 if (needed_states &&
1076 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1077 assert(pCreateInfo->pDepthStencilState);
1078
1079 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1080 dynamic->depth_bounds.min =
1081 pCreateInfo->pDepthStencilState->minDepthBounds;
1082 dynamic->depth_bounds.max =
1083 pCreateInfo->pDepthStencilState->maxDepthBounds;
1084 }
1085
1086 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1087 dynamic->stencil_compare_mask.front =
1088 pCreateInfo->pDepthStencilState->front.compareMask;
1089 dynamic->stencil_compare_mask.back =
1090 pCreateInfo->pDepthStencilState->back.compareMask;
1091 }
1092
1093 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1094 dynamic->stencil_write_mask.front =
1095 pCreateInfo->pDepthStencilState->front.writeMask;
1096 dynamic->stencil_write_mask.back =
1097 pCreateInfo->pDepthStencilState->back.writeMask;
1098 }
1099
1100 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1101 dynamic->stencil_reference.front =
1102 pCreateInfo->pDepthStencilState->front.reference;
1103 dynamic->stencil_reference.back =
1104 pCreateInfo->pDepthStencilState->back.reference;
1105 }
1106 }
1107
1108 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1109 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1110 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1111 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1112 typed_memcpy(dynamic->discard_rectangle.rectangles,
1113 discard_rectangle_info->pDiscardRectangles,
1114 discard_rectangle_info->discardRectangleCount);
1115 }
1116
1117 pipeline->dynamic_state.mask = states;
1118 }
1119
1120 static struct radv_gs_state
1121 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1122 const struct radv_pipeline *pipeline)
1123 {
1124 struct radv_gs_state gs = {0};
1125 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1126 struct radv_es_output_info *es_info;
1127 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1128 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1129 else
1130 es_info = radv_pipeline_has_tess(pipeline) ?
1131 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1132 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1133
1134 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1135 bool uses_adjacency;
1136 switch(pCreateInfo->pInputAssemblyState->topology) {
1137 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1138 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1139 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1140 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1141 uses_adjacency = true;
1142 break;
1143 default:
1144 uses_adjacency = false;
1145 break;
1146 }
1147
1148 /* All these are in dwords: */
1149 /* We can't allow using the whole LDS, because GS waves compete with
1150 * other shader stages for LDS space. */
1151 const unsigned max_lds_size = 8 * 1024;
1152 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1153 unsigned esgs_lds_size;
1154
1155 /* All these are per subgroup: */
1156 const unsigned max_out_prims = 32 * 1024;
1157 const unsigned max_es_verts = 255;
1158 const unsigned ideal_gs_prims = 64;
1159 unsigned max_gs_prims, gs_prims;
1160 unsigned min_es_verts, es_verts, worst_case_es_verts;
1161
1162 if (uses_adjacency || gs_num_invocations > 1)
1163 max_gs_prims = 127 / gs_num_invocations;
1164 else
1165 max_gs_prims = 255;
1166
1167 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1168 * Make sure we don't go over the maximum value.
1169 */
1170 if (gs_info->gs.vertices_out > 0) {
1171 max_gs_prims = MIN2(max_gs_prims,
1172 max_out_prims /
1173 (gs_info->gs.vertices_out * gs_num_invocations));
1174 }
1175 assert(max_gs_prims > 0);
1176
1177 /* If the primitive has adjacency, halve the number of vertices
1178 * that will be reused in multiple primitives.
1179 */
1180 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1181
1182 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1183 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1184
1185 /* Compute ESGS LDS size based on the worst case number of ES vertices
1186 * needed to create the target number of GS prims per subgroup.
1187 */
1188 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1189
1190 /* If total LDS usage is too big, refactor partitions based on ratio
1191 * of ESGS item sizes.
1192 */
1193 if (esgs_lds_size > max_lds_size) {
1194 /* Our target GS Prims Per Subgroup was too large. Calculate
1195 * the maximum number of GS Prims Per Subgroup that will fit
1196 * into LDS, capped by the maximum that the hardware can support.
1197 */
1198 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1199 max_gs_prims);
1200 assert(gs_prims > 0);
1201 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1202 max_es_verts);
1203
1204 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1205 assert(esgs_lds_size <= max_lds_size);
1206 }
1207
1208 /* Now calculate remaining ESGS information. */
1209 if (esgs_lds_size)
1210 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1211 else
1212 es_verts = max_es_verts;
1213
1214 /* Vertices for adjacency primitives are not always reused, so restore
1215 * it for ES_VERTS_PER_SUBGRP.
1216 */
1217 min_es_verts = gs_info->gs.vertices_in;
1218
1219 /* For normal primitives, the VGT only checks if they are past the ES
1220 * verts per subgroup after allocating a full GS primitive and if they
1221 * are, kick off a new subgroup. But if those additional ES verts are
1222 * unique (e.g. not reused) we need to make sure there is enough LDS
1223 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1224 */
1225 es_verts -= min_es_verts - 1;
1226
1227 uint32_t es_verts_per_subgroup = es_verts;
1228 uint32_t gs_prims_per_subgroup = gs_prims;
1229 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1230 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1231 gs.lds_size = align(esgs_lds_size, 128) / 128;
1232 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1233 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1234 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1235 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1236 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1237 assert(max_prims_per_subgroup <= max_out_prims);
1238
1239 return gs;
1240 }
1241
1242 static void
1243 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1244 {
1245 struct radv_device *device = pipeline->device;
1246 unsigned num_se = device->physical_device->rad_info.max_se;
1247 unsigned wave_size = 64;
1248 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1249 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1250 unsigned alignment = 256 * num_se;
1251 /* The maximum size is 63.999 MB per SE. */
1252 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1253 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1254
1255 /* Calculate the minimum size. */
1256 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1257 wave_size, alignment);
1258 /* These are recommended sizes, not minimum sizes. */
1259 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1260 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1261 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1262 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1263
1264 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1265 esgs_ring_size = align(esgs_ring_size, alignment);
1266 gsvs_ring_size = align(gsvs_ring_size, alignment);
1267
1268 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1269 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1270
1271 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1272 }
1273
1274 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1275 unsigned *lds_size)
1276 {
1277 /* SPI barrier management bug:
1278 * Make sure we have at least 4k of LDS in use to avoid the bug.
1279 * It applies to workgroup sizes of more than one wavefront.
1280 */
1281 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1282 device->physical_device->rad_info.family == CHIP_KABINI ||
1283 device->physical_device->rad_info.family == CHIP_MULLINS)
1284 *lds_size = MAX2(*lds_size, 8);
1285 }
1286
1287 struct radv_shader_variant *
1288 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1289 {
1290 if (pipeline->shaders[MESA_SHADER_VERTEX])
1291 return pipeline->shaders[MESA_SHADER_VERTEX];
1292 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1293 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1294 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1295 }
1296
1297 static struct radv_shader_variant *
1298 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1299 {
1300 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1301 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1302 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1303 }
1304
1305 static struct radv_tessellation_state
1306 calculate_tess_state(struct radv_pipeline *pipeline,
1307 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1308 {
1309 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1310 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1311 unsigned num_tcs_patch_outputs;
1312 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1313 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1314 unsigned lds_size, hardware_lds_size;
1315 unsigned num_patches;
1316 struct radv_tessellation_state tess = {0};
1317
1318 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1319 * are laid out in LDS. */
1320 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1321
1322 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1323 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1324 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1325
1326 /* Ensure that we only need one wave per SIMD so we don't need to check
1327 * resource usage. Also ensures that the number of tcs in and out
1328 * vertices per threadgroup are at most 256.
1329 */
1330 input_vertex_size = num_tcs_inputs * 16;
1331 output_vertex_size = num_tcs_outputs * 16;
1332
1333 input_patch_size = num_tcs_input_cp * input_vertex_size;
1334
1335 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1336 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1337 /* Ensure that we only need one wave per SIMD so we don't need to check
1338 * resource usage. Also ensures that the number of tcs in and out
1339 * vertices per threadgroup are at most 256.
1340 */
1341 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1342
1343 /* Make sure that the data fits in LDS. This assumes the shaders only
1344 * use LDS for the inputs and outputs.
1345 */
1346 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1347 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1348
1349 /* Make sure the output data fits in the offchip buffer */
1350 num_patches = MIN2(num_patches,
1351 (pipeline->device->tess_offchip_block_dw_size * 4) /
1352 output_patch_size);
1353
1354 /* Not necessary for correctness, but improves performance. The
1355 * specific value is taken from the proprietary driver.
1356 */
1357 num_patches = MIN2(num_patches, 40);
1358
1359 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1360 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1361 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1362 num_patches = MIN2(num_patches, one_wave);
1363 }
1364
1365 output_patch0_offset = input_patch_size * num_patches;
1366
1367 lds_size = output_patch0_offset + output_patch_size * num_patches;
1368
1369 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1370 assert(lds_size <= 65536);
1371 lds_size = align(lds_size, 512) / 512;
1372 } else {
1373 assert(lds_size <= 32768);
1374 lds_size = align(lds_size, 256) / 256;
1375 }
1376 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1377
1378 tess.lds_size = lds_size;
1379
1380 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1381 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1382 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1383 tess.num_patches = num_patches;
1384
1385 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1386 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1387
1388 switch (tes->info.tes.primitive_mode) {
1389 case GL_TRIANGLES:
1390 type = V_028B6C_TESS_TRIANGLE;
1391 break;
1392 case GL_QUADS:
1393 type = V_028B6C_TESS_QUAD;
1394 break;
1395 case GL_ISOLINES:
1396 type = V_028B6C_TESS_ISOLINE;
1397 break;
1398 }
1399
1400 switch (tes->info.tes.spacing) {
1401 case TESS_SPACING_EQUAL:
1402 partitioning = V_028B6C_PART_INTEGER;
1403 break;
1404 case TESS_SPACING_FRACTIONAL_ODD:
1405 partitioning = V_028B6C_PART_FRAC_ODD;
1406 break;
1407 case TESS_SPACING_FRACTIONAL_EVEN:
1408 partitioning = V_028B6C_PART_FRAC_EVEN;
1409 break;
1410 default:
1411 break;
1412 }
1413
1414 bool ccw = tes->info.tes.ccw;
1415 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1416 vk_find_struct_const(pCreateInfo->pTessellationState,
1417 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1418
1419 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1420 ccw = !ccw;
1421
1422 if (tes->info.tes.point_mode)
1423 topology = V_028B6C_OUTPUT_POINT;
1424 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1425 topology = V_028B6C_OUTPUT_LINE;
1426 else if (ccw)
1427 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1428 else
1429 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1430
1431 if (pipeline->device->has_distributed_tess) {
1432 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1433 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1434 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1435 else
1436 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1437 } else
1438 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1439
1440 tess.tf_param = S_028B6C_TYPE(type) |
1441 S_028B6C_PARTITIONING(partitioning) |
1442 S_028B6C_TOPOLOGY(topology) |
1443 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1444
1445 return tess;
1446 }
1447
1448 static const struct radv_prim_vertex_count prim_size_table[] = {
1449 [V_008958_DI_PT_NONE] = {0, 0},
1450 [V_008958_DI_PT_POINTLIST] = {1, 1},
1451 [V_008958_DI_PT_LINELIST] = {2, 2},
1452 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1453 [V_008958_DI_PT_TRILIST] = {3, 3},
1454 [V_008958_DI_PT_TRIFAN] = {3, 1},
1455 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1456 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1457 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1458 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1459 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1460 [V_008958_DI_PT_RECTLIST] = {3, 3},
1461 [V_008958_DI_PT_LINELOOP] = {2, 1},
1462 [V_008958_DI_PT_POLYGON] = {3, 1},
1463 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1464 };
1465
1466 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1467 {
1468 if (radv_pipeline_has_gs(pipeline))
1469 return &pipeline->gs_copy_shader->info.vs.outinfo;
1470 else if (radv_pipeline_has_tess(pipeline))
1471 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1472 else
1473 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1474 }
1475
1476 static void
1477 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1478 {
1479 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1480 int shader_count = 0;
1481
1482 if(shaders[MESA_SHADER_FRAGMENT]) {
1483 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1484 }
1485 if(shaders[MESA_SHADER_GEOMETRY]) {
1486 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1487 }
1488 if(shaders[MESA_SHADER_TESS_EVAL]) {
1489 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1490 }
1491 if(shaders[MESA_SHADER_TESS_CTRL]) {
1492 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1493 }
1494 if(shaders[MESA_SHADER_VERTEX]) {
1495 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1496 }
1497
1498 for (int i = 1; i < shader_count; ++i) {
1499 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1500 ordered_shaders[i - 1]);
1501
1502 nir_remove_dead_variables(ordered_shaders[i],
1503 nir_var_shader_out);
1504 nir_remove_dead_variables(ordered_shaders[i - 1],
1505 nir_var_shader_in);
1506
1507 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1508 ordered_shaders[i - 1]);
1509
1510 nir_compact_varyings(ordered_shaders[i],
1511 ordered_shaders[i - 1], true);
1512
1513 if (progress) {
1514 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1515 ac_lower_indirect_derefs(ordered_shaders[i],
1516 pipeline->device->physical_device->rad_info.chip_class);
1517 }
1518 radv_optimize_nir(ordered_shaders[i]);
1519
1520 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1521 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1522 pipeline->device->physical_device->rad_info.chip_class);
1523 }
1524 radv_optimize_nir(ordered_shaders[i - 1]);
1525 }
1526 }
1527 }
1528
1529
1530 static struct radv_pipeline_key
1531 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1532 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1533 const struct radv_blend_state *blend,
1534 bool has_view_index)
1535 {
1536 const VkPipelineVertexInputStateCreateInfo *input_state =
1537 pCreateInfo->pVertexInputState;
1538 struct radv_pipeline_key key;
1539 memset(&key, 0, sizeof(key));
1540
1541 key.has_multiview_view_index = has_view_index;
1542
1543 uint32_t binding_input_rate = 0;
1544 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1545 if (input_state->pVertexBindingDescriptions[i].inputRate)
1546 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1547 }
1548
1549 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1550 unsigned binding;
1551 binding = input_state->pVertexAttributeDescriptions[i].binding;
1552 if (binding_input_rate & (1u << binding))
1553 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1554 }
1555
1556 if (pCreateInfo->pTessellationState)
1557 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1558
1559
1560 if (pCreateInfo->pMultisampleState &&
1561 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1562 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1563 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1564 key.multisample = true;
1565 key.log2_num_samples = util_logbase2(num_samples);
1566 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1567 }
1568
1569 key.col_format = blend->spi_shader_col_format;
1570 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1571 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1572
1573 return key;
1574 }
1575
1576 static void
1577 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1578 const struct radv_pipeline_key *key,
1579 nir_shader **nir)
1580 {
1581 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1582
1583 if (nir[MESA_SHADER_TESS_CTRL]) {
1584 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1585 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1586 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1587 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1588
1589 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1590 }
1591
1592 if (nir[MESA_SHADER_GEOMETRY]) {
1593 if (nir[MESA_SHADER_TESS_CTRL])
1594 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1595 else
1596 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1597 }
1598
1599 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1600 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1601
1602 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1603 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1604 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1605 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1606 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1607 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1608 }
1609
1610 static void
1611 merge_tess_info(struct shader_info *tes_info,
1612 const struct shader_info *tcs_info)
1613 {
1614 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1615 *
1616 * "PointMode. Controls generation of points rather than triangles
1617 * or lines. This functionality defaults to disabled, and is
1618 * enabled if either shader stage includes the execution mode.
1619 *
1620 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1621 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1622 * and OutputVertices, it says:
1623 *
1624 * "One mode must be set in at least one of the tessellation
1625 * shader stages."
1626 *
1627 * So, the fields can be set in either the TCS or TES, but they must
1628 * agree if set in both. Our backend looks at TES, so bitwise-or in
1629 * the values from the TCS.
1630 */
1631 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1632 tes_info->tess.tcs_vertices_out == 0 ||
1633 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1634 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1635
1636 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1637 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1638 tcs_info->tess.spacing == tes_info->tess.spacing);
1639 tes_info->tess.spacing |= tcs_info->tess.spacing;
1640
1641 assert(tcs_info->tess.primitive_mode == 0 ||
1642 tes_info->tess.primitive_mode == 0 ||
1643 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1644 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1645 tes_info->tess.ccw |= tcs_info->tess.ccw;
1646 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1647 }
1648
1649 static
1650 void radv_create_shaders(struct radv_pipeline *pipeline,
1651 struct radv_device *device,
1652 struct radv_pipeline_cache *cache,
1653 struct radv_pipeline_key key,
1654 const VkPipelineShaderStageCreateInfo **pStages)
1655 {
1656 struct radv_shader_module fs_m = {0};
1657 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1658 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1659 void *codes[MESA_SHADER_STAGES] = {0};
1660 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1661 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1662 unsigned char hash[20], gs_copy_hash[20];
1663
1664 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1665 if (pStages[i]) {
1666 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1667 if (modules[i]->nir)
1668 _mesa_sha1_compute(modules[i]->nir->info.name,
1669 strlen(modules[i]->nir->info.name),
1670 modules[i]->sha1);
1671 }
1672 }
1673
1674 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1675 memcpy(gs_copy_hash, hash, 20);
1676 gs_copy_hash[0] ^= 1;
1677
1678 if (modules[MESA_SHADER_GEOMETRY]) {
1679 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1680 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1681 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1682 }
1683
1684 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1685 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1686 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1687 if (pipeline->shaders[i])
1688 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1689 }
1690 return;
1691 }
1692
1693 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1694 nir_builder fs_b;
1695 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1696 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1697 fs_m.nir = fs_b.shader;
1698 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1699 }
1700
1701 /* Determine first and last stage. */
1702 unsigned first = MESA_SHADER_STAGES;
1703 unsigned last = 0;
1704 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1705 if (!pStages[i])
1706 continue;
1707 if (first == MESA_SHADER_STAGES)
1708 first = i;
1709 last = i;
1710 }
1711
1712 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1713 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1714
1715 if (!modules[i])
1716 continue;
1717
1718 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1719 stage ? stage->pName : "main", i,
1720 stage ? stage->pSpecializationInfo : NULL);
1721 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1722
1723 /* We don't want to alter meta shaders IR directly so clone it
1724 * first.
1725 */
1726 if (nir[i]->info.name) {
1727 nir[i] = nir_shader_clone(NULL, nir[i]);
1728 }
1729
1730 if (first != last) {
1731 nir_variable_mode mask = 0;
1732
1733 if (i != first)
1734 mask = mask | nir_var_shader_in;
1735
1736 if (i != last)
1737 mask = mask | nir_var_shader_out;
1738
1739 nir_lower_io_to_scalar_early(nir[i], mask);
1740 radv_optimize_nir(nir[i]);
1741 }
1742 }
1743
1744 if (nir[MESA_SHADER_TESS_CTRL]) {
1745 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1746 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1747 }
1748
1749 radv_link_shaders(pipeline, nir);
1750
1751 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1752 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1753 nir_print_shader(nir[i], stderr);
1754 }
1755
1756 radv_fill_shader_keys(keys, &key, nir);
1757
1758 if (nir[MESA_SHADER_FRAGMENT]) {
1759 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1760 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1761 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1762 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1763 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1764 }
1765
1766 /* TODO: These are no longer used as keys we should refactor this */
1767 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1768 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1769 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1770 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1771 }
1772
1773 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1774 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1775 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1776 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1777 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1778 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1779 pipeline->layout,
1780 &key, &codes[MESA_SHADER_TESS_CTRL],
1781 &code_sizes[MESA_SHADER_TESS_CTRL]);
1782 }
1783 modules[MESA_SHADER_VERTEX] = NULL;
1784 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1785 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1786 }
1787
1788 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1789 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1790 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1791 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1792 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1793 pipeline->layout,
1794 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1795 &code_sizes[MESA_SHADER_GEOMETRY]);
1796 }
1797 modules[pre_stage] = NULL;
1798 }
1799
1800 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1801 if(modules[i] && !pipeline->shaders[i]) {
1802 if (i == MESA_SHADER_TESS_CTRL) {
1803 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
1804 }
1805 if (i == MESA_SHADER_TESS_EVAL) {
1806 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1807 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1808 }
1809 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1810 pipeline->layout,
1811 keys + i, &codes[i],
1812 &code_sizes[i]);
1813 }
1814 }
1815
1816 if(modules[MESA_SHADER_GEOMETRY]) {
1817 void *gs_copy_code = NULL;
1818 unsigned gs_copy_code_size = 0;
1819 if (!pipeline->gs_copy_shader) {
1820 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1821 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1822 &gs_copy_code_size,
1823 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1824 }
1825
1826 if (pipeline->gs_copy_shader) {
1827 void *code[MESA_SHADER_STAGES] = {0};
1828 unsigned code_size[MESA_SHADER_STAGES] = {0};
1829 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1830
1831 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1832 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1833 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1834
1835 radv_pipeline_cache_insert_shaders(device, cache,
1836 gs_copy_hash,
1837 variants,
1838 (const void**)code,
1839 code_size);
1840 }
1841 free(gs_copy_code);
1842 }
1843
1844 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1845 (const void**)codes, code_sizes);
1846
1847 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1848 free(codes[i]);
1849 if (modules[i]) {
1850 if (!pipeline->device->keep_shader_info)
1851 ralloc_free(nir[i]);
1852
1853 if (radv_can_dump_shader_stats(device, modules[i]))
1854 radv_shader_dump_stats(device,
1855 pipeline->shaders[i],
1856 i, stderr);
1857 }
1858 }
1859
1860 if (fs_m.nir)
1861 ralloc_free(fs_m.nir);
1862 }
1863
1864 static uint32_t
1865 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1866 gl_shader_stage stage, enum chip_class chip_class)
1867 {
1868 bool has_gs = radv_pipeline_has_gs(pipeline);
1869 bool has_tess = radv_pipeline_has_tess(pipeline);
1870 switch (stage) {
1871 case MESA_SHADER_FRAGMENT:
1872 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1873 case MESA_SHADER_VERTEX:
1874 if (chip_class >= GFX9) {
1875 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1876 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1877 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1878 }
1879 if (has_tess)
1880 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1881 else
1882 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1883 case MESA_SHADER_GEOMETRY:
1884 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1885 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1886 case MESA_SHADER_COMPUTE:
1887 return R_00B900_COMPUTE_USER_DATA_0;
1888 case MESA_SHADER_TESS_CTRL:
1889 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1890 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1891 case MESA_SHADER_TESS_EVAL:
1892 if (chip_class >= GFX9) {
1893 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1894 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1895 }
1896 if (has_gs)
1897 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1898 else
1899 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1900 default:
1901 unreachable("unknown shader");
1902 }
1903 }
1904
1905 struct radv_bin_size_entry {
1906 unsigned bpp;
1907 VkExtent2D extent;
1908 };
1909
1910 static VkExtent2D
1911 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1912 {
1913 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1914 {
1915 /* One RB / SE */
1916 {
1917 /* One shader engine */
1918 { 0, {128, 128}},
1919 { 1, { 64, 128}},
1920 { 2, { 32, 128}},
1921 { 3, { 16, 128}},
1922 { 17, { 0, 0}},
1923 { UINT_MAX, { 0, 0}},
1924 },
1925 {
1926 /* Two shader engines */
1927 { 0, {128, 128}},
1928 { 2, { 64, 128}},
1929 { 3, { 32, 128}},
1930 { 5, { 16, 128}},
1931 { 17, { 0, 0}},
1932 { UINT_MAX, { 0, 0}},
1933 },
1934 {
1935 /* Four shader engines */
1936 { 0, {128, 128}},
1937 { 3, { 64, 128}},
1938 { 5, { 16, 128}},
1939 { 17, { 0, 0}},
1940 { UINT_MAX, { 0, 0}},
1941 },
1942 },
1943 {
1944 /* Two RB / SE */
1945 {
1946 /* One shader engine */
1947 { 0, {128, 128}},
1948 { 2, { 64, 128}},
1949 { 3, { 32, 128}},
1950 { 5, { 16, 128}},
1951 { 33, { 0, 0}},
1952 { UINT_MAX, { 0, 0}},
1953 },
1954 {
1955 /* Two shader engines */
1956 { 0, {128, 128}},
1957 { 3, { 64, 128}},
1958 { 5, { 32, 128}},
1959 { 9, { 16, 128}},
1960 { 33, { 0, 0}},
1961 { UINT_MAX, { 0, 0}},
1962 },
1963 {
1964 /* Four shader engines */
1965 { 0, {256, 256}},
1966 { 2, {128, 256}},
1967 { 3, {128, 128}},
1968 { 5, { 64, 128}},
1969 { 9, { 16, 128}},
1970 { 33, { 0, 0}},
1971 { UINT_MAX, { 0, 0}},
1972 },
1973 },
1974 {
1975 /* Four RB / SE */
1976 {
1977 /* One shader engine */
1978 { 0, {128, 256}},
1979 { 2, {128, 128}},
1980 { 3, { 64, 128}},
1981 { 5, { 32, 128}},
1982 { 9, { 16, 128}},
1983 { 33, { 0, 0}},
1984 { UINT_MAX, { 0, 0}},
1985 },
1986 {
1987 /* Two shader engines */
1988 { 0, {256, 256}},
1989 { 2, {128, 256}},
1990 { 3, {128, 128}},
1991 { 5, { 64, 128}},
1992 { 9, { 32, 128}},
1993 { 17, { 16, 128}},
1994 { 33, { 0, 0}},
1995 { UINT_MAX, { 0, 0}},
1996 },
1997 {
1998 /* Four shader engines */
1999 { 0, {256, 512}},
2000 { 2, {256, 256}},
2001 { 3, {128, 256}},
2002 { 5, {128, 128}},
2003 { 9, { 64, 128}},
2004 { 17, { 16, 128}},
2005 { 33, { 0, 0}},
2006 { UINT_MAX, { 0, 0}},
2007 },
2008 },
2009 };
2010 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2011 {
2012 // One RB / SE
2013 {
2014 // One shader engine
2015 { 0, {128, 256}},
2016 { 2, {128, 128}},
2017 { 4, { 64, 128}},
2018 { 7, { 32, 128}},
2019 { 13, { 16, 128}},
2020 { 49, { 0, 0}},
2021 { UINT_MAX, { 0, 0}},
2022 },
2023 {
2024 // Two shader engines
2025 { 0, {256, 256}},
2026 { 2, {128, 256}},
2027 { 4, {128, 128}},
2028 { 7, { 64, 128}},
2029 { 13, { 32, 128}},
2030 { 25, { 16, 128}},
2031 { 49, { 0, 0}},
2032 { UINT_MAX, { 0, 0}},
2033 },
2034 {
2035 // Four shader engines
2036 { 0, {256, 512}},
2037 { 2, {256, 256}},
2038 { 4, {128, 256}},
2039 { 7, {128, 128}},
2040 { 13, { 64, 128}},
2041 { 25, { 16, 128}},
2042 { 49, { 0, 0}},
2043 { UINT_MAX, { 0, 0}},
2044 },
2045 },
2046 {
2047 // Two RB / SE
2048 {
2049 // One shader engine
2050 { 0, {256, 256}},
2051 { 2, {128, 256}},
2052 { 4, {128, 128}},
2053 { 7, { 64, 128}},
2054 { 13, { 32, 128}},
2055 { 25, { 16, 128}},
2056 { 97, { 0, 0}},
2057 { UINT_MAX, { 0, 0}},
2058 },
2059 {
2060 // Two shader engines
2061 { 0, {256, 512}},
2062 { 2, {256, 256}},
2063 { 4, {128, 256}},
2064 { 7, {128, 128}},
2065 { 13, { 64, 128}},
2066 { 25, { 32, 128}},
2067 { 49, { 16, 128}},
2068 { 97, { 0, 0}},
2069 { UINT_MAX, { 0, 0}},
2070 },
2071 {
2072 // Four shader engines
2073 { 0, {512, 512}},
2074 { 2, {256, 512}},
2075 { 4, {256, 256}},
2076 { 7, {128, 256}},
2077 { 13, {128, 128}},
2078 { 25, { 64, 128}},
2079 { 49, { 16, 128}},
2080 { 97, { 0, 0}},
2081 { UINT_MAX, { 0, 0}},
2082 },
2083 },
2084 {
2085 // Four RB / SE
2086 {
2087 // One shader engine
2088 { 0, {256, 512}},
2089 { 2, {256, 256}},
2090 { 4, {128, 256}},
2091 { 7, {128, 128}},
2092 { 13, { 64, 128}},
2093 { 25, { 32, 128}},
2094 { 49, { 16, 128}},
2095 { UINT_MAX, { 0, 0}},
2096 },
2097 {
2098 // Two shader engines
2099 { 0, {512, 512}},
2100 { 2, {256, 512}},
2101 { 4, {256, 256}},
2102 { 7, {128, 256}},
2103 { 13, {128, 128}},
2104 { 25, { 64, 128}},
2105 { 49, { 32, 128}},
2106 { 97, { 16, 128}},
2107 { UINT_MAX, { 0, 0}},
2108 },
2109 {
2110 // Four shader engines
2111 { 0, {512, 512}},
2112 { 4, {256, 512}},
2113 { 7, {256, 256}},
2114 { 13, {128, 256}},
2115 { 25, {128, 128}},
2116 { 49, { 64, 128}},
2117 { 97, { 16, 128}},
2118 { UINT_MAX, { 0, 0}},
2119 },
2120 },
2121 };
2122
2123 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2124 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2125 VkExtent2D extent = {512, 512};
2126
2127 unsigned log_num_rb_per_se =
2128 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2129 pipeline->device->physical_device->rad_info.max_se);
2130 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2131
2132 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2133 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2134 unsigned effective_samples = total_samples;
2135 unsigned color_bytes_per_pixel = 0;
2136
2137 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2138 if (vkblend) {
2139 for (unsigned i = 0; i < subpass->color_count; i++) {
2140 if (!vkblend->pAttachments[i].colorWriteMask)
2141 continue;
2142
2143 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2144 continue;
2145
2146 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2147 color_bytes_per_pixel += vk_format_get_blocksize(format);
2148 }
2149
2150 /* MSAA images typically don't use all samples all the time. */
2151 if (effective_samples >= 2 && ps_iter_samples <= 1)
2152 effective_samples = 2;
2153 color_bytes_per_pixel *= effective_samples;
2154 }
2155
2156 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2157 while(color_entry->bpp <= color_bytes_per_pixel)
2158 ++color_entry;
2159
2160 extent = color_entry->extent;
2161
2162 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2163 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2164
2165 /* Coefficients taken from AMDVLK */
2166 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2167 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2168 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2169
2170 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2171 while(ds_entry->bpp <= ds_bytes_per_pixel)
2172 ++ds_entry;
2173
2174 extent.width = MIN2(extent.width, ds_entry->extent.width);
2175 extent.height = MIN2(extent.height, ds_entry->extent.height);
2176 }
2177
2178 return extent;
2179 }
2180
2181 static void
2182 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2183 struct radv_pipeline *pipeline,
2184 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2185 {
2186 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2187 return;
2188
2189 uint32_t pa_sc_binner_cntl_0 =
2190 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2191 S_028C44_DISABLE_START_OF_PRIM(1);
2192 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2193
2194 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2195
2196 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2197 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2198 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2199
2200 switch (pipeline->device->physical_device->rad_info.family) {
2201 case CHIP_VEGA10:
2202 context_states_per_bin = 1;
2203 persistent_states_per_bin = 1;
2204 fpovs_per_batch = 63;
2205 break;
2206 case CHIP_RAVEN:
2207 context_states_per_bin = 6;
2208 persistent_states_per_bin = 32;
2209 fpovs_per_batch = 63;
2210 break;
2211 default:
2212 unreachable("unhandled family while determining binning state.");
2213 }
2214
2215 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2216 pa_sc_binner_cntl_0 =
2217 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2218 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2219 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2220 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2221 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2222 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2223 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2224 S_028C44_DISABLE_START_OF_PRIM(1) |
2225 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2226 S_028C44_OPTIMAL_BIN_SELECTION(1);
2227 }
2228
2229 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2230 pa_sc_binner_cntl_0);
2231 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2232 db_dfsm_control);
2233 }
2234
2235
2236 static void
2237 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2238 struct radv_pipeline *pipeline,
2239 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2240 const struct radv_graphics_pipeline_create_info *extra)
2241 {
2242 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2243 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2244 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2245 struct radv_render_pass_attachment *attachment = NULL;
2246 uint32_t db_depth_control = 0, db_stencil_control = 0;
2247 uint32_t db_render_control = 0, db_render_override2 = 0;
2248
2249 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2250 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2251
2252 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2253 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2254
2255 if (vkds && has_depth_attachment) {
2256 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2257 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2258 S_028800_ZFUNC(vkds->depthCompareOp) |
2259 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2260
2261 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2262 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2263 }
2264
2265 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2266 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2267 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2268 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2269 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2270 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2271
2272 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2273 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2274 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2275 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2276 }
2277
2278 if (attachment && extra) {
2279 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2280 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2281
2282 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2283 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2284 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2285 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2286 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2287 }
2288
2289 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2290 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2291
2292 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2293 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2294 }
2295
2296 static void
2297 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2298 struct radv_pipeline *pipeline,
2299 const struct radv_blend_state *blend)
2300 {
2301 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2302 radeon_emit_array(cs, blend->cb_blend_control,
2303 8);
2304 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2305 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2306
2307 if (pipeline->device->physical_device->has_rbplus) {
2308
2309 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2310 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2311
2312 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2313 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2314 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2315 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2316 }
2317
2318 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2319
2320 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2321 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2322 }
2323
2324
2325 static void
2326 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2327 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2328 {
2329 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2330
2331 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2332 S_028810_PS_UCP_MODE(3) |
2333 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2334 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2335 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2336 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2337 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2338
2339 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2340 S_0286D4_FLAT_SHADE_ENA(1) |
2341 S_0286D4_PNT_SPRITE_ENA(1) |
2342 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2343 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2344 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2345 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2346 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2347
2348 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2349 S_028BE4_PIX_CENTER(1) | // TODO verify
2350 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2351 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2352
2353 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2354 S_028814_FACE(vkraster->frontFace) |
2355 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2356 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2357 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2358 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2359 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2360 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2361 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2362 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2363 }
2364
2365
2366 static void
2367 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2368 struct radv_pipeline *pipeline)
2369 {
2370 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2371
2372 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2373 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2374 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2375
2376 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2377 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2378
2379 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2380 uint32_t offset;
2381 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2382 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2383 if (loc->sgpr_idx == -1)
2384 return;
2385 assert(loc->num_sgprs == 1);
2386 assert(!loc->indirect);
2387 switch (pipeline->graphics.ms.num_samples) {
2388 default:
2389 offset = 0;
2390 break;
2391 case 2:
2392 offset = 1;
2393 break;
2394 case 4:
2395 offset = 3;
2396 break;
2397 case 8:
2398 offset = 7;
2399 break;
2400 case 16:
2401 offset = 15;
2402 break;
2403 }
2404
2405 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2406 }
2407 }
2408
2409 static void
2410 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2411 const struct radv_pipeline *pipeline)
2412 {
2413 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2414
2415 uint32_t vgt_primitiveid_en = false;
2416 uint32_t vgt_gs_mode = 0;
2417
2418 if (radv_pipeline_has_gs(pipeline)) {
2419 const struct radv_shader_variant *gs =
2420 pipeline->shaders[MESA_SHADER_GEOMETRY];
2421
2422 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2423 pipeline->device->physical_device->rad_info.chip_class);
2424 } else if (outinfo->export_prim_id) {
2425 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2426 vgt_primitiveid_en = true;
2427 }
2428
2429 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2430 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2431 }
2432
2433 static void
2434 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2435 struct radv_pipeline *pipeline,
2436 struct radv_shader_variant *shader)
2437 {
2438 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2439
2440 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2441 radeon_emit(cs, va >> 8);
2442 radeon_emit(cs, va >> 40);
2443 radeon_emit(cs, shader->rsrc1);
2444 radeon_emit(cs, shader->rsrc2);
2445
2446 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2447 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2448 clip_dist_mask = outinfo->clip_dist_mask;
2449 cull_dist_mask = outinfo->cull_dist_mask;
2450 total_mask = clip_dist_mask | cull_dist_mask;
2451 bool misc_vec_ena = outinfo->writes_pointsize ||
2452 outinfo->writes_layer ||
2453 outinfo->writes_viewport_index;
2454
2455 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2456 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2457
2458 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2459 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2460 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2461 V_02870C_SPI_SHADER_4COMP :
2462 V_02870C_SPI_SHADER_NONE) |
2463 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2464 V_02870C_SPI_SHADER_4COMP :
2465 V_02870C_SPI_SHADER_NONE) |
2466 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2467 V_02870C_SPI_SHADER_4COMP :
2468 V_02870C_SPI_SHADER_NONE));
2469
2470 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2471 S_028818_VTX_W0_FMT(1) |
2472 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2473 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2474 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2475
2476 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2477 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2478 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2479 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2480 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2481 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2482 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2483 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2484 cull_dist_mask << 8 |
2485 clip_dist_mask);
2486
2487 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2488 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2489 outinfo->writes_viewport_index);
2490 }
2491
2492 static void
2493 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2494 struct radv_pipeline *pipeline,
2495 struct radv_shader_variant *shader)
2496 {
2497 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2498
2499 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2500 radeon_emit(cs, va >> 8);
2501 radeon_emit(cs, va >> 40);
2502 radeon_emit(cs, shader->rsrc1);
2503 radeon_emit(cs, shader->rsrc2);
2504 }
2505
2506 static void
2507 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2508 struct radv_pipeline *pipeline,
2509 struct radv_shader_variant *shader,
2510 const struct radv_tessellation_state *tess)
2511 {
2512 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2513 uint32_t rsrc2 = shader->rsrc2;
2514
2515 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2516 radeon_emit(cs, va >> 8);
2517 radeon_emit(cs, va >> 40);
2518
2519 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2520 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2521 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2522 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2523
2524 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2525 radeon_emit(cs, shader->rsrc1);
2526 radeon_emit(cs, rsrc2);
2527 }
2528
2529 static void
2530 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2531 struct radv_pipeline *pipeline,
2532 struct radv_shader_variant *shader,
2533 const struct radv_tessellation_state *tess)
2534 {
2535 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2536
2537 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2538 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2539 radeon_emit(cs, va >> 8);
2540 radeon_emit(cs, va >> 40);
2541
2542 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2543 radeon_emit(cs, shader->rsrc1);
2544 radeon_emit(cs, shader->rsrc2 |
2545 S_00B42C_LDS_SIZE(tess->lds_size));
2546 } else {
2547 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2548 radeon_emit(cs, va >> 8);
2549 radeon_emit(cs, va >> 40);
2550 radeon_emit(cs, shader->rsrc1);
2551 radeon_emit(cs, shader->rsrc2);
2552 }
2553 }
2554
2555 static void
2556 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2557 struct radv_pipeline *pipeline,
2558 const struct radv_tessellation_state *tess)
2559 {
2560 struct radv_shader_variant *vs;
2561
2562 /* Skip shaders merged into HS/GS */
2563 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2564 if (!vs)
2565 return;
2566
2567 if (vs->info.vs.as_ls)
2568 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2569 else if (vs->info.vs.as_es)
2570 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2571 else
2572 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2573 }
2574
2575 static void
2576 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2577 struct radv_pipeline *pipeline,
2578 const struct radv_tessellation_state *tess)
2579 {
2580 if (!radv_pipeline_has_tess(pipeline))
2581 return;
2582
2583 struct radv_shader_variant *tes, *tcs;
2584
2585 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2586 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2587
2588 if (tes) {
2589 if (tes->info.tes.as_es)
2590 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2591 else
2592 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2593 }
2594
2595 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2596
2597 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2598 tess->tf_param);
2599
2600 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2601 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2602 tess->ls_hs_config);
2603 else
2604 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2605 tess->ls_hs_config);
2606 }
2607
2608 static void
2609 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2610 struct radv_pipeline *pipeline,
2611 const struct radv_gs_state *gs_state)
2612 {
2613 struct radv_shader_variant *gs;
2614 uint64_t va;
2615
2616 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2617 if (!gs)
2618 return;
2619
2620 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2621
2622 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2623 radeon_emit(cs, gsvs_itemsize);
2624 radeon_emit(cs, gsvs_itemsize);
2625 radeon_emit(cs, gsvs_itemsize);
2626
2627 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2628
2629 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2630
2631 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2632 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2633 radeon_emit(cs, gs_vert_itemsize >> 2);
2634 radeon_emit(cs, 0);
2635 radeon_emit(cs, 0);
2636 radeon_emit(cs, 0);
2637
2638 uint32_t gs_num_invocations = gs->info.gs.invocations;
2639 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2640 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2641 S_028B90_ENABLE(gs_num_invocations > 0));
2642
2643 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2644 gs_state->vgt_esgs_ring_itemsize);
2645
2646 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2647
2648 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2649 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2650 radeon_emit(cs, va >> 8);
2651 radeon_emit(cs, va >> 40);
2652
2653 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2654 radeon_emit(cs, gs->rsrc1);
2655 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2656
2657 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2658 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2659 } else {
2660 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2661 radeon_emit(cs, va >> 8);
2662 radeon_emit(cs, va >> 40);
2663 radeon_emit(cs, gs->rsrc1);
2664 radeon_emit(cs, gs->rsrc2);
2665 }
2666
2667 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2668
2669 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2670 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
2671 if (loc->sgpr_idx != -1) {
2672 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
2673 uint32_t num_entries = 64;
2674 bool is_vi = pipeline->device->physical_device->rad_info.chip_class >= VI;
2675
2676 if (is_vi)
2677 num_entries *= stride;
2678
2679 stride = S_008F04_STRIDE(stride);
2680 radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
2681 radeon_emit(cs, stride);
2682 radeon_emit(cs, num_entries);
2683 }
2684 }
2685
2686 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2687 {
2688 uint32_t ps_input_cntl;
2689 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2690 ps_input_cntl = S_028644_OFFSET(offset);
2691 if (flat_shade)
2692 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2693 } else {
2694 /* The input is a DEFAULT_VAL constant. */
2695 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2696 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2697 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2698 ps_input_cntl = S_028644_OFFSET(0x20) |
2699 S_028644_DEFAULT_VAL(offset);
2700 }
2701 return ps_input_cntl;
2702 }
2703
2704 static void
2705 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2706 struct radv_pipeline *pipeline)
2707 {
2708 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2709 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2710 uint32_t ps_input_cntl[32];
2711
2712 unsigned ps_offset = 0;
2713
2714 if (ps->info.info.ps.prim_id_input) {
2715 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2716 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2717 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2718 ++ps_offset;
2719 }
2720 }
2721
2722 if (ps->info.info.ps.layer_input ||
2723 ps->info.info.ps.uses_input_attachments ||
2724 ps->info.info.needs_multiview_view_index) {
2725 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2726 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2727 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2728 else
2729 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2730 ++ps_offset;
2731 }
2732
2733 if (ps->info.info.ps.has_pcoord) {
2734 unsigned val;
2735 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2736 ps_input_cntl[ps_offset] = val;
2737 ps_offset++;
2738 }
2739
2740 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2741 unsigned vs_offset;
2742 bool flat_shade;
2743 if (!(ps->info.fs.input_mask & (1u << i)))
2744 continue;
2745
2746 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2747 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2748 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2749 ++ps_offset;
2750 continue;
2751 }
2752
2753 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2754
2755 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2756 ++ps_offset;
2757 }
2758
2759 if (ps_offset) {
2760 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2761 for (unsigned i = 0; i < ps_offset; i++) {
2762 radeon_emit(cs, ps_input_cntl[i]);
2763 }
2764 }
2765 }
2766
2767 static uint32_t
2768 radv_compute_db_shader_control(const struct radv_device *device,
2769 const struct radv_shader_variant *ps)
2770 {
2771 unsigned z_order;
2772 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2773 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2774 else
2775 z_order = V_02880C_LATE_Z;
2776
2777 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
2778 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
2779 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2780 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
2781 S_02880C_Z_ORDER(z_order) |
2782 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2783 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2784 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
2785 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
2786 }
2787
2788 static void
2789 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2790 struct radv_pipeline *pipeline)
2791 {
2792 struct radv_shader_variant *ps;
2793 uint64_t va;
2794 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2795
2796 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2797 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2798
2799 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2800 radeon_emit(cs, va >> 8);
2801 radeon_emit(cs, va >> 40);
2802 radeon_emit(cs, ps->rsrc1);
2803 radeon_emit(cs, ps->rsrc2);
2804
2805 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2806 radv_compute_db_shader_control(pipeline->device, ps));
2807
2808 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2809 ps->config.spi_ps_input_ena);
2810
2811 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2812 ps->config.spi_ps_input_addr);
2813
2814 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2815 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2816
2817 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2818
2819 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2820 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
2821 ps->info.info.ps.writes_stencil,
2822 ps->info.info.ps.writes_sample_mask));
2823
2824 if (pipeline->device->dfsm_allowed) {
2825 /* optimise this? */
2826 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2827 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2828 }
2829 }
2830
2831 static void
2832 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2833 struct radv_pipeline *pipeline)
2834 {
2835 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2836 return;
2837
2838 unsigned vtx_reuse_depth = 30;
2839 if (radv_pipeline_has_tess(pipeline) &&
2840 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2841 vtx_reuse_depth = 14;
2842 }
2843 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2844 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2845 }
2846
2847 static uint32_t
2848 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
2849 {
2850 uint32_t stages = 0;
2851 if (radv_pipeline_has_tess(pipeline)) {
2852 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2853 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2854
2855 if (radv_pipeline_has_gs(pipeline))
2856 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2857 S_028B54_GS_EN(1) |
2858 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2859 else
2860 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2861
2862 } else if (radv_pipeline_has_gs(pipeline))
2863 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2864 S_028B54_GS_EN(1) |
2865 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2866
2867 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
2868 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2869
2870 return stages;
2871 }
2872
2873 static uint32_t
2874 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
2875 {
2876 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
2877 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
2878
2879 if (!discard_rectangle_info)
2880 return 0xffff;
2881
2882 unsigned mask = 0;
2883
2884 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
2885 /* Interpret i as a bitmask, and then set the bit in the mask if
2886 * that combination of rectangles in which the pixel is contained
2887 * should pass the cliprect test. */
2888 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
2889
2890 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
2891 !relevant_subset)
2892 continue;
2893
2894 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
2895 relevant_subset)
2896 continue;
2897
2898 mask |= 1u << i;
2899 }
2900
2901 return mask;
2902 }
2903
2904 static void
2905 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2906 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2907 const struct radv_graphics_pipeline_create_info *extra,
2908 const struct radv_blend_state *blend,
2909 const struct radv_tessellation_state *tess,
2910 const struct radv_gs_state *gs,
2911 unsigned prim, unsigned gs_out)
2912 {
2913 pipeline->cs.buf = malloc(4 * 256);
2914 pipeline->cs.max_dw = 256;
2915
2916 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2917 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
2918 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
2919 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2920 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
2921 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
2922 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
2923 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
2924 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2925 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2926 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2927 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2928
2929 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2930 S_0286E8_WAVES(pipeline->max_waves) |
2931 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2932
2933 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
2934
2935 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2936 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
2937 } else {
2938 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
2939 }
2940 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
2941
2942 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
2943
2944 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2945 }
2946
2947 static struct radv_ia_multi_vgt_param_helpers
2948 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
2949 const struct radv_tessellation_state *tess,
2950 uint32_t prim)
2951 {
2952 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
2953 const struct radv_device *device = pipeline->device;
2954
2955 if (radv_pipeline_has_tess(pipeline))
2956 ia_multi_vgt_param.primgroup_size = tess->num_patches;
2957 else if (radv_pipeline_has_gs(pipeline))
2958 ia_multi_vgt_param.primgroup_size = 64;
2959 else
2960 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
2961
2962 ia_multi_vgt_param.partial_es_wave = false;
2963 if (pipeline->device->has_distributed_tess) {
2964 if (radv_pipeline_has_gs(pipeline)) {
2965 if (device->physical_device->rad_info.chip_class <= VI)
2966 ia_multi_vgt_param.partial_es_wave = true;
2967 }
2968 }
2969 /* GS requirement. */
2970 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
2971 ia_multi_vgt_param.partial_es_wave = true;
2972
2973 ia_multi_vgt_param.wd_switch_on_eop = false;
2974 if (device->physical_device->rad_info.chip_class >= CIK) {
2975 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2976 * 4 shader engines. Set 1 to pass the assertion below.
2977 * The other cases are hardware requirements. */
2978 if (device->physical_device->rad_info.max_se < 4 ||
2979 prim == V_008958_DI_PT_POLYGON ||
2980 prim == V_008958_DI_PT_LINELOOP ||
2981 prim == V_008958_DI_PT_TRIFAN ||
2982 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
2983 (pipeline->graphics.prim_restart_enable &&
2984 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
2985 (prim != V_008958_DI_PT_POINTLIST &&
2986 prim != V_008958_DI_PT_LINESTRIP &&
2987 prim != V_008958_DI_PT_TRISTRIP))))
2988 ia_multi_vgt_param.wd_switch_on_eop = true;
2989 }
2990
2991 ia_multi_vgt_param.ia_switch_on_eoi = false;
2992 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
2993 ia_multi_vgt_param.ia_switch_on_eoi = true;
2994 if (radv_pipeline_has_gs(pipeline) &&
2995 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
2996 ia_multi_vgt_param.ia_switch_on_eoi = true;
2997 if (radv_pipeline_has_tess(pipeline)) {
2998 /* SWITCH_ON_EOI must be set if PrimID is used. */
2999 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3000 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3001 ia_multi_vgt_param.ia_switch_on_eoi = true;
3002 }
3003
3004 ia_multi_vgt_param.partial_vs_wave = false;
3005 if (radv_pipeline_has_tess(pipeline)) {
3006 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3007 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3008 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3009 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3010 radv_pipeline_has_gs(pipeline))
3011 ia_multi_vgt_param.partial_vs_wave = true;
3012 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3013 if (device->has_distributed_tess) {
3014 if (radv_pipeline_has_gs(pipeline)) {
3015 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3016 device->physical_device->rad_info.family == CHIP_FIJI ||
3017 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3018 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3019 device->physical_device->rad_info.family == CHIP_POLARIS12)
3020 ia_multi_vgt_param.partial_vs_wave = true;
3021 } else {
3022 ia_multi_vgt_param.partial_vs_wave = true;
3023 }
3024 }
3025 }
3026
3027 ia_multi_vgt_param.base =
3028 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3029 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3030 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3031 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3032 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3033
3034 return ia_multi_vgt_param;
3035 }
3036
3037
3038 static void
3039 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3040 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3041 {
3042 const VkPipelineVertexInputStateCreateInfo *vi_info =
3043 pCreateInfo->pVertexInputState;
3044 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3045
3046 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3047 const VkVertexInputAttributeDescription *desc =
3048 &vi_info->pVertexAttributeDescriptions[i];
3049 unsigned loc = desc->location;
3050 const struct vk_format_description *format_desc;
3051 int first_non_void;
3052 uint32_t num_format, data_format;
3053 format_desc = vk_format_description(desc->format);
3054 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3055
3056 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3057 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3058
3059 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3060 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3061 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3062 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3063 S_008F0C_NUM_FORMAT(num_format) |
3064 S_008F0C_DATA_FORMAT(data_format);
3065 velems->format_size[loc] = format_desc->block.bits / 8;
3066 velems->offset[loc] = desc->offset;
3067 velems->binding[loc] = desc->binding;
3068 velems->count = MAX2(velems->count, loc + 1);
3069 }
3070
3071 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3072 const VkVertexInputBindingDescription *desc =
3073 &vi_info->pVertexBindingDescriptions[i];
3074
3075 pipeline->binding_stride[desc->binding] = desc->stride;
3076 }
3077 }
3078
3079 static VkResult
3080 radv_pipeline_init(struct radv_pipeline *pipeline,
3081 struct radv_device *device,
3082 struct radv_pipeline_cache *cache,
3083 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3084 const struct radv_graphics_pipeline_create_info *extra,
3085 const VkAllocationCallbacks *alloc)
3086 {
3087 VkResult result;
3088 bool has_view_index = false;
3089
3090 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3091 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3092 if (subpass->view_mask)
3093 has_view_index = true;
3094 if (alloc == NULL)
3095 alloc = &device->alloc;
3096
3097 pipeline->device = device;
3098 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3099 assert(pipeline->layout);
3100
3101 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3102
3103 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3104 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3105 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3106 pStages[stage] = &pCreateInfo->pStages[i];
3107 }
3108
3109 radv_create_shaders(pipeline, device, cache,
3110 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3111 pStages);
3112
3113 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3114 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
3115 uint32_t gs_out;
3116 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3117
3118 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3119
3120 if (radv_pipeline_has_gs(pipeline)) {
3121 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3122 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3123 } else {
3124 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3125 }
3126 if (extra && extra->use_rectlist) {
3127 prim = V_008958_DI_PT_RECTLIST;
3128 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3129 pipeline->graphics.can_use_guardband = true;
3130 }
3131 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3132 /* prim vertex count will need TESS changes */
3133 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3134
3135 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3136
3137 /* Ensure that some export memory is always allocated, for two reasons:
3138 *
3139 * 1) Correctness: The hardware ignores the EXEC mask if no export
3140 * memory is allocated, so KILL and alpha test do not work correctly
3141 * without this.
3142 * 2) Performance: Every shader needs at least a NULL export, even when
3143 * it writes no color/depth output. The NULL export instruction
3144 * stalls without this setting.
3145 *
3146 * Don't add this to CB_SHADER_MASK.
3147 */
3148 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3149 if (!blend.spi_shader_col_format) {
3150 if (!ps->info.info.ps.writes_z &&
3151 !ps->info.info.ps.writes_stencil &&
3152 !ps->info.info.ps.writes_sample_mask)
3153 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3154 }
3155
3156 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3157 if (pipeline->shaders[i]) {
3158 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3159 }
3160 }
3161
3162 struct radv_gs_state gs = {0};
3163 if (radv_pipeline_has_gs(pipeline)) {
3164 gs = calculate_gs_info(pCreateInfo, pipeline);
3165 calculate_gs_ring_sizes(pipeline, &gs);
3166 }
3167
3168 struct radv_tessellation_state tess = {0};
3169 if (radv_pipeline_has_tess(pipeline)) {
3170 if (prim == V_008958_DI_PT_PATCH) {
3171 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3172 pipeline->graphics.prim_vertex_count.incr = 1;
3173 }
3174 tess = calculate_tess_state(pipeline, pCreateInfo);
3175 }
3176
3177 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3178
3179 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3180
3181 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3182 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3183
3184 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3185 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3186 if (loc->sgpr_idx != -1) {
3187 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3188 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3189 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3190 pipeline->graphics.vtx_emit_num = 3;
3191 else
3192 pipeline->graphics.vtx_emit_num = 2;
3193 }
3194
3195 result = radv_pipeline_scratch_init(device, pipeline);
3196 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3197
3198 return result;
3199 }
3200
3201 VkResult
3202 radv_graphics_pipeline_create(
3203 VkDevice _device,
3204 VkPipelineCache _cache,
3205 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3206 const struct radv_graphics_pipeline_create_info *extra,
3207 const VkAllocationCallbacks *pAllocator,
3208 VkPipeline *pPipeline)
3209 {
3210 RADV_FROM_HANDLE(radv_device, device, _device);
3211 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3212 struct radv_pipeline *pipeline;
3213 VkResult result;
3214
3215 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3216 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3217 if (pipeline == NULL)
3218 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3219
3220 result = radv_pipeline_init(pipeline, device, cache,
3221 pCreateInfo, extra, pAllocator);
3222 if (result != VK_SUCCESS) {
3223 radv_pipeline_destroy(device, pipeline, pAllocator);
3224 return result;
3225 }
3226
3227 *pPipeline = radv_pipeline_to_handle(pipeline);
3228
3229 return VK_SUCCESS;
3230 }
3231
3232 VkResult radv_CreateGraphicsPipelines(
3233 VkDevice _device,
3234 VkPipelineCache pipelineCache,
3235 uint32_t count,
3236 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3237 const VkAllocationCallbacks* pAllocator,
3238 VkPipeline* pPipelines)
3239 {
3240 VkResult result = VK_SUCCESS;
3241 unsigned i = 0;
3242
3243 for (; i < count; i++) {
3244 VkResult r;
3245 r = radv_graphics_pipeline_create(_device,
3246 pipelineCache,
3247 &pCreateInfos[i],
3248 NULL, pAllocator, &pPipelines[i]);
3249 if (r != VK_SUCCESS) {
3250 result = r;
3251 pPipelines[i] = VK_NULL_HANDLE;
3252 }
3253 }
3254
3255 return result;
3256 }
3257
3258
3259 static void
3260 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3261 {
3262 struct radv_shader_variant *compute_shader;
3263 struct radv_device *device = pipeline->device;
3264 unsigned compute_resource_limits;
3265 unsigned waves_per_threadgroup;
3266 uint64_t va;
3267
3268 pipeline->cs.buf = malloc(20 * 4);
3269 pipeline->cs.max_dw = 20;
3270
3271 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3272 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3273
3274 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3275 radeon_emit(&pipeline->cs, va >> 8);
3276 radeon_emit(&pipeline->cs, va >> 40);
3277
3278 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3279 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3280 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3281
3282 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3283 S_00B860_WAVES(pipeline->max_waves) |
3284 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3285
3286 /* Calculate best compute resource limits. */
3287 waves_per_threadgroup =
3288 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3289 compute_shader->info.cs.block_size[1] *
3290 compute_shader->info.cs.block_size[2], 64);
3291 compute_resource_limits =
3292 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3293
3294 if (device->physical_device->rad_info.chip_class >= CIK) {
3295 unsigned num_cu_per_se =
3296 device->physical_device->rad_info.num_good_compute_units /
3297 device->physical_device->rad_info.max_se;
3298
3299 /* Force even distribution on all SIMDs in CU if the workgroup
3300 * size is 64. This has shown some good improvements if # of
3301 * CUs per SE is not a multiple of 4.
3302 */
3303 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3304 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3305 }
3306
3307 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3308 compute_resource_limits);
3309
3310 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3311 radeon_emit(&pipeline->cs,
3312 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3313 radeon_emit(&pipeline->cs,
3314 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3315 radeon_emit(&pipeline->cs,
3316 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3317
3318 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3319 }
3320
3321 static VkResult radv_compute_pipeline_create(
3322 VkDevice _device,
3323 VkPipelineCache _cache,
3324 const VkComputePipelineCreateInfo* pCreateInfo,
3325 const VkAllocationCallbacks* pAllocator,
3326 VkPipeline* pPipeline)
3327 {
3328 RADV_FROM_HANDLE(radv_device, device, _device);
3329 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3330 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3331 struct radv_pipeline *pipeline;
3332 VkResult result;
3333
3334 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3335 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3336 if (pipeline == NULL)
3337 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3338
3339 pipeline->device = device;
3340 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3341 assert(pipeline->layout);
3342
3343 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3344 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3345
3346 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3347 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3348 result = radv_pipeline_scratch_init(device, pipeline);
3349 if (result != VK_SUCCESS) {
3350 radv_pipeline_destroy(device, pipeline, pAllocator);
3351 return result;
3352 }
3353
3354 radv_compute_generate_pm4(pipeline);
3355
3356 *pPipeline = radv_pipeline_to_handle(pipeline);
3357
3358 return VK_SUCCESS;
3359 }
3360
3361 VkResult radv_CreateComputePipelines(
3362 VkDevice _device,
3363 VkPipelineCache pipelineCache,
3364 uint32_t count,
3365 const VkComputePipelineCreateInfo* pCreateInfos,
3366 const VkAllocationCallbacks* pAllocator,
3367 VkPipeline* pPipelines)
3368 {
3369 VkResult result = VK_SUCCESS;
3370
3371 unsigned i = 0;
3372 for (; i < count; i++) {
3373 VkResult r;
3374 r = radv_compute_pipeline_create(_device, pipelineCache,
3375 &pCreateInfos[i],
3376 pAllocator, &pPipelines[i]);
3377 if (r != VK_SUCCESS) {
3378 result = r;
3379 pPipelines[i] = VK_NULL_HANDLE;
3380 }
3381 }
3382
3383 return result;
3384 }