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radv: Merge vs state computation with PM4 generation.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 static void
53 radv_pipeline_destroy(struct radv_device *device,
54 struct radv_pipeline *pipeline,
55 const VkAllocationCallbacks* allocator)
56 {
57 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
58 if (pipeline->shaders[i])
59 radv_shader_variant_destroy(device, pipeline->shaders[i]);
60
61 if (pipeline->gs_copy_shader)
62 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
63
64 if(pipeline->cs.buf)
65 free(pipeline->cs.buf);
66 vk_free2(&device->alloc, allocator, pipeline);
67 }
68
69 void radv_DestroyPipeline(
70 VkDevice _device,
71 VkPipeline _pipeline,
72 const VkAllocationCallbacks* pAllocator)
73 {
74 RADV_FROM_HANDLE(radv_device, device, _device);
75 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
76
77 if (!_pipeline)
78 return;
79
80 radv_pipeline_destroy(device, pipeline, pAllocator);
81 }
82
83 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
84 {
85 int i;
86
87 for (i = 0; i < MESA_SHADER_STAGES; i++) {
88 if (!pipeline->shaders[i])
89 continue;
90
91 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
92 }
93 }
94
95 static uint32_t get_hash_flags(struct radv_device *device)
96 {
97 uint32_t hash_flags = 0;
98
99 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
100 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
101 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
102 hash_flags |= RADV_HASH_SHADER_SISCHED;
103 return hash_flags;
104 }
105
106 static VkResult
107 radv_pipeline_scratch_init(struct radv_device *device,
108 struct radv_pipeline *pipeline)
109 {
110 unsigned scratch_bytes_per_wave = 0;
111 unsigned max_waves = 0;
112 unsigned min_waves = 1;
113
114 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
115 if (pipeline->shaders[i]) {
116 unsigned max_stage_waves = device->scratch_waves;
117
118 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
119 pipeline->shaders[i]->config.scratch_bytes_per_wave);
120
121 max_stage_waves = MIN2(max_stage_waves,
122 4 * device->physical_device->rad_info.num_good_compute_units *
123 (256 / pipeline->shaders[i]->config.num_vgprs));
124 max_waves = MAX2(max_waves, max_stage_waves);
125 }
126 }
127
128 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
129 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
130 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
131 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
132 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
133 }
134
135 if (scratch_bytes_per_wave)
136 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
137
138 if (scratch_bytes_per_wave && max_waves < min_waves) {
139 /* Not really true at this moment, but will be true on first
140 * execution. Avoid having hanging shaders. */
141 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
142 }
143 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
144 pipeline->max_waves = max_waves;
145 return VK_SUCCESS;
146 }
147
148 static uint32_t si_translate_blend_function(VkBlendOp op)
149 {
150 switch (op) {
151 case VK_BLEND_OP_ADD:
152 return V_028780_COMB_DST_PLUS_SRC;
153 case VK_BLEND_OP_SUBTRACT:
154 return V_028780_COMB_SRC_MINUS_DST;
155 case VK_BLEND_OP_REVERSE_SUBTRACT:
156 return V_028780_COMB_DST_MINUS_SRC;
157 case VK_BLEND_OP_MIN:
158 return V_028780_COMB_MIN_DST_SRC;
159 case VK_BLEND_OP_MAX:
160 return V_028780_COMB_MAX_DST_SRC;
161 default:
162 return 0;
163 }
164 }
165
166 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
167 {
168 switch (factor) {
169 case VK_BLEND_FACTOR_ZERO:
170 return V_028780_BLEND_ZERO;
171 case VK_BLEND_FACTOR_ONE:
172 return V_028780_BLEND_ONE;
173 case VK_BLEND_FACTOR_SRC_COLOR:
174 return V_028780_BLEND_SRC_COLOR;
175 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
176 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
177 case VK_BLEND_FACTOR_DST_COLOR:
178 return V_028780_BLEND_DST_COLOR;
179 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
180 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
181 case VK_BLEND_FACTOR_SRC_ALPHA:
182 return V_028780_BLEND_SRC_ALPHA;
183 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
184 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
185 case VK_BLEND_FACTOR_DST_ALPHA:
186 return V_028780_BLEND_DST_ALPHA;
187 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
188 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
189 case VK_BLEND_FACTOR_CONSTANT_COLOR:
190 return V_028780_BLEND_CONSTANT_COLOR;
191 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
192 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
193 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
194 return V_028780_BLEND_CONSTANT_ALPHA;
195 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
196 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
197 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
198 return V_028780_BLEND_SRC_ALPHA_SATURATE;
199 case VK_BLEND_FACTOR_SRC1_COLOR:
200 return V_028780_BLEND_SRC1_COLOR;
201 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
202 return V_028780_BLEND_INV_SRC1_COLOR;
203 case VK_BLEND_FACTOR_SRC1_ALPHA:
204 return V_028780_BLEND_SRC1_ALPHA;
205 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
206 return V_028780_BLEND_INV_SRC1_ALPHA;
207 default:
208 return 0;
209 }
210 }
211
212 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
213 {
214 switch (op) {
215 case VK_BLEND_OP_ADD:
216 return V_028760_OPT_COMB_ADD;
217 case VK_BLEND_OP_SUBTRACT:
218 return V_028760_OPT_COMB_SUBTRACT;
219 case VK_BLEND_OP_REVERSE_SUBTRACT:
220 return V_028760_OPT_COMB_REVSUBTRACT;
221 case VK_BLEND_OP_MIN:
222 return V_028760_OPT_COMB_MIN;
223 case VK_BLEND_OP_MAX:
224 return V_028760_OPT_COMB_MAX;
225 default:
226 return V_028760_OPT_COMB_BLEND_DISABLED;
227 }
228 }
229
230 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
231 {
232 switch (factor) {
233 case VK_BLEND_FACTOR_ZERO:
234 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
235 case VK_BLEND_FACTOR_ONE:
236 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
237 case VK_BLEND_FACTOR_SRC_COLOR:
238 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
239 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
240 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
241 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
242 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
243 case VK_BLEND_FACTOR_SRC_ALPHA:
244 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
245 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
246 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
247 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
248 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
249 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
250 default:
251 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
252 }
253 }
254
255 /**
256 * Get rid of DST in the blend factors by commuting the operands:
257 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
258 */
259 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
260 unsigned *dst_factor, unsigned expected_dst,
261 unsigned replacement_src)
262 {
263 if (*src_factor == expected_dst &&
264 *dst_factor == VK_BLEND_FACTOR_ZERO) {
265 *src_factor = VK_BLEND_FACTOR_ZERO;
266 *dst_factor = replacement_src;
267
268 /* Commuting the operands requires reversing subtractions. */
269 if (*func == VK_BLEND_OP_SUBTRACT)
270 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
271 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
272 *func = VK_BLEND_OP_SUBTRACT;
273 }
274 }
275
276 static bool si_blend_factor_uses_dst(unsigned factor)
277 {
278 return factor == VK_BLEND_FACTOR_DST_COLOR ||
279 factor == VK_BLEND_FACTOR_DST_ALPHA ||
280 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
281 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
282 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
283 }
284
285 static bool is_dual_src(VkBlendFactor factor)
286 {
287 switch (factor) {
288 case VK_BLEND_FACTOR_SRC1_COLOR:
289 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
290 case VK_BLEND_FACTOR_SRC1_ALPHA:
291 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
292 return true;
293 default:
294 return false;
295 }
296 }
297
298 static unsigned si_choose_spi_color_format(VkFormat vk_format,
299 bool blend_enable,
300 bool blend_need_alpha)
301 {
302 const struct vk_format_description *desc = vk_format_description(vk_format);
303 unsigned format, ntype, swap;
304
305 /* Alpha is needed for alpha-to-coverage.
306 * Blending may be with or without alpha.
307 */
308 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
309 unsigned alpha = 0; /* exports alpha, but may not support blending */
310 unsigned blend = 0; /* supports blending, but may not export alpha */
311 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
312
313 format = radv_translate_colorformat(vk_format);
314 ntype = radv_translate_color_numformat(vk_format, desc,
315 vk_format_get_first_non_void_channel(vk_format));
316 swap = radv_translate_colorswap(vk_format, false);
317
318 /* Choose the SPI color formats. These are required values for Stoney/RB+.
319 * Other chips have multiple choices, though they are not necessarily better.
320 */
321 switch (format) {
322 case V_028C70_COLOR_5_6_5:
323 case V_028C70_COLOR_1_5_5_5:
324 case V_028C70_COLOR_5_5_5_1:
325 case V_028C70_COLOR_4_4_4_4:
326 case V_028C70_COLOR_10_11_11:
327 case V_028C70_COLOR_11_11_10:
328 case V_028C70_COLOR_8:
329 case V_028C70_COLOR_8_8:
330 case V_028C70_COLOR_8_8_8_8:
331 case V_028C70_COLOR_10_10_10_2:
332 case V_028C70_COLOR_2_10_10_10:
333 if (ntype == V_028C70_NUMBER_UINT)
334 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
335 else if (ntype == V_028C70_NUMBER_SINT)
336 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
337 else
338 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
339 break;
340
341 case V_028C70_COLOR_16:
342 case V_028C70_COLOR_16_16:
343 case V_028C70_COLOR_16_16_16_16:
344 if (ntype == V_028C70_NUMBER_UNORM ||
345 ntype == V_028C70_NUMBER_SNORM) {
346 /* UNORM16 and SNORM16 don't support blending */
347 if (ntype == V_028C70_NUMBER_UNORM)
348 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
349 else
350 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
351
352 /* Use 32 bits per channel for blending. */
353 if (format == V_028C70_COLOR_16) {
354 if (swap == V_028C70_SWAP_STD) { /* R */
355 blend = V_028714_SPI_SHADER_32_R;
356 blend_alpha = V_028714_SPI_SHADER_32_AR;
357 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
358 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
359 else
360 assert(0);
361 } else if (format == V_028C70_COLOR_16_16) {
362 if (swap == V_028C70_SWAP_STD) { /* RG */
363 blend = V_028714_SPI_SHADER_32_GR;
364 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
365 } else if (swap == V_028C70_SWAP_ALT) /* RA */
366 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
367 else
368 assert(0);
369 } else /* 16_16_16_16 */
370 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
371 } else if (ntype == V_028C70_NUMBER_UINT)
372 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
373 else if (ntype == V_028C70_NUMBER_SINT)
374 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
375 else if (ntype == V_028C70_NUMBER_FLOAT)
376 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
377 else
378 assert(0);
379 break;
380
381 case V_028C70_COLOR_32:
382 if (swap == V_028C70_SWAP_STD) { /* R */
383 blend = normal = V_028714_SPI_SHADER_32_R;
384 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
385 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
386 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
387 else
388 assert(0);
389 break;
390
391 case V_028C70_COLOR_32_32:
392 if (swap == V_028C70_SWAP_STD) { /* RG */
393 blend = normal = V_028714_SPI_SHADER_32_GR;
394 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
395 } else if (swap == V_028C70_SWAP_ALT) /* RA */
396 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
397 else
398 assert(0);
399 break;
400
401 case V_028C70_COLOR_32_32_32_32:
402 case V_028C70_COLOR_8_24:
403 case V_028C70_COLOR_24_8:
404 case V_028C70_COLOR_X24_8_32_FLOAT:
405 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
406 break;
407
408 default:
409 unreachable("unhandled blend format");
410 }
411
412 if (blend_enable && blend_need_alpha)
413 return blend_alpha;
414 else if(blend_need_alpha)
415 return alpha;
416 else if(blend_enable)
417 return blend;
418 else
419 return normal;
420 }
421
422 static void
423 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
424 const VkGraphicsPipelineCreateInfo *pCreateInfo,
425 uint32_t blend_enable,
426 uint32_t blend_need_alpha,
427 bool single_cb_enable,
428 bool blend_mrt0_is_dual_src)
429 {
430 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
431 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
432 struct radv_blend_state *blend = &pipeline->graphics.blend;
433 unsigned col_format = 0;
434
435 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
436 unsigned cf;
437
438 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
439 cf = V_028714_SPI_SHADER_ZERO;
440 } else {
441 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
442
443 cf = si_choose_spi_color_format(attachment->format,
444 blend_enable & (1 << i),
445 blend_need_alpha & (1 << i));
446 }
447
448 col_format |= cf << (4 * i);
449 }
450
451 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
452
453 if (blend_mrt0_is_dual_src)
454 col_format |= (col_format & 0xf) << 4;
455 blend->spi_shader_col_format = col_format;
456 }
457
458 static bool
459 format_is_int8(VkFormat format)
460 {
461 const struct vk_format_description *desc = vk_format_description(format);
462 int channel = vk_format_get_first_non_void_channel(format);
463
464 return channel >= 0 && desc->channel[channel].pure_integer &&
465 desc->channel[channel].size == 8;
466 }
467
468 static bool
469 format_is_int10(VkFormat format)
470 {
471 const struct vk_format_description *desc = vk_format_description(format);
472
473 if (desc->nr_channels != 4)
474 return false;
475 for (unsigned i = 0; i < 4; i++) {
476 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
477 return true;
478 }
479 return false;
480 }
481
482 unsigned radv_format_meta_fs_key(VkFormat format)
483 {
484 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
485 bool is_int8 = format_is_int8(format);
486 bool is_int10 = format_is_int10(format);
487
488 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
489 }
490
491 static void
492 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
493 unsigned *is_int8, unsigned *is_int10)
494 {
495 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
496 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
497 *is_int8 = 0;
498 *is_int10 = 0;
499
500 for (unsigned i = 0; i < subpass->color_count; ++i) {
501 struct radv_render_pass_attachment *attachment;
502
503 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
504 continue;
505
506 attachment = pass->attachments + subpass->color_attachments[i].attachment;
507
508 if (format_is_int8(attachment->format))
509 *is_int8 |= 1 << i;
510 if (format_is_int10(attachment->format))
511 *is_int10 |= 1 << i;
512 }
513 }
514
515 static void
516 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
517 const VkGraphicsPipelineCreateInfo *pCreateInfo,
518 const struct radv_graphics_pipeline_create_info *extra)
519 {
520 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
521 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
522 struct radv_blend_state *blend = &pipeline->graphics.blend;
523 unsigned mode = V_028808_CB_NORMAL;
524 uint32_t blend_enable = 0, blend_need_alpha = 0;
525 bool blend_mrt0_is_dual_src = false;
526 int i;
527 bool single_cb_enable = false;
528
529 if (!vkblend)
530 return;
531
532 if (extra && extra->custom_blend_mode) {
533 single_cb_enable = true;
534 mode = extra->custom_blend_mode;
535 }
536 blend->cb_color_control = 0;
537 if (vkblend->logicOpEnable)
538 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
539 else
540 blend->cb_color_control |= S_028808_ROP3(0xcc);
541
542 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
543 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
544 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
545 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
546
547 if (vkms && vkms->alphaToCoverageEnable) {
548 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
549 }
550
551 blend->cb_target_mask = 0;
552 for (i = 0; i < vkblend->attachmentCount; i++) {
553 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
554 unsigned blend_cntl = 0;
555 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
556 VkBlendOp eqRGB = att->colorBlendOp;
557 VkBlendFactor srcRGB = att->srcColorBlendFactor;
558 VkBlendFactor dstRGB = att->dstColorBlendFactor;
559 VkBlendOp eqA = att->alphaBlendOp;
560 VkBlendFactor srcA = att->srcAlphaBlendFactor;
561 VkBlendFactor dstA = att->dstAlphaBlendFactor;
562
563 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
564
565 if (!att->colorWriteMask)
566 continue;
567
568 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
569 if (!att->blendEnable) {
570 blend->cb_blend_control[i] = blend_cntl;
571 continue;
572 }
573
574 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
575 if (i == 0)
576 blend_mrt0_is_dual_src = true;
577
578 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
579 srcRGB = VK_BLEND_FACTOR_ONE;
580 dstRGB = VK_BLEND_FACTOR_ONE;
581 }
582 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
583 srcA = VK_BLEND_FACTOR_ONE;
584 dstA = VK_BLEND_FACTOR_ONE;
585 }
586
587 /* Blending optimizations for RB+.
588 * These transformations don't change the behavior.
589 *
590 * First, get rid of DST in the blend factors:
591 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
592 */
593 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
594 VK_BLEND_FACTOR_DST_COLOR,
595 VK_BLEND_FACTOR_SRC_COLOR);
596
597 si_blend_remove_dst(&eqA, &srcA, &dstA,
598 VK_BLEND_FACTOR_DST_COLOR,
599 VK_BLEND_FACTOR_SRC_COLOR);
600
601 si_blend_remove_dst(&eqA, &srcA, &dstA,
602 VK_BLEND_FACTOR_DST_ALPHA,
603 VK_BLEND_FACTOR_SRC_ALPHA);
604
605 /* Look up the ideal settings from tables. */
606 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
607 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
608 srcA_opt = si_translate_blend_opt_factor(srcA, true);
609 dstA_opt = si_translate_blend_opt_factor(dstA, true);
610
611 /* Handle interdependencies. */
612 if (si_blend_factor_uses_dst(srcRGB))
613 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
614 if (si_blend_factor_uses_dst(srcA))
615 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
616
617 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
618 (dstRGB == VK_BLEND_FACTOR_ZERO ||
619 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
620 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
621 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
622
623 /* Set the final value. */
624 blend->sx_mrt_blend_opt[i] =
625 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
626 S_028760_COLOR_DST_OPT(dstRGB_opt) |
627 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
628 S_028760_ALPHA_SRC_OPT(srcA_opt) |
629 S_028760_ALPHA_DST_OPT(dstA_opt) |
630 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
631 blend_cntl |= S_028780_ENABLE(1);
632
633 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
634 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
635 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
636 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
637 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
638 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
639 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
640 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
641 }
642 blend->cb_blend_control[i] = blend_cntl;
643
644 blend_enable |= 1 << i;
645
646 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
647 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
648 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
649 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
650 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
651 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
652 blend_need_alpha |= 1 << i;
653 }
654 for (i = vkblend->attachmentCount; i < 8; i++) {
655 blend->cb_blend_control[i] = 0;
656 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
657 }
658
659 /* disable RB+ for now */
660 if (pipeline->device->physical_device->has_rbplus)
661 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
662
663 if (blend->cb_target_mask)
664 blend->cb_color_control |= S_028808_MODE(mode);
665 else
666 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
667
668 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
669 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
670 }
671
672 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
673 {
674 switch (op) {
675 case VK_STENCIL_OP_KEEP:
676 return V_02842C_STENCIL_KEEP;
677 case VK_STENCIL_OP_ZERO:
678 return V_02842C_STENCIL_ZERO;
679 case VK_STENCIL_OP_REPLACE:
680 return V_02842C_STENCIL_REPLACE_TEST;
681 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
682 return V_02842C_STENCIL_ADD_CLAMP;
683 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
684 return V_02842C_STENCIL_SUB_CLAMP;
685 case VK_STENCIL_OP_INVERT:
686 return V_02842C_STENCIL_INVERT;
687 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
688 return V_02842C_STENCIL_ADD_WRAP;
689 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
690 return V_02842C_STENCIL_SUB_WRAP;
691 default:
692 return 0;
693 }
694 }
695 static void
696 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
697 const VkGraphicsPipelineCreateInfo *pCreateInfo,
698 const struct radv_graphics_pipeline_create_info *extra)
699 {
700 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
701 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
702
703 if (!vkds)
704 return;
705
706 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
707 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
708 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
709 return;
710
711 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
712 bool has_depth_attachment = vk_format_is_depth(attachment->format);
713 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
714
715 if (has_depth_attachment) {
716 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
717 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
718 S_028800_ZFUNC(vkds->depthCompareOp) |
719 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
720
721 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
722 ds->db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
723 }
724
725 if (has_stencil_attachment && vkds->stencilTestEnable) {
726 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
727 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
728 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
729 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
730 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
731
732 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
733 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
734 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
735 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
736 }
737
738 if (extra) {
739
740 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
741 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
742
743 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
744 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
745 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
746 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
747 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
748 }
749 }
750
751 static uint32_t si_translate_fill(VkPolygonMode func)
752 {
753 switch(func) {
754 case VK_POLYGON_MODE_FILL:
755 return V_028814_X_DRAW_TRIANGLES;
756 case VK_POLYGON_MODE_LINE:
757 return V_028814_X_DRAW_LINES;
758 case VK_POLYGON_MODE_POINT:
759 return V_028814_X_DRAW_POINTS;
760 default:
761 assert(0);
762 return V_028814_X_DRAW_POINTS;
763 }
764 }
765 static void
766 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
767 const VkGraphicsPipelineCreateInfo *pCreateInfo)
768 {
769 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
770 struct radv_raster_state *raster = &pipeline->graphics.raster;
771
772 raster->spi_interp_control =
773 S_0286D4_FLAT_SHADE_ENA(1) |
774 S_0286D4_PNT_SPRITE_ENA(1) |
775 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
776 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
777 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
778 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
779 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
780
781
782 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
783 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
784 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
785 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
786 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
787 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
788
789 raster->pa_su_vtx_cntl =
790 S_028BE4_PIX_CENTER(1) | // TODO verify
791 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
792 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
793
794 raster->pa_su_sc_mode_cntl =
795 S_028814_FACE(vkraster->frontFace) |
796 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
797 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
798 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
799 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
800 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
801 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
802 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
803 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
804
805 }
806
807 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
808 {
809 uint32_t num_samples = vkms->rasterizationSamples;
810 uint32_t ps_iter_samples = 1;
811
812 if (vkms->sampleShadingEnable) {
813 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
814 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
815 }
816 return ps_iter_samples;
817 }
818
819 static void
820 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
821 const VkGraphicsPipelineCreateInfo *pCreateInfo)
822 {
823 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
824 struct radv_multisample_state *ms = &pipeline->graphics.ms;
825 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
826 int ps_iter_samples = 1;
827 uint32_t mask = 0xffff;
828
829 if (vkms)
830 ms->num_samples = vkms->rasterizationSamples;
831 else
832 ms->num_samples = 1;
833
834 if (vkms)
835 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
836 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
837 ps_iter_samples = ms->num_samples;
838 }
839
840 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
841 ms->pa_sc_aa_config = 0;
842 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
843 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
844 ms->pa_sc_mode_cntl_1 =
845 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
846 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
847 /* always 1: */
848 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
849 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
850 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
851 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
852 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
853 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
854 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
855 S_028A48_VPORT_SCISSOR_ENABLE(1);
856
857 if (ms->num_samples > 1) {
858 unsigned log_samples = util_logbase2(ms->num_samples);
859 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
860 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
861 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
862 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
863 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
864 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
865 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
866 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
867 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
868 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
869 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
870 if (ps_iter_samples > 1)
871 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
872 }
873
874 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
875 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
876 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
877 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
878 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
879 }
880
881 if (vkms && vkms->pSampleMask) {
882 mask = vkms->pSampleMask[0] & 0xffff;
883 }
884
885 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
886 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
887 }
888
889 static bool
890 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
891 {
892 switch (topology) {
893 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
894 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
895 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
896 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
897 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
898 return false;
899 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
900 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
901 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
902 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
903 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
904 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
905 return true;
906 default:
907 unreachable("unhandled primitive type");
908 }
909 }
910
911 static uint32_t
912 si_translate_prim(enum VkPrimitiveTopology topology)
913 {
914 switch (topology) {
915 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
916 return V_008958_DI_PT_POINTLIST;
917 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
918 return V_008958_DI_PT_LINELIST;
919 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
920 return V_008958_DI_PT_LINESTRIP;
921 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
922 return V_008958_DI_PT_TRILIST;
923 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
924 return V_008958_DI_PT_TRISTRIP;
925 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
926 return V_008958_DI_PT_TRIFAN;
927 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
928 return V_008958_DI_PT_LINELIST_ADJ;
929 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
930 return V_008958_DI_PT_LINESTRIP_ADJ;
931 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
932 return V_008958_DI_PT_TRILIST_ADJ;
933 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
934 return V_008958_DI_PT_TRISTRIP_ADJ;
935 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
936 return V_008958_DI_PT_PATCH;
937 default:
938 assert(0);
939 return 0;
940 }
941 }
942
943 static uint32_t
944 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
945 {
946 switch (gl_prim) {
947 case 0: /* GL_POINTS */
948 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
949 case 1: /* GL_LINES */
950 case 3: /* GL_LINE_STRIP */
951 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
952 case 0x8E7A: /* GL_ISOLINES */
953 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
954
955 case 4: /* GL_TRIANGLES */
956 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
957 case 5: /* GL_TRIANGLE_STRIP */
958 case 7: /* GL_QUADS */
959 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
960 default:
961 assert(0);
962 return 0;
963 }
964 }
965
966 static uint32_t
967 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
968 {
969 switch (topology) {
970 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
971 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
972 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
973 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
974 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
975 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
976 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
977 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
978 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
979 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
980 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
981 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
982 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
983 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
984 default:
985 assert(0);
986 return 0;
987 }
988 }
989
990 static unsigned si_map_swizzle(unsigned swizzle)
991 {
992 switch (swizzle) {
993 case VK_SWIZZLE_Y:
994 return V_008F0C_SQ_SEL_Y;
995 case VK_SWIZZLE_Z:
996 return V_008F0C_SQ_SEL_Z;
997 case VK_SWIZZLE_W:
998 return V_008F0C_SQ_SEL_W;
999 case VK_SWIZZLE_0:
1000 return V_008F0C_SQ_SEL_0;
1001 case VK_SWIZZLE_1:
1002 return V_008F0C_SQ_SEL_1;
1003 default: /* VK_SWIZZLE_X */
1004 return V_008F0C_SQ_SEL_X;
1005 }
1006 }
1007
1008
1009 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1010 {
1011 switch(state) {
1012 case VK_DYNAMIC_STATE_VIEWPORT:
1013 return RADV_DYNAMIC_VIEWPORT;
1014 case VK_DYNAMIC_STATE_SCISSOR:
1015 return RADV_DYNAMIC_SCISSOR;
1016 case VK_DYNAMIC_STATE_LINE_WIDTH:
1017 return RADV_DYNAMIC_LINE_WIDTH;
1018 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1019 return RADV_DYNAMIC_DEPTH_BIAS;
1020 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1021 return RADV_DYNAMIC_BLEND_CONSTANTS;
1022 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1023 return RADV_DYNAMIC_DEPTH_BOUNDS;
1024 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1025 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1026 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1027 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1028 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1029 return RADV_DYNAMIC_STENCIL_REFERENCE;
1030 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1031 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1032 default:
1033 unreachable("Unhandled dynamic state");
1034 }
1035 }
1036
1037 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1038 {
1039 uint32_t states = RADV_DYNAMIC_ALL;
1040
1041 /* If rasterization is disabled we do not care about any of the dynamic states,
1042 * since they are all rasterization related only. */
1043 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1044 return 0;
1045
1046 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1047 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1048
1049 if (!pCreateInfo->pDepthStencilState ||
1050 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1051 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1052
1053 if (!pCreateInfo->pDepthStencilState ||
1054 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1055 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1056 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1057 RADV_DYNAMIC_STENCIL_REFERENCE);
1058
1059 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1060 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1061
1062 /* TODO: blend constants & line width. */
1063
1064 return states;
1065 }
1066
1067
1068 static void
1069 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1070 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1071 {
1072 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1073 uint32_t states = needed_states;
1074 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1075 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1076
1077 pipeline->dynamic_state = default_dynamic_state;
1078 pipeline->graphics.needed_dynamic_state = needed_states;
1079
1080 if (pCreateInfo->pDynamicState) {
1081 /* Remove all of the states that are marked as dynamic */
1082 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1083 for (uint32_t s = 0; s < count; s++)
1084 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1085 }
1086
1087 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1088
1089 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1090 assert(pCreateInfo->pViewportState);
1091
1092 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1093 if (states & RADV_DYNAMIC_VIEWPORT) {
1094 typed_memcpy(dynamic->viewport.viewports,
1095 pCreateInfo->pViewportState->pViewports,
1096 pCreateInfo->pViewportState->viewportCount);
1097 }
1098 }
1099
1100 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1101 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1102 if (states & RADV_DYNAMIC_SCISSOR) {
1103 typed_memcpy(dynamic->scissor.scissors,
1104 pCreateInfo->pViewportState->pScissors,
1105 pCreateInfo->pViewportState->scissorCount);
1106 }
1107 }
1108
1109 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1110 assert(pCreateInfo->pRasterizationState);
1111 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1112 }
1113
1114 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1115 assert(pCreateInfo->pRasterizationState);
1116 dynamic->depth_bias.bias =
1117 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1118 dynamic->depth_bias.clamp =
1119 pCreateInfo->pRasterizationState->depthBiasClamp;
1120 dynamic->depth_bias.slope =
1121 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1122 }
1123
1124 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1125 *
1126 * pColorBlendState is [...] NULL if the pipeline has rasterization
1127 * disabled or if the subpass of the render pass the pipeline is
1128 * created against does not use any color attachments.
1129 */
1130 bool uses_color_att = false;
1131 for (unsigned i = 0; i < subpass->color_count; ++i) {
1132 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1133 uses_color_att = true;
1134 break;
1135 }
1136 }
1137
1138 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1139 assert(pCreateInfo->pColorBlendState);
1140 typed_memcpy(dynamic->blend_constants,
1141 pCreateInfo->pColorBlendState->blendConstants, 4);
1142 }
1143
1144 /* If there is no depthstencil attachment, then don't read
1145 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1146 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1147 * no need to override the depthstencil defaults in
1148 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1149 *
1150 * Section 9.2 of the Vulkan 1.0.15 spec says:
1151 *
1152 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1153 * disabled or if the subpass of the render pass the pipeline is created
1154 * against does not use a depth/stencil attachment.
1155 */
1156 if (needed_states &&
1157 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1158 assert(pCreateInfo->pDepthStencilState);
1159
1160 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1161 dynamic->depth_bounds.min =
1162 pCreateInfo->pDepthStencilState->minDepthBounds;
1163 dynamic->depth_bounds.max =
1164 pCreateInfo->pDepthStencilState->maxDepthBounds;
1165 }
1166
1167 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1168 dynamic->stencil_compare_mask.front =
1169 pCreateInfo->pDepthStencilState->front.compareMask;
1170 dynamic->stencil_compare_mask.back =
1171 pCreateInfo->pDepthStencilState->back.compareMask;
1172 }
1173
1174 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1175 dynamic->stencil_write_mask.front =
1176 pCreateInfo->pDepthStencilState->front.writeMask;
1177 dynamic->stencil_write_mask.back =
1178 pCreateInfo->pDepthStencilState->back.writeMask;
1179 }
1180
1181 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1182 dynamic->stencil_reference.front =
1183 pCreateInfo->pDepthStencilState->front.reference;
1184 dynamic->stencil_reference.back =
1185 pCreateInfo->pDepthStencilState->back.reference;
1186 }
1187 }
1188
1189 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1190 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1191 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1192 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1193 typed_memcpy(dynamic->discard_rectangle.rectangles,
1194 discard_rectangle_info->pDiscardRectangles,
1195 discard_rectangle_info->discardRectangleCount);
1196
1197 unsigned mask = 0;
1198
1199 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
1200 /* Interpret i as a bitmask, and then set the bit in the mask if
1201 * that combination of rectangles in which the pixel is contained
1202 * should pass the cliprect test. */
1203 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
1204
1205 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
1206 !relevant_subset)
1207 continue;
1208
1209 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
1210 relevant_subset)
1211 continue;
1212
1213 mask |= 1u << i;
1214 }
1215 pipeline->graphics.pa_sc_cliprect_rule = mask;
1216 } else {
1217 /* Allow from all rectangle combinations */
1218 pipeline->graphics.pa_sc_cliprect_rule = 0xffff;
1219 }
1220 pipeline->dynamic_state.mask = states;
1221 }
1222
1223 static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1224 struct radv_pipeline *pipeline)
1225 {
1226 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1227 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1228 &gs_info->tes.es_info : &gs_info->vs.es_info;
1229 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1230 bool uses_adjacency;
1231 switch(pCreateInfo->pInputAssemblyState->topology) {
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1236 uses_adjacency = true;
1237 break;
1238 default:
1239 uses_adjacency = false;
1240 break;
1241 }
1242
1243 /* All these are in dwords: */
1244 /* We can't allow using the whole LDS, because GS waves compete with
1245 * other shader stages for LDS space. */
1246 const unsigned max_lds_size = 8 * 1024;
1247 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1248 unsigned esgs_lds_size;
1249
1250 /* All these are per subgroup: */
1251 const unsigned max_out_prims = 32 * 1024;
1252 const unsigned max_es_verts = 255;
1253 const unsigned ideal_gs_prims = 64;
1254 unsigned max_gs_prims, gs_prims;
1255 unsigned min_es_verts, es_verts, worst_case_es_verts;
1256
1257 if (uses_adjacency || gs_num_invocations > 1)
1258 max_gs_prims = 127 / gs_num_invocations;
1259 else
1260 max_gs_prims = 255;
1261
1262 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1263 * Make sure we don't go over the maximum value.
1264 */
1265 if (gs_info->gs.vertices_out > 0) {
1266 max_gs_prims = MIN2(max_gs_prims,
1267 max_out_prims /
1268 (gs_info->gs.vertices_out * gs_num_invocations));
1269 }
1270 assert(max_gs_prims > 0);
1271
1272 /* If the primitive has adjacency, halve the number of vertices
1273 * that will be reused in multiple primitives.
1274 */
1275 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1276
1277 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1278 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1279
1280 /* Compute ESGS LDS size based on the worst case number of ES vertices
1281 * needed to create the target number of GS prims per subgroup.
1282 */
1283 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1284
1285 /* If total LDS usage is too big, refactor partitions based on ratio
1286 * of ESGS item sizes.
1287 */
1288 if (esgs_lds_size > max_lds_size) {
1289 /* Our target GS Prims Per Subgroup was too large. Calculate
1290 * the maximum number of GS Prims Per Subgroup that will fit
1291 * into LDS, capped by the maximum that the hardware can support.
1292 */
1293 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1294 max_gs_prims);
1295 assert(gs_prims > 0);
1296 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1297 max_es_verts);
1298
1299 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1300 assert(esgs_lds_size <= max_lds_size);
1301 }
1302
1303 /* Now calculate remaining ESGS information. */
1304 if (esgs_lds_size)
1305 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1306 else
1307 es_verts = max_es_verts;
1308
1309 /* Vertices for adjacency primitives are not always reused, so restore
1310 * it for ES_VERTS_PER_SUBGRP.
1311 */
1312 min_es_verts = gs_info->gs.vertices_in;
1313
1314 /* For normal primitives, the VGT only checks if they are past the ES
1315 * verts per subgroup after allocating a full GS primitive and if they
1316 * are, kick off a new subgroup. But if those additional ES verts are
1317 * unique (e.g. not reused) we need to make sure there is enough LDS
1318 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1319 */
1320 es_verts -= min_es_verts - 1;
1321
1322 uint32_t es_verts_per_subgroup = es_verts;
1323 uint32_t gs_prims_per_subgroup = gs_prims;
1324 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1325 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1326 pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128;
1327 pipeline->graphics.gs.vgt_gs_onchip_cntl =
1328 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1329 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1330 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1331 pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup =
1332 S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1333 pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1334 assert(max_prims_per_subgroup <= max_out_prims);
1335 }
1336
1337 static void
1338 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1339 {
1340 struct radv_device *device = pipeline->device;
1341 unsigned num_se = device->physical_device->rad_info.max_se;
1342 unsigned wave_size = 64;
1343 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1344 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1345 unsigned alignment = 256 * num_se;
1346 /* The maximum size is 63.999 MB per SE. */
1347 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1348 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1349 struct ac_es_output_info *es_info;
1350 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1351 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1352 else
1353 es_info = radv_pipeline_has_tess(pipeline) ?
1354 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1355 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1356
1357 /* Calculate the minimum size. */
1358 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1359 wave_size, alignment);
1360 /* These are recommended sizes, not minimum sizes. */
1361 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1362 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1363 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1364 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1365
1366 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1367 esgs_ring_size = align(esgs_ring_size, alignment);
1368 gsvs_ring_size = align(gsvs_ring_size, alignment);
1369
1370 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1371 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1372
1373 pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1374 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1375 }
1376
1377 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1378 unsigned *lds_size)
1379 {
1380 /* SPI barrier management bug:
1381 * Make sure we have at least 4k of LDS in use to avoid the bug.
1382 * It applies to workgroup sizes of more than one wavefront.
1383 */
1384 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1385 device->physical_device->rad_info.family == CHIP_KABINI ||
1386 device->physical_device->rad_info.family == CHIP_MULLINS)
1387 *lds_size = MAX2(*lds_size, 8);
1388 }
1389
1390 struct radv_shader_variant *
1391 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1392 {
1393 if (pipeline->shaders[MESA_SHADER_VERTEX])
1394 return pipeline->shaders[MESA_SHADER_VERTEX];
1395 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1396 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1397 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1398 }
1399
1400 static struct radv_shader_variant *
1401 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1402 {
1403 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1404 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1405 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1406 }
1407
1408 static void
1409 calculate_tess_state(struct radv_pipeline *pipeline,
1410 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1411 {
1412 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1413 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1414 unsigned num_tcs_patch_outputs;
1415 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1416 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1417 unsigned lds_size, hardware_lds_size;
1418 unsigned perpatch_output_offset;
1419 unsigned num_patches;
1420 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1421
1422 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1423 * are laid out in LDS. */
1424 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1425
1426 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1427 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1428 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1429
1430 /* Ensure that we only need one wave per SIMD so we don't need to check
1431 * resource usage. Also ensures that the number of tcs in and out
1432 * vertices per threadgroup are at most 256.
1433 */
1434 input_vertex_size = num_tcs_inputs * 16;
1435 output_vertex_size = num_tcs_outputs * 16;
1436
1437 input_patch_size = num_tcs_input_cp * input_vertex_size;
1438
1439 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1440 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1441 /* Ensure that we only need one wave per SIMD so we don't need to check
1442 * resource usage. Also ensures that the number of tcs in and out
1443 * vertices per threadgroup are at most 256.
1444 */
1445 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1446
1447 /* Make sure that the data fits in LDS. This assumes the shaders only
1448 * use LDS for the inputs and outputs.
1449 */
1450 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1451 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1452
1453 /* Make sure the output data fits in the offchip buffer */
1454 num_patches = MIN2(num_patches,
1455 (pipeline->device->tess_offchip_block_dw_size * 4) /
1456 output_patch_size);
1457
1458 /* Not necessary for correctness, but improves performance. The
1459 * specific value is taken from the proprietary driver.
1460 */
1461 num_patches = MIN2(num_patches, 40);
1462
1463 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1464 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1465 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1466 num_patches = MIN2(num_patches, one_wave);
1467 }
1468
1469 output_patch0_offset = input_patch_size * num_patches;
1470 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1471
1472 lds_size = output_patch0_offset + output_patch_size * num_patches;
1473
1474 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1475 assert(lds_size <= 65536);
1476 lds_size = align(lds_size, 512) / 512;
1477 } else {
1478 assert(lds_size <= 32768);
1479 lds_size = align(lds_size, 256) / 256;
1480 }
1481 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1482
1483 tess->lds_size = lds_size;
1484
1485 tess->tcs_in_layout = (input_patch_size / 4) |
1486 ((input_vertex_size / 4) << 13);
1487 tess->tcs_out_layout = (output_patch_size / 4) |
1488 ((output_vertex_size / 4) << 13);
1489 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1490 ((perpatch_output_offset / 16) << 16);
1491 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1492 (num_tcs_output_cp << 9) | num_patches;
1493
1494 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1495 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1496 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1497 tess->num_patches = num_patches;
1498 tess->num_tcs_input_cp = num_tcs_input_cp;
1499
1500 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1501 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1502
1503 switch (tes->info.tes.primitive_mode) {
1504 case GL_TRIANGLES:
1505 type = V_028B6C_TESS_TRIANGLE;
1506 break;
1507 case GL_QUADS:
1508 type = V_028B6C_TESS_QUAD;
1509 break;
1510 case GL_ISOLINES:
1511 type = V_028B6C_TESS_ISOLINE;
1512 break;
1513 }
1514
1515 switch (tes->info.tes.spacing) {
1516 case TESS_SPACING_EQUAL:
1517 partitioning = V_028B6C_PART_INTEGER;
1518 break;
1519 case TESS_SPACING_FRACTIONAL_ODD:
1520 partitioning = V_028B6C_PART_FRAC_ODD;
1521 break;
1522 case TESS_SPACING_FRACTIONAL_EVEN:
1523 partitioning = V_028B6C_PART_FRAC_EVEN;
1524 break;
1525 default:
1526 break;
1527 }
1528
1529 bool ccw = tes->info.tes.ccw;
1530 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1531 vk_find_struct_const(pCreateInfo->pTessellationState,
1532 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1533
1534 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1535 ccw = !ccw;
1536
1537 if (tes->info.tes.point_mode)
1538 topology = V_028B6C_OUTPUT_POINT;
1539 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1540 topology = V_028B6C_OUTPUT_LINE;
1541 else if (ccw)
1542 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1543 else
1544 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1545
1546 if (pipeline->device->has_distributed_tess) {
1547 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1548 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1549 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1550 else
1551 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1552 } else
1553 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1554
1555 tess->tf_param = S_028B6C_TYPE(type) |
1556 S_028B6C_PARTITIONING(partitioning) |
1557 S_028B6C_TOPOLOGY(topology) |
1558 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1559 }
1560
1561 static const struct radv_prim_vertex_count prim_size_table[] = {
1562 [V_008958_DI_PT_NONE] = {0, 0},
1563 [V_008958_DI_PT_POINTLIST] = {1, 1},
1564 [V_008958_DI_PT_LINELIST] = {2, 2},
1565 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1566 [V_008958_DI_PT_TRILIST] = {3, 3},
1567 [V_008958_DI_PT_TRIFAN] = {3, 1},
1568 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1569 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1570 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1571 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1572 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1573 [V_008958_DI_PT_RECTLIST] = {3, 3},
1574 [V_008958_DI_PT_LINELOOP] = {2, 1},
1575 [V_008958_DI_PT_POLYGON] = {3, 1},
1576 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1577 };
1578
1579 static const struct ac_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1580 {
1581 if (radv_pipeline_has_gs(pipeline))
1582 return &pipeline->gs_copy_shader->info.vs.outinfo;
1583 else if (radv_pipeline_has_tess(pipeline))
1584 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1585 else
1586 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1587 }
1588
1589 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1590 {
1591 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1592
1593 pipeline->graphics.vgt_primitiveid_en = false;
1594 pipeline->graphics.vgt_gs_mode = 0;
1595
1596 if (radv_pipeline_has_gs(pipeline)) {
1597 struct radv_shader_variant *gs =
1598 pipeline->shaders[MESA_SHADER_GEOMETRY];
1599
1600 pipeline->graphics.vgt_gs_mode =
1601 ac_vgt_gs_mode(gs->info.gs.vertices_out,
1602 pipeline->device->physical_device->rad_info.chip_class);
1603 } else if (outinfo->export_prim_id) {
1604 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1605 pipeline->graphics.vgt_primitiveid_en = true;
1606 }
1607 }
1608
1609 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1610 {
1611 uint32_t ps_input_cntl;
1612 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1613 ps_input_cntl = S_028644_OFFSET(offset);
1614 if (flat_shade)
1615 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1616 } else {
1617 /* The input is a DEFAULT_VAL constant. */
1618 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1619 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1620 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1621 ps_input_cntl = S_028644_OFFSET(0x20) |
1622 S_028644_DEFAULT_VAL(offset);
1623 }
1624 return ps_input_cntl;
1625 }
1626
1627 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1628 {
1629 struct radv_shader_variant *ps;
1630 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1631
1632 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1633
1634 unsigned ps_offset = 0;
1635
1636 if (ps->info.fs.prim_id_input) {
1637 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1638 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1639 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1640 ++ps_offset;
1641 }
1642 }
1643
1644 if (ps->info.fs.layer_input) {
1645 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1646 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1647 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1648 else
1649 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1650 ++ps_offset;
1651 }
1652
1653 if (ps->info.fs.has_pcoord) {
1654 unsigned val;
1655 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1656 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1657 ps_offset++;
1658 }
1659
1660 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1661 unsigned vs_offset;
1662 bool flat_shade;
1663 if (!(ps->info.fs.input_mask & (1u << i)))
1664 continue;
1665
1666 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1667 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1668 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1669 ++ps_offset;
1670 continue;
1671 }
1672
1673 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1674
1675 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1676 ++ps_offset;
1677 }
1678
1679 pipeline->graphics.ps_input_cntl_num = ps_offset;
1680 }
1681
1682 static void
1683 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1684 {
1685 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1686 int shader_count = 0;
1687
1688 if(shaders[MESA_SHADER_FRAGMENT]) {
1689 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1690 }
1691 if(shaders[MESA_SHADER_GEOMETRY]) {
1692 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1693 }
1694 if(shaders[MESA_SHADER_TESS_EVAL]) {
1695 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1696 }
1697 if(shaders[MESA_SHADER_TESS_CTRL]) {
1698 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1699 }
1700 if(shaders[MESA_SHADER_VERTEX]) {
1701 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1702 }
1703
1704 for (int i = 1; i < shader_count; ++i) {
1705 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1706 ordered_shaders[i - 1]);
1707
1708 nir_remove_dead_variables(ordered_shaders[i],
1709 nir_var_shader_out);
1710 nir_remove_dead_variables(ordered_shaders[i - 1],
1711 nir_var_shader_in);
1712
1713 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1714 ordered_shaders[i - 1]);
1715
1716 if (progress) {
1717 nir_lower_global_vars_to_local(ordered_shaders[i]);
1718 radv_optimize_nir(ordered_shaders[i]);
1719 nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
1720 radv_optimize_nir(ordered_shaders[i - 1]);
1721 }
1722 }
1723 }
1724
1725
1726 static struct radv_pipeline_key
1727 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1728 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1729 bool has_view_index)
1730 {
1731 const VkPipelineVertexInputStateCreateInfo *input_state =
1732 pCreateInfo->pVertexInputState;
1733 struct radv_pipeline_key key;
1734 memset(&key, 0, sizeof(key));
1735
1736 key.has_multiview_view_index = has_view_index;
1737
1738 uint32_t binding_input_rate = 0;
1739 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1740 if (input_state->pVertexBindingDescriptions[i].inputRate)
1741 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1742 }
1743
1744 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1745 unsigned binding;
1746 binding = input_state->pVertexAttributeDescriptions[i].binding;
1747 if (binding_input_rate & (1u << binding))
1748 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1749 }
1750
1751 if (pCreateInfo->pTessellationState)
1752 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1753
1754
1755 if (pCreateInfo->pMultisampleState &&
1756 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1757 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1758 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1759 key.multisample = true;
1760 key.log2_num_samples = util_logbase2(num_samples);
1761 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1762 }
1763
1764 key.col_format = pipeline->graphics.blend.spi_shader_col_format;
1765 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1766 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1767
1768 return key;
1769 }
1770
1771 static void
1772 radv_fill_shader_keys(struct ac_shader_variant_key *keys,
1773 const struct radv_pipeline_key *key,
1774 nir_shader **nir)
1775 {
1776 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1777
1778 if (nir[MESA_SHADER_TESS_CTRL]) {
1779 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1780 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1781 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1782
1783 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1784 }
1785
1786 if (nir[MESA_SHADER_GEOMETRY]) {
1787 if (nir[MESA_SHADER_TESS_CTRL])
1788 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1789 else
1790 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1791 }
1792
1793 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1794 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1795
1796 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1797 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1798 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1799 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1800 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1801 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1802 }
1803
1804 static void
1805 merge_tess_info(struct shader_info *tes_info,
1806 const struct shader_info *tcs_info)
1807 {
1808 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1809 *
1810 * "PointMode. Controls generation of points rather than triangles
1811 * or lines. This functionality defaults to disabled, and is
1812 * enabled if either shader stage includes the execution mode.
1813 *
1814 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1815 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1816 * and OutputVertices, it says:
1817 *
1818 * "One mode must be set in at least one of the tessellation
1819 * shader stages."
1820 *
1821 * So, the fields can be set in either the TCS or TES, but they must
1822 * agree if set in both. Our backend looks at TES, so bitwise-or in
1823 * the values from the TCS.
1824 */
1825 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1826 tes_info->tess.tcs_vertices_out == 0 ||
1827 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1828 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1829
1830 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1831 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1832 tcs_info->tess.spacing == tes_info->tess.spacing);
1833 tes_info->tess.spacing |= tcs_info->tess.spacing;
1834
1835 assert(tcs_info->tess.primitive_mode == 0 ||
1836 tes_info->tess.primitive_mode == 0 ||
1837 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1838 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1839 tes_info->tess.ccw |= tcs_info->tess.ccw;
1840 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1841 }
1842
1843 static
1844 void radv_create_shaders(struct radv_pipeline *pipeline,
1845 struct radv_device *device,
1846 struct radv_pipeline_cache *cache,
1847 struct radv_pipeline_key key,
1848 const VkPipelineShaderStageCreateInfo **pStages)
1849 {
1850 struct radv_shader_module fs_m = {0};
1851 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1852 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1853 void *codes[MESA_SHADER_STAGES] = {0};
1854 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1855 struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1856 unsigned char hash[20], gs_copy_hash[20];
1857
1858 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1859 if (pStages[i]) {
1860 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1861 if (modules[i]->nir)
1862 _mesa_sha1_compute(modules[i]->nir->info.name,
1863 strlen(modules[i]->nir->info.name),
1864 modules[i]->sha1);
1865 }
1866 }
1867
1868 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1869 memcpy(gs_copy_hash, hash, 20);
1870 gs_copy_hash[0] ^= 1;
1871
1872 if (modules[MESA_SHADER_GEOMETRY]) {
1873 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1874 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1875 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1876 }
1877
1878 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1879 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1880 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1881 if (pipeline->shaders[i])
1882 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1883 }
1884 return;
1885 }
1886
1887 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1888 nir_builder fs_b;
1889 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1890 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1891 fs_m.nir = fs_b.shader;
1892 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1893 }
1894
1895 /* Determine first and last stage. */
1896 unsigned first = MESA_SHADER_STAGES;
1897 unsigned last = 0;
1898 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1899 if (!pStages[i])
1900 continue;
1901 if (first == MESA_SHADER_STAGES)
1902 first = i;
1903 last = i;
1904 }
1905
1906 int prev = -1;
1907 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1908 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1909
1910 if (!modules[i])
1911 continue;
1912
1913 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1914 stage ? stage->pName : "main", i,
1915 stage ? stage->pSpecializationInfo : NULL);
1916 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1917
1918 /* We don't want to alter meta shaders IR directly so clone it
1919 * first.
1920 */
1921 if (nir[i]->info.name) {
1922 nir[i] = nir_shader_clone(NULL, nir[i]);
1923 }
1924
1925 if (first != last) {
1926 nir_variable_mode mask = 0;
1927
1928 if (i != first)
1929 mask = mask | nir_var_shader_in;
1930
1931 if (i != last)
1932 mask = mask | nir_var_shader_out;
1933
1934 nir_lower_io_to_scalar_early(nir[i], mask);
1935 radv_optimize_nir(nir[i]);
1936 }
1937
1938 if (prev != -1) {
1939 nir_compact_varyings(nir[prev], nir[i], true);
1940 }
1941 prev = i;
1942 }
1943
1944 if (nir[MESA_SHADER_TESS_CTRL]) {
1945 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1946 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1947 }
1948
1949 radv_link_shaders(pipeline, nir);
1950
1951 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1952 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1953 nir_print_shader(nir[i], stderr);
1954 }
1955
1956 radv_fill_shader_keys(keys, &key, nir);
1957
1958 if (nir[MESA_SHADER_FRAGMENT]) {
1959 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1960 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1961 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1962 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1963 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1964 }
1965
1966 /* TODO: These are no longer used as keys we should refactor this */
1967 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1968 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1969 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1970 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1971 }
1972
1973 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1974 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1975 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1976 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1977 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1978 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1979 pipeline->layout,
1980 &key, &codes[MESA_SHADER_TESS_CTRL],
1981 &code_sizes[MESA_SHADER_TESS_CTRL]);
1982 }
1983 modules[MESA_SHADER_VERTEX] = NULL;
1984 }
1985
1986 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1987 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1988 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1989 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1990 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1991 pipeline->layout,
1992 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1993 &code_sizes[MESA_SHADER_GEOMETRY]);
1994 }
1995 modules[pre_stage] = NULL;
1996 }
1997
1998 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1999 if(modules[i] && !pipeline->shaders[i]) {
2000 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2001 pipeline->layout,
2002 keys + i, &codes[i],
2003 &code_sizes[i]);
2004 }
2005 }
2006
2007 if(modules[MESA_SHADER_GEOMETRY]) {
2008 void *gs_copy_code = NULL;
2009 unsigned gs_copy_code_size = 0;
2010 if (!pipeline->gs_copy_shader) {
2011 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2012 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2013 &gs_copy_code_size,
2014 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2015 }
2016
2017 if (pipeline->gs_copy_shader) {
2018 void *code[MESA_SHADER_STAGES] = {0};
2019 unsigned code_size[MESA_SHADER_STAGES] = {0};
2020 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2021
2022 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2023 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2024 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2025
2026 radv_pipeline_cache_insert_shaders(device, cache,
2027 gs_copy_hash,
2028 variants,
2029 (const void**)code,
2030 code_size);
2031 }
2032 free(gs_copy_code);
2033 }
2034
2035 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2036 (const void**)codes, code_sizes);
2037
2038 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2039 free(codes[i]);
2040 if (modules[i] && !pipeline->device->keep_shader_info)
2041 ralloc_free(nir[i]);
2042 }
2043
2044 if (fs_m.nir)
2045 ralloc_free(fs_m.nir);
2046 }
2047
2048 static uint32_t
2049 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2050 gl_shader_stage stage, enum chip_class chip_class)
2051 {
2052 bool has_gs = radv_pipeline_has_gs(pipeline);
2053 bool has_tess = radv_pipeline_has_tess(pipeline);
2054 switch (stage) {
2055 case MESA_SHADER_FRAGMENT:
2056 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2057 case MESA_SHADER_VERTEX:
2058 if (chip_class >= GFX9) {
2059 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2060 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2061 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2062 }
2063 if (has_tess)
2064 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2065 else
2066 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2067 case MESA_SHADER_GEOMETRY:
2068 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2069 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2070 case MESA_SHADER_COMPUTE:
2071 return R_00B900_COMPUTE_USER_DATA_0;
2072 case MESA_SHADER_TESS_CTRL:
2073 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2074 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2075 case MESA_SHADER_TESS_EVAL:
2076 if (chip_class >= GFX9) {
2077 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2078 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2079 }
2080 if (has_gs)
2081 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2082 else
2083 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2084 default:
2085 unreachable("unknown shader");
2086 }
2087 }
2088
2089 struct radv_bin_size_entry {
2090 unsigned bpp;
2091 VkExtent2D extent;
2092 };
2093
2094 static VkExtent2D
2095 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2096 {
2097 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2098 {
2099 /* One RB / SE */
2100 {
2101 /* One shader engine */
2102 { 0, {128, 128}},
2103 { 1, { 64, 128}},
2104 { 2, { 32, 128}},
2105 { 3, { 16, 128}},
2106 { 17, { 0, 0}},
2107 { UINT_MAX, { 0, 0}},
2108 },
2109 {
2110 /* Two shader engines */
2111 { 0, {128, 128}},
2112 { 2, { 64, 128}},
2113 { 3, { 32, 128}},
2114 { 5, { 16, 128}},
2115 { 17, { 0, 0}},
2116 { UINT_MAX, { 0, 0}},
2117 },
2118 {
2119 /* Four shader engines */
2120 { 0, {128, 128}},
2121 { 3, { 64, 128}},
2122 { 5, { 16, 128}},
2123 { 17, { 0, 0}},
2124 { UINT_MAX, { 0, 0}},
2125 },
2126 },
2127 {
2128 /* Two RB / SE */
2129 {
2130 /* One shader engine */
2131 { 0, {128, 128}},
2132 { 2, { 64, 128}},
2133 { 3, { 32, 128}},
2134 { 5, { 16, 128}},
2135 { 33, { 0, 0}},
2136 { UINT_MAX, { 0, 0}},
2137 },
2138 {
2139 /* Two shader engines */
2140 { 0, {128, 128}},
2141 { 3, { 64, 128}},
2142 { 5, { 32, 128}},
2143 { 9, { 16, 128}},
2144 { 33, { 0, 0}},
2145 { UINT_MAX, { 0, 0}},
2146 },
2147 {
2148 /* Four shader engines */
2149 { 0, {256, 256}},
2150 { 2, {128, 256}},
2151 { 3, {128, 128}},
2152 { 5, { 64, 128}},
2153 { 9, { 16, 128}},
2154 { 33, { 0, 0}},
2155 { UINT_MAX, { 0, 0}},
2156 },
2157 },
2158 {
2159 /* Four RB / SE */
2160 {
2161 /* One shader engine */
2162 { 0, {128, 256}},
2163 { 2, {128, 128}},
2164 { 3, { 64, 128}},
2165 { 5, { 32, 128}},
2166 { 9, { 16, 128}},
2167 { 33, { 0, 0}},
2168 { UINT_MAX, { 0, 0}},
2169 },
2170 {
2171 /* Two shader engines */
2172 { 0, {256, 256}},
2173 { 2, {128, 256}},
2174 { 3, {128, 128}},
2175 { 5, { 64, 128}},
2176 { 9, { 32, 128}},
2177 { 17, { 16, 128}},
2178 { 33, { 0, 0}},
2179 { UINT_MAX, { 0, 0}},
2180 },
2181 {
2182 /* Four shader engines */
2183 { 0, {256, 512}},
2184 { 2, {256, 256}},
2185 { 3, {128, 256}},
2186 { 5, {128, 128}},
2187 { 9, { 64, 128}},
2188 { 17, { 16, 128}},
2189 { 33, { 0, 0}},
2190 { UINT_MAX, { 0, 0}},
2191 },
2192 },
2193 };
2194 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2195 {
2196 // One RB / SE
2197 {
2198 // One shader engine
2199 { 0, {128, 256}},
2200 { 2, {128, 128}},
2201 { 4, { 64, 128}},
2202 { 7, { 32, 128}},
2203 { 13, { 16, 128}},
2204 { 49, { 0, 0}},
2205 { UINT_MAX, { 0, 0}},
2206 },
2207 {
2208 // Two shader engines
2209 { 0, {256, 256}},
2210 { 2, {128, 256}},
2211 { 4, {128, 128}},
2212 { 7, { 64, 128}},
2213 { 13, { 32, 128}},
2214 { 25, { 16, 128}},
2215 { 49, { 0, 0}},
2216 { UINT_MAX, { 0, 0}},
2217 },
2218 {
2219 // Four shader engines
2220 { 0, {256, 512}},
2221 { 2, {256, 256}},
2222 { 4, {128, 256}},
2223 { 7, {128, 128}},
2224 { 13, { 64, 128}},
2225 { 25, { 16, 128}},
2226 { 49, { 0, 0}},
2227 { UINT_MAX, { 0, 0}},
2228 },
2229 },
2230 {
2231 // Two RB / SE
2232 {
2233 // One shader engine
2234 { 0, {256, 256}},
2235 { 2, {128, 256}},
2236 { 4, {128, 128}},
2237 { 7, { 64, 128}},
2238 { 13, { 32, 128}},
2239 { 25, { 16, 128}},
2240 { 97, { 0, 0}},
2241 { UINT_MAX, { 0, 0}},
2242 },
2243 {
2244 // Two shader engines
2245 { 0, {256, 512}},
2246 { 2, {256, 256}},
2247 { 4, {128, 256}},
2248 { 7, {128, 128}},
2249 { 13, { 64, 128}},
2250 { 25, { 32, 128}},
2251 { 49, { 16, 128}},
2252 { 97, { 0, 0}},
2253 { UINT_MAX, { 0, 0}},
2254 },
2255 {
2256 // Four shader engines
2257 { 0, {512, 512}},
2258 { 2, {256, 512}},
2259 { 4, {256, 256}},
2260 { 7, {128, 256}},
2261 { 13, {128, 128}},
2262 { 25, { 64, 128}},
2263 { 49, { 16, 128}},
2264 { 97, { 0, 0}},
2265 { UINT_MAX, { 0, 0}},
2266 },
2267 },
2268 {
2269 // Four RB / SE
2270 {
2271 // One shader engine
2272 { 0, {256, 512}},
2273 { 2, {256, 256}},
2274 { 4, {128, 256}},
2275 { 7, {128, 128}},
2276 { 13, { 64, 128}},
2277 { 25, { 32, 128}},
2278 { 49, { 16, 128}},
2279 { UINT_MAX, { 0, 0}},
2280 },
2281 {
2282 // Two shader engines
2283 { 0, {512, 512}},
2284 { 2, {256, 512}},
2285 { 4, {256, 256}},
2286 { 7, {128, 256}},
2287 { 13, {128, 128}},
2288 { 25, { 64, 128}},
2289 { 49, { 32, 128}},
2290 { 97, { 16, 128}},
2291 { UINT_MAX, { 0, 0}},
2292 },
2293 {
2294 // Four shader engines
2295 { 0, {512, 512}},
2296 { 4, {256, 512}},
2297 { 7, {256, 256}},
2298 { 13, {128, 256}},
2299 { 25, {128, 128}},
2300 { 49, { 64, 128}},
2301 { 97, { 16, 128}},
2302 { UINT_MAX, { 0, 0}},
2303 },
2304 },
2305 };
2306
2307 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2308 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2309 VkExtent2D extent = {512, 512};
2310
2311 unsigned log_num_rb_per_se =
2312 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2313 pipeline->device->physical_device->rad_info.max_se);
2314 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2315
2316 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2317 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2318 unsigned effective_samples = total_samples;
2319 unsigned cb_target_mask = pipeline->graphics.blend.cb_target_mask;
2320 unsigned color_bytes_per_pixel = 0;
2321
2322 for (unsigned i = 0; i < subpass->color_count; i++) {
2323 if (!(cb_target_mask & (0xf << (i * 4))))
2324 continue;
2325
2326 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2327 continue;
2328
2329 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2330 color_bytes_per_pixel += vk_format_get_blocksize(format);
2331 }
2332
2333 /* MSAA images typically don't use all samples all the time. */
2334 if (effective_samples >= 2 && ps_iter_samples <= 1)
2335 effective_samples = 2;
2336 color_bytes_per_pixel *= effective_samples;
2337
2338 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2339 while(color_entry->bpp <= color_bytes_per_pixel)
2340 ++color_entry;
2341
2342 extent = color_entry->extent;
2343
2344 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2345 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2346
2347 /* Coefficients taken from AMDVLK */
2348 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2349 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2350 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2351
2352 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2353 while(ds_entry->bpp <= ds_bytes_per_pixel)
2354 ++ds_entry;
2355
2356 extent.width = MIN2(extent.width, ds_entry->extent.width);
2357 extent.height = MIN2(extent.height, ds_entry->extent.height);
2358 }
2359
2360 return extent;
2361 }
2362
2363 static void
2364 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2365 struct radv_pipeline *pipeline,
2366 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2367 {
2368 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2369 return;
2370
2371 uint32_t pa_sc_binner_cntl_0 =
2372 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2373 S_028C44_DISABLE_START_OF_PRIM(1);
2374 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2375
2376 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2377
2378 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2379 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2380 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2381
2382 switch (pipeline->device->physical_device->rad_info.family) {
2383 case CHIP_VEGA10:
2384 context_states_per_bin = 1;
2385 persistent_states_per_bin = 1;
2386 fpovs_per_batch = 63;
2387 break;
2388 case CHIP_RAVEN:
2389 context_states_per_bin = 6;
2390 persistent_states_per_bin = 32;
2391 fpovs_per_batch = 63;
2392 break;
2393 default:
2394 unreachable("unhandled family while determining binning state.");
2395 }
2396
2397 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2398 pa_sc_binner_cntl_0 =
2399 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2400 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2401 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2402 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2403 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2404 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2405 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2406 S_028C44_DISABLE_START_OF_PRIM(1) |
2407 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2408 S_028C44_OPTIMAL_BIN_SELECTION(1);
2409 }
2410
2411 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2412 pa_sc_binner_cntl_0);
2413 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2414 db_dfsm_control);
2415 }
2416
2417
2418 static void
2419 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2420 struct radv_pipeline *pipeline)
2421 {
2422 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
2423 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
2424 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
2425
2426 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
2427 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
2428 }
2429
2430 static void
2431 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2432 struct radv_pipeline *pipeline)
2433 {
2434 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2435 radeon_emit_array(cs, pipeline->graphics.blend.cb_blend_control,
2436 8);
2437 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
2438 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
2439
2440 if (pipeline->device->physical_device->has_rbplus) {
2441
2442 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2443 radeon_emit_array(cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
2444
2445 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2446 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2447 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2448 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2449 }
2450 }
2451
2452
2453 static void
2454 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2455 struct radv_pipeline *pipeline)
2456 {
2457 struct radv_raster_state *raster = &pipeline->graphics.raster;
2458
2459 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2460 raster->pa_cl_clip_cntl);
2461 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2462 raster->spi_interp_control);
2463 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2464 raster->pa_su_vtx_cntl);
2465 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2466 raster->pa_su_sc_mode_cntl);
2467 }
2468
2469
2470 static void
2471 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2472 struct radv_pipeline *pipeline)
2473 {
2474 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2475
2476 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2477 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2478 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2479
2480 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2481 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2482
2483 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2484 uint32_t offset;
2485 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2486 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2487 if (loc->sgpr_idx == -1)
2488 return;
2489 assert(loc->num_sgprs == 1);
2490 assert(!loc->indirect);
2491 switch (pipeline->graphics.ms.num_samples) {
2492 default:
2493 offset = 0;
2494 break;
2495 case 2:
2496 offset = 1;
2497 break;
2498 case 4:
2499 offset = 3;
2500 break;
2501 case 8:
2502 offset = 7;
2503 break;
2504 case 16:
2505 offset = 15;
2506 break;
2507 }
2508
2509 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2510 }
2511 }
2512
2513 static void
2514 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2515 struct radv_pipeline *pipeline,
2516 struct radv_shader_variant *shader)
2517 {
2518 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2519
2520 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2521 radeon_emit(cs, va >> 8);
2522 radeon_emit(cs, va >> 40);
2523 radeon_emit(cs, shader->rsrc1);
2524 radeon_emit(cs, shader->rsrc2);
2525
2526 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
2527 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2528 clip_dist_mask = outinfo->clip_dist_mask;
2529 cull_dist_mask = outinfo->cull_dist_mask;
2530 total_mask = clip_dist_mask | cull_dist_mask;
2531 bool misc_vec_ena = outinfo->writes_pointsize ||
2532 outinfo->writes_layer ||
2533 outinfo->writes_viewport_index;
2534
2535 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2536 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2537
2538 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2539 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2540 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2541 V_02870C_SPI_SHADER_4COMP :
2542 V_02870C_SPI_SHADER_NONE) |
2543 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2544 V_02870C_SPI_SHADER_4COMP :
2545 V_02870C_SPI_SHADER_NONE) |
2546 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2547 V_02870C_SPI_SHADER_4COMP :
2548 V_02870C_SPI_SHADER_NONE));
2549
2550 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2551 S_028818_VTX_W0_FMT(1) |
2552 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2553 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2554 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2555
2556 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2557 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2558 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2559 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2560 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2561 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2562 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2563 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2564 cull_dist_mask << 8 |
2565 clip_dist_mask);
2566
2567 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2568 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2569 outinfo->writes_viewport_index);
2570 }
2571
2572 static void
2573 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2574 struct radv_pipeline *pipeline,
2575 struct radv_shader_variant *shader)
2576 {
2577 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2578
2579 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2580 radeon_emit(cs, va >> 8);
2581 radeon_emit(cs, va >> 40);
2582 radeon_emit(cs, shader->rsrc1);
2583 radeon_emit(cs, shader->rsrc2);
2584 }
2585
2586 static void
2587 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2588 struct radv_pipeline *pipeline,
2589 struct radv_shader_variant *shader)
2590 {
2591 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2592 uint32_t rsrc2 = shader->rsrc2;
2593
2594 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2595 radeon_emit(cs, va >> 8);
2596 radeon_emit(cs, va >> 40);
2597
2598 rsrc2 |= S_00B52C_LDS_SIZE(pipeline->graphics.tess.lds_size);
2599 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2600 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2601 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2602
2603 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2604 radeon_emit(cs, shader->rsrc1);
2605 radeon_emit(cs, rsrc2);
2606 }
2607
2608 static void
2609 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2610 struct radv_pipeline *pipeline,
2611 struct radv_shader_variant *shader)
2612 {
2613 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2614
2615 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2616 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2617 radeon_emit(cs, va >> 8);
2618 radeon_emit(cs, va >> 40);
2619
2620 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2621 radeon_emit(cs, shader->rsrc1);
2622 radeon_emit(cs, shader->rsrc2 |
2623 S_00B42C_LDS_SIZE(pipeline->graphics.tess.lds_size));
2624 } else {
2625 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2626 radeon_emit(cs, va >> 8);
2627 radeon_emit(cs, va >> 40);
2628 radeon_emit(cs, shader->rsrc1);
2629 radeon_emit(cs, shader->rsrc2);
2630 }
2631 }
2632
2633 static void
2634 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2635 struct radv_pipeline *pipeline)
2636 {
2637 struct radv_shader_variant *vs;
2638
2639 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
2640
2641 /* Skip shaders merged into HS/GS */
2642 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2643 if (!vs)
2644 return;
2645
2646 if (vs->info.vs.as_ls)
2647 radv_pipeline_generate_hw_ls(cs, pipeline, vs);
2648 else if (vs->info.vs.as_es)
2649 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2650 else
2651 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2652 }
2653
2654 static void
2655 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2656 struct radv_pipeline *pipeline)
2657 {
2658 if (!radv_pipeline_has_tess(pipeline))
2659 return;
2660
2661 struct radv_shader_variant *tes, *tcs;
2662
2663 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2664 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2665
2666 if (tes) {
2667 if (tes->info.tes.as_es)
2668 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2669 else
2670 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2671 }
2672
2673 radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
2674
2675 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2676 pipeline->graphics.tess.tf_param);
2677
2678 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2679 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2680 pipeline->graphics.tess.ls_hs_config);
2681 else
2682 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2683 pipeline->graphics.tess.ls_hs_config);
2684
2685 struct ac_userdata_info *loc;
2686
2687 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
2688 if (loc->sgpr_idx != -1) {
2689 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
2690 assert(loc->num_sgprs == 4);
2691 assert(!loc->indirect);
2692 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
2693 radeon_emit(cs, pipeline->graphics.tess.offchip_layout);
2694 radeon_emit(cs, pipeline->graphics.tess.tcs_out_offsets);
2695 radeon_emit(cs, pipeline->graphics.tess.tcs_out_layout |
2696 pipeline->graphics.tess.num_tcs_input_cp << 26);
2697 radeon_emit(cs, pipeline->graphics.tess.tcs_in_layout);
2698 }
2699
2700 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
2701 if (loc->sgpr_idx != -1) {
2702 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
2703 assert(loc->num_sgprs == 1);
2704 assert(!loc->indirect);
2705
2706 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2707 pipeline->graphics.tess.offchip_layout);
2708 }
2709
2710 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
2711 if (loc->sgpr_idx != -1) {
2712 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
2713 assert(loc->num_sgprs == 1);
2714 assert(!loc->indirect);
2715
2716 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2717 pipeline->graphics.tess.tcs_in_layout);
2718 }
2719 }
2720
2721 static void
2722 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2723 struct radv_pipeline *pipeline)
2724 {
2725 struct radv_shader_variant *gs;
2726 uint64_t va;
2727
2728 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
2729
2730 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2731 if (!gs)
2732 return;
2733
2734 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2735
2736 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2737 radeon_emit(cs, gsvs_itemsize);
2738 radeon_emit(cs, gsvs_itemsize);
2739 radeon_emit(cs, gsvs_itemsize);
2740
2741 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2742
2743 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2744
2745 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2746 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2747 radeon_emit(cs, gs_vert_itemsize >> 2);
2748 radeon_emit(cs, 0);
2749 radeon_emit(cs, 0);
2750 radeon_emit(cs, 0);
2751
2752 uint32_t gs_num_invocations = gs->info.gs.invocations;
2753 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2754 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2755 S_028B90_ENABLE(gs_num_invocations > 0));
2756
2757 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2758 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
2759
2760 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2761
2762 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2763 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2764 radeon_emit(cs, va >> 8);
2765 radeon_emit(cs, va >> 40);
2766
2767 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2768 radeon_emit(cs, gs->rsrc1);
2769 radeon_emit(cs, gs->rsrc2 |
2770 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
2771
2772 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
2773 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
2774 } else {
2775 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2776 radeon_emit(cs, va >> 8);
2777 radeon_emit(cs, va >> 40);
2778 radeon_emit(cs, gs->rsrc1);
2779 radeon_emit(cs, gs->rsrc2);
2780 }
2781
2782 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2783
2784 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2785 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
2786 if (loc->sgpr_idx != -1) {
2787 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
2788 uint32_t num_entries = 64;
2789 bool is_vi = pipeline->device->physical_device->rad_info.chip_class >= VI;
2790
2791 if (is_vi)
2792 num_entries *= stride;
2793
2794 stride = S_008F04_STRIDE(stride);
2795 radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
2796 radeon_emit(cs, stride);
2797 radeon_emit(cs, num_entries);
2798 }
2799 }
2800
2801
2802 static void
2803 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2804 struct radv_pipeline *pipeline)
2805 {
2806 struct radv_shader_variant *ps;
2807 uint64_t va;
2808 struct radv_blend_state *blend = &pipeline->graphics.blend;
2809 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2810
2811 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2812 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2813
2814 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2815 radeon_emit(cs, va >> 8);
2816 radeon_emit(cs, va >> 40);
2817 radeon_emit(cs, ps->rsrc1);
2818 radeon_emit(cs, ps->rsrc2);
2819
2820 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2821 pipeline->graphics.db_shader_control);
2822
2823 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2824 ps->config.spi_ps_input_ena);
2825
2826 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2827 ps->config.spi_ps_input_addr);
2828
2829 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2830 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2831
2832 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2833
2834 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2835 pipeline->graphics.shader_z_format);
2836
2837 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2838
2839 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2840 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2841
2842 if (pipeline->device->dfsm_allowed) {
2843 /* optimise this? */
2844 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2845 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2846 }
2847
2848 if (pipeline->graphics.ps_input_cntl_num) {
2849 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
2850 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
2851 radeon_emit(cs, pipeline->graphics.ps_input_cntl[i]);
2852 }
2853 }
2854 }
2855
2856 static void
2857 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2858 struct radv_pipeline *pipeline)
2859 {
2860 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2861 return;
2862
2863 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2864 pipeline->graphics.vtx_reuse_depth);
2865 }
2866
2867 static void
2868 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2869 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2870 {
2871 pipeline->cs.buf = malloc(4 * 256);
2872 pipeline->cs.max_dw = 256;
2873
2874 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline);
2875 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline);
2876 radv_pipeline_generate_raster_state(&pipeline->cs, pipeline);
2877 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2878 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline);
2879 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline);
2880 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline);
2881 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2882 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2883 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2884
2885 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2886 S_0286E8_WAVES(pipeline->max_waves) |
2887 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2888
2889 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
2890
2891 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2892 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
2893 } else {
2894 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
2895 }
2896 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
2897
2898 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, pipeline->graphics.pa_sc_cliprect_rule);
2899
2900 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2901 }
2902
2903 static VkResult
2904 radv_pipeline_init(struct radv_pipeline *pipeline,
2905 struct radv_device *device,
2906 struct radv_pipeline_cache *cache,
2907 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2908 const struct radv_graphics_pipeline_create_info *extra,
2909 const VkAllocationCallbacks *alloc)
2910 {
2911 VkResult result;
2912 bool has_view_index = false;
2913
2914 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2915 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2916 if (subpass->view_mask)
2917 has_view_index = true;
2918 if (alloc == NULL)
2919 alloc = &device->alloc;
2920
2921 pipeline->device = device;
2922 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2923 assert(pipeline->layout);
2924
2925 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2926
2927 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2928 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2929 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2930 pStages[stage] = &pCreateInfo->pStages[i];
2931 }
2932
2933 radv_create_shaders(pipeline, device, cache,
2934 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, has_view_index),
2935 pStages);
2936
2937 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
2938 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2939 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2940 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2941 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2942 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2943
2944 if (radv_pipeline_has_gs(pipeline)) {
2945 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2946 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2947 } else {
2948 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2949 }
2950 if (extra && extra->use_rectlist) {
2951 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2952 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2953 pipeline->graphics.can_use_guardband = true;
2954 }
2955 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2956 /* prim vertex count will need TESS changes */
2957 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2958
2959 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2960
2961 /* Ensure that some export memory is always allocated, for two reasons:
2962 *
2963 * 1) Correctness: The hardware ignores the EXEC mask if no export
2964 * memory is allocated, so KILL and alpha test do not work correctly
2965 * without this.
2966 * 2) Performance: Every shader needs at least a NULL export, even when
2967 * it writes no color/depth output. The NULL export instruction
2968 * stalls without this setting.
2969 *
2970 * Don't add this to CB_SHADER_MASK.
2971 */
2972 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2973 if (!pipeline->graphics.blend.spi_shader_col_format) {
2974 if (!ps->info.fs.writes_z &&
2975 !ps->info.fs.writes_stencil &&
2976 !ps->info.fs.writes_sample_mask)
2977 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2978 }
2979
2980 unsigned z_order;
2981 pipeline->graphics.db_shader_control = 0;
2982 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2983 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2984 else
2985 z_order = V_02880C_LATE_Z;
2986
2987 pipeline->graphics.db_shader_control =
2988 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2989 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2990 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2991 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2992 S_02880C_Z_ORDER(z_order) |
2993 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2994 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2995 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory);
2996
2997 if (pipeline->device->physical_device->has_rbplus)
2998 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2999
3000 unsigned shader_z_format =
3001 ac_get_spi_shader_z_format(ps->info.fs.writes_z,
3002 ps->info.fs.writes_stencil,
3003 ps->info.fs.writes_sample_mask);
3004 pipeline->graphics.shader_z_format = shader_z_format;
3005
3006 calculate_vgt_gs_mode(pipeline);
3007 calculate_ps_inputs(pipeline);
3008
3009 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3010 if (pipeline->shaders[i]) {
3011 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3012 }
3013 }
3014
3015 uint32_t stages = 0;
3016 if (radv_pipeline_has_tess(pipeline)) {
3017 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3018 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3019
3020 if (radv_pipeline_has_gs(pipeline))
3021 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3022 S_028B54_GS_EN(1) |
3023 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3024 else
3025 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3026
3027 } else if (radv_pipeline_has_gs(pipeline))
3028 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3029 S_028B54_GS_EN(1) |
3030 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3031
3032 if (device->physical_device->rad_info.chip_class >= GFX9)
3033 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3034
3035 pipeline->graphics.vgt_shader_stages_en = stages;
3036
3037 if (radv_pipeline_has_gs(pipeline)) {
3038 calculate_gs_ring_sizes(pipeline);
3039 if (device->physical_device->rad_info.chip_class >= GFX9)
3040 calculate_gfx9_gs_info(pCreateInfo, pipeline);
3041 }
3042
3043 if (radv_pipeline_has_tess(pipeline)) {
3044 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
3045 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3046 pipeline->graphics.prim_vertex_count.incr = 1;
3047 }
3048 calculate_tess_state(pipeline, pCreateInfo);
3049 }
3050
3051 if (radv_pipeline_has_tess(pipeline))
3052 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
3053 else if (radv_pipeline_has_gs(pipeline))
3054 pipeline->graphics.primgroup_size = 64;
3055 else
3056 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
3057
3058 pipeline->graphics.partial_es_wave = false;
3059 if (pipeline->device->has_distributed_tess) {
3060 if (radv_pipeline_has_gs(pipeline)) {
3061 if (device->physical_device->rad_info.chip_class <= VI)
3062 pipeline->graphics.partial_es_wave = true;
3063 }
3064 }
3065 /* GS requirement. */
3066 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
3067 pipeline->graphics.partial_es_wave = true;
3068
3069 pipeline->graphics.wd_switch_on_eop = false;
3070 if (device->physical_device->rad_info.chip_class >= CIK) {
3071 unsigned prim = pipeline->graphics.prim;
3072 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3073 * 4 shader engines. Set 1 to pass the assertion below.
3074 * The other cases are hardware requirements. */
3075 if (device->physical_device->rad_info.max_se < 4 ||
3076 prim == V_008958_DI_PT_POLYGON ||
3077 prim == V_008958_DI_PT_LINELOOP ||
3078 prim == V_008958_DI_PT_TRIFAN ||
3079 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3080 (pipeline->graphics.prim_restart_enable &&
3081 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3082 (prim != V_008958_DI_PT_POINTLIST &&
3083 prim != V_008958_DI_PT_LINESTRIP &&
3084 prim != V_008958_DI_PT_TRISTRIP))))
3085 pipeline->graphics.wd_switch_on_eop = true;
3086 }
3087
3088 pipeline->graphics.ia_switch_on_eoi = false;
3089 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
3090 pipeline->graphics.ia_switch_on_eoi = true;
3091 if (radv_pipeline_has_gs(pipeline) &&
3092 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3093 pipeline->graphics.ia_switch_on_eoi = true;
3094 if (radv_pipeline_has_tess(pipeline)) {
3095 /* SWITCH_ON_EOI must be set if PrimID is used. */
3096 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3097 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3098 pipeline->graphics.ia_switch_on_eoi = true;
3099 }
3100
3101 pipeline->graphics.partial_vs_wave = false;
3102 if (radv_pipeline_has_tess(pipeline)) {
3103 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3104 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3105 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3106 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3107 radv_pipeline_has_gs(pipeline))
3108 pipeline->graphics.partial_vs_wave = true;
3109 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3110 if (device->has_distributed_tess) {
3111 if (radv_pipeline_has_gs(pipeline)) {
3112 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3113 device->physical_device->rad_info.family == CHIP_FIJI ||
3114 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3115 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3116 device->physical_device->rad_info.family == CHIP_POLARIS12)
3117 pipeline->graphics.partial_vs_wave = true;
3118 } else {
3119 pipeline->graphics.partial_vs_wave = true;
3120 }
3121 }
3122 }
3123
3124 pipeline->graphics.base_ia_multi_vgt_param =
3125 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
3126 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3127 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3128 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3129 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3130
3131 const VkPipelineVertexInputStateCreateInfo *vi_info =
3132 pCreateInfo->pVertexInputState;
3133 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3134
3135 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3136 const VkVertexInputAttributeDescription *desc =
3137 &vi_info->pVertexAttributeDescriptions[i];
3138 unsigned loc = desc->location;
3139 const struct vk_format_description *format_desc;
3140 int first_non_void;
3141 uint32_t num_format, data_format;
3142 format_desc = vk_format_description(desc->format);
3143 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3144
3145 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3146 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3147
3148 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3149 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3150 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3151 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3152 S_008F0C_NUM_FORMAT(num_format) |
3153 S_008F0C_DATA_FORMAT(data_format);
3154 velems->format_size[loc] = format_desc->block.bits / 8;
3155 velems->offset[loc] = desc->offset;
3156 velems->binding[loc] = desc->binding;
3157 velems->count = MAX2(velems->count, loc + 1);
3158 }
3159
3160 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3161 const VkVertexInputBindingDescription *desc =
3162 &vi_info->pVertexBindingDescriptions[i];
3163
3164 pipeline->binding_stride[desc->binding] = desc->stride;
3165 }
3166
3167 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3168 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3169
3170 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3171 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3172 if (loc->sgpr_idx != -1) {
3173 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3174 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3175 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3176 pipeline->graphics.vtx_emit_num = 3;
3177 else
3178 pipeline->graphics.vtx_emit_num = 2;
3179 }
3180
3181 pipeline->graphics.vtx_reuse_depth = 30;
3182 if (radv_pipeline_has_tess(pipeline) &&
3183 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3184 pipeline->graphics.vtx_reuse_depth = 14;
3185 }
3186
3187 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
3188 radv_dump_pipeline_stats(device, pipeline);
3189 }
3190
3191 result = radv_pipeline_scratch_init(device, pipeline);
3192 radv_pipeline_generate_pm4(pipeline, pCreateInfo);
3193
3194 return result;
3195 }
3196
3197 VkResult
3198 radv_graphics_pipeline_create(
3199 VkDevice _device,
3200 VkPipelineCache _cache,
3201 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3202 const struct radv_graphics_pipeline_create_info *extra,
3203 const VkAllocationCallbacks *pAllocator,
3204 VkPipeline *pPipeline)
3205 {
3206 RADV_FROM_HANDLE(radv_device, device, _device);
3207 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3208 struct radv_pipeline *pipeline;
3209 VkResult result;
3210
3211 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3212 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3213 if (pipeline == NULL)
3214 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3215
3216 result = radv_pipeline_init(pipeline, device, cache,
3217 pCreateInfo, extra, pAllocator);
3218 if (result != VK_SUCCESS) {
3219 radv_pipeline_destroy(device, pipeline, pAllocator);
3220 return result;
3221 }
3222
3223 *pPipeline = radv_pipeline_to_handle(pipeline);
3224
3225 return VK_SUCCESS;
3226 }
3227
3228 VkResult radv_CreateGraphicsPipelines(
3229 VkDevice _device,
3230 VkPipelineCache pipelineCache,
3231 uint32_t count,
3232 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3233 const VkAllocationCallbacks* pAllocator,
3234 VkPipeline* pPipelines)
3235 {
3236 VkResult result = VK_SUCCESS;
3237 unsigned i = 0;
3238
3239 for (; i < count; i++) {
3240 VkResult r;
3241 r = radv_graphics_pipeline_create(_device,
3242 pipelineCache,
3243 &pCreateInfos[i],
3244 NULL, pAllocator, &pPipelines[i]);
3245 if (r != VK_SUCCESS) {
3246 result = r;
3247 pPipelines[i] = VK_NULL_HANDLE;
3248 }
3249 }
3250
3251 return result;
3252 }
3253
3254
3255 static void
3256 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3257 {
3258 struct radv_shader_variant *compute_shader;
3259 struct radv_device *device = pipeline->device;
3260 unsigned compute_resource_limits;
3261 unsigned waves_per_threadgroup;
3262 uint64_t va;
3263
3264 pipeline->cs.buf = malloc(20 * 4);
3265 pipeline->cs.max_dw = 20;
3266
3267 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3268 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3269
3270 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3271 radeon_emit(&pipeline->cs, va >> 8);
3272 radeon_emit(&pipeline->cs, va >> 40);
3273
3274 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3275 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3276 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3277
3278 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3279 S_00B860_WAVES(pipeline->max_waves) |
3280 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3281
3282 /* Calculate best compute resource limits. */
3283 waves_per_threadgroup =
3284 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3285 compute_shader->info.cs.block_size[1] *
3286 compute_shader->info.cs.block_size[2], 64);
3287 compute_resource_limits =
3288 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3289
3290 if (device->physical_device->rad_info.chip_class >= CIK) {
3291 unsigned num_cu_per_se =
3292 device->physical_device->rad_info.num_good_compute_units /
3293 device->physical_device->rad_info.max_se;
3294
3295 /* Force even distribution on all SIMDs in CU if the workgroup
3296 * size is 64. This has shown some good improvements if # of
3297 * CUs per SE is not a multiple of 4.
3298 */
3299 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3300 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3301 }
3302
3303 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3304 compute_resource_limits);
3305
3306 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3307 radeon_emit(&pipeline->cs,
3308 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3309 radeon_emit(&pipeline->cs,
3310 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3311 radeon_emit(&pipeline->cs,
3312 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3313
3314 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3315 }
3316
3317 static VkResult radv_compute_pipeline_create(
3318 VkDevice _device,
3319 VkPipelineCache _cache,
3320 const VkComputePipelineCreateInfo* pCreateInfo,
3321 const VkAllocationCallbacks* pAllocator,
3322 VkPipeline* pPipeline)
3323 {
3324 RADV_FROM_HANDLE(radv_device, device, _device);
3325 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3326 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3327 struct radv_pipeline *pipeline;
3328 VkResult result;
3329
3330 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3331 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3332 if (pipeline == NULL)
3333 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3334
3335 pipeline->device = device;
3336 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3337 assert(pipeline->layout);
3338
3339 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3340 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3341
3342 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3343 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3344 result = radv_pipeline_scratch_init(device, pipeline);
3345 if (result != VK_SUCCESS) {
3346 radv_pipeline_destroy(device, pipeline, pAllocator);
3347 return result;
3348 }
3349
3350 radv_compute_generate_pm4(pipeline);
3351
3352 *pPipeline = radv_pipeline_to_handle(pipeline);
3353
3354 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
3355 radv_dump_pipeline_stats(device, pipeline);
3356 }
3357 return VK_SUCCESS;
3358 }
3359
3360 VkResult radv_CreateComputePipelines(
3361 VkDevice _device,
3362 VkPipelineCache pipelineCache,
3363 uint32_t count,
3364 const VkComputePipelineCreateInfo* pCreateInfos,
3365 const VkAllocationCallbacks* pAllocator,
3366 VkPipeline* pPipelines)
3367 {
3368 VkResult result = VK_SUCCESS;
3369
3370 unsigned i = 0;
3371 for (; i < count; i++) {
3372 VkResult r;
3373 r = radv_compute_pipeline_create(_device, pipelineCache,
3374 &pCreateInfos[i],
3375 pAllocator, &pPipelines[i]);
3376 if (r != VK_SUCCESS) {
3377 result = r;
3378 pPipelines[i] = VK_NULL_HANDLE;
3379 }
3380 }
3381
3382 return result;
3383 }