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radv: add multisample Z optimisation from amdvlk
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "vk_util.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40
41 #include "sid.h"
42 #include "gfx9d.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49 #include "ac_shader_util.h"
50
51 static void
52 radv_pipeline_destroy(struct radv_device *device,
53 struct radv_pipeline *pipeline,
54 const VkAllocationCallbacks* allocator)
55 {
56 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
57 if (pipeline->shaders[i])
58 radv_shader_variant_destroy(device, pipeline->shaders[i]);
59
60 if (pipeline->gs_copy_shader)
61 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
62
63 vk_free2(&device->alloc, allocator, pipeline);
64 }
65
66 void radv_DestroyPipeline(
67 VkDevice _device,
68 VkPipeline _pipeline,
69 const VkAllocationCallbacks* pAllocator)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
73
74 if (!_pipeline)
75 return;
76
77 radv_pipeline_destroy(device, pipeline, pAllocator);
78 }
79
80 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
81 {
82 int i;
83
84 for (i = 0; i < MESA_SHADER_STAGES; i++) {
85 if (!pipeline->shaders[i])
86 continue;
87
88 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
89 }
90 }
91
92 static uint32_t get_hash_flags(struct radv_device *device)
93 {
94 uint32_t hash_flags = 0;
95
96 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
97 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
98 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
99 hash_flags |= RADV_HASH_SHADER_SISCHED;
100 return hash_flags;
101 }
102
103 static VkResult
104 radv_pipeline_scratch_init(struct radv_device *device,
105 struct radv_pipeline *pipeline)
106 {
107 unsigned scratch_bytes_per_wave = 0;
108 unsigned max_waves = 0;
109 unsigned min_waves = 1;
110
111 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
112 if (pipeline->shaders[i]) {
113 unsigned max_stage_waves = device->scratch_waves;
114
115 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
116 pipeline->shaders[i]->config.scratch_bytes_per_wave);
117
118 max_stage_waves = MIN2(max_stage_waves,
119 4 * device->physical_device->rad_info.num_good_compute_units *
120 (256 / pipeline->shaders[i]->config.num_vgprs));
121 max_waves = MAX2(max_waves, max_stage_waves);
122 }
123 }
124
125 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
126 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
127 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
128 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
129 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
130 }
131
132 if (scratch_bytes_per_wave)
133 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
134
135 if (scratch_bytes_per_wave && max_waves < min_waves) {
136 /* Not really true at this moment, but will be true on first
137 * execution. Avoid having hanging shaders. */
138 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
139 }
140 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
141 pipeline->max_waves = max_waves;
142 return VK_SUCCESS;
143 }
144
145 static uint32_t si_translate_blend_function(VkBlendOp op)
146 {
147 switch (op) {
148 case VK_BLEND_OP_ADD:
149 return V_028780_COMB_DST_PLUS_SRC;
150 case VK_BLEND_OP_SUBTRACT:
151 return V_028780_COMB_SRC_MINUS_DST;
152 case VK_BLEND_OP_REVERSE_SUBTRACT:
153 return V_028780_COMB_DST_MINUS_SRC;
154 case VK_BLEND_OP_MIN:
155 return V_028780_COMB_MIN_DST_SRC;
156 case VK_BLEND_OP_MAX:
157 return V_028780_COMB_MAX_DST_SRC;
158 default:
159 return 0;
160 }
161 }
162
163 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
164 {
165 switch (factor) {
166 case VK_BLEND_FACTOR_ZERO:
167 return V_028780_BLEND_ZERO;
168 case VK_BLEND_FACTOR_ONE:
169 return V_028780_BLEND_ONE;
170 case VK_BLEND_FACTOR_SRC_COLOR:
171 return V_028780_BLEND_SRC_COLOR;
172 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
173 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
174 case VK_BLEND_FACTOR_DST_COLOR:
175 return V_028780_BLEND_DST_COLOR;
176 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
177 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
178 case VK_BLEND_FACTOR_SRC_ALPHA:
179 return V_028780_BLEND_SRC_ALPHA;
180 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
181 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
182 case VK_BLEND_FACTOR_DST_ALPHA:
183 return V_028780_BLEND_DST_ALPHA;
184 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
185 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
186 case VK_BLEND_FACTOR_CONSTANT_COLOR:
187 return V_028780_BLEND_CONSTANT_COLOR;
188 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
189 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
190 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
191 return V_028780_BLEND_CONSTANT_ALPHA;
192 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
193 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
194 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
195 return V_028780_BLEND_SRC_ALPHA_SATURATE;
196 case VK_BLEND_FACTOR_SRC1_COLOR:
197 return V_028780_BLEND_SRC1_COLOR;
198 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
199 return V_028780_BLEND_INV_SRC1_COLOR;
200 case VK_BLEND_FACTOR_SRC1_ALPHA:
201 return V_028780_BLEND_SRC1_ALPHA;
202 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
203 return V_028780_BLEND_INV_SRC1_ALPHA;
204 default:
205 return 0;
206 }
207 }
208
209 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
210 {
211 switch (op) {
212 case VK_BLEND_OP_ADD:
213 return V_028760_OPT_COMB_ADD;
214 case VK_BLEND_OP_SUBTRACT:
215 return V_028760_OPT_COMB_SUBTRACT;
216 case VK_BLEND_OP_REVERSE_SUBTRACT:
217 return V_028760_OPT_COMB_REVSUBTRACT;
218 case VK_BLEND_OP_MIN:
219 return V_028760_OPT_COMB_MIN;
220 case VK_BLEND_OP_MAX:
221 return V_028760_OPT_COMB_MAX;
222 default:
223 return V_028760_OPT_COMB_BLEND_DISABLED;
224 }
225 }
226
227 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
228 {
229 switch (factor) {
230 case VK_BLEND_FACTOR_ZERO:
231 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
232 case VK_BLEND_FACTOR_ONE:
233 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
234 case VK_BLEND_FACTOR_SRC_COLOR:
235 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
236 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
237 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
238 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
239 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
240 case VK_BLEND_FACTOR_SRC_ALPHA:
241 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
242 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
243 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
244 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
245 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
246 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
247 default:
248 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
249 }
250 }
251
252 /**
253 * Get rid of DST in the blend factors by commuting the operands:
254 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
255 */
256 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
257 unsigned *dst_factor, unsigned expected_dst,
258 unsigned replacement_src)
259 {
260 if (*src_factor == expected_dst &&
261 *dst_factor == VK_BLEND_FACTOR_ZERO) {
262 *src_factor = VK_BLEND_FACTOR_ZERO;
263 *dst_factor = replacement_src;
264
265 /* Commuting the operands requires reversing subtractions. */
266 if (*func == VK_BLEND_OP_SUBTRACT)
267 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
268 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
269 *func = VK_BLEND_OP_SUBTRACT;
270 }
271 }
272
273 static bool si_blend_factor_uses_dst(unsigned factor)
274 {
275 return factor == VK_BLEND_FACTOR_DST_COLOR ||
276 factor == VK_BLEND_FACTOR_DST_ALPHA ||
277 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
278 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
279 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
280 }
281
282 static bool is_dual_src(VkBlendFactor factor)
283 {
284 switch (factor) {
285 case VK_BLEND_FACTOR_SRC1_COLOR:
286 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
287 case VK_BLEND_FACTOR_SRC1_ALPHA:
288 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
289 return true;
290 default:
291 return false;
292 }
293 }
294
295 static unsigned si_choose_spi_color_format(VkFormat vk_format,
296 bool blend_enable,
297 bool blend_need_alpha)
298 {
299 const struct vk_format_description *desc = vk_format_description(vk_format);
300 unsigned format, ntype, swap;
301
302 /* Alpha is needed for alpha-to-coverage.
303 * Blending may be with or without alpha.
304 */
305 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
306 unsigned alpha = 0; /* exports alpha, but may not support blending */
307 unsigned blend = 0; /* supports blending, but may not export alpha */
308 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
309
310 format = radv_translate_colorformat(vk_format);
311 ntype = radv_translate_color_numformat(vk_format, desc,
312 vk_format_get_first_non_void_channel(vk_format));
313 swap = radv_translate_colorswap(vk_format, false);
314
315 /* Choose the SPI color formats. These are required values for Stoney/RB+.
316 * Other chips have multiple choices, though they are not necessarily better.
317 */
318 switch (format) {
319 case V_028C70_COLOR_5_6_5:
320 case V_028C70_COLOR_1_5_5_5:
321 case V_028C70_COLOR_5_5_5_1:
322 case V_028C70_COLOR_4_4_4_4:
323 case V_028C70_COLOR_10_11_11:
324 case V_028C70_COLOR_11_11_10:
325 case V_028C70_COLOR_8:
326 case V_028C70_COLOR_8_8:
327 case V_028C70_COLOR_8_8_8_8:
328 case V_028C70_COLOR_10_10_10_2:
329 case V_028C70_COLOR_2_10_10_10:
330 if (ntype == V_028C70_NUMBER_UINT)
331 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
332 else if (ntype == V_028C70_NUMBER_SINT)
333 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
334 else
335 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
336 break;
337
338 case V_028C70_COLOR_16:
339 case V_028C70_COLOR_16_16:
340 case V_028C70_COLOR_16_16_16_16:
341 if (ntype == V_028C70_NUMBER_UNORM ||
342 ntype == V_028C70_NUMBER_SNORM) {
343 /* UNORM16 and SNORM16 don't support blending */
344 if (ntype == V_028C70_NUMBER_UNORM)
345 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
346 else
347 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
348
349 /* Use 32 bits per channel for blending. */
350 if (format == V_028C70_COLOR_16) {
351 if (swap == V_028C70_SWAP_STD) { /* R */
352 blend = V_028714_SPI_SHADER_32_R;
353 blend_alpha = V_028714_SPI_SHADER_32_AR;
354 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
355 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
356 else
357 assert(0);
358 } else if (format == V_028C70_COLOR_16_16) {
359 if (swap == V_028C70_SWAP_STD) { /* RG */
360 blend = V_028714_SPI_SHADER_32_GR;
361 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
362 } else if (swap == V_028C70_SWAP_ALT) /* RA */
363 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
364 else
365 assert(0);
366 } else /* 16_16_16_16 */
367 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
368 } else if (ntype == V_028C70_NUMBER_UINT)
369 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
370 else if (ntype == V_028C70_NUMBER_SINT)
371 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
372 else if (ntype == V_028C70_NUMBER_FLOAT)
373 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
374 else
375 assert(0);
376 break;
377
378 case V_028C70_COLOR_32:
379 if (swap == V_028C70_SWAP_STD) { /* R */
380 blend = normal = V_028714_SPI_SHADER_32_R;
381 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
382 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
383 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
384 else
385 assert(0);
386 break;
387
388 case V_028C70_COLOR_32_32:
389 if (swap == V_028C70_SWAP_STD) { /* RG */
390 blend = normal = V_028714_SPI_SHADER_32_GR;
391 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
392 } else if (swap == V_028C70_SWAP_ALT) /* RA */
393 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
394 else
395 assert(0);
396 break;
397
398 case V_028C70_COLOR_32_32_32_32:
399 case V_028C70_COLOR_8_24:
400 case V_028C70_COLOR_24_8:
401 case V_028C70_COLOR_X24_8_32_FLOAT:
402 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
403 break;
404
405 default:
406 unreachable("unhandled blend format");
407 }
408
409 if (blend_enable && blend_need_alpha)
410 return blend_alpha;
411 else if(blend_need_alpha)
412 return alpha;
413 else if(blend_enable)
414 return blend;
415 else
416 return normal;
417 }
418
419 static void
420 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
421 const VkGraphicsPipelineCreateInfo *pCreateInfo,
422 uint32_t blend_enable,
423 uint32_t blend_need_alpha,
424 bool single_cb_enable,
425 bool blend_mrt0_is_dual_src)
426 {
427 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
428 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
429 struct radv_blend_state *blend = &pipeline->graphics.blend;
430 unsigned col_format = 0;
431
432 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
433 unsigned cf;
434
435 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
436 cf = V_028714_SPI_SHADER_ZERO;
437 } else {
438 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
439
440 cf = si_choose_spi_color_format(attachment->format,
441 blend_enable & (1 << i),
442 blend_need_alpha & (1 << i));
443 }
444
445 col_format |= cf << (4 * i);
446 }
447
448 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
449
450 if (blend_mrt0_is_dual_src)
451 col_format |= (col_format & 0xf) << 4;
452 blend->spi_shader_col_format = col_format;
453 }
454
455 static bool
456 format_is_int8(VkFormat format)
457 {
458 const struct vk_format_description *desc = vk_format_description(format);
459 int channel = vk_format_get_first_non_void_channel(format);
460
461 return channel >= 0 && desc->channel[channel].pure_integer &&
462 desc->channel[channel].size == 8;
463 }
464
465 static bool
466 format_is_int10(VkFormat format)
467 {
468 const struct vk_format_description *desc = vk_format_description(format);
469
470 if (desc->nr_channels != 4)
471 return false;
472 for (unsigned i = 0; i < 4; i++) {
473 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
474 return true;
475 }
476 return false;
477 }
478
479 unsigned radv_format_meta_fs_key(VkFormat format)
480 {
481 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
482 bool is_int8 = format_is_int8(format);
483 bool is_int10 = format_is_int10(format);
484
485 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
486 }
487
488 static void
489 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
490 unsigned *is_int8, unsigned *is_int10)
491 {
492 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
493 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
494 *is_int8 = 0;
495 *is_int10 = 0;
496
497 for (unsigned i = 0; i < subpass->color_count; ++i) {
498 struct radv_render_pass_attachment *attachment;
499
500 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
501 continue;
502
503 attachment = pass->attachments + subpass->color_attachments[i].attachment;
504
505 if (format_is_int8(attachment->format))
506 *is_int8 |= 1 << i;
507 if (format_is_int10(attachment->format))
508 *is_int10 |= 1 << i;
509 }
510 }
511
512 static void
513 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
514 const VkGraphicsPipelineCreateInfo *pCreateInfo,
515 const struct radv_graphics_pipeline_create_info *extra)
516 {
517 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
518 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
519 struct radv_blend_state *blend = &pipeline->graphics.blend;
520 unsigned mode = V_028808_CB_NORMAL;
521 uint32_t blend_enable = 0, blend_need_alpha = 0;
522 bool blend_mrt0_is_dual_src = false;
523 int i;
524 bool single_cb_enable = false;
525
526 if (!vkblend)
527 return;
528
529 if (extra && extra->custom_blend_mode) {
530 single_cb_enable = true;
531 mode = extra->custom_blend_mode;
532 }
533 blend->cb_color_control = 0;
534 if (vkblend->logicOpEnable)
535 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
536 else
537 blend->cb_color_control |= S_028808_ROP3(0xcc);
538
539 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
540 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
541 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
542 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
543
544 if (vkms && vkms->alphaToCoverageEnable) {
545 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
546 }
547
548 blend->cb_target_mask = 0;
549 for (i = 0; i < vkblend->attachmentCount; i++) {
550 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
551 unsigned blend_cntl = 0;
552 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
553 VkBlendOp eqRGB = att->colorBlendOp;
554 VkBlendFactor srcRGB = att->srcColorBlendFactor;
555 VkBlendFactor dstRGB = att->dstColorBlendFactor;
556 VkBlendOp eqA = att->alphaBlendOp;
557 VkBlendFactor srcA = att->srcAlphaBlendFactor;
558 VkBlendFactor dstA = att->dstAlphaBlendFactor;
559
560 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
561
562 if (!att->colorWriteMask)
563 continue;
564
565 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
566 if (!att->blendEnable) {
567 blend->cb_blend_control[i] = blend_cntl;
568 continue;
569 }
570
571 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
572 if (i == 0)
573 blend_mrt0_is_dual_src = true;
574
575 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
576 srcRGB = VK_BLEND_FACTOR_ONE;
577 dstRGB = VK_BLEND_FACTOR_ONE;
578 }
579 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
580 srcA = VK_BLEND_FACTOR_ONE;
581 dstA = VK_BLEND_FACTOR_ONE;
582 }
583
584 /* Blending optimizations for RB+.
585 * These transformations don't change the behavior.
586 *
587 * First, get rid of DST in the blend factors:
588 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
589 */
590 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
591 VK_BLEND_FACTOR_DST_COLOR,
592 VK_BLEND_FACTOR_SRC_COLOR);
593
594 si_blend_remove_dst(&eqA, &srcA, &dstA,
595 VK_BLEND_FACTOR_DST_COLOR,
596 VK_BLEND_FACTOR_SRC_COLOR);
597
598 si_blend_remove_dst(&eqA, &srcA, &dstA,
599 VK_BLEND_FACTOR_DST_ALPHA,
600 VK_BLEND_FACTOR_SRC_ALPHA);
601
602 /* Look up the ideal settings from tables. */
603 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
604 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
605 srcA_opt = si_translate_blend_opt_factor(srcA, true);
606 dstA_opt = si_translate_blend_opt_factor(dstA, true);
607
608 /* Handle interdependencies. */
609 if (si_blend_factor_uses_dst(srcRGB))
610 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
611 if (si_blend_factor_uses_dst(srcA))
612 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
613
614 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
615 (dstRGB == VK_BLEND_FACTOR_ZERO ||
616 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
617 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
618 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
619
620 /* Set the final value. */
621 blend->sx_mrt_blend_opt[i] =
622 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
623 S_028760_COLOR_DST_OPT(dstRGB_opt) |
624 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
625 S_028760_ALPHA_SRC_OPT(srcA_opt) |
626 S_028760_ALPHA_DST_OPT(dstA_opt) |
627 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
628 blend_cntl |= S_028780_ENABLE(1);
629
630 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
631 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
632 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
633 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
634 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
635 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
636 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
637 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
638 }
639 blend->cb_blend_control[i] = blend_cntl;
640
641 blend_enable |= 1 << i;
642
643 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
644 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
645 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
646 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
647 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
648 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
649 blend_need_alpha |= 1 << i;
650 }
651 for (i = vkblend->attachmentCount; i < 8; i++) {
652 blend->cb_blend_control[i] = 0;
653 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
654 }
655
656 /* disable RB+ for now */
657 if (pipeline->device->physical_device->has_rbplus)
658 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
659
660 if (blend->cb_target_mask)
661 blend->cb_color_control |= S_028808_MODE(mode);
662 else
663 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
664
665 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
666 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
667 }
668
669 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
670 {
671 switch (op) {
672 case VK_STENCIL_OP_KEEP:
673 return V_02842C_STENCIL_KEEP;
674 case VK_STENCIL_OP_ZERO:
675 return V_02842C_STENCIL_ZERO;
676 case VK_STENCIL_OP_REPLACE:
677 return V_02842C_STENCIL_REPLACE_TEST;
678 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
679 return V_02842C_STENCIL_ADD_CLAMP;
680 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
681 return V_02842C_STENCIL_SUB_CLAMP;
682 case VK_STENCIL_OP_INVERT:
683 return V_02842C_STENCIL_INVERT;
684 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
685 return V_02842C_STENCIL_ADD_WRAP;
686 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
687 return V_02842C_STENCIL_SUB_WRAP;
688 default:
689 return 0;
690 }
691 }
692 static void
693 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
694 const VkGraphicsPipelineCreateInfo *pCreateInfo,
695 const struct radv_graphics_pipeline_create_info *extra)
696 {
697 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
698 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
699
700 if (!vkds)
701 return;
702
703 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
704 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
705 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
706 return;
707
708 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
709 bool has_depth_attachment = vk_format_is_depth(attachment->format);
710 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
711
712 if (has_depth_attachment) {
713 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
714 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
715 S_028800_ZFUNC(vkds->depthCompareOp) |
716 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
717
718 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
719 ds->db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
720 }
721
722 if (has_stencil_attachment && vkds->stencilTestEnable) {
723 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
724 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
725 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
726 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
727 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
728
729 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
730 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
731 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
732 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
733 }
734
735 if (extra) {
736
737 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
738 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
739
740 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
741 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
742 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
743 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
744 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
745 }
746 }
747
748 static uint32_t si_translate_fill(VkPolygonMode func)
749 {
750 switch(func) {
751 case VK_POLYGON_MODE_FILL:
752 return V_028814_X_DRAW_TRIANGLES;
753 case VK_POLYGON_MODE_LINE:
754 return V_028814_X_DRAW_LINES;
755 case VK_POLYGON_MODE_POINT:
756 return V_028814_X_DRAW_POINTS;
757 default:
758 assert(0);
759 return V_028814_X_DRAW_POINTS;
760 }
761 }
762 static void
763 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
764 const VkGraphicsPipelineCreateInfo *pCreateInfo)
765 {
766 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
767 struct radv_raster_state *raster = &pipeline->graphics.raster;
768
769 raster->spi_interp_control =
770 S_0286D4_FLAT_SHADE_ENA(1) |
771 S_0286D4_PNT_SPRITE_ENA(1) |
772 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
773 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
774 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
775 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
776 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
777
778
779 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
780 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
781 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
782 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
783 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
784 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
785
786 raster->pa_su_vtx_cntl =
787 S_028BE4_PIX_CENTER(1) | // TODO verify
788 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
789 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
790
791 raster->pa_su_sc_mode_cntl =
792 S_028814_FACE(vkraster->frontFace) |
793 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
794 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
795 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
796 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
797 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
798 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
799 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
800 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
801
802 }
803
804 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
805 {
806 uint32_t num_samples = vkms->rasterizationSamples;
807 uint32_t ps_iter_samples = 1;
808
809 if (vkms->sampleShadingEnable) {
810 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
811 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
812 }
813 return ps_iter_samples;
814 }
815
816 static void
817 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
818 const VkGraphicsPipelineCreateInfo *pCreateInfo)
819 {
820 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
821 struct radv_multisample_state *ms = &pipeline->graphics.ms;
822 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
823 int ps_iter_samples = 1;
824 uint32_t mask = 0xffff;
825
826 if (vkms)
827 ms->num_samples = vkms->rasterizationSamples;
828 else
829 ms->num_samples = 1;
830
831 if (vkms)
832 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
833 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
834 ps_iter_samples = ms->num_samples;
835 }
836
837 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
838 ms->pa_sc_aa_config = 0;
839 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
840 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
841 ms->pa_sc_mode_cntl_1 =
842 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
843 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
844 /* always 1: */
845 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
846 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
847 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
848 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
849 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
850 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
851 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
852 S_028A48_VPORT_SCISSOR_ENABLE(1);
853
854 if (ms->num_samples > 1) {
855 unsigned log_samples = util_logbase2(ms->num_samples);
856 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
857 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
858 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
859 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
860 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
861 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
862 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
863 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
864 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
865 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
866 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
867 if (ps_iter_samples > 1)
868 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
869 }
870
871 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
872 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
873 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
874 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
875 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
876 }
877
878 if (vkms && vkms->pSampleMask) {
879 mask = vkms->pSampleMask[0] & 0xffff;
880 }
881
882 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
883 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
884 }
885
886 static bool
887 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
888 {
889 switch (topology) {
890 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
891 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
892 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
893 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
894 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
895 return false;
896 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
897 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
898 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
899 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
900 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
901 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
902 return true;
903 default:
904 unreachable("unhandled primitive type");
905 }
906 }
907
908 static uint32_t
909 si_translate_prim(enum VkPrimitiveTopology topology)
910 {
911 switch (topology) {
912 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
913 return V_008958_DI_PT_POINTLIST;
914 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
915 return V_008958_DI_PT_LINELIST;
916 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
917 return V_008958_DI_PT_LINESTRIP;
918 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
919 return V_008958_DI_PT_TRILIST;
920 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
921 return V_008958_DI_PT_TRISTRIP;
922 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
923 return V_008958_DI_PT_TRIFAN;
924 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
925 return V_008958_DI_PT_LINELIST_ADJ;
926 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
927 return V_008958_DI_PT_LINESTRIP_ADJ;
928 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
929 return V_008958_DI_PT_TRILIST_ADJ;
930 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
931 return V_008958_DI_PT_TRISTRIP_ADJ;
932 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
933 return V_008958_DI_PT_PATCH;
934 default:
935 assert(0);
936 return 0;
937 }
938 }
939
940 static uint32_t
941 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
942 {
943 switch (gl_prim) {
944 case 0: /* GL_POINTS */
945 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
946 case 1: /* GL_LINES */
947 case 3: /* GL_LINE_STRIP */
948 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
949 case 0x8E7A: /* GL_ISOLINES */
950 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
951
952 case 4: /* GL_TRIANGLES */
953 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
954 case 5: /* GL_TRIANGLE_STRIP */
955 case 7: /* GL_QUADS */
956 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
957 default:
958 assert(0);
959 return 0;
960 }
961 }
962
963 static uint32_t
964 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
965 {
966 switch (topology) {
967 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
968 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
969 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
970 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
971 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
972 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
973 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
974 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
975 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
976 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
977 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
978 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
979 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
980 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
981 default:
982 assert(0);
983 return 0;
984 }
985 }
986
987 static unsigned si_map_swizzle(unsigned swizzle)
988 {
989 switch (swizzle) {
990 case VK_SWIZZLE_Y:
991 return V_008F0C_SQ_SEL_Y;
992 case VK_SWIZZLE_Z:
993 return V_008F0C_SQ_SEL_Z;
994 case VK_SWIZZLE_W:
995 return V_008F0C_SQ_SEL_W;
996 case VK_SWIZZLE_0:
997 return V_008F0C_SQ_SEL_0;
998 case VK_SWIZZLE_1:
999 return V_008F0C_SQ_SEL_1;
1000 default: /* VK_SWIZZLE_X */
1001 return V_008F0C_SQ_SEL_X;
1002 }
1003 }
1004
1005
1006 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1007 {
1008 switch(state) {
1009 case VK_DYNAMIC_STATE_VIEWPORT:
1010 return RADV_DYNAMIC_VIEWPORT;
1011 case VK_DYNAMIC_STATE_SCISSOR:
1012 return RADV_DYNAMIC_SCISSOR;
1013 case VK_DYNAMIC_STATE_LINE_WIDTH:
1014 return RADV_DYNAMIC_LINE_WIDTH;
1015 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1016 return RADV_DYNAMIC_DEPTH_BIAS;
1017 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1018 return RADV_DYNAMIC_BLEND_CONSTANTS;
1019 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1020 return RADV_DYNAMIC_DEPTH_BOUNDS;
1021 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1022 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1023 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1024 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1025 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1026 return RADV_DYNAMIC_STENCIL_REFERENCE;
1027 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1028 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1029 default:
1030 unreachable("Unhandled dynamic state");
1031 }
1032 }
1033
1034 static void
1035 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1036 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1037 {
1038 uint32_t states = RADV_DYNAMIC_ALL;
1039 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1040 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1041
1042 pipeline->dynamic_state = default_dynamic_state;
1043
1044 if (pCreateInfo->pDynamicState) {
1045 /* Remove all of the states that are marked as dynamic */
1046 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1047 for (uint32_t s = 0; s < count; s++)
1048 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1049 }
1050
1051 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1052
1053 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1054 *
1055 * pViewportState is [...] NULL if the pipeline
1056 * has rasterization disabled.
1057 */
1058 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1059 assert(pCreateInfo->pViewportState);
1060
1061 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1062 if (states & RADV_DYNAMIC_VIEWPORT) {
1063 typed_memcpy(dynamic->viewport.viewports,
1064 pCreateInfo->pViewportState->pViewports,
1065 pCreateInfo->pViewportState->viewportCount);
1066 }
1067
1068 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1069 if (states & RADV_DYNAMIC_SCISSOR) {
1070 typed_memcpy(dynamic->scissor.scissors,
1071 pCreateInfo->pViewportState->pScissors,
1072 pCreateInfo->pViewportState->scissorCount);
1073 }
1074 }
1075
1076 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1077 assert(pCreateInfo->pRasterizationState);
1078 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1079 }
1080
1081 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1082 assert(pCreateInfo->pRasterizationState);
1083 dynamic->depth_bias.bias =
1084 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1085 dynamic->depth_bias.clamp =
1086 pCreateInfo->pRasterizationState->depthBiasClamp;
1087 dynamic->depth_bias.slope =
1088 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1089 }
1090
1091 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1092 *
1093 * pColorBlendState is [...] NULL if the pipeline has rasterization
1094 * disabled or if the subpass of the render pass the pipeline is
1095 * created against does not use any color attachments.
1096 */
1097 bool uses_color_att = false;
1098 for (unsigned i = 0; i < subpass->color_count; ++i) {
1099 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1100 uses_color_att = true;
1101 break;
1102 }
1103 }
1104
1105 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1106 assert(pCreateInfo->pColorBlendState);
1107 typed_memcpy(dynamic->blend_constants,
1108 pCreateInfo->pColorBlendState->blendConstants, 4);
1109 }
1110
1111 /* If there is no depthstencil attachment, then don't read
1112 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1113 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1114 * no need to override the depthstencil defaults in
1115 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1116 *
1117 * Section 9.2 of the Vulkan 1.0.15 spec says:
1118 *
1119 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1120 * disabled or if the subpass of the render pass the pipeline is created
1121 * against does not use a depth/stencil attachment.
1122 */
1123 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1124 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1125 assert(pCreateInfo->pDepthStencilState);
1126
1127 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1128 dynamic->depth_bounds.min =
1129 pCreateInfo->pDepthStencilState->minDepthBounds;
1130 dynamic->depth_bounds.max =
1131 pCreateInfo->pDepthStencilState->maxDepthBounds;
1132 }
1133
1134 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1135 dynamic->stencil_compare_mask.front =
1136 pCreateInfo->pDepthStencilState->front.compareMask;
1137 dynamic->stencil_compare_mask.back =
1138 pCreateInfo->pDepthStencilState->back.compareMask;
1139 }
1140
1141 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1142 dynamic->stencil_write_mask.front =
1143 pCreateInfo->pDepthStencilState->front.writeMask;
1144 dynamic->stencil_write_mask.back =
1145 pCreateInfo->pDepthStencilState->back.writeMask;
1146 }
1147
1148 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1149 dynamic->stencil_reference.front =
1150 pCreateInfo->pDepthStencilState->front.reference;
1151 dynamic->stencil_reference.back =
1152 pCreateInfo->pDepthStencilState->back.reference;
1153 }
1154 }
1155
1156 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1157 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1158 if (discard_rectangle_info) {
1159 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1160 typed_memcpy(dynamic->discard_rectangle.rectangles,
1161 discard_rectangle_info->pDiscardRectangles,
1162 discard_rectangle_info->discardRectangleCount);
1163
1164 unsigned mask = 0;
1165
1166 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
1167 /* Interpret i as a bitmask, and then set the bit in the mask if
1168 * that combination of rectangles in which the pixel is contained
1169 * should pass the cliprect test. */
1170 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
1171
1172 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
1173 !relevant_subset)
1174 continue;
1175
1176 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
1177 relevant_subset)
1178 continue;
1179
1180 mask |= 1u << i;
1181 }
1182 pipeline->graphics.pa_sc_cliprect_rule = mask;
1183 } else {
1184 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1185
1186 /* Allow from all rectangle combinations */
1187 pipeline->graphics.pa_sc_cliprect_rule = 0xffff;
1188 }
1189 pipeline->dynamic_state.mask = states;
1190 }
1191
1192 static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1193 struct radv_pipeline *pipeline)
1194 {
1195 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1196 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1197 &gs_info->tes.es_info : &gs_info->vs.es_info;
1198 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1199 bool uses_adjacency;
1200 switch(pCreateInfo->pInputAssemblyState->topology) {
1201 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1205 uses_adjacency = true;
1206 break;
1207 default:
1208 uses_adjacency = false;
1209 break;
1210 }
1211
1212 /* All these are in dwords: */
1213 /* We can't allow using the whole LDS, because GS waves compete with
1214 * other shader stages for LDS space. */
1215 const unsigned max_lds_size = 8 * 1024;
1216 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1217 unsigned esgs_lds_size;
1218
1219 /* All these are per subgroup: */
1220 const unsigned max_out_prims = 32 * 1024;
1221 const unsigned max_es_verts = 255;
1222 const unsigned ideal_gs_prims = 64;
1223 unsigned max_gs_prims, gs_prims;
1224 unsigned min_es_verts, es_verts, worst_case_es_verts;
1225
1226 if (uses_adjacency || gs_num_invocations > 1)
1227 max_gs_prims = 127 / gs_num_invocations;
1228 else
1229 max_gs_prims = 255;
1230
1231 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1232 * Make sure we don't go over the maximum value.
1233 */
1234 if (gs_info->gs.vertices_out > 0) {
1235 max_gs_prims = MIN2(max_gs_prims,
1236 max_out_prims /
1237 (gs_info->gs.vertices_out * gs_num_invocations));
1238 }
1239 assert(max_gs_prims > 0);
1240
1241 /* If the primitive has adjacency, halve the number of vertices
1242 * that will be reused in multiple primitives.
1243 */
1244 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1245
1246 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1247 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1248
1249 /* Compute ESGS LDS size based on the worst case number of ES vertices
1250 * needed to create the target number of GS prims per subgroup.
1251 */
1252 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1253
1254 /* If total LDS usage is too big, refactor partitions based on ratio
1255 * of ESGS item sizes.
1256 */
1257 if (esgs_lds_size > max_lds_size) {
1258 /* Our target GS Prims Per Subgroup was too large. Calculate
1259 * the maximum number of GS Prims Per Subgroup that will fit
1260 * into LDS, capped by the maximum that the hardware can support.
1261 */
1262 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1263 max_gs_prims);
1264 assert(gs_prims > 0);
1265 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1266 max_es_verts);
1267
1268 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1269 assert(esgs_lds_size <= max_lds_size);
1270 }
1271
1272 /* Now calculate remaining ESGS information. */
1273 if (esgs_lds_size)
1274 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1275 else
1276 es_verts = max_es_verts;
1277
1278 /* Vertices for adjacency primitives are not always reused, so restore
1279 * it for ES_VERTS_PER_SUBGRP.
1280 */
1281 min_es_verts = gs_info->gs.vertices_in;
1282
1283 /* For normal primitives, the VGT only checks if they are past the ES
1284 * verts per subgroup after allocating a full GS primitive and if they
1285 * are, kick off a new subgroup. But if those additional ES verts are
1286 * unique (e.g. not reused) we need to make sure there is enough LDS
1287 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1288 */
1289 es_verts -= min_es_verts - 1;
1290
1291 uint32_t es_verts_per_subgroup = es_verts;
1292 uint32_t gs_prims_per_subgroup = gs_prims;
1293 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1294 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1295 pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128;
1296 pipeline->graphics.gs.vgt_gs_onchip_cntl =
1297 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1298 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1299 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1300 pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup =
1301 S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1302 pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1303 assert(max_prims_per_subgroup <= max_out_prims);
1304 }
1305
1306 static void
1307 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1308 {
1309 struct radv_device *device = pipeline->device;
1310 unsigned num_se = device->physical_device->rad_info.max_se;
1311 unsigned wave_size = 64;
1312 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1313 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1314 unsigned alignment = 256 * num_se;
1315 /* The maximum size is 63.999 MB per SE. */
1316 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1317 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1318 struct ac_es_output_info *es_info;
1319 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1320 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1321 else
1322 es_info = radv_pipeline_has_tess(pipeline) ?
1323 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1324 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1325
1326 /* Calculate the minimum size. */
1327 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1328 wave_size, alignment);
1329 /* These are recommended sizes, not minimum sizes. */
1330 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1331 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1332 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1333 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1334
1335 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1336 esgs_ring_size = align(esgs_ring_size, alignment);
1337 gsvs_ring_size = align(gsvs_ring_size, alignment);
1338
1339 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1340 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1341
1342 pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1343 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1344 }
1345
1346 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1347 unsigned *lds_size)
1348 {
1349 /* SPI barrier management bug:
1350 * Make sure we have at least 4k of LDS in use to avoid the bug.
1351 * It applies to workgroup sizes of more than one wavefront.
1352 */
1353 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1354 device->physical_device->rad_info.family == CHIP_KABINI ||
1355 device->physical_device->rad_info.family == CHIP_MULLINS)
1356 *lds_size = MAX2(*lds_size, 8);
1357 }
1358
1359 struct radv_shader_variant *
1360 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1361 {
1362 if (pipeline->shaders[MESA_SHADER_VERTEX])
1363 return pipeline->shaders[MESA_SHADER_VERTEX];
1364 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1365 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1366 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1367 }
1368
1369 static struct radv_shader_variant *
1370 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1371 {
1372 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1373 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1374 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1375 }
1376
1377 static void
1378 calculate_tess_state(struct radv_pipeline *pipeline,
1379 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1380 {
1381 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1382 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1383 unsigned num_tcs_patch_outputs;
1384 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1385 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1386 unsigned lds_size, hardware_lds_size;
1387 unsigned perpatch_output_offset;
1388 unsigned num_patches;
1389 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1390
1391 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1392 * are laid out in LDS. */
1393 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1394
1395 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1396 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1397 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1398
1399 /* Ensure that we only need one wave per SIMD so we don't need to check
1400 * resource usage. Also ensures that the number of tcs in and out
1401 * vertices per threadgroup are at most 256.
1402 */
1403 input_vertex_size = num_tcs_inputs * 16;
1404 output_vertex_size = num_tcs_outputs * 16;
1405
1406 input_patch_size = num_tcs_input_cp * input_vertex_size;
1407
1408 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1409 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1410 /* Ensure that we only need one wave per SIMD so we don't need to check
1411 * resource usage. Also ensures that the number of tcs in and out
1412 * vertices per threadgroup are at most 256.
1413 */
1414 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1415
1416 /* Make sure that the data fits in LDS. This assumes the shaders only
1417 * use LDS for the inputs and outputs.
1418 */
1419 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1420 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1421
1422 /* Make sure the output data fits in the offchip buffer */
1423 num_patches = MIN2(num_patches,
1424 (pipeline->device->tess_offchip_block_dw_size * 4) /
1425 output_patch_size);
1426
1427 /* Not necessary for correctness, but improves performance. The
1428 * specific value is taken from the proprietary driver.
1429 */
1430 num_patches = MIN2(num_patches, 40);
1431
1432 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1433 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1434 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1435 num_patches = MIN2(num_patches, one_wave);
1436 }
1437
1438 output_patch0_offset = input_patch_size * num_patches;
1439 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1440
1441 lds_size = output_patch0_offset + output_patch_size * num_patches;
1442
1443 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1444 assert(lds_size <= 65536);
1445 lds_size = align(lds_size, 512) / 512;
1446 } else {
1447 assert(lds_size <= 32768);
1448 lds_size = align(lds_size, 256) / 256;
1449 }
1450 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1451
1452 tess->lds_size = lds_size;
1453
1454 tess->tcs_in_layout = (input_patch_size / 4) |
1455 ((input_vertex_size / 4) << 13);
1456 tess->tcs_out_layout = (output_patch_size / 4) |
1457 ((output_vertex_size / 4) << 13);
1458 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1459 ((perpatch_output_offset / 16) << 16);
1460 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1461 (num_tcs_output_cp << 9) | num_patches;
1462
1463 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1464 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1465 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1466 tess->num_patches = num_patches;
1467 tess->num_tcs_input_cp = num_tcs_input_cp;
1468
1469 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1470 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1471
1472 switch (tes->info.tes.primitive_mode) {
1473 case GL_TRIANGLES:
1474 type = V_028B6C_TESS_TRIANGLE;
1475 break;
1476 case GL_QUADS:
1477 type = V_028B6C_TESS_QUAD;
1478 break;
1479 case GL_ISOLINES:
1480 type = V_028B6C_TESS_ISOLINE;
1481 break;
1482 }
1483
1484 switch (tes->info.tes.spacing) {
1485 case TESS_SPACING_EQUAL:
1486 partitioning = V_028B6C_PART_INTEGER;
1487 break;
1488 case TESS_SPACING_FRACTIONAL_ODD:
1489 partitioning = V_028B6C_PART_FRAC_ODD;
1490 break;
1491 case TESS_SPACING_FRACTIONAL_EVEN:
1492 partitioning = V_028B6C_PART_FRAC_EVEN;
1493 break;
1494 default:
1495 break;
1496 }
1497
1498 bool ccw = tes->info.tes.ccw;
1499 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1500 vk_find_struct_const(pCreateInfo->pTessellationState,
1501 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1502
1503 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1504 ccw = !ccw;
1505
1506 if (tes->info.tes.point_mode)
1507 topology = V_028B6C_OUTPUT_POINT;
1508 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1509 topology = V_028B6C_OUTPUT_LINE;
1510 else if (ccw)
1511 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1512 else
1513 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1514
1515 if (pipeline->device->has_distributed_tess) {
1516 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1517 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1518 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1519 else
1520 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1521 } else
1522 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1523
1524 tess->tf_param = S_028B6C_TYPE(type) |
1525 S_028B6C_PARTITIONING(partitioning) |
1526 S_028B6C_TOPOLOGY(topology) |
1527 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1528 }
1529
1530 static const struct radv_prim_vertex_count prim_size_table[] = {
1531 [V_008958_DI_PT_NONE] = {0, 0},
1532 [V_008958_DI_PT_POINTLIST] = {1, 1},
1533 [V_008958_DI_PT_LINELIST] = {2, 2},
1534 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1535 [V_008958_DI_PT_TRILIST] = {3, 3},
1536 [V_008958_DI_PT_TRIFAN] = {3, 1},
1537 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1538 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1539 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1540 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1541 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1542 [V_008958_DI_PT_RECTLIST] = {3, 3},
1543 [V_008958_DI_PT_LINELOOP] = {2, 1},
1544 [V_008958_DI_PT_POLYGON] = {3, 1},
1545 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1546 };
1547
1548 static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline *pipeline)
1549 {
1550 if (radv_pipeline_has_gs(pipeline))
1551 return &pipeline->gs_copy_shader->info.vs.outinfo;
1552 else if (radv_pipeline_has_tess(pipeline))
1553 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1554 else
1555 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1556 }
1557
1558 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1559 {
1560 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1561
1562 pipeline->graphics.vgt_primitiveid_en = false;
1563 pipeline->graphics.vgt_gs_mode = 0;
1564
1565 if (radv_pipeline_has_gs(pipeline)) {
1566 struct radv_shader_variant *gs =
1567 pipeline->shaders[MESA_SHADER_GEOMETRY];
1568
1569 pipeline->graphics.vgt_gs_mode =
1570 ac_vgt_gs_mode(gs->info.gs.vertices_out,
1571 pipeline->device->physical_device->rad_info.chip_class);
1572 } else if (outinfo->export_prim_id) {
1573 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1574 pipeline->graphics.vgt_primitiveid_en = true;
1575 }
1576 }
1577
1578 static void calculate_vs_outinfo(struct radv_pipeline *pipeline)
1579 {
1580 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1581
1582 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1583 clip_dist_mask = outinfo->clip_dist_mask;
1584 cull_dist_mask = outinfo->cull_dist_mask;
1585 total_mask = clip_dist_mask | cull_dist_mask;
1586
1587 bool misc_vec_ena = outinfo->writes_pointsize ||
1588 outinfo->writes_layer ||
1589 outinfo->writes_viewport_index;
1590 pipeline->graphics.vs.pa_cl_vs_out_cntl =
1591 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1592 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1593 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1594 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1595 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1596 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1597 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1598 cull_dist_mask << 8 |
1599 clip_dist_mask;
1600
1601 pipeline->graphics.vs.spi_shader_pos_format =
1602 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1603 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
1604 V_02870C_SPI_SHADER_4COMP :
1605 V_02870C_SPI_SHADER_NONE) |
1606 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
1607 V_02870C_SPI_SHADER_4COMP :
1608 V_02870C_SPI_SHADER_NONE) |
1609 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
1610 V_02870C_SPI_SHADER_4COMP :
1611 V_02870C_SPI_SHADER_NONE);
1612
1613 pipeline->graphics.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1);
1614 /* only emitted on pre-VI */
1615 pipeline->graphics.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(outinfo->writes_viewport_index);
1616 }
1617
1618 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1619 {
1620 uint32_t ps_input_cntl;
1621 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1622 ps_input_cntl = S_028644_OFFSET(offset);
1623 if (flat_shade)
1624 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1625 } else {
1626 /* The input is a DEFAULT_VAL constant. */
1627 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1628 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1629 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1630 ps_input_cntl = S_028644_OFFSET(0x20) |
1631 S_028644_DEFAULT_VAL(offset);
1632 }
1633 return ps_input_cntl;
1634 }
1635
1636 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1637 {
1638 struct radv_shader_variant *ps;
1639 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1640
1641 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1642
1643 unsigned ps_offset = 0;
1644
1645 if (ps->info.fs.prim_id_input) {
1646 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1647 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1648 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1649 ++ps_offset;
1650 }
1651 }
1652
1653 if (ps->info.fs.layer_input) {
1654 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1655 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1656 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1657 else
1658 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1659 ++ps_offset;
1660 }
1661
1662 if (ps->info.fs.has_pcoord) {
1663 unsigned val;
1664 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1665 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1666 ps_offset++;
1667 }
1668
1669 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1670 unsigned vs_offset;
1671 bool flat_shade;
1672 if (!(ps->info.fs.input_mask & (1u << i)))
1673 continue;
1674
1675 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1676 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1677 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1678 ++ps_offset;
1679 continue;
1680 }
1681
1682 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1683
1684 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1685 ++ps_offset;
1686 }
1687
1688 pipeline->graphics.ps_input_cntl_num = ps_offset;
1689 }
1690
1691 static void
1692 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1693 {
1694 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1695 int shader_count = 0;
1696
1697 if(shaders[MESA_SHADER_FRAGMENT]) {
1698 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1699 }
1700 if(shaders[MESA_SHADER_GEOMETRY]) {
1701 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1702 }
1703 if(shaders[MESA_SHADER_TESS_EVAL]) {
1704 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1705 }
1706 if(shaders[MESA_SHADER_TESS_CTRL]) {
1707 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1708 }
1709 if(shaders[MESA_SHADER_VERTEX]) {
1710 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1711 }
1712
1713 for (int i = 1; i < shader_count; ++i) {
1714 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1715 ordered_shaders[i - 1]);
1716
1717 nir_remove_dead_variables(ordered_shaders[i],
1718 nir_var_shader_out);
1719 nir_remove_dead_variables(ordered_shaders[i - 1],
1720 nir_var_shader_in);
1721
1722 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1723 ordered_shaders[i - 1]);
1724
1725 if (progress) {
1726 nir_lower_global_vars_to_local(ordered_shaders[i]);
1727 radv_optimize_nir(ordered_shaders[i]);
1728 nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
1729 radv_optimize_nir(ordered_shaders[i - 1]);
1730 }
1731 }
1732 }
1733
1734
1735 static struct radv_pipeline_key
1736 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1737 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1738 bool has_view_index)
1739 {
1740 const VkPipelineVertexInputStateCreateInfo *input_state =
1741 pCreateInfo->pVertexInputState;
1742 struct radv_pipeline_key key;
1743 memset(&key, 0, sizeof(key));
1744
1745 key.has_multiview_view_index = has_view_index;
1746
1747 uint32_t binding_input_rate = 0;
1748 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1749 if (input_state->pVertexBindingDescriptions[i].inputRate)
1750 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1751 }
1752
1753 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1754 unsigned binding;
1755 binding = input_state->pVertexAttributeDescriptions[i].binding;
1756 if (binding_input_rate & (1u << binding))
1757 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1758 }
1759
1760 if (pCreateInfo->pTessellationState)
1761 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1762
1763
1764 if (pCreateInfo->pMultisampleState &&
1765 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1766 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1767 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1768 key.multisample = true;
1769 key.log2_num_samples = util_logbase2(num_samples);
1770 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1771 }
1772
1773 key.col_format = pipeline->graphics.blend.spi_shader_col_format;
1774 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1775 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1776
1777 return key;
1778 }
1779
1780 static void
1781 radv_fill_shader_keys(struct ac_shader_variant_key *keys,
1782 const struct radv_pipeline_key *key,
1783 nir_shader **nir)
1784 {
1785 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1786
1787 if (nir[MESA_SHADER_TESS_CTRL]) {
1788 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1789 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1790 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1791
1792 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1793 }
1794
1795 if (nir[MESA_SHADER_GEOMETRY]) {
1796 if (nir[MESA_SHADER_TESS_CTRL])
1797 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1798 else
1799 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1800 }
1801
1802 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1803 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1804
1805 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1806 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1807 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1808 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1809 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1810 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1811 }
1812
1813 static void
1814 merge_tess_info(struct shader_info *tes_info,
1815 const struct shader_info *tcs_info)
1816 {
1817 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1818 *
1819 * "PointMode. Controls generation of points rather than triangles
1820 * or lines. This functionality defaults to disabled, and is
1821 * enabled if either shader stage includes the execution mode.
1822 *
1823 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1824 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1825 * and OutputVertices, it says:
1826 *
1827 * "One mode must be set in at least one of the tessellation
1828 * shader stages."
1829 *
1830 * So, the fields can be set in either the TCS or TES, but they must
1831 * agree if set in both. Our backend looks at TES, so bitwise-or in
1832 * the values from the TCS.
1833 */
1834 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1835 tes_info->tess.tcs_vertices_out == 0 ||
1836 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1837 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1838
1839 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1840 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1841 tcs_info->tess.spacing == tes_info->tess.spacing);
1842 tes_info->tess.spacing |= tcs_info->tess.spacing;
1843
1844 assert(tcs_info->tess.primitive_mode == 0 ||
1845 tes_info->tess.primitive_mode == 0 ||
1846 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1847 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1848 tes_info->tess.ccw |= tcs_info->tess.ccw;
1849 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1850 }
1851
1852 static
1853 void radv_create_shaders(struct radv_pipeline *pipeline,
1854 struct radv_device *device,
1855 struct radv_pipeline_cache *cache,
1856 struct radv_pipeline_key key,
1857 const VkPipelineShaderStageCreateInfo **pStages)
1858 {
1859 struct radv_shader_module fs_m = {0};
1860 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1861 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1862 void *codes[MESA_SHADER_STAGES] = {0};
1863 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1864 struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1865 unsigned char hash[20], gs_copy_hash[20];
1866
1867 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1868 if (pStages[i]) {
1869 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1870 if (modules[i]->nir)
1871 _mesa_sha1_compute(modules[i]->nir->info.name,
1872 strlen(modules[i]->nir->info.name),
1873 modules[i]->sha1);
1874 }
1875 }
1876
1877 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1878 memcpy(gs_copy_hash, hash, 20);
1879 gs_copy_hash[0] ^= 1;
1880
1881 if (modules[MESA_SHADER_GEOMETRY]) {
1882 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1883 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1884 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1885 }
1886
1887 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1888 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1889 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1890 if (pipeline->shaders[i])
1891 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1892 }
1893 return;
1894 }
1895
1896 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1897 nir_builder fs_b;
1898 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1899 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1900 fs_m.nir = fs_b.shader;
1901 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1902 }
1903
1904 /* Determine first and last stage. */
1905 unsigned first = MESA_SHADER_STAGES;
1906 unsigned last = 0;
1907 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1908 if (!pStages[i])
1909 continue;
1910 if (first == MESA_SHADER_STAGES)
1911 first = i;
1912 last = i;
1913 }
1914
1915 int prev = -1;
1916 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1917 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1918
1919 if (!modules[i])
1920 continue;
1921
1922 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1923 stage ? stage->pName : "main", i,
1924 stage ? stage->pSpecializationInfo : NULL);
1925 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1926
1927 /* We don't want to alter meta shaders IR directly so clone it
1928 * first.
1929 */
1930 if (nir[i]->info.name) {
1931 nir[i] = nir_shader_clone(NULL, nir[i]);
1932 }
1933
1934 if (first != last) {
1935 nir_variable_mode mask = 0;
1936
1937 if (i != first)
1938 mask = mask | nir_var_shader_in;
1939
1940 if (i != last)
1941 mask = mask | nir_var_shader_out;
1942
1943 nir_lower_io_to_scalar_early(nir[i], mask);
1944 radv_optimize_nir(nir[i]);
1945 }
1946
1947 if (prev != -1) {
1948 nir_compact_varyings(nir[prev], nir[i], true);
1949 }
1950 prev = i;
1951 }
1952
1953 if (nir[MESA_SHADER_TESS_CTRL]) {
1954 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1955 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1956 }
1957
1958 radv_link_shaders(pipeline, nir);
1959
1960 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1961 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1962 nir_print_shader(nir[i], stderr);
1963 }
1964
1965 radv_fill_shader_keys(keys, &key, nir);
1966
1967 if (nir[MESA_SHADER_FRAGMENT]) {
1968 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1969 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1970 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1971 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1972 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1973 }
1974
1975 /* TODO: These are no longer used as keys we should refactor this */
1976 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1977 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1978 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1979 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1980 }
1981
1982 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1983 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1984 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1985 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1986 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1987 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1988 pipeline->layout,
1989 &key, &codes[MESA_SHADER_TESS_CTRL],
1990 &code_sizes[MESA_SHADER_TESS_CTRL]);
1991 }
1992 modules[MESA_SHADER_VERTEX] = NULL;
1993 }
1994
1995 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1996 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1997 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1998 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1999 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2000 pipeline->layout,
2001 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
2002 &code_sizes[MESA_SHADER_GEOMETRY]);
2003 }
2004 modules[pre_stage] = NULL;
2005 }
2006
2007 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2008 if(modules[i] && !pipeline->shaders[i]) {
2009 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2010 pipeline->layout,
2011 keys + i, &codes[i],
2012 &code_sizes[i]);
2013 }
2014 }
2015
2016 if(modules[MESA_SHADER_GEOMETRY]) {
2017 void *gs_copy_code = NULL;
2018 unsigned gs_copy_code_size = 0;
2019 if (!pipeline->gs_copy_shader) {
2020 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2021 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2022 &gs_copy_code_size,
2023 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2024 }
2025
2026 if (pipeline->gs_copy_shader) {
2027 void *code[MESA_SHADER_STAGES] = {0};
2028 unsigned code_size[MESA_SHADER_STAGES] = {0};
2029 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2030
2031 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2032 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2033 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2034
2035 radv_pipeline_cache_insert_shaders(device, cache,
2036 gs_copy_hash,
2037 variants,
2038 (const void**)code,
2039 code_size);
2040 }
2041 free(gs_copy_code);
2042 }
2043
2044 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2045 (const void**)codes, code_sizes);
2046
2047 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2048 free(codes[i]);
2049 if (modules[i] && !pipeline->device->keep_shader_info)
2050 ralloc_free(nir[i]);
2051 }
2052
2053 if (fs_m.nir)
2054 ralloc_free(fs_m.nir);
2055 }
2056
2057 static uint32_t
2058 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2059 gl_shader_stage stage, enum chip_class chip_class)
2060 {
2061 bool has_gs = radv_pipeline_has_gs(pipeline);
2062 bool has_tess = radv_pipeline_has_tess(pipeline);
2063 switch (stage) {
2064 case MESA_SHADER_FRAGMENT:
2065 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2066 case MESA_SHADER_VERTEX:
2067 if (chip_class >= GFX9) {
2068 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2069 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2070 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2071 }
2072 if (has_tess)
2073 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2074 else
2075 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2076 case MESA_SHADER_GEOMETRY:
2077 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2078 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2079 case MESA_SHADER_COMPUTE:
2080 return R_00B900_COMPUTE_USER_DATA_0;
2081 case MESA_SHADER_TESS_CTRL:
2082 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2083 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2084 case MESA_SHADER_TESS_EVAL:
2085 if (chip_class >= GFX9) {
2086 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2087 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2088 }
2089 if (has_gs)
2090 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2091 else
2092 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2093 default:
2094 unreachable("unknown shader");
2095 }
2096 }
2097
2098 struct radv_bin_size_entry {
2099 unsigned bpp;
2100 VkExtent2D extent;
2101 };
2102
2103 static VkExtent2D
2104 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2105 {
2106 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2107 {
2108 /* One RB / SE */
2109 {
2110 /* One shader engine */
2111 { 0, {128, 128}},
2112 { 1, { 64, 128}},
2113 { 2, { 32, 128}},
2114 { 3, { 16, 128}},
2115 { 17, { 0, 0}},
2116 { UINT_MAX, { 0, 0}},
2117 },
2118 {
2119 /* Two shader engines */
2120 { 0, {128, 128}},
2121 { 2, { 64, 128}},
2122 { 3, { 32, 128}},
2123 { 5, { 16, 128}},
2124 { 17, { 0, 0}},
2125 { UINT_MAX, { 0, 0}},
2126 },
2127 {
2128 /* Four shader engines */
2129 { 0, {128, 128}},
2130 { 3, { 64, 128}},
2131 { 5, { 16, 128}},
2132 { 17, { 0, 0}},
2133 { UINT_MAX, { 0, 0}},
2134 },
2135 },
2136 {
2137 /* Two RB / SE */
2138 {
2139 /* One shader engine */
2140 { 0, {128, 128}},
2141 { 2, { 64, 128}},
2142 { 3, { 32, 128}},
2143 { 5, { 16, 128}},
2144 { 33, { 0, 0}},
2145 { UINT_MAX, { 0, 0}},
2146 },
2147 {
2148 /* Two shader engines */
2149 { 0, {128, 128}},
2150 { 3, { 64, 128}},
2151 { 5, { 32, 128}},
2152 { 9, { 16, 128}},
2153 { 33, { 0, 0}},
2154 { UINT_MAX, { 0, 0}},
2155 },
2156 {
2157 /* Four shader engines */
2158 { 0, {256, 256}},
2159 { 2, {128, 256}},
2160 { 3, {128, 128}},
2161 { 5, { 64, 128}},
2162 { 9, { 16, 128}},
2163 { 33, { 0, 0}},
2164 { UINT_MAX, { 0, 0}},
2165 },
2166 },
2167 {
2168 /* Four RB / SE */
2169 {
2170 /* One shader engine */
2171 { 0, {128, 256}},
2172 { 2, {128, 128}},
2173 { 3, { 64, 128}},
2174 { 5, { 32, 128}},
2175 { 9, { 16, 128}},
2176 { 33, { 0, 0}},
2177 { UINT_MAX, { 0, 0}},
2178 },
2179 {
2180 /* Two shader engines */
2181 { 0, {256, 256}},
2182 { 2, {128, 256}},
2183 { 3, {128, 128}},
2184 { 5, { 64, 128}},
2185 { 9, { 32, 128}},
2186 { 17, { 16, 128}},
2187 { 33, { 0, 0}},
2188 { UINT_MAX, { 0, 0}},
2189 },
2190 {
2191 /* Four shader engines */
2192 { 0, {256, 512}},
2193 { 2, {256, 256}},
2194 { 3, {128, 256}},
2195 { 5, {128, 128}},
2196 { 9, { 64, 128}},
2197 { 17, { 16, 128}},
2198 { 33, { 0, 0}},
2199 { UINT_MAX, { 0, 0}},
2200 },
2201 },
2202 };
2203 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2204 {
2205 // One RB / SE
2206 {
2207 // One shader engine
2208 { 0, {128, 256}},
2209 { 2, {128, 128}},
2210 { 4, { 64, 128}},
2211 { 7, { 32, 128}},
2212 { 13, { 16, 128}},
2213 { 49, { 0, 0}},
2214 { UINT_MAX, { 0, 0}},
2215 },
2216 {
2217 // Two shader engines
2218 { 0, {256, 256}},
2219 { 2, {128, 256}},
2220 { 4, {128, 128}},
2221 { 7, { 64, 128}},
2222 { 13, { 32, 128}},
2223 { 25, { 16, 128}},
2224 { 49, { 0, 0}},
2225 { UINT_MAX, { 0, 0}},
2226 },
2227 {
2228 // Four shader engines
2229 { 0, {256, 512}},
2230 { 2, {256, 256}},
2231 { 4, {128, 256}},
2232 { 7, {128, 128}},
2233 { 13, { 64, 128}},
2234 { 25, { 16, 128}},
2235 { 49, { 0, 0}},
2236 { UINT_MAX, { 0, 0}},
2237 },
2238 },
2239 {
2240 // Two RB / SE
2241 {
2242 // One shader engine
2243 { 0, {256, 256}},
2244 { 2, {128, 256}},
2245 { 4, {128, 128}},
2246 { 7, { 64, 128}},
2247 { 13, { 32, 128}},
2248 { 25, { 16, 128}},
2249 { 97, { 0, 0}},
2250 { UINT_MAX, { 0, 0}},
2251 },
2252 {
2253 // Two shader engines
2254 { 0, {256, 512}},
2255 { 2, {256, 256}},
2256 { 4, {128, 256}},
2257 { 7, {128, 128}},
2258 { 13, { 64, 128}},
2259 { 25, { 32, 128}},
2260 { 49, { 16, 128}},
2261 { 97, { 0, 0}},
2262 { UINT_MAX, { 0, 0}},
2263 },
2264 {
2265 // Four shader engines
2266 { 0, {512, 512}},
2267 { 2, {256, 512}},
2268 { 4, {256, 256}},
2269 { 7, {128, 256}},
2270 { 13, {128, 128}},
2271 { 25, { 64, 128}},
2272 { 49, { 16, 128}},
2273 { 97, { 0, 0}},
2274 { UINT_MAX, { 0, 0}},
2275 },
2276 },
2277 {
2278 // Four RB / SE
2279 {
2280 // One shader engine
2281 { 0, {256, 512}},
2282 { 2, {256, 256}},
2283 { 4, {128, 256}},
2284 { 7, {128, 128}},
2285 { 13, { 64, 128}},
2286 { 25, { 32, 128}},
2287 { 49, { 16, 128}},
2288 { UINT_MAX, { 0, 0}},
2289 },
2290 {
2291 // Two shader engines
2292 { 0, {512, 512}},
2293 { 2, {256, 512}},
2294 { 4, {256, 256}},
2295 { 7, {128, 256}},
2296 { 13, {128, 128}},
2297 { 25, { 64, 128}},
2298 { 49, { 32, 128}},
2299 { 97, { 16, 128}},
2300 { UINT_MAX, { 0, 0}},
2301 },
2302 {
2303 // Four shader engines
2304 { 0, {512, 512}},
2305 { 4, {256, 512}},
2306 { 7, {256, 256}},
2307 { 13, {128, 256}},
2308 { 25, {128, 128}},
2309 { 49, { 64, 128}},
2310 { 97, { 16, 128}},
2311 { UINT_MAX, { 0, 0}},
2312 },
2313 },
2314 };
2315
2316 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2317 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2318 VkExtent2D extent = {512, 512};
2319
2320 unsigned log_num_rb_per_se =
2321 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2322 pipeline->device->physical_device->rad_info.max_se);
2323 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2324
2325 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2326 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2327 unsigned effective_samples = total_samples;
2328 unsigned cb_target_mask = pipeline->graphics.blend.cb_target_mask;
2329 unsigned color_bytes_per_pixel = 0;
2330
2331 for (unsigned i = 0; i < subpass->color_count; i++) {
2332 if (!(cb_target_mask & (0xf << (i * 4))))
2333 continue;
2334
2335 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2336 continue;
2337
2338 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2339 color_bytes_per_pixel += vk_format_get_blocksize(format);
2340 }
2341
2342 /* MSAA images typically don't use all samples all the time. */
2343 if (effective_samples >= 2 && ps_iter_samples <= 1)
2344 effective_samples = 2;
2345 color_bytes_per_pixel *= effective_samples;
2346
2347 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2348 while(color_entry->bpp <= color_bytes_per_pixel)
2349 ++color_entry;
2350
2351 extent = color_entry->extent;
2352
2353 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2354 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2355
2356 /* Coefficients taken from AMDVLK */
2357 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2358 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2359 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2360
2361 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2362 while(ds_entry->bpp <= ds_bytes_per_pixel)
2363 ++ds_entry;
2364
2365 extent.width = MIN2(extent.width, ds_entry->extent.width);
2366 extent.height = MIN2(extent.height, ds_entry->extent.height);
2367 }
2368
2369 return extent;
2370 }
2371
2372 static void
2373 radv_compute_binning_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2374 {
2375 pipeline->graphics.bin.pa_sc_binner_cntl_0 =
2376 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2377 S_028C44_DISABLE_START_OF_PRIM(1);
2378 pipeline->graphics.bin.db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2379
2380 if (!pipeline->device->pbb_allowed)
2381 return;
2382
2383 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2384 if (!bin_size.width || !bin_size.height)
2385 return;
2386
2387 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2388 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2389 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2390
2391 switch (pipeline->device->physical_device->rad_info.family) {
2392 case CHIP_VEGA10:
2393 context_states_per_bin = 1;
2394 persistent_states_per_bin = 1;
2395 fpovs_per_batch = 63;
2396 break;
2397 case CHIP_RAVEN:
2398 context_states_per_bin = 6;
2399 persistent_states_per_bin = 32;
2400 fpovs_per_batch = 63;
2401 break;
2402 default:
2403 unreachable("unhandled family while determining binning state.");
2404 }
2405
2406 pipeline->graphics.bin.pa_sc_binner_cntl_0 =
2407 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2408 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2409 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2410 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2411 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2412 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2413 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2414 S_028C44_DISABLE_START_OF_PRIM(1) |
2415 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2416 S_028C44_OPTIMAL_BIN_SELECTION(1);
2417
2418 /* DFSM is not implemented yet */
2419 assert(!pipeline->device->dfsm_allowed);
2420 }
2421
2422 static VkResult
2423 radv_pipeline_init(struct radv_pipeline *pipeline,
2424 struct radv_device *device,
2425 struct radv_pipeline_cache *cache,
2426 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2427 const struct radv_graphics_pipeline_create_info *extra,
2428 const VkAllocationCallbacks *alloc)
2429 {
2430 VkResult result;
2431 bool has_view_index = false;
2432
2433 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2434 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2435 if (subpass->view_mask)
2436 has_view_index = true;
2437 if (alloc == NULL)
2438 alloc = &device->alloc;
2439
2440 pipeline->device = device;
2441 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2442 assert(pipeline->layout);
2443
2444 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2445 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2446
2447 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2448 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2449 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2450 pStages[stage] = &pCreateInfo->pStages[i];
2451 }
2452
2453 radv_create_shaders(pipeline, device, cache,
2454 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, has_view_index),
2455 pStages);
2456
2457 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
2458 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2459 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2460 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2461 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2462 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2463
2464 if (radv_pipeline_has_gs(pipeline)) {
2465 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2466 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2467 } else {
2468 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2469 }
2470 if (extra && extra->use_rectlist) {
2471 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2472 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2473 pipeline->graphics.can_use_guardband = true;
2474 }
2475 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2476 /* prim vertex count will need TESS changes */
2477 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2478
2479 /* Ensure that some export memory is always allocated, for two reasons:
2480 *
2481 * 1) Correctness: The hardware ignores the EXEC mask if no export
2482 * memory is allocated, so KILL and alpha test do not work correctly
2483 * without this.
2484 * 2) Performance: Every shader needs at least a NULL export, even when
2485 * it writes no color/depth output. The NULL export instruction
2486 * stalls without this setting.
2487 *
2488 * Don't add this to CB_SHADER_MASK.
2489 */
2490 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2491 if (!pipeline->graphics.blend.spi_shader_col_format) {
2492 if (!ps->info.fs.writes_z &&
2493 !ps->info.fs.writes_stencil &&
2494 !ps->info.fs.writes_sample_mask)
2495 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2496 }
2497
2498 unsigned z_order;
2499 pipeline->graphics.db_shader_control = 0;
2500 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2501 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2502 else
2503 z_order = V_02880C_LATE_Z;
2504
2505 pipeline->graphics.db_shader_control =
2506 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2507 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2508 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2509 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2510 S_02880C_Z_ORDER(z_order) |
2511 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2512 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2513 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2514
2515 if (pipeline->device->physical_device->has_rbplus)
2516 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2517
2518 unsigned shader_z_format =
2519 ac_get_spi_shader_z_format(ps->info.fs.writes_z,
2520 ps->info.fs.writes_stencil,
2521 ps->info.fs.writes_sample_mask);
2522 pipeline->graphics.shader_z_format = shader_z_format;
2523
2524 calculate_vgt_gs_mode(pipeline);
2525 calculate_vs_outinfo(pipeline);
2526 calculate_ps_inputs(pipeline);
2527
2528 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2529 if (pipeline->shaders[i]) {
2530 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2531 }
2532 }
2533
2534 uint32_t stages = 0;
2535 if (radv_pipeline_has_tess(pipeline)) {
2536 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2537 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2538
2539 if (radv_pipeline_has_gs(pipeline))
2540 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2541 S_028B54_GS_EN(1) |
2542 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2543 else
2544 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2545
2546 } else if (radv_pipeline_has_gs(pipeline))
2547 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2548 S_028B54_GS_EN(1) |
2549 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2550
2551 if (device->physical_device->rad_info.chip_class >= GFX9)
2552 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2553
2554 pipeline->graphics.vgt_shader_stages_en = stages;
2555
2556 if (radv_pipeline_has_gs(pipeline)) {
2557 calculate_gs_ring_sizes(pipeline);
2558 if (device->physical_device->rad_info.chip_class >= GFX9)
2559 calculate_gfx9_gs_info(pCreateInfo, pipeline);
2560 }
2561
2562 if (radv_pipeline_has_tess(pipeline)) {
2563 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2564 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2565 pipeline->graphics.prim_vertex_count.incr = 1;
2566 }
2567 calculate_tess_state(pipeline, pCreateInfo);
2568 }
2569
2570 if (radv_pipeline_has_tess(pipeline))
2571 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
2572 else if (radv_pipeline_has_gs(pipeline))
2573 pipeline->graphics.primgroup_size = 64;
2574 else
2575 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
2576
2577 pipeline->graphics.partial_es_wave = false;
2578 if (pipeline->device->has_distributed_tess) {
2579 if (radv_pipeline_has_gs(pipeline)) {
2580 if (device->physical_device->rad_info.chip_class <= VI)
2581 pipeline->graphics.partial_es_wave = true;
2582 }
2583 }
2584 /* GS requirement. */
2585 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
2586 pipeline->graphics.partial_es_wave = true;
2587
2588 pipeline->graphics.wd_switch_on_eop = false;
2589 if (device->physical_device->rad_info.chip_class >= CIK) {
2590 unsigned prim = pipeline->graphics.prim;
2591 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2592 * 4 shader engines. Set 1 to pass the assertion below.
2593 * The other cases are hardware requirements. */
2594 if (device->physical_device->rad_info.max_se < 4 ||
2595 prim == V_008958_DI_PT_POLYGON ||
2596 prim == V_008958_DI_PT_LINELOOP ||
2597 prim == V_008958_DI_PT_TRIFAN ||
2598 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
2599 (pipeline->graphics.prim_restart_enable &&
2600 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
2601 (prim != V_008958_DI_PT_POINTLIST &&
2602 prim != V_008958_DI_PT_LINESTRIP &&
2603 prim != V_008958_DI_PT_TRISTRIP))))
2604 pipeline->graphics.wd_switch_on_eop = true;
2605 }
2606
2607 pipeline->graphics.ia_switch_on_eoi = false;
2608 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2609 pipeline->graphics.ia_switch_on_eoi = true;
2610 if (radv_pipeline_has_gs(pipeline) &&
2611 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
2612 pipeline->graphics.ia_switch_on_eoi = true;
2613 if (radv_pipeline_has_tess(pipeline)) {
2614 /* SWITCH_ON_EOI must be set if PrimID is used. */
2615 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
2616 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
2617 pipeline->graphics.ia_switch_on_eoi = true;
2618 }
2619
2620 pipeline->graphics.partial_vs_wave = false;
2621 if (radv_pipeline_has_tess(pipeline)) {
2622 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2623 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2624 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2625 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2626 radv_pipeline_has_gs(pipeline))
2627 pipeline->graphics.partial_vs_wave = true;
2628 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2629 if (device->has_distributed_tess) {
2630 if (radv_pipeline_has_gs(pipeline)) {
2631 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2632 device->physical_device->rad_info.family == CHIP_FIJI ||
2633 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2634 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2635 device->physical_device->rad_info.family == CHIP_POLARIS12)
2636 pipeline->graphics.partial_vs_wave = true;
2637 } else {
2638 pipeline->graphics.partial_vs_wave = true;
2639 }
2640 }
2641 }
2642
2643 pipeline->graphics.base_ia_multi_vgt_param =
2644 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
2645 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
2646 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
2647 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
2648 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
2649
2650 const VkPipelineVertexInputStateCreateInfo *vi_info =
2651 pCreateInfo->pVertexInputState;
2652 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2653
2654 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2655 const VkVertexInputAttributeDescription *desc =
2656 &vi_info->pVertexAttributeDescriptions[i];
2657 unsigned loc = desc->location;
2658 const struct vk_format_description *format_desc;
2659 int first_non_void;
2660 uint32_t num_format, data_format;
2661 format_desc = vk_format_description(desc->format);
2662 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2663
2664 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2665 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2666
2667 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2668 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2669 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2670 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2671 S_008F0C_NUM_FORMAT(num_format) |
2672 S_008F0C_DATA_FORMAT(data_format);
2673 velems->format_size[loc] = format_desc->block.bits / 8;
2674 velems->offset[loc] = desc->offset;
2675 velems->binding[loc] = desc->binding;
2676 velems->count = MAX2(velems->count, loc + 1);
2677 }
2678
2679 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2680 const VkVertexInputBindingDescription *desc =
2681 &vi_info->pVertexBindingDescriptions[i];
2682
2683 pipeline->binding_stride[desc->binding] = desc->stride;
2684 }
2685
2686 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2687 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
2688
2689 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2690 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2691 if (loc->sgpr_idx != -1) {
2692 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
2693 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2694 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
2695 pipeline->graphics.vtx_emit_num = 3;
2696 else
2697 pipeline->graphics.vtx_emit_num = 2;
2698 }
2699
2700 pipeline->graphics.vtx_reuse_depth = 30;
2701 if (radv_pipeline_has_tess(pipeline) &&
2702 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2703 pipeline->graphics.vtx_reuse_depth = 14;
2704 }
2705
2706 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2707 radv_dump_pipeline_stats(device, pipeline);
2708 }
2709
2710 radv_compute_binning_state(pipeline, pCreateInfo);
2711
2712 result = radv_pipeline_scratch_init(device, pipeline);
2713 return result;
2714 }
2715
2716 VkResult
2717 radv_graphics_pipeline_create(
2718 VkDevice _device,
2719 VkPipelineCache _cache,
2720 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2721 const struct radv_graphics_pipeline_create_info *extra,
2722 const VkAllocationCallbacks *pAllocator,
2723 VkPipeline *pPipeline)
2724 {
2725 RADV_FROM_HANDLE(radv_device, device, _device);
2726 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2727 struct radv_pipeline *pipeline;
2728 VkResult result;
2729
2730 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2731 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2732 if (pipeline == NULL)
2733 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2734
2735 result = radv_pipeline_init(pipeline, device, cache,
2736 pCreateInfo, extra, pAllocator);
2737 if (result != VK_SUCCESS) {
2738 radv_pipeline_destroy(device, pipeline, pAllocator);
2739 return result;
2740 }
2741
2742 *pPipeline = radv_pipeline_to_handle(pipeline);
2743
2744 return VK_SUCCESS;
2745 }
2746
2747 VkResult radv_CreateGraphicsPipelines(
2748 VkDevice _device,
2749 VkPipelineCache pipelineCache,
2750 uint32_t count,
2751 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2752 const VkAllocationCallbacks* pAllocator,
2753 VkPipeline* pPipelines)
2754 {
2755 VkResult result = VK_SUCCESS;
2756 unsigned i = 0;
2757
2758 for (; i < count; i++) {
2759 VkResult r;
2760 r = radv_graphics_pipeline_create(_device,
2761 pipelineCache,
2762 &pCreateInfos[i],
2763 NULL, pAllocator, &pPipelines[i]);
2764 if (r != VK_SUCCESS) {
2765 result = r;
2766 pPipelines[i] = VK_NULL_HANDLE;
2767 }
2768 }
2769
2770 return result;
2771 }
2772
2773 static VkResult radv_compute_pipeline_create(
2774 VkDevice _device,
2775 VkPipelineCache _cache,
2776 const VkComputePipelineCreateInfo* pCreateInfo,
2777 const VkAllocationCallbacks* pAllocator,
2778 VkPipeline* pPipeline)
2779 {
2780 RADV_FROM_HANDLE(radv_device, device, _device);
2781 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2782 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2783 struct radv_pipeline *pipeline;
2784 VkResult result;
2785
2786 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2787 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2788 if (pipeline == NULL)
2789 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2790
2791 pipeline->device = device;
2792 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2793 assert(pipeline->layout);
2794
2795 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
2796 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
2797
2798 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
2799 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2800 result = radv_pipeline_scratch_init(device, pipeline);
2801 if (result != VK_SUCCESS) {
2802 radv_pipeline_destroy(device, pipeline, pAllocator);
2803 return result;
2804 }
2805
2806 *pPipeline = radv_pipeline_to_handle(pipeline);
2807
2808 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2809 radv_dump_pipeline_stats(device, pipeline);
2810 }
2811 return VK_SUCCESS;
2812 }
2813 VkResult radv_CreateComputePipelines(
2814 VkDevice _device,
2815 VkPipelineCache pipelineCache,
2816 uint32_t count,
2817 const VkComputePipelineCreateInfo* pCreateInfos,
2818 const VkAllocationCallbacks* pAllocator,
2819 VkPipeline* pPipelines)
2820 {
2821 VkResult result = VK_SUCCESS;
2822
2823 unsigned i = 0;
2824 for (; i < count; i++) {
2825 VkResult r;
2826 r = radv_compute_pipeline_create(_device, pipelineCache,
2827 &pCreateInfos[i],
2828 pAllocator, &pPipelines[i]);
2829 if (r != VK_SUCCESS) {
2830 result = r;
2831 pPipelines[i] = VK_NULL_HANDLE;
2832 }
2833 }
2834
2835 return result;
2836 }