2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
33 #include "radv_shader.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
53 struct radv_blend_state
{
54 uint32_t blend_enable_4bit
;
55 uint32_t need_src_alpha
;
57 uint32_t cb_color_control
;
58 uint32_t cb_target_mask
;
59 uint32_t cb_target_enabled_4bit
;
60 uint32_t sx_mrt_blend_opt
[8];
61 uint32_t cb_blend_control
[8];
63 uint32_t spi_shader_col_format
;
64 uint32_t cb_shader_mask
;
65 uint32_t db_alpha_to_mask
;
67 uint32_t commutative_4bit
;
69 bool single_cb_enable
;
70 bool mrt0_is_dual_src
;
73 struct radv_dsa_order_invariance
{
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
86 struct radv_tessellation_state
{
87 uint32_t ls_hs_config
;
93 struct radv_gs_state
{
94 uint32_t vgt_gs_onchip_cntl
;
95 uint32_t vgt_gs_max_prims_per_subgroup
;
96 uint32_t vgt_esgs_ring_itemsize
;
101 radv_pipeline_destroy(struct radv_device
*device
,
102 struct radv_pipeline
*pipeline
,
103 const VkAllocationCallbacks
* allocator
)
105 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
106 if (pipeline
->shaders
[i
])
107 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
109 if (pipeline
->gs_copy_shader
)
110 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
113 free(pipeline
->cs
.buf
);
114 vk_free2(&device
->alloc
, allocator
, pipeline
);
117 void radv_DestroyPipeline(
119 VkPipeline _pipeline
,
120 const VkAllocationCallbacks
* pAllocator
)
122 RADV_FROM_HANDLE(radv_device
, device
, _device
);
123 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
128 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
131 static uint32_t get_hash_flags(struct radv_device
*device
)
133 uint32_t hash_flags
= 0;
135 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
136 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
137 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
138 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
143 radv_pipeline_scratch_init(struct radv_device
*device
,
144 struct radv_pipeline
*pipeline
)
146 unsigned scratch_bytes_per_wave
= 0;
147 unsigned max_waves
= 0;
148 unsigned min_waves
= 1;
150 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
151 if (pipeline
->shaders
[i
]) {
152 unsigned max_stage_waves
= device
->scratch_waves
;
154 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
155 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
157 max_stage_waves
= MIN2(max_stage_waves
,
158 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
159 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
160 max_waves
= MAX2(max_waves
, max_stage_waves
);
164 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
165 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
166 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
167 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
168 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
171 if (scratch_bytes_per_wave
)
172 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
174 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
179 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
180 pipeline
->max_waves
= max_waves
;
184 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
187 case VK_LOGIC_OP_CLEAR
:
188 return V_028808_ROP3_CLEAR
;
189 case VK_LOGIC_OP_AND
:
190 return V_028808_ROP3_AND
;
191 case VK_LOGIC_OP_AND_REVERSE
:
192 return V_028808_ROP3_AND_REVERSE
;
193 case VK_LOGIC_OP_COPY
:
194 return V_028808_ROP3_COPY
;
195 case VK_LOGIC_OP_AND_INVERTED
:
196 return V_028808_ROP3_AND_INVERTED
;
197 case VK_LOGIC_OP_NO_OP
:
198 return V_028808_ROP3_NO_OP
;
199 case VK_LOGIC_OP_XOR
:
200 return V_028808_ROP3_XOR
;
202 return V_028808_ROP3_OR
;
203 case VK_LOGIC_OP_NOR
:
204 return V_028808_ROP3_NOR
;
205 case VK_LOGIC_OP_EQUIVALENT
:
206 return V_028808_ROP3_EQUIVALENT
;
207 case VK_LOGIC_OP_INVERT
:
208 return V_028808_ROP3_INVERT
;
209 case VK_LOGIC_OP_OR_REVERSE
:
210 return V_028808_ROP3_OR_REVERSE
;
211 case VK_LOGIC_OP_COPY_INVERTED
:
212 return V_028808_ROP3_COPY_INVERTED
;
213 case VK_LOGIC_OP_OR_INVERTED
:
214 return V_028808_ROP3_OR_INVERTED
;
215 case VK_LOGIC_OP_NAND
:
216 return V_028808_ROP3_NAND
;
217 case VK_LOGIC_OP_SET
:
218 return V_028808_ROP3_SET
;
220 unreachable("Unhandled logic op");
225 static uint32_t si_translate_blend_function(VkBlendOp op
)
228 case VK_BLEND_OP_ADD
:
229 return V_028780_COMB_DST_PLUS_SRC
;
230 case VK_BLEND_OP_SUBTRACT
:
231 return V_028780_COMB_SRC_MINUS_DST
;
232 case VK_BLEND_OP_REVERSE_SUBTRACT
:
233 return V_028780_COMB_DST_MINUS_SRC
;
234 case VK_BLEND_OP_MIN
:
235 return V_028780_COMB_MIN_DST_SRC
;
236 case VK_BLEND_OP_MAX
:
237 return V_028780_COMB_MAX_DST_SRC
;
243 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
246 case VK_BLEND_FACTOR_ZERO
:
247 return V_028780_BLEND_ZERO
;
248 case VK_BLEND_FACTOR_ONE
:
249 return V_028780_BLEND_ONE
;
250 case VK_BLEND_FACTOR_SRC_COLOR
:
251 return V_028780_BLEND_SRC_COLOR
;
252 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
253 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
254 case VK_BLEND_FACTOR_DST_COLOR
:
255 return V_028780_BLEND_DST_COLOR
;
256 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
257 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
258 case VK_BLEND_FACTOR_SRC_ALPHA
:
259 return V_028780_BLEND_SRC_ALPHA
;
260 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
261 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
262 case VK_BLEND_FACTOR_DST_ALPHA
:
263 return V_028780_BLEND_DST_ALPHA
;
264 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
265 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
266 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
267 return V_028780_BLEND_CONSTANT_COLOR
;
268 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
269 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
270 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
271 return V_028780_BLEND_CONSTANT_ALPHA
;
272 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
273 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
274 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
275 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
276 case VK_BLEND_FACTOR_SRC1_COLOR
:
277 return V_028780_BLEND_SRC1_COLOR
;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
279 return V_028780_BLEND_INV_SRC1_COLOR
;
280 case VK_BLEND_FACTOR_SRC1_ALPHA
:
281 return V_028780_BLEND_SRC1_ALPHA
;
282 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
283 return V_028780_BLEND_INV_SRC1_ALPHA
;
289 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
292 case VK_BLEND_OP_ADD
:
293 return V_028760_OPT_COMB_ADD
;
294 case VK_BLEND_OP_SUBTRACT
:
295 return V_028760_OPT_COMB_SUBTRACT
;
296 case VK_BLEND_OP_REVERSE_SUBTRACT
:
297 return V_028760_OPT_COMB_REVSUBTRACT
;
298 case VK_BLEND_OP_MIN
:
299 return V_028760_OPT_COMB_MIN
;
300 case VK_BLEND_OP_MAX
:
301 return V_028760_OPT_COMB_MAX
;
303 return V_028760_OPT_COMB_BLEND_DISABLED
;
307 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
310 case VK_BLEND_FACTOR_ZERO
:
311 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
312 case VK_BLEND_FACTOR_ONE
:
313 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
314 case VK_BLEND_FACTOR_SRC_COLOR
:
315 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
316 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
318 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
319 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
320 case VK_BLEND_FACTOR_SRC_ALPHA
:
321 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
322 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
323 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
325 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
326 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
328 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
333 * Get rid of DST in the blend factors by commuting the operands:
334 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
336 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
337 unsigned *dst_factor
, unsigned expected_dst
,
338 unsigned replacement_src
)
340 if (*src_factor
== expected_dst
&&
341 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
342 *src_factor
= VK_BLEND_FACTOR_ZERO
;
343 *dst_factor
= replacement_src
;
345 /* Commuting the operands requires reversing subtractions. */
346 if (*func
== VK_BLEND_OP_SUBTRACT
)
347 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
348 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
349 *func
= VK_BLEND_OP_SUBTRACT
;
353 static bool si_blend_factor_uses_dst(unsigned factor
)
355 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
356 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
357 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
358 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
359 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
362 static bool is_dual_src(VkBlendFactor factor
)
365 case VK_BLEND_FACTOR_SRC1_COLOR
:
366 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
367 case VK_BLEND_FACTOR_SRC1_ALPHA
:
368 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
375 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
377 bool blend_need_alpha
)
379 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
380 unsigned format
, ntype
, swap
;
382 /* Alpha is needed for alpha-to-coverage.
383 * Blending may be with or without alpha.
385 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
386 unsigned alpha
= 0; /* exports alpha, but may not support blending */
387 unsigned blend
= 0; /* supports blending, but may not export alpha */
388 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
390 format
= radv_translate_colorformat(vk_format
);
391 ntype
= radv_translate_color_numformat(vk_format
, desc
,
392 vk_format_get_first_non_void_channel(vk_format
));
393 swap
= radv_translate_colorswap(vk_format
, false);
395 /* Choose the SPI color formats. These are required values for Stoney/RB+.
396 * Other chips have multiple choices, though they are not necessarily better.
399 case V_028C70_COLOR_5_6_5
:
400 case V_028C70_COLOR_1_5_5_5
:
401 case V_028C70_COLOR_5_5_5_1
:
402 case V_028C70_COLOR_4_4_4_4
:
403 case V_028C70_COLOR_10_11_11
:
404 case V_028C70_COLOR_11_11_10
:
405 case V_028C70_COLOR_8
:
406 case V_028C70_COLOR_8_8
:
407 case V_028C70_COLOR_8_8_8_8
:
408 case V_028C70_COLOR_10_10_10_2
:
409 case V_028C70_COLOR_2_10_10_10
:
410 if (ntype
== V_028C70_NUMBER_UINT
)
411 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
412 else if (ntype
== V_028C70_NUMBER_SINT
)
413 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
415 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
418 case V_028C70_COLOR_16
:
419 case V_028C70_COLOR_16_16
:
420 case V_028C70_COLOR_16_16_16_16
:
421 if (ntype
== V_028C70_NUMBER_UNORM
||
422 ntype
== V_028C70_NUMBER_SNORM
) {
423 /* UNORM16 and SNORM16 don't support blending */
424 if (ntype
== V_028C70_NUMBER_UNORM
)
425 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
427 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
429 /* Use 32 bits per channel for blending. */
430 if (format
== V_028C70_COLOR_16
) {
431 if (swap
== V_028C70_SWAP_STD
) { /* R */
432 blend
= V_028714_SPI_SHADER_32_R
;
433 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
434 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
435 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
438 } else if (format
== V_028C70_COLOR_16_16
) {
439 if (swap
== V_028C70_SWAP_STD
) { /* RG */
440 blend
= V_028714_SPI_SHADER_32_GR
;
441 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
442 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
443 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
446 } else /* 16_16_16_16 */
447 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
448 } else if (ntype
== V_028C70_NUMBER_UINT
)
449 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
450 else if (ntype
== V_028C70_NUMBER_SINT
)
451 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
452 else if (ntype
== V_028C70_NUMBER_FLOAT
)
453 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
458 case V_028C70_COLOR_32
:
459 if (swap
== V_028C70_SWAP_STD
) { /* R */
460 blend
= normal
= V_028714_SPI_SHADER_32_R
;
461 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
462 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
463 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
468 case V_028C70_COLOR_32_32
:
469 if (swap
== V_028C70_SWAP_STD
) { /* RG */
470 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
471 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
472 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
473 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
478 case V_028C70_COLOR_32_32_32_32
:
479 case V_028C70_COLOR_8_24
:
480 case V_028C70_COLOR_24_8
:
481 case V_028C70_COLOR_X24_8_32_FLOAT
:
482 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
486 unreachable("unhandled blend format");
489 if (blend_enable
&& blend_need_alpha
)
491 else if(blend_need_alpha
)
493 else if(blend_enable
)
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
501 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
502 struct radv_blend_state
*blend
)
504 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
505 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
506 unsigned col_format
= 0;
507 unsigned num_targets
;
509 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
512 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
513 cf
= V_028714_SPI_SHADER_ZERO
;
515 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
517 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
519 cf
= si_choose_spi_color_format(attachment
->format
,
521 blend
->need_src_alpha
& (1 << i
));
524 col_format
|= cf
<< (4 * i
);
527 if (!col_format
&& blend
->need_src_alpha
& (1 << 0)) {
528 /* When a subpass doesn't have any color attachments, write the
529 * alpha channel of MRT0 when alpha coverage is enabled because
530 * the depth attachment needs it.
532 col_format
|= V_028714_SPI_SHADER_32_AR
;
535 /* If the i-th target format is set, all previous target formats must
536 * be non-zero to avoid hangs.
538 num_targets
= (util_last_bit(col_format
) + 3) / 4;
539 for (unsigned i
= 0; i
< num_targets
; i
++) {
540 if (!(col_format
& (0xf << (i
* 4)))) {
541 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
545 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
547 if (blend
->mrt0_is_dual_src
)
548 col_format
|= (col_format
& 0xf) << 4;
549 blend
->spi_shader_col_format
= col_format
;
553 format_is_int8(VkFormat format
)
555 const struct vk_format_description
*desc
= vk_format_description(format
);
556 int channel
= vk_format_get_first_non_void_channel(format
);
558 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
559 desc
->channel
[channel
].size
== 8;
563 format_is_int10(VkFormat format
)
565 const struct vk_format_description
*desc
= vk_format_description(format
);
567 if (desc
->nr_channels
!= 4)
569 for (unsigned i
= 0; i
< 4; i
++) {
570 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
577 * Ordered so that for each i,
578 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
580 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
581 VK_FORMAT_R32_SFLOAT
,
582 VK_FORMAT_R32G32_SFLOAT
,
583 VK_FORMAT_R8G8B8A8_UNORM
,
584 VK_FORMAT_R16G16B16A16_UNORM
,
585 VK_FORMAT_R16G16B16A16_SNORM
,
586 VK_FORMAT_R16G16B16A16_UINT
,
587 VK_FORMAT_R16G16B16A16_SINT
,
588 VK_FORMAT_R32G32B32A32_SFLOAT
,
589 VK_FORMAT_R8G8B8A8_UINT
,
590 VK_FORMAT_R8G8B8A8_SINT
,
591 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
592 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
595 unsigned radv_format_meta_fs_key(VkFormat format
)
597 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
599 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
600 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
601 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
603 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
604 bool is_int8
= format_is_int8(format
);
605 bool is_int10
= format_is_int10(format
);
607 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
611 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
612 unsigned *is_int8
, unsigned *is_int10
)
614 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
615 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
619 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
620 struct radv_render_pass_attachment
*attachment
;
622 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
625 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
627 if (format_is_int8(attachment
->format
))
629 if (format_is_int10(attachment
->format
))
635 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
636 VkBlendOp op
, VkBlendFactor src
,
637 VkBlendFactor dst
, unsigned chanmask
)
639 /* Src factor is allowed when it does not depend on Dst. */
640 static const uint32_t src_allowed
=
641 (1u << VK_BLEND_FACTOR_ONE
) |
642 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
643 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
644 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
645 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
646 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
647 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
648 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
649 (1u << VK_BLEND_FACTOR_ZERO
) |
650 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
651 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
652 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
653 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
654 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
655 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
657 if (dst
== VK_BLEND_FACTOR_ONE
&&
658 (src_allowed
& (1u << src
))) {
659 /* Addition is commutative, but floating point addition isn't
660 * associative: subtle changes can be introduced via different
661 * rounding. Be conservative, only enable for min and max.
663 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
664 blend
->commutative_4bit
|= chanmask
;
668 static struct radv_blend_state
669 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
670 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
671 const struct radv_graphics_pipeline_create_info
*extra
)
673 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
674 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
675 struct radv_blend_state blend
= {0};
676 unsigned mode
= V_028808_CB_NORMAL
;
682 if (extra
&& extra
->custom_blend_mode
) {
683 blend
.single_cb_enable
= true;
684 mode
= extra
->custom_blend_mode
;
686 blend
.cb_color_control
= 0;
687 if (vkblend
->logicOpEnable
)
688 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
690 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
692 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
693 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
694 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
695 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
696 S_028B70_OFFSET_ROUND(1);
698 if (vkms
&& vkms
->alphaToCoverageEnable
) {
699 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
700 blend
.need_src_alpha
|= 0x1;
703 blend
.cb_target_mask
= 0;
704 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
705 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
706 unsigned blend_cntl
= 0;
707 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
708 VkBlendOp eqRGB
= att
->colorBlendOp
;
709 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
710 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
711 VkBlendOp eqA
= att
->alphaBlendOp
;
712 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
713 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
715 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
717 if (!att
->colorWriteMask
)
720 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
721 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
722 if (!att
->blendEnable
) {
723 blend
.cb_blend_control
[i
] = blend_cntl
;
727 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
729 blend
.mrt0_is_dual_src
= true;
731 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
732 srcRGB
= VK_BLEND_FACTOR_ONE
;
733 dstRGB
= VK_BLEND_FACTOR_ONE
;
735 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
736 srcA
= VK_BLEND_FACTOR_ONE
;
737 dstA
= VK_BLEND_FACTOR_ONE
;
740 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
742 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
745 /* Blending optimizations for RB+.
746 * These transformations don't change the behavior.
748 * First, get rid of DST in the blend factors:
749 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
751 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
752 VK_BLEND_FACTOR_DST_COLOR
,
753 VK_BLEND_FACTOR_SRC_COLOR
);
755 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
756 VK_BLEND_FACTOR_DST_COLOR
,
757 VK_BLEND_FACTOR_SRC_COLOR
);
759 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
760 VK_BLEND_FACTOR_DST_ALPHA
,
761 VK_BLEND_FACTOR_SRC_ALPHA
);
763 /* Look up the ideal settings from tables. */
764 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
765 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
766 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
767 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
769 /* Handle interdependencies. */
770 if (si_blend_factor_uses_dst(srcRGB
))
771 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
772 if (si_blend_factor_uses_dst(srcA
))
773 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
775 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
776 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
777 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
778 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
779 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
781 /* Set the final value. */
782 blend
.sx_mrt_blend_opt
[i
] =
783 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
784 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
785 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
786 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
787 S_028760_ALPHA_DST_OPT(dstA_opt
) |
788 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
789 blend_cntl
|= S_028780_ENABLE(1);
791 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
792 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
793 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
794 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
795 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
796 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
797 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
798 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
800 blend
.cb_blend_control
[i
] = blend_cntl
;
802 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
804 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
805 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
806 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
807 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
808 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
809 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
810 blend
.need_src_alpha
|= 1 << i
;
812 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
813 blend
.cb_blend_control
[i
] = 0;
814 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
817 if (pipeline
->device
->physical_device
->has_rbplus
) {
818 /* Disable RB+ blend optimizations for dual source blending. */
819 if (blend
.mrt0_is_dual_src
) {
820 for (i
= 0; i
< 8; i
++) {
821 blend
.sx_mrt_blend_opt
[i
] =
822 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
823 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
827 /* RB+ doesn't work with dual source blending, logic op and
830 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
831 mode
== V_028808_CB_RESOLVE
)
832 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
835 if (blend
.cb_target_mask
)
836 blend
.cb_color_control
|= S_028808_MODE(mode
);
838 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
840 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
844 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
847 case VK_STENCIL_OP_KEEP
:
848 return V_02842C_STENCIL_KEEP
;
849 case VK_STENCIL_OP_ZERO
:
850 return V_02842C_STENCIL_ZERO
;
851 case VK_STENCIL_OP_REPLACE
:
852 return V_02842C_STENCIL_REPLACE_TEST
;
853 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
854 return V_02842C_STENCIL_ADD_CLAMP
;
855 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
856 return V_02842C_STENCIL_SUB_CLAMP
;
857 case VK_STENCIL_OP_INVERT
:
858 return V_02842C_STENCIL_INVERT
;
859 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
860 return V_02842C_STENCIL_ADD_WRAP
;
861 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
862 return V_02842C_STENCIL_SUB_WRAP
;
868 static uint32_t si_translate_fill(VkPolygonMode func
)
871 case VK_POLYGON_MODE_FILL
:
872 return V_028814_X_DRAW_TRIANGLES
;
873 case VK_POLYGON_MODE_LINE
:
874 return V_028814_X_DRAW_LINES
;
875 case VK_POLYGON_MODE_POINT
:
876 return V_028814_X_DRAW_POINTS
;
879 return V_028814_X_DRAW_POINTS
;
883 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
885 uint32_t num_samples
= vkms
->rasterizationSamples
;
886 uint32_t ps_iter_samples
= 1;
888 if (vkms
->sampleShadingEnable
) {
889 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
890 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
892 return ps_iter_samples
;
896 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
898 return pCreateInfo
->depthTestEnable
&&
899 pCreateInfo
->depthWriteEnable
&&
900 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
904 radv_writes_stencil(const VkStencilOpState
*state
)
906 return state
->writeMask
&&
907 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
908 state
->passOp
!= VK_STENCIL_OP_KEEP
||
909 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
913 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
915 return pCreateInfo
->stencilTestEnable
&&
916 (radv_writes_stencil(&pCreateInfo
->front
) ||
917 radv_writes_stencil(&pCreateInfo
->back
));
921 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
923 return radv_is_depth_write_enabled(pCreateInfo
) ||
924 radv_is_stencil_write_enabled(pCreateInfo
);
928 radv_order_invariant_stencil_op(VkStencilOp op
)
930 /* REPLACE is normally order invariant, except when the stencil
931 * reference value is written by the fragment shader. Tracking this
932 * interaction does not seem worth the effort, so be conservative.
934 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
935 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
936 op
!= VK_STENCIL_OP_REPLACE
;
940 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
942 /* Compute whether, assuming Z writes are disabled, this stencil state
943 * is order invariant in the sense that the set of passing fragments as
944 * well as the final stencil buffer result does not depend on the order
947 return !state
->writeMask
||
948 /* The following assumes that Z writes are disabled. */
949 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
950 radv_order_invariant_stencil_op(state
->passOp
) &&
951 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
952 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
953 radv_order_invariant_stencil_op(state
->failOp
));
957 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
958 struct radv_blend_state
*blend
,
959 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
961 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
962 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
963 unsigned colormask
= blend
->cb_target_enabled_4bit
;
965 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
968 /* Be conservative if a logic operation is enabled with color buffers. */
969 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
972 /* Default depth/stencil invariance when no attachment is bound. */
973 struct radv_dsa_order_invariance dsa_order_invariant
= {
974 .zs
= true, .pass_set
= true
977 if (pCreateInfo
->pDepthStencilState
&&
978 subpass
->depth_stencil_attachment
) {
979 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
980 pCreateInfo
->pDepthStencilState
;
981 struct radv_render_pass_attachment
*attachment
=
982 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
983 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
984 struct radv_dsa_order_invariance order_invariance
[2];
985 struct radv_shader_variant
*ps
=
986 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
988 /* Compute depth/stencil order invariance in order to know if
989 * it's safe to enable out-of-order.
991 bool zfunc_is_ordered
=
992 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
993 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
994 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
995 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
996 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
998 bool nozwrite_and_order_invariant_stencil
=
999 !radv_is_ds_write_enabled(vkds
) ||
1000 (!radv_is_depth_write_enabled(vkds
) &&
1001 radv_order_invariant_stencil_state(&vkds
->front
) &&
1002 radv_order_invariant_stencil_state(&vkds
->back
));
1004 order_invariance
[1].zs
=
1005 nozwrite_and_order_invariant_stencil
||
1006 (!radv_is_stencil_write_enabled(vkds
) &&
1008 order_invariance
[0].zs
=
1009 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1011 order_invariance
[1].pass_set
=
1012 nozwrite_and_order_invariant_stencil
||
1013 (!radv_is_stencil_write_enabled(vkds
) &&
1014 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1015 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1016 order_invariance
[0].pass_set
=
1017 !radv_is_depth_write_enabled(vkds
) ||
1018 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1019 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1021 dsa_order_invariant
= order_invariance
[has_stencil
];
1022 if (!dsa_order_invariant
.zs
)
1025 /* The set of PS invocations is always order invariant,
1026 * except when early Z/S tests are requested.
1029 ps
->info
.info
.ps
.writes_memory
&&
1030 ps
->info
.fs
.early_fragment_test
&&
1031 !dsa_order_invariant
.pass_set
)
1034 /* Determine if out-of-order rasterization should be disabled
1035 * when occlusion queries are used.
1037 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1038 !dsa_order_invariant
.pass_set
;
1041 /* No color buffers are enabled for writing. */
1045 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1048 /* Only commutative blending. */
1049 if (blendmask
& ~blend
->commutative_4bit
)
1052 if (!dsa_order_invariant
.pass_set
)
1056 if (colormask
& ~blendmask
)
1063 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1064 struct radv_blend_state
*blend
,
1065 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1067 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1068 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1069 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1070 bool out_of_order_rast
= false;
1071 int ps_iter_samples
= 1;
1072 uint32_t mask
= 0xffff;
1075 ms
->num_samples
= vkms
->rasterizationSamples
;
1077 ms
->num_samples
= 1;
1080 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1081 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.force_persample
) {
1082 ps_iter_samples
= ms
->num_samples
;
1085 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1086 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1087 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1088 /* Out-of-order rasterization is explicitly enabled by the
1091 out_of_order_rast
= true;
1093 /* Determine if the driver can enable out-of-order
1094 * rasterization internally.
1097 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1100 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1101 ms
->pa_sc_aa_config
= 0;
1102 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1103 S_028804_INCOHERENT_EQAA_READS(1) |
1104 S_028804_INTERPOLATE_COMP_Z(1) |
1105 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1106 ms
->pa_sc_mode_cntl_1
=
1107 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1108 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1109 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1110 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1112 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1113 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1114 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1115 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1116 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1117 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1118 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1119 S_028A48_VPORT_SCISSOR_ENABLE(1);
1121 if (ms
->num_samples
> 1) {
1122 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1123 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1124 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1125 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1126 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1127 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1128 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1129 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1130 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1131 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1132 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1133 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1134 if (ps_iter_samples
> 1)
1135 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1138 if (vkms
&& vkms
->pSampleMask
) {
1139 mask
= vkms
->pSampleMask
[0] & 0xffff;
1142 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1143 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1147 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1150 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1151 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1152 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1153 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1154 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1156 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1157 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1158 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1159 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1160 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1161 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1164 unreachable("unhandled primitive type");
1169 si_translate_prim(enum VkPrimitiveTopology topology
)
1172 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1173 return V_008958_DI_PT_POINTLIST
;
1174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1175 return V_008958_DI_PT_LINELIST
;
1176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1177 return V_008958_DI_PT_LINESTRIP
;
1178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1179 return V_008958_DI_PT_TRILIST
;
1180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1181 return V_008958_DI_PT_TRISTRIP
;
1182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1183 return V_008958_DI_PT_TRIFAN
;
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1185 return V_008958_DI_PT_LINELIST_ADJ
;
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1187 return V_008958_DI_PT_LINESTRIP_ADJ
;
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1189 return V_008958_DI_PT_TRILIST_ADJ
;
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1191 return V_008958_DI_PT_TRISTRIP_ADJ
;
1192 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1193 return V_008958_DI_PT_PATCH
;
1201 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1204 case 0: /* GL_POINTS */
1205 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1206 case 1: /* GL_LINES */
1207 case 3: /* GL_LINE_STRIP */
1208 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1209 case 0x8E7A: /* GL_ISOLINES */
1210 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1212 case 4: /* GL_TRIANGLES */
1213 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1214 case 5: /* GL_TRIANGLE_STRIP */
1215 case 7: /* GL_QUADS */
1216 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1224 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1227 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1228 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1229 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1234 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1240 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1247 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1250 case VK_DYNAMIC_STATE_VIEWPORT
:
1251 return RADV_DYNAMIC_VIEWPORT
;
1252 case VK_DYNAMIC_STATE_SCISSOR
:
1253 return RADV_DYNAMIC_SCISSOR
;
1254 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1255 return RADV_DYNAMIC_LINE_WIDTH
;
1256 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1257 return RADV_DYNAMIC_DEPTH_BIAS
;
1258 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1259 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1260 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1261 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1262 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1263 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1264 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1265 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1266 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1267 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1268 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1269 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1270 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1271 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1273 unreachable("Unhandled dynamic state");
1277 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1279 uint32_t states
= RADV_DYNAMIC_ALL
;
1281 /* If rasterization is disabled we do not care about any of the dynamic states,
1282 * since they are all rasterization related only. */
1283 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1286 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1287 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1289 if (!pCreateInfo
->pDepthStencilState
||
1290 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1291 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1293 if (!pCreateInfo
->pDepthStencilState
||
1294 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1295 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1296 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1297 RADV_DYNAMIC_STENCIL_REFERENCE
);
1299 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1300 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1302 if (!pCreateInfo
->pMultisampleState
||
1303 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1304 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1305 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1307 /* TODO: blend constants & line width. */
1314 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1315 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1317 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1318 uint32_t states
= needed_states
;
1319 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1320 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1322 pipeline
->dynamic_state
= default_dynamic_state
;
1323 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1325 if (pCreateInfo
->pDynamicState
) {
1326 /* Remove all of the states that are marked as dynamic */
1327 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1328 for (uint32_t s
= 0; s
< count
; s
++)
1329 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1332 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1334 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1335 assert(pCreateInfo
->pViewportState
);
1337 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1338 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1339 typed_memcpy(dynamic
->viewport
.viewports
,
1340 pCreateInfo
->pViewportState
->pViewports
,
1341 pCreateInfo
->pViewportState
->viewportCount
);
1345 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1346 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1347 if (states
& RADV_DYNAMIC_SCISSOR
) {
1348 typed_memcpy(dynamic
->scissor
.scissors
,
1349 pCreateInfo
->pViewportState
->pScissors
,
1350 pCreateInfo
->pViewportState
->scissorCount
);
1354 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1355 assert(pCreateInfo
->pRasterizationState
);
1356 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1359 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1360 assert(pCreateInfo
->pRasterizationState
);
1361 dynamic
->depth_bias
.bias
=
1362 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1363 dynamic
->depth_bias
.clamp
=
1364 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1365 dynamic
->depth_bias
.slope
=
1366 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1369 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1371 * pColorBlendState is [...] NULL if the pipeline has rasterization
1372 * disabled or if the subpass of the render pass the pipeline is
1373 * created against does not use any color attachments.
1375 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1376 assert(pCreateInfo
->pColorBlendState
);
1377 typed_memcpy(dynamic
->blend_constants
,
1378 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1381 /* If there is no depthstencil attachment, then don't read
1382 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1383 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1384 * no need to override the depthstencil defaults in
1385 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1387 * Section 9.2 of the Vulkan 1.0.15 spec says:
1389 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1390 * disabled or if the subpass of the render pass the pipeline is created
1391 * against does not use a depth/stencil attachment.
1393 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1394 assert(pCreateInfo
->pDepthStencilState
);
1396 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1397 dynamic
->depth_bounds
.min
=
1398 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1399 dynamic
->depth_bounds
.max
=
1400 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1403 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1404 dynamic
->stencil_compare_mask
.front
=
1405 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1406 dynamic
->stencil_compare_mask
.back
=
1407 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1410 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1411 dynamic
->stencil_write_mask
.front
=
1412 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1413 dynamic
->stencil_write_mask
.back
=
1414 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1417 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1418 dynamic
->stencil_reference
.front
=
1419 pCreateInfo
->pDepthStencilState
->front
.reference
;
1420 dynamic
->stencil_reference
.back
=
1421 pCreateInfo
->pDepthStencilState
->back
.reference
;
1425 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1426 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1427 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1428 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1429 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1430 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1431 discard_rectangle_info
->pDiscardRectangles
,
1432 discard_rectangle_info
->discardRectangleCount
);
1436 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1437 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1438 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1439 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1440 /* If sampleLocationsEnable is VK_FALSE, the default sample
1441 * locations are used and the values specified in
1442 * sampleLocationsInfo are ignored.
1444 if (sample_location_info
->sampleLocationsEnable
) {
1445 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1446 &sample_location_info
->sampleLocationsInfo
;
1448 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1450 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1451 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1452 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1453 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1454 pSampleLocationsInfo
->pSampleLocations
,
1455 pSampleLocationsInfo
->sampleLocationsCount
);
1459 pipeline
->dynamic_state
.mask
= states
;
1462 static struct radv_gs_state
1463 calculate_gs_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1464 const struct radv_pipeline
*pipeline
)
1466 struct radv_gs_state gs
= {0};
1467 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1468 struct radv_es_output_info
*es_info
;
1469 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1470 es_info
= radv_pipeline_has_tess(pipeline
) ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1472 es_info
= radv_pipeline_has_tess(pipeline
) ?
1473 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1474 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1476 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1477 bool uses_adjacency
;
1478 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1479 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1480 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1481 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1482 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1483 uses_adjacency
= true;
1486 uses_adjacency
= false;
1490 /* All these are in dwords: */
1491 /* We can't allow using the whole LDS, because GS waves compete with
1492 * other shader stages for LDS space. */
1493 const unsigned max_lds_size
= 8 * 1024;
1494 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1495 unsigned esgs_lds_size
;
1497 /* All these are per subgroup: */
1498 const unsigned max_out_prims
= 32 * 1024;
1499 const unsigned max_es_verts
= 255;
1500 const unsigned ideal_gs_prims
= 64;
1501 unsigned max_gs_prims
, gs_prims
;
1502 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1504 if (uses_adjacency
|| gs_num_invocations
> 1)
1505 max_gs_prims
= 127 / gs_num_invocations
;
1509 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1510 * Make sure we don't go over the maximum value.
1512 if (gs_info
->gs
.vertices_out
> 0) {
1513 max_gs_prims
= MIN2(max_gs_prims
,
1515 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1517 assert(max_gs_prims
> 0);
1519 /* If the primitive has adjacency, halve the number of vertices
1520 * that will be reused in multiple primitives.
1522 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1524 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1525 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1527 /* Compute ESGS LDS size based on the worst case number of ES vertices
1528 * needed to create the target number of GS prims per subgroup.
1530 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1532 /* If total LDS usage is too big, refactor partitions based on ratio
1533 * of ESGS item sizes.
1535 if (esgs_lds_size
> max_lds_size
) {
1536 /* Our target GS Prims Per Subgroup was too large. Calculate
1537 * the maximum number of GS Prims Per Subgroup that will fit
1538 * into LDS, capped by the maximum that the hardware can support.
1540 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1542 assert(gs_prims
> 0);
1543 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1546 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1547 assert(esgs_lds_size
<= max_lds_size
);
1550 /* Now calculate remaining ESGS information. */
1552 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1554 es_verts
= max_es_verts
;
1556 /* Vertices for adjacency primitives are not always reused, so restore
1557 * it for ES_VERTS_PER_SUBGRP.
1559 min_es_verts
= gs_info
->gs
.vertices_in
;
1561 /* For normal primitives, the VGT only checks if they are past the ES
1562 * verts per subgroup after allocating a full GS primitive and if they
1563 * are, kick off a new subgroup. But if those additional ES verts are
1564 * unique (e.g. not reused) we need to make sure there is enough LDS
1565 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1567 es_verts
-= min_es_verts
- 1;
1569 uint32_t es_verts_per_subgroup
= es_verts
;
1570 uint32_t gs_prims_per_subgroup
= gs_prims
;
1571 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1572 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1573 gs
.lds_size
= align(esgs_lds_size
, 128) / 128;
1574 gs
.vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1575 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1576 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1577 gs
.vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1578 gs
.vgt_esgs_ring_itemsize
= esgs_itemsize
;
1579 assert(max_prims_per_subgroup
<= max_out_prims
);
1585 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
, const struct radv_gs_state
*gs
)
1587 struct radv_device
*device
= pipeline
->device
;
1588 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1589 unsigned wave_size
= 64;
1590 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1591 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1592 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1594 unsigned gs_vertex_reuse
=
1595 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1596 unsigned alignment
= 256 * num_se
;
1597 /* The maximum size is 63.999 MB per SE. */
1598 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1599 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1601 /* Calculate the minimum size. */
1602 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1603 wave_size
, alignment
);
1604 /* These are recommended sizes, not minimum sizes. */
1605 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1606 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1607 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1608 gs_info
->gs
.max_gsvs_emit_size
;
1610 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1611 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1612 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1614 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1615 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1617 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1620 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1623 /* If tessellation is all offchip and on-chip GS isn't used, this
1624 * workaround is not needed.
1628 /* SPI barrier management bug:
1629 * Make sure we have at least 4k of LDS in use to avoid the bug.
1630 * It applies to workgroup sizes of more than one wavefront.
1632 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1633 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1634 *lds_size
= MAX2(*lds_size
, 8);
1637 struct radv_shader_variant
*
1638 radv_get_shader(struct radv_pipeline
*pipeline
,
1639 gl_shader_stage stage
)
1641 if (stage
== MESA_SHADER_VERTEX
) {
1642 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1643 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1644 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1645 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1646 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1647 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1648 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1649 if (!radv_pipeline_has_tess(pipeline
))
1651 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1652 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1653 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1654 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1656 return pipeline
->shaders
[stage
];
1659 static struct radv_tessellation_state
1660 calculate_tess_state(struct radv_pipeline
*pipeline
,
1661 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1663 unsigned num_tcs_input_cp
;
1664 unsigned num_tcs_output_cp
;
1666 unsigned num_patches
;
1667 struct radv_tessellation_state tess
= {0};
1669 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1670 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1671 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1673 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1675 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1676 assert(lds_size
<= 65536);
1677 lds_size
= align(lds_size
, 512) / 512;
1679 assert(lds_size
<= 32768);
1680 lds_size
= align(lds_size
, 256) / 256;
1682 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1684 tess
.lds_size
= lds_size
;
1686 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1687 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1688 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1689 tess
.num_patches
= num_patches
;
1691 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1692 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1694 switch (tes
->info
.tes
.primitive_mode
) {
1696 type
= V_028B6C_TESS_TRIANGLE
;
1699 type
= V_028B6C_TESS_QUAD
;
1702 type
= V_028B6C_TESS_ISOLINE
;
1706 switch (tes
->info
.tes
.spacing
) {
1707 case TESS_SPACING_EQUAL
:
1708 partitioning
= V_028B6C_PART_INTEGER
;
1710 case TESS_SPACING_FRACTIONAL_ODD
:
1711 partitioning
= V_028B6C_PART_FRAC_ODD
;
1713 case TESS_SPACING_FRACTIONAL_EVEN
:
1714 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1720 bool ccw
= tes
->info
.tes
.ccw
;
1721 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1722 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1723 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
1725 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
1728 if (tes
->info
.tes
.point_mode
)
1729 topology
= V_028B6C_OUTPUT_POINT
;
1730 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1731 topology
= V_028B6C_OUTPUT_LINE
;
1733 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
1735 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
1737 if (pipeline
->device
->has_distributed_tess
) {
1738 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
1739 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
1740 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
1742 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
1744 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
1746 tess
.tf_param
= S_028B6C_TYPE(type
) |
1747 S_028B6C_PARTITIONING(partitioning
) |
1748 S_028B6C_TOPOLOGY(topology
) |
1749 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
1754 static const struct radv_prim_vertex_count prim_size_table
[] = {
1755 [V_008958_DI_PT_NONE
] = {0, 0},
1756 [V_008958_DI_PT_POINTLIST
] = {1, 1},
1757 [V_008958_DI_PT_LINELIST
] = {2, 2},
1758 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
1759 [V_008958_DI_PT_TRILIST
] = {3, 3},
1760 [V_008958_DI_PT_TRIFAN
] = {3, 1},
1761 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
1762 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
1763 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
1764 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
1765 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
1766 [V_008958_DI_PT_RECTLIST
] = {3, 3},
1767 [V_008958_DI_PT_LINELOOP
] = {2, 1},
1768 [V_008958_DI_PT_POLYGON
] = {3, 1},
1769 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
1772 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
1774 if (radv_pipeline_has_gs(pipeline
))
1775 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
1776 else if (radv_pipeline_has_tess(pipeline
))
1777 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
1779 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
1783 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
1785 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
1786 int shader_count
= 0;
1788 if(shaders
[MESA_SHADER_FRAGMENT
]) {
1789 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
1791 if(shaders
[MESA_SHADER_GEOMETRY
]) {
1792 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
1794 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
1795 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
1797 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
1798 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
1800 if(shaders
[MESA_SHADER_VERTEX
]) {
1801 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
1804 if (shader_count
> 1) {
1805 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
1806 unsigned last
= ordered_shaders
[0]->info
.stage
;
1808 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
1809 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
1810 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
1812 for (int i
= 0; i
< shader_count
; ++i
) {
1813 nir_variable_mode mask
= 0;
1815 if (ordered_shaders
[i
]->info
.stage
!= first
)
1816 mask
= mask
| nir_var_shader_in
;
1818 if (ordered_shaders
[i
]->info
.stage
!= last
)
1819 mask
= mask
| nir_var_shader_out
;
1821 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
1822 radv_optimize_nir(ordered_shaders
[i
], false, false);
1826 for (int i
= 1; i
< shader_count
; ++i
) {
1827 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
1828 ordered_shaders
[i
- 1]);
1830 if (nir_link_opt_varyings(ordered_shaders
[i
],
1831 ordered_shaders
[i
- 1]))
1832 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
1834 nir_remove_dead_variables(ordered_shaders
[i
],
1835 nir_var_shader_out
);
1836 nir_remove_dead_variables(ordered_shaders
[i
- 1],
1839 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
1840 ordered_shaders
[i
- 1]);
1842 nir_compact_varyings(ordered_shaders
[i
],
1843 ordered_shaders
[i
- 1], true);
1846 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
1847 ac_lower_indirect_derefs(ordered_shaders
[i
],
1848 pipeline
->device
->physical_device
->rad_info
.chip_class
);
1850 radv_optimize_nir(ordered_shaders
[i
], false, false);
1852 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
1853 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
1854 pipeline
->device
->physical_device
->rad_info
.chip_class
);
1856 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
1862 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
1863 uint32_t attrib_binding
)
1865 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
1866 const VkVertexInputBindingDescription
*input_binding
=
1867 &input_state
->pVertexBindingDescriptions
[i
];
1869 if (input_binding
->binding
== attrib_binding
)
1870 return input_binding
->stride
;
1876 static struct radv_pipeline_key
1877 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
1878 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1879 const struct radv_blend_state
*blend
,
1880 bool has_view_index
)
1882 const VkPipelineVertexInputStateCreateInfo
*input_state
=
1883 pCreateInfo
->pVertexInputState
;
1884 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
1885 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1887 struct radv_pipeline_key key
;
1888 memset(&key
, 0, sizeof(key
));
1890 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
1891 key
.optimisations_disabled
= 1;
1893 key
.has_multiview_view_index
= has_view_index
;
1895 uint32_t binding_input_rate
= 0;
1896 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
1897 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
1898 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
1899 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
1900 binding_input_rate
|= 1u << binding
;
1901 instance_rate_divisors
[binding
] = 1;
1904 if (divisor_state
) {
1905 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
1906 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
1907 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
1911 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
1912 const VkVertexInputAttributeDescription
*desc
=
1913 &input_state
->pVertexAttributeDescriptions
[i
];
1914 const struct vk_format_description
*format_desc
;
1915 unsigned location
= desc
->location
;
1916 unsigned binding
= desc
->binding
;
1917 unsigned num_format
, data_format
;
1920 if (binding_input_rate
& (1u << binding
)) {
1921 key
.instance_rate_inputs
|= 1u << location
;
1922 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
1925 format_desc
= vk_format_description(desc
->format
);
1926 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
1928 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
1929 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
1931 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
1932 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
1933 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
1934 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
1936 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
1937 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
1938 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
1941 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
1942 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
1943 adjust
= RADV_ALPHA_ADJUST_SNORM
;
1945 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
1946 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
1947 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
1949 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
1950 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
1951 adjust
= RADV_ALPHA_ADJUST_SINT
;
1957 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
1960 switch (desc
->format
) {
1961 case VK_FORMAT_B8G8R8A8_UNORM
:
1962 case VK_FORMAT_B8G8R8A8_SNORM
:
1963 case VK_FORMAT_B8G8R8A8_USCALED
:
1964 case VK_FORMAT_B8G8R8A8_SSCALED
:
1965 case VK_FORMAT_B8G8R8A8_UINT
:
1966 case VK_FORMAT_B8G8R8A8_SINT
:
1967 case VK_FORMAT_B8G8R8A8_SRGB
:
1968 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
1969 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
1970 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
1971 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
1972 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
1973 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
1974 key
.vertex_post_shuffle
|= 1 << location
;
1981 if (pCreateInfo
->pTessellationState
)
1982 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1985 if (pCreateInfo
->pMultisampleState
&&
1986 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
1987 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
1988 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
1989 key
.num_samples
= num_samples
;
1990 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1993 key
.col_format
= blend
->spi_shader_col_format
;
1994 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
1995 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2001 radv_fill_shader_keys(struct radv_shader_variant_key
*keys
,
2002 const struct radv_pipeline_key
*key
,
2005 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2006 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2007 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2008 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2009 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2010 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2011 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2012 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2013 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2016 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2017 keys
[MESA_SHADER_VERTEX
].vs
.as_ls
= true;
2018 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2019 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2020 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2022 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2025 if (nir
[MESA_SHADER_GEOMETRY
]) {
2026 if (nir
[MESA_SHADER_TESS_CTRL
])
2027 keys
[MESA_SHADER_TESS_EVAL
].tes
.as_es
= true;
2029 keys
[MESA_SHADER_VERTEX
].vs
.as_es
= true;
2032 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2033 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2035 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2036 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2037 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2038 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2039 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2043 merge_tess_info(struct shader_info
*tes_info
,
2044 const struct shader_info
*tcs_info
)
2046 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2048 * "PointMode. Controls generation of points rather than triangles
2049 * or lines. This functionality defaults to disabled, and is
2050 * enabled if either shader stage includes the execution mode.
2052 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2053 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2054 * and OutputVertices, it says:
2056 * "One mode must be set in at least one of the tessellation
2059 * So, the fields can be set in either the TCS or TES, but they must
2060 * agree if set in both. Our backend looks at TES, so bitwise-or in
2061 * the values from the TCS.
2063 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2064 tes_info
->tess
.tcs_vertices_out
== 0 ||
2065 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2066 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2068 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2069 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2070 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2071 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2073 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2074 tes_info
->tess
.primitive_mode
== 0 ||
2075 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2076 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2077 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2078 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2082 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2087 if (ext
->pPipelineCreationFeedback
) {
2088 ext
->pPipelineCreationFeedback
->flags
= 0;
2089 ext
->pPipelineCreationFeedback
->duration
= 0;
2092 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2093 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2094 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2099 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2104 feedback
->duration
-= radv_get_current_time();
2105 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2109 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2114 feedback
->duration
+= radv_get_current_time();
2115 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2116 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2120 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2121 struct radv_device
*device
,
2122 struct radv_pipeline_cache
*cache
,
2123 const struct radv_pipeline_key
*key
,
2124 const VkPipelineShaderStageCreateInfo
**pStages
,
2125 const VkPipelineCreateFlags flags
,
2126 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2127 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2129 struct radv_shader_module fs_m
= {0};
2130 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2131 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2132 void *codes
[MESA_SHADER_STAGES
] = {0};
2133 unsigned code_sizes
[MESA_SHADER_STAGES
] = {0};
2134 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{0}}}};
2135 unsigned char hash
[20], gs_copy_hash
[20];
2137 radv_start_feedback(pipeline_feedback
);
2139 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2141 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2142 if (modules
[i
]->nir
)
2143 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2144 strlen(modules
[i
]->nir
->info
.name
),
2147 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2151 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2152 memcpy(gs_copy_hash
, hash
, 20);
2153 gs_copy_hash
[0] ^= 1;
2155 bool found_in_application_cache
= true;
2156 if (modules
[MESA_SHADER_GEOMETRY
]) {
2157 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2158 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2159 &found_in_application_cache
);
2160 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2163 if (radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2164 &found_in_application_cache
) &&
2165 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2166 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2170 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2172 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2173 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2174 fs_m
.nir
= fs_b
.shader
;
2175 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2178 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2179 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2184 radv_start_feedback(stage_feedbacks
[i
]);
2186 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2187 stage
? stage
->pName
: "main", i
,
2188 stage
? stage
->pSpecializationInfo
: NULL
,
2189 flags
, pipeline
->layout
);
2191 /* We don't want to alter meta shaders IR directly so clone it
2194 if (nir
[i
]->info
.name
) {
2195 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2198 radv_stop_feedback(stage_feedbacks
[i
], false);
2201 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2202 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2203 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2206 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2207 radv_link_shaders(pipeline
, nir
);
2209 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2211 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2212 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2213 nir_lower_non_uniform_ubo_access
|
2214 nir_lower_non_uniform_ssbo_access
|
2215 nir_lower_non_uniform_texture_access
|
2216 nir_lower_non_uniform_image_access
);
2219 if (radv_can_dump_shader(device
, modules
[i
], false))
2220 nir_print_shader(nir
[i
], stderr
);
2223 radv_fill_shader_keys(keys
, key
, nir
);
2225 if (nir
[MESA_SHADER_FRAGMENT
]) {
2226 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2227 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2229 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2230 radv_shader_variant_create(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2231 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2232 &codes
[MESA_SHADER_FRAGMENT
], &code_sizes
[MESA_SHADER_FRAGMENT
]);
2234 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2237 /* TODO: These are no longer used as keys we should refactor this */
2238 keys
[MESA_SHADER_VERTEX
].vs
.export_prim_id
=
2239 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2240 keys
[MESA_SHADER_VERTEX
].vs
.export_layer_id
=
2241 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2242 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_prim_id
=
2243 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2244 keys
[MESA_SHADER_TESS_EVAL
].tes
.export_layer_id
=
2245 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2248 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2249 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2250 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2251 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2252 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2254 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2256 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2258 &key
, &codes
[MESA_SHADER_TESS_CTRL
],
2259 &code_sizes
[MESA_SHADER_TESS_CTRL
]);
2261 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2263 modules
[MESA_SHADER_VERTEX
] = NULL
;
2264 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2265 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2268 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2269 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2270 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2271 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2273 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2275 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_create(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2277 &keys
[pre_stage
] , &codes
[MESA_SHADER_GEOMETRY
],
2278 &code_sizes
[MESA_SHADER_GEOMETRY
]);
2280 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2282 modules
[pre_stage
] = NULL
;
2285 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2286 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2287 if (i
== MESA_SHADER_TESS_CTRL
) {
2288 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.ls_outputs_written
);
2290 if (i
== MESA_SHADER_TESS_EVAL
) {
2291 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2292 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2295 radv_start_feedback(stage_feedbacks
[i
]);
2297 pipeline
->shaders
[i
] = radv_shader_variant_create(device
, modules
[i
], &nir
[i
], 1,
2299 keys
+ i
, &codes
[i
],
2302 radv_stop_feedback(stage_feedbacks
[i
], false);
2306 if(modules
[MESA_SHADER_GEOMETRY
]) {
2307 void *gs_copy_code
= NULL
;
2308 unsigned gs_copy_code_size
= 0;
2309 if (!pipeline
->gs_copy_shader
) {
2310 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2311 device
, nir
[MESA_SHADER_GEOMETRY
], &gs_copy_code
,
2313 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2316 if (pipeline
->gs_copy_shader
) {
2317 void *code
[MESA_SHADER_STAGES
] = {0};
2318 unsigned code_size
[MESA_SHADER_STAGES
] = {0};
2319 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2321 code
[MESA_SHADER_GEOMETRY
] = gs_copy_code
;
2322 code_size
[MESA_SHADER_GEOMETRY
] = gs_copy_code_size
;
2323 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2325 radv_pipeline_cache_insert_shaders(device
, cache
,
2334 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2335 (const void**)codes
, code_sizes
);
2337 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2340 if (!pipeline
->device
->keep_shader_info
)
2341 ralloc_free(nir
[i
]);
2343 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2344 radv_shader_dump_stats(device
,
2345 pipeline
->shaders
[i
],
2351 ralloc_free(fs_m
.nir
);
2353 radv_stop_feedback(pipeline_feedback
, false);
2357 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2358 gl_shader_stage stage
, enum chip_class chip_class
)
2360 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2361 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2363 case MESA_SHADER_FRAGMENT
:
2364 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2365 case MESA_SHADER_VERTEX
:
2366 if (chip_class
>= GFX9
) {
2367 return has_tess
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2368 has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2369 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2372 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2374 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2375 case MESA_SHADER_GEOMETRY
:
2376 return chip_class
>= GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2377 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2378 case MESA_SHADER_COMPUTE
:
2379 return R_00B900_COMPUTE_USER_DATA_0
;
2380 case MESA_SHADER_TESS_CTRL
:
2381 return chip_class
>= GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2382 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2383 case MESA_SHADER_TESS_EVAL
:
2384 if (chip_class
>= GFX9
) {
2385 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2386 R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2389 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2391 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2393 unreachable("unknown shader");
2397 struct radv_bin_size_entry
{
2403 radv_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2405 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2409 /* One shader engine */
2415 { UINT_MAX
, { 0, 0}},
2418 /* Two shader engines */
2424 { UINT_MAX
, { 0, 0}},
2427 /* Four shader engines */
2432 { UINT_MAX
, { 0, 0}},
2438 /* One shader engine */
2444 { UINT_MAX
, { 0, 0}},
2447 /* Two shader engines */
2453 { UINT_MAX
, { 0, 0}},
2456 /* Four shader engines */
2463 { UINT_MAX
, { 0, 0}},
2469 /* One shader engine */
2476 { UINT_MAX
, { 0, 0}},
2479 /* Two shader engines */
2487 { UINT_MAX
, { 0, 0}},
2490 /* Four shader engines */
2498 { UINT_MAX
, { 0, 0}},
2502 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
2506 // One shader engine
2513 { UINT_MAX
, { 0, 0}},
2516 // Two shader engines
2524 { UINT_MAX
, { 0, 0}},
2527 // Four shader engines
2535 { UINT_MAX
, { 0, 0}},
2541 // One shader engine
2549 { UINT_MAX
, { 0, 0}},
2552 // Two shader engines
2561 { UINT_MAX
, { 0, 0}},
2564 // Four shader engines
2573 { UINT_MAX
, { 0, 0}},
2579 // One shader engine
2587 { UINT_MAX
, { 0, 0}},
2590 // Two shader engines
2599 { UINT_MAX
, { 0, 0}},
2602 // Four shader engines
2610 { UINT_MAX
, { 0, 0}},
2615 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2616 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2617 VkExtent2D extent
= {512, 512};
2619 unsigned log_num_rb_per_se
=
2620 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
2621 pipeline
->device
->physical_device
->rad_info
.max_se
);
2622 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
2624 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
2625 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
2626 unsigned effective_samples
= total_samples
;
2627 unsigned color_bytes_per_pixel
= 0;
2629 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
2631 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2632 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
2635 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
2638 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
2639 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
2642 /* MSAA images typically don't use all samples all the time. */
2643 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
2644 effective_samples
= 2;
2645 color_bytes_per_pixel
*= effective_samples
;
2648 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
2649 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
2652 extent
= color_entry
->extent
;
2654 if (subpass
->depth_stencil_attachment
) {
2655 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
2657 /* Coefficients taken from AMDVLK */
2658 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
2659 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
2660 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
2662 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
2663 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
2666 extent
.width
= MIN2(extent
.width
, ds_entry
->extent
.width
);
2667 extent
.height
= MIN2(extent
.height
, ds_entry
->extent
.height
);
2674 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
2675 struct radv_pipeline
*pipeline
,
2676 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2678 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
2681 uint32_t pa_sc_binner_cntl_0
=
2682 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
2683 S_028C44_DISABLE_START_OF_PRIM(1);
2684 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
2686 VkExtent2D bin_size
= radv_compute_bin_size(pipeline
, pCreateInfo
);
2688 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
2689 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
2690 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
2692 switch (pipeline
->device
->physical_device
->rad_info
.family
) {
2696 context_states_per_bin
= 1;
2697 persistent_states_per_bin
= 1;
2698 fpovs_per_batch
= 63;
2702 context_states_per_bin
= 6;
2703 persistent_states_per_bin
= 32;
2704 fpovs_per_batch
= 63;
2707 unreachable("unhandled family while determining binning state.");
2710 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
2711 pa_sc_binner_cntl_0
=
2712 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
2713 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
2714 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
2715 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
2716 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
2717 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
2718 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
2719 S_028C44_DISABLE_START_OF_PRIM(1) |
2720 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
2721 S_028C44_OPTIMAL_BIN_SELECTION(1);
2724 radeon_set_context_reg(ctx_cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
2725 pa_sc_binner_cntl_0
);
2726 radeon_set_context_reg(ctx_cs
, R_028060_DB_DFSM_CONTROL
,
2732 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
2733 struct radv_pipeline
*pipeline
,
2734 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2735 const struct radv_graphics_pipeline_create_info
*extra
)
2737 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
2738 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2739 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2740 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
2741 struct radv_render_pass_attachment
*attachment
= NULL
;
2742 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
2743 uint32_t db_render_control
= 0, db_render_override2
= 0;
2744 uint32_t db_render_override
= 0;
2746 if (subpass
->depth_stencil_attachment
)
2747 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
2749 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
2750 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
2752 if (vkds
&& has_depth_attachment
) {
2753 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
2754 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
2755 S_028800_ZFUNC(vkds
->depthCompareOp
) |
2756 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
2758 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2759 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
2762 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
2763 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2764 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
2765 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
2766 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
2767 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
2769 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
2770 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
2771 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
2772 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
2775 if (attachment
&& extra
) {
2776 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
2777 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
2779 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
2780 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
2781 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
2782 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
2783 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
2786 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
2787 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
2789 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
2790 ps
->info
.info
.ps
.writes_z
) {
2791 /* From VK_EXT_depth_range_unrestricted spec:
2793 * "The behavior described in Primitive Clipping still applies.
2794 * If depth clamping is disabled the depth values are still
2795 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2796 * depth clamping is enabled the above equation is ignored and
2797 * the depth values are instead clamped to the VkViewport
2798 * minDepth and maxDepth values, which in the case of this
2799 * extension can be outside of the 0.0 to 1.0 range."
2801 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2804 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
2805 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
2807 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
2808 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
2809 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
2813 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
2814 struct radv_pipeline
*pipeline
,
2815 const struct radv_blend_state
*blend
)
2817 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
2818 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
2820 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
2821 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
2823 if (pipeline
->device
->physical_device
->has_rbplus
) {
2825 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
2826 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
2829 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
2831 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
2832 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
2834 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
2835 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
2838 static const VkConservativeRasterizationModeEXT
2839 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
2841 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
2842 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
2844 if (!conservative_raster
)
2845 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
2846 return conservative_raster
->conservativeRasterizationMode
;
2850 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
2851 struct radv_pipeline
*pipeline
,
2852 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2854 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
2855 const VkConservativeRasterizationModeEXT mode
=
2856 radv_get_conservative_raster_mode(vkraster
);
2857 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
2858 bool depth_clip_disable
= vkraster
->depthClampEnable
;
2860 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
2861 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
2862 if (depth_clip_state
) {
2863 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
2866 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
2867 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2868 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
2869 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
2870 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
2871 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2873 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
2874 S_0286D4_FLAT_SHADE_ENA(1) |
2875 S_0286D4_PNT_SPRITE_ENA(1) |
2876 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
2877 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
2878 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
2879 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
2880 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2882 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
2883 S_028BE4_PIX_CENTER(1) | // TODO verify
2884 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
2885 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
2887 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
2888 S_028814_FACE(vkraster
->frontFace
) |
2889 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
2890 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
2891 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
2892 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
2893 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
2894 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
2895 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
2896 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
2898 /* Conservative rasterization. */
2899 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
2900 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
2902 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
2903 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
2904 S_028804_OVERRASTERIZATION_AMOUNT(4);
2906 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
2907 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
2908 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
2910 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
2911 pa_sc_conservative_rast
|=
2912 S_028C4C_OVER_RAST_ENABLE(1) |
2913 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
2914 S_028C4C_UNDER_RAST_ENABLE(0) |
2915 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
2916 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
2918 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
2919 pa_sc_conservative_rast
|=
2920 S_028C4C_OVER_RAST_ENABLE(0) |
2921 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
2922 S_028C4C_UNDER_RAST_ENABLE(1) |
2923 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
2924 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
2928 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
2929 pa_sc_conservative_rast
);
2934 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
2935 struct radv_pipeline
*pipeline
)
2937 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
2939 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
2940 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
2941 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
2943 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
2944 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
2946 /* The exclusion bits can be set to improve rasterization efficiency
2947 * if no sample lies on the pixel boundary (-8 sample offset). It's
2948 * currently always TRUE because the driver doesn't support 16 samples.
2950 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
2951 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
2952 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
2953 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
2957 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
2958 struct radv_pipeline
*pipeline
)
2960 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2962 uint32_t vgt_primitiveid_en
= false;
2963 uint32_t vgt_gs_mode
= 0;
2965 if (radv_pipeline_has_gs(pipeline
)) {
2966 const struct radv_shader_variant
*gs
=
2967 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2969 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
2970 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2971 } else if (outinfo
->export_prim_id
) {
2972 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
2973 vgt_primitiveid_en
= true;
2976 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
2977 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
2981 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
2982 struct radeon_cmdbuf
*cs
,
2983 struct radv_pipeline
*pipeline
,
2984 struct radv_shader_variant
*shader
)
2986 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
2988 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
2989 radeon_emit(cs
, va
>> 8);
2990 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
2991 radeon_emit(cs
, shader
->rsrc1
);
2992 radeon_emit(cs
, shader
->rsrc2
);
2994 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
2995 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
2996 clip_dist_mask
= outinfo
->clip_dist_mask
;
2997 cull_dist_mask
= outinfo
->cull_dist_mask
;
2998 total_mask
= clip_dist_mask
| cull_dist_mask
;
2999 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3000 outinfo
->writes_layer
||
3001 outinfo
->writes_viewport_index
;
3003 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3004 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo
->param_exports
) - 1));
3006 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3007 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3008 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3009 V_02870C_SPI_SHADER_4COMP
:
3010 V_02870C_SPI_SHADER_NONE
) |
3011 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3012 V_02870C_SPI_SHADER_4COMP
:
3013 V_02870C_SPI_SHADER_NONE
) |
3014 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3015 V_02870C_SPI_SHADER_4COMP
:
3016 V_02870C_SPI_SHADER_NONE
));
3018 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3019 S_028818_VTX_W0_FMT(1) |
3020 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3021 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3022 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3024 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3025 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3026 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3027 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3028 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3029 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3030 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3031 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3032 cull_dist_mask
<< 8 |
3035 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3036 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3037 outinfo
->writes_viewport_index
);
3041 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3042 struct radv_pipeline
*pipeline
,
3043 struct radv_shader_variant
*shader
)
3045 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3047 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3048 radeon_emit(cs
, va
>> 8);
3049 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3050 radeon_emit(cs
, shader
->rsrc1
);
3051 radeon_emit(cs
, shader
->rsrc2
);
3055 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3056 struct radv_pipeline
*pipeline
,
3057 struct radv_shader_variant
*shader
,
3058 const struct radv_tessellation_state
*tess
)
3060 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3061 uint32_t rsrc2
= shader
->rsrc2
;
3063 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3064 radeon_emit(cs
, va
>> 8);
3065 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3067 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3068 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3069 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3070 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3072 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3073 radeon_emit(cs
, shader
->rsrc1
);
3074 radeon_emit(cs
, rsrc2
);
3078 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3079 struct radv_pipeline
*pipeline
,
3080 struct radv_shader_variant
*shader
,
3081 const struct radv_tessellation_state
*tess
)
3083 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3085 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3086 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
3087 radeon_emit(cs
, va
>> 8);
3088 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
3090 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
3091 radeon_emit(cs
, shader
->rsrc1
);
3092 radeon_emit(cs
, shader
->rsrc2
|
3093 S_00B42C_LDS_SIZE(tess
->lds_size
));
3095 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
3096 radeon_emit(cs
, va
>> 8);
3097 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
3098 radeon_emit(cs
, shader
->rsrc1
);
3099 radeon_emit(cs
, shader
->rsrc2
);
3104 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
3105 struct radeon_cmdbuf
*cs
,
3106 struct radv_pipeline
*pipeline
,
3107 const struct radv_tessellation_state
*tess
)
3109 struct radv_shader_variant
*vs
;
3111 /* Skip shaders merged into HS/GS */
3112 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
3116 if (vs
->info
.vs
.as_ls
)
3117 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
3118 else if (vs
->info
.vs
.as_es
)
3119 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
3121 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
3125 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
3126 struct radeon_cmdbuf
*cs
,
3127 struct radv_pipeline
*pipeline
,
3128 const struct radv_tessellation_state
*tess
)
3130 if (!radv_pipeline_has_tess(pipeline
))
3133 struct radv_shader_variant
*tes
, *tcs
;
3135 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
3136 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
3139 if (tes
->info
.tes
.as_es
)
3140 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
3142 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
3145 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
3147 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
3150 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3151 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
3152 tess
->ls_hs_config
);
3154 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
3155 tess
->ls_hs_config
);
3159 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
3160 struct radeon_cmdbuf
*cs
,
3161 struct radv_pipeline
*pipeline
,
3162 const struct radv_gs_state
*gs_state
)
3164 struct radv_shader_variant
*gs
;
3165 unsigned gs_max_out_vertices
;
3166 uint8_t *num_components
;
3171 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3175 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
3176 max_stream
= gs
->info
.info
.gs
.max_stream
;
3177 num_components
= gs
->info
.info
.gs
.num_stream_output_components
;
3179 offset
= num_components
[0] * gs_max_out_vertices
;
3181 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
3182 radeon_emit(ctx_cs
, offset
);
3183 if (max_stream
>= 1)
3184 offset
+= num_components
[1] * gs_max_out_vertices
;
3185 radeon_emit(ctx_cs
, offset
);
3186 if (max_stream
>= 2)
3187 offset
+= num_components
[2] * gs_max_out_vertices
;
3188 radeon_emit(ctx_cs
, offset
);
3189 if (max_stream
>= 3)
3190 offset
+= num_components
[3] * gs_max_out_vertices
;
3191 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
3193 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
3195 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
3196 radeon_emit(ctx_cs
, num_components
[0]);
3197 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
3198 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
3199 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
3201 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
3202 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3203 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
3204 S_028B90_ENABLE(gs_num_invocations
> 0));
3206 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3207 gs_state
->vgt_esgs_ring_itemsize
);
3209 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
3211 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3212 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
3213 radeon_emit(cs
, va
>> 8);
3214 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
3216 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3217 radeon_emit(cs
, gs
->rsrc1
);
3218 radeon_emit(cs
, gs
->rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
3220 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
3221 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
3223 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
3224 radeon_emit(cs
, va
>> 8);
3225 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
3226 radeon_emit(cs
, gs
->rsrc1
);
3227 radeon_emit(cs
, gs
->rsrc2
);
3230 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
3233 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
3235 uint32_t ps_input_cntl
;
3236 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3237 ps_input_cntl
= S_028644_OFFSET(offset
);
3239 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3241 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
3242 S_028644_ATTR0_VALID(1);
3245 /* The input is a DEFAULT_VAL constant. */
3246 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3247 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3248 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3249 ps_input_cntl
= S_028644_OFFSET(0x20) |
3250 S_028644_DEFAULT_VAL(offset
);
3252 return ps_input_cntl
;
3256 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
3257 struct radv_pipeline
*pipeline
)
3259 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3260 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3261 uint32_t ps_input_cntl
[32];
3263 unsigned ps_offset
= 0;
3265 if (ps
->info
.info
.ps
.prim_id_input
) {
3266 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
3267 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3268 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
3273 if (ps
->info
.info
.ps
.layer_input
||
3274 ps
->info
.info
.ps
.uses_input_attachments
||
3275 ps
->info
.info
.needs_multiview_view_index
) {
3276 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
3277 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
3278 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
3280 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
3284 if (ps
->info
.info
.ps
.has_pcoord
) {
3286 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3287 ps_input_cntl
[ps_offset
] = val
;
3291 if (ps
->info
.info
.ps
.num_input_clips_culls
) {
3294 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
3295 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3296 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
3300 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
3301 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
3302 ps
->info
.info
.ps
.num_input_clips_culls
> 4) {
3303 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
3308 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
3312 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
3315 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
3316 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
3317 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
3322 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
3323 float16
= !!(ps
->info
.fs
.float16_shaded_mask
& (1u << ps_offset
));
3325 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
3330 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
3331 for (unsigned i
= 0; i
< ps_offset
; i
++) {
3332 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
3338 radv_compute_db_shader_control(const struct radv_device
*device
,
3339 const struct radv_pipeline
*pipeline
,
3340 const struct radv_shader_variant
*ps
)
3343 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.info
.ps
.writes_memory
)
3344 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
3346 z_order
= V_02880C_LATE_Z
;
3348 bool disable_rbplus
= device
->physical_device
->has_rbplus
&&
3349 !device
->physical_device
->rbplus_allowed
;
3351 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
3352 * but this appears to break Project Cars (DXVK). See
3353 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
3355 bool mask_export_enable
= ps
->info
.info
.ps
.writes_sample_mask
;
3357 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_z
) |
3358 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_stencil
) |
3359 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
3360 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
3361 S_02880C_Z_ORDER(z_order
) |
3362 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
3363 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.info
.ps
.writes_memory
) |
3364 S_02880C_EXEC_ON_NOOP(ps
->info
.info
.ps
.writes_memory
) |
3365 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
3369 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
3370 struct radeon_cmdbuf
*cs
,
3371 struct radv_pipeline
*pipeline
)
3373 struct radv_shader_variant
*ps
;
3375 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
3377 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3378 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
3380 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
3381 radeon_emit(cs
, va
>> 8);
3382 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
3383 radeon_emit(cs
, ps
->rsrc1
);
3384 radeon_emit(cs
, ps
->rsrc2
);
3386 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
3387 radv_compute_db_shader_control(pipeline
->device
,
3390 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
3391 ps
->config
.spi_ps_input_ena
);
3393 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
3394 ps
->config
.spi_ps_input_addr
);
3396 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
3397 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
3399 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
3401 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
3402 ac_get_spi_shader_z_format(ps
->info
.info
.ps
.writes_z
,
3403 ps
->info
.info
.ps
.writes_stencil
,
3404 ps
->info
.info
.ps
.writes_sample_mask
));
3406 if (pipeline
->device
->dfsm_allowed
) {
3407 /* optimise this? */
3408 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3409 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3414 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
3415 struct radv_pipeline
*pipeline
)
3417 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
3420 unsigned vtx_reuse_depth
= 30;
3421 if (radv_pipeline_has_tess(pipeline
) &&
3422 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
3423 vtx_reuse_depth
= 14;
3425 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
3426 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
3430 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
3432 uint32_t stages
= 0;
3433 if (radv_pipeline_has_tess(pipeline
)) {
3434 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3435 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3437 if (radv_pipeline_has_gs(pipeline
))
3438 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3440 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3442 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3444 } else if (radv_pipeline_has_gs(pipeline
))
3445 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3447 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3449 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
3450 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3456 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3458 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
3459 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
3461 if (!discard_rectangle_info
)
3466 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
3467 /* Interpret i as a bitmask, and then set the bit in the mask if
3468 * that combination of rectangles in which the pixel is contained
3469 * should pass the cliprect test. */
3470 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
3472 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
3476 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
3487 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
3488 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3489 const struct radv_graphics_pipeline_create_info
*extra
,
3490 const struct radv_blend_state
*blend
,
3491 const struct radv_tessellation_state
*tess
,
3492 const struct radv_gs_state
*gs
,
3493 unsigned prim
, unsigned gs_out
)
3495 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
3496 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
3499 ctx_cs
->max_dw
= 256;
3500 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
3501 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
3503 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
3504 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
3505 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
3506 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
3507 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
3508 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
3509 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
3510 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
, gs
);
3511 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
3512 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
3513 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
3514 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3516 radeon_set_context_reg(ctx_cs
, R_0286E8_SPI_TMPRING_SIZE
,
3517 S_0286E8_WAVES(pipeline
->max_waves
) |
3518 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3520 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
3522 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3523 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
3525 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
3527 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
3529 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
3531 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
3533 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
3534 assert(cs
->cdw
<= cs
->max_dw
);
3537 static struct radv_ia_multi_vgt_param_helpers
3538 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
3539 const struct radv_tessellation_state
*tess
,
3542 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
3543 const struct radv_device
*device
= pipeline
->device
;
3545 if (radv_pipeline_has_tess(pipeline
))
3546 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
3547 else if (radv_pipeline_has_gs(pipeline
))
3548 ia_multi_vgt_param
.primgroup_size
= 64;
3550 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
3552 /* GS requirement. */
3553 ia_multi_vgt_param
.partial_es_wave
= false;
3554 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3555 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
3556 ia_multi_vgt_param
.partial_es_wave
= true;
3558 ia_multi_vgt_param
.wd_switch_on_eop
= false;
3559 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3560 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3561 * 4 shader engines. Set 1 to pass the assertion below.
3562 * The other cases are hardware requirements. */
3563 if (device
->physical_device
->rad_info
.max_se
< 4 ||
3564 prim
== V_008958_DI_PT_POLYGON
||
3565 prim
== V_008958_DI_PT_LINELOOP
||
3566 prim
== V_008958_DI_PT_TRIFAN
||
3567 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
3568 (pipeline
->graphics
.prim_restart_enable
&&
3569 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
3570 (prim
!= V_008958_DI_PT_POINTLIST
&&
3571 prim
!= V_008958_DI_PT_LINESTRIP
))))
3572 ia_multi_vgt_param
.wd_switch_on_eop
= true;
3575 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
3576 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
)
3577 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3578 if (radv_pipeline_has_gs(pipeline
) &&
3579 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.info
.uses_prim_id
)
3580 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3581 if (radv_pipeline_has_tess(pipeline
)) {
3582 /* SWITCH_ON_EOI must be set if PrimID is used. */
3583 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.uses_prim_id
||
3584 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.info
.uses_prim_id
)
3585 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
3588 ia_multi_vgt_param
.partial_vs_wave
= false;
3589 if (radv_pipeline_has_tess(pipeline
)) {
3590 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3591 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
3592 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
3593 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
3594 radv_pipeline_has_gs(pipeline
))
3595 ia_multi_vgt_param
.partial_vs_wave
= true;
3596 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3597 if (device
->has_distributed_tess
) {
3598 if (radv_pipeline_has_gs(pipeline
)) {
3599 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3600 ia_multi_vgt_param
.partial_es_wave
= true;
3602 ia_multi_vgt_param
.partial_vs_wave
= true;
3607 /* Workaround for a VGT hang when strip primitive types are used with
3608 * primitive restart.
3610 if (pipeline
->graphics
.prim_restart_enable
&&
3611 (prim
== V_008958_DI_PT_LINESTRIP
||
3612 prim
== V_008958_DI_PT_TRISTRIP
||
3613 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
3614 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
3615 ia_multi_vgt_param
.partial_vs_wave
= true;
3618 if (radv_pipeline_has_gs(pipeline
)) {
3619 /* On these chips there is the possibility of a hang if the
3620 * pipeline uses a GS and partial_vs_wave is not set.
3622 * This mostly does not hit 4-SE chips, as those typically set
3623 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
3624 * with GS due to another workaround.
3626 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
3628 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
3629 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
3630 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
3631 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
3632 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
3633 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
3634 ia_multi_vgt_param
.partial_vs_wave
= true;
3638 ia_multi_vgt_param
.base
=
3639 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
3640 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3641 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
3642 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
3643 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
3645 return ia_multi_vgt_param
;
3650 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
3651 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3653 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
3654 pCreateInfo
->pVertexInputState
;
3655 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
3657 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
3658 const VkVertexInputAttributeDescription
*desc
=
3659 &vi_info
->pVertexAttributeDescriptions
[i
];
3660 unsigned loc
= desc
->location
;
3661 const struct vk_format_description
*format_desc
;
3663 format_desc
= vk_format_description(desc
->format
);
3665 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
3668 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
3669 const VkVertexInputBindingDescription
*desc
=
3670 &vi_info
->pVertexBindingDescriptions
[i
];
3672 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
3673 pipeline
->num_vertex_bindings
=
3674 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
3678 static struct radv_shader_variant
*
3679 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
3683 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
3684 struct radv_shader_variant
*shader
=
3685 radv_get_shader(pipeline
, i
);
3687 if (shader
&& shader
->info
.info
.so
.num_outputs
> 0)
3695 radv_pipeline_init(struct radv_pipeline
*pipeline
,
3696 struct radv_device
*device
,
3697 struct radv_pipeline_cache
*cache
,
3698 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3699 const struct radv_graphics_pipeline_create_info
*extra
)
3702 bool has_view_index
= false;
3704 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3705 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3706 if (subpass
->view_mask
)
3707 has_view_index
= true;
3709 pipeline
->device
= device
;
3710 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3711 assert(pipeline
->layout
);
3713 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
3715 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
3716 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
3717 radv_init_feedback(creation_feedback
);
3719 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
3721 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3722 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
3723 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
3724 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
3725 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
3726 if(creation_feedback
)
3727 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
3730 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
3731 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
3733 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
3734 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
3736 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
3738 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
3740 if (radv_pipeline_has_gs(pipeline
)) {
3741 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
3742 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3744 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
3746 if (extra
&& extra
->use_rectlist
) {
3747 prim
= V_008958_DI_PT_RECTLIST
;
3748 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
3749 pipeline
->graphics
.can_use_guardband
= true;
3751 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
3752 /* prim vertex count will need TESS changes */
3753 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
3755 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
3757 /* Ensure that some export memory is always allocated, for two reasons:
3759 * 1) Correctness: The hardware ignores the EXEC mask if no export
3760 * memory is allocated, so KILL and alpha test do not work correctly
3762 * 2) Performance: Every shader needs at least a NULL export, even when
3763 * it writes no color/depth output. The NULL export instruction
3764 * stalls without this setting.
3766 * Don't add this to CB_SHADER_MASK.
3768 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3769 if (!blend
.spi_shader_col_format
) {
3770 if (!ps
->info
.info
.ps
.writes_z
&&
3771 !ps
->info
.info
.ps
.writes_stencil
&&
3772 !ps
->info
.info
.ps
.writes_sample_mask
)
3773 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
3776 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
3777 if (pipeline
->shaders
[i
]) {
3778 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
3782 struct radv_gs_state gs
= {0};
3783 if (radv_pipeline_has_gs(pipeline
)) {
3784 gs
= calculate_gs_info(pCreateInfo
, pipeline
);
3785 calculate_gs_ring_sizes(pipeline
, &gs
);
3788 struct radv_tessellation_state tess
= {0};
3789 if (radv_pipeline_has_tess(pipeline
)) {
3790 if (prim
== V_008958_DI_PT_PATCH
) {
3791 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
3792 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
3794 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
3797 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
3799 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
3801 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
3802 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
3804 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
3805 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
3806 if (loc
->sgpr_idx
!= -1) {
3807 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
3808 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
3809 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
)
3810 pipeline
->graphics
.vtx_emit_num
= 3;
3812 pipeline
->graphics
.vtx_emit_num
= 2;
3815 /* Find the last vertex shader stage that eventually uses streamout. */
3816 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
3818 result
= radv_pipeline_scratch_init(device
, pipeline
);
3819 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, &gs
, prim
, gs_out
);
3825 radv_graphics_pipeline_create(
3827 VkPipelineCache _cache
,
3828 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3829 const struct radv_graphics_pipeline_create_info
*extra
,
3830 const VkAllocationCallbacks
*pAllocator
,
3831 VkPipeline
*pPipeline
)
3833 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3834 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3835 struct radv_pipeline
*pipeline
;
3838 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3839 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3840 if (pipeline
== NULL
)
3841 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3843 result
= radv_pipeline_init(pipeline
, device
, cache
,
3844 pCreateInfo
, extra
);
3845 if (result
!= VK_SUCCESS
) {
3846 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3850 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3855 VkResult
radv_CreateGraphicsPipelines(
3857 VkPipelineCache pipelineCache
,
3859 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
3860 const VkAllocationCallbacks
* pAllocator
,
3861 VkPipeline
* pPipelines
)
3863 VkResult result
= VK_SUCCESS
;
3866 for (; i
< count
; i
++) {
3868 r
= radv_graphics_pipeline_create(_device
,
3871 NULL
, pAllocator
, &pPipelines
[i
]);
3872 if (r
!= VK_SUCCESS
) {
3874 pPipelines
[i
] = VK_NULL_HANDLE
;
3883 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
3885 struct radv_shader_variant
*compute_shader
;
3886 struct radv_device
*device
= pipeline
->device
;
3887 unsigned compute_resource_limits
;
3888 unsigned waves_per_threadgroup
;
3891 pipeline
->cs
.buf
= malloc(20 * 4);
3892 pipeline
->cs
.max_dw
= 20;
3894 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3895 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
3897 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
3898 radeon_emit(&pipeline
->cs
, va
>> 8);
3899 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
3901 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
3902 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc1
);
3903 radeon_emit(&pipeline
->cs
, compute_shader
->rsrc2
);
3905 radeon_set_sh_reg(&pipeline
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3906 S_00B860_WAVES(pipeline
->max_waves
) |
3907 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
3909 /* Calculate best compute resource limits. */
3910 waves_per_threadgroup
=
3911 DIV_ROUND_UP(compute_shader
->info
.cs
.block_size
[0] *
3912 compute_shader
->info
.cs
.block_size
[1] *
3913 compute_shader
->info
.cs
.block_size
[2], 64);
3914 compute_resource_limits
=
3915 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
3917 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3918 unsigned num_cu_per_se
=
3919 device
->physical_device
->rad_info
.num_good_compute_units
/
3920 device
->physical_device
->rad_info
.max_se
;
3922 /* Force even distribution on all SIMDs in CU if the workgroup
3923 * size is 64. This has shown some good improvements if # of
3924 * CUs per SE is not a multiple of 4.
3926 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
3927 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
3930 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
3931 compute_resource_limits
);
3933 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3934 radeon_emit(&pipeline
->cs
,
3935 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
3936 radeon_emit(&pipeline
->cs
,
3937 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
3938 radeon_emit(&pipeline
->cs
,
3939 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
3941 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
3944 static VkResult
radv_compute_pipeline_create(
3946 VkPipelineCache _cache
,
3947 const VkComputePipelineCreateInfo
* pCreateInfo
,
3948 const VkAllocationCallbacks
* pAllocator
,
3949 VkPipeline
* pPipeline
)
3951 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3952 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
3953 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
3954 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
3955 struct radv_pipeline
*pipeline
;
3958 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
3959 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3960 if (pipeline
== NULL
)
3961 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3963 pipeline
->device
= device
;
3964 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
3965 assert(pipeline
->layout
);
3967 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
3968 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
3969 radv_init_feedback(creation_feedback
);
3971 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
3972 if (creation_feedback
)
3973 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
3975 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
3976 radv_create_shaders(pipeline
, device
, cache
, &(struct radv_pipeline_key
) {0}, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
3978 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
3979 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
3980 result
= radv_pipeline_scratch_init(device
, pipeline
);
3981 if (result
!= VK_SUCCESS
) {
3982 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
3986 radv_compute_generate_pm4(pipeline
);
3988 *pPipeline
= radv_pipeline_to_handle(pipeline
);
3993 VkResult
radv_CreateComputePipelines(
3995 VkPipelineCache pipelineCache
,
3997 const VkComputePipelineCreateInfo
* pCreateInfos
,
3998 const VkAllocationCallbacks
* pAllocator
,
3999 VkPipeline
* pPipelines
)
4001 VkResult result
= VK_SUCCESS
;
4004 for (; i
< count
; i
++) {
4006 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
4008 pAllocator
, &pPipelines
[i
]);
4009 if (r
!= VK_SUCCESS
) {
4011 pPipelines
[i
] = VK_NULL_HANDLE
;