projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Merge depth stencil state with PM4 generation.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 static void
53 radv_pipeline_destroy(struct radv_device *device,
54 struct radv_pipeline *pipeline,
55 const VkAllocationCallbacks* allocator)
56 {
57 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
58 if (pipeline->shaders[i])
59 radv_shader_variant_destroy(device, pipeline->shaders[i]);
60
61 if (pipeline->gs_copy_shader)
62 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
63
64 if(pipeline->cs.buf)
65 free(pipeline->cs.buf);
66 vk_free2(&device->alloc, allocator, pipeline);
67 }
68
69 void radv_DestroyPipeline(
70 VkDevice _device,
71 VkPipeline _pipeline,
72 const VkAllocationCallbacks* pAllocator)
73 {
74 RADV_FROM_HANDLE(radv_device, device, _device);
75 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
76
77 if (!_pipeline)
78 return;
79
80 radv_pipeline_destroy(device, pipeline, pAllocator);
81 }
82
83 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
84 {
85 int i;
86
87 for (i = 0; i < MESA_SHADER_STAGES; i++) {
88 if (!pipeline->shaders[i])
89 continue;
90
91 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
92 }
93 }
94
95 static uint32_t get_hash_flags(struct radv_device *device)
96 {
97 uint32_t hash_flags = 0;
98
99 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
100 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
101 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
102 hash_flags |= RADV_HASH_SHADER_SISCHED;
103 return hash_flags;
104 }
105
106 static VkResult
107 radv_pipeline_scratch_init(struct radv_device *device,
108 struct radv_pipeline *pipeline)
109 {
110 unsigned scratch_bytes_per_wave = 0;
111 unsigned max_waves = 0;
112 unsigned min_waves = 1;
113
114 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
115 if (pipeline->shaders[i]) {
116 unsigned max_stage_waves = device->scratch_waves;
117
118 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
119 pipeline->shaders[i]->config.scratch_bytes_per_wave);
120
121 max_stage_waves = MIN2(max_stage_waves,
122 4 * device->physical_device->rad_info.num_good_compute_units *
123 (256 / pipeline->shaders[i]->config.num_vgprs));
124 max_waves = MAX2(max_waves, max_stage_waves);
125 }
126 }
127
128 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
129 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
130 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
131 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
132 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
133 }
134
135 if (scratch_bytes_per_wave)
136 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
137
138 if (scratch_bytes_per_wave && max_waves < min_waves) {
139 /* Not really true at this moment, but will be true on first
140 * execution. Avoid having hanging shaders. */
141 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
142 }
143 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
144 pipeline->max_waves = max_waves;
145 return VK_SUCCESS;
146 }
147
148 static uint32_t si_translate_blend_function(VkBlendOp op)
149 {
150 switch (op) {
151 case VK_BLEND_OP_ADD:
152 return V_028780_COMB_DST_PLUS_SRC;
153 case VK_BLEND_OP_SUBTRACT:
154 return V_028780_COMB_SRC_MINUS_DST;
155 case VK_BLEND_OP_REVERSE_SUBTRACT:
156 return V_028780_COMB_DST_MINUS_SRC;
157 case VK_BLEND_OP_MIN:
158 return V_028780_COMB_MIN_DST_SRC;
159 case VK_BLEND_OP_MAX:
160 return V_028780_COMB_MAX_DST_SRC;
161 default:
162 return 0;
163 }
164 }
165
166 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
167 {
168 switch (factor) {
169 case VK_BLEND_FACTOR_ZERO:
170 return V_028780_BLEND_ZERO;
171 case VK_BLEND_FACTOR_ONE:
172 return V_028780_BLEND_ONE;
173 case VK_BLEND_FACTOR_SRC_COLOR:
174 return V_028780_BLEND_SRC_COLOR;
175 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
176 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
177 case VK_BLEND_FACTOR_DST_COLOR:
178 return V_028780_BLEND_DST_COLOR;
179 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
180 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
181 case VK_BLEND_FACTOR_SRC_ALPHA:
182 return V_028780_BLEND_SRC_ALPHA;
183 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
184 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
185 case VK_BLEND_FACTOR_DST_ALPHA:
186 return V_028780_BLEND_DST_ALPHA;
187 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
188 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
189 case VK_BLEND_FACTOR_CONSTANT_COLOR:
190 return V_028780_BLEND_CONSTANT_COLOR;
191 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
192 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
193 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
194 return V_028780_BLEND_CONSTANT_ALPHA;
195 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
196 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
197 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
198 return V_028780_BLEND_SRC_ALPHA_SATURATE;
199 case VK_BLEND_FACTOR_SRC1_COLOR:
200 return V_028780_BLEND_SRC1_COLOR;
201 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
202 return V_028780_BLEND_INV_SRC1_COLOR;
203 case VK_BLEND_FACTOR_SRC1_ALPHA:
204 return V_028780_BLEND_SRC1_ALPHA;
205 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
206 return V_028780_BLEND_INV_SRC1_ALPHA;
207 default:
208 return 0;
209 }
210 }
211
212 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
213 {
214 switch (op) {
215 case VK_BLEND_OP_ADD:
216 return V_028760_OPT_COMB_ADD;
217 case VK_BLEND_OP_SUBTRACT:
218 return V_028760_OPT_COMB_SUBTRACT;
219 case VK_BLEND_OP_REVERSE_SUBTRACT:
220 return V_028760_OPT_COMB_REVSUBTRACT;
221 case VK_BLEND_OP_MIN:
222 return V_028760_OPT_COMB_MIN;
223 case VK_BLEND_OP_MAX:
224 return V_028760_OPT_COMB_MAX;
225 default:
226 return V_028760_OPT_COMB_BLEND_DISABLED;
227 }
228 }
229
230 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
231 {
232 switch (factor) {
233 case VK_BLEND_FACTOR_ZERO:
234 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
235 case VK_BLEND_FACTOR_ONE:
236 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
237 case VK_BLEND_FACTOR_SRC_COLOR:
238 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
239 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
240 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
241 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
242 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
243 case VK_BLEND_FACTOR_SRC_ALPHA:
244 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
245 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
246 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
247 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
248 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
249 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
250 default:
251 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
252 }
253 }
254
255 /**
256 * Get rid of DST in the blend factors by commuting the operands:
257 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
258 */
259 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
260 unsigned *dst_factor, unsigned expected_dst,
261 unsigned replacement_src)
262 {
263 if (*src_factor == expected_dst &&
264 *dst_factor == VK_BLEND_FACTOR_ZERO) {
265 *src_factor = VK_BLEND_FACTOR_ZERO;
266 *dst_factor = replacement_src;
267
268 /* Commuting the operands requires reversing subtractions. */
269 if (*func == VK_BLEND_OP_SUBTRACT)
270 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
271 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
272 *func = VK_BLEND_OP_SUBTRACT;
273 }
274 }
275
276 static bool si_blend_factor_uses_dst(unsigned factor)
277 {
278 return factor == VK_BLEND_FACTOR_DST_COLOR ||
279 factor == VK_BLEND_FACTOR_DST_ALPHA ||
280 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
281 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
282 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
283 }
284
285 static bool is_dual_src(VkBlendFactor factor)
286 {
287 switch (factor) {
288 case VK_BLEND_FACTOR_SRC1_COLOR:
289 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
290 case VK_BLEND_FACTOR_SRC1_ALPHA:
291 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
292 return true;
293 default:
294 return false;
295 }
296 }
297
298 static unsigned si_choose_spi_color_format(VkFormat vk_format,
299 bool blend_enable,
300 bool blend_need_alpha)
301 {
302 const struct vk_format_description *desc = vk_format_description(vk_format);
303 unsigned format, ntype, swap;
304
305 /* Alpha is needed for alpha-to-coverage.
306 * Blending may be with or without alpha.
307 */
308 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
309 unsigned alpha = 0; /* exports alpha, but may not support blending */
310 unsigned blend = 0; /* supports blending, but may not export alpha */
311 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
312
313 format = radv_translate_colorformat(vk_format);
314 ntype = radv_translate_color_numformat(vk_format, desc,
315 vk_format_get_first_non_void_channel(vk_format));
316 swap = radv_translate_colorswap(vk_format, false);
317
318 /* Choose the SPI color formats. These are required values for Stoney/RB+.
319 * Other chips have multiple choices, though they are not necessarily better.
320 */
321 switch (format) {
322 case V_028C70_COLOR_5_6_5:
323 case V_028C70_COLOR_1_5_5_5:
324 case V_028C70_COLOR_5_5_5_1:
325 case V_028C70_COLOR_4_4_4_4:
326 case V_028C70_COLOR_10_11_11:
327 case V_028C70_COLOR_11_11_10:
328 case V_028C70_COLOR_8:
329 case V_028C70_COLOR_8_8:
330 case V_028C70_COLOR_8_8_8_8:
331 case V_028C70_COLOR_10_10_10_2:
332 case V_028C70_COLOR_2_10_10_10:
333 if (ntype == V_028C70_NUMBER_UINT)
334 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
335 else if (ntype == V_028C70_NUMBER_SINT)
336 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
337 else
338 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
339 break;
340
341 case V_028C70_COLOR_16:
342 case V_028C70_COLOR_16_16:
343 case V_028C70_COLOR_16_16_16_16:
344 if (ntype == V_028C70_NUMBER_UNORM ||
345 ntype == V_028C70_NUMBER_SNORM) {
346 /* UNORM16 and SNORM16 don't support blending */
347 if (ntype == V_028C70_NUMBER_UNORM)
348 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
349 else
350 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
351
352 /* Use 32 bits per channel for blending. */
353 if (format == V_028C70_COLOR_16) {
354 if (swap == V_028C70_SWAP_STD) { /* R */
355 blend = V_028714_SPI_SHADER_32_R;
356 blend_alpha = V_028714_SPI_SHADER_32_AR;
357 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
358 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
359 else
360 assert(0);
361 } else if (format == V_028C70_COLOR_16_16) {
362 if (swap == V_028C70_SWAP_STD) { /* RG */
363 blend = V_028714_SPI_SHADER_32_GR;
364 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
365 } else if (swap == V_028C70_SWAP_ALT) /* RA */
366 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
367 else
368 assert(0);
369 } else /* 16_16_16_16 */
370 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
371 } else if (ntype == V_028C70_NUMBER_UINT)
372 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
373 else if (ntype == V_028C70_NUMBER_SINT)
374 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
375 else if (ntype == V_028C70_NUMBER_FLOAT)
376 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
377 else
378 assert(0);
379 break;
380
381 case V_028C70_COLOR_32:
382 if (swap == V_028C70_SWAP_STD) { /* R */
383 blend = normal = V_028714_SPI_SHADER_32_R;
384 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
385 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
386 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
387 else
388 assert(0);
389 break;
390
391 case V_028C70_COLOR_32_32:
392 if (swap == V_028C70_SWAP_STD) { /* RG */
393 blend = normal = V_028714_SPI_SHADER_32_GR;
394 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
395 } else if (swap == V_028C70_SWAP_ALT) /* RA */
396 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
397 else
398 assert(0);
399 break;
400
401 case V_028C70_COLOR_32_32_32_32:
402 case V_028C70_COLOR_8_24:
403 case V_028C70_COLOR_24_8:
404 case V_028C70_COLOR_X24_8_32_FLOAT:
405 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
406 break;
407
408 default:
409 unreachable("unhandled blend format");
410 }
411
412 if (blend_enable && blend_need_alpha)
413 return blend_alpha;
414 else if(blend_need_alpha)
415 return alpha;
416 else if(blend_enable)
417 return blend;
418 else
419 return normal;
420 }
421
422 static void
423 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
424 const VkGraphicsPipelineCreateInfo *pCreateInfo,
425 uint32_t blend_enable,
426 uint32_t blend_need_alpha,
427 bool single_cb_enable,
428 bool blend_mrt0_is_dual_src)
429 {
430 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
431 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
432 struct radv_blend_state *blend = &pipeline->graphics.blend;
433 unsigned col_format = 0;
434
435 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
436 unsigned cf;
437
438 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
439 cf = V_028714_SPI_SHADER_ZERO;
440 } else {
441 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
442
443 cf = si_choose_spi_color_format(attachment->format,
444 blend_enable & (1 << i),
445 blend_need_alpha & (1 << i));
446 }
447
448 col_format |= cf << (4 * i);
449 }
450
451 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
452
453 if (blend_mrt0_is_dual_src)
454 col_format |= (col_format & 0xf) << 4;
455 blend->spi_shader_col_format = col_format;
456 }
457
458 static bool
459 format_is_int8(VkFormat format)
460 {
461 const struct vk_format_description *desc = vk_format_description(format);
462 int channel = vk_format_get_first_non_void_channel(format);
463
464 return channel >= 0 && desc->channel[channel].pure_integer &&
465 desc->channel[channel].size == 8;
466 }
467
468 static bool
469 format_is_int10(VkFormat format)
470 {
471 const struct vk_format_description *desc = vk_format_description(format);
472
473 if (desc->nr_channels != 4)
474 return false;
475 for (unsigned i = 0; i < 4; i++) {
476 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
477 return true;
478 }
479 return false;
480 }
481
482 unsigned radv_format_meta_fs_key(VkFormat format)
483 {
484 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
485 bool is_int8 = format_is_int8(format);
486 bool is_int10 = format_is_int10(format);
487
488 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
489 }
490
491 static void
492 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
493 unsigned *is_int8, unsigned *is_int10)
494 {
495 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
496 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
497 *is_int8 = 0;
498 *is_int10 = 0;
499
500 for (unsigned i = 0; i < subpass->color_count; ++i) {
501 struct radv_render_pass_attachment *attachment;
502
503 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
504 continue;
505
506 attachment = pass->attachments + subpass->color_attachments[i].attachment;
507
508 if (format_is_int8(attachment->format))
509 *is_int8 |= 1 << i;
510 if (format_is_int10(attachment->format))
511 *is_int10 |= 1 << i;
512 }
513 }
514
515 static void
516 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
517 const VkGraphicsPipelineCreateInfo *pCreateInfo,
518 const struct radv_graphics_pipeline_create_info *extra)
519 {
520 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
521 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
522 struct radv_blend_state *blend = &pipeline->graphics.blend;
523 unsigned mode = V_028808_CB_NORMAL;
524 uint32_t blend_enable = 0, blend_need_alpha = 0;
525 bool blend_mrt0_is_dual_src = false;
526 int i;
527 bool single_cb_enable = false;
528
529 if (!vkblend)
530 return;
531
532 if (extra && extra->custom_blend_mode) {
533 single_cb_enable = true;
534 mode = extra->custom_blend_mode;
535 }
536 blend->cb_color_control = 0;
537 if (vkblend->logicOpEnable)
538 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
539 else
540 blend->cb_color_control |= S_028808_ROP3(0xcc);
541
542 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
543 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
544 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
545 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
546
547 if (vkms && vkms->alphaToCoverageEnable) {
548 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
549 }
550
551 blend->cb_target_mask = 0;
552 for (i = 0; i < vkblend->attachmentCount; i++) {
553 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
554 unsigned blend_cntl = 0;
555 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
556 VkBlendOp eqRGB = att->colorBlendOp;
557 VkBlendFactor srcRGB = att->srcColorBlendFactor;
558 VkBlendFactor dstRGB = att->dstColorBlendFactor;
559 VkBlendOp eqA = att->alphaBlendOp;
560 VkBlendFactor srcA = att->srcAlphaBlendFactor;
561 VkBlendFactor dstA = att->dstAlphaBlendFactor;
562
563 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
564
565 if (!att->colorWriteMask)
566 continue;
567
568 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
569 if (!att->blendEnable) {
570 blend->cb_blend_control[i] = blend_cntl;
571 continue;
572 }
573
574 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
575 if (i == 0)
576 blend_mrt0_is_dual_src = true;
577
578 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
579 srcRGB = VK_BLEND_FACTOR_ONE;
580 dstRGB = VK_BLEND_FACTOR_ONE;
581 }
582 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
583 srcA = VK_BLEND_FACTOR_ONE;
584 dstA = VK_BLEND_FACTOR_ONE;
585 }
586
587 /* Blending optimizations for RB+.
588 * These transformations don't change the behavior.
589 *
590 * First, get rid of DST in the blend factors:
591 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
592 */
593 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
594 VK_BLEND_FACTOR_DST_COLOR,
595 VK_BLEND_FACTOR_SRC_COLOR);
596
597 si_blend_remove_dst(&eqA, &srcA, &dstA,
598 VK_BLEND_FACTOR_DST_COLOR,
599 VK_BLEND_FACTOR_SRC_COLOR);
600
601 si_blend_remove_dst(&eqA, &srcA, &dstA,
602 VK_BLEND_FACTOR_DST_ALPHA,
603 VK_BLEND_FACTOR_SRC_ALPHA);
604
605 /* Look up the ideal settings from tables. */
606 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
607 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
608 srcA_opt = si_translate_blend_opt_factor(srcA, true);
609 dstA_opt = si_translate_blend_opt_factor(dstA, true);
610
611 /* Handle interdependencies. */
612 if (si_blend_factor_uses_dst(srcRGB))
613 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
614 if (si_blend_factor_uses_dst(srcA))
615 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
616
617 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
618 (dstRGB == VK_BLEND_FACTOR_ZERO ||
619 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
620 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
621 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
622
623 /* Set the final value. */
624 blend->sx_mrt_blend_opt[i] =
625 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
626 S_028760_COLOR_DST_OPT(dstRGB_opt) |
627 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
628 S_028760_ALPHA_SRC_OPT(srcA_opt) |
629 S_028760_ALPHA_DST_OPT(dstA_opt) |
630 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
631 blend_cntl |= S_028780_ENABLE(1);
632
633 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
634 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
635 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
636 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
637 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
638 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
639 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
640 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
641 }
642 blend->cb_blend_control[i] = blend_cntl;
643
644 blend_enable |= 1 << i;
645
646 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
647 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
648 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
649 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
650 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
651 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
652 blend_need_alpha |= 1 << i;
653 }
654 for (i = vkblend->attachmentCount; i < 8; i++) {
655 blend->cb_blend_control[i] = 0;
656 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
657 }
658
659 /* disable RB+ for now */
660 if (pipeline->device->physical_device->has_rbplus)
661 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
662
663 if (blend->cb_target_mask)
664 blend->cb_color_control |= S_028808_MODE(mode);
665 else
666 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
667
668 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
669 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
670 }
671
672 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
673 {
674 switch (op) {
675 case VK_STENCIL_OP_KEEP:
676 return V_02842C_STENCIL_KEEP;
677 case VK_STENCIL_OP_ZERO:
678 return V_02842C_STENCIL_ZERO;
679 case VK_STENCIL_OP_REPLACE:
680 return V_02842C_STENCIL_REPLACE_TEST;
681 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
682 return V_02842C_STENCIL_ADD_CLAMP;
683 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
684 return V_02842C_STENCIL_SUB_CLAMP;
685 case VK_STENCIL_OP_INVERT:
686 return V_02842C_STENCIL_INVERT;
687 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
688 return V_02842C_STENCIL_ADD_WRAP;
689 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
690 return V_02842C_STENCIL_SUB_WRAP;
691 default:
692 return 0;
693 }
694 }
695
696 static uint32_t si_translate_fill(VkPolygonMode func)
697 {
698 switch(func) {
699 case VK_POLYGON_MODE_FILL:
700 return V_028814_X_DRAW_TRIANGLES;
701 case VK_POLYGON_MODE_LINE:
702 return V_028814_X_DRAW_LINES;
703 case VK_POLYGON_MODE_POINT:
704 return V_028814_X_DRAW_POINTS;
705 default:
706 assert(0);
707 return V_028814_X_DRAW_POINTS;
708 }
709 }
710 static void
711 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
712 const VkGraphicsPipelineCreateInfo *pCreateInfo)
713 {
714 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
715 struct radv_raster_state *raster = &pipeline->graphics.raster;
716
717 raster->spi_interp_control =
718 S_0286D4_FLAT_SHADE_ENA(1) |
719 S_0286D4_PNT_SPRITE_ENA(1) |
720 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
721 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
722 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
723 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
724 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
725
726
727 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
728 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
729 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
730 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
731 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
732 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
733
734 raster->pa_su_vtx_cntl =
735 S_028BE4_PIX_CENTER(1) | // TODO verify
736 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
737 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
738
739 raster->pa_su_sc_mode_cntl =
740 S_028814_FACE(vkraster->frontFace) |
741 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
742 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
743 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
744 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
745 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
746 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
747 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
748 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
749
750 }
751
752 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
753 {
754 uint32_t num_samples = vkms->rasterizationSamples;
755 uint32_t ps_iter_samples = 1;
756
757 if (vkms->sampleShadingEnable) {
758 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
759 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
760 }
761 return ps_iter_samples;
762 }
763
764 static void
765 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
766 const VkGraphicsPipelineCreateInfo *pCreateInfo)
767 {
768 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
769 struct radv_multisample_state *ms = &pipeline->graphics.ms;
770 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
771 int ps_iter_samples = 1;
772 uint32_t mask = 0xffff;
773
774 if (vkms)
775 ms->num_samples = vkms->rasterizationSamples;
776 else
777 ms->num_samples = 1;
778
779 if (vkms)
780 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
781 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
782 ps_iter_samples = ms->num_samples;
783 }
784
785 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
786 ms->pa_sc_aa_config = 0;
787 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
788 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
789 ms->pa_sc_mode_cntl_1 =
790 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
791 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
792 /* always 1: */
793 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
794 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
795 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
796 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
797 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
798 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
799 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
800 S_028A48_VPORT_SCISSOR_ENABLE(1);
801
802 if (ms->num_samples > 1) {
803 unsigned log_samples = util_logbase2(ms->num_samples);
804 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
805 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
806 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
807 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
808 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
809 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
810 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
811 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
812 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
813 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
814 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
815 if (ps_iter_samples > 1)
816 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
817 }
818
819 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
820 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
821 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
822 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
823 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
824 }
825
826 if (vkms && vkms->pSampleMask) {
827 mask = vkms->pSampleMask[0] & 0xffff;
828 }
829
830 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
831 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
832 }
833
834 static bool
835 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
836 {
837 switch (topology) {
838 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
839 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
840 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
841 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
842 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
843 return false;
844 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
845 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
846 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
847 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
848 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
849 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
850 return true;
851 default:
852 unreachable("unhandled primitive type");
853 }
854 }
855
856 static uint32_t
857 si_translate_prim(enum VkPrimitiveTopology topology)
858 {
859 switch (topology) {
860 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
861 return V_008958_DI_PT_POINTLIST;
862 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
863 return V_008958_DI_PT_LINELIST;
864 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
865 return V_008958_DI_PT_LINESTRIP;
866 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
867 return V_008958_DI_PT_TRILIST;
868 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
869 return V_008958_DI_PT_TRISTRIP;
870 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
871 return V_008958_DI_PT_TRIFAN;
872 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
873 return V_008958_DI_PT_LINELIST_ADJ;
874 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
875 return V_008958_DI_PT_LINESTRIP_ADJ;
876 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
877 return V_008958_DI_PT_TRILIST_ADJ;
878 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
879 return V_008958_DI_PT_TRISTRIP_ADJ;
880 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
881 return V_008958_DI_PT_PATCH;
882 default:
883 assert(0);
884 return 0;
885 }
886 }
887
888 static uint32_t
889 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
890 {
891 switch (gl_prim) {
892 case 0: /* GL_POINTS */
893 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
894 case 1: /* GL_LINES */
895 case 3: /* GL_LINE_STRIP */
896 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
897 case 0x8E7A: /* GL_ISOLINES */
898 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
899
900 case 4: /* GL_TRIANGLES */
901 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
902 case 5: /* GL_TRIANGLE_STRIP */
903 case 7: /* GL_QUADS */
904 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
905 default:
906 assert(0);
907 return 0;
908 }
909 }
910
911 static uint32_t
912 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
913 {
914 switch (topology) {
915 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
916 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
917 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
918 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
919 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
920 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
921 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
922 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
923 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
924 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
925 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
926 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
927 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
928 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
929 default:
930 assert(0);
931 return 0;
932 }
933 }
934
935 static unsigned si_map_swizzle(unsigned swizzle)
936 {
937 switch (swizzle) {
938 case VK_SWIZZLE_Y:
939 return V_008F0C_SQ_SEL_Y;
940 case VK_SWIZZLE_Z:
941 return V_008F0C_SQ_SEL_Z;
942 case VK_SWIZZLE_W:
943 return V_008F0C_SQ_SEL_W;
944 case VK_SWIZZLE_0:
945 return V_008F0C_SQ_SEL_0;
946 case VK_SWIZZLE_1:
947 return V_008F0C_SQ_SEL_1;
948 default: /* VK_SWIZZLE_X */
949 return V_008F0C_SQ_SEL_X;
950 }
951 }
952
953
954 static unsigned radv_dynamic_state_mask(VkDynamicState state)
955 {
956 switch(state) {
957 case VK_DYNAMIC_STATE_VIEWPORT:
958 return RADV_DYNAMIC_VIEWPORT;
959 case VK_DYNAMIC_STATE_SCISSOR:
960 return RADV_DYNAMIC_SCISSOR;
961 case VK_DYNAMIC_STATE_LINE_WIDTH:
962 return RADV_DYNAMIC_LINE_WIDTH;
963 case VK_DYNAMIC_STATE_DEPTH_BIAS:
964 return RADV_DYNAMIC_DEPTH_BIAS;
965 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
966 return RADV_DYNAMIC_BLEND_CONSTANTS;
967 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
968 return RADV_DYNAMIC_DEPTH_BOUNDS;
969 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
970 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
971 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
972 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
973 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
974 return RADV_DYNAMIC_STENCIL_REFERENCE;
975 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
976 return RADV_DYNAMIC_DISCARD_RECTANGLE;
977 default:
978 unreachable("Unhandled dynamic state");
979 }
980 }
981
982 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
983 {
984 uint32_t states = RADV_DYNAMIC_ALL;
985
986 /* If rasterization is disabled we do not care about any of the dynamic states,
987 * since they are all rasterization related only. */
988 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
989 return 0;
990
991 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
992 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
993
994 if (!pCreateInfo->pDepthStencilState ||
995 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
996 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
997
998 if (!pCreateInfo->pDepthStencilState ||
999 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1000 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1001 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1002 RADV_DYNAMIC_STENCIL_REFERENCE);
1003
1004 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1005 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1006
1007 /* TODO: blend constants & line width. */
1008
1009 return states;
1010 }
1011
1012
1013 static void
1014 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1015 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1016 {
1017 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1018 uint32_t states = needed_states;
1019 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1020 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1021
1022 pipeline->dynamic_state = default_dynamic_state;
1023 pipeline->graphics.needed_dynamic_state = needed_states;
1024
1025 if (pCreateInfo->pDynamicState) {
1026 /* Remove all of the states that are marked as dynamic */
1027 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1028 for (uint32_t s = 0; s < count; s++)
1029 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1030 }
1031
1032 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1033
1034 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1035 assert(pCreateInfo->pViewportState);
1036
1037 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1038 if (states & RADV_DYNAMIC_VIEWPORT) {
1039 typed_memcpy(dynamic->viewport.viewports,
1040 pCreateInfo->pViewportState->pViewports,
1041 pCreateInfo->pViewportState->viewportCount);
1042 }
1043 }
1044
1045 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1046 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1047 if (states & RADV_DYNAMIC_SCISSOR) {
1048 typed_memcpy(dynamic->scissor.scissors,
1049 pCreateInfo->pViewportState->pScissors,
1050 pCreateInfo->pViewportState->scissorCount);
1051 }
1052 }
1053
1054 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1055 assert(pCreateInfo->pRasterizationState);
1056 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1057 }
1058
1059 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1060 assert(pCreateInfo->pRasterizationState);
1061 dynamic->depth_bias.bias =
1062 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1063 dynamic->depth_bias.clamp =
1064 pCreateInfo->pRasterizationState->depthBiasClamp;
1065 dynamic->depth_bias.slope =
1066 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1067 }
1068
1069 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1070 *
1071 * pColorBlendState is [...] NULL if the pipeline has rasterization
1072 * disabled or if the subpass of the render pass the pipeline is
1073 * created against does not use any color attachments.
1074 */
1075 bool uses_color_att = false;
1076 for (unsigned i = 0; i < subpass->color_count; ++i) {
1077 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1078 uses_color_att = true;
1079 break;
1080 }
1081 }
1082
1083 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1084 assert(pCreateInfo->pColorBlendState);
1085 typed_memcpy(dynamic->blend_constants,
1086 pCreateInfo->pColorBlendState->blendConstants, 4);
1087 }
1088
1089 /* If there is no depthstencil attachment, then don't read
1090 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1091 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1092 * no need to override the depthstencil defaults in
1093 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1094 *
1095 * Section 9.2 of the Vulkan 1.0.15 spec says:
1096 *
1097 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1098 * disabled or if the subpass of the render pass the pipeline is created
1099 * against does not use a depth/stencil attachment.
1100 */
1101 if (needed_states &&
1102 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1103 assert(pCreateInfo->pDepthStencilState);
1104
1105 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1106 dynamic->depth_bounds.min =
1107 pCreateInfo->pDepthStencilState->minDepthBounds;
1108 dynamic->depth_bounds.max =
1109 pCreateInfo->pDepthStencilState->maxDepthBounds;
1110 }
1111
1112 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1113 dynamic->stencil_compare_mask.front =
1114 pCreateInfo->pDepthStencilState->front.compareMask;
1115 dynamic->stencil_compare_mask.back =
1116 pCreateInfo->pDepthStencilState->back.compareMask;
1117 }
1118
1119 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1120 dynamic->stencil_write_mask.front =
1121 pCreateInfo->pDepthStencilState->front.writeMask;
1122 dynamic->stencil_write_mask.back =
1123 pCreateInfo->pDepthStencilState->back.writeMask;
1124 }
1125
1126 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1127 dynamic->stencil_reference.front =
1128 pCreateInfo->pDepthStencilState->front.reference;
1129 dynamic->stencil_reference.back =
1130 pCreateInfo->pDepthStencilState->back.reference;
1131 }
1132 }
1133
1134 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1135 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1136 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1137 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1138 typed_memcpy(dynamic->discard_rectangle.rectangles,
1139 discard_rectangle_info->pDiscardRectangles,
1140 discard_rectangle_info->discardRectangleCount);
1141
1142 unsigned mask = 0;
1143
1144 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
1145 /* Interpret i as a bitmask, and then set the bit in the mask if
1146 * that combination of rectangles in which the pixel is contained
1147 * should pass the cliprect test. */
1148 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
1149
1150 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
1151 !relevant_subset)
1152 continue;
1153
1154 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
1155 relevant_subset)
1156 continue;
1157
1158 mask |= 1u << i;
1159 }
1160 pipeline->graphics.pa_sc_cliprect_rule = mask;
1161 } else {
1162 /* Allow from all rectangle combinations */
1163 pipeline->graphics.pa_sc_cliprect_rule = 0xffff;
1164 }
1165 pipeline->dynamic_state.mask = states;
1166 }
1167
1168 static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1169 struct radv_pipeline *pipeline)
1170 {
1171 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1172 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1173 &gs_info->tes.es_info : &gs_info->vs.es_info;
1174 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1175 bool uses_adjacency;
1176 switch(pCreateInfo->pInputAssemblyState->topology) {
1177 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1181 uses_adjacency = true;
1182 break;
1183 default:
1184 uses_adjacency = false;
1185 break;
1186 }
1187
1188 /* All these are in dwords: */
1189 /* We can't allow using the whole LDS, because GS waves compete with
1190 * other shader stages for LDS space. */
1191 const unsigned max_lds_size = 8 * 1024;
1192 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1193 unsigned esgs_lds_size;
1194
1195 /* All these are per subgroup: */
1196 const unsigned max_out_prims = 32 * 1024;
1197 const unsigned max_es_verts = 255;
1198 const unsigned ideal_gs_prims = 64;
1199 unsigned max_gs_prims, gs_prims;
1200 unsigned min_es_verts, es_verts, worst_case_es_verts;
1201
1202 if (uses_adjacency || gs_num_invocations > 1)
1203 max_gs_prims = 127 / gs_num_invocations;
1204 else
1205 max_gs_prims = 255;
1206
1207 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1208 * Make sure we don't go over the maximum value.
1209 */
1210 if (gs_info->gs.vertices_out > 0) {
1211 max_gs_prims = MIN2(max_gs_prims,
1212 max_out_prims /
1213 (gs_info->gs.vertices_out * gs_num_invocations));
1214 }
1215 assert(max_gs_prims > 0);
1216
1217 /* If the primitive has adjacency, halve the number of vertices
1218 * that will be reused in multiple primitives.
1219 */
1220 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1221
1222 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1223 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1224
1225 /* Compute ESGS LDS size based on the worst case number of ES vertices
1226 * needed to create the target number of GS prims per subgroup.
1227 */
1228 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1229
1230 /* If total LDS usage is too big, refactor partitions based on ratio
1231 * of ESGS item sizes.
1232 */
1233 if (esgs_lds_size > max_lds_size) {
1234 /* Our target GS Prims Per Subgroup was too large. Calculate
1235 * the maximum number of GS Prims Per Subgroup that will fit
1236 * into LDS, capped by the maximum that the hardware can support.
1237 */
1238 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1239 max_gs_prims);
1240 assert(gs_prims > 0);
1241 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1242 max_es_verts);
1243
1244 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1245 assert(esgs_lds_size <= max_lds_size);
1246 }
1247
1248 /* Now calculate remaining ESGS information. */
1249 if (esgs_lds_size)
1250 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1251 else
1252 es_verts = max_es_verts;
1253
1254 /* Vertices for adjacency primitives are not always reused, so restore
1255 * it for ES_VERTS_PER_SUBGRP.
1256 */
1257 min_es_verts = gs_info->gs.vertices_in;
1258
1259 /* For normal primitives, the VGT only checks if they are past the ES
1260 * verts per subgroup after allocating a full GS primitive and if they
1261 * are, kick off a new subgroup. But if those additional ES verts are
1262 * unique (e.g. not reused) we need to make sure there is enough LDS
1263 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1264 */
1265 es_verts -= min_es_verts - 1;
1266
1267 uint32_t es_verts_per_subgroup = es_verts;
1268 uint32_t gs_prims_per_subgroup = gs_prims;
1269 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1270 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1271 pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128;
1272 pipeline->graphics.gs.vgt_gs_onchip_cntl =
1273 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1274 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1275 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1276 pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup =
1277 S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1278 pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1279 assert(max_prims_per_subgroup <= max_out_prims);
1280 }
1281
1282 static void
1283 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1284 {
1285 struct radv_device *device = pipeline->device;
1286 unsigned num_se = device->physical_device->rad_info.max_se;
1287 unsigned wave_size = 64;
1288 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1289 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1290 unsigned alignment = 256 * num_se;
1291 /* The maximum size is 63.999 MB per SE. */
1292 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1293 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1294 struct ac_es_output_info *es_info;
1295 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1296 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1297 else
1298 es_info = radv_pipeline_has_tess(pipeline) ?
1299 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1300 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1301
1302 /* Calculate the minimum size. */
1303 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1304 wave_size, alignment);
1305 /* These are recommended sizes, not minimum sizes. */
1306 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1307 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1308 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1309 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1310
1311 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1312 esgs_ring_size = align(esgs_ring_size, alignment);
1313 gsvs_ring_size = align(gsvs_ring_size, alignment);
1314
1315 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1316 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1317
1318 pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1319 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1320 }
1321
1322 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1323 unsigned *lds_size)
1324 {
1325 /* SPI barrier management bug:
1326 * Make sure we have at least 4k of LDS in use to avoid the bug.
1327 * It applies to workgroup sizes of more than one wavefront.
1328 */
1329 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1330 device->physical_device->rad_info.family == CHIP_KABINI ||
1331 device->physical_device->rad_info.family == CHIP_MULLINS)
1332 *lds_size = MAX2(*lds_size, 8);
1333 }
1334
1335 struct radv_shader_variant *
1336 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1337 {
1338 if (pipeline->shaders[MESA_SHADER_VERTEX])
1339 return pipeline->shaders[MESA_SHADER_VERTEX];
1340 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1341 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1342 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1343 }
1344
1345 static struct radv_shader_variant *
1346 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1347 {
1348 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1349 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1350 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1351 }
1352
1353 static void
1354 calculate_tess_state(struct radv_pipeline *pipeline,
1355 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1356 {
1357 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1358 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1359 unsigned num_tcs_patch_outputs;
1360 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1361 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1362 unsigned lds_size, hardware_lds_size;
1363 unsigned perpatch_output_offset;
1364 unsigned num_patches;
1365 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1366
1367 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1368 * are laid out in LDS. */
1369 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1370
1371 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1372 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1373 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1374
1375 /* Ensure that we only need one wave per SIMD so we don't need to check
1376 * resource usage. Also ensures that the number of tcs in and out
1377 * vertices per threadgroup are at most 256.
1378 */
1379 input_vertex_size = num_tcs_inputs * 16;
1380 output_vertex_size = num_tcs_outputs * 16;
1381
1382 input_patch_size = num_tcs_input_cp * input_vertex_size;
1383
1384 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1385 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1386 /* Ensure that we only need one wave per SIMD so we don't need to check
1387 * resource usage. Also ensures that the number of tcs in and out
1388 * vertices per threadgroup are at most 256.
1389 */
1390 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1391
1392 /* Make sure that the data fits in LDS. This assumes the shaders only
1393 * use LDS for the inputs and outputs.
1394 */
1395 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1396 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1397
1398 /* Make sure the output data fits in the offchip buffer */
1399 num_patches = MIN2(num_patches,
1400 (pipeline->device->tess_offchip_block_dw_size * 4) /
1401 output_patch_size);
1402
1403 /* Not necessary for correctness, but improves performance. The
1404 * specific value is taken from the proprietary driver.
1405 */
1406 num_patches = MIN2(num_patches, 40);
1407
1408 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1409 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1410 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1411 num_patches = MIN2(num_patches, one_wave);
1412 }
1413
1414 output_patch0_offset = input_patch_size * num_patches;
1415 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1416
1417 lds_size = output_patch0_offset + output_patch_size * num_patches;
1418
1419 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1420 assert(lds_size <= 65536);
1421 lds_size = align(lds_size, 512) / 512;
1422 } else {
1423 assert(lds_size <= 32768);
1424 lds_size = align(lds_size, 256) / 256;
1425 }
1426 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1427
1428 tess->lds_size = lds_size;
1429
1430 tess->tcs_in_layout = (input_patch_size / 4) |
1431 ((input_vertex_size / 4) << 13);
1432 tess->tcs_out_layout = (output_patch_size / 4) |
1433 ((output_vertex_size / 4) << 13);
1434 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1435 ((perpatch_output_offset / 16) << 16);
1436 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1437 (num_tcs_output_cp << 9) | num_patches;
1438
1439 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1440 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1441 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1442 tess->num_patches = num_patches;
1443 tess->num_tcs_input_cp = num_tcs_input_cp;
1444
1445 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1446 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1447
1448 switch (tes->info.tes.primitive_mode) {
1449 case GL_TRIANGLES:
1450 type = V_028B6C_TESS_TRIANGLE;
1451 break;
1452 case GL_QUADS:
1453 type = V_028B6C_TESS_QUAD;
1454 break;
1455 case GL_ISOLINES:
1456 type = V_028B6C_TESS_ISOLINE;
1457 break;
1458 }
1459
1460 switch (tes->info.tes.spacing) {
1461 case TESS_SPACING_EQUAL:
1462 partitioning = V_028B6C_PART_INTEGER;
1463 break;
1464 case TESS_SPACING_FRACTIONAL_ODD:
1465 partitioning = V_028B6C_PART_FRAC_ODD;
1466 break;
1467 case TESS_SPACING_FRACTIONAL_EVEN:
1468 partitioning = V_028B6C_PART_FRAC_EVEN;
1469 break;
1470 default:
1471 break;
1472 }
1473
1474 bool ccw = tes->info.tes.ccw;
1475 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1476 vk_find_struct_const(pCreateInfo->pTessellationState,
1477 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1478
1479 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1480 ccw = !ccw;
1481
1482 if (tes->info.tes.point_mode)
1483 topology = V_028B6C_OUTPUT_POINT;
1484 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1485 topology = V_028B6C_OUTPUT_LINE;
1486 else if (ccw)
1487 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1488 else
1489 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1490
1491 if (pipeline->device->has_distributed_tess) {
1492 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1493 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1494 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1495 else
1496 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1497 } else
1498 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1499
1500 tess->tf_param = S_028B6C_TYPE(type) |
1501 S_028B6C_PARTITIONING(partitioning) |
1502 S_028B6C_TOPOLOGY(topology) |
1503 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1504 }
1505
1506 static const struct radv_prim_vertex_count prim_size_table[] = {
1507 [V_008958_DI_PT_NONE] = {0, 0},
1508 [V_008958_DI_PT_POINTLIST] = {1, 1},
1509 [V_008958_DI_PT_LINELIST] = {2, 2},
1510 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1511 [V_008958_DI_PT_TRILIST] = {3, 3},
1512 [V_008958_DI_PT_TRIFAN] = {3, 1},
1513 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1514 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1515 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1516 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1517 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1518 [V_008958_DI_PT_RECTLIST] = {3, 3},
1519 [V_008958_DI_PT_LINELOOP] = {2, 1},
1520 [V_008958_DI_PT_POLYGON] = {3, 1},
1521 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1522 };
1523
1524 static const struct ac_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1525 {
1526 if (radv_pipeline_has_gs(pipeline))
1527 return &pipeline->gs_copy_shader->info.vs.outinfo;
1528 else if (radv_pipeline_has_tess(pipeline))
1529 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1530 else
1531 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1532 }
1533
1534 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1535 {
1536 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1537
1538 pipeline->graphics.vgt_primitiveid_en = false;
1539 pipeline->graphics.vgt_gs_mode = 0;
1540
1541 if (radv_pipeline_has_gs(pipeline)) {
1542 struct radv_shader_variant *gs =
1543 pipeline->shaders[MESA_SHADER_GEOMETRY];
1544
1545 pipeline->graphics.vgt_gs_mode =
1546 ac_vgt_gs_mode(gs->info.gs.vertices_out,
1547 pipeline->device->physical_device->rad_info.chip_class);
1548 } else if (outinfo->export_prim_id) {
1549 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1550 pipeline->graphics.vgt_primitiveid_en = true;
1551 }
1552 }
1553
1554 static void
1555 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1556 {
1557 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1558 int shader_count = 0;
1559
1560 if(shaders[MESA_SHADER_FRAGMENT]) {
1561 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1562 }
1563 if(shaders[MESA_SHADER_GEOMETRY]) {
1564 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1565 }
1566 if(shaders[MESA_SHADER_TESS_EVAL]) {
1567 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1568 }
1569 if(shaders[MESA_SHADER_TESS_CTRL]) {
1570 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1571 }
1572 if(shaders[MESA_SHADER_VERTEX]) {
1573 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1574 }
1575
1576 for (int i = 1; i < shader_count; ++i) {
1577 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1578 ordered_shaders[i - 1]);
1579
1580 nir_remove_dead_variables(ordered_shaders[i],
1581 nir_var_shader_out);
1582 nir_remove_dead_variables(ordered_shaders[i - 1],
1583 nir_var_shader_in);
1584
1585 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1586 ordered_shaders[i - 1]);
1587
1588 if (progress) {
1589 nir_lower_global_vars_to_local(ordered_shaders[i]);
1590 radv_optimize_nir(ordered_shaders[i]);
1591 nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
1592 radv_optimize_nir(ordered_shaders[i - 1]);
1593 }
1594 }
1595 }
1596
1597
1598 static struct radv_pipeline_key
1599 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1600 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1601 bool has_view_index)
1602 {
1603 const VkPipelineVertexInputStateCreateInfo *input_state =
1604 pCreateInfo->pVertexInputState;
1605 struct radv_pipeline_key key;
1606 memset(&key, 0, sizeof(key));
1607
1608 key.has_multiview_view_index = has_view_index;
1609
1610 uint32_t binding_input_rate = 0;
1611 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1612 if (input_state->pVertexBindingDescriptions[i].inputRate)
1613 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1614 }
1615
1616 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1617 unsigned binding;
1618 binding = input_state->pVertexAttributeDescriptions[i].binding;
1619 if (binding_input_rate & (1u << binding))
1620 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1621 }
1622
1623 if (pCreateInfo->pTessellationState)
1624 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1625
1626
1627 if (pCreateInfo->pMultisampleState &&
1628 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1629 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1630 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1631 key.multisample = true;
1632 key.log2_num_samples = util_logbase2(num_samples);
1633 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1634 }
1635
1636 key.col_format = pipeline->graphics.blend.spi_shader_col_format;
1637 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1638 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1639
1640 return key;
1641 }
1642
1643 static void
1644 radv_fill_shader_keys(struct ac_shader_variant_key *keys,
1645 const struct radv_pipeline_key *key,
1646 nir_shader **nir)
1647 {
1648 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1649
1650 if (nir[MESA_SHADER_TESS_CTRL]) {
1651 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1652 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1653 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1654
1655 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1656 }
1657
1658 if (nir[MESA_SHADER_GEOMETRY]) {
1659 if (nir[MESA_SHADER_TESS_CTRL])
1660 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1661 else
1662 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1663 }
1664
1665 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1666 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1667
1668 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1669 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1670 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1671 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1672 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1673 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1674 }
1675
1676 static void
1677 merge_tess_info(struct shader_info *tes_info,
1678 const struct shader_info *tcs_info)
1679 {
1680 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1681 *
1682 * "PointMode. Controls generation of points rather than triangles
1683 * or lines. This functionality defaults to disabled, and is
1684 * enabled if either shader stage includes the execution mode.
1685 *
1686 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1687 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1688 * and OutputVertices, it says:
1689 *
1690 * "One mode must be set in at least one of the tessellation
1691 * shader stages."
1692 *
1693 * So, the fields can be set in either the TCS or TES, but they must
1694 * agree if set in both. Our backend looks at TES, so bitwise-or in
1695 * the values from the TCS.
1696 */
1697 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1698 tes_info->tess.tcs_vertices_out == 0 ||
1699 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1700 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1701
1702 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1703 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1704 tcs_info->tess.spacing == tes_info->tess.spacing);
1705 tes_info->tess.spacing |= tcs_info->tess.spacing;
1706
1707 assert(tcs_info->tess.primitive_mode == 0 ||
1708 tes_info->tess.primitive_mode == 0 ||
1709 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1710 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1711 tes_info->tess.ccw |= tcs_info->tess.ccw;
1712 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1713 }
1714
1715 static
1716 void radv_create_shaders(struct radv_pipeline *pipeline,
1717 struct radv_device *device,
1718 struct radv_pipeline_cache *cache,
1719 struct radv_pipeline_key key,
1720 const VkPipelineShaderStageCreateInfo **pStages)
1721 {
1722 struct radv_shader_module fs_m = {0};
1723 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1724 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1725 void *codes[MESA_SHADER_STAGES] = {0};
1726 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1727 struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1728 unsigned char hash[20], gs_copy_hash[20];
1729
1730 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1731 if (pStages[i]) {
1732 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1733 if (modules[i]->nir)
1734 _mesa_sha1_compute(modules[i]->nir->info.name,
1735 strlen(modules[i]->nir->info.name),
1736 modules[i]->sha1);
1737 }
1738 }
1739
1740 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1741 memcpy(gs_copy_hash, hash, 20);
1742 gs_copy_hash[0] ^= 1;
1743
1744 if (modules[MESA_SHADER_GEOMETRY]) {
1745 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1746 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1747 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1748 }
1749
1750 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1751 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1752 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1753 if (pipeline->shaders[i])
1754 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1755 }
1756 return;
1757 }
1758
1759 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1760 nir_builder fs_b;
1761 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1762 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1763 fs_m.nir = fs_b.shader;
1764 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1765 }
1766
1767 /* Determine first and last stage. */
1768 unsigned first = MESA_SHADER_STAGES;
1769 unsigned last = 0;
1770 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1771 if (!pStages[i])
1772 continue;
1773 if (first == MESA_SHADER_STAGES)
1774 first = i;
1775 last = i;
1776 }
1777
1778 int prev = -1;
1779 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1780 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1781
1782 if (!modules[i])
1783 continue;
1784
1785 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1786 stage ? stage->pName : "main", i,
1787 stage ? stage->pSpecializationInfo : NULL);
1788 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1789
1790 /* We don't want to alter meta shaders IR directly so clone it
1791 * first.
1792 */
1793 if (nir[i]->info.name) {
1794 nir[i] = nir_shader_clone(NULL, nir[i]);
1795 }
1796
1797 if (first != last) {
1798 nir_variable_mode mask = 0;
1799
1800 if (i != first)
1801 mask = mask | nir_var_shader_in;
1802
1803 if (i != last)
1804 mask = mask | nir_var_shader_out;
1805
1806 nir_lower_io_to_scalar_early(nir[i], mask);
1807 radv_optimize_nir(nir[i]);
1808 }
1809
1810 if (prev != -1) {
1811 nir_compact_varyings(nir[prev], nir[i], true);
1812 }
1813 prev = i;
1814 }
1815
1816 if (nir[MESA_SHADER_TESS_CTRL]) {
1817 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1818 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1819 }
1820
1821 radv_link_shaders(pipeline, nir);
1822
1823 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1824 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1825 nir_print_shader(nir[i], stderr);
1826 }
1827
1828 radv_fill_shader_keys(keys, &key, nir);
1829
1830 if (nir[MESA_SHADER_FRAGMENT]) {
1831 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1832 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1833 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1834 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1835 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1836 }
1837
1838 /* TODO: These are no longer used as keys we should refactor this */
1839 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1840 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1841 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1842 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1843 }
1844
1845 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1846 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1847 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1848 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1849 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1850 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1851 pipeline->layout,
1852 &key, &codes[MESA_SHADER_TESS_CTRL],
1853 &code_sizes[MESA_SHADER_TESS_CTRL]);
1854 }
1855 modules[MESA_SHADER_VERTEX] = NULL;
1856 }
1857
1858 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1859 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1860 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1861 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1862 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1863 pipeline->layout,
1864 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1865 &code_sizes[MESA_SHADER_GEOMETRY]);
1866 }
1867 modules[pre_stage] = NULL;
1868 }
1869
1870 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1871 if(modules[i] && !pipeline->shaders[i]) {
1872 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1873 pipeline->layout,
1874 keys + i, &codes[i],
1875 &code_sizes[i]);
1876 }
1877 }
1878
1879 if(modules[MESA_SHADER_GEOMETRY]) {
1880 void *gs_copy_code = NULL;
1881 unsigned gs_copy_code_size = 0;
1882 if (!pipeline->gs_copy_shader) {
1883 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1884 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1885 &gs_copy_code_size,
1886 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1887 }
1888
1889 if (pipeline->gs_copy_shader) {
1890 void *code[MESA_SHADER_STAGES] = {0};
1891 unsigned code_size[MESA_SHADER_STAGES] = {0};
1892 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1893
1894 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1895 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1896 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1897
1898 radv_pipeline_cache_insert_shaders(device, cache,
1899 gs_copy_hash,
1900 variants,
1901 (const void**)code,
1902 code_size);
1903 }
1904 free(gs_copy_code);
1905 }
1906
1907 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1908 (const void**)codes, code_sizes);
1909
1910 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1911 free(codes[i]);
1912 if (modules[i] && !pipeline->device->keep_shader_info)
1913 ralloc_free(nir[i]);
1914 }
1915
1916 if (fs_m.nir)
1917 ralloc_free(fs_m.nir);
1918 }
1919
1920 static uint32_t
1921 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1922 gl_shader_stage stage, enum chip_class chip_class)
1923 {
1924 bool has_gs = radv_pipeline_has_gs(pipeline);
1925 bool has_tess = radv_pipeline_has_tess(pipeline);
1926 switch (stage) {
1927 case MESA_SHADER_FRAGMENT:
1928 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1929 case MESA_SHADER_VERTEX:
1930 if (chip_class >= GFX9) {
1931 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1932 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1933 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1934 }
1935 if (has_tess)
1936 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1937 else
1938 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1939 case MESA_SHADER_GEOMETRY:
1940 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1941 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1942 case MESA_SHADER_COMPUTE:
1943 return R_00B900_COMPUTE_USER_DATA_0;
1944 case MESA_SHADER_TESS_CTRL:
1945 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1946 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1947 case MESA_SHADER_TESS_EVAL:
1948 if (chip_class >= GFX9) {
1949 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1950 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1951 }
1952 if (has_gs)
1953 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1954 else
1955 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1956 default:
1957 unreachable("unknown shader");
1958 }
1959 }
1960
1961 struct radv_bin_size_entry {
1962 unsigned bpp;
1963 VkExtent2D extent;
1964 };
1965
1966 static VkExtent2D
1967 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1968 {
1969 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1970 {
1971 /* One RB / SE */
1972 {
1973 /* One shader engine */
1974 { 0, {128, 128}},
1975 { 1, { 64, 128}},
1976 { 2, { 32, 128}},
1977 { 3, { 16, 128}},
1978 { 17, { 0, 0}},
1979 { UINT_MAX, { 0, 0}},
1980 },
1981 {
1982 /* Two shader engines */
1983 { 0, {128, 128}},
1984 { 2, { 64, 128}},
1985 { 3, { 32, 128}},
1986 { 5, { 16, 128}},
1987 { 17, { 0, 0}},
1988 { UINT_MAX, { 0, 0}},
1989 },
1990 {
1991 /* Four shader engines */
1992 { 0, {128, 128}},
1993 { 3, { 64, 128}},
1994 { 5, { 16, 128}},
1995 { 17, { 0, 0}},
1996 { UINT_MAX, { 0, 0}},
1997 },
1998 },
1999 {
2000 /* Two RB / SE */
2001 {
2002 /* One shader engine */
2003 { 0, {128, 128}},
2004 { 2, { 64, 128}},
2005 { 3, { 32, 128}},
2006 { 5, { 16, 128}},
2007 { 33, { 0, 0}},
2008 { UINT_MAX, { 0, 0}},
2009 },
2010 {
2011 /* Two shader engines */
2012 { 0, {128, 128}},
2013 { 3, { 64, 128}},
2014 { 5, { 32, 128}},
2015 { 9, { 16, 128}},
2016 { 33, { 0, 0}},
2017 { UINT_MAX, { 0, 0}},
2018 },
2019 {
2020 /* Four shader engines */
2021 { 0, {256, 256}},
2022 { 2, {128, 256}},
2023 { 3, {128, 128}},
2024 { 5, { 64, 128}},
2025 { 9, { 16, 128}},
2026 { 33, { 0, 0}},
2027 { UINT_MAX, { 0, 0}},
2028 },
2029 },
2030 {
2031 /* Four RB / SE */
2032 {
2033 /* One shader engine */
2034 { 0, {128, 256}},
2035 { 2, {128, 128}},
2036 { 3, { 64, 128}},
2037 { 5, { 32, 128}},
2038 { 9, { 16, 128}},
2039 { 33, { 0, 0}},
2040 { UINT_MAX, { 0, 0}},
2041 },
2042 {
2043 /* Two shader engines */
2044 { 0, {256, 256}},
2045 { 2, {128, 256}},
2046 { 3, {128, 128}},
2047 { 5, { 64, 128}},
2048 { 9, { 32, 128}},
2049 { 17, { 16, 128}},
2050 { 33, { 0, 0}},
2051 { UINT_MAX, { 0, 0}},
2052 },
2053 {
2054 /* Four shader engines */
2055 { 0, {256, 512}},
2056 { 2, {256, 256}},
2057 { 3, {128, 256}},
2058 { 5, {128, 128}},
2059 { 9, { 64, 128}},
2060 { 17, { 16, 128}},
2061 { 33, { 0, 0}},
2062 { UINT_MAX, { 0, 0}},
2063 },
2064 },
2065 };
2066 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2067 {
2068 // One RB / SE
2069 {
2070 // One shader engine
2071 { 0, {128, 256}},
2072 { 2, {128, 128}},
2073 { 4, { 64, 128}},
2074 { 7, { 32, 128}},
2075 { 13, { 16, 128}},
2076 { 49, { 0, 0}},
2077 { UINT_MAX, { 0, 0}},
2078 },
2079 {
2080 // Two shader engines
2081 { 0, {256, 256}},
2082 { 2, {128, 256}},
2083 { 4, {128, 128}},
2084 { 7, { 64, 128}},
2085 { 13, { 32, 128}},
2086 { 25, { 16, 128}},
2087 { 49, { 0, 0}},
2088 { UINT_MAX, { 0, 0}},
2089 },
2090 {
2091 // Four shader engines
2092 { 0, {256, 512}},
2093 { 2, {256, 256}},
2094 { 4, {128, 256}},
2095 { 7, {128, 128}},
2096 { 13, { 64, 128}},
2097 { 25, { 16, 128}},
2098 { 49, { 0, 0}},
2099 { UINT_MAX, { 0, 0}},
2100 },
2101 },
2102 {
2103 // Two RB / SE
2104 {
2105 // One shader engine
2106 { 0, {256, 256}},
2107 { 2, {128, 256}},
2108 { 4, {128, 128}},
2109 { 7, { 64, 128}},
2110 { 13, { 32, 128}},
2111 { 25, { 16, 128}},
2112 { 97, { 0, 0}},
2113 { UINT_MAX, { 0, 0}},
2114 },
2115 {
2116 // Two shader engines
2117 { 0, {256, 512}},
2118 { 2, {256, 256}},
2119 { 4, {128, 256}},
2120 { 7, {128, 128}},
2121 { 13, { 64, 128}},
2122 { 25, { 32, 128}},
2123 { 49, { 16, 128}},
2124 { 97, { 0, 0}},
2125 { UINT_MAX, { 0, 0}},
2126 },
2127 {
2128 // Four shader engines
2129 { 0, {512, 512}},
2130 { 2, {256, 512}},
2131 { 4, {256, 256}},
2132 { 7, {128, 256}},
2133 { 13, {128, 128}},
2134 { 25, { 64, 128}},
2135 { 49, { 16, 128}},
2136 { 97, { 0, 0}},
2137 { UINT_MAX, { 0, 0}},
2138 },
2139 },
2140 {
2141 // Four RB / SE
2142 {
2143 // One shader engine
2144 { 0, {256, 512}},
2145 { 2, {256, 256}},
2146 { 4, {128, 256}},
2147 { 7, {128, 128}},
2148 { 13, { 64, 128}},
2149 { 25, { 32, 128}},
2150 { 49, { 16, 128}},
2151 { UINT_MAX, { 0, 0}},
2152 },
2153 {
2154 // Two shader engines
2155 { 0, {512, 512}},
2156 { 2, {256, 512}},
2157 { 4, {256, 256}},
2158 { 7, {128, 256}},
2159 { 13, {128, 128}},
2160 { 25, { 64, 128}},
2161 { 49, { 32, 128}},
2162 { 97, { 16, 128}},
2163 { UINT_MAX, { 0, 0}},
2164 },
2165 {
2166 // Four shader engines
2167 { 0, {512, 512}},
2168 { 4, {256, 512}},
2169 { 7, {256, 256}},
2170 { 13, {128, 256}},
2171 { 25, {128, 128}},
2172 { 49, { 64, 128}},
2173 { 97, { 16, 128}},
2174 { UINT_MAX, { 0, 0}},
2175 },
2176 },
2177 };
2178
2179 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2180 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2181 VkExtent2D extent = {512, 512};
2182
2183 unsigned log_num_rb_per_se =
2184 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2185 pipeline->device->physical_device->rad_info.max_se);
2186 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2187
2188 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2189 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2190 unsigned effective_samples = total_samples;
2191 unsigned cb_target_mask = pipeline->graphics.blend.cb_target_mask;
2192 unsigned color_bytes_per_pixel = 0;
2193
2194 for (unsigned i = 0; i < subpass->color_count; i++) {
2195 if (!(cb_target_mask & (0xf << (i * 4))))
2196 continue;
2197
2198 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2199 continue;
2200
2201 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2202 color_bytes_per_pixel += vk_format_get_blocksize(format);
2203 }
2204
2205 /* MSAA images typically don't use all samples all the time. */
2206 if (effective_samples >= 2 && ps_iter_samples <= 1)
2207 effective_samples = 2;
2208 color_bytes_per_pixel *= effective_samples;
2209
2210 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2211 while(color_entry->bpp <= color_bytes_per_pixel)
2212 ++color_entry;
2213
2214 extent = color_entry->extent;
2215
2216 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2217 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2218
2219 /* Coefficients taken from AMDVLK */
2220 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2221 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2222 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2223
2224 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2225 while(ds_entry->bpp <= ds_bytes_per_pixel)
2226 ++ds_entry;
2227
2228 extent.width = MIN2(extent.width, ds_entry->extent.width);
2229 extent.height = MIN2(extent.height, ds_entry->extent.height);
2230 }
2231
2232 return extent;
2233 }
2234
2235 static void
2236 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2237 struct radv_pipeline *pipeline,
2238 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2239 {
2240 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2241 return;
2242
2243 uint32_t pa_sc_binner_cntl_0 =
2244 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2245 S_028C44_DISABLE_START_OF_PRIM(1);
2246 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2247
2248 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2249
2250 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2251 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2252 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2253
2254 switch (pipeline->device->physical_device->rad_info.family) {
2255 case CHIP_VEGA10:
2256 context_states_per_bin = 1;
2257 persistent_states_per_bin = 1;
2258 fpovs_per_batch = 63;
2259 break;
2260 case CHIP_RAVEN:
2261 context_states_per_bin = 6;
2262 persistent_states_per_bin = 32;
2263 fpovs_per_batch = 63;
2264 break;
2265 default:
2266 unreachable("unhandled family while determining binning state.");
2267 }
2268
2269 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2270 pa_sc_binner_cntl_0 =
2271 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2272 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2273 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2274 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2275 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2276 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2277 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2278 S_028C44_DISABLE_START_OF_PRIM(1) |
2279 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2280 S_028C44_OPTIMAL_BIN_SELECTION(1);
2281 }
2282
2283 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2284 pa_sc_binner_cntl_0);
2285 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2286 db_dfsm_control);
2287 }
2288
2289
2290 static void
2291 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2292 struct radv_pipeline *pipeline,
2293 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2294 const struct radv_graphics_pipeline_create_info *extra)
2295 {
2296 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2297 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2298 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2299 struct radv_render_pass_attachment *attachment = NULL;
2300 uint32_t db_depth_control = 0, db_stencil_control = 0;
2301 uint32_t db_render_control = 0, db_render_override2 = 0;
2302
2303 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2304 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2305
2306 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2307 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2308
2309 if (vkds && has_depth_attachment) {
2310 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2311 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2312 S_028800_ZFUNC(vkds->depthCompareOp) |
2313 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2314
2315 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2316 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2317 }
2318
2319 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2320 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2321 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2322 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2323 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2324 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2325
2326 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2327 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2328 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2329 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2330 }
2331
2332 if (attachment && extra) {
2333 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2334 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2335
2336 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2337 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2338 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2339 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2340 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2341 }
2342
2343 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2344 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2345
2346 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2347 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2348 }
2349
2350 static void
2351 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2352 struct radv_pipeline *pipeline)
2353 {
2354 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2355 radeon_emit_array(cs, pipeline->graphics.blend.cb_blend_control,
2356 8);
2357 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
2358 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
2359
2360 if (pipeline->device->physical_device->has_rbplus) {
2361
2362 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2363 radeon_emit_array(cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
2364
2365 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2366 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2367 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2368 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2369 }
2370 }
2371
2372
2373 static void
2374 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2375 struct radv_pipeline *pipeline)
2376 {
2377 struct radv_raster_state *raster = &pipeline->graphics.raster;
2378
2379 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2380 raster->pa_cl_clip_cntl);
2381 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2382 raster->spi_interp_control);
2383 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2384 raster->pa_su_vtx_cntl);
2385 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2386 raster->pa_su_sc_mode_cntl);
2387 }
2388
2389
2390 static void
2391 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2392 struct radv_pipeline *pipeline)
2393 {
2394 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2395
2396 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2397 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2398 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2399
2400 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2401 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2402
2403 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2404 uint32_t offset;
2405 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2406 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2407 if (loc->sgpr_idx == -1)
2408 return;
2409 assert(loc->num_sgprs == 1);
2410 assert(!loc->indirect);
2411 switch (pipeline->graphics.ms.num_samples) {
2412 default:
2413 offset = 0;
2414 break;
2415 case 2:
2416 offset = 1;
2417 break;
2418 case 4:
2419 offset = 3;
2420 break;
2421 case 8:
2422 offset = 7;
2423 break;
2424 case 16:
2425 offset = 15;
2426 break;
2427 }
2428
2429 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2430 }
2431 }
2432
2433 static void
2434 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2435 struct radv_pipeline *pipeline,
2436 struct radv_shader_variant *shader)
2437 {
2438 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2439
2440 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2441 radeon_emit(cs, va >> 8);
2442 radeon_emit(cs, va >> 40);
2443 radeon_emit(cs, shader->rsrc1);
2444 radeon_emit(cs, shader->rsrc2);
2445
2446 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
2447 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2448 clip_dist_mask = outinfo->clip_dist_mask;
2449 cull_dist_mask = outinfo->cull_dist_mask;
2450 total_mask = clip_dist_mask | cull_dist_mask;
2451 bool misc_vec_ena = outinfo->writes_pointsize ||
2452 outinfo->writes_layer ||
2453 outinfo->writes_viewport_index;
2454
2455 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2456 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2457
2458 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2459 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2460 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2461 V_02870C_SPI_SHADER_4COMP :
2462 V_02870C_SPI_SHADER_NONE) |
2463 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2464 V_02870C_SPI_SHADER_4COMP :
2465 V_02870C_SPI_SHADER_NONE) |
2466 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2467 V_02870C_SPI_SHADER_4COMP :
2468 V_02870C_SPI_SHADER_NONE));
2469
2470 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2471 S_028818_VTX_W0_FMT(1) |
2472 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2473 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2474 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2475
2476 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2477 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2478 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2479 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2480 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2481 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2482 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2483 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2484 cull_dist_mask << 8 |
2485 clip_dist_mask);
2486
2487 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2488 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2489 outinfo->writes_viewport_index);
2490 }
2491
2492 static void
2493 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2494 struct radv_pipeline *pipeline,
2495 struct radv_shader_variant *shader)
2496 {
2497 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2498
2499 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2500 radeon_emit(cs, va >> 8);
2501 radeon_emit(cs, va >> 40);
2502 radeon_emit(cs, shader->rsrc1);
2503 radeon_emit(cs, shader->rsrc2);
2504 }
2505
2506 static void
2507 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2508 struct radv_pipeline *pipeline,
2509 struct radv_shader_variant *shader)
2510 {
2511 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2512 uint32_t rsrc2 = shader->rsrc2;
2513
2514 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2515 radeon_emit(cs, va >> 8);
2516 radeon_emit(cs, va >> 40);
2517
2518 rsrc2 |= S_00B52C_LDS_SIZE(pipeline->graphics.tess.lds_size);
2519 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2520 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2521 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2522
2523 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2524 radeon_emit(cs, shader->rsrc1);
2525 radeon_emit(cs, rsrc2);
2526 }
2527
2528 static void
2529 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2530 struct radv_pipeline *pipeline,
2531 struct radv_shader_variant *shader)
2532 {
2533 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2534
2535 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2536 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2537 radeon_emit(cs, va >> 8);
2538 radeon_emit(cs, va >> 40);
2539
2540 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2541 radeon_emit(cs, shader->rsrc1);
2542 radeon_emit(cs, shader->rsrc2 |
2543 S_00B42C_LDS_SIZE(pipeline->graphics.tess.lds_size));
2544 } else {
2545 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2546 radeon_emit(cs, va >> 8);
2547 radeon_emit(cs, va >> 40);
2548 radeon_emit(cs, shader->rsrc1);
2549 radeon_emit(cs, shader->rsrc2);
2550 }
2551 }
2552
2553 static void
2554 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2555 struct radv_pipeline *pipeline)
2556 {
2557 struct radv_shader_variant *vs;
2558
2559 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
2560
2561 /* Skip shaders merged into HS/GS */
2562 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2563 if (!vs)
2564 return;
2565
2566 if (vs->info.vs.as_ls)
2567 radv_pipeline_generate_hw_ls(cs, pipeline, vs);
2568 else if (vs->info.vs.as_es)
2569 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2570 else
2571 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2572 }
2573
2574 static void
2575 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2576 struct radv_pipeline *pipeline)
2577 {
2578 if (!radv_pipeline_has_tess(pipeline))
2579 return;
2580
2581 struct radv_shader_variant *tes, *tcs;
2582
2583 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2584 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2585
2586 if (tes) {
2587 if (tes->info.tes.as_es)
2588 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2589 else
2590 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2591 }
2592
2593 radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
2594
2595 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2596 pipeline->graphics.tess.tf_param);
2597
2598 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2599 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2600 pipeline->graphics.tess.ls_hs_config);
2601 else
2602 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2603 pipeline->graphics.tess.ls_hs_config);
2604
2605 struct ac_userdata_info *loc;
2606
2607 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
2608 if (loc->sgpr_idx != -1) {
2609 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
2610 assert(loc->num_sgprs == 4);
2611 assert(!loc->indirect);
2612 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
2613 radeon_emit(cs, pipeline->graphics.tess.offchip_layout);
2614 radeon_emit(cs, pipeline->graphics.tess.tcs_out_offsets);
2615 radeon_emit(cs, pipeline->graphics.tess.tcs_out_layout |
2616 pipeline->graphics.tess.num_tcs_input_cp << 26);
2617 radeon_emit(cs, pipeline->graphics.tess.tcs_in_layout);
2618 }
2619
2620 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
2621 if (loc->sgpr_idx != -1) {
2622 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
2623 assert(loc->num_sgprs == 1);
2624 assert(!loc->indirect);
2625
2626 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2627 pipeline->graphics.tess.offchip_layout);
2628 }
2629
2630 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
2631 if (loc->sgpr_idx != -1) {
2632 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
2633 assert(loc->num_sgprs == 1);
2634 assert(!loc->indirect);
2635
2636 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2637 pipeline->graphics.tess.tcs_in_layout);
2638 }
2639 }
2640
2641 static void
2642 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2643 struct radv_pipeline *pipeline)
2644 {
2645 struct radv_shader_variant *gs;
2646 uint64_t va;
2647
2648 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
2649
2650 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2651 if (!gs)
2652 return;
2653
2654 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2655
2656 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2657 radeon_emit(cs, gsvs_itemsize);
2658 radeon_emit(cs, gsvs_itemsize);
2659 radeon_emit(cs, gsvs_itemsize);
2660
2661 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2662
2663 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2664
2665 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2666 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2667 radeon_emit(cs, gs_vert_itemsize >> 2);
2668 radeon_emit(cs, 0);
2669 radeon_emit(cs, 0);
2670 radeon_emit(cs, 0);
2671
2672 uint32_t gs_num_invocations = gs->info.gs.invocations;
2673 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2674 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2675 S_028B90_ENABLE(gs_num_invocations > 0));
2676
2677 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2678 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
2679
2680 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2681
2682 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2683 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2684 radeon_emit(cs, va >> 8);
2685 radeon_emit(cs, va >> 40);
2686
2687 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2688 radeon_emit(cs, gs->rsrc1);
2689 radeon_emit(cs, gs->rsrc2 |
2690 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
2691
2692 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
2693 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
2694 } else {
2695 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2696 radeon_emit(cs, va >> 8);
2697 radeon_emit(cs, va >> 40);
2698 radeon_emit(cs, gs->rsrc1);
2699 radeon_emit(cs, gs->rsrc2);
2700 }
2701
2702 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2703
2704 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2705 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
2706 if (loc->sgpr_idx != -1) {
2707 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
2708 uint32_t num_entries = 64;
2709 bool is_vi = pipeline->device->physical_device->rad_info.chip_class >= VI;
2710
2711 if (is_vi)
2712 num_entries *= stride;
2713
2714 stride = S_008F04_STRIDE(stride);
2715 radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
2716 radeon_emit(cs, stride);
2717 radeon_emit(cs, num_entries);
2718 }
2719 }
2720
2721 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2722 {
2723 uint32_t ps_input_cntl;
2724 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2725 ps_input_cntl = S_028644_OFFSET(offset);
2726 if (flat_shade)
2727 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2728 } else {
2729 /* The input is a DEFAULT_VAL constant. */
2730 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2731 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2732 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2733 ps_input_cntl = S_028644_OFFSET(0x20) |
2734 S_028644_DEFAULT_VAL(offset);
2735 }
2736 return ps_input_cntl;
2737 }
2738
2739 static void
2740 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2741 struct radv_pipeline *pipeline)
2742 {
2743 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2744 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
2745 uint32_t ps_input_cntl[32];
2746
2747 unsigned ps_offset = 0;
2748
2749 if (ps->info.fs.prim_id_input) {
2750 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2751 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2752 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2753 ++ps_offset;
2754 }
2755 }
2756
2757 if (ps->info.fs.layer_input) {
2758 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2759 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2760 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2761 else
2762 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2763 ++ps_offset;
2764 }
2765
2766 if (ps->info.fs.has_pcoord) {
2767 unsigned val;
2768 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2769 ps_input_cntl[ps_offset] = val;
2770 ps_offset++;
2771 }
2772
2773 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2774 unsigned vs_offset;
2775 bool flat_shade;
2776 if (!(ps->info.fs.input_mask & (1u << i)))
2777 continue;
2778
2779 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2780 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2781 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2782 ++ps_offset;
2783 continue;
2784 }
2785
2786 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2787
2788 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2789 ++ps_offset;
2790 }
2791
2792 if (ps_offset) {
2793 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2794 for (unsigned i = 0; i < ps_offset; i++) {
2795 radeon_emit(cs, ps_input_cntl[i]);
2796 }
2797 }
2798 }
2799
2800 static void
2801 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2802 struct radv_pipeline *pipeline)
2803 {
2804 struct radv_shader_variant *ps;
2805 uint64_t va;
2806 struct radv_blend_state *blend = &pipeline->graphics.blend;
2807 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2808
2809 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2810 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2811
2812 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2813 radeon_emit(cs, va >> 8);
2814 radeon_emit(cs, va >> 40);
2815 radeon_emit(cs, ps->rsrc1);
2816 radeon_emit(cs, ps->rsrc2);
2817
2818 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2819 pipeline->graphics.db_shader_control);
2820
2821 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2822 ps->config.spi_ps_input_ena);
2823
2824 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2825 ps->config.spi_ps_input_addr);
2826
2827 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2828 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2829
2830 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2831
2832 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2833 pipeline->graphics.shader_z_format);
2834
2835 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2836
2837 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2838 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2839
2840 if (pipeline->device->dfsm_allowed) {
2841 /* optimise this? */
2842 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2843 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2844 }
2845 }
2846
2847 static void
2848 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2849 struct radv_pipeline *pipeline)
2850 {
2851 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2852 return;
2853
2854 unsigned vtx_reuse_depth = 30;
2855 if (radv_pipeline_has_tess(pipeline) &&
2856 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2857 vtx_reuse_depth = 14;
2858 }
2859 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2860 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2861 }
2862
2863 static void
2864 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2865 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2866 const struct radv_graphics_pipeline_create_info *extra)
2867 {
2868 pipeline->cs.buf = malloc(4 * 256);
2869 pipeline->cs.max_dw = 256;
2870
2871 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2872 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline);
2873 radv_pipeline_generate_raster_state(&pipeline->cs, pipeline);
2874 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2875 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline);
2876 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline);
2877 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline);
2878 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2879 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2880 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2881 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2882
2883 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2884 S_0286E8_WAVES(pipeline->max_waves) |
2885 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2886
2887 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
2888
2889 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2890 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
2891 } else {
2892 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
2893 }
2894 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
2895
2896 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, pipeline->graphics.pa_sc_cliprect_rule);
2897
2898 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2899 }
2900
2901 static VkResult
2902 radv_pipeline_init(struct radv_pipeline *pipeline,
2903 struct radv_device *device,
2904 struct radv_pipeline_cache *cache,
2905 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2906 const struct radv_graphics_pipeline_create_info *extra,
2907 const VkAllocationCallbacks *alloc)
2908 {
2909 VkResult result;
2910 bool has_view_index = false;
2911
2912 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2913 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2914 if (subpass->view_mask)
2915 has_view_index = true;
2916 if (alloc == NULL)
2917 alloc = &device->alloc;
2918
2919 pipeline->device = device;
2920 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2921 assert(pipeline->layout);
2922
2923 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2924
2925 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2926 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2927 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2928 pStages[stage] = &pCreateInfo->pStages[i];
2929 }
2930
2931 radv_create_shaders(pipeline, device, cache,
2932 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, has_view_index),
2933 pStages);
2934
2935 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
2936 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2937 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2938 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2939 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2940
2941 if (radv_pipeline_has_gs(pipeline)) {
2942 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2943 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2944 } else {
2945 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2946 }
2947 if (extra && extra->use_rectlist) {
2948 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2949 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2950 pipeline->graphics.can_use_guardband = true;
2951 }
2952 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2953 /* prim vertex count will need TESS changes */
2954 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2955
2956 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2957
2958 /* Ensure that some export memory is always allocated, for two reasons:
2959 *
2960 * 1) Correctness: The hardware ignores the EXEC mask if no export
2961 * memory is allocated, so KILL and alpha test do not work correctly
2962 * without this.
2963 * 2) Performance: Every shader needs at least a NULL export, even when
2964 * it writes no color/depth output. The NULL export instruction
2965 * stalls without this setting.
2966 *
2967 * Don't add this to CB_SHADER_MASK.
2968 */
2969 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2970 if (!pipeline->graphics.blend.spi_shader_col_format) {
2971 if (!ps->info.fs.writes_z &&
2972 !ps->info.fs.writes_stencil &&
2973 !ps->info.fs.writes_sample_mask)
2974 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2975 }
2976
2977 unsigned z_order;
2978 pipeline->graphics.db_shader_control = 0;
2979 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2980 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2981 else
2982 z_order = V_02880C_LATE_Z;
2983
2984 pipeline->graphics.db_shader_control =
2985 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2986 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2987 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2988 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2989 S_02880C_Z_ORDER(z_order) |
2990 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2991 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2992 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory);
2993
2994 if (pipeline->device->physical_device->has_rbplus)
2995 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2996
2997 unsigned shader_z_format =
2998 ac_get_spi_shader_z_format(ps->info.fs.writes_z,
2999 ps->info.fs.writes_stencil,
3000 ps->info.fs.writes_sample_mask);
3001 pipeline->graphics.shader_z_format = shader_z_format;
3002
3003 calculate_vgt_gs_mode(pipeline);
3004
3005 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3006 if (pipeline->shaders[i]) {
3007 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3008 }
3009 }
3010
3011 uint32_t stages = 0;
3012 if (radv_pipeline_has_tess(pipeline)) {
3013 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3014 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3015
3016 if (radv_pipeline_has_gs(pipeline))
3017 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3018 S_028B54_GS_EN(1) |
3019 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3020 else
3021 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3022
3023 } else if (radv_pipeline_has_gs(pipeline))
3024 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3025 S_028B54_GS_EN(1) |
3026 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3027
3028 if (device->physical_device->rad_info.chip_class >= GFX9)
3029 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3030
3031 pipeline->graphics.vgt_shader_stages_en = stages;
3032
3033 if (radv_pipeline_has_gs(pipeline)) {
3034 calculate_gs_ring_sizes(pipeline);
3035 if (device->physical_device->rad_info.chip_class >= GFX9)
3036 calculate_gfx9_gs_info(pCreateInfo, pipeline);
3037 }
3038
3039 if (radv_pipeline_has_tess(pipeline)) {
3040 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
3041 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3042 pipeline->graphics.prim_vertex_count.incr = 1;
3043 }
3044 calculate_tess_state(pipeline, pCreateInfo);
3045 }
3046
3047 if (radv_pipeline_has_tess(pipeline))
3048 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
3049 else if (radv_pipeline_has_gs(pipeline))
3050 pipeline->graphics.primgroup_size = 64;
3051 else
3052 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
3053
3054 pipeline->graphics.partial_es_wave = false;
3055 if (pipeline->device->has_distributed_tess) {
3056 if (radv_pipeline_has_gs(pipeline)) {
3057 if (device->physical_device->rad_info.chip_class <= VI)
3058 pipeline->graphics.partial_es_wave = true;
3059 }
3060 }
3061 /* GS requirement. */
3062 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
3063 pipeline->graphics.partial_es_wave = true;
3064
3065 pipeline->graphics.wd_switch_on_eop = false;
3066 if (device->physical_device->rad_info.chip_class >= CIK) {
3067 unsigned prim = pipeline->graphics.prim;
3068 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3069 * 4 shader engines. Set 1 to pass the assertion below.
3070 * The other cases are hardware requirements. */
3071 if (device->physical_device->rad_info.max_se < 4 ||
3072 prim == V_008958_DI_PT_POLYGON ||
3073 prim == V_008958_DI_PT_LINELOOP ||
3074 prim == V_008958_DI_PT_TRIFAN ||
3075 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3076 (pipeline->graphics.prim_restart_enable &&
3077 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3078 (prim != V_008958_DI_PT_POINTLIST &&
3079 prim != V_008958_DI_PT_LINESTRIP &&
3080 prim != V_008958_DI_PT_TRISTRIP))))
3081 pipeline->graphics.wd_switch_on_eop = true;
3082 }
3083
3084 pipeline->graphics.ia_switch_on_eoi = false;
3085 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
3086 pipeline->graphics.ia_switch_on_eoi = true;
3087 if (radv_pipeline_has_gs(pipeline) &&
3088 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3089 pipeline->graphics.ia_switch_on_eoi = true;
3090 if (radv_pipeline_has_tess(pipeline)) {
3091 /* SWITCH_ON_EOI must be set if PrimID is used. */
3092 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3093 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3094 pipeline->graphics.ia_switch_on_eoi = true;
3095 }
3096
3097 pipeline->graphics.partial_vs_wave = false;
3098 if (radv_pipeline_has_tess(pipeline)) {
3099 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3100 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3101 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3102 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3103 radv_pipeline_has_gs(pipeline))
3104 pipeline->graphics.partial_vs_wave = true;
3105 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3106 if (device->has_distributed_tess) {
3107 if (radv_pipeline_has_gs(pipeline)) {
3108 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3109 device->physical_device->rad_info.family == CHIP_FIJI ||
3110 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3111 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3112 device->physical_device->rad_info.family == CHIP_POLARIS12)
3113 pipeline->graphics.partial_vs_wave = true;
3114 } else {
3115 pipeline->graphics.partial_vs_wave = true;
3116 }
3117 }
3118 }
3119
3120 pipeline->graphics.base_ia_multi_vgt_param =
3121 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
3122 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3123 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3124 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3125 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3126
3127 const VkPipelineVertexInputStateCreateInfo *vi_info =
3128 pCreateInfo->pVertexInputState;
3129 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3130
3131 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3132 const VkVertexInputAttributeDescription *desc =
3133 &vi_info->pVertexAttributeDescriptions[i];
3134 unsigned loc = desc->location;
3135 const struct vk_format_description *format_desc;
3136 int first_non_void;
3137 uint32_t num_format, data_format;
3138 format_desc = vk_format_description(desc->format);
3139 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3140
3141 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3142 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3143
3144 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3145 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3146 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3147 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3148 S_008F0C_NUM_FORMAT(num_format) |
3149 S_008F0C_DATA_FORMAT(data_format);
3150 velems->format_size[loc] = format_desc->block.bits / 8;
3151 velems->offset[loc] = desc->offset;
3152 velems->binding[loc] = desc->binding;
3153 velems->count = MAX2(velems->count, loc + 1);
3154 }
3155
3156 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3157 const VkVertexInputBindingDescription *desc =
3158 &vi_info->pVertexBindingDescriptions[i];
3159
3160 pipeline->binding_stride[desc->binding] = desc->stride;
3161 }
3162
3163 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3164 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3165
3166 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3167 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3168 if (loc->sgpr_idx != -1) {
3169 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3170 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3171 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3172 pipeline->graphics.vtx_emit_num = 3;
3173 else
3174 pipeline->graphics.vtx_emit_num = 2;
3175 }
3176
3177 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
3178 radv_dump_pipeline_stats(device, pipeline);
3179 }
3180
3181 result = radv_pipeline_scratch_init(device, pipeline);
3182 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra);
3183
3184 return result;
3185 }
3186
3187 VkResult
3188 radv_graphics_pipeline_create(
3189 VkDevice _device,
3190 VkPipelineCache _cache,
3191 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3192 const struct radv_graphics_pipeline_create_info *extra,
3193 const VkAllocationCallbacks *pAllocator,
3194 VkPipeline *pPipeline)
3195 {
3196 RADV_FROM_HANDLE(radv_device, device, _device);
3197 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3198 struct radv_pipeline *pipeline;
3199 VkResult result;
3200
3201 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3203 if (pipeline == NULL)
3204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3205
3206 result = radv_pipeline_init(pipeline, device, cache,
3207 pCreateInfo, extra, pAllocator);
3208 if (result != VK_SUCCESS) {
3209 radv_pipeline_destroy(device, pipeline, pAllocator);
3210 return result;
3211 }
3212
3213 *pPipeline = radv_pipeline_to_handle(pipeline);
3214
3215 return VK_SUCCESS;
3216 }
3217
3218 VkResult radv_CreateGraphicsPipelines(
3219 VkDevice _device,
3220 VkPipelineCache pipelineCache,
3221 uint32_t count,
3222 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3223 const VkAllocationCallbacks* pAllocator,
3224 VkPipeline* pPipelines)
3225 {
3226 VkResult result = VK_SUCCESS;
3227 unsigned i = 0;
3228
3229 for (; i < count; i++) {
3230 VkResult r;
3231 r = radv_graphics_pipeline_create(_device,
3232 pipelineCache,
3233 &pCreateInfos[i],
3234 NULL, pAllocator, &pPipelines[i]);
3235 if (r != VK_SUCCESS) {
3236 result = r;
3237 pPipelines[i] = VK_NULL_HANDLE;
3238 }
3239 }
3240
3241 return result;
3242 }
3243
3244
3245 static void
3246 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3247 {
3248 struct radv_shader_variant *compute_shader;
3249 struct radv_device *device = pipeline->device;
3250 unsigned compute_resource_limits;
3251 unsigned waves_per_threadgroup;
3252 uint64_t va;
3253
3254 pipeline->cs.buf = malloc(20 * 4);
3255 pipeline->cs.max_dw = 20;
3256
3257 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3258 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3259
3260 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3261 radeon_emit(&pipeline->cs, va >> 8);
3262 radeon_emit(&pipeline->cs, va >> 40);
3263
3264 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3265 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3266 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3267
3268 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3269 S_00B860_WAVES(pipeline->max_waves) |
3270 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3271
3272 /* Calculate best compute resource limits. */
3273 waves_per_threadgroup =
3274 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3275 compute_shader->info.cs.block_size[1] *
3276 compute_shader->info.cs.block_size[2], 64);
3277 compute_resource_limits =
3278 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3279
3280 if (device->physical_device->rad_info.chip_class >= CIK) {
3281 unsigned num_cu_per_se =
3282 device->physical_device->rad_info.num_good_compute_units /
3283 device->physical_device->rad_info.max_se;
3284
3285 /* Force even distribution on all SIMDs in CU if the workgroup
3286 * size is 64. This has shown some good improvements if # of
3287 * CUs per SE is not a multiple of 4.
3288 */
3289 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3290 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3291 }
3292
3293 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3294 compute_resource_limits);
3295
3296 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3297 radeon_emit(&pipeline->cs,
3298 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3299 radeon_emit(&pipeline->cs,
3300 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3301 radeon_emit(&pipeline->cs,
3302 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3303
3304 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3305 }
3306
3307 static VkResult radv_compute_pipeline_create(
3308 VkDevice _device,
3309 VkPipelineCache _cache,
3310 const VkComputePipelineCreateInfo* pCreateInfo,
3311 const VkAllocationCallbacks* pAllocator,
3312 VkPipeline* pPipeline)
3313 {
3314 RADV_FROM_HANDLE(radv_device, device, _device);
3315 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3316 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3317 struct radv_pipeline *pipeline;
3318 VkResult result;
3319
3320 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3321 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3322 if (pipeline == NULL)
3323 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3324
3325 pipeline->device = device;
3326 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3327 assert(pipeline->layout);
3328
3329 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3330 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3331
3332 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3333 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3334 result = radv_pipeline_scratch_init(device, pipeline);
3335 if (result != VK_SUCCESS) {
3336 radv_pipeline_destroy(device, pipeline, pAllocator);
3337 return result;
3338 }
3339
3340 radv_compute_generate_pm4(pipeline);
3341
3342 *pPipeline = radv_pipeline_to_handle(pipeline);
3343
3344 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
3345 radv_dump_pipeline_stats(device, pipeline);
3346 }
3347 return VK_SUCCESS;
3348 }
3349
3350 VkResult radv_CreateComputePipelines(
3351 VkDevice _device,
3352 VkPipelineCache pipelineCache,
3353 uint32_t count,
3354 const VkComputePipelineCreateInfo* pCreateInfos,
3355 const VkAllocationCallbacks* pAllocator,
3356 VkPipeline* pPipelines)
3357 {
3358 VkResult result = VK_SUCCESS;
3359
3360 unsigned i = 0;
3361 for (; i < count; i++) {
3362 VkResult r;
3363 r = radv_compute_pipeline_create(_device, pipelineCache,
3364 &pCreateInfos[i],
3365 pAllocator, &pPipelines[i]);
3366 if (r != VK_SUCCESS) {
3367 result = r;
3368 pPipelines[i] = VK_NULL_HANDLE;
3369 }
3370 }
3371
3372 return result;
3373 }