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radv: do not always disable dual quad mode when chip has RbPlus
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t cb_color_control;
54 uint32_t cb_target_mask;
55 uint32_t sx_mrt_blend_opt[8];
56 uint32_t cb_blend_control[8];
57
58 uint32_t spi_shader_col_format;
59 uint32_t cb_shader_mask;
60 uint32_t db_alpha_to_mask;
61 };
62
63 struct radv_tessellation_state {
64 uint32_t ls_hs_config;
65 unsigned num_patches;
66 unsigned lds_size;
67 uint32_t tf_param;
68 };
69
70 struct radv_gs_state {
71 uint32_t vgt_gs_onchip_cntl;
72 uint32_t vgt_gs_max_prims_per_subgroup;
73 uint32_t vgt_esgs_ring_itemsize;
74 uint32_t lds_size;
75 };
76
77 static void
78 radv_pipeline_destroy(struct radv_device *device,
79 struct radv_pipeline *pipeline,
80 const VkAllocationCallbacks* allocator)
81 {
82 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
83 if (pipeline->shaders[i])
84 radv_shader_variant_destroy(device, pipeline->shaders[i]);
85
86 if (pipeline->gs_copy_shader)
87 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
88
89 if(pipeline->cs.buf)
90 free(pipeline->cs.buf);
91 vk_free2(&device->alloc, allocator, pipeline);
92 }
93
94 void radv_DestroyPipeline(
95 VkDevice _device,
96 VkPipeline _pipeline,
97 const VkAllocationCallbacks* pAllocator)
98 {
99 RADV_FROM_HANDLE(radv_device, device, _device);
100 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
101
102 if (!_pipeline)
103 return;
104
105 radv_pipeline_destroy(device, pipeline, pAllocator);
106 }
107
108 static uint32_t get_hash_flags(struct radv_device *device)
109 {
110 uint32_t hash_flags = 0;
111
112 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
113 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
114 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
115 hash_flags |= RADV_HASH_SHADER_SISCHED;
116 return hash_flags;
117 }
118
119 static VkResult
120 radv_pipeline_scratch_init(struct radv_device *device,
121 struct radv_pipeline *pipeline)
122 {
123 unsigned scratch_bytes_per_wave = 0;
124 unsigned max_waves = 0;
125 unsigned min_waves = 1;
126
127 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
128 if (pipeline->shaders[i]) {
129 unsigned max_stage_waves = device->scratch_waves;
130
131 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
132 pipeline->shaders[i]->config.scratch_bytes_per_wave);
133
134 max_stage_waves = MIN2(max_stage_waves,
135 4 * device->physical_device->rad_info.num_good_compute_units *
136 (256 / pipeline->shaders[i]->config.num_vgprs));
137 max_waves = MAX2(max_waves, max_stage_waves);
138 }
139 }
140
141 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
142 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
143 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
144 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
145 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
146 }
147
148 if (scratch_bytes_per_wave)
149 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
150
151 if (scratch_bytes_per_wave && max_waves < min_waves) {
152 /* Not really true at this moment, but will be true on first
153 * execution. Avoid having hanging shaders. */
154 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
155 }
156 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
157 pipeline->max_waves = max_waves;
158 return VK_SUCCESS;
159 }
160
161 static uint32_t si_translate_blend_function(VkBlendOp op)
162 {
163 switch (op) {
164 case VK_BLEND_OP_ADD:
165 return V_028780_COMB_DST_PLUS_SRC;
166 case VK_BLEND_OP_SUBTRACT:
167 return V_028780_COMB_SRC_MINUS_DST;
168 case VK_BLEND_OP_REVERSE_SUBTRACT:
169 return V_028780_COMB_DST_MINUS_SRC;
170 case VK_BLEND_OP_MIN:
171 return V_028780_COMB_MIN_DST_SRC;
172 case VK_BLEND_OP_MAX:
173 return V_028780_COMB_MAX_DST_SRC;
174 default:
175 return 0;
176 }
177 }
178
179 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
180 {
181 switch (factor) {
182 case VK_BLEND_FACTOR_ZERO:
183 return V_028780_BLEND_ZERO;
184 case VK_BLEND_FACTOR_ONE:
185 return V_028780_BLEND_ONE;
186 case VK_BLEND_FACTOR_SRC_COLOR:
187 return V_028780_BLEND_SRC_COLOR;
188 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
189 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
190 case VK_BLEND_FACTOR_DST_COLOR:
191 return V_028780_BLEND_DST_COLOR;
192 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
193 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
194 case VK_BLEND_FACTOR_SRC_ALPHA:
195 return V_028780_BLEND_SRC_ALPHA;
196 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
197 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
198 case VK_BLEND_FACTOR_DST_ALPHA:
199 return V_028780_BLEND_DST_ALPHA;
200 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
201 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
202 case VK_BLEND_FACTOR_CONSTANT_COLOR:
203 return V_028780_BLEND_CONSTANT_COLOR;
204 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
205 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
206 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
207 return V_028780_BLEND_CONSTANT_ALPHA;
208 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
209 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
210 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
211 return V_028780_BLEND_SRC_ALPHA_SATURATE;
212 case VK_BLEND_FACTOR_SRC1_COLOR:
213 return V_028780_BLEND_SRC1_COLOR;
214 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
215 return V_028780_BLEND_INV_SRC1_COLOR;
216 case VK_BLEND_FACTOR_SRC1_ALPHA:
217 return V_028780_BLEND_SRC1_ALPHA;
218 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
219 return V_028780_BLEND_INV_SRC1_ALPHA;
220 default:
221 return 0;
222 }
223 }
224
225 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
226 {
227 switch (op) {
228 case VK_BLEND_OP_ADD:
229 return V_028760_OPT_COMB_ADD;
230 case VK_BLEND_OP_SUBTRACT:
231 return V_028760_OPT_COMB_SUBTRACT;
232 case VK_BLEND_OP_REVERSE_SUBTRACT:
233 return V_028760_OPT_COMB_REVSUBTRACT;
234 case VK_BLEND_OP_MIN:
235 return V_028760_OPT_COMB_MIN;
236 case VK_BLEND_OP_MAX:
237 return V_028760_OPT_COMB_MAX;
238 default:
239 return V_028760_OPT_COMB_BLEND_DISABLED;
240 }
241 }
242
243 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
244 {
245 switch (factor) {
246 case VK_BLEND_FACTOR_ZERO:
247 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
248 case VK_BLEND_FACTOR_ONE:
249 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
250 case VK_BLEND_FACTOR_SRC_COLOR:
251 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
252 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
253 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
254 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
255 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
256 case VK_BLEND_FACTOR_SRC_ALPHA:
257 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
258 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
259 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
260 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
261 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
262 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
263 default:
264 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
265 }
266 }
267
268 /**
269 * Get rid of DST in the blend factors by commuting the operands:
270 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
271 */
272 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
273 unsigned *dst_factor, unsigned expected_dst,
274 unsigned replacement_src)
275 {
276 if (*src_factor == expected_dst &&
277 *dst_factor == VK_BLEND_FACTOR_ZERO) {
278 *src_factor = VK_BLEND_FACTOR_ZERO;
279 *dst_factor = replacement_src;
280
281 /* Commuting the operands requires reversing subtractions. */
282 if (*func == VK_BLEND_OP_SUBTRACT)
283 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
284 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
285 *func = VK_BLEND_OP_SUBTRACT;
286 }
287 }
288
289 static bool si_blend_factor_uses_dst(unsigned factor)
290 {
291 return factor == VK_BLEND_FACTOR_DST_COLOR ||
292 factor == VK_BLEND_FACTOR_DST_ALPHA ||
293 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
294 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
295 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
296 }
297
298 static bool is_dual_src(VkBlendFactor factor)
299 {
300 switch (factor) {
301 case VK_BLEND_FACTOR_SRC1_COLOR:
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
303 case VK_BLEND_FACTOR_SRC1_ALPHA:
304 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
305 return true;
306 default:
307 return false;
308 }
309 }
310
311 static unsigned si_choose_spi_color_format(VkFormat vk_format,
312 bool blend_enable,
313 bool blend_need_alpha)
314 {
315 const struct vk_format_description *desc = vk_format_description(vk_format);
316 unsigned format, ntype, swap;
317
318 /* Alpha is needed for alpha-to-coverage.
319 * Blending may be with or without alpha.
320 */
321 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
322 unsigned alpha = 0; /* exports alpha, but may not support blending */
323 unsigned blend = 0; /* supports blending, but may not export alpha */
324 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
325
326 format = radv_translate_colorformat(vk_format);
327 ntype = radv_translate_color_numformat(vk_format, desc,
328 vk_format_get_first_non_void_channel(vk_format));
329 swap = radv_translate_colorswap(vk_format, false);
330
331 /* Choose the SPI color formats. These are required values for Stoney/RB+.
332 * Other chips have multiple choices, though they are not necessarily better.
333 */
334 switch (format) {
335 case V_028C70_COLOR_5_6_5:
336 case V_028C70_COLOR_1_5_5_5:
337 case V_028C70_COLOR_5_5_5_1:
338 case V_028C70_COLOR_4_4_4_4:
339 case V_028C70_COLOR_10_11_11:
340 case V_028C70_COLOR_11_11_10:
341 case V_028C70_COLOR_8:
342 case V_028C70_COLOR_8_8:
343 case V_028C70_COLOR_8_8_8_8:
344 case V_028C70_COLOR_10_10_10_2:
345 case V_028C70_COLOR_2_10_10_10:
346 if (ntype == V_028C70_NUMBER_UINT)
347 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
348 else if (ntype == V_028C70_NUMBER_SINT)
349 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
350 else
351 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
352 break;
353
354 case V_028C70_COLOR_16:
355 case V_028C70_COLOR_16_16:
356 case V_028C70_COLOR_16_16_16_16:
357 if (ntype == V_028C70_NUMBER_UNORM ||
358 ntype == V_028C70_NUMBER_SNORM) {
359 /* UNORM16 and SNORM16 don't support blending */
360 if (ntype == V_028C70_NUMBER_UNORM)
361 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
362 else
363 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
364
365 /* Use 32 bits per channel for blending. */
366 if (format == V_028C70_COLOR_16) {
367 if (swap == V_028C70_SWAP_STD) { /* R */
368 blend = V_028714_SPI_SHADER_32_R;
369 blend_alpha = V_028714_SPI_SHADER_32_AR;
370 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
371 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
372 else
373 assert(0);
374 } else if (format == V_028C70_COLOR_16_16) {
375 if (swap == V_028C70_SWAP_STD) { /* RG */
376 blend = V_028714_SPI_SHADER_32_GR;
377 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
378 } else if (swap == V_028C70_SWAP_ALT) /* RA */
379 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
380 else
381 assert(0);
382 } else /* 16_16_16_16 */
383 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
384 } else if (ntype == V_028C70_NUMBER_UINT)
385 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
386 else if (ntype == V_028C70_NUMBER_SINT)
387 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
388 else if (ntype == V_028C70_NUMBER_FLOAT)
389 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
390 else
391 assert(0);
392 break;
393
394 case V_028C70_COLOR_32:
395 if (swap == V_028C70_SWAP_STD) { /* R */
396 blend = normal = V_028714_SPI_SHADER_32_R;
397 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
398 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
399 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
400 else
401 assert(0);
402 break;
403
404 case V_028C70_COLOR_32_32:
405 if (swap == V_028C70_SWAP_STD) { /* RG */
406 blend = normal = V_028714_SPI_SHADER_32_GR;
407 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
408 } else if (swap == V_028C70_SWAP_ALT) /* RA */
409 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
410 else
411 assert(0);
412 break;
413
414 case V_028C70_COLOR_32_32_32_32:
415 case V_028C70_COLOR_8_24:
416 case V_028C70_COLOR_24_8:
417 case V_028C70_COLOR_X24_8_32_FLOAT:
418 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
419 break;
420
421 default:
422 unreachable("unhandled blend format");
423 }
424
425 if (blend_enable && blend_need_alpha)
426 return blend_alpha;
427 else if(blend_need_alpha)
428 return alpha;
429 else if(blend_enable)
430 return blend;
431 else
432 return normal;
433 }
434
435 static void
436 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
437 const VkGraphicsPipelineCreateInfo *pCreateInfo,
438 uint32_t blend_enable,
439 uint32_t blend_need_alpha,
440 bool single_cb_enable,
441 bool blend_mrt0_is_dual_src,
442 struct radv_blend_state *blend)
443 {
444 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
445 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
446 unsigned col_format = 0;
447
448 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
449 unsigned cf;
450
451 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
452 cf = V_028714_SPI_SHADER_ZERO;
453 } else {
454 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
455
456 cf = si_choose_spi_color_format(attachment->format,
457 blend_enable & (1 << i),
458 blend_need_alpha & (1 << i));
459 }
460
461 col_format |= cf << (4 * i);
462 }
463
464 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
465
466 if (blend_mrt0_is_dual_src)
467 col_format |= (col_format & 0xf) << 4;
468 blend->spi_shader_col_format = col_format;
469 }
470
471 static bool
472 format_is_int8(VkFormat format)
473 {
474 const struct vk_format_description *desc = vk_format_description(format);
475 int channel = vk_format_get_first_non_void_channel(format);
476
477 return channel >= 0 && desc->channel[channel].pure_integer &&
478 desc->channel[channel].size == 8;
479 }
480
481 static bool
482 format_is_int10(VkFormat format)
483 {
484 const struct vk_format_description *desc = vk_format_description(format);
485
486 if (desc->nr_channels != 4)
487 return false;
488 for (unsigned i = 0; i < 4; i++) {
489 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
490 return true;
491 }
492 return false;
493 }
494
495 unsigned radv_format_meta_fs_key(VkFormat format)
496 {
497 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
498 bool is_int8 = format_is_int8(format);
499 bool is_int10 = format_is_int10(format);
500
501 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
502 }
503
504 static void
505 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
506 unsigned *is_int8, unsigned *is_int10)
507 {
508 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
509 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
510 *is_int8 = 0;
511 *is_int10 = 0;
512
513 for (unsigned i = 0; i < subpass->color_count; ++i) {
514 struct radv_render_pass_attachment *attachment;
515
516 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
517 continue;
518
519 attachment = pass->attachments + subpass->color_attachments[i].attachment;
520
521 if (format_is_int8(attachment->format))
522 *is_int8 |= 1 << i;
523 if (format_is_int10(attachment->format))
524 *is_int10 |= 1 << i;
525 }
526 }
527
528 static struct radv_blend_state
529 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
530 const VkGraphicsPipelineCreateInfo *pCreateInfo,
531 const struct radv_graphics_pipeline_create_info *extra)
532 {
533 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
534 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
535 struct radv_blend_state blend = {0};
536 unsigned mode = V_028808_CB_NORMAL;
537 uint32_t blend_enable = 0, blend_need_alpha = 0;
538 bool blend_mrt0_is_dual_src = false;
539 int i;
540 bool single_cb_enable = false;
541
542 if (!vkblend)
543 return blend;
544
545 if (extra && extra->custom_blend_mode) {
546 single_cb_enable = true;
547 mode = extra->custom_blend_mode;
548 }
549 blend.cb_color_control = 0;
550 if (vkblend->logicOpEnable)
551 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
552 else
553 blend.cb_color_control |= S_028808_ROP3(0xcc);
554
555 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
556 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
557 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
558 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
559
560 if (vkms && vkms->alphaToCoverageEnable) {
561 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
562 }
563
564 blend.cb_target_mask = 0;
565 for (i = 0; i < vkblend->attachmentCount; i++) {
566 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
567 unsigned blend_cntl = 0;
568 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
569 VkBlendOp eqRGB = att->colorBlendOp;
570 VkBlendFactor srcRGB = att->srcColorBlendFactor;
571 VkBlendFactor dstRGB = att->dstColorBlendFactor;
572 VkBlendOp eqA = att->alphaBlendOp;
573 VkBlendFactor srcA = att->srcAlphaBlendFactor;
574 VkBlendFactor dstA = att->dstAlphaBlendFactor;
575
576 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
577
578 if (!att->colorWriteMask)
579 continue;
580
581 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
582 if (!att->blendEnable) {
583 blend.cb_blend_control[i] = blend_cntl;
584 continue;
585 }
586
587 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
588 if (i == 0)
589 blend_mrt0_is_dual_src = true;
590
591 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
592 srcRGB = VK_BLEND_FACTOR_ONE;
593 dstRGB = VK_BLEND_FACTOR_ONE;
594 }
595 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
596 srcA = VK_BLEND_FACTOR_ONE;
597 dstA = VK_BLEND_FACTOR_ONE;
598 }
599
600 /* Blending optimizations for RB+.
601 * These transformations don't change the behavior.
602 *
603 * First, get rid of DST in the blend factors:
604 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
605 */
606 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
607 VK_BLEND_FACTOR_DST_COLOR,
608 VK_BLEND_FACTOR_SRC_COLOR);
609
610 si_blend_remove_dst(&eqA, &srcA, &dstA,
611 VK_BLEND_FACTOR_DST_COLOR,
612 VK_BLEND_FACTOR_SRC_COLOR);
613
614 si_blend_remove_dst(&eqA, &srcA, &dstA,
615 VK_BLEND_FACTOR_DST_ALPHA,
616 VK_BLEND_FACTOR_SRC_ALPHA);
617
618 /* Look up the ideal settings from tables. */
619 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
620 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
621 srcA_opt = si_translate_blend_opt_factor(srcA, true);
622 dstA_opt = si_translate_blend_opt_factor(dstA, true);
623
624 /* Handle interdependencies. */
625 if (si_blend_factor_uses_dst(srcRGB))
626 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
627 if (si_blend_factor_uses_dst(srcA))
628 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
629
630 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
631 (dstRGB == VK_BLEND_FACTOR_ZERO ||
632 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
633 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
634 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
635
636 /* Set the final value. */
637 blend.sx_mrt_blend_opt[i] =
638 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
639 S_028760_COLOR_DST_OPT(dstRGB_opt) |
640 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
641 S_028760_ALPHA_SRC_OPT(srcA_opt) |
642 S_028760_ALPHA_DST_OPT(dstA_opt) |
643 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
644 blend_cntl |= S_028780_ENABLE(1);
645
646 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
647 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
648 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
649 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
650 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
651 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
652 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
653 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
654 }
655 blend.cb_blend_control[i] = blend_cntl;
656
657 blend_enable |= 1 << i;
658
659 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
660 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
661 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
662 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
663 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
664 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
665 blend_need_alpha |= 1 << i;
666 }
667 for (i = vkblend->attachmentCount; i < 8; i++) {
668 blend.cb_blend_control[i] = 0;
669 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
670 }
671
672 if (pipeline->device->physical_device->has_rbplus) {
673 /* Disable RB+ blend optimizations for dual source blending. */
674 if (blend_mrt0_is_dual_src) {
675 for (i = 0; i < 8; i++) {
676 blend.sx_mrt_blend_opt[i] =
677 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
678 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
679 }
680 }
681
682 /* RB+ doesn't work with dual source blending, logic op and
683 * RESOLVE.
684 */
685 if (blend_mrt0_is_dual_src || vkblend->logicOpEnable ||
686 mode == V_028808_CB_RESOLVE)
687 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
688 }
689
690 if (blend.cb_target_mask)
691 blend.cb_color_control |= S_028808_MODE(mode);
692 else
693 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
694
695 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
696 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src,
697 &blend);
698 return blend;
699 }
700
701 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
702 {
703 switch (op) {
704 case VK_STENCIL_OP_KEEP:
705 return V_02842C_STENCIL_KEEP;
706 case VK_STENCIL_OP_ZERO:
707 return V_02842C_STENCIL_ZERO;
708 case VK_STENCIL_OP_REPLACE:
709 return V_02842C_STENCIL_REPLACE_TEST;
710 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
711 return V_02842C_STENCIL_ADD_CLAMP;
712 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
713 return V_02842C_STENCIL_SUB_CLAMP;
714 case VK_STENCIL_OP_INVERT:
715 return V_02842C_STENCIL_INVERT;
716 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
717 return V_02842C_STENCIL_ADD_WRAP;
718 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
719 return V_02842C_STENCIL_SUB_WRAP;
720 default:
721 return 0;
722 }
723 }
724
725 static uint32_t si_translate_fill(VkPolygonMode func)
726 {
727 switch(func) {
728 case VK_POLYGON_MODE_FILL:
729 return V_028814_X_DRAW_TRIANGLES;
730 case VK_POLYGON_MODE_LINE:
731 return V_028814_X_DRAW_LINES;
732 case VK_POLYGON_MODE_POINT:
733 return V_028814_X_DRAW_POINTS;
734 default:
735 assert(0);
736 return V_028814_X_DRAW_POINTS;
737 }
738 }
739
740 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
741 {
742 uint32_t num_samples = vkms->rasterizationSamples;
743 uint32_t ps_iter_samples = 1;
744
745 if (vkms->sampleShadingEnable) {
746 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
747 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
748 }
749 return ps_iter_samples;
750 }
751
752 static void
753 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
754 const VkGraphicsPipelineCreateInfo *pCreateInfo)
755 {
756 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
757 struct radv_multisample_state *ms = &pipeline->graphics.ms;
758 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
759 int ps_iter_samples = 1;
760 uint32_t mask = 0xffff;
761
762 if (vkms)
763 ms->num_samples = vkms->rasterizationSamples;
764 else
765 ms->num_samples = 1;
766
767 if (vkms)
768 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
769 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
770 ps_iter_samples = ms->num_samples;
771 }
772
773 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
774 ms->pa_sc_aa_config = 0;
775 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
776 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
777 ms->pa_sc_mode_cntl_1 =
778 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
779 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
780 /* always 1: */
781 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
782 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
783 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
784 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
785 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
786 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
787 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
788 S_028A48_VPORT_SCISSOR_ENABLE(1);
789
790 if (ms->num_samples > 1) {
791 unsigned log_samples = util_logbase2(ms->num_samples);
792 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
793 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
794 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
795 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
796 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
797 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
798 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
799 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
800 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
801 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
802 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
803 if (ps_iter_samples > 1)
804 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
805 }
806
807 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
808 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
809 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
810 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
811 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
812 }
813
814 if (vkms && vkms->pSampleMask) {
815 mask = vkms->pSampleMask[0] & 0xffff;
816 }
817
818 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
819 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
820 }
821
822 static bool
823 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
824 {
825 switch (topology) {
826 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
827 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
828 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
829 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
830 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
831 return false;
832 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
833 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
834 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
835 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
836 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
837 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
838 return true;
839 default:
840 unreachable("unhandled primitive type");
841 }
842 }
843
844 static uint32_t
845 si_translate_prim(enum VkPrimitiveTopology topology)
846 {
847 switch (topology) {
848 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
849 return V_008958_DI_PT_POINTLIST;
850 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
851 return V_008958_DI_PT_LINELIST;
852 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
853 return V_008958_DI_PT_LINESTRIP;
854 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
855 return V_008958_DI_PT_TRILIST;
856 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
857 return V_008958_DI_PT_TRISTRIP;
858 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
859 return V_008958_DI_PT_TRIFAN;
860 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
861 return V_008958_DI_PT_LINELIST_ADJ;
862 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
863 return V_008958_DI_PT_LINESTRIP_ADJ;
864 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
865 return V_008958_DI_PT_TRILIST_ADJ;
866 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
867 return V_008958_DI_PT_TRISTRIP_ADJ;
868 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
869 return V_008958_DI_PT_PATCH;
870 default:
871 assert(0);
872 return 0;
873 }
874 }
875
876 static uint32_t
877 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
878 {
879 switch (gl_prim) {
880 case 0: /* GL_POINTS */
881 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
882 case 1: /* GL_LINES */
883 case 3: /* GL_LINE_STRIP */
884 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
885 case 0x8E7A: /* GL_ISOLINES */
886 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
887
888 case 4: /* GL_TRIANGLES */
889 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
890 case 5: /* GL_TRIANGLE_STRIP */
891 case 7: /* GL_QUADS */
892 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
893 default:
894 assert(0);
895 return 0;
896 }
897 }
898
899 static uint32_t
900 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
901 {
902 switch (topology) {
903 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
904 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
905 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
906 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
907 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
908 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
909 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
910 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
911 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
912 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
913 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
914 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
915 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
916 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
917 default:
918 assert(0);
919 return 0;
920 }
921 }
922
923 static unsigned si_map_swizzle(unsigned swizzle)
924 {
925 switch (swizzle) {
926 case VK_SWIZZLE_Y:
927 return V_008F0C_SQ_SEL_Y;
928 case VK_SWIZZLE_Z:
929 return V_008F0C_SQ_SEL_Z;
930 case VK_SWIZZLE_W:
931 return V_008F0C_SQ_SEL_W;
932 case VK_SWIZZLE_0:
933 return V_008F0C_SQ_SEL_0;
934 case VK_SWIZZLE_1:
935 return V_008F0C_SQ_SEL_1;
936 default: /* VK_SWIZZLE_X */
937 return V_008F0C_SQ_SEL_X;
938 }
939 }
940
941
942 static unsigned radv_dynamic_state_mask(VkDynamicState state)
943 {
944 switch(state) {
945 case VK_DYNAMIC_STATE_VIEWPORT:
946 return RADV_DYNAMIC_VIEWPORT;
947 case VK_DYNAMIC_STATE_SCISSOR:
948 return RADV_DYNAMIC_SCISSOR;
949 case VK_DYNAMIC_STATE_LINE_WIDTH:
950 return RADV_DYNAMIC_LINE_WIDTH;
951 case VK_DYNAMIC_STATE_DEPTH_BIAS:
952 return RADV_DYNAMIC_DEPTH_BIAS;
953 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
954 return RADV_DYNAMIC_BLEND_CONSTANTS;
955 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
956 return RADV_DYNAMIC_DEPTH_BOUNDS;
957 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
958 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
959 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
960 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
961 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
962 return RADV_DYNAMIC_STENCIL_REFERENCE;
963 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
964 return RADV_DYNAMIC_DISCARD_RECTANGLE;
965 default:
966 unreachable("Unhandled dynamic state");
967 }
968 }
969
970 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
971 {
972 uint32_t states = RADV_DYNAMIC_ALL;
973
974 /* If rasterization is disabled we do not care about any of the dynamic states,
975 * since they are all rasterization related only. */
976 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
977 return 0;
978
979 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
980 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
981
982 if (!pCreateInfo->pDepthStencilState ||
983 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
984 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
985
986 if (!pCreateInfo->pDepthStencilState ||
987 !pCreateInfo->pDepthStencilState->stencilTestEnable)
988 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
989 RADV_DYNAMIC_STENCIL_WRITE_MASK |
990 RADV_DYNAMIC_STENCIL_REFERENCE);
991
992 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
993 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
994
995 /* TODO: blend constants & line width. */
996
997 return states;
998 }
999
1000
1001 static void
1002 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1003 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1004 {
1005 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1006 uint32_t states = needed_states;
1007 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1008 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1009
1010 pipeline->dynamic_state = default_dynamic_state;
1011 pipeline->graphics.needed_dynamic_state = needed_states;
1012
1013 if (pCreateInfo->pDynamicState) {
1014 /* Remove all of the states that are marked as dynamic */
1015 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1016 for (uint32_t s = 0; s < count; s++)
1017 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1018 }
1019
1020 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1021
1022 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1023 assert(pCreateInfo->pViewportState);
1024
1025 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1026 if (states & RADV_DYNAMIC_VIEWPORT) {
1027 typed_memcpy(dynamic->viewport.viewports,
1028 pCreateInfo->pViewportState->pViewports,
1029 pCreateInfo->pViewportState->viewportCount);
1030 }
1031 }
1032
1033 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1034 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1035 if (states & RADV_DYNAMIC_SCISSOR) {
1036 typed_memcpy(dynamic->scissor.scissors,
1037 pCreateInfo->pViewportState->pScissors,
1038 pCreateInfo->pViewportState->scissorCount);
1039 }
1040 }
1041
1042 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1043 assert(pCreateInfo->pRasterizationState);
1044 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1045 }
1046
1047 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1048 assert(pCreateInfo->pRasterizationState);
1049 dynamic->depth_bias.bias =
1050 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1051 dynamic->depth_bias.clamp =
1052 pCreateInfo->pRasterizationState->depthBiasClamp;
1053 dynamic->depth_bias.slope =
1054 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1055 }
1056
1057 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1058 *
1059 * pColorBlendState is [...] NULL if the pipeline has rasterization
1060 * disabled or if the subpass of the render pass the pipeline is
1061 * created against does not use any color attachments.
1062 */
1063 bool uses_color_att = false;
1064 for (unsigned i = 0; i < subpass->color_count; ++i) {
1065 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1066 uses_color_att = true;
1067 break;
1068 }
1069 }
1070
1071 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1072 assert(pCreateInfo->pColorBlendState);
1073 typed_memcpy(dynamic->blend_constants,
1074 pCreateInfo->pColorBlendState->blendConstants, 4);
1075 }
1076
1077 /* If there is no depthstencil attachment, then don't read
1078 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1079 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1080 * no need to override the depthstencil defaults in
1081 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1082 *
1083 * Section 9.2 of the Vulkan 1.0.15 spec says:
1084 *
1085 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1086 * disabled or if the subpass of the render pass the pipeline is created
1087 * against does not use a depth/stencil attachment.
1088 */
1089 if (needed_states &&
1090 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1091 assert(pCreateInfo->pDepthStencilState);
1092
1093 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1094 dynamic->depth_bounds.min =
1095 pCreateInfo->pDepthStencilState->minDepthBounds;
1096 dynamic->depth_bounds.max =
1097 pCreateInfo->pDepthStencilState->maxDepthBounds;
1098 }
1099
1100 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1101 dynamic->stencil_compare_mask.front =
1102 pCreateInfo->pDepthStencilState->front.compareMask;
1103 dynamic->stencil_compare_mask.back =
1104 pCreateInfo->pDepthStencilState->back.compareMask;
1105 }
1106
1107 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1108 dynamic->stencil_write_mask.front =
1109 pCreateInfo->pDepthStencilState->front.writeMask;
1110 dynamic->stencil_write_mask.back =
1111 pCreateInfo->pDepthStencilState->back.writeMask;
1112 }
1113
1114 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1115 dynamic->stencil_reference.front =
1116 pCreateInfo->pDepthStencilState->front.reference;
1117 dynamic->stencil_reference.back =
1118 pCreateInfo->pDepthStencilState->back.reference;
1119 }
1120 }
1121
1122 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1123 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1124 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1125 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1126 typed_memcpy(dynamic->discard_rectangle.rectangles,
1127 discard_rectangle_info->pDiscardRectangles,
1128 discard_rectangle_info->discardRectangleCount);
1129 }
1130
1131 pipeline->dynamic_state.mask = states;
1132 }
1133
1134 static struct radv_gs_state
1135 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1136 const struct radv_pipeline *pipeline)
1137 {
1138 struct radv_gs_state gs = {0};
1139 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1140 struct radv_es_output_info *es_info;
1141 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1142 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1143 else
1144 es_info = radv_pipeline_has_tess(pipeline) ?
1145 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1146 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1147
1148 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1149 bool uses_adjacency;
1150 switch(pCreateInfo->pInputAssemblyState->topology) {
1151 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1152 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1153 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1154 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1155 uses_adjacency = true;
1156 break;
1157 default:
1158 uses_adjacency = false;
1159 break;
1160 }
1161
1162 /* All these are in dwords: */
1163 /* We can't allow using the whole LDS, because GS waves compete with
1164 * other shader stages for LDS space. */
1165 const unsigned max_lds_size = 8 * 1024;
1166 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1167 unsigned esgs_lds_size;
1168
1169 /* All these are per subgroup: */
1170 const unsigned max_out_prims = 32 * 1024;
1171 const unsigned max_es_verts = 255;
1172 const unsigned ideal_gs_prims = 64;
1173 unsigned max_gs_prims, gs_prims;
1174 unsigned min_es_verts, es_verts, worst_case_es_verts;
1175
1176 if (uses_adjacency || gs_num_invocations > 1)
1177 max_gs_prims = 127 / gs_num_invocations;
1178 else
1179 max_gs_prims = 255;
1180
1181 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1182 * Make sure we don't go over the maximum value.
1183 */
1184 if (gs_info->gs.vertices_out > 0) {
1185 max_gs_prims = MIN2(max_gs_prims,
1186 max_out_prims /
1187 (gs_info->gs.vertices_out * gs_num_invocations));
1188 }
1189 assert(max_gs_prims > 0);
1190
1191 /* If the primitive has adjacency, halve the number of vertices
1192 * that will be reused in multiple primitives.
1193 */
1194 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1195
1196 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1197 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1198
1199 /* Compute ESGS LDS size based on the worst case number of ES vertices
1200 * needed to create the target number of GS prims per subgroup.
1201 */
1202 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1203
1204 /* If total LDS usage is too big, refactor partitions based on ratio
1205 * of ESGS item sizes.
1206 */
1207 if (esgs_lds_size > max_lds_size) {
1208 /* Our target GS Prims Per Subgroup was too large. Calculate
1209 * the maximum number of GS Prims Per Subgroup that will fit
1210 * into LDS, capped by the maximum that the hardware can support.
1211 */
1212 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1213 max_gs_prims);
1214 assert(gs_prims > 0);
1215 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1216 max_es_verts);
1217
1218 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1219 assert(esgs_lds_size <= max_lds_size);
1220 }
1221
1222 /* Now calculate remaining ESGS information. */
1223 if (esgs_lds_size)
1224 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1225 else
1226 es_verts = max_es_verts;
1227
1228 /* Vertices for adjacency primitives are not always reused, so restore
1229 * it for ES_VERTS_PER_SUBGRP.
1230 */
1231 min_es_verts = gs_info->gs.vertices_in;
1232
1233 /* For normal primitives, the VGT only checks if they are past the ES
1234 * verts per subgroup after allocating a full GS primitive and if they
1235 * are, kick off a new subgroup. But if those additional ES verts are
1236 * unique (e.g. not reused) we need to make sure there is enough LDS
1237 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1238 */
1239 es_verts -= min_es_verts - 1;
1240
1241 uint32_t es_verts_per_subgroup = es_verts;
1242 uint32_t gs_prims_per_subgroup = gs_prims;
1243 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1244 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1245 gs.lds_size = align(esgs_lds_size, 128) / 128;
1246 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1247 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1248 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1249 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1250 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1251 assert(max_prims_per_subgroup <= max_out_prims);
1252
1253 return gs;
1254 }
1255
1256 static void
1257 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1258 {
1259 struct radv_device *device = pipeline->device;
1260 unsigned num_se = device->physical_device->rad_info.max_se;
1261 unsigned wave_size = 64;
1262 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1263 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1264 unsigned alignment = 256 * num_se;
1265 /* The maximum size is 63.999 MB per SE. */
1266 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1267 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1268
1269 /* Calculate the minimum size. */
1270 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1271 wave_size, alignment);
1272 /* These are recommended sizes, not minimum sizes. */
1273 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1274 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1275 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1276 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1277
1278 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1279 esgs_ring_size = align(esgs_ring_size, alignment);
1280 gsvs_ring_size = align(gsvs_ring_size, alignment);
1281
1282 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1283 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1284
1285 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1286 }
1287
1288 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1289 unsigned *lds_size)
1290 {
1291 /* If tessellation is all offchip and on-chip GS isn't used, this
1292 * workaround is not needed.
1293 */
1294 return;
1295
1296 /* SPI barrier management bug:
1297 * Make sure we have at least 4k of LDS in use to avoid the bug.
1298 * It applies to workgroup sizes of more than one wavefront.
1299 */
1300 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1301 device->physical_device->rad_info.family == CHIP_KABINI ||
1302 device->physical_device->rad_info.family == CHIP_MULLINS)
1303 *lds_size = MAX2(*lds_size, 8);
1304 }
1305
1306 struct radv_shader_variant *
1307 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1308 {
1309 if (pipeline->shaders[MESA_SHADER_VERTEX])
1310 return pipeline->shaders[MESA_SHADER_VERTEX];
1311 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1312 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1313 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1314 }
1315
1316 static struct radv_shader_variant *
1317 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1318 {
1319 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1320 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1321 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1322 }
1323
1324 static struct radv_tessellation_state
1325 calculate_tess_state(struct radv_pipeline *pipeline,
1326 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1327 {
1328 unsigned num_tcs_input_cp;
1329 unsigned num_tcs_output_cp;
1330 unsigned lds_size;
1331 unsigned num_patches;
1332 struct radv_tessellation_state tess = {0};
1333
1334 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1335 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1336 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1337
1338 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1339
1340 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1341 assert(lds_size <= 65536);
1342 lds_size = align(lds_size, 512) / 512;
1343 } else {
1344 assert(lds_size <= 32768);
1345 lds_size = align(lds_size, 256) / 256;
1346 }
1347 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1348
1349 tess.lds_size = lds_size;
1350
1351 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1352 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1353 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1354 tess.num_patches = num_patches;
1355
1356 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1357 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1358
1359 switch (tes->info.tes.primitive_mode) {
1360 case GL_TRIANGLES:
1361 type = V_028B6C_TESS_TRIANGLE;
1362 break;
1363 case GL_QUADS:
1364 type = V_028B6C_TESS_QUAD;
1365 break;
1366 case GL_ISOLINES:
1367 type = V_028B6C_TESS_ISOLINE;
1368 break;
1369 }
1370
1371 switch (tes->info.tes.spacing) {
1372 case TESS_SPACING_EQUAL:
1373 partitioning = V_028B6C_PART_INTEGER;
1374 break;
1375 case TESS_SPACING_FRACTIONAL_ODD:
1376 partitioning = V_028B6C_PART_FRAC_ODD;
1377 break;
1378 case TESS_SPACING_FRACTIONAL_EVEN:
1379 partitioning = V_028B6C_PART_FRAC_EVEN;
1380 break;
1381 default:
1382 break;
1383 }
1384
1385 bool ccw = tes->info.tes.ccw;
1386 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1387 vk_find_struct_const(pCreateInfo->pTessellationState,
1388 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1389
1390 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1391 ccw = !ccw;
1392
1393 if (tes->info.tes.point_mode)
1394 topology = V_028B6C_OUTPUT_POINT;
1395 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1396 topology = V_028B6C_OUTPUT_LINE;
1397 else if (ccw)
1398 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1399 else
1400 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1401
1402 if (pipeline->device->has_distributed_tess) {
1403 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1404 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1405 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1406 else
1407 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1408 } else
1409 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1410
1411 tess.tf_param = S_028B6C_TYPE(type) |
1412 S_028B6C_PARTITIONING(partitioning) |
1413 S_028B6C_TOPOLOGY(topology) |
1414 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1415
1416 return tess;
1417 }
1418
1419 static const struct radv_prim_vertex_count prim_size_table[] = {
1420 [V_008958_DI_PT_NONE] = {0, 0},
1421 [V_008958_DI_PT_POINTLIST] = {1, 1},
1422 [V_008958_DI_PT_LINELIST] = {2, 2},
1423 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1424 [V_008958_DI_PT_TRILIST] = {3, 3},
1425 [V_008958_DI_PT_TRIFAN] = {3, 1},
1426 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1427 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1428 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1429 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1430 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1431 [V_008958_DI_PT_RECTLIST] = {3, 3},
1432 [V_008958_DI_PT_LINELOOP] = {2, 1},
1433 [V_008958_DI_PT_POLYGON] = {3, 1},
1434 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1435 };
1436
1437 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1438 {
1439 if (radv_pipeline_has_gs(pipeline))
1440 return &pipeline->gs_copy_shader->info.vs.outinfo;
1441 else if (radv_pipeline_has_tess(pipeline))
1442 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1443 else
1444 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1445 }
1446
1447 static void
1448 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1449 {
1450 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1451 int shader_count = 0;
1452
1453 if(shaders[MESA_SHADER_FRAGMENT]) {
1454 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1455 }
1456 if(shaders[MESA_SHADER_GEOMETRY]) {
1457 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1458 }
1459 if(shaders[MESA_SHADER_TESS_EVAL]) {
1460 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1461 }
1462 if(shaders[MESA_SHADER_TESS_CTRL]) {
1463 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1464 }
1465 if(shaders[MESA_SHADER_VERTEX]) {
1466 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1467 }
1468
1469 for (int i = 1; i < shader_count; ++i) {
1470 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1471 ordered_shaders[i - 1]);
1472
1473 nir_remove_dead_variables(ordered_shaders[i],
1474 nir_var_shader_out);
1475 nir_remove_dead_variables(ordered_shaders[i - 1],
1476 nir_var_shader_in);
1477
1478 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1479 ordered_shaders[i - 1]);
1480
1481 nir_compact_varyings(ordered_shaders[i],
1482 ordered_shaders[i - 1], true);
1483
1484 if (progress) {
1485 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1486 ac_lower_indirect_derefs(ordered_shaders[i],
1487 pipeline->device->physical_device->rad_info.chip_class);
1488 }
1489 radv_optimize_nir(ordered_shaders[i]);
1490
1491 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1492 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1493 pipeline->device->physical_device->rad_info.chip_class);
1494 }
1495 radv_optimize_nir(ordered_shaders[i - 1]);
1496 }
1497 }
1498 }
1499
1500
1501 static struct radv_pipeline_key
1502 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1503 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1504 const struct radv_blend_state *blend,
1505 bool has_view_index)
1506 {
1507 const VkPipelineVertexInputStateCreateInfo *input_state =
1508 pCreateInfo->pVertexInputState;
1509 struct radv_pipeline_key key;
1510 memset(&key, 0, sizeof(key));
1511
1512 key.has_multiview_view_index = has_view_index;
1513
1514 uint32_t binding_input_rate = 0;
1515 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1516 if (input_state->pVertexBindingDescriptions[i].inputRate)
1517 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1518 }
1519
1520 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1521 unsigned binding;
1522 binding = input_state->pVertexAttributeDescriptions[i].binding;
1523 if (binding_input_rate & (1u << binding))
1524 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1525 }
1526
1527 if (pCreateInfo->pTessellationState)
1528 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1529
1530
1531 if (pCreateInfo->pMultisampleState &&
1532 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1533 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1534 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1535 key.multisample = true;
1536 key.log2_num_samples = util_logbase2(num_samples);
1537 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1538 }
1539
1540 key.col_format = blend->spi_shader_col_format;
1541 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1542 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1543
1544 return key;
1545 }
1546
1547 static void
1548 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1549 const struct radv_pipeline_key *key,
1550 nir_shader **nir)
1551 {
1552 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1553
1554 if (nir[MESA_SHADER_TESS_CTRL]) {
1555 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1556 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1557 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1558 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1559
1560 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1561 }
1562
1563 if (nir[MESA_SHADER_GEOMETRY]) {
1564 if (nir[MESA_SHADER_TESS_CTRL])
1565 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1566 else
1567 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1568 }
1569
1570 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1571 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1572
1573 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1574 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1575 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1576 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1577 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1578 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1579 }
1580
1581 static void
1582 merge_tess_info(struct shader_info *tes_info,
1583 const struct shader_info *tcs_info)
1584 {
1585 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1586 *
1587 * "PointMode. Controls generation of points rather than triangles
1588 * or lines. This functionality defaults to disabled, and is
1589 * enabled if either shader stage includes the execution mode.
1590 *
1591 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1592 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1593 * and OutputVertices, it says:
1594 *
1595 * "One mode must be set in at least one of the tessellation
1596 * shader stages."
1597 *
1598 * So, the fields can be set in either the TCS or TES, but they must
1599 * agree if set in both. Our backend looks at TES, so bitwise-or in
1600 * the values from the TCS.
1601 */
1602 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1603 tes_info->tess.tcs_vertices_out == 0 ||
1604 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1605 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1606
1607 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1608 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1609 tcs_info->tess.spacing == tes_info->tess.spacing);
1610 tes_info->tess.spacing |= tcs_info->tess.spacing;
1611
1612 assert(tcs_info->tess.primitive_mode == 0 ||
1613 tes_info->tess.primitive_mode == 0 ||
1614 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1615 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1616 tes_info->tess.ccw |= tcs_info->tess.ccw;
1617 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1618 }
1619
1620 static
1621 void radv_create_shaders(struct radv_pipeline *pipeline,
1622 struct radv_device *device,
1623 struct radv_pipeline_cache *cache,
1624 struct radv_pipeline_key key,
1625 const VkPipelineShaderStageCreateInfo **pStages)
1626 {
1627 struct radv_shader_module fs_m = {0};
1628 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1629 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1630 void *codes[MESA_SHADER_STAGES] = {0};
1631 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1632 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1633 unsigned char hash[20], gs_copy_hash[20];
1634
1635 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1636 if (pStages[i]) {
1637 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1638 if (modules[i]->nir)
1639 _mesa_sha1_compute(modules[i]->nir->info.name,
1640 strlen(modules[i]->nir->info.name),
1641 modules[i]->sha1);
1642 }
1643 }
1644
1645 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1646 memcpy(gs_copy_hash, hash, 20);
1647 gs_copy_hash[0] ^= 1;
1648
1649 if (modules[MESA_SHADER_GEOMETRY]) {
1650 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1651 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1652 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1653 }
1654
1655 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1656 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1657 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1658 if (pipeline->shaders[i])
1659 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1660 }
1661 return;
1662 }
1663
1664 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1665 nir_builder fs_b;
1666 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1667 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1668 fs_m.nir = fs_b.shader;
1669 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1670 }
1671
1672 /* Determine first and last stage. */
1673 unsigned first = MESA_SHADER_STAGES;
1674 unsigned last = 0;
1675 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1676 if (!pStages[i])
1677 continue;
1678 if (first == MESA_SHADER_STAGES)
1679 first = i;
1680 last = i;
1681 }
1682
1683 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1684 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1685
1686 if (!modules[i])
1687 continue;
1688
1689 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1690 stage ? stage->pName : "main", i,
1691 stage ? stage->pSpecializationInfo : NULL);
1692 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1693
1694 /* We don't want to alter meta shaders IR directly so clone it
1695 * first.
1696 */
1697 if (nir[i]->info.name) {
1698 nir[i] = nir_shader_clone(NULL, nir[i]);
1699 }
1700
1701 if (first != last) {
1702 nir_variable_mode mask = 0;
1703
1704 if (i != first)
1705 mask = mask | nir_var_shader_in;
1706
1707 if (i != last)
1708 mask = mask | nir_var_shader_out;
1709
1710 nir_lower_io_to_scalar_early(nir[i], mask);
1711 radv_optimize_nir(nir[i]);
1712 }
1713 }
1714
1715 if (nir[MESA_SHADER_TESS_CTRL]) {
1716 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1717 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1718 }
1719
1720 radv_link_shaders(pipeline, nir);
1721
1722 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1723 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1724 nir_print_shader(nir[i], stderr);
1725 }
1726
1727 radv_fill_shader_keys(keys, &key, nir);
1728
1729 if (nir[MESA_SHADER_FRAGMENT]) {
1730 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1731 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1732 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1733 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1734 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1735 }
1736
1737 /* TODO: These are no longer used as keys we should refactor this */
1738 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1739 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1740 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
1741 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1742 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1743 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1744 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
1745 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1746 }
1747
1748 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1749 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1750 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1751 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1752 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1753 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1754 pipeline->layout,
1755 &key, &codes[MESA_SHADER_TESS_CTRL],
1756 &code_sizes[MESA_SHADER_TESS_CTRL]);
1757 }
1758 modules[MESA_SHADER_VERTEX] = NULL;
1759 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1760 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1761 }
1762
1763 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1764 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1765 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1766 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1767 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1768 pipeline->layout,
1769 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1770 &code_sizes[MESA_SHADER_GEOMETRY]);
1771 }
1772 modules[pre_stage] = NULL;
1773 }
1774
1775 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1776 if(modules[i] && !pipeline->shaders[i]) {
1777 if (i == MESA_SHADER_TESS_CTRL) {
1778 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
1779 }
1780 if (i == MESA_SHADER_TESS_EVAL) {
1781 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1782 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1783 }
1784 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1785 pipeline->layout,
1786 keys + i, &codes[i],
1787 &code_sizes[i]);
1788 }
1789 }
1790
1791 if(modules[MESA_SHADER_GEOMETRY]) {
1792 void *gs_copy_code = NULL;
1793 unsigned gs_copy_code_size = 0;
1794 if (!pipeline->gs_copy_shader) {
1795 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1796 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1797 &gs_copy_code_size,
1798 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1799 }
1800
1801 if (pipeline->gs_copy_shader) {
1802 void *code[MESA_SHADER_STAGES] = {0};
1803 unsigned code_size[MESA_SHADER_STAGES] = {0};
1804 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1805
1806 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1807 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1808 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1809
1810 radv_pipeline_cache_insert_shaders(device, cache,
1811 gs_copy_hash,
1812 variants,
1813 (const void**)code,
1814 code_size);
1815 }
1816 free(gs_copy_code);
1817 }
1818
1819 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1820 (const void**)codes, code_sizes);
1821
1822 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1823 free(codes[i]);
1824 if (modules[i]) {
1825 if (!pipeline->device->keep_shader_info)
1826 ralloc_free(nir[i]);
1827
1828 if (radv_can_dump_shader_stats(device, modules[i]))
1829 radv_shader_dump_stats(device,
1830 pipeline->shaders[i],
1831 i, stderr);
1832 }
1833 }
1834
1835 if (fs_m.nir)
1836 ralloc_free(fs_m.nir);
1837 }
1838
1839 static uint32_t
1840 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1841 gl_shader_stage stage, enum chip_class chip_class)
1842 {
1843 bool has_gs = radv_pipeline_has_gs(pipeline);
1844 bool has_tess = radv_pipeline_has_tess(pipeline);
1845 switch (stage) {
1846 case MESA_SHADER_FRAGMENT:
1847 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1848 case MESA_SHADER_VERTEX:
1849 if (chip_class >= GFX9) {
1850 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1851 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1852 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1853 }
1854 if (has_tess)
1855 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1856 else
1857 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1858 case MESA_SHADER_GEOMETRY:
1859 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1860 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1861 case MESA_SHADER_COMPUTE:
1862 return R_00B900_COMPUTE_USER_DATA_0;
1863 case MESA_SHADER_TESS_CTRL:
1864 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1865 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1866 case MESA_SHADER_TESS_EVAL:
1867 if (chip_class >= GFX9) {
1868 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1869 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1870 }
1871 if (has_gs)
1872 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1873 else
1874 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1875 default:
1876 unreachable("unknown shader");
1877 }
1878 }
1879
1880 struct radv_bin_size_entry {
1881 unsigned bpp;
1882 VkExtent2D extent;
1883 };
1884
1885 static VkExtent2D
1886 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1887 {
1888 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1889 {
1890 /* One RB / SE */
1891 {
1892 /* One shader engine */
1893 { 0, {128, 128}},
1894 { 1, { 64, 128}},
1895 { 2, { 32, 128}},
1896 { 3, { 16, 128}},
1897 { 17, { 0, 0}},
1898 { UINT_MAX, { 0, 0}},
1899 },
1900 {
1901 /* Two shader engines */
1902 { 0, {128, 128}},
1903 { 2, { 64, 128}},
1904 { 3, { 32, 128}},
1905 { 5, { 16, 128}},
1906 { 17, { 0, 0}},
1907 { UINT_MAX, { 0, 0}},
1908 },
1909 {
1910 /* Four shader engines */
1911 { 0, {128, 128}},
1912 { 3, { 64, 128}},
1913 { 5, { 16, 128}},
1914 { 17, { 0, 0}},
1915 { UINT_MAX, { 0, 0}},
1916 },
1917 },
1918 {
1919 /* Two RB / SE */
1920 {
1921 /* One shader engine */
1922 { 0, {128, 128}},
1923 { 2, { 64, 128}},
1924 { 3, { 32, 128}},
1925 { 5, { 16, 128}},
1926 { 33, { 0, 0}},
1927 { UINT_MAX, { 0, 0}},
1928 },
1929 {
1930 /* Two shader engines */
1931 { 0, {128, 128}},
1932 { 3, { 64, 128}},
1933 { 5, { 32, 128}},
1934 { 9, { 16, 128}},
1935 { 33, { 0, 0}},
1936 { UINT_MAX, { 0, 0}},
1937 },
1938 {
1939 /* Four shader engines */
1940 { 0, {256, 256}},
1941 { 2, {128, 256}},
1942 { 3, {128, 128}},
1943 { 5, { 64, 128}},
1944 { 9, { 16, 128}},
1945 { 33, { 0, 0}},
1946 { UINT_MAX, { 0, 0}},
1947 },
1948 },
1949 {
1950 /* Four RB / SE */
1951 {
1952 /* One shader engine */
1953 { 0, {128, 256}},
1954 { 2, {128, 128}},
1955 { 3, { 64, 128}},
1956 { 5, { 32, 128}},
1957 { 9, { 16, 128}},
1958 { 33, { 0, 0}},
1959 { UINT_MAX, { 0, 0}},
1960 },
1961 {
1962 /* Two shader engines */
1963 { 0, {256, 256}},
1964 { 2, {128, 256}},
1965 { 3, {128, 128}},
1966 { 5, { 64, 128}},
1967 { 9, { 32, 128}},
1968 { 17, { 16, 128}},
1969 { 33, { 0, 0}},
1970 { UINT_MAX, { 0, 0}},
1971 },
1972 {
1973 /* Four shader engines */
1974 { 0, {256, 512}},
1975 { 2, {256, 256}},
1976 { 3, {128, 256}},
1977 { 5, {128, 128}},
1978 { 9, { 64, 128}},
1979 { 17, { 16, 128}},
1980 { 33, { 0, 0}},
1981 { UINT_MAX, { 0, 0}},
1982 },
1983 },
1984 };
1985 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
1986 {
1987 // One RB / SE
1988 {
1989 // One shader engine
1990 { 0, {128, 256}},
1991 { 2, {128, 128}},
1992 { 4, { 64, 128}},
1993 { 7, { 32, 128}},
1994 { 13, { 16, 128}},
1995 { 49, { 0, 0}},
1996 { UINT_MAX, { 0, 0}},
1997 },
1998 {
1999 // Two shader engines
2000 { 0, {256, 256}},
2001 { 2, {128, 256}},
2002 { 4, {128, 128}},
2003 { 7, { 64, 128}},
2004 { 13, { 32, 128}},
2005 { 25, { 16, 128}},
2006 { 49, { 0, 0}},
2007 { UINT_MAX, { 0, 0}},
2008 },
2009 {
2010 // Four shader engines
2011 { 0, {256, 512}},
2012 { 2, {256, 256}},
2013 { 4, {128, 256}},
2014 { 7, {128, 128}},
2015 { 13, { 64, 128}},
2016 { 25, { 16, 128}},
2017 { 49, { 0, 0}},
2018 { UINT_MAX, { 0, 0}},
2019 },
2020 },
2021 {
2022 // Two RB / SE
2023 {
2024 // One shader engine
2025 { 0, {256, 256}},
2026 { 2, {128, 256}},
2027 { 4, {128, 128}},
2028 { 7, { 64, 128}},
2029 { 13, { 32, 128}},
2030 { 25, { 16, 128}},
2031 { 97, { 0, 0}},
2032 { UINT_MAX, { 0, 0}},
2033 },
2034 {
2035 // Two shader engines
2036 { 0, {256, 512}},
2037 { 2, {256, 256}},
2038 { 4, {128, 256}},
2039 { 7, {128, 128}},
2040 { 13, { 64, 128}},
2041 { 25, { 32, 128}},
2042 { 49, { 16, 128}},
2043 { 97, { 0, 0}},
2044 { UINT_MAX, { 0, 0}},
2045 },
2046 {
2047 // Four shader engines
2048 { 0, {512, 512}},
2049 { 2, {256, 512}},
2050 { 4, {256, 256}},
2051 { 7, {128, 256}},
2052 { 13, {128, 128}},
2053 { 25, { 64, 128}},
2054 { 49, { 16, 128}},
2055 { 97, { 0, 0}},
2056 { UINT_MAX, { 0, 0}},
2057 },
2058 },
2059 {
2060 // Four RB / SE
2061 {
2062 // One shader engine
2063 { 0, {256, 512}},
2064 { 2, {256, 256}},
2065 { 4, {128, 256}},
2066 { 7, {128, 128}},
2067 { 13, { 64, 128}},
2068 { 25, { 32, 128}},
2069 { 49, { 16, 128}},
2070 { UINT_MAX, { 0, 0}},
2071 },
2072 {
2073 // Two shader engines
2074 { 0, {512, 512}},
2075 { 2, {256, 512}},
2076 { 4, {256, 256}},
2077 { 7, {128, 256}},
2078 { 13, {128, 128}},
2079 { 25, { 64, 128}},
2080 { 49, { 32, 128}},
2081 { 97, { 16, 128}},
2082 { UINT_MAX, { 0, 0}},
2083 },
2084 {
2085 // Four shader engines
2086 { 0, {512, 512}},
2087 { 4, {256, 512}},
2088 { 7, {256, 256}},
2089 { 13, {128, 256}},
2090 { 25, {128, 128}},
2091 { 49, { 64, 128}},
2092 { 97, { 16, 128}},
2093 { UINT_MAX, { 0, 0}},
2094 },
2095 },
2096 };
2097
2098 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2099 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2100 VkExtent2D extent = {512, 512};
2101
2102 unsigned log_num_rb_per_se =
2103 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2104 pipeline->device->physical_device->rad_info.max_se);
2105 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2106
2107 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2108 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2109 unsigned effective_samples = total_samples;
2110 unsigned color_bytes_per_pixel = 0;
2111
2112 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2113 if (vkblend) {
2114 for (unsigned i = 0; i < subpass->color_count; i++) {
2115 if (!vkblend->pAttachments[i].colorWriteMask)
2116 continue;
2117
2118 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2119 continue;
2120
2121 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2122 color_bytes_per_pixel += vk_format_get_blocksize(format);
2123 }
2124
2125 /* MSAA images typically don't use all samples all the time. */
2126 if (effective_samples >= 2 && ps_iter_samples <= 1)
2127 effective_samples = 2;
2128 color_bytes_per_pixel *= effective_samples;
2129 }
2130
2131 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2132 while(color_entry->bpp <= color_bytes_per_pixel)
2133 ++color_entry;
2134
2135 extent = color_entry->extent;
2136
2137 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2138 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2139
2140 /* Coefficients taken from AMDVLK */
2141 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2142 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2143 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2144
2145 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2146 while(ds_entry->bpp <= ds_bytes_per_pixel)
2147 ++ds_entry;
2148
2149 extent.width = MIN2(extent.width, ds_entry->extent.width);
2150 extent.height = MIN2(extent.height, ds_entry->extent.height);
2151 }
2152
2153 return extent;
2154 }
2155
2156 static void
2157 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2158 struct radv_pipeline *pipeline,
2159 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2160 {
2161 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2162 return;
2163
2164 uint32_t pa_sc_binner_cntl_0 =
2165 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2166 S_028C44_DISABLE_START_OF_PRIM(1);
2167 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2168
2169 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2170
2171 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2172 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2173 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2174
2175 switch (pipeline->device->physical_device->rad_info.family) {
2176 case CHIP_VEGA10:
2177 case CHIP_VEGA12:
2178 context_states_per_bin = 1;
2179 persistent_states_per_bin = 1;
2180 fpovs_per_batch = 63;
2181 break;
2182 case CHIP_RAVEN:
2183 context_states_per_bin = 6;
2184 persistent_states_per_bin = 32;
2185 fpovs_per_batch = 63;
2186 break;
2187 default:
2188 unreachable("unhandled family while determining binning state.");
2189 }
2190
2191 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2192 pa_sc_binner_cntl_0 =
2193 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2194 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2195 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2196 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2197 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2198 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2199 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2200 S_028C44_DISABLE_START_OF_PRIM(1) |
2201 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2202 S_028C44_OPTIMAL_BIN_SELECTION(1);
2203 }
2204
2205 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2206 pa_sc_binner_cntl_0);
2207 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2208 db_dfsm_control);
2209 }
2210
2211
2212 static void
2213 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2214 struct radv_pipeline *pipeline,
2215 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2216 const struct radv_graphics_pipeline_create_info *extra)
2217 {
2218 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2219 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2220 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2221 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2222 struct radv_render_pass_attachment *attachment = NULL;
2223 uint32_t db_depth_control = 0, db_stencil_control = 0;
2224 uint32_t db_render_control = 0, db_render_override2 = 0;
2225 uint32_t db_render_override = 0;
2226
2227 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2228 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2229
2230 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2231 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2232
2233 if (vkds && has_depth_attachment) {
2234 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2235 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2236 S_028800_ZFUNC(vkds->depthCompareOp) |
2237 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2238
2239 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2240 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2241 }
2242
2243 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2244 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2245 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2246 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2247 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2248 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2249
2250 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2251 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2252 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2253 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2254 }
2255
2256 if (attachment && extra) {
2257 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2258 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2259
2260 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2261 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2262 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2263 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2264 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2265 }
2266
2267 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2268 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2269
2270 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2271 !pCreateInfo->pRasterizationState->depthClampEnable &&
2272 ps->info.info.ps.writes_z) {
2273 /* From VK_EXT_depth_range_unrestricted spec:
2274 *
2275 * "The behavior described in Primitive Clipping still applies.
2276 * If depth clamping is disabled the depth values are still
2277 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2278 * depth clamping is enabled the above equation is ignored and
2279 * the depth values are instead clamped to the VkViewport
2280 * minDepth and maxDepth values, which in the case of this
2281 * extension can be outside of the 0.0 to 1.0 range."
2282 */
2283 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2284 }
2285
2286 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2287 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2288
2289 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2290 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2291 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2292 }
2293
2294 static void
2295 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2296 struct radv_pipeline *pipeline,
2297 const struct radv_blend_state *blend)
2298 {
2299 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2300 radeon_emit_array(cs, blend->cb_blend_control,
2301 8);
2302 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2303 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2304
2305 if (pipeline->device->physical_device->has_rbplus) {
2306
2307 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2308 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2309
2310 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2311 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2312 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2313 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2314 }
2315
2316 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2317
2318 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2319 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2320 }
2321
2322
2323 static void
2324 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2325 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2326 {
2327 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2328
2329 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2330 S_028810_PS_UCP_MODE(3) |
2331 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2332 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2333 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2334 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2335 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2336
2337 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2338 S_0286D4_FLAT_SHADE_ENA(1) |
2339 S_0286D4_PNT_SPRITE_ENA(1) |
2340 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2341 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2342 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2343 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2344 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2345
2346 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2347 S_028BE4_PIX_CENTER(1) | // TODO verify
2348 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2349 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2350
2351 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2352 S_028814_FACE(vkraster->frontFace) |
2353 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2354 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2355 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2356 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2357 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2358 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2359 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2360 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2361 }
2362
2363
2364 static void
2365 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2366 struct radv_pipeline *pipeline)
2367 {
2368 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2369
2370 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2371 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2372 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2373
2374 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2375 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2376
2377 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2378 uint32_t offset;
2379 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2380 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2381 if (loc->sgpr_idx == -1)
2382 return;
2383 assert(loc->num_sgprs == 1);
2384 assert(!loc->indirect);
2385 switch (pipeline->graphics.ms.num_samples) {
2386 default:
2387 offset = 0;
2388 break;
2389 case 2:
2390 offset = 1;
2391 break;
2392 case 4:
2393 offset = 3;
2394 break;
2395 case 8:
2396 offset = 7;
2397 break;
2398 case 16:
2399 offset = 15;
2400 break;
2401 }
2402
2403 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2404 }
2405 }
2406
2407 static void
2408 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2409 const struct radv_pipeline *pipeline)
2410 {
2411 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2412
2413 uint32_t vgt_primitiveid_en = false;
2414 uint32_t vgt_gs_mode = 0;
2415
2416 if (radv_pipeline_has_gs(pipeline)) {
2417 const struct radv_shader_variant *gs =
2418 pipeline->shaders[MESA_SHADER_GEOMETRY];
2419
2420 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2421 pipeline->device->physical_device->rad_info.chip_class);
2422 } else if (outinfo->export_prim_id) {
2423 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2424 vgt_primitiveid_en = true;
2425 }
2426
2427 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2428 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2429 }
2430
2431 static void
2432 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2433 struct radv_pipeline *pipeline,
2434 struct radv_shader_variant *shader)
2435 {
2436 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2437
2438 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2439 radeon_emit(cs, va >> 8);
2440 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2441 radeon_emit(cs, shader->rsrc1);
2442 radeon_emit(cs, shader->rsrc2);
2443
2444 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2445 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2446 clip_dist_mask = outinfo->clip_dist_mask;
2447 cull_dist_mask = outinfo->cull_dist_mask;
2448 total_mask = clip_dist_mask | cull_dist_mask;
2449 bool misc_vec_ena = outinfo->writes_pointsize ||
2450 outinfo->writes_layer ||
2451 outinfo->writes_viewport_index;
2452
2453 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2454 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2455
2456 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2457 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2458 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2459 V_02870C_SPI_SHADER_4COMP :
2460 V_02870C_SPI_SHADER_NONE) |
2461 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2462 V_02870C_SPI_SHADER_4COMP :
2463 V_02870C_SPI_SHADER_NONE) |
2464 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2465 V_02870C_SPI_SHADER_4COMP :
2466 V_02870C_SPI_SHADER_NONE));
2467
2468 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2469 S_028818_VTX_W0_FMT(1) |
2470 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2471 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2472 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2473
2474 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2475 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2476 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2477 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2478 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2479 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2480 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2481 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2482 cull_dist_mask << 8 |
2483 clip_dist_mask);
2484
2485 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2486 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2487 outinfo->writes_viewport_index);
2488 }
2489
2490 static void
2491 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2492 struct radv_pipeline *pipeline,
2493 struct radv_shader_variant *shader)
2494 {
2495 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2496
2497 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2498 radeon_emit(cs, va >> 8);
2499 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2500 radeon_emit(cs, shader->rsrc1);
2501 radeon_emit(cs, shader->rsrc2);
2502 }
2503
2504 static void
2505 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2506 struct radv_pipeline *pipeline,
2507 struct radv_shader_variant *shader,
2508 const struct radv_tessellation_state *tess)
2509 {
2510 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2511 uint32_t rsrc2 = shader->rsrc2;
2512
2513 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2514 radeon_emit(cs, va >> 8);
2515 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2516
2517 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2518 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2519 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2520 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2521
2522 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2523 radeon_emit(cs, shader->rsrc1);
2524 radeon_emit(cs, rsrc2);
2525 }
2526
2527 static void
2528 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2529 struct radv_pipeline *pipeline,
2530 struct radv_shader_variant *shader,
2531 const struct radv_tessellation_state *tess)
2532 {
2533 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2534
2535 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2536 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2537 radeon_emit(cs, va >> 8);
2538 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2539
2540 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2541 radeon_emit(cs, shader->rsrc1);
2542 radeon_emit(cs, shader->rsrc2 |
2543 S_00B42C_LDS_SIZE(tess->lds_size));
2544 } else {
2545 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2546 radeon_emit(cs, va >> 8);
2547 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2548 radeon_emit(cs, shader->rsrc1);
2549 radeon_emit(cs, shader->rsrc2);
2550 }
2551 }
2552
2553 static void
2554 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2555 struct radv_pipeline *pipeline,
2556 const struct radv_tessellation_state *tess)
2557 {
2558 struct radv_shader_variant *vs;
2559
2560 /* Skip shaders merged into HS/GS */
2561 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2562 if (!vs)
2563 return;
2564
2565 if (vs->info.vs.as_ls)
2566 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2567 else if (vs->info.vs.as_es)
2568 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2569 else
2570 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2571 }
2572
2573 static void
2574 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2575 struct radv_pipeline *pipeline,
2576 const struct radv_tessellation_state *tess)
2577 {
2578 if (!radv_pipeline_has_tess(pipeline))
2579 return;
2580
2581 struct radv_shader_variant *tes, *tcs;
2582
2583 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2584 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2585
2586 if (tes) {
2587 if (tes->info.tes.as_es)
2588 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2589 else
2590 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2591 }
2592
2593 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2594
2595 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2596 tess->tf_param);
2597
2598 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2599 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2600 tess->ls_hs_config);
2601 else
2602 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2603 tess->ls_hs_config);
2604 }
2605
2606 static void
2607 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2608 struct radv_pipeline *pipeline,
2609 const struct radv_gs_state *gs_state)
2610 {
2611 struct radv_shader_variant *gs;
2612 uint64_t va;
2613
2614 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2615 if (!gs)
2616 return;
2617
2618 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2619
2620 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2621 radeon_emit(cs, gsvs_itemsize);
2622 radeon_emit(cs, gsvs_itemsize);
2623 radeon_emit(cs, gsvs_itemsize);
2624
2625 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2626
2627 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2628
2629 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2630 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2631 radeon_emit(cs, gs_vert_itemsize >> 2);
2632 radeon_emit(cs, 0);
2633 radeon_emit(cs, 0);
2634 radeon_emit(cs, 0);
2635
2636 uint32_t gs_num_invocations = gs->info.gs.invocations;
2637 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2638 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2639 S_028B90_ENABLE(gs_num_invocations > 0));
2640
2641 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2642 gs_state->vgt_esgs_ring_itemsize);
2643
2644 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2645
2646 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2647 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2648 radeon_emit(cs, va >> 8);
2649 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
2650
2651 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2652 radeon_emit(cs, gs->rsrc1);
2653 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2654
2655 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2656 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2657 } else {
2658 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2659 radeon_emit(cs, va >> 8);
2660 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
2661 radeon_emit(cs, gs->rsrc1);
2662 radeon_emit(cs, gs->rsrc2);
2663 }
2664
2665 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2666 }
2667
2668 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2669 {
2670 uint32_t ps_input_cntl;
2671 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2672 ps_input_cntl = S_028644_OFFSET(offset);
2673 if (flat_shade)
2674 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2675 } else {
2676 /* The input is a DEFAULT_VAL constant. */
2677 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2678 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2679 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2680 ps_input_cntl = S_028644_OFFSET(0x20) |
2681 S_028644_DEFAULT_VAL(offset);
2682 }
2683 return ps_input_cntl;
2684 }
2685
2686 static void
2687 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2688 struct radv_pipeline *pipeline)
2689 {
2690 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2691 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2692 uint32_t ps_input_cntl[32];
2693
2694 unsigned ps_offset = 0;
2695
2696 if (ps->info.info.ps.prim_id_input) {
2697 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2698 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2699 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2700 ++ps_offset;
2701 }
2702 }
2703
2704 if (ps->info.info.ps.layer_input ||
2705 ps->info.info.ps.uses_input_attachments ||
2706 ps->info.info.needs_multiview_view_index) {
2707 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2708 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2709 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2710 else
2711 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2712 ++ps_offset;
2713 }
2714
2715 if (ps->info.info.ps.has_pcoord) {
2716 unsigned val;
2717 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2718 ps_input_cntl[ps_offset] = val;
2719 ps_offset++;
2720 }
2721
2722 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2723 unsigned vs_offset;
2724 bool flat_shade;
2725 if (!(ps->info.fs.input_mask & (1u << i)))
2726 continue;
2727
2728 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2729 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2730 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2731 ++ps_offset;
2732 continue;
2733 }
2734
2735 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2736
2737 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2738 ++ps_offset;
2739 }
2740
2741 if (ps_offset) {
2742 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2743 for (unsigned i = 0; i < ps_offset; i++) {
2744 radeon_emit(cs, ps_input_cntl[i]);
2745 }
2746 }
2747 }
2748
2749 static uint32_t
2750 radv_compute_db_shader_control(const struct radv_device *device,
2751 const struct radv_shader_variant *ps)
2752 {
2753 unsigned z_order;
2754 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2755 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2756 else
2757 z_order = V_02880C_LATE_Z;
2758
2759 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
2760 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
2761 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2762 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
2763 S_02880C_Z_ORDER(z_order) |
2764 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2765 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2766 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
2767 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
2768 }
2769
2770 static void
2771 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2772 struct radv_pipeline *pipeline)
2773 {
2774 struct radv_shader_variant *ps;
2775 uint64_t va;
2776 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2777
2778 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2779 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2780
2781 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2782 radeon_emit(cs, va >> 8);
2783 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
2784 radeon_emit(cs, ps->rsrc1);
2785 radeon_emit(cs, ps->rsrc2);
2786
2787 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2788 radv_compute_db_shader_control(pipeline->device, ps));
2789
2790 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2791 ps->config.spi_ps_input_ena);
2792
2793 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2794 ps->config.spi_ps_input_addr);
2795
2796 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2797 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2798
2799 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2800
2801 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2802 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
2803 ps->info.info.ps.writes_stencil,
2804 ps->info.info.ps.writes_sample_mask));
2805
2806 if (pipeline->device->dfsm_allowed) {
2807 /* optimise this? */
2808 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2809 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2810 }
2811 }
2812
2813 static void
2814 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2815 struct radv_pipeline *pipeline)
2816 {
2817 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2818 return;
2819
2820 unsigned vtx_reuse_depth = 30;
2821 if (radv_pipeline_has_tess(pipeline) &&
2822 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2823 vtx_reuse_depth = 14;
2824 }
2825 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2826 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2827 }
2828
2829 static uint32_t
2830 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
2831 {
2832 uint32_t stages = 0;
2833 if (radv_pipeline_has_tess(pipeline)) {
2834 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2835 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2836
2837 if (radv_pipeline_has_gs(pipeline))
2838 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2839 S_028B54_GS_EN(1) |
2840 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2841 else
2842 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2843
2844 } else if (radv_pipeline_has_gs(pipeline))
2845 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2846 S_028B54_GS_EN(1) |
2847 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2848
2849 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
2850 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2851
2852 return stages;
2853 }
2854
2855 static uint32_t
2856 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
2857 {
2858 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
2859 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
2860
2861 if (!discard_rectangle_info)
2862 return 0xffff;
2863
2864 unsigned mask = 0;
2865
2866 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
2867 /* Interpret i as a bitmask, and then set the bit in the mask if
2868 * that combination of rectangles in which the pixel is contained
2869 * should pass the cliprect test. */
2870 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
2871
2872 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
2873 !relevant_subset)
2874 continue;
2875
2876 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
2877 relevant_subset)
2878 continue;
2879
2880 mask |= 1u << i;
2881 }
2882
2883 return mask;
2884 }
2885
2886 static void
2887 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2888 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2889 const struct radv_graphics_pipeline_create_info *extra,
2890 const struct radv_blend_state *blend,
2891 const struct radv_tessellation_state *tess,
2892 const struct radv_gs_state *gs,
2893 unsigned prim, unsigned gs_out)
2894 {
2895 pipeline->cs.buf = malloc(4 * 256);
2896 pipeline->cs.max_dw = 256;
2897
2898 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2899 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
2900 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
2901 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2902 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
2903 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
2904 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
2905 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
2906 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2907 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2908 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2909 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2910
2911 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2912 S_0286E8_WAVES(pipeline->max_waves) |
2913 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2914
2915 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
2916
2917 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2918 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
2919 } else {
2920 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
2921 }
2922 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
2923
2924 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
2925
2926 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2927 }
2928
2929 static struct radv_ia_multi_vgt_param_helpers
2930 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
2931 const struct radv_tessellation_state *tess,
2932 uint32_t prim)
2933 {
2934 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
2935 const struct radv_device *device = pipeline->device;
2936
2937 if (radv_pipeline_has_tess(pipeline))
2938 ia_multi_vgt_param.primgroup_size = tess->num_patches;
2939 else if (radv_pipeline_has_gs(pipeline))
2940 ia_multi_vgt_param.primgroup_size = 64;
2941 else
2942 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
2943
2944 ia_multi_vgt_param.partial_es_wave = false;
2945 if (pipeline->device->has_distributed_tess) {
2946 if (radv_pipeline_has_gs(pipeline)) {
2947 if (device->physical_device->rad_info.chip_class <= VI)
2948 ia_multi_vgt_param.partial_es_wave = true;
2949 }
2950 }
2951 /* GS requirement. */
2952 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
2953 ia_multi_vgt_param.partial_es_wave = true;
2954
2955 ia_multi_vgt_param.wd_switch_on_eop = false;
2956 if (device->physical_device->rad_info.chip_class >= CIK) {
2957 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2958 * 4 shader engines. Set 1 to pass the assertion below.
2959 * The other cases are hardware requirements. */
2960 if (device->physical_device->rad_info.max_se < 4 ||
2961 prim == V_008958_DI_PT_POLYGON ||
2962 prim == V_008958_DI_PT_LINELOOP ||
2963 prim == V_008958_DI_PT_TRIFAN ||
2964 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
2965 (pipeline->graphics.prim_restart_enable &&
2966 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
2967 (prim != V_008958_DI_PT_POINTLIST &&
2968 prim != V_008958_DI_PT_LINESTRIP &&
2969 prim != V_008958_DI_PT_TRISTRIP))))
2970 ia_multi_vgt_param.wd_switch_on_eop = true;
2971 }
2972
2973 ia_multi_vgt_param.ia_switch_on_eoi = false;
2974 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
2975 ia_multi_vgt_param.ia_switch_on_eoi = true;
2976 if (radv_pipeline_has_gs(pipeline) &&
2977 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
2978 ia_multi_vgt_param.ia_switch_on_eoi = true;
2979 if (radv_pipeline_has_tess(pipeline)) {
2980 /* SWITCH_ON_EOI must be set if PrimID is used. */
2981 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
2982 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
2983 ia_multi_vgt_param.ia_switch_on_eoi = true;
2984 }
2985
2986 ia_multi_vgt_param.partial_vs_wave = false;
2987 if (radv_pipeline_has_tess(pipeline)) {
2988 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2989 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2990 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2991 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2992 radv_pipeline_has_gs(pipeline))
2993 ia_multi_vgt_param.partial_vs_wave = true;
2994 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2995 if (device->has_distributed_tess) {
2996 if (radv_pipeline_has_gs(pipeline)) {
2997 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2998 device->physical_device->rad_info.family == CHIP_FIJI ||
2999 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3000 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3001 device->physical_device->rad_info.family == CHIP_POLARIS12)
3002 ia_multi_vgt_param.partial_vs_wave = true;
3003 } else {
3004 ia_multi_vgt_param.partial_vs_wave = true;
3005 }
3006 }
3007 }
3008
3009 ia_multi_vgt_param.base =
3010 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3011 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3012 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3013 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3014 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3015
3016 return ia_multi_vgt_param;
3017 }
3018
3019
3020 static void
3021 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3022 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3023 {
3024 const VkPipelineVertexInputStateCreateInfo *vi_info =
3025 pCreateInfo->pVertexInputState;
3026 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3027
3028 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3029 const VkVertexInputAttributeDescription *desc =
3030 &vi_info->pVertexAttributeDescriptions[i];
3031 unsigned loc = desc->location;
3032 const struct vk_format_description *format_desc;
3033 int first_non_void;
3034 uint32_t num_format, data_format;
3035 format_desc = vk_format_description(desc->format);
3036 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3037
3038 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3039 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3040
3041 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3042 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3043 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3044 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3045 S_008F0C_NUM_FORMAT(num_format) |
3046 S_008F0C_DATA_FORMAT(data_format);
3047 velems->format_size[loc] = format_desc->block.bits / 8;
3048 velems->offset[loc] = desc->offset;
3049 velems->binding[loc] = desc->binding;
3050 velems->count = MAX2(velems->count, loc + 1);
3051 }
3052
3053 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3054 const VkVertexInputBindingDescription *desc =
3055 &vi_info->pVertexBindingDescriptions[i];
3056
3057 pipeline->binding_stride[desc->binding] = desc->stride;
3058 }
3059 }
3060
3061 static VkResult
3062 radv_pipeline_init(struct radv_pipeline *pipeline,
3063 struct radv_device *device,
3064 struct radv_pipeline_cache *cache,
3065 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3066 const struct radv_graphics_pipeline_create_info *extra,
3067 const VkAllocationCallbacks *alloc)
3068 {
3069 VkResult result;
3070 bool has_view_index = false;
3071
3072 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3073 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3074 if (subpass->view_mask)
3075 has_view_index = true;
3076 if (alloc == NULL)
3077 alloc = &device->alloc;
3078
3079 pipeline->device = device;
3080 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3081 assert(pipeline->layout);
3082
3083 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3084
3085 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3086 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3087 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3088 pStages[stage] = &pCreateInfo->pStages[i];
3089 }
3090
3091 radv_create_shaders(pipeline, device, cache,
3092 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3093 pStages);
3094
3095 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3096 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
3097 uint32_t gs_out;
3098 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3099
3100 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3101
3102 if (radv_pipeline_has_gs(pipeline)) {
3103 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3104 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3105 } else {
3106 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3107 }
3108 if (extra && extra->use_rectlist) {
3109 prim = V_008958_DI_PT_RECTLIST;
3110 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3111 pipeline->graphics.can_use_guardband = true;
3112 }
3113 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3114 /* prim vertex count will need TESS changes */
3115 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3116
3117 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3118
3119 /* Ensure that some export memory is always allocated, for two reasons:
3120 *
3121 * 1) Correctness: The hardware ignores the EXEC mask if no export
3122 * memory is allocated, so KILL and alpha test do not work correctly
3123 * without this.
3124 * 2) Performance: Every shader needs at least a NULL export, even when
3125 * it writes no color/depth output. The NULL export instruction
3126 * stalls without this setting.
3127 *
3128 * Don't add this to CB_SHADER_MASK.
3129 */
3130 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3131 if (!blend.spi_shader_col_format) {
3132 if (!ps->info.info.ps.writes_z &&
3133 !ps->info.info.ps.writes_stencil &&
3134 !ps->info.info.ps.writes_sample_mask)
3135 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3136 }
3137
3138 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3139 if (pipeline->shaders[i]) {
3140 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3141 }
3142 }
3143
3144 struct radv_gs_state gs = {0};
3145 if (radv_pipeline_has_gs(pipeline)) {
3146 gs = calculate_gs_info(pCreateInfo, pipeline);
3147 calculate_gs_ring_sizes(pipeline, &gs);
3148 }
3149
3150 struct radv_tessellation_state tess = {0};
3151 if (radv_pipeline_has_tess(pipeline)) {
3152 if (prim == V_008958_DI_PT_PATCH) {
3153 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3154 pipeline->graphics.prim_vertex_count.incr = 1;
3155 }
3156 tess = calculate_tess_state(pipeline, pCreateInfo);
3157 }
3158
3159 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3160
3161 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3162
3163 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3164 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3165
3166 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3167 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3168 if (loc->sgpr_idx != -1) {
3169 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3170 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3171 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3172 pipeline->graphics.vtx_emit_num = 3;
3173 else
3174 pipeline->graphics.vtx_emit_num = 2;
3175 }
3176
3177 result = radv_pipeline_scratch_init(device, pipeline);
3178 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3179
3180 return result;
3181 }
3182
3183 VkResult
3184 radv_graphics_pipeline_create(
3185 VkDevice _device,
3186 VkPipelineCache _cache,
3187 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3188 const struct radv_graphics_pipeline_create_info *extra,
3189 const VkAllocationCallbacks *pAllocator,
3190 VkPipeline *pPipeline)
3191 {
3192 RADV_FROM_HANDLE(radv_device, device, _device);
3193 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3194 struct radv_pipeline *pipeline;
3195 VkResult result;
3196
3197 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3198 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3199 if (pipeline == NULL)
3200 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3201
3202 result = radv_pipeline_init(pipeline, device, cache,
3203 pCreateInfo, extra, pAllocator);
3204 if (result != VK_SUCCESS) {
3205 radv_pipeline_destroy(device, pipeline, pAllocator);
3206 return result;
3207 }
3208
3209 *pPipeline = radv_pipeline_to_handle(pipeline);
3210
3211 return VK_SUCCESS;
3212 }
3213
3214 VkResult radv_CreateGraphicsPipelines(
3215 VkDevice _device,
3216 VkPipelineCache pipelineCache,
3217 uint32_t count,
3218 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3219 const VkAllocationCallbacks* pAllocator,
3220 VkPipeline* pPipelines)
3221 {
3222 VkResult result = VK_SUCCESS;
3223 unsigned i = 0;
3224
3225 for (; i < count; i++) {
3226 VkResult r;
3227 r = radv_graphics_pipeline_create(_device,
3228 pipelineCache,
3229 &pCreateInfos[i],
3230 NULL, pAllocator, &pPipelines[i]);
3231 if (r != VK_SUCCESS) {
3232 result = r;
3233 pPipelines[i] = VK_NULL_HANDLE;
3234 }
3235 }
3236
3237 return result;
3238 }
3239
3240
3241 static void
3242 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3243 {
3244 struct radv_shader_variant *compute_shader;
3245 struct radv_device *device = pipeline->device;
3246 unsigned compute_resource_limits;
3247 unsigned waves_per_threadgroup;
3248 uint64_t va;
3249
3250 pipeline->cs.buf = malloc(20 * 4);
3251 pipeline->cs.max_dw = 20;
3252
3253 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3254 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3255
3256 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3257 radeon_emit(&pipeline->cs, va >> 8);
3258 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3259
3260 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3261 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3262 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3263
3264 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3265 S_00B860_WAVES(pipeline->max_waves) |
3266 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3267
3268 /* Calculate best compute resource limits. */
3269 waves_per_threadgroup =
3270 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3271 compute_shader->info.cs.block_size[1] *
3272 compute_shader->info.cs.block_size[2], 64);
3273 compute_resource_limits =
3274 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3275
3276 if (device->physical_device->rad_info.chip_class >= CIK) {
3277 unsigned num_cu_per_se =
3278 device->physical_device->rad_info.num_good_compute_units /
3279 device->physical_device->rad_info.max_se;
3280
3281 /* Force even distribution on all SIMDs in CU if the workgroup
3282 * size is 64. This has shown some good improvements if # of
3283 * CUs per SE is not a multiple of 4.
3284 */
3285 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3286 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3287 }
3288
3289 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3290 compute_resource_limits);
3291
3292 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3293 radeon_emit(&pipeline->cs,
3294 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3295 radeon_emit(&pipeline->cs,
3296 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3297 radeon_emit(&pipeline->cs,
3298 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3299
3300 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3301 }
3302
3303 static VkResult radv_compute_pipeline_create(
3304 VkDevice _device,
3305 VkPipelineCache _cache,
3306 const VkComputePipelineCreateInfo* pCreateInfo,
3307 const VkAllocationCallbacks* pAllocator,
3308 VkPipeline* pPipeline)
3309 {
3310 RADV_FROM_HANDLE(radv_device, device, _device);
3311 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3312 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3313 struct radv_pipeline *pipeline;
3314 VkResult result;
3315
3316 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3317 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3318 if (pipeline == NULL)
3319 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3320
3321 pipeline->device = device;
3322 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3323 assert(pipeline->layout);
3324
3325 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3326 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3327
3328 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3329 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3330 result = radv_pipeline_scratch_init(device, pipeline);
3331 if (result != VK_SUCCESS) {
3332 radv_pipeline_destroy(device, pipeline, pAllocator);
3333 return result;
3334 }
3335
3336 radv_compute_generate_pm4(pipeline);
3337
3338 *pPipeline = radv_pipeline_to_handle(pipeline);
3339
3340 return VK_SUCCESS;
3341 }
3342
3343 VkResult radv_CreateComputePipelines(
3344 VkDevice _device,
3345 VkPipelineCache pipelineCache,
3346 uint32_t count,
3347 const VkComputePipelineCreateInfo* pCreateInfos,
3348 const VkAllocationCallbacks* pAllocator,
3349 VkPipeline* pPipelines)
3350 {
3351 VkResult result = VK_SUCCESS;
3352
3353 unsigned i = 0;
3354 for (; i < count; i++) {
3355 VkResult r;
3356 r = radv_compute_pipeline_create(_device, pipelineCache,
3357 &pCreateInfos[i],
3358 pAllocator, &pPipelines[i]);
3359 if (r != VK_SUCCESS) {
3360 result = r;
3361 pPipelines[i] = VK_NULL_HANDLE;
3362 }
3363 }
3364
3365 return result;
3366 }