projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: store the ESGS ring size as part of gfx10_ngg_info
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
38 #include "vk_util.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
94 {
95 struct radv_shader_variant *variant = NULL;
96 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
97 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
98 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
99 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
100 else if (pipeline->shaders[MESA_SHADER_VERTEX])
101 variant = pipeline->shaders[MESA_SHADER_VERTEX];
102 else
103 return false;
104 return variant->info.is_ngg;
105 }
106
107 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
108 {
109 if (!radv_pipeline_has_gs(pipeline))
110 return false;
111
112 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
113 * On GFX10, it might be required in rare cases if it's not possible to
114 * enable NGG.
115 */
116 if (radv_pipeline_has_ngg(pipeline))
117 return false;
118
119 assert(pipeline->gs_copy_shader);
120 return true;
121 }
122
123 static void
124 radv_pipeline_destroy(struct radv_device *device,
125 struct radv_pipeline *pipeline,
126 const VkAllocationCallbacks* allocator)
127 {
128 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
129 if (pipeline->shaders[i])
130 radv_shader_variant_destroy(device, pipeline->shaders[i]);
131
132 if (pipeline->gs_copy_shader)
133 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
134
135 if(pipeline->cs.buf)
136 free(pipeline->cs.buf);
137 vk_free2(&device->alloc, allocator, pipeline);
138 }
139
140 void radv_DestroyPipeline(
141 VkDevice _device,
142 VkPipeline _pipeline,
143 const VkAllocationCallbacks* pAllocator)
144 {
145 RADV_FROM_HANDLE(radv_device, device, _device);
146 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
147
148 if (!_pipeline)
149 return;
150
151 radv_pipeline_destroy(device, pipeline, pAllocator);
152 }
153
154 static uint32_t get_hash_flags(struct radv_device *device)
155 {
156 uint32_t hash_flags = 0;
157
158 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
159 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
160 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
161 hash_flags |= RADV_HASH_SHADER_NO_NGG;
162 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
163 hash_flags |= RADV_HASH_SHADER_SISCHED;
164 if (device->physical_device->cs_wave_size == 32)
165 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
166 if (device->physical_device->ps_wave_size == 32)
167 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
168 if (device->physical_device->ge_wave_size == 32)
169 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
170 return hash_flags;
171 }
172
173 static VkResult
174 radv_pipeline_scratch_init(struct radv_device *device,
175 struct radv_pipeline *pipeline)
176 {
177 unsigned scratch_bytes_per_wave = 0;
178 unsigned max_waves = 0;
179 unsigned min_waves = 1;
180
181 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
182 if (pipeline->shaders[i]) {
183 unsigned max_stage_waves = device->scratch_waves;
184
185 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
186 pipeline->shaders[i]->config.scratch_bytes_per_wave);
187
188 max_stage_waves = MIN2(max_stage_waves,
189 4 * device->physical_device->rad_info.num_good_compute_units *
190 (256 / pipeline->shaders[i]->config.num_vgprs));
191 max_waves = MAX2(max_waves, max_stage_waves);
192 }
193 }
194
195 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
196 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
197 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
198 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
199 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
200 }
201
202 if (scratch_bytes_per_wave)
203 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
204
205 if (scratch_bytes_per_wave && max_waves < min_waves) {
206 /* Not really true at this moment, but will be true on first
207 * execution. Avoid having hanging shaders. */
208 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
209 }
210 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
211 pipeline->max_waves = max_waves;
212 return VK_SUCCESS;
213 }
214
215 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
216 {
217 switch (op) {
218 case VK_LOGIC_OP_CLEAR:
219 return V_028808_ROP3_CLEAR;
220 case VK_LOGIC_OP_AND:
221 return V_028808_ROP3_AND;
222 case VK_LOGIC_OP_AND_REVERSE:
223 return V_028808_ROP3_AND_REVERSE;
224 case VK_LOGIC_OP_COPY:
225 return V_028808_ROP3_COPY;
226 case VK_LOGIC_OP_AND_INVERTED:
227 return V_028808_ROP3_AND_INVERTED;
228 case VK_LOGIC_OP_NO_OP:
229 return V_028808_ROP3_NO_OP;
230 case VK_LOGIC_OP_XOR:
231 return V_028808_ROP3_XOR;
232 case VK_LOGIC_OP_OR:
233 return V_028808_ROP3_OR;
234 case VK_LOGIC_OP_NOR:
235 return V_028808_ROP3_NOR;
236 case VK_LOGIC_OP_EQUIVALENT:
237 return V_028808_ROP3_EQUIVALENT;
238 case VK_LOGIC_OP_INVERT:
239 return V_028808_ROP3_INVERT;
240 case VK_LOGIC_OP_OR_REVERSE:
241 return V_028808_ROP3_OR_REVERSE;
242 case VK_LOGIC_OP_COPY_INVERTED:
243 return V_028808_ROP3_COPY_INVERTED;
244 case VK_LOGIC_OP_OR_INVERTED:
245 return V_028808_ROP3_OR_INVERTED;
246 case VK_LOGIC_OP_NAND:
247 return V_028808_ROP3_NAND;
248 case VK_LOGIC_OP_SET:
249 return V_028808_ROP3_SET;
250 default:
251 unreachable("Unhandled logic op");
252 }
253 }
254
255
256 static uint32_t si_translate_blend_function(VkBlendOp op)
257 {
258 switch (op) {
259 case VK_BLEND_OP_ADD:
260 return V_028780_COMB_DST_PLUS_SRC;
261 case VK_BLEND_OP_SUBTRACT:
262 return V_028780_COMB_SRC_MINUS_DST;
263 case VK_BLEND_OP_REVERSE_SUBTRACT:
264 return V_028780_COMB_DST_MINUS_SRC;
265 case VK_BLEND_OP_MIN:
266 return V_028780_COMB_MIN_DST_SRC;
267 case VK_BLEND_OP_MAX:
268 return V_028780_COMB_MAX_DST_SRC;
269 default:
270 return 0;
271 }
272 }
273
274 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
275 {
276 switch (factor) {
277 case VK_BLEND_FACTOR_ZERO:
278 return V_028780_BLEND_ZERO;
279 case VK_BLEND_FACTOR_ONE:
280 return V_028780_BLEND_ONE;
281 case VK_BLEND_FACTOR_SRC_COLOR:
282 return V_028780_BLEND_SRC_COLOR;
283 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
284 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
285 case VK_BLEND_FACTOR_DST_COLOR:
286 return V_028780_BLEND_DST_COLOR;
287 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
288 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
289 case VK_BLEND_FACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
292 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
293 case VK_BLEND_FACTOR_DST_ALPHA:
294 return V_028780_BLEND_DST_ALPHA;
295 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
296 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
297 case VK_BLEND_FACTOR_CONSTANT_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
300 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
301 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
302 return V_028780_BLEND_CONSTANT_ALPHA;
303 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
304 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
305 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
306 return V_028780_BLEND_SRC_ALPHA_SATURATE;
307 case VK_BLEND_FACTOR_SRC1_COLOR:
308 return V_028780_BLEND_SRC1_COLOR;
309 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
310 return V_028780_BLEND_INV_SRC1_COLOR;
311 case VK_BLEND_FACTOR_SRC1_ALPHA:
312 return V_028780_BLEND_SRC1_ALPHA;
313 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
314 return V_028780_BLEND_INV_SRC1_ALPHA;
315 default:
316 return 0;
317 }
318 }
319
320 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
321 {
322 switch (op) {
323 case VK_BLEND_OP_ADD:
324 return V_028760_OPT_COMB_ADD;
325 case VK_BLEND_OP_SUBTRACT:
326 return V_028760_OPT_COMB_SUBTRACT;
327 case VK_BLEND_OP_REVERSE_SUBTRACT:
328 return V_028760_OPT_COMB_REVSUBTRACT;
329 case VK_BLEND_OP_MIN:
330 return V_028760_OPT_COMB_MIN;
331 case VK_BLEND_OP_MAX:
332 return V_028760_OPT_COMB_MAX;
333 default:
334 return V_028760_OPT_COMB_BLEND_DISABLED;
335 }
336 }
337
338 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
339 {
340 switch (factor) {
341 case VK_BLEND_FACTOR_ZERO:
342 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
343 case VK_BLEND_FACTOR_ONE:
344 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
345 case VK_BLEND_FACTOR_SRC_COLOR:
346 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
347 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
348 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
349 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
350 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
351 case VK_BLEND_FACTOR_SRC_ALPHA:
352 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
353 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
354 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
357 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
358 default:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
360 }
361 }
362
363 /**
364 * Get rid of DST in the blend factors by commuting the operands:
365 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
366 */
367 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
368 unsigned *dst_factor, unsigned expected_dst,
369 unsigned replacement_src)
370 {
371 if (*src_factor == expected_dst &&
372 *dst_factor == VK_BLEND_FACTOR_ZERO) {
373 *src_factor = VK_BLEND_FACTOR_ZERO;
374 *dst_factor = replacement_src;
375
376 /* Commuting the operands requires reversing subtractions. */
377 if (*func == VK_BLEND_OP_SUBTRACT)
378 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
379 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
380 *func = VK_BLEND_OP_SUBTRACT;
381 }
382 }
383
384 static bool si_blend_factor_uses_dst(unsigned factor)
385 {
386 return factor == VK_BLEND_FACTOR_DST_COLOR ||
387 factor == VK_BLEND_FACTOR_DST_ALPHA ||
388 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
389 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
390 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
391 }
392
393 static bool is_dual_src(VkBlendFactor factor)
394 {
395 switch (factor) {
396 case VK_BLEND_FACTOR_SRC1_COLOR:
397 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
398 case VK_BLEND_FACTOR_SRC1_ALPHA:
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
400 return true;
401 default:
402 return false;
403 }
404 }
405
406 static unsigned si_choose_spi_color_format(VkFormat vk_format,
407 bool blend_enable,
408 bool blend_need_alpha)
409 {
410 const struct vk_format_description *desc = vk_format_description(vk_format);
411 unsigned format, ntype, swap;
412
413 /* Alpha is needed for alpha-to-coverage.
414 * Blending may be with or without alpha.
415 */
416 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
417 unsigned alpha = 0; /* exports alpha, but may not support blending */
418 unsigned blend = 0; /* supports blending, but may not export alpha */
419 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
420
421 format = radv_translate_colorformat(vk_format);
422 ntype = radv_translate_color_numformat(vk_format, desc,
423 vk_format_get_first_non_void_channel(vk_format));
424 swap = radv_translate_colorswap(vk_format, false);
425
426 /* Choose the SPI color formats. These are required values for Stoney/RB+.
427 * Other chips have multiple choices, though they are not necessarily better.
428 */
429 switch (format) {
430 case V_028C70_COLOR_5_6_5:
431 case V_028C70_COLOR_1_5_5_5:
432 case V_028C70_COLOR_5_5_5_1:
433 case V_028C70_COLOR_4_4_4_4:
434 case V_028C70_COLOR_10_11_11:
435 case V_028C70_COLOR_11_11_10:
436 case V_028C70_COLOR_8:
437 case V_028C70_COLOR_8_8:
438 case V_028C70_COLOR_8_8_8_8:
439 case V_028C70_COLOR_10_10_10_2:
440 case V_028C70_COLOR_2_10_10_10:
441 if (ntype == V_028C70_NUMBER_UINT)
442 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
443 else if (ntype == V_028C70_NUMBER_SINT)
444 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
445 else
446 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
447 break;
448
449 case V_028C70_COLOR_16:
450 case V_028C70_COLOR_16_16:
451 case V_028C70_COLOR_16_16_16_16:
452 if (ntype == V_028C70_NUMBER_UNORM ||
453 ntype == V_028C70_NUMBER_SNORM) {
454 /* UNORM16 and SNORM16 don't support blending */
455 if (ntype == V_028C70_NUMBER_UNORM)
456 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
457 else
458 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
459
460 /* Use 32 bits per channel for blending. */
461 if (format == V_028C70_COLOR_16) {
462 if (swap == V_028C70_SWAP_STD) { /* R */
463 blend = V_028714_SPI_SHADER_32_R;
464 blend_alpha = V_028714_SPI_SHADER_32_AR;
465 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
466 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
467 else
468 assert(0);
469 } else if (format == V_028C70_COLOR_16_16) {
470 if (swap == V_028C70_SWAP_STD) { /* RG */
471 blend = V_028714_SPI_SHADER_32_GR;
472 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
473 } else if (swap == V_028C70_SWAP_ALT) /* RA */
474 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
475 else
476 assert(0);
477 } else /* 16_16_16_16 */
478 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
479 } else if (ntype == V_028C70_NUMBER_UINT)
480 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
481 else if (ntype == V_028C70_NUMBER_SINT)
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
483 else if (ntype == V_028C70_NUMBER_FLOAT)
484 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
485 else
486 assert(0);
487 break;
488
489 case V_028C70_COLOR_32:
490 if (swap == V_028C70_SWAP_STD) { /* R */
491 blend = normal = V_028714_SPI_SHADER_32_R;
492 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
493 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
494 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
495 else
496 assert(0);
497 break;
498
499 case V_028C70_COLOR_32_32:
500 if (swap == V_028C70_SWAP_STD) { /* RG */
501 blend = normal = V_028714_SPI_SHADER_32_GR;
502 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
503 } else if (swap == V_028C70_SWAP_ALT) /* RA */
504 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
505 else
506 assert(0);
507 break;
508
509 case V_028C70_COLOR_32_32_32_32:
510 case V_028C70_COLOR_8_24:
511 case V_028C70_COLOR_24_8:
512 case V_028C70_COLOR_X24_8_32_FLOAT:
513 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
514 break;
515
516 default:
517 unreachable("unhandled blend format");
518 }
519
520 if (blend_enable && blend_need_alpha)
521 return blend_alpha;
522 else if(blend_need_alpha)
523 return alpha;
524 else if(blend_enable)
525 return blend;
526 else
527 return normal;
528 }
529
530 static void
531 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
532 const VkGraphicsPipelineCreateInfo *pCreateInfo,
533 struct radv_blend_state *blend)
534 {
535 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
536 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
537 unsigned col_format = 0;
538 unsigned num_targets;
539
540 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
541 unsigned cf;
542
543 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
544 cf = V_028714_SPI_SHADER_ZERO;
545 } else {
546 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
547 bool blend_enable =
548 blend->blend_enable_4bit & (0xfu << (i * 4));
549
550 cf = si_choose_spi_color_format(attachment->format,
551 blend_enable,
552 blend->need_src_alpha & (1 << i));
553 }
554
555 col_format |= cf << (4 * i);
556 }
557
558 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
559 /* When a subpass doesn't have any color attachments, write the
560 * alpha channel of MRT0 when alpha coverage is enabled because
561 * the depth attachment needs it.
562 */
563 col_format |= V_028714_SPI_SHADER_32_AR;
564 }
565
566 /* If the i-th target format is set, all previous target formats must
567 * be non-zero to avoid hangs.
568 */
569 num_targets = (util_last_bit(col_format) + 3) / 4;
570 for (unsigned i = 0; i < num_targets; i++) {
571 if (!(col_format & (0xf << (i * 4)))) {
572 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
573 }
574 }
575
576 /* The output for dual source blending should have the same format as
577 * the first output.
578 */
579 if (blend->mrt0_is_dual_src)
580 col_format |= (col_format & 0xf) << 4;
581
582 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
583 blend->spi_shader_col_format = col_format;
584 }
585
586 static bool
587 format_is_int8(VkFormat format)
588 {
589 const struct vk_format_description *desc = vk_format_description(format);
590 int channel = vk_format_get_first_non_void_channel(format);
591
592 return channel >= 0 && desc->channel[channel].pure_integer &&
593 desc->channel[channel].size == 8;
594 }
595
596 static bool
597 format_is_int10(VkFormat format)
598 {
599 const struct vk_format_description *desc = vk_format_description(format);
600
601 if (desc->nr_channels != 4)
602 return false;
603 for (unsigned i = 0; i < 4; i++) {
604 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
605 return true;
606 }
607 return false;
608 }
609
610 /*
611 * Ordered so that for each i,
612 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
613 */
614 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
615 VK_FORMAT_R32_SFLOAT,
616 VK_FORMAT_R32G32_SFLOAT,
617 VK_FORMAT_R8G8B8A8_UNORM,
618 VK_FORMAT_R16G16B16A16_UNORM,
619 VK_FORMAT_R16G16B16A16_SNORM,
620 VK_FORMAT_R16G16B16A16_UINT,
621 VK_FORMAT_R16G16B16A16_SINT,
622 VK_FORMAT_R32G32B32A32_SFLOAT,
623 VK_FORMAT_R8G8B8A8_UINT,
624 VK_FORMAT_R8G8B8A8_SINT,
625 VK_FORMAT_A2R10G10B10_UINT_PACK32,
626 VK_FORMAT_A2R10G10B10_SINT_PACK32,
627 };
628
629 unsigned radv_format_meta_fs_key(VkFormat format)
630 {
631 unsigned col_format = si_choose_spi_color_format(format, false, false);
632
633 assert(col_format != V_028714_SPI_SHADER_32_AR);
634 if (col_format >= V_028714_SPI_SHADER_32_AR)
635 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
636
637 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
638 bool is_int8 = format_is_int8(format);
639 bool is_int10 = format_is_int10(format);
640
641 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
642 }
643
644 static void
645 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
646 unsigned *is_int8, unsigned *is_int10)
647 {
648 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
649 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
650 *is_int8 = 0;
651 *is_int10 = 0;
652
653 for (unsigned i = 0; i < subpass->color_count; ++i) {
654 struct radv_render_pass_attachment *attachment;
655
656 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
657 continue;
658
659 attachment = pass->attachments + subpass->color_attachments[i].attachment;
660
661 if (format_is_int8(attachment->format))
662 *is_int8 |= 1 << i;
663 if (format_is_int10(attachment->format))
664 *is_int10 |= 1 << i;
665 }
666 }
667
668 static void
669 radv_blend_check_commutativity(struct radv_blend_state *blend,
670 VkBlendOp op, VkBlendFactor src,
671 VkBlendFactor dst, unsigned chanmask)
672 {
673 /* Src factor is allowed when it does not depend on Dst. */
674 static const uint32_t src_allowed =
675 (1u << VK_BLEND_FACTOR_ONE) |
676 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
677 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
678 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
679 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
680 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
681 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
682 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
683 (1u << VK_BLEND_FACTOR_ZERO) |
684 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
685 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
686 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
687 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
688 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
689 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
690
691 if (dst == VK_BLEND_FACTOR_ONE &&
692 (src_allowed & (1u << src))) {
693 /* Addition is commutative, but floating point addition isn't
694 * associative: subtle changes can be introduced via different
695 * rounding. Be conservative, only enable for min and max.
696 */
697 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
698 blend->commutative_4bit |= chanmask;
699 }
700 }
701
702 static struct radv_blend_state
703 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
704 const VkGraphicsPipelineCreateInfo *pCreateInfo,
705 const struct radv_graphics_pipeline_create_info *extra)
706 {
707 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
708 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
709 struct radv_blend_state blend = {0};
710 unsigned mode = V_028808_CB_NORMAL;
711 int i;
712
713 if (!vkblend)
714 return blend;
715
716 if (extra && extra->custom_blend_mode) {
717 blend.single_cb_enable = true;
718 mode = extra->custom_blend_mode;
719 }
720 blend.cb_color_control = 0;
721 if (vkblend->logicOpEnable)
722 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
723 else
724 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
725
726 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
727 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
728 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
729 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
730 S_028B70_OFFSET_ROUND(1);
731
732 if (vkms && vkms->alphaToCoverageEnable) {
733 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
734 blend.need_src_alpha |= 0x1;
735 }
736
737 blend.cb_target_mask = 0;
738 for (i = 0; i < vkblend->attachmentCount; i++) {
739 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
740 unsigned blend_cntl = 0;
741 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
742 VkBlendOp eqRGB = att->colorBlendOp;
743 VkBlendFactor srcRGB = att->srcColorBlendFactor;
744 VkBlendFactor dstRGB = att->dstColorBlendFactor;
745 VkBlendOp eqA = att->alphaBlendOp;
746 VkBlendFactor srcA = att->srcAlphaBlendFactor;
747 VkBlendFactor dstA = att->dstAlphaBlendFactor;
748
749 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
750
751 if (!att->colorWriteMask)
752 continue;
753
754 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
755 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
756 if (!att->blendEnable) {
757 blend.cb_blend_control[i] = blend_cntl;
758 continue;
759 }
760
761 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
762 if (i == 0)
763 blend.mrt0_is_dual_src = true;
764
765 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
766 srcRGB = VK_BLEND_FACTOR_ONE;
767 dstRGB = VK_BLEND_FACTOR_ONE;
768 }
769 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
770 srcA = VK_BLEND_FACTOR_ONE;
771 dstA = VK_BLEND_FACTOR_ONE;
772 }
773
774 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
775 0x7 << (4 * i));
776 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
777 0x8 << (4 * i));
778
779 /* Blending optimizations for RB+.
780 * These transformations don't change the behavior.
781 *
782 * First, get rid of DST in the blend factors:
783 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
784 */
785 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
786 VK_BLEND_FACTOR_DST_COLOR,
787 VK_BLEND_FACTOR_SRC_COLOR);
788
789 si_blend_remove_dst(&eqA, &srcA, &dstA,
790 VK_BLEND_FACTOR_DST_COLOR,
791 VK_BLEND_FACTOR_SRC_COLOR);
792
793 si_blend_remove_dst(&eqA, &srcA, &dstA,
794 VK_BLEND_FACTOR_DST_ALPHA,
795 VK_BLEND_FACTOR_SRC_ALPHA);
796
797 /* Look up the ideal settings from tables. */
798 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
799 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
800 srcA_opt = si_translate_blend_opt_factor(srcA, true);
801 dstA_opt = si_translate_blend_opt_factor(dstA, true);
802
803 /* Handle interdependencies. */
804 if (si_blend_factor_uses_dst(srcRGB))
805 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
806 if (si_blend_factor_uses_dst(srcA))
807 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
808
809 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
810 (dstRGB == VK_BLEND_FACTOR_ZERO ||
811 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
812 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
813 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
814
815 /* Set the final value. */
816 blend.sx_mrt_blend_opt[i] =
817 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
818 S_028760_COLOR_DST_OPT(dstRGB_opt) |
819 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
820 S_028760_ALPHA_SRC_OPT(srcA_opt) |
821 S_028760_ALPHA_DST_OPT(dstA_opt) |
822 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
823 blend_cntl |= S_028780_ENABLE(1);
824
825 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
826 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
827 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
828 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
829 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
830 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
831 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
832 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
833 }
834 blend.cb_blend_control[i] = blend_cntl;
835
836 blend.blend_enable_4bit |= 0xfu << (i * 4);
837
838 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
839 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
840 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
841 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
842 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
843 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
844 blend.need_src_alpha |= 1 << i;
845 }
846 for (i = vkblend->attachmentCount; i < 8; i++) {
847 blend.cb_blend_control[i] = 0;
848 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
849 }
850
851 if (pipeline->device->physical_device->rad_info.has_rbplus) {
852 /* Disable RB+ blend optimizations for dual source blending. */
853 if (blend.mrt0_is_dual_src) {
854 for (i = 0; i < 8; i++) {
855 blend.sx_mrt_blend_opt[i] =
856 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
857 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
858 }
859 }
860
861 /* RB+ doesn't work with dual source blending, logic op and
862 * RESOLVE.
863 */
864 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
865 mode == V_028808_CB_RESOLVE)
866 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
867 }
868
869 if (blend.cb_target_mask)
870 blend.cb_color_control |= S_028808_MODE(mode);
871 else
872 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
873
874 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
875 return blend;
876 }
877
878 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
879 {
880 switch (op) {
881 case VK_STENCIL_OP_KEEP:
882 return V_02842C_STENCIL_KEEP;
883 case VK_STENCIL_OP_ZERO:
884 return V_02842C_STENCIL_ZERO;
885 case VK_STENCIL_OP_REPLACE:
886 return V_02842C_STENCIL_REPLACE_TEST;
887 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
888 return V_02842C_STENCIL_ADD_CLAMP;
889 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
890 return V_02842C_STENCIL_SUB_CLAMP;
891 case VK_STENCIL_OP_INVERT:
892 return V_02842C_STENCIL_INVERT;
893 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
894 return V_02842C_STENCIL_ADD_WRAP;
895 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
896 return V_02842C_STENCIL_SUB_WRAP;
897 default:
898 return 0;
899 }
900 }
901
902 static uint32_t si_translate_fill(VkPolygonMode func)
903 {
904 switch(func) {
905 case VK_POLYGON_MODE_FILL:
906 return V_028814_X_DRAW_TRIANGLES;
907 case VK_POLYGON_MODE_LINE:
908 return V_028814_X_DRAW_LINES;
909 case VK_POLYGON_MODE_POINT:
910 return V_028814_X_DRAW_POINTS;
911 default:
912 assert(0);
913 return V_028814_X_DRAW_POINTS;
914 }
915 }
916
917 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
918 {
919 uint32_t num_samples = vkms->rasterizationSamples;
920 uint32_t ps_iter_samples = 1;
921
922 if (vkms->sampleShadingEnable) {
923 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
924 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
925 }
926 return ps_iter_samples;
927 }
928
929 static bool
930 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
931 {
932 return pCreateInfo->depthTestEnable &&
933 pCreateInfo->depthWriteEnable &&
934 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
935 }
936
937 static bool
938 radv_writes_stencil(const VkStencilOpState *state)
939 {
940 return state->writeMask &&
941 (state->failOp != VK_STENCIL_OP_KEEP ||
942 state->passOp != VK_STENCIL_OP_KEEP ||
943 state->depthFailOp != VK_STENCIL_OP_KEEP);
944 }
945
946 static bool
947 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
948 {
949 return pCreateInfo->stencilTestEnable &&
950 (radv_writes_stencil(&pCreateInfo->front) ||
951 radv_writes_stencil(&pCreateInfo->back));
952 }
953
954 static bool
955 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
956 {
957 return radv_is_depth_write_enabled(pCreateInfo) ||
958 radv_is_stencil_write_enabled(pCreateInfo);
959 }
960
961 static bool
962 radv_order_invariant_stencil_op(VkStencilOp op)
963 {
964 /* REPLACE is normally order invariant, except when the stencil
965 * reference value is written by the fragment shader. Tracking this
966 * interaction does not seem worth the effort, so be conservative.
967 */
968 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
969 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
970 op != VK_STENCIL_OP_REPLACE;
971 }
972
973 static bool
974 radv_order_invariant_stencil_state(const VkStencilOpState *state)
975 {
976 /* Compute whether, assuming Z writes are disabled, this stencil state
977 * is order invariant in the sense that the set of passing fragments as
978 * well as the final stencil buffer result does not depend on the order
979 * of fragments.
980 */
981 return !state->writeMask ||
982 /* The following assumes that Z writes are disabled. */
983 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
984 radv_order_invariant_stencil_op(state->passOp) &&
985 radv_order_invariant_stencil_op(state->depthFailOp)) ||
986 (state->compareOp == VK_COMPARE_OP_NEVER &&
987 radv_order_invariant_stencil_op(state->failOp));
988 }
989
990 static bool
991 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
992 struct radv_blend_state *blend,
993 const VkGraphicsPipelineCreateInfo *pCreateInfo)
994 {
995 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
996 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
997 unsigned colormask = blend->cb_target_enabled_4bit;
998
999 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1000 return false;
1001
1002 /* Be conservative if a logic operation is enabled with color buffers. */
1003 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1004 return false;
1005
1006 /* Default depth/stencil invariance when no attachment is bound. */
1007 struct radv_dsa_order_invariance dsa_order_invariant = {
1008 .zs = true, .pass_set = true
1009 };
1010
1011 if (pCreateInfo->pDepthStencilState &&
1012 subpass->depth_stencil_attachment) {
1013 const VkPipelineDepthStencilStateCreateInfo *vkds =
1014 pCreateInfo->pDepthStencilState;
1015 struct radv_render_pass_attachment *attachment =
1016 pass->attachments + subpass->depth_stencil_attachment->attachment;
1017 bool has_stencil = vk_format_is_stencil(attachment->format);
1018 struct radv_dsa_order_invariance order_invariance[2];
1019 struct radv_shader_variant *ps =
1020 pipeline->shaders[MESA_SHADER_FRAGMENT];
1021
1022 /* Compute depth/stencil order invariance in order to know if
1023 * it's safe to enable out-of-order.
1024 */
1025 bool zfunc_is_ordered =
1026 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1027 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1028 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1029 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1030 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1031
1032 bool nozwrite_and_order_invariant_stencil =
1033 !radv_is_ds_write_enabled(vkds) ||
1034 (!radv_is_depth_write_enabled(vkds) &&
1035 radv_order_invariant_stencil_state(&vkds->front) &&
1036 radv_order_invariant_stencil_state(&vkds->back));
1037
1038 order_invariance[1].zs =
1039 nozwrite_and_order_invariant_stencil ||
1040 (!radv_is_stencil_write_enabled(vkds) &&
1041 zfunc_is_ordered);
1042 order_invariance[0].zs =
1043 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1044
1045 order_invariance[1].pass_set =
1046 nozwrite_and_order_invariant_stencil ||
1047 (!radv_is_stencil_write_enabled(vkds) &&
1048 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1049 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1050 order_invariance[0].pass_set =
1051 !radv_is_depth_write_enabled(vkds) ||
1052 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1053 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1054
1055 dsa_order_invariant = order_invariance[has_stencil];
1056 if (!dsa_order_invariant.zs)
1057 return false;
1058
1059 /* The set of PS invocations is always order invariant,
1060 * except when early Z/S tests are requested.
1061 */
1062 if (ps &&
1063 ps->info.ps.writes_memory &&
1064 ps->info.ps.early_fragment_test &&
1065 !dsa_order_invariant.pass_set)
1066 return false;
1067
1068 /* Determine if out-of-order rasterization should be disabled
1069 * when occlusion queries are used.
1070 */
1071 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1072 !dsa_order_invariant.pass_set;
1073 }
1074
1075 /* No color buffers are enabled for writing. */
1076 if (!colormask)
1077 return true;
1078
1079 unsigned blendmask = colormask & blend->blend_enable_4bit;
1080
1081 if (blendmask) {
1082 /* Only commutative blending. */
1083 if (blendmask & ~blend->commutative_4bit)
1084 return false;
1085
1086 if (!dsa_order_invariant.pass_set)
1087 return false;
1088 }
1089
1090 if (colormask & ~blendmask)
1091 return false;
1092
1093 return true;
1094 }
1095
1096 static void
1097 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1098 struct radv_blend_state *blend,
1099 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1100 {
1101 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1102 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1103 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1104 bool out_of_order_rast = false;
1105 int ps_iter_samples = 1;
1106 uint32_t mask = 0xffff;
1107
1108 if (vkms)
1109 ms->num_samples = vkms->rasterizationSamples;
1110 else
1111 ms->num_samples = 1;
1112
1113 if (vkms)
1114 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1115 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1116 ps_iter_samples = ms->num_samples;
1117 }
1118
1119 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1120 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1121 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1122 /* Out-of-order rasterization is explicitly enabled by the
1123 * application.
1124 */
1125 out_of_order_rast = true;
1126 } else {
1127 /* Determine if the driver can enable out-of-order
1128 * rasterization internally.
1129 */
1130 out_of_order_rast =
1131 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1132 }
1133
1134 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1135 ms->pa_sc_aa_config = 0;
1136 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1137 S_028804_INCOHERENT_EQAA_READS(1) |
1138 S_028804_INTERPOLATE_COMP_Z(1) |
1139 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1140 ms->pa_sc_mode_cntl_1 =
1141 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1142 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1143 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1144 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1145 /* always 1: */
1146 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1147 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1148 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1149 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1150 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1151 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1152 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1153 S_028A48_VPORT_SCISSOR_ENABLE(1);
1154
1155 if (ms->num_samples > 1) {
1156 unsigned log_samples = util_logbase2(ms->num_samples);
1157 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1158 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1159 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1160 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1161 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1162 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1163 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1164 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1165 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1166 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1167 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1168 if (ps_iter_samples > 1)
1169 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1170 }
1171
1172 if (vkms && vkms->pSampleMask) {
1173 mask = vkms->pSampleMask[0] & 0xffff;
1174 }
1175
1176 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1177 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1178 }
1179
1180 static bool
1181 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1182 {
1183 switch (topology) {
1184 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1189 return false;
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1195 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1196 return true;
1197 default:
1198 unreachable("unhandled primitive type");
1199 }
1200 }
1201
1202 static uint32_t
1203 si_translate_prim(enum VkPrimitiveTopology topology)
1204 {
1205 switch (topology) {
1206 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1207 return V_008958_DI_PT_POINTLIST;
1208 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1209 return V_008958_DI_PT_LINELIST;
1210 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1211 return V_008958_DI_PT_LINESTRIP;
1212 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1213 return V_008958_DI_PT_TRILIST;
1214 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1215 return V_008958_DI_PT_TRISTRIP;
1216 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1217 return V_008958_DI_PT_TRIFAN;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1219 return V_008958_DI_PT_LINELIST_ADJ;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1221 return V_008958_DI_PT_LINESTRIP_ADJ;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1223 return V_008958_DI_PT_TRILIST_ADJ;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1225 return V_008958_DI_PT_TRISTRIP_ADJ;
1226 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1227 return V_008958_DI_PT_PATCH;
1228 default:
1229 assert(0);
1230 return 0;
1231 }
1232 }
1233
1234 static uint32_t
1235 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1236 {
1237 switch (gl_prim) {
1238 case 0: /* GL_POINTS */
1239 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1240 case 1: /* GL_LINES */
1241 case 3: /* GL_LINE_STRIP */
1242 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1243 case 0x8E7A: /* GL_ISOLINES */
1244 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1245
1246 case 4: /* GL_TRIANGLES */
1247 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1248 case 5: /* GL_TRIANGLE_STRIP */
1249 case 7: /* GL_QUADS */
1250 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1251 default:
1252 assert(0);
1253 return 0;
1254 }
1255 }
1256
1257 static uint32_t
1258 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1259 {
1260 switch (topology) {
1261 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1262 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1263 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1264 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1265 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1266 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1267 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1268 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1269 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1270 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1273 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1274 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1275 default:
1276 assert(0);
1277 return 0;
1278 }
1279 }
1280
1281 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1282 {
1283 switch(state) {
1284 case VK_DYNAMIC_STATE_VIEWPORT:
1285 return RADV_DYNAMIC_VIEWPORT;
1286 case VK_DYNAMIC_STATE_SCISSOR:
1287 return RADV_DYNAMIC_SCISSOR;
1288 case VK_DYNAMIC_STATE_LINE_WIDTH:
1289 return RADV_DYNAMIC_LINE_WIDTH;
1290 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1291 return RADV_DYNAMIC_DEPTH_BIAS;
1292 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1293 return RADV_DYNAMIC_BLEND_CONSTANTS;
1294 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1295 return RADV_DYNAMIC_DEPTH_BOUNDS;
1296 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1297 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1298 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1299 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1300 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1301 return RADV_DYNAMIC_STENCIL_REFERENCE;
1302 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1303 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1304 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1305 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1306 default:
1307 unreachable("Unhandled dynamic state");
1308 }
1309 }
1310
1311 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1312 {
1313 uint32_t states = RADV_DYNAMIC_ALL;
1314
1315 /* If rasterization is disabled we do not care about any of the dynamic states,
1316 * since they are all rasterization related only. */
1317 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1318 return 0;
1319
1320 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1321 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1322
1323 if (!pCreateInfo->pDepthStencilState ||
1324 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1325 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1326
1327 if (!pCreateInfo->pDepthStencilState ||
1328 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1329 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1330 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1331 RADV_DYNAMIC_STENCIL_REFERENCE);
1332
1333 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1334 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1335
1336 if (!pCreateInfo->pMultisampleState ||
1337 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1338 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1339 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1340
1341 /* TODO: blend constants & line width. */
1342
1343 return states;
1344 }
1345
1346
1347 static void
1348 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1349 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1350 {
1351 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1352 uint32_t states = needed_states;
1353 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1354 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1355
1356 pipeline->dynamic_state = default_dynamic_state;
1357 pipeline->graphics.needed_dynamic_state = needed_states;
1358
1359 if (pCreateInfo->pDynamicState) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1362 for (uint32_t s = 0; s < count; s++)
1363 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1364 }
1365
1366 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1367
1368 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1369 assert(pCreateInfo->pViewportState);
1370
1371 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1372 if (states & RADV_DYNAMIC_VIEWPORT) {
1373 typed_memcpy(dynamic->viewport.viewports,
1374 pCreateInfo->pViewportState->pViewports,
1375 pCreateInfo->pViewportState->viewportCount);
1376 }
1377 }
1378
1379 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1380 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1381 if (states & RADV_DYNAMIC_SCISSOR) {
1382 typed_memcpy(dynamic->scissor.scissors,
1383 pCreateInfo->pViewportState->pScissors,
1384 pCreateInfo->pViewportState->scissorCount);
1385 }
1386 }
1387
1388 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1389 assert(pCreateInfo->pRasterizationState);
1390 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1391 }
1392
1393 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1394 assert(pCreateInfo->pRasterizationState);
1395 dynamic->depth_bias.bias =
1396 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1397 dynamic->depth_bias.clamp =
1398 pCreateInfo->pRasterizationState->depthBiasClamp;
1399 dynamic->depth_bias.slope =
1400 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1401 }
1402
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 *
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1408 */
1409 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1410 assert(pCreateInfo->pColorBlendState);
1411 typed_memcpy(dynamic->blend_constants,
1412 pCreateInfo->pColorBlendState->blendConstants, 4);
1413 }
1414
1415 /* If there is no depthstencil attachment, then don't read
1416 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1417 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1418 * no need to override the depthstencil defaults in
1419 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1420 *
1421 * Section 9.2 of the Vulkan 1.0.15 spec says:
1422 *
1423 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1424 * disabled or if the subpass of the render pass the pipeline is created
1425 * against does not use a depth/stencil attachment.
1426 */
1427 if (needed_states && subpass->depth_stencil_attachment) {
1428 assert(pCreateInfo->pDepthStencilState);
1429
1430 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1431 dynamic->depth_bounds.min =
1432 pCreateInfo->pDepthStencilState->minDepthBounds;
1433 dynamic->depth_bounds.max =
1434 pCreateInfo->pDepthStencilState->maxDepthBounds;
1435 }
1436
1437 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1438 dynamic->stencil_compare_mask.front =
1439 pCreateInfo->pDepthStencilState->front.compareMask;
1440 dynamic->stencil_compare_mask.back =
1441 pCreateInfo->pDepthStencilState->back.compareMask;
1442 }
1443
1444 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1445 dynamic->stencil_write_mask.front =
1446 pCreateInfo->pDepthStencilState->front.writeMask;
1447 dynamic->stencil_write_mask.back =
1448 pCreateInfo->pDepthStencilState->back.writeMask;
1449 }
1450
1451 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1452 dynamic->stencil_reference.front =
1453 pCreateInfo->pDepthStencilState->front.reference;
1454 dynamic->stencil_reference.back =
1455 pCreateInfo->pDepthStencilState->back.reference;
1456 }
1457 }
1458
1459 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1460 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1461 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1462 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1463 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1464 typed_memcpy(dynamic->discard_rectangle.rectangles,
1465 discard_rectangle_info->pDiscardRectangles,
1466 discard_rectangle_info->discardRectangleCount);
1467 }
1468 }
1469
1470 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1471 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1472 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1473 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1474 /* If sampleLocationsEnable is VK_FALSE, the default sample
1475 * locations are used and the values specified in
1476 * sampleLocationsInfo are ignored.
1477 */
1478 if (sample_location_info->sampleLocationsEnable) {
1479 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1480 &sample_location_info->sampleLocationsInfo;
1481
1482 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1483
1484 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1485 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1486 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1487 typed_memcpy(&dynamic->sample_location.locations[0],
1488 pSampleLocationsInfo->pSampleLocations,
1489 pSampleLocationsInfo->sampleLocationsCount);
1490 }
1491 }
1492
1493 pipeline->dynamic_state.mask = states;
1494 }
1495
1496 static void
1497 gfx9_get_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1498 const struct radv_pipeline *pipeline,
1499 struct gfx9_gs_info *out)
1500 {
1501 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1502 struct radv_es_output_info *es_info;
1503 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1504 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1505 else
1506 es_info = radv_pipeline_has_tess(pipeline) ?
1507 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1508 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1509
1510 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1511 bool uses_adjacency;
1512 switch(pCreateInfo->pInputAssemblyState->topology) {
1513 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1514 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1515 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1516 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1517 uses_adjacency = true;
1518 break;
1519 default:
1520 uses_adjacency = false;
1521 break;
1522 }
1523
1524 /* All these are in dwords: */
1525 /* We can't allow using the whole LDS, because GS waves compete with
1526 * other shader stages for LDS space. */
1527 const unsigned max_lds_size = 8 * 1024;
1528 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1529 unsigned esgs_lds_size;
1530
1531 /* All these are per subgroup: */
1532 const unsigned max_out_prims = 32 * 1024;
1533 const unsigned max_es_verts = 255;
1534 const unsigned ideal_gs_prims = 64;
1535 unsigned max_gs_prims, gs_prims;
1536 unsigned min_es_verts, es_verts, worst_case_es_verts;
1537
1538 if (uses_adjacency || gs_num_invocations > 1)
1539 max_gs_prims = 127 / gs_num_invocations;
1540 else
1541 max_gs_prims = 255;
1542
1543 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1544 * Make sure we don't go over the maximum value.
1545 */
1546 if (gs_info->gs.vertices_out > 0) {
1547 max_gs_prims = MIN2(max_gs_prims,
1548 max_out_prims /
1549 (gs_info->gs.vertices_out * gs_num_invocations));
1550 }
1551 assert(max_gs_prims > 0);
1552
1553 /* If the primitive has adjacency, halve the number of vertices
1554 * that will be reused in multiple primitives.
1555 */
1556 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1557
1558 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1559 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1560
1561 /* Compute ESGS LDS size based on the worst case number of ES vertices
1562 * needed to create the target number of GS prims per subgroup.
1563 */
1564 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1565
1566 /* If total LDS usage is too big, refactor partitions based on ratio
1567 * of ESGS item sizes.
1568 */
1569 if (esgs_lds_size > max_lds_size) {
1570 /* Our target GS Prims Per Subgroup was too large. Calculate
1571 * the maximum number of GS Prims Per Subgroup that will fit
1572 * into LDS, capped by the maximum that the hardware can support.
1573 */
1574 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1575 max_gs_prims);
1576 assert(gs_prims > 0);
1577 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1578 max_es_verts);
1579
1580 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1581 assert(esgs_lds_size <= max_lds_size);
1582 }
1583
1584 /* Now calculate remaining ESGS information. */
1585 if (esgs_lds_size)
1586 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1587 else
1588 es_verts = max_es_verts;
1589
1590 /* Vertices for adjacency primitives are not always reused, so restore
1591 * it for ES_VERTS_PER_SUBGRP.
1592 */
1593 min_es_verts = gs_info->gs.vertices_in;
1594
1595 /* For normal primitives, the VGT only checks if they are past the ES
1596 * verts per subgroup after allocating a full GS primitive and if they
1597 * are, kick off a new subgroup. But if those additional ES verts are
1598 * unique (e.g. not reused) we need to make sure there is enough LDS
1599 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1600 */
1601 es_verts -= min_es_verts - 1;
1602
1603 uint32_t es_verts_per_subgroup = es_verts;
1604 uint32_t gs_prims_per_subgroup = gs_prims;
1605 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1606 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1607 out->lds_size = align(esgs_lds_size, 128) / 128;
1608 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1609 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1610 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1611 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1612 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1613 assert(max_prims_per_subgroup <= max_out_prims);
1614 }
1615
1616 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1617 unsigned min_verts_per_prim, bool use_adjacency)
1618 {
1619 unsigned max_reuse = max_esverts - min_verts_per_prim;
1620 if (use_adjacency)
1621 max_reuse /= 2;
1622 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1623 }
1624
1625 static unsigned
1626 radv_get_num_input_vertices(struct radv_pipeline *pipeline)
1627 {
1628 if (radv_pipeline_has_gs(pipeline)) {
1629 struct radv_shader_variant *gs =
1630 radv_get_shader(pipeline, MESA_SHADER_GEOMETRY);
1631
1632 return gs->info.gs.vertices_in;
1633 }
1634
1635 if (radv_pipeline_has_tess(pipeline)) {
1636 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1637
1638 if (tes->info.tes.point_mode)
1639 return 1;
1640 if (tes->info.tes.primitive_mode == GL_ISOLINES)
1641 return 2;
1642 return 3;
1643 }
1644
1645 return 3;
1646 }
1647
1648 static void
1649 gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1650 struct radv_pipeline *pipeline,
1651 struct gfx10_ngg_info *ngg)
1652 {
1653 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1654 struct radv_es_output_info *es_info =
1655 radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1656 unsigned gs_type = radv_pipeline_has_gs(pipeline) ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1657 unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
1658 unsigned min_verts_per_prim =
1659 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1660 unsigned gs_num_invocations = radv_pipeline_has_gs(pipeline) ? MAX2(gs_info->gs.invocations, 1) : 1;
1661 bool uses_adjacency;
1662 switch(pCreateInfo->pInputAssemblyState->topology) {
1663 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1664 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1665 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1666 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1667 uses_adjacency = true;
1668 break;
1669 default:
1670 uses_adjacency = false;
1671 break;
1672 }
1673
1674 /* All these are in dwords: */
1675 /* We can't allow using the whole LDS, because GS waves compete with
1676 * other shader stages for LDS space.
1677 *
1678 * Streamout can increase the ESGS buffer size later on, so be more
1679 * conservative with streamout and use 4K dwords. This may be suboptimal.
1680 *
1681 * Otherwise, use the limit of 7K dwords. The reason is that we need
1682 * to leave some headroom for the max_esverts increase at the end.
1683 *
1684 * TODO: We should really take the shader's internal LDS use into
1685 * account. The linker will fail if the size is greater than
1686 * 8K dwords.
1687 */
1688 const unsigned max_lds_size = (0 /*gs_info->info.so.num_outputs*/ ? 4 : 7) * 1024 - 128;
1689 const unsigned target_lds_size = max_lds_size;
1690 unsigned esvert_lds_size = 0;
1691 unsigned gsprim_lds_size = 0;
1692
1693 /* All these are per subgroup: */
1694 bool max_vert_out_per_gs_instance = false;
1695 unsigned max_esverts_base = 256;
1696 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1697
1698 /* Hardware has the following non-natural restrictions on the value
1699 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1700 * the draw:
1701 * - at most 252 for any line input primitive type
1702 * - at most 251 for any quad input primitive type
1703 * - at most 251 for triangle strips with adjacency (this happens to
1704 * be the natural limit for triangle *lists* with adjacency)
1705 */
1706 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1707
1708 if (gs_type == MESA_SHADER_GEOMETRY) {
1709 unsigned max_out_verts_per_gsprim =
1710 gs_info->gs.vertices_out * gs_num_invocations;
1711
1712 if (max_out_verts_per_gsprim <= 256) {
1713 if (max_out_verts_per_gsprim) {
1714 max_gsprims_base = MIN2(max_gsprims_base,
1715 256 / max_out_verts_per_gsprim);
1716 }
1717 } else {
1718 /* Use special multi-cycling mode in which each GS
1719 * instance gets its own subgroup. Does not work with
1720 * tessellation. */
1721 max_vert_out_per_gs_instance = true;
1722 max_gsprims_base = 1;
1723 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1724 }
1725
1726 esvert_lds_size = es_info->esgs_itemsize / 4;
1727 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1728 } else {
1729 /* TODO: This needs to be adjusted once LDS use for compaction
1730 * after culling is implemented. */
1731 /*
1732 if (es_info->info.so.num_outputs)
1733 esvert_lds_size = 4 * es_info->info.so.num_outputs + 1;
1734 */
1735
1736 /* LDS size for passing data from GS to ES.
1737 * GS stores Primitive IDs (one DWORD) into LDS at the address
1738 * corresponding to the ES thread of the provoking vertex. All
1739 * ES threads load and export PrimitiveID for their thread.
1740 */
1741 if (!radv_pipeline_has_tess(pipeline) &&
1742 pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.export_prim_id)
1743 esvert_lds_size = MAX2(esvert_lds_size, 1);
1744 }
1745
1746 unsigned max_gsprims = max_gsprims_base;
1747 unsigned max_esverts = max_esverts_base;
1748
1749 if (esvert_lds_size)
1750 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1751 if (gsprim_lds_size)
1752 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1753
1754 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1755 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1756 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1757
1758 if (esvert_lds_size || gsprim_lds_size) {
1759 /* Now that we have a rough proportionality between esverts
1760 * and gsprims based on the primitive type, scale both of them
1761 * down simultaneously based on required LDS space.
1762 *
1763 * We could be smarter about this if we knew how much vertex
1764 * reuse to expect.
1765 */
1766 unsigned lds_total = max_esverts * esvert_lds_size +
1767 max_gsprims * gsprim_lds_size;
1768 if (lds_total > target_lds_size) {
1769 max_esverts = max_esverts * target_lds_size / lds_total;
1770 max_gsprims = max_gsprims * target_lds_size / lds_total;
1771
1772 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1773 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1774 min_verts_per_prim, uses_adjacency);
1775 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1776 }
1777 }
1778
1779 /* Round up towards full wave sizes for better ALU utilization. */
1780 if (!max_vert_out_per_gs_instance) {
1781 const unsigned wavesize = pipeline->device->physical_device->ge_wave_size;
1782 unsigned orig_max_esverts;
1783 unsigned orig_max_gsprims;
1784 do {
1785 orig_max_esverts = max_esverts;
1786 orig_max_gsprims = max_gsprims;
1787
1788 max_esverts = align(max_esverts, wavesize);
1789 max_esverts = MIN2(max_esverts, max_esverts_base);
1790 if (esvert_lds_size)
1791 max_esverts = MIN2(max_esverts,
1792 (max_lds_size - max_gsprims * gsprim_lds_size) /
1793 esvert_lds_size);
1794 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1795
1796 max_gsprims = align(max_gsprims, wavesize);
1797 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1798 if (gsprim_lds_size)
1799 max_gsprims = MIN2(max_gsprims,
1800 (max_lds_size - max_esverts * esvert_lds_size) /
1801 gsprim_lds_size);
1802 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1803 min_verts_per_prim, uses_adjacency);
1804 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1805 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1806 }
1807
1808 /* Hardware restriction: minimum value of max_esverts */
1809 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1810
1811 unsigned max_out_vertices =
1812 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1813 gs_type == MESA_SHADER_GEOMETRY ?
1814 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1815 max_esverts;
1816 assert(max_out_vertices <= 256);
1817
1818 unsigned prim_amp_factor = 1;
1819 if (gs_type == MESA_SHADER_GEOMETRY) {
1820 /* Number of output primitives per GS input primitive after
1821 * GS instancing. */
1822 prim_amp_factor = gs_info->gs.vertices_out;
1823 }
1824
1825 /* The GE only checks against the maximum number of ES verts after
1826 * allocating a full GS primitive. So we need to ensure that whenever
1827 * this check passes, there is enough space for a full primitive without
1828 * vertex reuse.
1829 */
1830 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1831 ngg->max_gsprims = max_gsprims;
1832 ngg->max_out_verts = max_out_vertices;
1833 ngg->prim_amp_factor = prim_amp_factor;
1834 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1835 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1836 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1837
1838 if (gs_type == MESA_SHADER_GEOMETRY) {
1839 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1840 } else {
1841 ngg->vgt_esgs_ring_itemsize = 1;
1842 }
1843
1844 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1845
1846 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1847 }
1848
1849 static void
1850 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1851 const struct gfx9_gs_info *gs)
1852 {
1853 struct radv_device *device = pipeline->device;
1854 unsigned num_se = device->physical_device->rad_info.max_se;
1855 unsigned wave_size = 64;
1856 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1857 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1858 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1859 */
1860 unsigned gs_vertex_reuse =
1861 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1862 unsigned alignment = 256 * num_se;
1863 /* The maximum size is 63.999 MB per SE. */
1864 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1865 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1866
1867 /* Calculate the minimum size. */
1868 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1869 wave_size, alignment);
1870 /* These are recommended sizes, not minimum sizes. */
1871 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1872 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1873 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1874 gs_info->gs.max_gsvs_emit_size;
1875
1876 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1877 esgs_ring_size = align(esgs_ring_size, alignment);
1878 gsvs_ring_size = align(gsvs_ring_size, alignment);
1879
1880 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1881 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1882
1883 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1884 }
1885
1886 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1887 unsigned *lds_size)
1888 {
1889 /* If tessellation is all offchip and on-chip GS isn't used, this
1890 * workaround is not needed.
1891 */
1892 return;
1893
1894 /* SPI barrier management bug:
1895 * Make sure we have at least 4k of LDS in use to avoid the bug.
1896 * It applies to workgroup sizes of more than one wavefront.
1897 */
1898 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1899 device->physical_device->rad_info.family == CHIP_KABINI)
1900 *lds_size = MAX2(*lds_size, 8);
1901 }
1902
1903 struct radv_shader_variant *
1904 radv_get_shader(struct radv_pipeline *pipeline,
1905 gl_shader_stage stage)
1906 {
1907 if (stage == MESA_SHADER_VERTEX) {
1908 if (pipeline->shaders[MESA_SHADER_VERTEX])
1909 return pipeline->shaders[MESA_SHADER_VERTEX];
1910 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1911 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1912 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1913 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1914 } else if (stage == MESA_SHADER_TESS_EVAL) {
1915 if (!radv_pipeline_has_tess(pipeline))
1916 return NULL;
1917 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1918 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1919 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1920 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1921 }
1922 return pipeline->shaders[stage];
1923 }
1924
1925 static struct radv_tessellation_state
1926 calculate_tess_state(struct radv_pipeline *pipeline,
1927 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1928 {
1929 unsigned num_tcs_input_cp;
1930 unsigned num_tcs_output_cp;
1931 unsigned lds_size;
1932 unsigned num_patches;
1933 struct radv_tessellation_state tess = {0};
1934
1935 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1936 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1937 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1938
1939 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1940
1941 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1942 assert(lds_size <= 65536);
1943 lds_size = align(lds_size, 512) / 512;
1944 } else {
1945 assert(lds_size <= 32768);
1946 lds_size = align(lds_size, 256) / 256;
1947 }
1948 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1949
1950 tess.lds_size = lds_size;
1951
1952 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1953 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1954 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1955 tess.num_patches = num_patches;
1956
1957 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1958 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1959
1960 switch (tes->info.tes.primitive_mode) {
1961 case GL_TRIANGLES:
1962 type = V_028B6C_TESS_TRIANGLE;
1963 break;
1964 case GL_QUADS:
1965 type = V_028B6C_TESS_QUAD;
1966 break;
1967 case GL_ISOLINES:
1968 type = V_028B6C_TESS_ISOLINE;
1969 break;
1970 }
1971
1972 switch (tes->info.tes.spacing) {
1973 case TESS_SPACING_EQUAL:
1974 partitioning = V_028B6C_PART_INTEGER;
1975 break;
1976 case TESS_SPACING_FRACTIONAL_ODD:
1977 partitioning = V_028B6C_PART_FRAC_ODD;
1978 break;
1979 case TESS_SPACING_FRACTIONAL_EVEN:
1980 partitioning = V_028B6C_PART_FRAC_EVEN;
1981 break;
1982 default:
1983 break;
1984 }
1985
1986 bool ccw = tes->info.tes.ccw;
1987 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1988 vk_find_struct_const(pCreateInfo->pTessellationState,
1989 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
1990
1991 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
1992 ccw = !ccw;
1993
1994 if (tes->info.tes.point_mode)
1995 topology = V_028B6C_OUTPUT_POINT;
1996 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1997 topology = V_028B6C_OUTPUT_LINE;
1998 else if (ccw)
1999 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2000 else
2001 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2002
2003 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2004 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2005 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2006 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2007 else
2008 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2009 } else
2010 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2011
2012 tess.tf_param = S_028B6C_TYPE(type) |
2013 S_028B6C_PARTITIONING(partitioning) |
2014 S_028B6C_TOPOLOGY(topology) |
2015 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2016
2017 return tess;
2018 }
2019
2020 static const struct radv_prim_vertex_count prim_size_table[] = {
2021 [V_008958_DI_PT_NONE] = {0, 0},
2022 [V_008958_DI_PT_POINTLIST] = {1, 1},
2023 [V_008958_DI_PT_LINELIST] = {2, 2},
2024 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2025 [V_008958_DI_PT_TRILIST] = {3, 3},
2026 [V_008958_DI_PT_TRIFAN] = {3, 1},
2027 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2028 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2029 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2030 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2031 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2032 [V_008958_DI_PT_RECTLIST] = {3, 3},
2033 [V_008958_DI_PT_LINELOOP] = {2, 1},
2034 [V_008958_DI_PT_POLYGON] = {3, 1},
2035 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2036 };
2037
2038 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2039 {
2040 if (radv_pipeline_has_gs(pipeline))
2041 if (radv_pipeline_has_ngg(pipeline))
2042 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2043 else
2044 return &pipeline->gs_copy_shader->info.vs.outinfo;
2045 else if (radv_pipeline_has_tess(pipeline))
2046 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2047 else
2048 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2049 }
2050
2051 static void
2052 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2053 {
2054 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2055 int shader_count = 0;
2056
2057 if(shaders[MESA_SHADER_FRAGMENT]) {
2058 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2059 }
2060 if(shaders[MESA_SHADER_GEOMETRY]) {
2061 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2062 }
2063 if(shaders[MESA_SHADER_TESS_EVAL]) {
2064 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2065 }
2066 if(shaders[MESA_SHADER_TESS_CTRL]) {
2067 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2068 }
2069 if(shaders[MESA_SHADER_VERTEX]) {
2070 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2071 }
2072
2073 if (shader_count > 1) {
2074 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2075 unsigned last = ordered_shaders[0]->info.stage;
2076
2077 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2078 ordered_shaders[1]->info.has_transform_feedback_varyings)
2079 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2080
2081 for (int i = 0; i < shader_count; ++i) {
2082 nir_variable_mode mask = 0;
2083
2084 if (ordered_shaders[i]->info.stage != first)
2085 mask = mask | nir_var_shader_in;
2086
2087 if (ordered_shaders[i]->info.stage != last)
2088 mask = mask | nir_var_shader_out;
2089
2090 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2091 radv_optimize_nir(ordered_shaders[i], false, false);
2092 }
2093 }
2094
2095 for (int i = 1; i < shader_count; ++i) {
2096 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2097 ordered_shaders[i - 1]);
2098
2099 if (nir_link_opt_varyings(ordered_shaders[i],
2100 ordered_shaders[i - 1]))
2101 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2102
2103 nir_remove_dead_variables(ordered_shaders[i],
2104 nir_var_shader_out);
2105 nir_remove_dead_variables(ordered_shaders[i - 1],
2106 nir_var_shader_in);
2107
2108 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2109 ordered_shaders[i - 1]);
2110
2111 nir_compact_varyings(ordered_shaders[i],
2112 ordered_shaders[i - 1], true);
2113
2114 if (progress) {
2115 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2116 ac_lower_indirect_derefs(ordered_shaders[i],
2117 pipeline->device->physical_device->rad_info.chip_class);
2118 }
2119 radv_optimize_nir(ordered_shaders[i], false, false);
2120
2121 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2122 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2123 pipeline->device->physical_device->rad_info.chip_class);
2124 }
2125 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2126 }
2127 }
2128 }
2129
2130 static uint32_t
2131 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2132 uint32_t attrib_binding)
2133 {
2134 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2135 const VkVertexInputBindingDescription *input_binding =
2136 &input_state->pVertexBindingDescriptions[i];
2137
2138 if (input_binding->binding == attrib_binding)
2139 return input_binding->stride;
2140 }
2141
2142 return 0;
2143 }
2144
2145 static struct radv_pipeline_key
2146 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2147 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2148 const struct radv_blend_state *blend,
2149 bool has_view_index)
2150 {
2151 const VkPipelineVertexInputStateCreateInfo *input_state =
2152 pCreateInfo->pVertexInputState;
2153 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2154 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2155
2156 struct radv_pipeline_key key;
2157 memset(&key, 0, sizeof(key));
2158
2159 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2160 key.optimisations_disabled = 1;
2161
2162 key.has_multiview_view_index = has_view_index;
2163
2164 uint32_t binding_input_rate = 0;
2165 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2166 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2167 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2168 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2169 binding_input_rate |= 1u << binding;
2170 instance_rate_divisors[binding] = 1;
2171 }
2172 }
2173 if (divisor_state) {
2174 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2175 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2176 divisor_state->pVertexBindingDivisors[i].divisor;
2177 }
2178 }
2179
2180 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2181 const VkVertexInputAttributeDescription *desc =
2182 &input_state->pVertexAttributeDescriptions[i];
2183 const struct vk_format_description *format_desc;
2184 unsigned location = desc->location;
2185 unsigned binding = desc->binding;
2186 unsigned num_format, data_format;
2187 int first_non_void;
2188
2189 if (binding_input_rate & (1u << binding)) {
2190 key.instance_rate_inputs |= 1u << location;
2191 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2192 }
2193
2194 format_desc = vk_format_description(desc->format);
2195 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2196
2197 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2198 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2199
2200 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2201 key.vertex_attribute_bindings[location] = desc->binding;
2202 key.vertex_attribute_offsets[location] = desc->offset;
2203 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2204
2205 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2206 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2207 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2208 uint64_t adjust;
2209 switch(format) {
2210 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2211 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2212 adjust = RADV_ALPHA_ADJUST_SNORM;
2213 break;
2214 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2215 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2216 adjust = RADV_ALPHA_ADJUST_SSCALED;
2217 break;
2218 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2219 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2220 adjust = RADV_ALPHA_ADJUST_SINT;
2221 break;
2222 default:
2223 adjust = 0;
2224 break;
2225 }
2226 key.vertex_alpha_adjust |= adjust << (2 * location);
2227 }
2228
2229 switch (desc->format) {
2230 case VK_FORMAT_B8G8R8A8_UNORM:
2231 case VK_FORMAT_B8G8R8A8_SNORM:
2232 case VK_FORMAT_B8G8R8A8_USCALED:
2233 case VK_FORMAT_B8G8R8A8_SSCALED:
2234 case VK_FORMAT_B8G8R8A8_UINT:
2235 case VK_FORMAT_B8G8R8A8_SINT:
2236 case VK_FORMAT_B8G8R8A8_SRGB:
2237 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2238 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2239 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2240 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2241 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2242 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2243 key.vertex_post_shuffle |= 1 << location;
2244 break;
2245 default:
2246 break;
2247 }
2248 }
2249
2250 if (pCreateInfo->pTessellationState)
2251 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2252
2253
2254 if (pCreateInfo->pMultisampleState &&
2255 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2256 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2257 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2258 key.num_samples = num_samples;
2259 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2260 }
2261
2262 key.col_format = blend->spi_shader_col_format;
2263 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2264 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2265
2266 return key;
2267 }
2268
2269 static bool
2270 radv_nir_stage_uses_xfb(const nir_shader *nir)
2271 {
2272 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2273 bool uses_xfb = !!xfb;
2274
2275 ralloc_free(xfb);
2276 return uses_xfb;
2277 }
2278
2279 static void
2280 radv_fill_shader_keys(struct radv_device *device,
2281 struct radv_shader_variant_key *keys,
2282 const struct radv_pipeline_key *key,
2283 nir_shader **nir)
2284 {
2285 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2286 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2287 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2288 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2289 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2290 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2291 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2292 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2293 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2294 }
2295
2296 if (nir[MESA_SHADER_TESS_CTRL]) {
2297 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2298 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2299 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2300 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2301
2302 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2303 }
2304
2305 if (nir[MESA_SHADER_GEOMETRY]) {
2306 if (nir[MESA_SHADER_TESS_CTRL])
2307 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2308 else
2309 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2310 }
2311
2312 if (device->physical_device->rad_info.chip_class >= GFX10 &&
2313 device->physical_device->rad_info.family != CHIP_NAVI14 &&
2314 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
2315 if (nir[MESA_SHADER_TESS_CTRL]) {
2316 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2317 } else {
2318 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2319 }
2320
2321 if (nir[MESA_SHADER_TESS_CTRL] &&
2322 nir[MESA_SHADER_GEOMETRY] &&
2323 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2324 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2325 /* Fallback to the legacy path if tessellation is
2326 * enabled with extreme geometry because
2327 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2328 * might hang.
2329 */
2330 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2331 }
2332
2333 /*
2334 * Disable NGG with geometry shaders. There are a bunch of
2335 * issues still:
2336 * * GS primitives in pipeline statistic queries do not get
2337 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2338 * * dEQP-VK.clipping.user_defined.clip_cull_distance_dynamic_index.*geom* failures
2339 * * Interactions with tessellation failing:
2340 * dEQP-VK.tessellation.geometry_interaction.passthrough.tessellate_isolines_passthrough_geometry_no_change
2341 * * General issues with the last primitive missing/corrupt:
2342 * https://bugs.freedesktop.org/show_bug.cgi?id=111248
2343 *
2344 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2345 */
2346 if (nir[MESA_SHADER_GEOMETRY]) {
2347 if (nir[MESA_SHADER_TESS_CTRL])
2348 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2349 else
2350 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2351 }
2352
2353 /* TODO: Implement streamout support for NGG. */
2354 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2355
2356 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2357 if (nir[i])
2358 last_xfb_stage = i;
2359 }
2360
2361 if (nir[last_xfb_stage] &&
2362 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2363 if (nir[MESA_SHADER_TESS_CTRL])
2364 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2365 else
2366 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2367 }
2368 }
2369
2370 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2371 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2372
2373 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2374 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2375 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2376 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2377 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2378 }
2379
2380 static void
2381 radv_fill_shader_info(struct radv_pipeline *pipeline,
2382 struct radv_shader_variant_key *keys,
2383 struct radv_shader_info *infos,
2384 nir_shader **nir)
2385 {
2386 unsigned active_stages = 0;
2387 unsigned filled_stages = 0;
2388
2389 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2390 if (nir[i])
2391 active_stages |= (1 << i);
2392 }
2393
2394 if (nir[MESA_SHADER_FRAGMENT]) {
2395 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2396 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2397 pipeline->layout,
2398 &keys[MESA_SHADER_FRAGMENT],
2399 &infos[MESA_SHADER_FRAGMENT]);
2400
2401 /* TODO: These are no longer used as keys we should refactor this */
2402 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2403 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2404 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2405 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2406 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2407 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2408 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2409 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2410 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2411 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2412 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2413 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2414
2415 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2416 }
2417
2418 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2419 nir[MESA_SHADER_TESS_CTRL]) {
2420 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2421 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2422 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2423
2424 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2425
2426 for (int i = 0; i < 2; i++) {
2427 radv_nir_shader_info_pass(combined_nir[i],
2428 pipeline->layout, &key,
2429 &infos[MESA_SHADER_TESS_CTRL]);
2430 }
2431
2432 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2433 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2434 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2435 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2436
2437 filled_stages |= (1 << MESA_SHADER_VERTEX);
2438 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2439 }
2440
2441 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2442 nir[MESA_SHADER_GEOMETRY]) {
2443 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2444 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2445
2446 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2447
2448 for (int i = 0; i < 2; i++) {
2449 radv_nir_shader_info_pass(combined_nir[i],
2450 pipeline->layout,
2451 &keys[pre_stage],
2452 &infos[MESA_SHADER_GEOMETRY]);
2453 }
2454
2455 filled_stages |= (1 << pre_stage);
2456 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2457 }
2458
2459 active_stages ^= filled_stages;
2460 while (active_stages) {
2461 int i = u_bit_scan(&active_stages);
2462
2463 if (i == MESA_SHADER_TESS_CTRL) {
2464 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2465 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2466 }
2467
2468 if (i == MESA_SHADER_TESS_EVAL) {
2469 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2470 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2471 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2472 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2473 }
2474
2475 radv_nir_shader_info_init(&infos[i]);
2476 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2477 &keys[i], &infos[i]);
2478 }
2479 }
2480
2481 static void
2482 merge_tess_info(struct shader_info *tes_info,
2483 const struct shader_info *tcs_info)
2484 {
2485 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2486 *
2487 * "PointMode. Controls generation of points rather than triangles
2488 * or lines. This functionality defaults to disabled, and is
2489 * enabled if either shader stage includes the execution mode.
2490 *
2491 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2492 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2493 * and OutputVertices, it says:
2494 *
2495 * "One mode must be set in at least one of the tessellation
2496 * shader stages."
2497 *
2498 * So, the fields can be set in either the TCS or TES, but they must
2499 * agree if set in both. Our backend looks at TES, so bitwise-or in
2500 * the values from the TCS.
2501 */
2502 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2503 tes_info->tess.tcs_vertices_out == 0 ||
2504 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2505 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2506
2507 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2508 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2509 tcs_info->tess.spacing == tes_info->tess.spacing);
2510 tes_info->tess.spacing |= tcs_info->tess.spacing;
2511
2512 assert(tcs_info->tess.primitive_mode == 0 ||
2513 tes_info->tess.primitive_mode == 0 ||
2514 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2515 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2516 tes_info->tess.ccw |= tcs_info->tess.ccw;
2517 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2518 }
2519
2520 static
2521 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2522 {
2523 if (!ext)
2524 return;
2525
2526 if (ext->pPipelineCreationFeedback) {
2527 ext->pPipelineCreationFeedback->flags = 0;
2528 ext->pPipelineCreationFeedback->duration = 0;
2529 }
2530
2531 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2532 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2533 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2534 }
2535 }
2536
2537 static
2538 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2539 {
2540 if (!feedback)
2541 return;
2542
2543 feedback->duration -= radv_get_current_time();
2544 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2545 }
2546
2547 static
2548 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2549 {
2550 if (!feedback)
2551 return;
2552
2553 feedback->duration += radv_get_current_time();
2554 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2555 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2556 }
2557
2558 static
2559 void radv_create_shaders(struct radv_pipeline *pipeline,
2560 struct radv_device *device,
2561 struct radv_pipeline_cache *cache,
2562 const struct radv_pipeline_key *key,
2563 const VkPipelineShaderStageCreateInfo **pStages,
2564 const VkPipelineCreateFlags flags,
2565 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2566 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2567 {
2568 struct radv_shader_module fs_m = {0};
2569 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2570 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2571 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2572 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2573 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2574 unsigned char hash[20], gs_copy_hash[20];
2575 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2576
2577 radv_start_feedback(pipeline_feedback);
2578
2579 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2580 if (pStages[i]) {
2581 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2582 if (modules[i]->nir)
2583 _mesa_sha1_compute(modules[i]->nir->info.name,
2584 strlen(modules[i]->nir->info.name),
2585 modules[i]->sha1);
2586
2587 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2588 }
2589 }
2590
2591 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2592 memcpy(gs_copy_hash, hash, 20);
2593 gs_copy_hash[0] ^= 1;
2594
2595 bool found_in_application_cache = true;
2596 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2597 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2598 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2599 &found_in_application_cache);
2600 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2601 }
2602
2603 if (!keep_executable_info &&
2604 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2605 &found_in_application_cache) &&
2606 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2607 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2608 return;
2609 }
2610
2611 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2612 nir_builder fs_b;
2613 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2614 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2615 fs_m.nir = fs_b.shader;
2616 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2617 }
2618
2619 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2620 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2621
2622 if (!modules[i])
2623 continue;
2624
2625 radv_start_feedback(stage_feedbacks[i]);
2626
2627 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2628 stage ? stage->pName : "main", i,
2629 stage ? stage->pSpecializationInfo : NULL,
2630 flags, pipeline->layout);
2631
2632 /* We don't want to alter meta shaders IR directly so clone it
2633 * first.
2634 */
2635 if (nir[i]->info.name) {
2636 nir[i] = nir_shader_clone(NULL, nir[i]);
2637 }
2638
2639 radv_stop_feedback(stage_feedbacks[i], false);
2640 }
2641
2642 if (nir[MESA_SHADER_TESS_CTRL]) {
2643 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2644 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2645 }
2646
2647 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2648 radv_link_shaders(pipeline, nir);
2649
2650 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2651 if (nir[i]) {
2652 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2653 nir_lower_non_uniform_ubo_access |
2654 nir_lower_non_uniform_ssbo_access |
2655 nir_lower_non_uniform_texture_access |
2656 nir_lower_non_uniform_image_access);
2657 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2658 }
2659
2660 if (radv_can_dump_shader(device, modules[i], false))
2661 nir_print_shader(nir[i], stderr);
2662 }
2663
2664 if (nir[MESA_SHADER_FRAGMENT])
2665 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2666
2667 radv_fill_shader_keys(device, keys, key, nir);
2668
2669 radv_fill_shader_info(pipeline, keys, infos, nir);
2670
2671 if (nir[MESA_SHADER_FRAGMENT]) {
2672 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2673 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2674
2675 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2676 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2677 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2678 infos + MESA_SHADER_FRAGMENT,
2679 keep_executable_info, &binaries[MESA_SHADER_FRAGMENT]);
2680
2681 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2682 }
2683
2684 /* TODO: These are no longer used as keys we should refactor this */
2685 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2686 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2687 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2688 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2689 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2690 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2691 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2692 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2693 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2694 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2695 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2696 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2697 }
2698
2699 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2700 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2701 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2702 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2703 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2704
2705 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2706
2707 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2708 pipeline->layout,
2709 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2710 &binaries[MESA_SHADER_TESS_CTRL]);
2711
2712 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2713 }
2714 modules[MESA_SHADER_VERTEX] = NULL;
2715 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2716 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2717 }
2718
2719 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2720 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2721 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2722 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2723
2724 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2725
2726 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2727 pipeline->layout,
2728 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2729 &binaries[MESA_SHADER_GEOMETRY]);
2730
2731 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2732 }
2733 modules[pre_stage] = NULL;
2734 }
2735
2736 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2737 if(modules[i] && !pipeline->shaders[i]) {
2738 if (i == MESA_SHADER_TESS_CTRL) {
2739 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2740 }
2741 if (i == MESA_SHADER_TESS_EVAL) {
2742 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2743 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2744 }
2745
2746 radv_start_feedback(stage_feedbacks[i]);
2747
2748 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2749 pipeline->layout,
2750 keys + i, infos + i,keep_executable_info,
2751 &binaries[i]);
2752
2753 radv_stop_feedback(stage_feedbacks[i], false);
2754 }
2755 }
2756
2757 if(modules[MESA_SHADER_GEOMETRY]) {
2758 struct radv_shader_binary *gs_copy_binary = NULL;
2759 if (!pipeline->gs_copy_shader &&
2760 !radv_pipeline_has_ngg(pipeline)) {
2761 struct radv_shader_info info = {};
2762 struct radv_shader_variant_key key = {};
2763
2764 key.has_multiview_view_index =
2765 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2766
2767 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2768 pipeline->layout, &key,
2769 &info);
2770
2771 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2772 device, nir[MESA_SHADER_GEOMETRY], &info,
2773 &gs_copy_binary, keep_executable_info,
2774 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2775 }
2776
2777 if (!keep_executable_info && pipeline->gs_copy_shader) {
2778 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2779 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2780
2781 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2782 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2783
2784 radv_pipeline_cache_insert_shaders(device, cache,
2785 gs_copy_hash,
2786 variants,
2787 binaries);
2788 }
2789 free(gs_copy_binary);
2790 }
2791
2792 if (!keep_executable_info) {
2793 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2794 binaries);
2795 }
2796
2797 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2798 free(binaries[i]);
2799 if (nir[i]) {
2800 ralloc_free(nir[i]);
2801
2802 if (radv_can_dump_shader_stats(device, modules[i]))
2803 radv_shader_dump_stats(device,
2804 pipeline->shaders[i],
2805 i, stderr);
2806 }
2807 }
2808
2809 if (fs_m.nir)
2810 ralloc_free(fs_m.nir);
2811
2812 radv_stop_feedback(pipeline_feedback, false);
2813 }
2814
2815 static uint32_t
2816 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2817 gl_shader_stage stage, enum chip_class chip_class)
2818 {
2819 bool has_gs = radv_pipeline_has_gs(pipeline);
2820 bool has_tess = radv_pipeline_has_tess(pipeline);
2821 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2822
2823 switch (stage) {
2824 case MESA_SHADER_FRAGMENT:
2825 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2826 case MESA_SHADER_VERTEX:
2827 if (has_tess) {
2828 if (chip_class >= GFX10) {
2829 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2830 } else if (chip_class == GFX9) {
2831 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2832 } else {
2833 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2834 }
2835
2836 }
2837
2838 if (has_gs) {
2839 if (chip_class >= GFX10) {
2840 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2841 } else {
2842 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2843 }
2844 }
2845
2846 if (has_ngg)
2847 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2848
2849 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2850 case MESA_SHADER_GEOMETRY:
2851 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2852 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2853 case MESA_SHADER_COMPUTE:
2854 return R_00B900_COMPUTE_USER_DATA_0;
2855 case MESA_SHADER_TESS_CTRL:
2856 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2857 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2858 case MESA_SHADER_TESS_EVAL:
2859 if (has_gs) {
2860 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2861 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2862 } else if (has_ngg) {
2863 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2864 } else {
2865 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2866 }
2867 default:
2868 unreachable("unknown shader");
2869 }
2870 }
2871
2872 struct radv_bin_size_entry {
2873 unsigned bpp;
2874 VkExtent2D extent;
2875 };
2876
2877 static VkExtent2D
2878 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2879 {
2880 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2881 {
2882 /* One RB / SE */
2883 {
2884 /* One shader engine */
2885 { 0, {128, 128}},
2886 { 1, { 64, 128}},
2887 { 2, { 32, 128}},
2888 { 3, { 16, 128}},
2889 { 17, { 0, 0}},
2890 { UINT_MAX, { 0, 0}},
2891 },
2892 {
2893 /* Two shader engines */
2894 { 0, {128, 128}},
2895 { 2, { 64, 128}},
2896 { 3, { 32, 128}},
2897 { 5, { 16, 128}},
2898 { 17, { 0, 0}},
2899 { UINT_MAX, { 0, 0}},
2900 },
2901 {
2902 /* Four shader engines */
2903 { 0, {128, 128}},
2904 { 3, { 64, 128}},
2905 { 5, { 16, 128}},
2906 { 17, { 0, 0}},
2907 { UINT_MAX, { 0, 0}},
2908 },
2909 },
2910 {
2911 /* Two RB / SE */
2912 {
2913 /* One shader engine */
2914 { 0, {128, 128}},
2915 { 2, { 64, 128}},
2916 { 3, { 32, 128}},
2917 { 5, { 16, 128}},
2918 { 33, { 0, 0}},
2919 { UINT_MAX, { 0, 0}},
2920 },
2921 {
2922 /* Two shader engines */
2923 { 0, {128, 128}},
2924 { 3, { 64, 128}},
2925 { 5, { 32, 128}},
2926 { 9, { 16, 128}},
2927 { 33, { 0, 0}},
2928 { UINT_MAX, { 0, 0}},
2929 },
2930 {
2931 /* Four shader engines */
2932 { 0, {256, 256}},
2933 { 2, {128, 256}},
2934 { 3, {128, 128}},
2935 { 5, { 64, 128}},
2936 { 9, { 16, 128}},
2937 { 33, { 0, 0}},
2938 { UINT_MAX, { 0, 0}},
2939 },
2940 },
2941 {
2942 /* Four RB / SE */
2943 {
2944 /* One shader engine */
2945 { 0, {128, 256}},
2946 { 2, {128, 128}},
2947 { 3, { 64, 128}},
2948 { 5, { 32, 128}},
2949 { 9, { 16, 128}},
2950 { 33, { 0, 0}},
2951 { UINT_MAX, { 0, 0}},
2952 },
2953 {
2954 /* Two shader engines */
2955 { 0, {256, 256}},
2956 { 2, {128, 256}},
2957 { 3, {128, 128}},
2958 { 5, { 64, 128}},
2959 { 9, { 32, 128}},
2960 { 17, { 16, 128}},
2961 { 33, { 0, 0}},
2962 { UINT_MAX, { 0, 0}},
2963 },
2964 {
2965 /* Four shader engines */
2966 { 0, {256, 512}},
2967 { 2, {256, 256}},
2968 { 3, {128, 256}},
2969 { 5, {128, 128}},
2970 { 9, { 64, 128}},
2971 { 17, { 16, 128}},
2972 { 33, { 0, 0}},
2973 { UINT_MAX, { 0, 0}},
2974 },
2975 },
2976 };
2977 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2978 {
2979 // One RB / SE
2980 {
2981 // One shader engine
2982 { 0, {128, 256}},
2983 { 2, {128, 128}},
2984 { 4, { 64, 128}},
2985 { 7, { 32, 128}},
2986 { 13, { 16, 128}},
2987 { 49, { 0, 0}},
2988 { UINT_MAX, { 0, 0}},
2989 },
2990 {
2991 // Two shader engines
2992 { 0, {256, 256}},
2993 { 2, {128, 256}},
2994 { 4, {128, 128}},
2995 { 7, { 64, 128}},
2996 { 13, { 32, 128}},
2997 { 25, { 16, 128}},
2998 { 49, { 0, 0}},
2999 { UINT_MAX, { 0, 0}},
3000 },
3001 {
3002 // Four shader engines
3003 { 0, {256, 512}},
3004 { 2, {256, 256}},
3005 { 4, {128, 256}},
3006 { 7, {128, 128}},
3007 { 13, { 64, 128}},
3008 { 25, { 16, 128}},
3009 { 49, { 0, 0}},
3010 { UINT_MAX, { 0, 0}},
3011 },
3012 },
3013 {
3014 // Two RB / SE
3015 {
3016 // One shader engine
3017 { 0, {256, 256}},
3018 { 2, {128, 256}},
3019 { 4, {128, 128}},
3020 { 7, { 64, 128}},
3021 { 13, { 32, 128}},
3022 { 25, { 16, 128}},
3023 { 97, { 0, 0}},
3024 { UINT_MAX, { 0, 0}},
3025 },
3026 {
3027 // Two shader engines
3028 { 0, {256, 512}},
3029 { 2, {256, 256}},
3030 { 4, {128, 256}},
3031 { 7, {128, 128}},
3032 { 13, { 64, 128}},
3033 { 25, { 32, 128}},
3034 { 49, { 16, 128}},
3035 { 97, { 0, 0}},
3036 { UINT_MAX, { 0, 0}},
3037 },
3038 {
3039 // Four shader engines
3040 { 0, {512, 512}},
3041 { 2, {256, 512}},
3042 { 4, {256, 256}},
3043 { 7, {128, 256}},
3044 { 13, {128, 128}},
3045 { 25, { 64, 128}},
3046 { 49, { 16, 128}},
3047 { 97, { 0, 0}},
3048 { UINT_MAX, { 0, 0}},
3049 },
3050 },
3051 {
3052 // Four RB / SE
3053 {
3054 // One shader engine
3055 { 0, {256, 512}},
3056 { 2, {256, 256}},
3057 { 4, {128, 256}},
3058 { 7, {128, 128}},
3059 { 13, { 64, 128}},
3060 { 25, { 32, 128}},
3061 { 49, { 16, 128}},
3062 { UINT_MAX, { 0, 0}},
3063 },
3064 {
3065 // Two shader engines
3066 { 0, {512, 512}},
3067 { 2, {256, 512}},
3068 { 4, {256, 256}},
3069 { 7, {128, 256}},
3070 { 13, {128, 128}},
3071 { 25, { 64, 128}},
3072 { 49, { 32, 128}},
3073 { 97, { 16, 128}},
3074 { UINT_MAX, { 0, 0}},
3075 },
3076 {
3077 // Four shader engines
3078 { 0, {512, 512}},
3079 { 4, {256, 512}},
3080 { 7, {256, 256}},
3081 { 13, {128, 256}},
3082 { 25, {128, 128}},
3083 { 49, { 64, 128}},
3084 { 97, { 16, 128}},
3085 { UINT_MAX, { 0, 0}},
3086 },
3087 },
3088 };
3089
3090 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3091 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3092 VkExtent2D extent = {512, 512};
3093
3094 unsigned log_num_rb_per_se =
3095 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3096 pipeline->device->physical_device->rad_info.max_se);
3097 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3098
3099 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3100 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3101 unsigned effective_samples = total_samples;
3102 unsigned color_bytes_per_pixel = 0;
3103
3104 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3105 if (vkblend) {
3106 for (unsigned i = 0; i < subpass->color_count; i++) {
3107 if (!vkblend->pAttachments[i].colorWriteMask)
3108 continue;
3109
3110 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3111 continue;
3112
3113 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3114 color_bytes_per_pixel += vk_format_get_blocksize(format);
3115 }
3116
3117 /* MSAA images typically don't use all samples all the time. */
3118 if (effective_samples >= 2 && ps_iter_samples <= 1)
3119 effective_samples = 2;
3120 color_bytes_per_pixel *= effective_samples;
3121 }
3122
3123 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3124 while(color_entry[1].bpp <= color_bytes_per_pixel)
3125 ++color_entry;
3126
3127 extent = color_entry->extent;
3128
3129 if (subpass->depth_stencil_attachment) {
3130 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3131
3132 /* Coefficients taken from AMDVLK */
3133 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3134 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3135 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3136
3137 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3138 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3139 ++ds_entry;
3140
3141 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3142 extent = ds_entry->extent;
3143 }
3144
3145 return extent;
3146 }
3147
3148 static VkExtent2D
3149 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3150 {
3151 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3152 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3153 VkExtent2D extent = {512, 512};
3154
3155 unsigned sdp_interface_count;
3156
3157 switch(pipeline->device->physical_device->rad_info.family) {
3158 case CHIP_NAVI10:
3159 case CHIP_NAVI12:
3160 sdp_interface_count = 16;
3161 break;
3162 case CHIP_NAVI14:
3163 sdp_interface_count = 8;
3164 break;
3165 default:
3166 unreachable("Unhandled GFX10 chip");
3167 }
3168
3169 const unsigned db_tag_size = 64;
3170 const unsigned db_tag_count = 312;
3171 const unsigned color_tag_size = 1024;
3172 const unsigned color_tag_count = 31;
3173 const unsigned fmask_tag_size = 256;
3174 const unsigned fmask_tag_count = 44;
3175
3176 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3177 const unsigned pipe_count = MAX2(rb_count, sdp_interface_count);
3178
3179 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3180 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3181 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3182
3183 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3184 const unsigned samples_log = util_logbase2_ceil(total_samples);
3185
3186 unsigned color_bytes_per_pixel = 0;
3187 unsigned fmask_bytes_per_pixel = 0;
3188
3189 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3190 if (vkblend) {
3191 for (unsigned i = 0; i < subpass->color_count; i++) {
3192 if (!vkblend->pAttachments[i].colorWriteMask)
3193 continue;
3194
3195 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3196 continue;
3197
3198 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3199 color_bytes_per_pixel += vk_format_get_blocksize(format);
3200
3201 if (total_samples > 1) {
3202 const unsigned fmask_array[] = {0, 1, 1, 4};
3203 fmask_bytes_per_pixel += fmask_array[samples_log];
3204 }
3205 }
3206
3207 color_bytes_per_pixel *= total_samples;
3208 }
3209 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3210
3211 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3212 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3213 extent.height = 1ull << (color_pixel_count_log / 2);
3214
3215 if (fmask_bytes_per_pixel) {
3216 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3217
3218 const VkExtent2D fmask_extent = (VkExtent2D){
3219 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3220 .height = 1ull << (color_pixel_count_log / 2)
3221 };
3222
3223 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3224 extent = fmask_extent;
3225 }
3226
3227 if (subpass->depth_stencil_attachment) {
3228 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3229
3230 /* Coefficients taken from AMDVLK */
3231 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3232 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3233 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3234
3235 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3236
3237 const VkExtent2D db_extent = (VkExtent2D){
3238 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3239 .height = 1ull << (color_pixel_count_log / 2)
3240 };
3241
3242 if (db_extent.width * db_extent.height < extent.width * extent.height)
3243 extent = db_extent;
3244 }
3245
3246 extent.width = MAX2(extent.width, 128);
3247 extent.height = MAX2(extent.width, 64);
3248
3249 return extent;
3250 }
3251
3252 static void
3253 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3254 struct radv_pipeline *pipeline,
3255 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3256 {
3257 uint32_t pa_sc_binner_cntl_0 =
3258 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3259 S_028C44_DISABLE_START_OF_PRIM(1);
3260 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3261
3262 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3263 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3264 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3265 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3266 unsigned min_bytes_per_pixel = 0;
3267
3268 if (vkblend) {
3269 for (unsigned i = 0; i < subpass->color_count; i++) {
3270 if (!vkblend->pAttachments[i].colorWriteMask)
3271 continue;
3272
3273 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3274 continue;
3275
3276 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3277 unsigned bytes = vk_format_get_blocksize(format);
3278 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3279 min_bytes_per_pixel = bytes;
3280 }
3281 }
3282
3283 pa_sc_binner_cntl_0 =
3284 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3285 S_028C44_BIN_SIZE_X(0) |
3286 S_028C44_BIN_SIZE_Y(0) |
3287 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3288 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3289 S_028C44_DISABLE_START_OF_PRIM(1);
3290 }
3291
3292 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3293 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3294 }
3295
3296 static void
3297 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3298 struct radv_pipeline *pipeline,
3299 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3300 {
3301 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3302 return;
3303
3304 VkExtent2D bin_size;
3305 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3306 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3307 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3308 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3309 } else
3310 unreachable("Unhandled generation for binning bin size calculation");
3311
3312 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3313 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3314 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3315 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3316
3317 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3318 context_states_per_bin = 1;
3319 persistent_states_per_bin = 1;
3320 fpovs_per_batch = 63;
3321 } else {
3322 /* The context states are affected by the scissor bug. */
3323 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3324 /* 32 causes hangs for RAVEN. */
3325 persistent_states_per_bin = 16;
3326 fpovs_per_batch = 63;
3327 }
3328
3329 const uint32_t pa_sc_binner_cntl_0 =
3330 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3331 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3332 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3333 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3334 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3335 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3336 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3337 S_028C44_DISABLE_START_OF_PRIM(1) |
3338 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3339 S_028C44_OPTIMAL_BIN_SELECTION(1);
3340
3341 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3342
3343 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3344 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3345 } else
3346 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3347 }
3348
3349
3350 static void
3351 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3352 struct radv_pipeline *pipeline,
3353 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3354 const struct radv_graphics_pipeline_create_info *extra)
3355 {
3356 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3357 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3358 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3359 struct radv_render_pass_attachment *attachment = NULL;
3360 uint32_t db_depth_control = 0, db_stencil_control = 0;
3361 uint32_t db_render_control = 0, db_render_override2 = 0;
3362 uint32_t db_render_override = 0;
3363
3364 if (subpass->depth_stencil_attachment)
3365 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3366
3367 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3368 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3369
3370 if (vkds && has_depth_attachment) {
3371 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3372 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3373 S_028800_ZFUNC(vkds->depthCompareOp) |
3374 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3375
3376 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3377 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3378 }
3379
3380 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3381 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3382 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3383 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3384 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3385 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3386
3387 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3388 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3389 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3390 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3391 }
3392
3393 if (attachment && extra) {
3394 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3395 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3396
3397 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3398 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3399 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3400 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3401 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3402 }
3403
3404 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3405 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3406
3407 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
3408 /* From VK_EXT_depth_range_unrestricted spec:
3409 *
3410 * "The behavior described in Primitive Clipping still applies.
3411 * If depth clamping is disabled the depth values are still
3412 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3413 * depth clamping is enabled the above equation is ignored and
3414 * the depth values are instead clamped to the VkViewport
3415 * minDepth and maxDepth values, which in the case of this
3416 * extension can be outside of the 0.0 to 1.0 range."
3417 */
3418 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3419 }
3420
3421 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3422 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3423
3424 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3425 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3426 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3427 }
3428
3429 static void
3430 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3431 struct radv_pipeline *pipeline,
3432 const struct radv_blend_state *blend)
3433 {
3434 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3435 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3436 8);
3437 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3438 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3439
3440 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3441
3442 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3443 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3444 }
3445
3446 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3447
3448 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3449 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3450
3451 pipeline->graphics.col_format = blend->spi_shader_col_format;
3452 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3453 }
3454
3455 static const VkConservativeRasterizationModeEXT
3456 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3457 {
3458 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3459 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3460
3461 if (!conservative_raster)
3462 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3463 return conservative_raster->conservativeRasterizationMode;
3464 }
3465
3466 static void
3467 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3468 struct radv_pipeline *pipeline,
3469 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3470 {
3471 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3472 const VkConservativeRasterizationModeEXT mode =
3473 radv_get_conservative_raster_mode(vkraster);
3474 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3475 bool depth_clip_disable = vkraster->depthClampEnable;
3476
3477 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3478 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3479 if (depth_clip_state) {
3480 depth_clip_disable = !depth_clip_state->depthClipEnable;
3481 }
3482
3483 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3484 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3485 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3486 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3487 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3488 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3489
3490 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3491 S_0286D4_FLAT_SHADE_ENA(1) |
3492 S_0286D4_PNT_SPRITE_ENA(1) |
3493 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3494 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3495 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3496 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3497 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3498
3499 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3500 S_028BE4_PIX_CENTER(1) | // TODO verify
3501 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3502 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3503
3504 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3505 S_028814_FACE(vkraster->frontFace) |
3506 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3507 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3508 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3509 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3510 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3511 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3512 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3513 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3514
3515 /* Conservative rasterization. */
3516 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3517 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3518
3519 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3520 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3521 S_028804_OVERRASTERIZATION_AMOUNT(4);
3522
3523 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3524 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3525 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3526
3527 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3528 pa_sc_conservative_rast |=
3529 S_028C4C_OVER_RAST_ENABLE(1) |
3530 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3531 S_028C4C_UNDER_RAST_ENABLE(0) |
3532 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3533 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3534 } else {
3535 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3536 pa_sc_conservative_rast |=
3537 S_028C4C_OVER_RAST_ENABLE(0) |
3538 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3539 S_028C4C_UNDER_RAST_ENABLE(1) |
3540 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3541 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3542 }
3543 }
3544
3545 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3546 pa_sc_conservative_rast);
3547 }
3548
3549
3550 static void
3551 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3552 struct radv_pipeline *pipeline)
3553 {
3554 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3555
3556 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3557 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3558 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3559
3560 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3561 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3562
3563 /* The exclusion bits can be set to improve rasterization efficiency
3564 * if no sample lies on the pixel boundary (-8 sample offset). It's
3565 * currently always TRUE because the driver doesn't support 16 samples.
3566 */
3567 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3568 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3569 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3570 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3571 }
3572
3573 static void
3574 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3575 struct radv_pipeline *pipeline)
3576 {
3577 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3578 const struct radv_shader_variant *vs =
3579 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3580 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3581 pipeline->shaders[MESA_SHADER_VERTEX];
3582 unsigned vgt_primitiveid_en = 0;
3583 uint32_t vgt_gs_mode = 0;
3584
3585 if (radv_pipeline_has_ngg(pipeline))
3586 return;
3587
3588 if (radv_pipeline_has_gs(pipeline)) {
3589 const struct radv_shader_variant *gs =
3590 pipeline->shaders[MESA_SHADER_GEOMETRY];
3591
3592 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3593 pipeline->device->physical_device->rad_info.chip_class);
3594 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3595 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3596 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3597 }
3598
3599 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3600 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3601 }
3602
3603 static void
3604 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3605 struct radeon_cmdbuf *cs,
3606 struct radv_pipeline *pipeline,
3607 struct radv_shader_variant *shader)
3608 {
3609 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3610
3611 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3612 radeon_emit(cs, va >> 8);
3613 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3614 radeon_emit(cs, shader->config.rsrc1);
3615 radeon_emit(cs, shader->config.rsrc2);
3616
3617 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3618 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3619 clip_dist_mask = outinfo->clip_dist_mask;
3620 cull_dist_mask = outinfo->cull_dist_mask;
3621 total_mask = clip_dist_mask | cull_dist_mask;
3622 bool misc_vec_ena = outinfo->writes_pointsize ||
3623 outinfo->writes_layer ||
3624 outinfo->writes_viewport_index;
3625 unsigned spi_vs_out_config, nparams;
3626
3627 /* VS is required to export at least one param. */
3628 nparams = MAX2(outinfo->param_exports, 1);
3629 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3630
3631 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3632 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3633 }
3634
3635 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3636
3637 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3638 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3639 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3640 V_02870C_SPI_SHADER_4COMP :
3641 V_02870C_SPI_SHADER_NONE) |
3642 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3643 V_02870C_SPI_SHADER_4COMP :
3644 V_02870C_SPI_SHADER_NONE) |
3645 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3646 V_02870C_SPI_SHADER_4COMP :
3647 V_02870C_SPI_SHADER_NONE));
3648
3649 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3650 S_028818_VTX_W0_FMT(1) |
3651 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3652 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3653 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3654
3655 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3656 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3657 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3658 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3659 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3660 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3661 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3662 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3663 cull_dist_mask << 8 |
3664 clip_dist_mask);
3665
3666 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3667 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3668 outinfo->writes_viewport_index);
3669 }
3670
3671 static void
3672 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3673 struct radv_pipeline *pipeline,
3674 struct radv_shader_variant *shader)
3675 {
3676 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3677
3678 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3679 radeon_emit(cs, va >> 8);
3680 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3681 radeon_emit(cs, shader->config.rsrc1);
3682 radeon_emit(cs, shader->config.rsrc2);
3683 }
3684
3685 static void
3686 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3687 struct radv_pipeline *pipeline,
3688 struct radv_shader_variant *shader,
3689 const struct radv_tessellation_state *tess)
3690 {
3691 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3692 uint32_t rsrc2 = shader->config.rsrc2;
3693
3694 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3695 radeon_emit(cs, va >> 8);
3696 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3697
3698 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3699 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3700 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3701 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3702
3703 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3704 radeon_emit(cs, shader->config.rsrc1);
3705 radeon_emit(cs, rsrc2);
3706 }
3707
3708 static void
3709 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3710 struct radeon_cmdbuf *cs,
3711 struct radv_pipeline *pipeline,
3712 struct radv_shader_variant *shader)
3713 {
3714 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3715 gl_shader_stage es_type =
3716 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3717 struct radv_shader_variant *es =
3718 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3719 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3720
3721 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3722 radeon_emit(cs, va >> 8);
3723 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3724 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3725 radeon_emit(cs, shader->config.rsrc1);
3726 radeon_emit(cs, shader->config.rsrc2);
3727
3728 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3729 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3730 clip_dist_mask = outinfo->clip_dist_mask;
3731 cull_dist_mask = outinfo->cull_dist_mask;
3732 total_mask = clip_dist_mask | cull_dist_mask;
3733 bool misc_vec_ena = outinfo->writes_pointsize ||
3734 outinfo->writes_layer ||
3735 outinfo->writes_viewport_index;
3736 bool es_enable_prim_id = outinfo->export_prim_id ||
3737 (es && es->info.uses_prim_id);
3738 bool break_wave_at_eoi = false;
3739 unsigned ge_cntl;
3740 unsigned nparams;
3741
3742 if (es_type == MESA_SHADER_TESS_EVAL) {
3743 struct radv_shader_variant *gs =
3744 pipeline->shaders[MESA_SHADER_GEOMETRY];
3745
3746 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3747 break_wave_at_eoi = true;
3748 }
3749
3750 nparams = MAX2(outinfo->param_exports, 1);
3751 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3752 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3753 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3754
3755 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3756 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3757 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3758 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3759 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3760 V_02870C_SPI_SHADER_4COMP :
3761 V_02870C_SPI_SHADER_NONE) |
3762 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3763 V_02870C_SPI_SHADER_4COMP :
3764 V_02870C_SPI_SHADER_NONE) |
3765 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3766 V_02870C_SPI_SHADER_4COMP :
3767 V_02870C_SPI_SHADER_NONE));
3768
3769 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3770 S_028818_VTX_W0_FMT(1) |
3771 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3772 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3773 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3774 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3775 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3776 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3777 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3778 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3779 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3780 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3781 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3782 cull_dist_mask << 8 |
3783 clip_dist_mask);
3784
3785 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3786 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3787 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3788
3789 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3790 ngg_state->vgt_esgs_ring_itemsize);
3791
3792 /* NGG specific registers. */
3793 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3794 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3795
3796 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3797 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3798 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3799 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3800 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3801 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3802 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3803 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3804 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3805 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3806 S_028B90_CNT(gs_num_invocations) |
3807 S_028B90_ENABLE(gs_num_invocations > 1) |
3808 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3809
3810 /* User edge flags are set by the pos exports. If user edge flags are
3811 * not used, we must use hw-generated edge flags and pass them via
3812 * the prim export to prevent drawing lines on internal edges of
3813 * decomposed primitives (such as quads) with polygon mode = lines.
3814 *
3815 * TODO: We should combine hw-generated edge flags with user edge
3816 * flags in the shader.
3817 */
3818 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3819 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3820 !radv_pipeline_has_gs(pipeline)));
3821
3822 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3823 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3824 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3825
3826 /* Bug workaround for a possible hang with non-tessellation cases.
3827 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3828 *
3829 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3830 */
3831 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3832 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3833 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3834 !radv_pipeline_has_tess(pipeline) &&
3835 ngg_state->hw_max_esverts != 256) {
3836 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3837
3838 if (ngg_state->hw_max_esverts > 5) {
3839 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3840 }
3841 }
3842
3843 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3844 }
3845
3846 static void
3847 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3848 struct radv_pipeline *pipeline,
3849 struct radv_shader_variant *shader,
3850 const struct radv_tessellation_state *tess)
3851 {
3852 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3853
3854 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3855 unsigned hs_rsrc2 = shader->config.rsrc2;
3856
3857 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3858 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3859 } else {
3860 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3861 }
3862
3863 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3864 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3865 radeon_emit(cs, va >> 8);
3866 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3867 } else {
3868 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3869 radeon_emit(cs, va >> 8);
3870 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3871 }
3872
3873 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3874 radeon_emit(cs, shader->config.rsrc1);
3875 radeon_emit(cs, hs_rsrc2);
3876 } else {
3877 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3878 radeon_emit(cs, va >> 8);
3879 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3880 radeon_emit(cs, shader->config.rsrc1);
3881 radeon_emit(cs, shader->config.rsrc2);
3882 }
3883 }
3884
3885 static void
3886 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3887 struct radeon_cmdbuf *cs,
3888 struct radv_pipeline *pipeline,
3889 const struct radv_tessellation_state *tess)
3890 {
3891 struct radv_shader_variant *vs;
3892
3893 /* Skip shaders merged into HS/GS */
3894 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3895 if (!vs)
3896 return;
3897
3898 if (vs->info.vs.as_ls)
3899 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3900 else if (vs->info.vs.as_es)
3901 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3902 else if (vs->info.is_ngg)
3903 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
3904 else
3905 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3906 }
3907
3908 static void
3909 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3910 struct radeon_cmdbuf *cs,
3911 struct radv_pipeline *pipeline,
3912 const struct radv_tessellation_state *tess)
3913 {
3914 if (!radv_pipeline_has_tess(pipeline))
3915 return;
3916
3917 struct radv_shader_variant *tes, *tcs;
3918
3919 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3920 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3921
3922 if (tes) {
3923 if (tes->info.is_ngg) {
3924 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
3925 } else if (tes->info.tes.as_es)
3926 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3927 else
3928 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3929 }
3930
3931 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3932
3933 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3934 tess->tf_param);
3935
3936 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3937 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3938 tess->ls_hs_config);
3939 else
3940 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3941 tess->ls_hs_config);
3942
3943 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
3944 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
3945 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3946 S_028A44_ES_VERTS_PER_SUBGRP(250) |
3947 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
3948 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
3949 }
3950 }
3951
3952 static void
3953 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
3954 struct radeon_cmdbuf *cs,
3955 struct radv_pipeline *pipeline,
3956 struct radv_shader_variant *gs)
3957 {
3958 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
3959 unsigned gs_max_out_vertices;
3960 uint8_t *num_components;
3961 uint8_t max_stream;
3962 unsigned offset;
3963 uint64_t va;
3964
3965 gs_max_out_vertices = gs->info.gs.vertices_out;
3966 max_stream = gs->info.gs.max_stream;
3967 num_components = gs->info.gs.num_stream_output_components;
3968
3969 offset = num_components[0] * gs_max_out_vertices;
3970
3971 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3972 radeon_emit(ctx_cs, offset);
3973 if (max_stream >= 1)
3974 offset += num_components[1] * gs_max_out_vertices;
3975 radeon_emit(ctx_cs, offset);
3976 if (max_stream >= 2)
3977 offset += num_components[2] * gs_max_out_vertices;
3978 radeon_emit(ctx_cs, offset);
3979 if (max_stream >= 3)
3980 offset += num_components[3] * gs_max_out_vertices;
3981 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3982
3983 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3984 radeon_emit(ctx_cs, num_components[0]);
3985 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
3986 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
3987 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
3988
3989 uint32_t gs_num_invocations = gs->info.gs.invocations;
3990 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3991 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3992 S_028B90_ENABLE(gs_num_invocations > 0));
3993
3994 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3995 gs_state->vgt_esgs_ring_itemsize);
3996
3997 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
3998
3999 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4000 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4001 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4002 radeon_emit(cs, va >> 8);
4003 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4004 } else {
4005 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4006 radeon_emit(cs, va >> 8);
4007 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4008 }
4009
4010 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4011 radeon_emit(cs, gs->config.rsrc1);
4012 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4013
4014 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4015 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4016 } else {
4017 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4018 radeon_emit(cs, va >> 8);
4019 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4020 radeon_emit(cs, gs->config.rsrc1);
4021 radeon_emit(cs, gs->config.rsrc2);
4022 }
4023
4024 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4025 }
4026
4027 static void
4028 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4029 struct radeon_cmdbuf *cs,
4030 struct radv_pipeline *pipeline)
4031 {
4032 struct radv_shader_variant *gs;
4033
4034 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4035 if (!gs)
4036 return;
4037
4038 if (gs->info.is_ngg)
4039 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4040 else
4041 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4042
4043 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4044 gs->info.gs.vertices_out);
4045 }
4046
4047 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4048 {
4049 uint32_t ps_input_cntl;
4050 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4051 ps_input_cntl = S_028644_OFFSET(offset);
4052 if (flat_shade)
4053 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4054 if (float16) {
4055 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4056 S_028644_ATTR0_VALID(1);
4057 }
4058 } else {
4059 /* The input is a DEFAULT_VAL constant. */
4060 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4061 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4062 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4063 ps_input_cntl = S_028644_OFFSET(0x20) |
4064 S_028644_DEFAULT_VAL(offset);
4065 }
4066 return ps_input_cntl;
4067 }
4068
4069 static void
4070 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4071 struct radv_pipeline *pipeline)
4072 {
4073 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4074 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4075 uint32_t ps_input_cntl[32];
4076
4077 unsigned ps_offset = 0;
4078
4079 if (ps->info.ps.prim_id_input) {
4080 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4081 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4082 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4083 ++ps_offset;
4084 }
4085 }
4086
4087 if (ps->info.ps.layer_input ||
4088 ps->info.needs_multiview_view_index) {
4089 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4090 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4091 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4092 else
4093 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4094 ++ps_offset;
4095 }
4096
4097 if (ps->info.ps.has_pcoord) {
4098 unsigned val;
4099 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4100 ps_input_cntl[ps_offset] = val;
4101 ps_offset++;
4102 }
4103
4104 if (ps->info.ps.num_input_clips_culls) {
4105 unsigned vs_offset;
4106
4107 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4108 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4109 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4110 ++ps_offset;
4111 }
4112
4113 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4114 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4115 ps->info.ps.num_input_clips_culls > 4) {
4116 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4117 ++ps_offset;
4118 }
4119 }
4120
4121 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4122 unsigned vs_offset;
4123 bool flat_shade;
4124 bool float16;
4125 if (!(ps->info.ps.input_mask & (1u << i)))
4126 continue;
4127
4128 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4129 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4130 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4131 ++ps_offset;
4132 continue;
4133 }
4134
4135 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4136 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4137
4138 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4139 ++ps_offset;
4140 }
4141
4142 if (ps_offset) {
4143 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4144 for (unsigned i = 0; i < ps_offset; i++) {
4145 radeon_emit(ctx_cs, ps_input_cntl[i]);
4146 }
4147 }
4148 }
4149
4150 static uint32_t
4151 radv_compute_db_shader_control(const struct radv_device *device,
4152 const struct radv_pipeline *pipeline,
4153 const struct radv_shader_variant *ps)
4154 {
4155 unsigned z_order;
4156 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4157 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4158 else
4159 z_order = V_02880C_LATE_Z;
4160
4161 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4162 !device->physical_device->rad_info.rbplus_allowed;
4163
4164 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4165 * but this appears to break Project Cars (DXVK). See
4166 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4167 */
4168 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4169
4170 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4171 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4172 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4173 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4174 S_02880C_Z_ORDER(z_order) |
4175 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4176 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4177 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4178 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4179 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4180 }
4181
4182 static void
4183 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4184 struct radeon_cmdbuf *cs,
4185 struct radv_pipeline *pipeline)
4186 {
4187 struct radv_shader_variant *ps;
4188 uint64_t va;
4189 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4190
4191 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4192 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4193
4194 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4195 radeon_emit(cs, va >> 8);
4196 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4197 radeon_emit(cs, ps->config.rsrc1);
4198 radeon_emit(cs, ps->config.rsrc2);
4199
4200 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4201 radv_compute_db_shader_control(pipeline->device,
4202 pipeline, ps));
4203
4204 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4205 ps->config.spi_ps_input_ena);
4206
4207 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4208 ps->config.spi_ps_input_addr);
4209
4210 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4211 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4212 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4213
4214 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4215
4216 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4217 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4218 ps->info.ps.writes_stencil,
4219 ps->info.ps.writes_sample_mask));
4220
4221 if (pipeline->device->dfsm_allowed) {
4222 /* optimise this? */
4223 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4224 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4225 }
4226 }
4227
4228 static void
4229 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4230 struct radv_pipeline *pipeline)
4231 {
4232 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4233 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4234 return;
4235
4236 unsigned vtx_reuse_depth = 30;
4237 if (radv_pipeline_has_tess(pipeline) &&
4238 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4239 vtx_reuse_depth = 14;
4240 }
4241 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4242 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4243 }
4244
4245 static uint32_t
4246 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4247 {
4248 uint32_t stages = 0;
4249 if (radv_pipeline_has_tess(pipeline)) {
4250 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4251 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4252
4253 if (radv_pipeline_has_gs(pipeline))
4254 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4255 S_028B54_GS_EN(1);
4256 else if (radv_pipeline_has_ngg(pipeline))
4257 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4258 else
4259 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4260 } else if (radv_pipeline_has_gs(pipeline)) {
4261 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4262 S_028B54_GS_EN(1);
4263 } else if (radv_pipeline_has_ngg(pipeline)) {
4264 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4265 }
4266
4267 if (radv_pipeline_has_ngg(pipeline)) {
4268 stages |= S_028B54_PRIMGEN_EN(1);
4269 } else if (radv_pipeline_has_gs(pipeline)) {
4270 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4271 }
4272
4273 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4274 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4275
4276 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4277 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4278
4279 if (radv_pipeline_has_tess(pipeline))
4280 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4281
4282 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4283 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4284 if (pipeline->gs_copy_shader)
4285 vs_size = pipeline->gs_copy_shader->info.wave_size;
4286 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4287 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4288 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4289 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4290
4291 if (radv_pipeline_has_ngg(pipeline))
4292 gs_size = vs_size;
4293
4294 /* legacy GS only supports Wave64 */
4295 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4296 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4297 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4298 }
4299
4300 return stages;
4301 }
4302
4303 static uint32_t
4304 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4305 {
4306 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4307 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4308
4309 if (!discard_rectangle_info)
4310 return 0xffff;
4311
4312 unsigned mask = 0;
4313
4314 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4315 /* Interpret i as a bitmask, and then set the bit in the mask if
4316 * that combination of rectangles in which the pixel is contained
4317 * should pass the cliprect test. */
4318 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4319
4320 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4321 !relevant_subset)
4322 continue;
4323
4324 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4325 relevant_subset)
4326 continue;
4327
4328 mask |= 1u << i;
4329 }
4330
4331 return mask;
4332 }
4333
4334 static void
4335 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4336 struct radv_pipeline *pipeline,
4337 const struct radv_tessellation_state *tess)
4338 {
4339 bool break_wave_at_eoi = false;
4340 unsigned primgroup_size;
4341 unsigned vertgroup_size;
4342
4343 if (radv_pipeline_has_tess(pipeline)) {
4344 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4345 vertgroup_size = 0;
4346 } else if (radv_pipeline_has_gs(pipeline)) {
4347 const struct gfx9_gs_info *gs_state =
4348 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4349 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4350 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4351 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4352 } else {
4353 primgroup_size = 128; /* recommended without a GS and tess */
4354 vertgroup_size = 0;
4355 }
4356
4357 if (radv_pipeline_has_tess(pipeline)) {
4358 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4359 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4360 break_wave_at_eoi = true;
4361 }
4362
4363 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4364 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4365 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4366 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4367 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4368 }
4369
4370 static void
4371 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4372 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4373 const struct radv_graphics_pipeline_create_info *extra,
4374 const struct radv_blend_state *blend,
4375 const struct radv_tessellation_state *tess,
4376 unsigned prim, unsigned gs_out)
4377 {
4378 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4379 struct radeon_cmdbuf *cs = &pipeline->cs;
4380
4381 cs->max_dw = 64;
4382 ctx_cs->max_dw = 256;
4383 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4384 ctx_cs->buf = cs->buf + cs->max_dw;
4385
4386 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4387 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4388 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4389 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4390 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4391 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4392 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4393 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4394 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4395 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4396 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4397 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
4398
4399 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4400 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4401
4402 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4403 S_0286E8_WAVES(pipeline->max_waves) |
4404 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4405
4406 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4407
4408 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4409 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4410 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4411 } else {
4412 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4413 }
4414 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4415
4416 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4417
4418 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4419
4420 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4421 assert(cs->cdw <= cs->max_dw);
4422 }
4423
4424 static struct radv_ia_multi_vgt_param_helpers
4425 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4426 const struct radv_tessellation_state *tess,
4427 uint32_t prim)
4428 {
4429 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4430 const struct radv_device *device = pipeline->device;
4431
4432 if (radv_pipeline_has_tess(pipeline))
4433 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4434 else if (radv_pipeline_has_gs(pipeline))
4435 ia_multi_vgt_param.primgroup_size = 64;
4436 else
4437 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4438
4439 /* GS requirement. */
4440 ia_multi_vgt_param.partial_es_wave = false;
4441 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4442 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4443 ia_multi_vgt_param.partial_es_wave = true;
4444
4445 ia_multi_vgt_param.wd_switch_on_eop = false;
4446 if (device->physical_device->rad_info.chip_class >= GFX7) {
4447 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4448 * 4 shader engines. Set 1 to pass the assertion below.
4449 * The other cases are hardware requirements. */
4450 if (device->physical_device->rad_info.max_se < 4 ||
4451 prim == V_008958_DI_PT_POLYGON ||
4452 prim == V_008958_DI_PT_LINELOOP ||
4453 prim == V_008958_DI_PT_TRIFAN ||
4454 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4455 (pipeline->graphics.prim_restart_enable &&
4456 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4457 (prim != V_008958_DI_PT_POINTLIST &&
4458 prim != V_008958_DI_PT_LINESTRIP))))
4459 ia_multi_vgt_param.wd_switch_on_eop = true;
4460 }
4461
4462 ia_multi_vgt_param.ia_switch_on_eoi = false;
4463 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4464 ia_multi_vgt_param.ia_switch_on_eoi = true;
4465 if (radv_pipeline_has_gs(pipeline) &&
4466 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4467 ia_multi_vgt_param.ia_switch_on_eoi = true;
4468 if (radv_pipeline_has_tess(pipeline)) {
4469 /* SWITCH_ON_EOI must be set if PrimID is used. */
4470 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4471 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4472 ia_multi_vgt_param.ia_switch_on_eoi = true;
4473 }
4474
4475 ia_multi_vgt_param.partial_vs_wave = false;
4476 if (radv_pipeline_has_tess(pipeline)) {
4477 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4478 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4479 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4480 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4481 radv_pipeline_has_gs(pipeline))
4482 ia_multi_vgt_param.partial_vs_wave = true;
4483 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4484 if (device->physical_device->rad_info.has_distributed_tess) {
4485 if (radv_pipeline_has_gs(pipeline)) {
4486 if (device->physical_device->rad_info.chip_class <= GFX8)
4487 ia_multi_vgt_param.partial_es_wave = true;
4488 } else {
4489 ia_multi_vgt_param.partial_vs_wave = true;
4490 }
4491 }
4492 }
4493
4494 /* Workaround for a VGT hang when strip primitive types are used with
4495 * primitive restart.
4496 */
4497 if (pipeline->graphics.prim_restart_enable &&
4498 (prim == V_008958_DI_PT_LINESTRIP ||
4499 prim == V_008958_DI_PT_TRISTRIP ||
4500 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4501 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4502 ia_multi_vgt_param.partial_vs_wave = true;
4503 }
4504
4505 if (radv_pipeline_has_gs(pipeline)) {
4506 /* On these chips there is the possibility of a hang if the
4507 * pipeline uses a GS and partial_vs_wave is not set.
4508 *
4509 * This mostly does not hit 4-SE chips, as those typically set
4510 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4511 * with GS due to another workaround.
4512 *
4513 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4514 */
4515 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4516 device->physical_device->rad_info.family == CHIP_FIJI ||
4517 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4518 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4519 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4520 device->physical_device->rad_info.family == CHIP_VEGAM) {
4521 ia_multi_vgt_param.partial_vs_wave = true;
4522 }
4523 }
4524
4525 ia_multi_vgt_param.base =
4526 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4527 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4528 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4529 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4530 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4531
4532 return ia_multi_vgt_param;
4533 }
4534
4535
4536 static void
4537 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4538 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4539 {
4540 const VkPipelineVertexInputStateCreateInfo *vi_info =
4541 pCreateInfo->pVertexInputState;
4542 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4543
4544 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4545 const VkVertexInputAttributeDescription *desc =
4546 &vi_info->pVertexAttributeDescriptions[i];
4547 unsigned loc = desc->location;
4548 const struct vk_format_description *format_desc;
4549
4550 format_desc = vk_format_description(desc->format);
4551
4552 velems->format_size[loc] = format_desc->block.bits / 8;
4553 }
4554
4555 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4556 const VkVertexInputBindingDescription *desc =
4557 &vi_info->pVertexBindingDescriptions[i];
4558
4559 pipeline->binding_stride[desc->binding] = desc->stride;
4560 pipeline->num_vertex_bindings =
4561 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4562 }
4563 }
4564
4565 static struct radv_shader_variant *
4566 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4567 {
4568 int i;
4569
4570 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4571 struct radv_shader_variant *shader =
4572 radv_get_shader(pipeline, i);
4573
4574 if (shader && shader->info.so.num_outputs > 0)
4575 return shader;
4576 }
4577
4578 return NULL;
4579 }
4580
4581 static VkResult
4582 radv_pipeline_init(struct radv_pipeline *pipeline,
4583 struct radv_device *device,
4584 struct radv_pipeline_cache *cache,
4585 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4586 const struct radv_graphics_pipeline_create_info *extra)
4587 {
4588 VkResult result;
4589 bool has_view_index = false;
4590
4591 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4592 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4593 if (subpass->view_mask)
4594 has_view_index = true;
4595
4596 pipeline->device = device;
4597 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4598 assert(pipeline->layout);
4599
4600 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4601
4602 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4603 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4604 radv_init_feedback(creation_feedback);
4605
4606 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4607
4608 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4609 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4610 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4611 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4612 pStages[stage] = &pCreateInfo->pStages[i];
4613 if(creation_feedback)
4614 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4615 }
4616
4617 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4618 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4619
4620 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4621 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4622 uint32_t gs_out;
4623 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4624
4625 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4626
4627 if (radv_pipeline_has_gs(pipeline)) {
4628 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4629 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4630 } else if (radv_pipeline_has_tess(pipeline)) {
4631 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4632 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4633 else
4634 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4635 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4636 } else {
4637 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4638 }
4639 if (extra && extra->use_rectlist) {
4640 prim = V_008958_DI_PT_RECTLIST;
4641 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4642 pipeline->graphics.can_use_guardband = true;
4643 if (radv_pipeline_has_ngg(pipeline))
4644 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4645 }
4646 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4647 /* prim vertex count will need TESS changes */
4648 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4649
4650 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4651
4652 /* Ensure that some export memory is always allocated, for two reasons:
4653 *
4654 * 1) Correctness: The hardware ignores the EXEC mask if no export
4655 * memory is allocated, so KILL and alpha test do not work correctly
4656 * without this.
4657 * 2) Performance: Every shader needs at least a NULL export, even when
4658 * it writes no color/depth output. The NULL export instruction
4659 * stalls without this setting.
4660 *
4661 * Don't add this to CB_SHADER_MASK.
4662 *
4663 * GFX10 supports pixel shaders without exports by setting both the
4664 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4665 * instructions if any are present.
4666 */
4667 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4668 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4669 ps->info.ps.can_discard) &&
4670 !blend.spi_shader_col_format) {
4671 if (!ps->info.ps.writes_z &&
4672 !ps->info.ps.writes_stencil &&
4673 !ps->info.ps.writes_sample_mask)
4674 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4675 }
4676
4677 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4678 if (pipeline->shaders[i]) {
4679 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4680 }
4681 }
4682
4683 if (radv_pipeline_has_ngg(pipeline)) {
4684 struct radv_shader_variant *ngg;
4685
4686 if (radv_pipeline_has_gs(pipeline))
4687 ngg = pipeline->shaders[MESA_SHADER_GEOMETRY];
4688 else if (radv_pipeline_has_tess(pipeline))
4689 ngg = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4690 else
4691 ngg = pipeline->shaders[MESA_SHADER_VERTEX];
4692
4693 gfx10_get_ngg_info(pCreateInfo, pipeline, &ngg->info.ngg_info);
4694 } else if (radv_pipeline_has_gs(pipeline)) {
4695 struct radv_shader_variant *gs =
4696 pipeline->shaders[MESA_SHADER_GEOMETRY];
4697
4698 gfx9_get_gs_info(pCreateInfo, pipeline, &gs->info.gs_ring_info);
4699 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4700 }
4701
4702 struct radv_tessellation_state tess = {0};
4703 if (radv_pipeline_has_tess(pipeline)) {
4704 if (prim == V_008958_DI_PT_PATCH) {
4705 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4706 pipeline->graphics.prim_vertex_count.incr = 1;
4707 }
4708 tess = calculate_tess_state(pipeline, pCreateInfo);
4709 }
4710
4711 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4712
4713 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4714
4715 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4716 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4717
4718 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4719 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4720 if (loc->sgpr_idx != -1) {
4721 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4722 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4723 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4724 pipeline->graphics.vtx_emit_num = 3;
4725 else
4726 pipeline->graphics.vtx_emit_num = 2;
4727 }
4728
4729 /* Find the last vertex shader stage that eventually uses streamout. */
4730 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4731
4732 result = radv_pipeline_scratch_init(device, pipeline);
4733 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
4734
4735 return result;
4736 }
4737
4738 VkResult
4739 radv_graphics_pipeline_create(
4740 VkDevice _device,
4741 VkPipelineCache _cache,
4742 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4743 const struct radv_graphics_pipeline_create_info *extra,
4744 const VkAllocationCallbacks *pAllocator,
4745 VkPipeline *pPipeline)
4746 {
4747 RADV_FROM_HANDLE(radv_device, device, _device);
4748 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4749 struct radv_pipeline *pipeline;
4750 VkResult result;
4751
4752 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4753 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4754 if (pipeline == NULL)
4755 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4756
4757 result = radv_pipeline_init(pipeline, device, cache,
4758 pCreateInfo, extra);
4759 if (result != VK_SUCCESS) {
4760 radv_pipeline_destroy(device, pipeline, pAllocator);
4761 return result;
4762 }
4763
4764 *pPipeline = radv_pipeline_to_handle(pipeline);
4765
4766 return VK_SUCCESS;
4767 }
4768
4769 VkResult radv_CreateGraphicsPipelines(
4770 VkDevice _device,
4771 VkPipelineCache pipelineCache,
4772 uint32_t count,
4773 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4774 const VkAllocationCallbacks* pAllocator,
4775 VkPipeline* pPipelines)
4776 {
4777 VkResult result = VK_SUCCESS;
4778 unsigned i = 0;
4779
4780 for (; i < count; i++) {
4781 VkResult r;
4782 r = radv_graphics_pipeline_create(_device,
4783 pipelineCache,
4784 &pCreateInfos[i],
4785 NULL, pAllocator, &pPipelines[i]);
4786 if (r != VK_SUCCESS) {
4787 result = r;
4788 pPipelines[i] = VK_NULL_HANDLE;
4789 }
4790 }
4791
4792 return result;
4793 }
4794
4795
4796 static void
4797 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
4798 {
4799 struct radv_shader_variant *compute_shader;
4800 struct radv_device *device = pipeline->device;
4801 unsigned threads_per_threadgroup;
4802 unsigned threadgroups_per_cu = 1;
4803 unsigned waves_per_threadgroup;
4804 unsigned max_waves_per_sh = 0;
4805 uint64_t va;
4806
4807 pipeline->cs.buf = malloc(20 * 4);
4808 pipeline->cs.max_dw = 20;
4809
4810 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4811 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
4812
4813 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
4814 radeon_emit(&pipeline->cs, va >> 8);
4815 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
4816
4817 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4818 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
4819 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
4820
4821 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
4822 S_00B860_WAVES(pipeline->max_waves) |
4823 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4824
4825 /* Calculate best compute resource limits. */
4826 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
4827 compute_shader->info.cs.block_size[1] *
4828 compute_shader->info.cs.block_size[2];
4829 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
4830 device->physical_device->cs_wave_size);
4831
4832 if (device->physical_device->rad_info.chip_class >= GFX10 &&
4833 waves_per_threadgroup == 1)
4834 threadgroups_per_cu = 2;
4835
4836 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4837 ac_get_compute_resource_limits(&device->physical_device->rad_info,
4838 waves_per_threadgroup,
4839 max_waves_per_sh,
4840 threadgroups_per_cu));
4841
4842 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4843 radeon_emit(&pipeline->cs,
4844 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4845 radeon_emit(&pipeline->cs,
4846 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4847 radeon_emit(&pipeline->cs,
4848 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4849
4850 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4851 }
4852
4853 static VkResult radv_compute_pipeline_create(
4854 VkDevice _device,
4855 VkPipelineCache _cache,
4856 const VkComputePipelineCreateInfo* pCreateInfo,
4857 const VkAllocationCallbacks* pAllocator,
4858 VkPipeline* pPipeline)
4859 {
4860 RADV_FROM_HANDLE(radv_device, device, _device);
4861 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4862 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4863 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4864 struct radv_pipeline *pipeline;
4865 VkResult result;
4866
4867 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4869 if (pipeline == NULL)
4870 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4871
4872 pipeline->device = device;
4873 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4874 assert(pipeline->layout);
4875
4876 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4877 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4878 radv_init_feedback(creation_feedback);
4879
4880 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4881 if (creation_feedback)
4882 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4883
4884 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4885 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4886
4887 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4888 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4889 result = radv_pipeline_scratch_init(device, pipeline);
4890 if (result != VK_SUCCESS) {
4891 radv_pipeline_destroy(device, pipeline, pAllocator);
4892 return result;
4893 }
4894
4895 radv_compute_generate_pm4(pipeline);
4896
4897 *pPipeline = radv_pipeline_to_handle(pipeline);
4898
4899 return VK_SUCCESS;
4900 }
4901
4902 VkResult radv_CreateComputePipelines(
4903 VkDevice _device,
4904 VkPipelineCache pipelineCache,
4905 uint32_t count,
4906 const VkComputePipelineCreateInfo* pCreateInfos,
4907 const VkAllocationCallbacks* pAllocator,
4908 VkPipeline* pPipelines)
4909 {
4910 VkResult result = VK_SUCCESS;
4911
4912 unsigned i = 0;
4913 for (; i < count; i++) {
4914 VkResult r;
4915 r = radv_compute_pipeline_create(_device, pipelineCache,
4916 &pCreateInfos[i],
4917 pAllocator, &pPipelines[i]);
4918 if (r != VK_SUCCESS) {
4919 result = r;
4920 pPipelines[i] = VK_NULL_HANDLE;
4921 }
4922 }
4923
4924 return result;
4925 }
4926
4927
4928 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
4929 {
4930 uint32_t ret = 0;
4931 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4932 if (pipeline->shaders[i])
4933 ret += i == MESA_SHADER_GEOMETRY ? 2u : 1u;
4934
4935 }
4936 return ret;
4937 }
4938
4939 static struct radv_shader_variant *
4940 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
4941 {
4942 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4943 if (!pipeline->shaders[i])
4944 continue;
4945 if (!index) {
4946 *stage = i;
4947 return pipeline->shaders[i];
4948 }
4949
4950 --index;
4951
4952 if (i == MESA_SHADER_GEOMETRY) {
4953 if (!index) {
4954 *stage = i;
4955 return pipeline->gs_copy_shader;
4956 }
4957 --index;
4958 }
4959 }
4960
4961 *stage = -1;
4962 return NULL;
4963 }
4964
4965 /* Basically strlcpy (which does not exist on linux) specialized for
4966 * descriptions. */
4967 static void desc_copy(char *desc, const char *src) {
4968 int len = strlen(src);
4969 assert(len < VK_MAX_DESCRIPTION_SIZE);
4970 memcpy(desc, src, len);
4971 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
4972 }
4973
4974 VkResult radv_GetPipelineExecutablePropertiesKHR(
4975 VkDevice _device,
4976 const VkPipelineInfoKHR* pPipelineInfo,
4977 uint32_t* pExecutableCount,
4978 VkPipelineExecutablePropertiesKHR* pProperties)
4979 {
4980 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
4981 const uint32_t total_count = radv_get_executable_count(pipeline);
4982
4983 if (!pProperties) {
4984 *pExecutableCount = total_count;
4985 return VK_SUCCESS;
4986 }
4987
4988 const uint32_t count = MIN2(total_count, *pExecutableCount);
4989 for (unsigned i = 0, executable_idx = 0;
4990 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
4991 if (!pipeline->shaders[i])
4992 continue;
4993 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
4994 const char *name = NULL;
4995 const char *description = NULL;
4996 switch(i) {
4997 case MESA_SHADER_VERTEX:
4998 name = "Vertex Shader";
4999 description = "Vulkan Vertex Shader";
5000 break;
5001 case MESA_SHADER_TESS_CTRL:
5002 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5003 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5004 name = "Vertex + Tessellation Control Shaders";
5005 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5006 } else {
5007 name = "Tessellation Control Shader";
5008 description = "Vulkan Tessellation Control Shader";
5009 }
5010 break;
5011 case MESA_SHADER_TESS_EVAL:
5012 name = "Tessellation Evaluation Shader";
5013 description = "Vulkan Tessellation Evaluation Shader";
5014 break;
5015 case MESA_SHADER_GEOMETRY:
5016 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5017 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5018 name = "Tessellation Evaluation + Geometry Shaders";
5019 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5020 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5021 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5022 name = "Vertex + Geometry Shader";
5023 description = "Combined Vulkan Vertex and Geometry Shaders";
5024 } else {
5025 name = "Geometry Shader";
5026 description = "Vulkan Geometry Shader";
5027 }
5028 break;
5029 case MESA_SHADER_FRAGMENT:
5030 name = "Fragment Shader";
5031 description = "Vulkan Fragment Shader";
5032 break;
5033 case MESA_SHADER_COMPUTE:
5034 name = "Compute Shader";
5035 description = "Vulkan Compute Shader";
5036 break;
5037 }
5038
5039 desc_copy(pProperties[executable_idx].name, name);
5040 desc_copy(pProperties[executable_idx].description, description);
5041
5042 ++executable_idx;
5043 if (i == MESA_SHADER_GEOMETRY) {
5044 assert(pipeline->gs_copy_shader);
5045 if (executable_idx >= count)
5046 break;
5047
5048 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5049 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5050 desc_copy(pProperties[executable_idx].description,
5051 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5052
5053 ++executable_idx;
5054 }
5055 }
5056
5057 for (unsigned i = 0; i < count; ++i)
5058 pProperties[i].subgroupSize = 64;
5059
5060 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5061 *pExecutableCount = count;
5062 return result;
5063 }
5064
5065 VkResult radv_GetPipelineExecutableStatisticsKHR(
5066 VkDevice _device,
5067 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5068 uint32_t* pStatisticCount,
5069 VkPipelineExecutableStatisticKHR* pStatistics)
5070 {
5071 RADV_FROM_HANDLE(radv_device, device, _device);
5072 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5073 gl_shader_stage stage;
5074 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5075
5076 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5077 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5078 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5079
5080 VkPipelineExecutableStatisticKHR *s = pStatistics;
5081 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5082 VkResult result = VK_SUCCESS;
5083
5084 if (s < end) {
5085 desc_copy(s->name, "SGPRs");
5086 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5087 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5088 s->value.u64 = shader->config.num_sgprs;
5089 }
5090 ++s;
5091
5092 if (s < end) {
5093 desc_copy(s->name, "VGPRs");
5094 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5095 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5096 s->value.u64 = shader->config.num_vgprs;
5097 }
5098 ++s;
5099
5100 if (s < end) {
5101 desc_copy(s->name, "Spilled SGPRs");
5102 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5103 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5104 s->value.u64 = shader->config.spilled_sgprs;
5105 }
5106 ++s;
5107
5108 if (s < end) {
5109 desc_copy(s->name, "Spilled VGPRs");
5110 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5111 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5112 s->value.u64 = shader->config.spilled_vgprs;
5113 }
5114 ++s;
5115
5116 if (s < end) {
5117 desc_copy(s->name, "PrivMem VGPRs");
5118 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5119 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5120 s->value.u64 = shader->info.private_mem_vgprs;
5121 }
5122 ++s;
5123
5124 if (s < end) {
5125 desc_copy(s->name, "Code size");
5126 desc_copy(s->description, "Code size in bytes");
5127 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5128 s->value.u64 = shader->exec_size;
5129 }
5130 ++s;
5131
5132 if (s < end) {
5133 desc_copy(s->name, "LDS size");
5134 desc_copy(s->description, "LDS size in bytes per workgroup");
5135 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5136 s->value.u64 = shader->config.lds_size * lds_increment;
5137 }
5138 ++s;
5139
5140 if (s < end) {
5141 desc_copy(s->name, "Scratch size");
5142 desc_copy(s->description, "Private memory in bytes per subgroup");
5143 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5144 s->value.u64 = shader->config.scratch_bytes_per_wave;
5145 }
5146 ++s;
5147
5148 if (s < end) {
5149 desc_copy(s->name, "Subgroups per SIMD");
5150 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5151 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5152 s->value.u64 = max_waves;
5153 }
5154 ++s;
5155
5156 if (!pStatistics)
5157 *pStatisticCount = s - pStatistics;
5158 else if (s > end) {
5159 *pStatisticCount = end - pStatistics;
5160 result = VK_INCOMPLETE;
5161 } else {
5162 *pStatisticCount = s - pStatistics;
5163 }
5164
5165 return result;
5166 }
5167
5168 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5169 {
5170 size_t total_size = strlen(src) + 1;
5171
5172 if (!data) {
5173 *data_size = total_size;
5174 return VK_SUCCESS;
5175 }
5176
5177 size_t size = MIN2(total_size, *data_size);
5178
5179 memcpy(data, src, size);
5180 if (size)
5181 *((char*)data + size - 1) = 0;
5182 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5183 }
5184
5185 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5186 VkDevice device,
5187 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5188 uint32_t* pInternalRepresentationCount,
5189 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5190 {
5191 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5192 gl_shader_stage stage;
5193 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5194
5195 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5196 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5197 VkResult result = VK_SUCCESS;
5198 /* optimized NIR */
5199 if (p < end) {
5200 p->isText = true;
5201 desc_copy(p->name, "NIR Shader(s)");
5202 desc_copy(p->description, "The optimized NIR shader(s)");
5203 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5204 result = VK_INCOMPLETE;
5205 }
5206 ++p;
5207
5208 /* LLVM IR */
5209 if (p < end) {
5210 p->isText = true;
5211 desc_copy(p->name, "LLVM IR");
5212 desc_copy(p->description, "The LLVM IR after some optimizations");
5213 if (radv_copy_representation(p->pData, &p->dataSize, shader->llvm_ir_string) != VK_SUCCESS)
5214 result = VK_INCOMPLETE;
5215 }
5216 ++p;
5217
5218 /* Disassembler */
5219 if (p < end) {
5220 p->isText = true;
5221 desc_copy(p->name, "Assembly");
5222 desc_copy(p->description, "Final Assembly");
5223 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5224 result = VK_INCOMPLETE;
5225 }
5226 ++p;
5227
5228 if (!pInternalRepresentations)
5229 *pInternalRepresentationCount = p - pInternalRepresentations;
5230 else if(p > end) {
5231 result = VK_INCOMPLETE;
5232 *pInternalRepresentationCount = end - pInternalRepresentations;
5233 } else {
5234 *pInternalRepresentationCount = p - pInternalRepresentations;
5235 }
5236
5237 return result;
5238 }