projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Handle VK_ATTACHMENT_UNUSED in color attachments.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_private.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34
35 #include <llvm-c/Core.h>
36 #include <llvm-c/TargetMachine.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "r600d_common.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 void radv_shader_variant_destroy(struct radv_device *device,
49 struct radv_shader_variant *variant);
50
51 static const struct nir_shader_compiler_options nir_options = {
52 .vertex_id_zero_based = true,
53 .lower_scmp = true,
54 .lower_flrp32 = true,
55 .lower_fsat = true,
56 .lower_fdiv = true,
57 .lower_sub = true,
58 .lower_pack_snorm_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_unorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_unpack_snorm_2x16 = true,
63 .lower_unpack_snorm_4x8 = true,
64 .lower_unpack_unorm_2x16 = true,
65 .lower_unpack_unorm_4x8 = true,
66 .lower_extract_byte = true,
67 .lower_extract_word = true,
68 .max_unroll_iterations = 32
69 };
70
71 VkResult radv_CreateShaderModule(
72 VkDevice _device,
73 const VkShaderModuleCreateInfo* pCreateInfo,
74 const VkAllocationCallbacks* pAllocator,
75 VkShaderModule* pShaderModule)
76 {
77 RADV_FROM_HANDLE(radv_device, device, _device);
78 struct radv_shader_module *module;
79
80 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
81 assert(pCreateInfo->flags == 0);
82
83 module = vk_alloc2(&device->alloc, pAllocator,
84 sizeof(*module) + pCreateInfo->codeSize, 8,
85 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
86 if (module == NULL)
87 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
88
89 module->nir = NULL;
90 module->size = pCreateInfo->codeSize;
91 memcpy(module->data, pCreateInfo->pCode, module->size);
92
93 _mesa_sha1_compute(module->data, module->size, module->sha1);
94
95 *pShaderModule = radv_shader_module_to_handle(module);
96
97 return VK_SUCCESS;
98 }
99
100 void radv_DestroyShaderModule(
101 VkDevice _device,
102 VkShaderModule _module,
103 const VkAllocationCallbacks* pAllocator)
104 {
105 RADV_FROM_HANDLE(radv_device, device, _device);
106 RADV_FROM_HANDLE(radv_shader_module, module, _module);
107
108 if (!module)
109 return;
110
111 vk_free2(&device->alloc, pAllocator, module);
112 }
113
114
115 static void
116 radv_pipeline_destroy(struct radv_device *device,
117 struct radv_pipeline *pipeline,
118 const VkAllocationCallbacks* allocator)
119 {
120 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
121 if (pipeline->shaders[i])
122 radv_shader_variant_destroy(device, pipeline->shaders[i]);
123
124 if (pipeline->gs_copy_shader)
125 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
126
127 vk_free2(&device->alloc, allocator, pipeline);
128 }
129
130 void radv_DestroyPipeline(
131 VkDevice _device,
132 VkPipeline _pipeline,
133 const VkAllocationCallbacks* pAllocator)
134 {
135 RADV_FROM_HANDLE(radv_device, device, _device);
136 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
137
138 if (!_pipeline)
139 return;
140
141 radv_pipeline_destroy(device, pipeline, pAllocator);
142 }
143
144
145 static void
146 radv_optimize_nir(struct nir_shader *shader)
147 {
148 bool progress;
149
150 do {
151 progress = false;
152
153 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
154 NIR_PASS_V(shader, nir_lower_64bit_pack);
155 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
156 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
157
158 NIR_PASS(progress, shader, nir_copy_prop);
159 NIR_PASS(progress, shader, nir_opt_remove_phis);
160 NIR_PASS(progress, shader, nir_opt_dce);
161 if (nir_opt_trivial_continues(shader)) {
162 progress = true;
163 NIR_PASS(progress, shader, nir_copy_prop);
164 NIR_PASS(progress, shader, nir_opt_dce);
165 }
166 NIR_PASS(progress, shader, nir_opt_if);
167 NIR_PASS(progress, shader, nir_opt_dead_cf);
168 NIR_PASS(progress, shader, nir_opt_cse);
169 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
170 NIR_PASS(progress, shader, nir_opt_algebraic);
171 NIR_PASS(progress, shader, nir_opt_constant_folding);
172 NIR_PASS(progress, shader, nir_opt_undef);
173 NIR_PASS(progress, shader, nir_opt_conditional_discard);
174 if (shader->options->max_unroll_iterations) {
175 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
176 }
177 } while (progress);
178 }
179
180 static nir_shader *
181 radv_shader_compile_to_nir(struct radv_device *device,
182 struct radv_shader_module *module,
183 const char *entrypoint_name,
184 gl_shader_stage stage,
185 const VkSpecializationInfo *spec_info,
186 bool dump)
187 {
188 if (strcmp(entrypoint_name, "main") != 0) {
189 radv_finishme("Multiple shaders per module not really supported");
190 }
191
192 nir_shader *nir;
193 nir_function *entry_point;
194 if (module->nir) {
195 /* Some things such as our meta clear/blit code will give us a NIR
196 * shader directly. In that case, we just ignore the SPIR-V entirely
197 * and just use the NIR shader */
198 nir = module->nir;
199 nir->options = &nir_options;
200 nir_validate_shader(nir);
201
202 assert(exec_list_length(&nir->functions) == 1);
203 struct exec_node *node = exec_list_get_head(&nir->functions);
204 entry_point = exec_node_data(nir_function, node, node);
205 } else {
206 uint32_t *spirv = (uint32_t *) module->data;
207 assert(module->size % 4 == 0);
208
209 uint32_t num_spec_entries = 0;
210 struct nir_spirv_specialization *spec_entries = NULL;
211 if (spec_info && spec_info->mapEntryCount > 0) {
212 num_spec_entries = spec_info->mapEntryCount;
213 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
214 for (uint32_t i = 0; i < num_spec_entries; i++) {
215 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
216 const void *data = spec_info->pData + entry.offset;
217 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
218
219 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
220 if (spec_info->dataSize == 8)
221 spec_entries[i].data64 = *(const uint64_t *)data;
222 else
223 spec_entries[i].data32 = *(const uint32_t *)data;
224 }
225 }
226 const struct nir_spirv_supported_extensions supported_ext = {
227 .draw_parameters = true,
228 .float64 = true,
229 .image_read_without_format = true,
230 .image_write_without_format = true,
231 .tessellation = true,
232 .int64 = true,
233 .variable_pointers = true,
234 };
235 entry_point = spirv_to_nir(spirv, module->size / 4,
236 spec_entries, num_spec_entries,
237 stage, entrypoint_name, &supported_ext, &nir_options);
238 nir = entry_point->shader;
239 assert(nir->stage == stage);
240 nir_validate_shader(nir);
241
242 free(spec_entries);
243
244 /* We have to lower away local constant initializers right before we
245 * inline functions. That way they get properly initialized at the top
246 * of the function and not at the top of its caller.
247 */
248 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
249 NIR_PASS_V(nir, nir_lower_returns);
250 NIR_PASS_V(nir, nir_inline_functions);
251
252 /* Pick off the single entrypoint that we want */
253 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
254 if (func != entry_point)
255 exec_node_remove(&func->node);
256 }
257 assert(exec_list_length(&nir->functions) == 1);
258 entry_point->name = ralloc_strdup(entry_point, "main");
259
260 NIR_PASS_V(nir, nir_remove_dead_variables,
261 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
262
263 /* Now that we've deleted all but the main function, we can go ahead and
264 * lower the rest of the constant initializers.
265 */
266 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
267 NIR_PASS_V(nir, nir_lower_system_values);
268 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
269 }
270
271 /* Vulkan uses the separate-shader linking model */
272 nir->info.separate_shader = true;
273
274 nir_shader_gather_info(nir, entry_point->impl);
275
276 nir_variable_mode indirect_mask = 0;
277 indirect_mask |= nir_var_shader_in;
278 indirect_mask |= nir_var_local;
279
280 nir_lower_indirect_derefs(nir, indirect_mask);
281
282 static const nir_lower_tex_options tex_options = {
283 .lower_txp = ~0,
284 };
285
286 nir_lower_tex(nir, &tex_options);
287
288 nir_lower_vars_to_ssa(nir);
289 nir_lower_var_copies(nir);
290 nir_lower_global_vars_to_local(nir);
291 nir_remove_dead_variables(nir, nir_var_local);
292 radv_optimize_nir(nir);
293
294 if (dump)
295 nir_print_shader(nir, stderr);
296
297 return nir;
298 }
299
300 static const char *radv_get_shader_name(struct radv_shader_variant *var,
301 gl_shader_stage stage)
302 {
303 switch (stage) {
304 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
305 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
306 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
307 case MESA_SHADER_COMPUTE: return "Compute Shader";
308 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
309 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
310 default:
311 return "Unknown shader";
312 };
313
314 }
315 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
316 {
317 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
318 struct radv_shader_variant *var;
319 struct ac_shader_config *conf;
320 int i;
321 FILE *file = stderr;
322 unsigned max_simd_waves = 10;
323 unsigned lds_per_wave = 0;
324
325 for (i = 0; i < MESA_SHADER_STAGES; i++) {
326 if (!pipeline->shaders[i])
327 continue;
328 var = pipeline->shaders[i];
329
330 conf = &var->config;
331
332 if (i == MESA_SHADER_FRAGMENT) {
333 lds_per_wave = conf->lds_size * lds_increment +
334 align(var->info.fs.num_interp * 48, lds_increment);
335 }
336
337 if (conf->num_sgprs) {
338 if (device->physical_device->rad_info.chip_class >= VI)
339 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
340 else
341 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
342 }
343
344 if (conf->num_vgprs)
345 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
346
347 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
348 * that PS can use.
349 */
350 if (lds_per_wave)
351 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
352
353 fprintf(file, "\n%s:\n",
354 radv_get_shader_name(var, i));
355 if (i == MESA_SHADER_FRAGMENT) {
356 fprintf(file, "*** SHADER CONFIG ***\n"
357 "SPI_PS_INPUT_ADDR = 0x%04x\n"
358 "SPI_PS_INPUT_ENA = 0x%04x\n",
359 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
360 }
361 fprintf(file, "*** SHADER STATS ***\n"
362 "SGPRS: %d\n"
363 "VGPRS: %d\n"
364 "Spilled SGPRs: %d\n"
365 "Spilled VGPRs: %d\n"
366 "Code Size: %d bytes\n"
367 "LDS: %d blocks\n"
368 "Scratch: %d bytes per wave\n"
369 "Max Waves: %d\n"
370 "********************\n\n\n",
371 conf->num_sgprs, conf->num_vgprs,
372 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
373 conf->lds_size, conf->scratch_bytes_per_wave,
374 max_simd_waves);
375 }
376 }
377
378 void radv_shader_variant_destroy(struct radv_device *device,
379 struct radv_shader_variant *variant)
380 {
381 if (!p_atomic_dec_zero(&variant->ref_count))
382 return;
383
384 device->ws->buffer_destroy(variant->bo);
385 free(variant);
386 }
387
388 static void radv_fill_shader_variant(struct radv_device *device,
389 struct radv_shader_variant *variant,
390 struct ac_shader_binary *binary,
391 gl_shader_stage stage)
392 {
393 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
394 unsigned vgpr_comp_cnt = 0;
395
396 if (scratch_enabled && !device->llvm_supports_spill)
397 radv_finishme("shader scratch support only available with LLVM 4.0");
398
399 variant->code_size = binary->code_size;
400 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
401 S_00B12C_SCRATCH_EN(scratch_enabled);
402
403 switch (stage) {
404 case MESA_SHADER_TESS_EVAL:
405 vgpr_comp_cnt = 3;
406 /* fallthrough */
407 case MESA_SHADER_TESS_CTRL:
408 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
409 break;
410 case MESA_SHADER_VERTEX:
411 case MESA_SHADER_GEOMETRY:
412 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
413 break;
414 case MESA_SHADER_FRAGMENT:
415 break;
416 case MESA_SHADER_COMPUTE:
417 variant->rsrc2 |=
418 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
419 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
420 S_00B84C_TG_SIZE_EN(1) |
421 S_00B84C_LDS_SIZE(variant->config.lds_size);
422 break;
423 default:
424 unreachable("unsupported shader type");
425 break;
426 }
427
428 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
429 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
430 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
431 S_00B848_DX10_CLAMP(1) |
432 S_00B848_FLOAT_MODE(variant->config.float_mode);
433
434 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
435 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
436
437 void *ptr = device->ws->buffer_map(variant->bo);
438 memcpy(ptr, binary->code, binary->code_size);
439 device->ws->buffer_unmap(variant->bo);
440
441
442 }
443
444 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
445 struct nir_shader *shader,
446 struct radv_pipeline_layout *layout,
447 const union ac_shader_variant_key *key,
448 void** code_out,
449 unsigned *code_size_out,
450 bool dump)
451 {
452 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
453 enum radeon_family chip_family = device->physical_device->rad_info.family;
454 LLVMTargetMachineRef tm;
455 if (!variant)
456 return NULL;
457
458 struct ac_nir_compiler_options options = {0};
459 options.layout = layout;
460 if (key)
461 options.key = *key;
462
463 struct ac_shader_binary binary;
464 enum ac_target_machine_options tm_options = 0;
465 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
466 options.family = chip_family;
467 options.chip_class = device->physical_device->rad_info.chip_class;
468 options.supports_spill = device->llvm_supports_spill;
469 if (options.supports_spill)
470 tm_options |= AC_TM_SUPPORTS_SPILL;
471 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
472 tm_options |= AC_TM_SISCHED;
473 tm = ac_create_target_machine(chip_family, tm_options);
474 ac_compile_nir_shader(tm, &binary, &variant->config,
475 &variant->info, shader, &options, dump);
476 LLVMDisposeTargetMachine(tm);
477
478 radv_fill_shader_variant(device, variant, &binary, shader->stage);
479
480 if (code_out) {
481 *code_out = binary.code;
482 *code_size_out = binary.code_size;
483 } else
484 free(binary.code);
485 free(binary.config);
486 free(binary.rodata);
487 free(binary.global_symbol_offsets);
488 free(binary.relocs);
489 free(binary.disasm_string);
490 variant->ref_count = 1;
491 return variant;
492 }
493
494 static struct radv_shader_variant *
495 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
496 struct nir_shader *nir,
497 void** code_out,
498 unsigned *code_size_out,
499 bool dump_shader)
500 {
501 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
502 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
503 LLVMTargetMachineRef tm;
504 if (!variant)
505 return NULL;
506
507 struct ac_nir_compiler_options options = {0};
508 struct ac_shader_binary binary;
509 enum ac_target_machine_options tm_options = 0;
510 options.family = chip_family;
511 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
512 if (options.supports_spill)
513 tm_options |= AC_TM_SUPPORTS_SPILL;
514 if (pipeline->device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
515 tm_options |= AC_TM_SISCHED;
516 tm = ac_create_target_machine(chip_family, tm_options);
517 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
518 LLVMDisposeTargetMachine(tm);
519
520 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
521
522 if (code_out) {
523 *code_out = binary.code;
524 *code_size_out = binary.code_size;
525 } else
526 free(binary.code);
527 free(binary.config);
528 free(binary.rodata);
529 free(binary.global_symbol_offsets);
530 free(binary.relocs);
531 free(binary.disasm_string);
532 variant->ref_count = 1;
533 return variant;
534 }
535
536 static struct radv_shader_variant *
537 radv_pipeline_compile(struct radv_pipeline *pipeline,
538 struct radv_pipeline_cache *cache,
539 struct radv_shader_module *module,
540 const char *entrypoint,
541 gl_shader_stage stage,
542 const VkSpecializationInfo *spec_info,
543 struct radv_pipeline_layout *layout,
544 const union ac_shader_variant_key *key)
545 {
546 unsigned char sha1[20];
547 unsigned char gs_copy_sha1[20];
548 struct radv_shader_variant *variant;
549 nir_shader *nir;
550 void *code = NULL;
551 unsigned code_size = 0;
552 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
553
554 if (module->nir)
555 _mesa_sha1_compute(module->nir->info.name,
556 strlen(module->nir->info.name),
557 module->sha1);
558
559 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
560 if (stage == MESA_SHADER_GEOMETRY)
561 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
562 layout, key, 1);
563
564 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
565 cache,
566 sha1);
567
568 if (stage == MESA_SHADER_GEOMETRY) {
569 pipeline->gs_copy_shader =
570 radv_create_shader_variant_from_pipeline_cache(
571 pipeline->device,
572 cache,
573 gs_copy_sha1);
574 }
575
576 if (variant &&
577 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
578 return variant;
579
580 nir = radv_shader_compile_to_nir(pipeline->device,
581 module, entrypoint, stage,
582 spec_info, dump);
583 if (nir == NULL)
584 return NULL;
585
586 if (!variant) {
587 variant = radv_shader_variant_create(pipeline->device, nir,
588 layout, key, &code,
589 &code_size, dump);
590 }
591
592 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
593 void *gs_copy_code = NULL;
594 unsigned gs_copy_code_size = 0;
595 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
596 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
597
598 if (pipeline->gs_copy_shader) {
599 pipeline->gs_copy_shader =
600 radv_pipeline_cache_insert_shader(cache,
601 gs_copy_sha1,
602 pipeline->gs_copy_shader,
603 gs_copy_code,
604 gs_copy_code_size);
605 }
606 }
607 if (!module->nir)
608 ralloc_free(nir);
609
610 if (variant)
611 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
612 code, code_size);
613
614 if (code)
615 free(code);
616 return variant;
617 }
618
619 static union ac_shader_variant_key
620 radv_compute_tes_key(bool as_es, bool export_prim_id)
621 {
622 union ac_shader_variant_key key;
623 memset(&key, 0, sizeof(key));
624 key.tes.as_es = as_es;
625 /* export prim id only happens when no geom shader */
626 if (!as_es)
627 key.tes.export_prim_id = export_prim_id;
628 return key;
629 }
630
631 static union ac_shader_variant_key
632 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
633 {
634 union ac_shader_variant_key key;
635 memset(&key, 0, sizeof(key));
636 key.tcs.primitive_mode = primitive_mode;
637 key.tcs.input_vertices = input_vertices;
638 return key;
639 }
640
641 static void
642 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
643 struct radv_pipeline_cache *cache,
644 struct radv_shader_module *tcs_module,
645 struct radv_shader_module *tes_module,
646 const char *tcs_entrypoint,
647 const char *tes_entrypoint,
648 const VkSpecializationInfo *tcs_spec_info,
649 const VkSpecializationInfo *tes_spec_info,
650 struct radv_pipeline_layout *layout,
651 unsigned input_vertices)
652 {
653 unsigned char tcs_sha1[20], tes_sha1[20];
654 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
655 nir_shader *tes_nir, *tcs_nir;
656 void *tes_code = NULL, *tcs_code = NULL;
657 unsigned tes_code_size = 0, tcs_code_size = 0;
658 union ac_shader_variant_key tes_key;
659 union ac_shader_variant_key tcs_key;
660 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
661
662 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
663 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
664 if (tes_module->nir)
665 _mesa_sha1_compute(tes_module->nir->info.name,
666 strlen(tes_module->nir->info.name),
667 tes_module->sha1);
668 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
669
670 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
671 cache,
672 tes_sha1);
673
674 if (tes_variant) {
675 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
676
677 if (tcs_module->nir)
678 _mesa_sha1_compute(tcs_module->nir->info.name,
679 strlen(tcs_module->nir->info.name),
680 tcs_module->sha1);
681
682 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
683
684 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
685 cache,
686 tcs_sha1);
687 }
688
689 if (tcs_variant && tes_variant) {
690 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
691 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
692 return;
693 }
694
695 tes_nir = radv_shader_compile_to_nir(pipeline->device,
696 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
697 tes_spec_info, dump);
698 if (tes_nir == NULL)
699 return;
700
701 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
702 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
703 tcs_spec_info, dump);
704 if (tcs_nir == NULL)
705 return;
706
707 nir_lower_tes_patch_vertices(tes_nir,
708 tcs_nir->info.tess.tcs_vertices_out);
709
710 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
711 layout, &tes_key, &tes_code,
712 &tes_code_size, dump);
713
714 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
715 if (tcs_module->nir)
716 _mesa_sha1_compute(tcs_module->nir->info.name,
717 strlen(tcs_module->nir->info.name),
718 tcs_module->sha1);
719
720 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
721
722 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
723 layout, &tcs_key, &tcs_code,
724 &tcs_code_size, dump);
725
726 if (!tes_module->nir)
727 ralloc_free(tes_nir);
728
729 if (!tcs_module->nir)
730 ralloc_free(tcs_nir);
731
732 if (tes_variant)
733 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
734 tes_code, tes_code_size);
735
736 if (tcs_variant)
737 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
738 tcs_code, tcs_code_size);
739
740 if (tes_code)
741 free(tes_code);
742 if (tcs_code)
743 free(tcs_code);
744 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
745 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
746 return;
747 }
748
749 static VkResult
750 radv_pipeline_scratch_init(struct radv_device *device,
751 struct radv_pipeline *pipeline)
752 {
753 unsigned scratch_bytes_per_wave = 0;
754 unsigned max_waves = 0;
755 unsigned min_waves = 1;
756
757 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
758 if (pipeline->shaders[i]) {
759 unsigned max_stage_waves = device->scratch_waves;
760
761 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
762 pipeline->shaders[i]->config.scratch_bytes_per_wave);
763
764 max_stage_waves = MIN2(max_stage_waves,
765 4 * device->physical_device->rad_info.num_good_compute_units *
766 (256 / pipeline->shaders[i]->config.num_vgprs));
767 max_waves = MAX2(max_waves, max_stage_waves);
768 }
769 }
770
771 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
772 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
773 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
774 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
775 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
776 }
777
778 if (scratch_bytes_per_wave)
779 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
780
781 if (scratch_bytes_per_wave && max_waves < min_waves) {
782 /* Not really true at this moment, but will be true on first
783 * execution. Avoid having hanging shaders. */
784 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
785 }
786 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
787 pipeline->max_waves = max_waves;
788 return VK_SUCCESS;
789 }
790
791 static uint32_t si_translate_blend_function(VkBlendOp op)
792 {
793 switch (op) {
794 case VK_BLEND_OP_ADD:
795 return V_028780_COMB_DST_PLUS_SRC;
796 case VK_BLEND_OP_SUBTRACT:
797 return V_028780_COMB_SRC_MINUS_DST;
798 case VK_BLEND_OP_REVERSE_SUBTRACT:
799 return V_028780_COMB_DST_MINUS_SRC;
800 case VK_BLEND_OP_MIN:
801 return V_028780_COMB_MIN_DST_SRC;
802 case VK_BLEND_OP_MAX:
803 return V_028780_COMB_MAX_DST_SRC;
804 default:
805 return 0;
806 }
807 }
808
809 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
810 {
811 switch (factor) {
812 case VK_BLEND_FACTOR_ZERO:
813 return V_028780_BLEND_ZERO;
814 case VK_BLEND_FACTOR_ONE:
815 return V_028780_BLEND_ONE;
816 case VK_BLEND_FACTOR_SRC_COLOR:
817 return V_028780_BLEND_SRC_COLOR;
818 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
819 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
820 case VK_BLEND_FACTOR_DST_COLOR:
821 return V_028780_BLEND_DST_COLOR;
822 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
823 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
824 case VK_BLEND_FACTOR_SRC_ALPHA:
825 return V_028780_BLEND_SRC_ALPHA;
826 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
827 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
828 case VK_BLEND_FACTOR_DST_ALPHA:
829 return V_028780_BLEND_DST_ALPHA;
830 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
831 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
832 case VK_BLEND_FACTOR_CONSTANT_COLOR:
833 return V_028780_BLEND_CONSTANT_COLOR;
834 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
835 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
836 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
837 return V_028780_BLEND_CONSTANT_ALPHA;
838 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
839 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
840 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
841 return V_028780_BLEND_SRC_ALPHA_SATURATE;
842 case VK_BLEND_FACTOR_SRC1_COLOR:
843 return V_028780_BLEND_SRC1_COLOR;
844 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
845 return V_028780_BLEND_INV_SRC1_COLOR;
846 case VK_BLEND_FACTOR_SRC1_ALPHA:
847 return V_028780_BLEND_SRC1_ALPHA;
848 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
849 return V_028780_BLEND_INV_SRC1_ALPHA;
850 default:
851 return 0;
852 }
853 }
854
855 static bool is_dual_src(VkBlendFactor factor)
856 {
857 switch (factor) {
858 case VK_BLEND_FACTOR_SRC1_COLOR:
859 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
860 case VK_BLEND_FACTOR_SRC1_ALPHA:
861 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
862 return true;
863 default:
864 return false;
865 }
866 }
867
868 static unsigned si_choose_spi_color_format(VkFormat vk_format,
869 bool blend_enable,
870 bool blend_need_alpha)
871 {
872 const struct vk_format_description *desc = vk_format_description(vk_format);
873 unsigned format, ntype, swap;
874
875 /* Alpha is needed for alpha-to-coverage.
876 * Blending may be with or without alpha.
877 */
878 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
879 unsigned alpha = 0; /* exports alpha, but may not support blending */
880 unsigned blend = 0; /* supports blending, but may not export alpha */
881 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
882
883 format = radv_translate_colorformat(vk_format);
884 ntype = radv_translate_color_numformat(vk_format, desc,
885 vk_format_get_first_non_void_channel(vk_format));
886 swap = radv_translate_colorswap(vk_format, false);
887
888 /* Choose the SPI color formats. These are required values for Stoney/RB+.
889 * Other chips have multiple choices, though they are not necessarily better.
890 */
891 switch (format) {
892 case V_028C70_COLOR_5_6_5:
893 case V_028C70_COLOR_1_5_5_5:
894 case V_028C70_COLOR_5_5_5_1:
895 case V_028C70_COLOR_4_4_4_4:
896 case V_028C70_COLOR_10_11_11:
897 case V_028C70_COLOR_11_11_10:
898 case V_028C70_COLOR_8:
899 case V_028C70_COLOR_8_8:
900 case V_028C70_COLOR_8_8_8_8:
901 case V_028C70_COLOR_10_10_10_2:
902 case V_028C70_COLOR_2_10_10_10:
903 if (ntype == V_028C70_NUMBER_UINT)
904 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
905 else if (ntype == V_028C70_NUMBER_SINT)
906 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
907 else
908 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
909 break;
910
911 case V_028C70_COLOR_16:
912 case V_028C70_COLOR_16_16:
913 case V_028C70_COLOR_16_16_16_16:
914 if (ntype == V_028C70_NUMBER_UNORM ||
915 ntype == V_028C70_NUMBER_SNORM) {
916 /* UNORM16 and SNORM16 don't support blending */
917 if (ntype == V_028C70_NUMBER_UNORM)
918 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
919 else
920 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
921
922 /* Use 32 bits per channel for blending. */
923 if (format == V_028C70_COLOR_16) {
924 if (swap == V_028C70_SWAP_STD) { /* R */
925 blend = V_028714_SPI_SHADER_32_R;
926 blend_alpha = V_028714_SPI_SHADER_32_AR;
927 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
928 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
929 else
930 assert(0);
931 } else if (format == V_028C70_COLOR_16_16) {
932 if (swap == V_028C70_SWAP_STD) { /* RG */
933 blend = V_028714_SPI_SHADER_32_GR;
934 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
935 } else if (swap == V_028C70_SWAP_ALT) /* RA */
936 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
937 else
938 assert(0);
939 } else /* 16_16_16_16 */
940 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
941 } else if (ntype == V_028C70_NUMBER_UINT)
942 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
943 else if (ntype == V_028C70_NUMBER_SINT)
944 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
945 else if (ntype == V_028C70_NUMBER_FLOAT)
946 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
947 else
948 assert(0);
949 break;
950
951 case V_028C70_COLOR_32:
952 if (swap == V_028C70_SWAP_STD) { /* R */
953 blend = normal = V_028714_SPI_SHADER_32_R;
954 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
955 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
956 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
957 else
958 assert(0);
959 break;
960
961 case V_028C70_COLOR_32_32:
962 if (swap == V_028C70_SWAP_STD) { /* RG */
963 blend = normal = V_028714_SPI_SHADER_32_GR;
964 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
965 } else if (swap == V_028C70_SWAP_ALT) /* RA */
966 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
967 else
968 assert(0);
969 break;
970
971 case V_028C70_COLOR_32_32_32_32:
972 case V_028C70_COLOR_8_24:
973 case V_028C70_COLOR_24_8:
974 case V_028C70_COLOR_X24_8_32_FLOAT:
975 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
976 break;
977
978 default:
979 unreachable("unhandled blend format");
980 }
981
982 if (blend_enable && blend_need_alpha)
983 return blend_alpha;
984 else if(blend_need_alpha)
985 return alpha;
986 else if(blend_enable)
987 return blend;
988 else
989 return normal;
990 }
991
992 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
993 {
994 unsigned i, cb_shader_mask = 0;
995
996 for (i = 0; i < 8; i++) {
997 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
998 case V_028714_SPI_SHADER_ZERO:
999 break;
1000 case V_028714_SPI_SHADER_32_R:
1001 cb_shader_mask |= 0x1 << (i * 4);
1002 break;
1003 case V_028714_SPI_SHADER_32_GR:
1004 cb_shader_mask |= 0x3 << (i * 4);
1005 break;
1006 case V_028714_SPI_SHADER_32_AR:
1007 cb_shader_mask |= 0x9 << (i * 4);
1008 break;
1009 case V_028714_SPI_SHADER_FP16_ABGR:
1010 case V_028714_SPI_SHADER_UNORM16_ABGR:
1011 case V_028714_SPI_SHADER_SNORM16_ABGR:
1012 case V_028714_SPI_SHADER_UINT16_ABGR:
1013 case V_028714_SPI_SHADER_SINT16_ABGR:
1014 case V_028714_SPI_SHADER_32_ABGR:
1015 cb_shader_mask |= 0xf << (i * 4);
1016 break;
1017 default:
1018 assert(0);
1019 }
1020 }
1021 return cb_shader_mask;
1022 }
1023
1024 static void
1025 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1026 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1027 uint32_t blend_enable,
1028 uint32_t blend_need_alpha,
1029 bool single_cb_enable,
1030 bool blend_mrt0_is_dual_src)
1031 {
1032 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1033 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1034 struct radv_blend_state *blend = &pipeline->graphics.blend;
1035 unsigned col_format = 0;
1036
1037 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1038 unsigned cf;
1039
1040 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1041 cf = V_028714_SPI_SHADER_ZERO;
1042 } else {
1043 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
1044
1045 cf = si_choose_spi_color_format(attachment->format,
1046 blend_enable & (1 << i),
1047 blend_need_alpha & (1 << i));
1048 }
1049
1050 col_format |= cf << (4 * i);
1051 }
1052
1053 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1054
1055 if (blend_mrt0_is_dual_src)
1056 col_format |= (col_format & 0xf) << 4;
1057 blend->spi_shader_col_format = col_format;
1058 }
1059
1060 static bool
1061 format_is_int8(VkFormat format)
1062 {
1063 const struct vk_format_description *desc = vk_format_description(format);
1064 int channel = vk_format_get_first_non_void_channel(format);
1065
1066 return channel >= 0 && desc->channel[channel].pure_integer &&
1067 desc->channel[channel].size == 8;
1068 }
1069
1070 unsigned radv_format_meta_fs_key(VkFormat format)
1071 {
1072 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1073 bool is_int8 = format_is_int8(format);
1074
1075 return col_format + (is_int8 ? 3 : 0);
1076 }
1077
1078 static unsigned
1079 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1080 {
1081 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1082 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1083 unsigned is_int8 = 0;
1084
1085 for (unsigned i = 0; i < subpass->color_count; ++i) {
1086 struct radv_render_pass_attachment *attachment;
1087
1088 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
1089 continue;
1090
1091 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1092
1093 if (format_is_int8(attachment->format))
1094 is_int8 |= 1 << i;
1095 }
1096
1097 return is_int8;
1098 }
1099
1100 static void
1101 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1102 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1103 const struct radv_graphics_pipeline_create_info *extra)
1104 {
1105 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1106 struct radv_blend_state *blend = &pipeline->graphics.blend;
1107 unsigned mode = V_028808_CB_NORMAL;
1108 uint32_t blend_enable = 0, blend_need_alpha = 0;
1109 bool blend_mrt0_is_dual_src = false;
1110 int i;
1111 bool single_cb_enable = false;
1112
1113 if (!vkblend)
1114 return;
1115
1116 if (extra && extra->custom_blend_mode) {
1117 single_cb_enable = true;
1118 mode = extra->custom_blend_mode;
1119 }
1120 blend->cb_color_control = 0;
1121 if (vkblend->logicOpEnable)
1122 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1123 else
1124 blend->cb_color_control |= S_028808_ROP3(0xcc);
1125
1126 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1127 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1128 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1129 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1130
1131 blend->cb_target_mask = 0;
1132 for (i = 0; i < vkblend->attachmentCount; i++) {
1133 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1134 unsigned blend_cntl = 0;
1135 VkBlendOp eqRGB = att->colorBlendOp;
1136 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1137 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1138 VkBlendOp eqA = att->alphaBlendOp;
1139 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1140 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1141
1142 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1143
1144 if (!att->colorWriteMask)
1145 continue;
1146
1147 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1148 if (!att->blendEnable) {
1149 blend->cb_blend_control[i] = blend_cntl;
1150 continue;
1151 }
1152
1153 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1154 if (i == 0)
1155 blend_mrt0_is_dual_src = true;
1156
1157 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1158 srcRGB = VK_BLEND_FACTOR_ONE;
1159 dstRGB = VK_BLEND_FACTOR_ONE;
1160 }
1161 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1162 srcA = VK_BLEND_FACTOR_ONE;
1163 dstA = VK_BLEND_FACTOR_ONE;
1164 }
1165
1166 blend_cntl |= S_028780_ENABLE(1);
1167
1168 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1169 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1170 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1171 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1172 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1173 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1174 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1175 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1176 }
1177 blend->cb_blend_control[i] = blend_cntl;
1178
1179 blend_enable |= 1 << i;
1180
1181 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1182 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1183 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1184 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1185 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1186 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1187 blend_need_alpha |= 1 << i;
1188 }
1189 for (i = vkblend->attachmentCount; i < 8; i++)
1190 blend->cb_blend_control[i] = 0;
1191
1192 if (blend->cb_target_mask)
1193 blend->cb_color_control |= S_028808_MODE(mode);
1194 else
1195 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1196
1197 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1198 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1199 }
1200
1201 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1202 {
1203 switch (op) {
1204 case VK_STENCIL_OP_KEEP:
1205 return V_02842C_STENCIL_KEEP;
1206 case VK_STENCIL_OP_ZERO:
1207 return V_02842C_STENCIL_ZERO;
1208 case VK_STENCIL_OP_REPLACE:
1209 return V_02842C_STENCIL_REPLACE_TEST;
1210 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1211 return V_02842C_STENCIL_ADD_CLAMP;
1212 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1213 return V_02842C_STENCIL_SUB_CLAMP;
1214 case VK_STENCIL_OP_INVERT:
1215 return V_02842C_STENCIL_INVERT;
1216 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1217 return V_02842C_STENCIL_ADD_WRAP;
1218 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1219 return V_02842C_STENCIL_SUB_WRAP;
1220 default:
1221 return 0;
1222 }
1223 }
1224 static void
1225 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1226 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1227 const struct radv_graphics_pipeline_create_info *extra)
1228 {
1229 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1230 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1231
1232 memset(ds, 0, sizeof(*ds));
1233 if (!vkds)
1234 return;
1235
1236 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1237 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1238 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1239 return;
1240
1241 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
1242 bool has_depth_attachment = vk_format_is_depth(attachment->format);
1243 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
1244
1245 if (has_depth_attachment) {
1246 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1247 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1248 S_028800_ZFUNC(vkds->depthCompareOp) |
1249 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1250 }
1251
1252 if (has_stencil_attachment && vkds->stencilTestEnable) {
1253 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1254 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1255 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1256 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1257 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1258
1259 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1260 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1261 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1262 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1263 }
1264
1265 if (extra) {
1266
1267 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1268 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1269
1270 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1271 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1272 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1273 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1274 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1275 }
1276 }
1277
1278 static uint32_t si_translate_fill(VkPolygonMode func)
1279 {
1280 switch(func) {
1281 case VK_POLYGON_MODE_FILL:
1282 return V_028814_X_DRAW_TRIANGLES;
1283 case VK_POLYGON_MODE_LINE:
1284 return V_028814_X_DRAW_LINES;
1285 case VK_POLYGON_MODE_POINT:
1286 return V_028814_X_DRAW_POINTS;
1287 default:
1288 assert(0);
1289 return V_028814_X_DRAW_POINTS;
1290 }
1291 }
1292 static void
1293 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1294 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1295 {
1296 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1297 struct radv_raster_state *raster = &pipeline->graphics.raster;
1298
1299 memset(raster, 0, sizeof(*raster));
1300
1301 raster->spi_interp_control =
1302 S_0286D4_FLAT_SHADE_ENA(1) |
1303 S_0286D4_PNT_SPRITE_ENA(1) |
1304 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1305 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1306 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1307 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1308 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1309
1310
1311 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1312 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1313 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1314 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1315 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1316 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1317
1318 raster->pa_su_vtx_cntl =
1319 S_028BE4_PIX_CENTER(1) | // TODO verify
1320 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1321 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1322
1323 raster->pa_su_sc_mode_cntl =
1324 S_028814_FACE(vkraster->frontFace) |
1325 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1326 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1327 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1328 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1329 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1330 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1331 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1332 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1333
1334 }
1335
1336 static void
1337 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1338 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1339 {
1340 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1341 struct radv_blend_state *blend = &pipeline->graphics.blend;
1342 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1343 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1344 int ps_iter_samples = 1;
1345 uint32_t mask = 0xffff;
1346
1347 if (vkms)
1348 ms->num_samples = vkms->rasterizationSamples;
1349 else
1350 ms->num_samples = 1;
1351
1352 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1353 ps_iter_samples = ms->num_samples;
1354 }
1355
1356 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1357 ms->pa_sc_aa_config = 0;
1358 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1359 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1360 ms->pa_sc_mode_cntl_1 =
1361 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1362 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1363 /* always 1: */
1364 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1365 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1366 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1367 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1368 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1369 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1370 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1371
1372 if (ms->num_samples > 1) {
1373 unsigned log_samples = util_logbase2(ms->num_samples);
1374 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1375 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1376 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1377 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1378 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1379 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1380 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1381 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1382 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1383 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1384 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1385 }
1386
1387 if (vkms) {
1388 if (vkms->alphaToCoverageEnable)
1389 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1390
1391 if (vkms->pSampleMask)
1392 mask = vkms->pSampleMask[0] & 0xffff;
1393 }
1394
1395 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1396 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1397 }
1398
1399 static bool
1400 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1401 {
1402 switch (topology) {
1403 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1404 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1405 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1406 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1407 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1408 return false;
1409 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1410 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1411 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1412 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1413 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1414 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1415 return true;
1416 default:
1417 unreachable("unhandled primitive type");
1418 }
1419 }
1420
1421 static uint32_t
1422 si_translate_prim(enum VkPrimitiveTopology topology)
1423 {
1424 switch (topology) {
1425 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1426 return V_008958_DI_PT_POINTLIST;
1427 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1428 return V_008958_DI_PT_LINELIST;
1429 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1430 return V_008958_DI_PT_LINESTRIP;
1431 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1432 return V_008958_DI_PT_TRILIST;
1433 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1434 return V_008958_DI_PT_TRISTRIP;
1435 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1436 return V_008958_DI_PT_TRIFAN;
1437 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1438 return V_008958_DI_PT_LINELIST_ADJ;
1439 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1440 return V_008958_DI_PT_LINESTRIP_ADJ;
1441 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1442 return V_008958_DI_PT_TRILIST_ADJ;
1443 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1444 return V_008958_DI_PT_TRISTRIP_ADJ;
1445 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1446 return V_008958_DI_PT_PATCH;
1447 default:
1448 assert(0);
1449 return 0;
1450 }
1451 }
1452
1453 static uint32_t
1454 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1455 {
1456 switch (gl_prim) {
1457 case 0: /* GL_POINTS */
1458 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1459 case 1: /* GL_LINES */
1460 case 3: /* GL_LINE_STRIP */
1461 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1462 case 0x8E7A: /* GL_ISOLINES */
1463 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1464
1465 case 4: /* GL_TRIANGLES */
1466 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1467 case 5: /* GL_TRIANGLE_STRIP */
1468 case 7: /* GL_QUADS */
1469 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1470 default:
1471 assert(0);
1472 return 0;
1473 }
1474 }
1475
1476 static uint32_t
1477 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1478 {
1479 switch (topology) {
1480 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1481 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1482 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1483 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1484 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1485 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1486 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1487 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1488 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1489 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1490 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1491 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1492 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1493 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1494 default:
1495 assert(0);
1496 return 0;
1497 }
1498 }
1499
1500 static unsigned si_map_swizzle(unsigned swizzle)
1501 {
1502 switch (swizzle) {
1503 case VK_SWIZZLE_Y:
1504 return V_008F0C_SQ_SEL_Y;
1505 case VK_SWIZZLE_Z:
1506 return V_008F0C_SQ_SEL_Z;
1507 case VK_SWIZZLE_W:
1508 return V_008F0C_SQ_SEL_W;
1509 case VK_SWIZZLE_0:
1510 return V_008F0C_SQ_SEL_0;
1511 case VK_SWIZZLE_1:
1512 return V_008F0C_SQ_SEL_1;
1513 default: /* VK_SWIZZLE_X */
1514 return V_008F0C_SQ_SEL_X;
1515 }
1516 }
1517
1518 static void
1519 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1520 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1521 {
1522 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1523 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1524 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1525
1526 pipeline->dynamic_state = default_dynamic_state;
1527
1528 if (pCreateInfo->pDynamicState) {
1529 /* Remove all of the states that are marked as dynamic */
1530 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1531 for (uint32_t s = 0; s < count; s++)
1532 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1533 }
1534
1535 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1536
1537 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1538 *
1539 * pViewportState is [...] NULL if the pipeline
1540 * has rasterization disabled.
1541 */
1542 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1543 assert(pCreateInfo->pViewportState);
1544
1545 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1546 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1547 typed_memcpy(dynamic->viewport.viewports,
1548 pCreateInfo->pViewportState->pViewports,
1549 pCreateInfo->pViewportState->viewportCount);
1550 }
1551
1552 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1553 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1554 typed_memcpy(dynamic->scissor.scissors,
1555 pCreateInfo->pViewportState->pScissors,
1556 pCreateInfo->pViewportState->scissorCount);
1557 }
1558 }
1559
1560 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1561 assert(pCreateInfo->pRasterizationState);
1562 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1563 }
1564
1565 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1566 assert(pCreateInfo->pRasterizationState);
1567 dynamic->depth_bias.bias =
1568 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1569 dynamic->depth_bias.clamp =
1570 pCreateInfo->pRasterizationState->depthBiasClamp;
1571 dynamic->depth_bias.slope =
1572 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1573 }
1574
1575 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1576 *
1577 * pColorBlendState is [...] NULL if the pipeline has rasterization
1578 * disabled or if the subpass of the render pass the pipeline is
1579 * created against does not use any color attachments.
1580 */
1581 bool uses_color_att = false;
1582 for (unsigned i = 0; i < subpass->color_count; ++i) {
1583 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1584 uses_color_att = true;
1585 break;
1586 }
1587 }
1588
1589 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1590 assert(pCreateInfo->pColorBlendState);
1591 typed_memcpy(dynamic->blend_constants,
1592 pCreateInfo->pColorBlendState->blendConstants, 4);
1593 }
1594
1595 /* If there is no depthstencil attachment, then don't read
1596 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1597 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1598 * no need to override the depthstencil defaults in
1599 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1600 *
1601 * Section 9.2 of the Vulkan 1.0.15 spec says:
1602 *
1603 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1604 * disabled or if the subpass of the render pass the pipeline is created
1605 * against does not use a depth/stencil attachment.
1606 */
1607 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1608 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1609 assert(pCreateInfo->pDepthStencilState);
1610
1611 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1612 dynamic->depth_bounds.min =
1613 pCreateInfo->pDepthStencilState->minDepthBounds;
1614 dynamic->depth_bounds.max =
1615 pCreateInfo->pDepthStencilState->maxDepthBounds;
1616 }
1617
1618 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1619 dynamic->stencil_compare_mask.front =
1620 pCreateInfo->pDepthStencilState->front.compareMask;
1621 dynamic->stencil_compare_mask.back =
1622 pCreateInfo->pDepthStencilState->back.compareMask;
1623 }
1624
1625 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1626 dynamic->stencil_write_mask.front =
1627 pCreateInfo->pDepthStencilState->front.writeMask;
1628 dynamic->stencil_write_mask.back =
1629 pCreateInfo->pDepthStencilState->back.writeMask;
1630 }
1631
1632 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1633 dynamic->stencil_reference.front =
1634 pCreateInfo->pDepthStencilState->front.reference;
1635 dynamic->stencil_reference.back =
1636 pCreateInfo->pDepthStencilState->back.reference;
1637 }
1638 }
1639
1640 pipeline->dynamic_state_mask = states;
1641 }
1642
1643 static union ac_shader_variant_key
1644 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1645 {
1646 union ac_shader_variant_key key;
1647 const VkPipelineVertexInputStateCreateInfo *input_state =
1648 pCreateInfo->pVertexInputState;
1649
1650 memset(&key, 0, sizeof(key));
1651 key.vs.instance_rate_inputs = 0;
1652 key.vs.as_es = as_es;
1653 key.vs.as_ls = as_ls;
1654 key.vs.export_prim_id = export_prim_id;
1655
1656 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1657 unsigned binding;
1658 binding = input_state->pVertexAttributeDescriptions[i].binding;
1659 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1660 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1661 }
1662 return key;
1663 }
1664
1665 static void
1666 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1667 {
1668 struct radv_device *device = pipeline->device;
1669 unsigned num_se = device->physical_device->rad_info.max_se;
1670 unsigned wave_size = 64;
1671 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1672 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1673 unsigned alignment = 256 * num_se;
1674 /* The maximum size is 63.999 MB per SE. */
1675 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1676 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1677 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1678 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1679 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1680
1681 /* Calculate the minimum size. */
1682 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1683 wave_size, alignment);
1684 /* These are recommended sizes, not minimum sizes. */
1685 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1686 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1687 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1688 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1689
1690 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1691 esgs_ring_size = align(esgs_ring_size, alignment);
1692 gsvs_ring_size = align(gsvs_ring_size, alignment);
1693
1694 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1695 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1696 }
1697
1698 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1699 unsigned *lds_size)
1700 {
1701 /* SPI barrier management bug:
1702 * Make sure we have at least 4k of LDS in use to avoid the bug.
1703 * It applies to workgroup sizes of more than one wavefront.
1704 */
1705 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1706 device->physical_device->rad_info.family == CHIP_KABINI ||
1707 device->physical_device->rad_info.family == CHIP_MULLINS)
1708 *lds_size = MAX2(*lds_size, 8);
1709 }
1710
1711 static void
1712 calculate_tess_state(struct radv_pipeline *pipeline,
1713 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1714 {
1715 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1716 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1717 unsigned num_tcs_patch_outputs;
1718 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1719 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1720 unsigned lds_size, hardware_lds_size;
1721 unsigned perpatch_output_offset;
1722 unsigned num_patches;
1723 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1724
1725 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1726 * are laid out in LDS. */
1727 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1728
1729 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1730 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1731 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1732
1733 /* Ensure that we only need one wave per SIMD so we don't need to check
1734 * resource usage. Also ensures that the number of tcs in and out
1735 * vertices per threadgroup are at most 256.
1736 */
1737 input_vertex_size = num_tcs_inputs * 16;
1738 output_vertex_size = num_tcs_outputs * 16;
1739
1740 input_patch_size = num_tcs_input_cp * input_vertex_size;
1741
1742 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1743 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1744 /* Ensure that we only need one wave per SIMD so we don't need to check
1745 * resource usage. Also ensures that the number of tcs in and out
1746 * vertices per threadgroup are at most 256.
1747 */
1748 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1749
1750 /* Make sure that the data fits in LDS. This assumes the shaders only
1751 * use LDS for the inputs and outputs.
1752 */
1753 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1754 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1755
1756 /* Make sure the output data fits in the offchip buffer */
1757 num_patches = MIN2(num_patches,
1758 (pipeline->device->tess_offchip_block_dw_size * 4) /
1759 output_patch_size);
1760
1761 /* Not necessary for correctness, but improves performance. The
1762 * specific value is taken from the proprietary driver.
1763 */
1764 num_patches = MIN2(num_patches, 40);
1765
1766 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1767 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1768 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1769 num_patches = MIN2(num_patches, one_wave);
1770 }
1771
1772 output_patch0_offset = input_patch_size * num_patches;
1773 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1774
1775 lds_size = output_patch0_offset + output_patch_size * num_patches;
1776
1777 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1778 assert(lds_size <= 65536);
1779 lds_size = align(lds_size, 512) / 512;
1780 } else {
1781 assert(lds_size <= 32768);
1782 lds_size = align(lds_size, 256) / 256;
1783 }
1784 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1785
1786 tess->lds_size = lds_size;
1787
1788 tess->tcs_in_layout = (input_patch_size / 4) |
1789 ((input_vertex_size / 4) << 13);
1790 tess->tcs_out_layout = (output_patch_size / 4) |
1791 ((output_vertex_size / 4) << 13);
1792 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1793 ((perpatch_output_offset / 16) << 16);
1794 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1795 (num_tcs_output_cp << 9) | num_patches;
1796
1797 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1798 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1799 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1800 tess->num_patches = num_patches;
1801 tess->num_tcs_input_cp = num_tcs_input_cp;
1802
1803 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1804 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1805
1806 switch (tes->info.tes.primitive_mode) {
1807 case GL_TRIANGLES:
1808 type = V_028B6C_TESS_TRIANGLE;
1809 break;
1810 case GL_QUADS:
1811 type = V_028B6C_TESS_QUAD;
1812 break;
1813 case GL_ISOLINES:
1814 type = V_028B6C_TESS_ISOLINE;
1815 break;
1816 }
1817
1818 switch (tes->info.tes.spacing) {
1819 case TESS_SPACING_EQUAL:
1820 partitioning = V_028B6C_PART_INTEGER;
1821 break;
1822 case TESS_SPACING_FRACTIONAL_ODD:
1823 partitioning = V_028B6C_PART_FRAC_ODD;
1824 break;
1825 case TESS_SPACING_FRACTIONAL_EVEN:
1826 partitioning = V_028B6C_PART_FRAC_EVEN;
1827 break;
1828 default:
1829 break;
1830 }
1831
1832 if (tes->info.tes.point_mode)
1833 topology = V_028B6C_OUTPUT_POINT;
1834 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1835 topology = V_028B6C_OUTPUT_LINE;
1836 else if (tes->info.tes.ccw)
1837 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1838 else
1839 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1840
1841 if (pipeline->device->has_distributed_tess) {
1842 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1843 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1844 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1845 else
1846 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1847 } else
1848 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1849
1850 tess->tf_param = S_028B6C_TYPE(type) |
1851 S_028B6C_PARTITIONING(partitioning) |
1852 S_028B6C_TOPOLOGY(topology) |
1853 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1854 }
1855
1856 static const struct radv_prim_vertex_count prim_size_table[] = {
1857 [V_008958_DI_PT_NONE] = {0, 0},
1858 [V_008958_DI_PT_POINTLIST] = {1, 1},
1859 [V_008958_DI_PT_LINELIST] = {2, 2},
1860 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1861 [V_008958_DI_PT_TRILIST] = {3, 3},
1862 [V_008958_DI_PT_TRIFAN] = {3, 1},
1863 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1864 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1865 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1866 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1867 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1868 [V_008958_DI_PT_RECTLIST] = {3, 3},
1869 [V_008958_DI_PT_LINELOOP] = {2, 1},
1870 [V_008958_DI_PT_POLYGON] = {3, 1},
1871 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1872 };
1873
1874 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1875 {
1876 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1877 unsigned cut_mode;
1878
1879 if (gs_max_vert_out <= 128) {
1880 cut_mode = V_028A40_GS_CUT_128;
1881 } else if (gs_max_vert_out <= 256) {
1882 cut_mode = V_028A40_GS_CUT_256;
1883 } else if (gs_max_vert_out <= 512) {
1884 cut_mode = V_028A40_GS_CUT_512;
1885 } else {
1886 assert(gs_max_vert_out <= 1024);
1887 cut_mode = V_028A40_GS_CUT_1024;
1888 }
1889
1890 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1891 S_028A40_CUT_MODE(cut_mode)|
1892 S_028A40_ES_WRITE_OPTIMIZE(1) |
1893 S_028A40_GS_WRITE_OPTIMIZE(1);
1894 }
1895
1896 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1897 {
1898 struct radv_shader_variant *vs;
1899 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1900
1901 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1902
1903 pipeline->graphics.vgt_primitiveid_en = false;
1904 pipeline->graphics.vgt_gs_mode = 0;
1905
1906 if (radv_pipeline_has_gs(pipeline)) {
1907 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1908 } else if (outinfo->export_prim_id) {
1909 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1910 pipeline->graphics.vgt_primitiveid_en = true;
1911 }
1912 }
1913
1914 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1915 {
1916 struct radv_shader_variant *vs;
1917 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1918
1919 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1920
1921 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1922 clip_dist_mask = outinfo->clip_dist_mask;
1923 cull_dist_mask = outinfo->cull_dist_mask;
1924 total_mask = clip_dist_mask | cull_dist_mask;
1925
1926 bool misc_vec_ena = outinfo->writes_pointsize ||
1927 outinfo->writes_layer ||
1928 outinfo->writes_viewport_index;
1929 pipeline->graphics.pa_cl_vs_out_cntl =
1930 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1931 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1932 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1933 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1934 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1935 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1936 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1937 cull_dist_mask << 8 |
1938 clip_dist_mask;
1939
1940 }
1941
1942 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1943 {
1944 uint32_t ps_input_cntl;
1945 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1946 ps_input_cntl = S_028644_OFFSET(offset);
1947 if (flat_shade)
1948 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1949 } else {
1950 /* The input is a DEFAULT_VAL constant. */
1951 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1952 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1953 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1954 ps_input_cntl = S_028644_OFFSET(0x20) |
1955 S_028644_DEFAULT_VAL(offset);
1956 }
1957 return ps_input_cntl;
1958 }
1959
1960 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1961 {
1962 struct radv_shader_variant *ps, *vs;
1963 struct ac_vs_output_info *outinfo;
1964
1965 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1966 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1967
1968 outinfo = &vs->info.vs.outinfo;
1969
1970 unsigned ps_offset = 0;
1971
1972 if (ps->info.fs.prim_id_input) {
1973 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1974 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1975 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1976 ++ps_offset;
1977 }
1978 }
1979
1980 if (ps->info.fs.layer_input) {
1981 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1982 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1983 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1984 ++ps_offset;
1985 }
1986 }
1987
1988 if (ps->info.fs.has_pcoord) {
1989 unsigned val;
1990 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1991 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1992 ps_offset++;
1993 }
1994
1995 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1996 unsigned vs_offset;
1997 bool flat_shade;
1998 if (!(ps->info.fs.input_mask & (1u << i)))
1999 continue;
2000
2001 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2002 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2003 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2004 ++ps_offset;
2005 continue;
2006 }
2007
2008 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2009
2010 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2011 ++ps_offset;
2012 }
2013
2014 pipeline->graphics.ps_input_cntl_num = ps_offset;
2015 }
2016
2017 VkResult
2018 radv_pipeline_init(struct radv_pipeline *pipeline,
2019 struct radv_device *device,
2020 struct radv_pipeline_cache *cache,
2021 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2022 const struct radv_graphics_pipeline_create_info *extra,
2023 const VkAllocationCallbacks *alloc)
2024 {
2025 struct radv_shader_module fs_m = {0};
2026 VkResult result;
2027
2028 if (alloc == NULL)
2029 alloc = &device->alloc;
2030
2031 pipeline->device = device;
2032 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2033
2034 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2035 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2036 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2037 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2038 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2039 pStages[stage] = &pCreateInfo->pStages[i];
2040 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2041 }
2042
2043 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2044
2045 if (!modules[MESA_SHADER_FRAGMENT]) {
2046 nir_builder fs_b;
2047 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2048 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2049 fs_m.nir = fs_b.shader;
2050 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2051 }
2052
2053 if (modules[MESA_SHADER_FRAGMENT]) {
2054 union ac_shader_variant_key key;
2055 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2056 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
2057
2058 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2059
2060 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2061 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2062 stage ? stage->pName : "main",
2063 MESA_SHADER_FRAGMENT,
2064 stage ? stage->pSpecializationInfo : NULL,
2065 pipeline->layout, &key);
2066 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2067 }
2068
2069 if (fs_m.nir)
2070 ralloc_free(fs_m.nir);
2071
2072 if (modules[MESA_SHADER_VERTEX]) {
2073 bool as_es = false;
2074 bool as_ls = false;
2075 bool export_prim_id = false;
2076 if (modules[MESA_SHADER_TESS_CTRL])
2077 as_ls = true;
2078 else if (modules[MESA_SHADER_GEOMETRY])
2079 as_es = true;
2080 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2081 export_prim_id = true;
2082 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2083
2084 pipeline->shaders[MESA_SHADER_VERTEX] =
2085 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2086 pStages[MESA_SHADER_VERTEX]->pName,
2087 MESA_SHADER_VERTEX,
2088 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2089 pipeline->layout, &key);
2090
2091 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2092 }
2093
2094 if (modules[MESA_SHADER_GEOMETRY]) {
2095 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2096
2097 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2098 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2099 pStages[MESA_SHADER_GEOMETRY]->pName,
2100 MESA_SHADER_GEOMETRY,
2101 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2102 pipeline->layout, &key);
2103
2104 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2105 }
2106
2107 if (modules[MESA_SHADER_TESS_EVAL]) {
2108 assert(modules[MESA_SHADER_TESS_CTRL]);
2109
2110 radv_tess_pipeline_compile(pipeline,
2111 cache,
2112 modules[MESA_SHADER_TESS_CTRL],
2113 modules[MESA_SHADER_TESS_EVAL],
2114 pStages[MESA_SHADER_TESS_CTRL]->pName,
2115 pStages[MESA_SHADER_TESS_EVAL]->pName,
2116 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2117 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2118 pipeline->layout,
2119 pCreateInfo->pTessellationState->patchControlPoints);
2120 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2121 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2122 }
2123
2124 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2125 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2126 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2127 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2128 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2129
2130 if (radv_pipeline_has_gs(pipeline)) {
2131 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2132 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2133 } else {
2134 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2135 }
2136 if (extra && extra->use_rectlist) {
2137 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2138 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2139 pipeline->graphics.can_use_guardband = true;
2140 }
2141 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2142 /* prim vertex count will need TESS changes */
2143 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2144
2145 /* Ensure that some export memory is always allocated, for two reasons:
2146 *
2147 * 1) Correctness: The hardware ignores the EXEC mask if no export
2148 * memory is allocated, so KILL and alpha test do not work correctly
2149 * without this.
2150 * 2) Performance: Every shader needs at least a NULL export, even when
2151 * it writes no color/depth output. The NULL export instruction
2152 * stalls without this setting.
2153 *
2154 * Don't add this to CB_SHADER_MASK.
2155 */
2156 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2157 if (!pipeline->graphics.blend.spi_shader_col_format) {
2158 if (!ps->info.fs.writes_z &&
2159 !ps->info.fs.writes_stencil &&
2160 !ps->info.fs.writes_sample_mask)
2161 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2162 }
2163
2164 unsigned z_order;
2165 pipeline->graphics.db_shader_control = 0;
2166 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2167 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2168 else
2169 z_order = V_02880C_LATE_Z;
2170
2171 pipeline->graphics.db_shader_control =
2172 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2173 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2174 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2175 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2176 S_02880C_Z_ORDER(z_order) |
2177 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2178 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2179 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2180
2181 pipeline->graphics.shader_z_format =
2182 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2183 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2184 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2185 V_028710_SPI_SHADER_ZERO;
2186
2187 calculate_vgt_gs_mode(pipeline);
2188 calculate_pa_cl_vs_out_cntl(pipeline);
2189 calculate_ps_inputs(pipeline);
2190
2191 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2192 if (pipeline->shaders[i]) {
2193 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2194 }
2195 }
2196
2197 uint32_t stages = 0;
2198 if (radv_pipeline_has_tess(pipeline)) {
2199 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2200 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2201
2202 if (radv_pipeline_has_gs(pipeline))
2203 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2204 S_028B54_GS_EN(1) |
2205 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2206 else
2207 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2208
2209 } else if (radv_pipeline_has_gs(pipeline))
2210 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2211 S_028B54_GS_EN(1) |
2212 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2213
2214 if (device->physical_device->rad_info.chip_class >= GFX9)
2215 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2216
2217 pipeline->graphics.vgt_shader_stages_en = stages;
2218
2219 if (radv_pipeline_has_gs(pipeline))
2220 calculate_gs_ring_sizes(pipeline);
2221
2222 if (radv_pipeline_has_tess(pipeline)) {
2223 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2224 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2225 pipeline->graphics.prim_vertex_count.incr = 1;
2226 }
2227 calculate_tess_state(pipeline, pCreateInfo);
2228 }
2229
2230 const VkPipelineVertexInputStateCreateInfo *vi_info =
2231 pCreateInfo->pVertexInputState;
2232 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2233 const VkVertexInputAttributeDescription *desc =
2234 &vi_info->pVertexAttributeDescriptions[i];
2235 unsigned loc = desc->location;
2236 const struct vk_format_description *format_desc;
2237 int first_non_void;
2238 uint32_t num_format, data_format;
2239 format_desc = vk_format_description(desc->format);
2240 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2241
2242 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2243 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2244
2245 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2246 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2247 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2248 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2249 S_008F0C_NUM_FORMAT(num_format) |
2250 S_008F0C_DATA_FORMAT(data_format);
2251 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2252 pipeline->va_offset[loc] = desc->offset;
2253 pipeline->va_binding[loc] = desc->binding;
2254 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2255 }
2256
2257 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2258 const VkVertexInputBindingDescription *desc =
2259 &vi_info->pVertexBindingDescriptions[i];
2260
2261 pipeline->binding_stride[desc->binding] = desc->stride;
2262 }
2263
2264 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2265 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2266 if (loc->sgpr_idx != -1) {
2267 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2268 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2269 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2270 pipeline->graphics.vtx_emit_num = 3;
2271 else
2272 pipeline->graphics.vtx_emit_num = 2;
2273 }
2274 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2275 radv_dump_pipeline_stats(device, pipeline);
2276 }
2277
2278 result = radv_pipeline_scratch_init(device, pipeline);
2279 return result;
2280 }
2281
2282 VkResult
2283 radv_graphics_pipeline_create(
2284 VkDevice _device,
2285 VkPipelineCache _cache,
2286 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2287 const struct radv_graphics_pipeline_create_info *extra,
2288 const VkAllocationCallbacks *pAllocator,
2289 VkPipeline *pPipeline)
2290 {
2291 RADV_FROM_HANDLE(radv_device, device, _device);
2292 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2293 struct radv_pipeline *pipeline;
2294 VkResult result;
2295
2296 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2297 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2298 if (pipeline == NULL)
2299 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2300
2301 memset(pipeline, 0, sizeof(*pipeline));
2302 result = radv_pipeline_init(pipeline, device, cache,
2303 pCreateInfo, extra, pAllocator);
2304 if (result != VK_SUCCESS) {
2305 radv_pipeline_destroy(device, pipeline, pAllocator);
2306 return result;
2307 }
2308
2309 *pPipeline = radv_pipeline_to_handle(pipeline);
2310
2311 return VK_SUCCESS;
2312 }
2313
2314 VkResult radv_CreateGraphicsPipelines(
2315 VkDevice _device,
2316 VkPipelineCache pipelineCache,
2317 uint32_t count,
2318 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2319 const VkAllocationCallbacks* pAllocator,
2320 VkPipeline* pPipelines)
2321 {
2322 VkResult result = VK_SUCCESS;
2323 unsigned i = 0;
2324
2325 for (; i < count; i++) {
2326 VkResult r;
2327 r = radv_graphics_pipeline_create(_device,
2328 pipelineCache,
2329 &pCreateInfos[i],
2330 NULL, pAllocator, &pPipelines[i]);
2331 if (r != VK_SUCCESS) {
2332 result = r;
2333 pPipelines[i] = VK_NULL_HANDLE;
2334 }
2335 }
2336
2337 return result;
2338 }
2339
2340 static VkResult radv_compute_pipeline_create(
2341 VkDevice _device,
2342 VkPipelineCache _cache,
2343 const VkComputePipelineCreateInfo* pCreateInfo,
2344 const VkAllocationCallbacks* pAllocator,
2345 VkPipeline* pPipeline)
2346 {
2347 RADV_FROM_HANDLE(radv_device, device, _device);
2348 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2349 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2350 struct radv_pipeline *pipeline;
2351 VkResult result;
2352
2353 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2354 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2355 if (pipeline == NULL)
2356 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2357
2358 memset(pipeline, 0, sizeof(*pipeline));
2359 pipeline->device = device;
2360 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2361
2362 pipeline->shaders[MESA_SHADER_COMPUTE] =
2363 radv_pipeline_compile(pipeline, cache, module,
2364 pCreateInfo->stage.pName,
2365 MESA_SHADER_COMPUTE,
2366 pCreateInfo->stage.pSpecializationInfo,
2367 pipeline->layout, NULL);
2368
2369
2370 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2371 result = radv_pipeline_scratch_init(device, pipeline);
2372 if (result != VK_SUCCESS) {
2373 radv_pipeline_destroy(device, pipeline, pAllocator);
2374 return result;
2375 }
2376
2377 *pPipeline = radv_pipeline_to_handle(pipeline);
2378
2379 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2380 radv_dump_pipeline_stats(device, pipeline);
2381 }
2382 return VK_SUCCESS;
2383 }
2384 VkResult radv_CreateComputePipelines(
2385 VkDevice _device,
2386 VkPipelineCache pipelineCache,
2387 uint32_t count,
2388 const VkComputePipelineCreateInfo* pCreateInfos,
2389 const VkAllocationCallbacks* pAllocator,
2390 VkPipeline* pPipelines)
2391 {
2392 VkResult result = VK_SUCCESS;
2393
2394 unsigned i = 0;
2395 for (; i < count; i++) {
2396 VkResult r;
2397 r = radv_compute_pipeline_create(_device, pipelineCache,
2398 &pCreateInfos[i],
2399 pAllocator, &pPipelines[i]);
2400 if (r != VK_SUCCESS) {
2401 result = r;
2402 pPipelines[i] = VK_NULL_HANDLE;
2403 }
2404 }
2405
2406 return result;
2407 }