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radv: ignore pDepthStencilState if rasterization is disabled
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
43
44 #include "sid.h"
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
53
54 struct radv_blend_state {
55 uint32_t blend_enable_4bit;
56 uint32_t need_src_alpha;
57
58 uint32_t cb_color_control;
59 uint32_t cb_target_mask;
60 uint32_t cb_target_enabled_4bit;
61 uint32_t sx_mrt_blend_opt[8];
62 uint32_t cb_blend_control[8];
63
64 uint32_t spi_shader_col_format;
65 uint32_t cb_shader_mask;
66 uint32_t db_alpha_to_mask;
67
68 uint32_t commutative_4bit;
69
70 bool single_cb_enable;
71 bool mrt0_is_dual_src;
72 };
73
74 struct radv_dsa_order_invariance {
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
77 */
78 bool zs;
79
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
82 * fragments arrive.
83 */
84 bool pass_set;
85 };
86
87 struct radv_tessellation_state {
88 uint32_t ls_hs_config;
89 unsigned num_patches;
90 unsigned lds_size;
91 uint32_t tf_param;
92 };
93
94 static const VkPipelineMultisampleStateCreateInfo *
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
96 {
97 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
98 return pCreateInfo->pMultisampleState;
99 return NULL;
100 }
101
102 static const VkPipelineTessellationStateCreateInfo *
103 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
104 {
105 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
106 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
107 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
108 return pCreateInfo->pTessellationState;
109 }
110 }
111 return NULL;
112 }
113
114 static const VkPipelineDepthStencilStateCreateInfo *
115 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
116 {
117 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
118 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
119
120 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
121 subpass->depth_stencil_attachment)
122 return pCreateInfo->pDepthStencilState;
123 return NULL;
124 }
125
126 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
127 {
128 struct radv_shader_variant *variant = NULL;
129 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
130 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
131 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
132 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
133 else if (pipeline->shaders[MESA_SHADER_VERTEX])
134 variant = pipeline->shaders[MESA_SHADER_VERTEX];
135 else
136 return false;
137 return variant->info.is_ngg;
138 }
139
140 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
141 {
142 if (!radv_pipeline_has_gs(pipeline))
143 return false;
144
145 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
146 * On GFX10, it might be required in rare cases if it's not possible to
147 * enable NGG.
148 */
149 if (radv_pipeline_has_ngg(pipeline))
150 return false;
151
152 assert(pipeline->gs_copy_shader);
153 return true;
154 }
155
156 static void
157 radv_pipeline_destroy(struct radv_device *device,
158 struct radv_pipeline *pipeline,
159 const VkAllocationCallbacks* allocator)
160 {
161 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
162 if (pipeline->shaders[i])
163 radv_shader_variant_destroy(device, pipeline->shaders[i]);
164
165 if (pipeline->gs_copy_shader)
166 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
167
168 if(pipeline->cs.buf)
169 free(pipeline->cs.buf);
170 vk_free2(&device->alloc, allocator, pipeline);
171 }
172
173 void radv_DestroyPipeline(
174 VkDevice _device,
175 VkPipeline _pipeline,
176 const VkAllocationCallbacks* pAllocator)
177 {
178 RADV_FROM_HANDLE(radv_device, device, _device);
179 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
180
181 if (!_pipeline)
182 return;
183
184 radv_pipeline_destroy(device, pipeline, pAllocator);
185 }
186
187 static uint32_t get_hash_flags(struct radv_device *device)
188 {
189 uint32_t hash_flags = 0;
190
191 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
192 hash_flags |= RADV_HASH_SHADER_NO_NGG;
193 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
194 hash_flags |= RADV_HASH_SHADER_SISCHED;
195 if (device->physical_device->cs_wave_size == 32)
196 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
197 if (device->physical_device->ps_wave_size == 32)
198 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
199 if (device->physical_device->ge_wave_size == 32)
200 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
201 if (device->physical_device->use_aco)
202 hash_flags |= RADV_HASH_SHADER_ACO;
203 return hash_flags;
204 }
205
206 static VkResult
207 radv_pipeline_scratch_init(struct radv_device *device,
208 struct radv_pipeline *pipeline)
209 {
210 unsigned scratch_bytes_per_wave = 0;
211 unsigned max_waves = 0;
212 unsigned min_waves = 1;
213
214 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
215 if (pipeline->shaders[i] &&
216 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
217 unsigned max_stage_waves = device->scratch_waves;
218
219 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
220 pipeline->shaders[i]->config.scratch_bytes_per_wave);
221
222 max_stage_waves = MIN2(max_stage_waves,
223 4 * device->physical_device->rad_info.num_good_compute_units *
224 (256 / pipeline->shaders[i]->config.num_vgprs));
225 max_waves = MAX2(max_waves, max_stage_waves);
226 }
227 }
228
229 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
230 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
231 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
232 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
233 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
234 }
235
236 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
237 pipeline->max_waves = max_waves;
238 return VK_SUCCESS;
239 }
240
241 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
242 {
243 switch (op) {
244 case VK_LOGIC_OP_CLEAR:
245 return V_028808_ROP3_CLEAR;
246 case VK_LOGIC_OP_AND:
247 return V_028808_ROP3_AND;
248 case VK_LOGIC_OP_AND_REVERSE:
249 return V_028808_ROP3_AND_REVERSE;
250 case VK_LOGIC_OP_COPY:
251 return V_028808_ROP3_COPY;
252 case VK_LOGIC_OP_AND_INVERTED:
253 return V_028808_ROP3_AND_INVERTED;
254 case VK_LOGIC_OP_NO_OP:
255 return V_028808_ROP3_NO_OP;
256 case VK_LOGIC_OP_XOR:
257 return V_028808_ROP3_XOR;
258 case VK_LOGIC_OP_OR:
259 return V_028808_ROP3_OR;
260 case VK_LOGIC_OP_NOR:
261 return V_028808_ROP3_NOR;
262 case VK_LOGIC_OP_EQUIVALENT:
263 return V_028808_ROP3_EQUIVALENT;
264 case VK_LOGIC_OP_INVERT:
265 return V_028808_ROP3_INVERT;
266 case VK_LOGIC_OP_OR_REVERSE:
267 return V_028808_ROP3_OR_REVERSE;
268 case VK_LOGIC_OP_COPY_INVERTED:
269 return V_028808_ROP3_COPY_INVERTED;
270 case VK_LOGIC_OP_OR_INVERTED:
271 return V_028808_ROP3_OR_INVERTED;
272 case VK_LOGIC_OP_NAND:
273 return V_028808_ROP3_NAND;
274 case VK_LOGIC_OP_SET:
275 return V_028808_ROP3_SET;
276 default:
277 unreachable("Unhandled logic op");
278 }
279 }
280
281
282 static uint32_t si_translate_blend_function(VkBlendOp op)
283 {
284 switch (op) {
285 case VK_BLEND_OP_ADD:
286 return V_028780_COMB_DST_PLUS_SRC;
287 case VK_BLEND_OP_SUBTRACT:
288 return V_028780_COMB_SRC_MINUS_DST;
289 case VK_BLEND_OP_REVERSE_SUBTRACT:
290 return V_028780_COMB_DST_MINUS_SRC;
291 case VK_BLEND_OP_MIN:
292 return V_028780_COMB_MIN_DST_SRC;
293 case VK_BLEND_OP_MAX:
294 return V_028780_COMB_MAX_DST_SRC;
295 default:
296 return 0;
297 }
298 }
299
300 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
301 {
302 switch (factor) {
303 case VK_BLEND_FACTOR_ZERO:
304 return V_028780_BLEND_ZERO;
305 case VK_BLEND_FACTOR_ONE:
306 return V_028780_BLEND_ONE;
307 case VK_BLEND_FACTOR_SRC_COLOR:
308 return V_028780_BLEND_SRC_COLOR;
309 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case VK_BLEND_FACTOR_DST_COLOR:
312 return V_028780_BLEND_DST_COLOR;
313 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
314 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
315 case VK_BLEND_FACTOR_SRC_ALPHA:
316 return V_028780_BLEND_SRC_ALPHA;
317 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
318 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
319 case VK_BLEND_FACTOR_DST_ALPHA:
320 return V_028780_BLEND_DST_ALPHA;
321 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
322 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
323 case VK_BLEND_FACTOR_CONSTANT_COLOR:
324 return V_028780_BLEND_CONSTANT_COLOR;
325 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
326 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
327 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
328 return V_028780_BLEND_CONSTANT_ALPHA;
329 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
330 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
331 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
332 return V_028780_BLEND_SRC_ALPHA_SATURATE;
333 case VK_BLEND_FACTOR_SRC1_COLOR:
334 return V_028780_BLEND_SRC1_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
336 return V_028780_BLEND_INV_SRC1_COLOR;
337 case VK_BLEND_FACTOR_SRC1_ALPHA:
338 return V_028780_BLEND_SRC1_ALPHA;
339 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
340 return V_028780_BLEND_INV_SRC1_ALPHA;
341 default:
342 return 0;
343 }
344 }
345
346 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
347 {
348 switch (op) {
349 case VK_BLEND_OP_ADD:
350 return V_028760_OPT_COMB_ADD;
351 case VK_BLEND_OP_SUBTRACT:
352 return V_028760_OPT_COMB_SUBTRACT;
353 case VK_BLEND_OP_REVERSE_SUBTRACT:
354 return V_028760_OPT_COMB_REVSUBTRACT;
355 case VK_BLEND_OP_MIN:
356 return V_028760_OPT_COMB_MIN;
357 case VK_BLEND_OP_MAX:
358 return V_028760_OPT_COMB_MAX;
359 default:
360 return V_028760_OPT_COMB_BLEND_DISABLED;
361 }
362 }
363
364 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
365 {
366 switch (factor) {
367 case VK_BLEND_FACTOR_ZERO:
368 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
369 case VK_BLEND_FACTOR_ONE:
370 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
371 case VK_BLEND_FACTOR_SRC_COLOR:
372 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
373 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
374 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
375 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
376 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
377 case VK_BLEND_FACTOR_SRC_ALPHA:
378 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
379 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
380 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
381 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
382 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
383 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
384 default:
385 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
386 }
387 }
388
389 /**
390 * Get rid of DST in the blend factors by commuting the operands:
391 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
392 */
393 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
394 unsigned *dst_factor, unsigned expected_dst,
395 unsigned replacement_src)
396 {
397 if (*src_factor == expected_dst &&
398 *dst_factor == VK_BLEND_FACTOR_ZERO) {
399 *src_factor = VK_BLEND_FACTOR_ZERO;
400 *dst_factor = replacement_src;
401
402 /* Commuting the operands requires reversing subtractions. */
403 if (*func == VK_BLEND_OP_SUBTRACT)
404 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
405 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
406 *func = VK_BLEND_OP_SUBTRACT;
407 }
408 }
409
410 static bool si_blend_factor_uses_dst(unsigned factor)
411 {
412 return factor == VK_BLEND_FACTOR_DST_COLOR ||
413 factor == VK_BLEND_FACTOR_DST_ALPHA ||
414 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
415 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
416 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
417 }
418
419 static bool is_dual_src(VkBlendFactor factor)
420 {
421 switch (factor) {
422 case VK_BLEND_FACTOR_SRC1_COLOR:
423 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
424 case VK_BLEND_FACTOR_SRC1_ALPHA:
425 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
426 return true;
427 default:
428 return false;
429 }
430 }
431
432 static unsigned si_choose_spi_color_format(VkFormat vk_format,
433 bool blend_enable,
434 bool blend_need_alpha)
435 {
436 const struct vk_format_description *desc = vk_format_description(vk_format);
437 unsigned format, ntype, swap;
438
439 /* Alpha is needed for alpha-to-coverage.
440 * Blending may be with or without alpha.
441 */
442 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
443 unsigned alpha = 0; /* exports alpha, but may not support blending */
444 unsigned blend = 0; /* supports blending, but may not export alpha */
445 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
446
447 format = radv_translate_colorformat(vk_format);
448 ntype = radv_translate_color_numformat(vk_format, desc,
449 vk_format_get_first_non_void_channel(vk_format));
450 swap = radv_translate_colorswap(vk_format, false);
451
452 /* Choose the SPI color formats. These are required values for Stoney/RB+.
453 * Other chips have multiple choices, though they are not necessarily better.
454 */
455 switch (format) {
456 case V_028C70_COLOR_5_6_5:
457 case V_028C70_COLOR_1_5_5_5:
458 case V_028C70_COLOR_5_5_5_1:
459 case V_028C70_COLOR_4_4_4_4:
460 case V_028C70_COLOR_10_11_11:
461 case V_028C70_COLOR_11_11_10:
462 case V_028C70_COLOR_8:
463 case V_028C70_COLOR_8_8:
464 case V_028C70_COLOR_8_8_8_8:
465 case V_028C70_COLOR_10_10_10_2:
466 case V_028C70_COLOR_2_10_10_10:
467 if (ntype == V_028C70_NUMBER_UINT)
468 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
469 else if (ntype == V_028C70_NUMBER_SINT)
470 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
471 else
472 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
473 break;
474
475 case V_028C70_COLOR_16:
476 case V_028C70_COLOR_16_16:
477 case V_028C70_COLOR_16_16_16_16:
478 if (ntype == V_028C70_NUMBER_UNORM ||
479 ntype == V_028C70_NUMBER_SNORM) {
480 /* UNORM16 and SNORM16 don't support blending */
481 if (ntype == V_028C70_NUMBER_UNORM)
482 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
483 else
484 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
485
486 /* Use 32 bits per channel for blending. */
487 if (format == V_028C70_COLOR_16) {
488 if (swap == V_028C70_SWAP_STD) { /* R */
489 blend = V_028714_SPI_SHADER_32_R;
490 blend_alpha = V_028714_SPI_SHADER_32_AR;
491 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
492 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
493 else
494 assert(0);
495 } else if (format == V_028C70_COLOR_16_16) {
496 if (swap == V_028C70_SWAP_STD) { /* RG */
497 blend = V_028714_SPI_SHADER_32_GR;
498 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
499 } else if (swap == V_028C70_SWAP_ALT) /* RA */
500 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
501 else
502 assert(0);
503 } else /* 16_16_16_16 */
504 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
505 } else if (ntype == V_028C70_NUMBER_UINT)
506 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
507 else if (ntype == V_028C70_NUMBER_SINT)
508 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
509 else if (ntype == V_028C70_NUMBER_FLOAT)
510 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
511 else
512 assert(0);
513 break;
514
515 case V_028C70_COLOR_32:
516 if (swap == V_028C70_SWAP_STD) { /* R */
517 blend = normal = V_028714_SPI_SHADER_32_R;
518 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
519 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
520 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
521 else
522 assert(0);
523 break;
524
525 case V_028C70_COLOR_32_32:
526 if (swap == V_028C70_SWAP_STD) { /* RG */
527 blend = normal = V_028714_SPI_SHADER_32_GR;
528 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
529 } else if (swap == V_028C70_SWAP_ALT) /* RA */
530 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
531 else
532 assert(0);
533 break;
534
535 case V_028C70_COLOR_32_32_32_32:
536 case V_028C70_COLOR_8_24:
537 case V_028C70_COLOR_24_8:
538 case V_028C70_COLOR_X24_8_32_FLOAT:
539 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
540 break;
541
542 default:
543 unreachable("unhandled blend format");
544 }
545
546 if (blend_enable && blend_need_alpha)
547 return blend_alpha;
548 else if(blend_need_alpha)
549 return alpha;
550 else if(blend_enable)
551 return blend;
552 else
553 return normal;
554 }
555
556 static void
557 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
558 const VkGraphicsPipelineCreateInfo *pCreateInfo,
559 struct radv_blend_state *blend)
560 {
561 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
562 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
563 unsigned col_format = 0;
564 unsigned num_targets;
565
566 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
567 unsigned cf;
568
569 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
570 cf = V_028714_SPI_SHADER_ZERO;
571 } else {
572 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
573 bool blend_enable =
574 blend->blend_enable_4bit & (0xfu << (i * 4));
575
576 cf = si_choose_spi_color_format(attachment->format,
577 blend_enable,
578 blend->need_src_alpha & (1 << i));
579 }
580
581 col_format |= cf << (4 * i);
582 }
583
584 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
585 /* When a subpass doesn't have any color attachments, write the
586 * alpha channel of MRT0 when alpha coverage is enabled because
587 * the depth attachment needs it.
588 */
589 col_format |= V_028714_SPI_SHADER_32_AR;
590 }
591
592 /* If the i-th target format is set, all previous target formats must
593 * be non-zero to avoid hangs.
594 */
595 num_targets = (util_last_bit(col_format) + 3) / 4;
596 for (unsigned i = 0; i < num_targets; i++) {
597 if (!(col_format & (0xf << (i * 4)))) {
598 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
599 }
600 }
601
602 /* The output for dual source blending should have the same format as
603 * the first output.
604 */
605 if (blend->mrt0_is_dual_src)
606 col_format |= (col_format & 0xf) << 4;
607
608 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
609 blend->spi_shader_col_format = col_format;
610 }
611
612 static bool
613 format_is_int8(VkFormat format)
614 {
615 const struct vk_format_description *desc = vk_format_description(format);
616 int channel = vk_format_get_first_non_void_channel(format);
617
618 return channel >= 0 && desc->channel[channel].pure_integer &&
619 desc->channel[channel].size == 8;
620 }
621
622 static bool
623 format_is_int10(VkFormat format)
624 {
625 const struct vk_format_description *desc = vk_format_description(format);
626
627 if (desc->nr_channels != 4)
628 return false;
629 for (unsigned i = 0; i < 4; i++) {
630 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
631 return true;
632 }
633 return false;
634 }
635
636 /*
637 * Ordered so that for each i,
638 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
639 */
640 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
641 VK_FORMAT_R32_SFLOAT,
642 VK_FORMAT_R32G32_SFLOAT,
643 VK_FORMAT_R8G8B8A8_UNORM,
644 VK_FORMAT_R16G16B16A16_UNORM,
645 VK_FORMAT_R16G16B16A16_SNORM,
646 VK_FORMAT_R16G16B16A16_UINT,
647 VK_FORMAT_R16G16B16A16_SINT,
648 VK_FORMAT_R32G32B32A32_SFLOAT,
649 VK_FORMAT_R8G8B8A8_UINT,
650 VK_FORMAT_R8G8B8A8_SINT,
651 VK_FORMAT_A2R10G10B10_UINT_PACK32,
652 VK_FORMAT_A2R10G10B10_SINT_PACK32,
653 };
654
655 unsigned radv_format_meta_fs_key(VkFormat format)
656 {
657 unsigned col_format = si_choose_spi_color_format(format, false, false);
658
659 assert(col_format != V_028714_SPI_SHADER_32_AR);
660 if (col_format >= V_028714_SPI_SHADER_32_AR)
661 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
662
663 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
664 bool is_int8 = format_is_int8(format);
665 bool is_int10 = format_is_int10(format);
666
667 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
668 }
669
670 static void
671 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
672 unsigned *is_int8, unsigned *is_int10)
673 {
674 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
675 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
676 *is_int8 = 0;
677 *is_int10 = 0;
678
679 for (unsigned i = 0; i < subpass->color_count; ++i) {
680 struct radv_render_pass_attachment *attachment;
681
682 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
683 continue;
684
685 attachment = pass->attachments + subpass->color_attachments[i].attachment;
686
687 if (format_is_int8(attachment->format))
688 *is_int8 |= 1 << i;
689 if (format_is_int10(attachment->format))
690 *is_int10 |= 1 << i;
691 }
692 }
693
694 static void
695 radv_blend_check_commutativity(struct radv_blend_state *blend,
696 VkBlendOp op, VkBlendFactor src,
697 VkBlendFactor dst, unsigned chanmask)
698 {
699 /* Src factor is allowed when it does not depend on Dst. */
700 static const uint32_t src_allowed =
701 (1u << VK_BLEND_FACTOR_ONE) |
702 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
703 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
704 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
705 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
706 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
707 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
708 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
709 (1u << VK_BLEND_FACTOR_ZERO) |
710 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
711 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
712 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
713 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
714 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
715 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
716
717 if (dst == VK_BLEND_FACTOR_ONE &&
718 (src_allowed & (1u << src))) {
719 /* Addition is commutative, but floating point addition isn't
720 * associative: subtle changes can be introduced via different
721 * rounding. Be conservative, only enable for min and max.
722 */
723 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
724 blend->commutative_4bit |= chanmask;
725 }
726 }
727
728 static struct radv_blend_state
729 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
730 const VkGraphicsPipelineCreateInfo *pCreateInfo,
731 const struct radv_graphics_pipeline_create_info *extra)
732 {
733 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
734 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
735 struct radv_blend_state blend = {0};
736 unsigned mode = V_028808_CB_NORMAL;
737 int i;
738
739 if (!vkblend)
740 return blend;
741
742 if (extra && extra->custom_blend_mode) {
743 blend.single_cb_enable = true;
744 mode = extra->custom_blend_mode;
745 }
746 blend.cb_color_control = 0;
747 if (vkblend->logicOpEnable)
748 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
749 else
750 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
751
752 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
753 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
754 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
755 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
756 S_028B70_OFFSET_ROUND(1);
757
758 if (vkms && vkms->alphaToCoverageEnable) {
759 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
760 blend.need_src_alpha |= 0x1;
761 }
762
763 blend.cb_target_mask = 0;
764 for (i = 0; i < vkblend->attachmentCount; i++) {
765 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
766 unsigned blend_cntl = 0;
767 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
768 VkBlendOp eqRGB = att->colorBlendOp;
769 VkBlendFactor srcRGB = att->srcColorBlendFactor;
770 VkBlendFactor dstRGB = att->dstColorBlendFactor;
771 VkBlendOp eqA = att->alphaBlendOp;
772 VkBlendFactor srcA = att->srcAlphaBlendFactor;
773 VkBlendFactor dstA = att->dstAlphaBlendFactor;
774
775 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
776
777 if (!att->colorWriteMask)
778 continue;
779
780 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
781 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
782 if (!att->blendEnable) {
783 blend.cb_blend_control[i] = blend_cntl;
784 continue;
785 }
786
787 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
788 if (i == 0)
789 blend.mrt0_is_dual_src = true;
790
791 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
792 srcRGB = VK_BLEND_FACTOR_ONE;
793 dstRGB = VK_BLEND_FACTOR_ONE;
794 }
795 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
796 srcA = VK_BLEND_FACTOR_ONE;
797 dstA = VK_BLEND_FACTOR_ONE;
798 }
799
800 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
801 0x7 << (4 * i));
802 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
803 0x8 << (4 * i));
804
805 /* Blending optimizations for RB+.
806 * These transformations don't change the behavior.
807 *
808 * First, get rid of DST in the blend factors:
809 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
810 */
811 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
812 VK_BLEND_FACTOR_DST_COLOR,
813 VK_BLEND_FACTOR_SRC_COLOR);
814
815 si_blend_remove_dst(&eqA, &srcA, &dstA,
816 VK_BLEND_FACTOR_DST_COLOR,
817 VK_BLEND_FACTOR_SRC_COLOR);
818
819 si_blend_remove_dst(&eqA, &srcA, &dstA,
820 VK_BLEND_FACTOR_DST_ALPHA,
821 VK_BLEND_FACTOR_SRC_ALPHA);
822
823 /* Look up the ideal settings from tables. */
824 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
825 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
826 srcA_opt = si_translate_blend_opt_factor(srcA, true);
827 dstA_opt = si_translate_blend_opt_factor(dstA, true);
828
829 /* Handle interdependencies. */
830 if (si_blend_factor_uses_dst(srcRGB))
831 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
832 if (si_blend_factor_uses_dst(srcA))
833 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
834
835 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
836 (dstRGB == VK_BLEND_FACTOR_ZERO ||
837 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
838 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
839 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
840
841 /* Set the final value. */
842 blend.sx_mrt_blend_opt[i] =
843 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
844 S_028760_COLOR_DST_OPT(dstRGB_opt) |
845 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
846 S_028760_ALPHA_SRC_OPT(srcA_opt) |
847 S_028760_ALPHA_DST_OPT(dstA_opt) |
848 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
849 blend_cntl |= S_028780_ENABLE(1);
850
851 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
852 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
853 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
854 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
855 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
856 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
857 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
858 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
859 }
860 blend.cb_blend_control[i] = blend_cntl;
861
862 blend.blend_enable_4bit |= 0xfu << (i * 4);
863
864 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
865 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
866 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
867 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
868 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
869 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
870 blend.need_src_alpha |= 1 << i;
871 }
872 for (i = vkblend->attachmentCount; i < 8; i++) {
873 blend.cb_blend_control[i] = 0;
874 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
875 }
876
877 if (pipeline->device->physical_device->rad_info.has_rbplus) {
878 /* Disable RB+ blend optimizations for dual source blending. */
879 if (blend.mrt0_is_dual_src) {
880 for (i = 0; i < 8; i++) {
881 blend.sx_mrt_blend_opt[i] =
882 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
883 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
884 }
885 }
886
887 /* RB+ doesn't work with dual source blending, logic op and
888 * RESOLVE.
889 */
890 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
891 mode == V_028808_CB_RESOLVE)
892 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
893 }
894
895 if (blend.cb_target_mask)
896 blend.cb_color_control |= S_028808_MODE(mode);
897 else
898 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
899
900 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
901 return blend;
902 }
903
904 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
905 {
906 switch (op) {
907 case VK_STENCIL_OP_KEEP:
908 return V_02842C_STENCIL_KEEP;
909 case VK_STENCIL_OP_ZERO:
910 return V_02842C_STENCIL_ZERO;
911 case VK_STENCIL_OP_REPLACE:
912 return V_02842C_STENCIL_REPLACE_TEST;
913 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
914 return V_02842C_STENCIL_ADD_CLAMP;
915 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
916 return V_02842C_STENCIL_SUB_CLAMP;
917 case VK_STENCIL_OP_INVERT:
918 return V_02842C_STENCIL_INVERT;
919 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
920 return V_02842C_STENCIL_ADD_WRAP;
921 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
922 return V_02842C_STENCIL_SUB_WRAP;
923 default:
924 return 0;
925 }
926 }
927
928 static uint32_t si_translate_fill(VkPolygonMode func)
929 {
930 switch(func) {
931 case VK_POLYGON_MODE_FILL:
932 return V_028814_X_DRAW_TRIANGLES;
933 case VK_POLYGON_MODE_LINE:
934 return V_028814_X_DRAW_LINES;
935 case VK_POLYGON_MODE_POINT:
936 return V_028814_X_DRAW_POINTS;
937 default:
938 assert(0);
939 return V_028814_X_DRAW_POINTS;
940 }
941 }
942
943 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
944 {
945 uint32_t num_samples = vkms->rasterizationSamples;
946 uint32_t ps_iter_samples = 1;
947
948 if (vkms->sampleShadingEnable) {
949 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
950 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
951 }
952 return ps_iter_samples;
953 }
954
955 static bool
956 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
957 {
958 return pCreateInfo->depthTestEnable &&
959 pCreateInfo->depthWriteEnable &&
960 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
961 }
962
963 static bool
964 radv_writes_stencil(const VkStencilOpState *state)
965 {
966 return state->writeMask &&
967 (state->failOp != VK_STENCIL_OP_KEEP ||
968 state->passOp != VK_STENCIL_OP_KEEP ||
969 state->depthFailOp != VK_STENCIL_OP_KEEP);
970 }
971
972 static bool
973 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
974 {
975 return pCreateInfo->stencilTestEnable &&
976 (radv_writes_stencil(&pCreateInfo->front) ||
977 radv_writes_stencil(&pCreateInfo->back));
978 }
979
980 static bool
981 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
982 {
983 return radv_is_depth_write_enabled(pCreateInfo) ||
984 radv_is_stencil_write_enabled(pCreateInfo);
985 }
986
987 static bool
988 radv_order_invariant_stencil_op(VkStencilOp op)
989 {
990 /* REPLACE is normally order invariant, except when the stencil
991 * reference value is written by the fragment shader. Tracking this
992 * interaction does not seem worth the effort, so be conservative.
993 */
994 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
995 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
996 op != VK_STENCIL_OP_REPLACE;
997 }
998
999 static bool
1000 radv_order_invariant_stencil_state(const VkStencilOpState *state)
1001 {
1002 /* Compute whether, assuming Z writes are disabled, this stencil state
1003 * is order invariant in the sense that the set of passing fragments as
1004 * well as the final stencil buffer result does not depend on the order
1005 * of fragments.
1006 */
1007 return !state->writeMask ||
1008 /* The following assumes that Z writes are disabled. */
1009 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
1010 radv_order_invariant_stencil_op(state->passOp) &&
1011 radv_order_invariant_stencil_op(state->depthFailOp)) ||
1012 (state->compareOp == VK_COMPARE_OP_NEVER &&
1013 radv_order_invariant_stencil_op(state->failOp));
1014 }
1015
1016 static bool
1017 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1018 struct radv_blend_state *blend,
1019 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1020 {
1021 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1022 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1023 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
1024 unsigned colormask = blend->cb_target_enabled_4bit;
1025
1026 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1027 return false;
1028
1029 /* Be conservative if a logic operation is enabled with color buffers. */
1030 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1031 return false;
1032
1033 /* Default depth/stencil invariance when no attachment is bound. */
1034 struct radv_dsa_order_invariance dsa_order_invariant = {
1035 .zs = true, .pass_set = true
1036 };
1037
1038 if (vkds) {
1039 struct radv_render_pass_attachment *attachment =
1040 pass->attachments + subpass->depth_stencil_attachment->attachment;
1041 bool has_stencil = vk_format_is_stencil(attachment->format);
1042 struct radv_dsa_order_invariance order_invariance[2];
1043 struct radv_shader_variant *ps =
1044 pipeline->shaders[MESA_SHADER_FRAGMENT];
1045
1046 /* Compute depth/stencil order invariance in order to know if
1047 * it's safe to enable out-of-order.
1048 */
1049 bool zfunc_is_ordered =
1050 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1051 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1052 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1053 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1054 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1055
1056 bool nozwrite_and_order_invariant_stencil =
1057 !radv_is_ds_write_enabled(vkds) ||
1058 (!radv_is_depth_write_enabled(vkds) &&
1059 radv_order_invariant_stencil_state(&vkds->front) &&
1060 radv_order_invariant_stencil_state(&vkds->back));
1061
1062 order_invariance[1].zs =
1063 nozwrite_and_order_invariant_stencil ||
1064 (!radv_is_stencil_write_enabled(vkds) &&
1065 zfunc_is_ordered);
1066 order_invariance[0].zs =
1067 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1068
1069 order_invariance[1].pass_set =
1070 nozwrite_and_order_invariant_stencil ||
1071 (!radv_is_stencil_write_enabled(vkds) &&
1072 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1073 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1074 order_invariance[0].pass_set =
1075 !radv_is_depth_write_enabled(vkds) ||
1076 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1077 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1078
1079 dsa_order_invariant = order_invariance[has_stencil];
1080 if (!dsa_order_invariant.zs)
1081 return false;
1082
1083 /* The set of PS invocations is always order invariant,
1084 * except when early Z/S tests are requested.
1085 */
1086 if (ps &&
1087 ps->info.ps.writes_memory &&
1088 ps->info.ps.early_fragment_test &&
1089 !dsa_order_invariant.pass_set)
1090 return false;
1091
1092 /* Determine if out-of-order rasterization should be disabled
1093 * when occlusion queries are used.
1094 */
1095 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1096 !dsa_order_invariant.pass_set;
1097 }
1098
1099 /* No color buffers are enabled for writing. */
1100 if (!colormask)
1101 return true;
1102
1103 unsigned blendmask = colormask & blend->blend_enable_4bit;
1104
1105 if (blendmask) {
1106 /* Only commutative blending. */
1107 if (blendmask & ~blend->commutative_4bit)
1108 return false;
1109
1110 if (!dsa_order_invariant.pass_set)
1111 return false;
1112 }
1113
1114 if (colormask & ~blendmask)
1115 return false;
1116
1117 return true;
1118 }
1119
1120 static void
1121 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1122 struct radv_blend_state *blend,
1123 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1124 {
1125 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1126 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1127 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1128 bool out_of_order_rast = false;
1129 int ps_iter_samples = 1;
1130 uint32_t mask = 0xffff;
1131
1132 if (vkms) {
1133 ms->num_samples = vkms->rasterizationSamples;
1134
1135 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1136 *
1137 * "Sample shading is enabled for a graphics pipeline:
1138 *
1139 * - If the interface of the fragment shader entry point of the
1140 * graphics pipeline includes an input variable decorated
1141 * with SampleId or SamplePosition. In this case
1142 * minSampleShadingFactor takes the value 1.0.
1143 * - Else if the sampleShadingEnable member of the
1144 * VkPipelineMultisampleStateCreateInfo structure specified
1145 * when creating the graphics pipeline is set to VK_TRUE. In
1146 * this case minSampleShadingFactor takes the value of
1147 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1148 *
1149 * Otherwise, sample shading is considered disabled."
1150 */
1151 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1152 ps_iter_samples = ms->num_samples;
1153 } else {
1154 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1155 }
1156 } else {
1157 ms->num_samples = 1;
1158 }
1159
1160 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1161 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1162 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1163 /* Out-of-order rasterization is explicitly enabled by the
1164 * application.
1165 */
1166 out_of_order_rast = true;
1167 } else {
1168 /* Determine if the driver can enable out-of-order
1169 * rasterization internally.
1170 */
1171 out_of_order_rast =
1172 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1173 }
1174
1175 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1176 ms->pa_sc_aa_config = 0;
1177 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1178 S_028804_INCOHERENT_EQAA_READS(1) |
1179 S_028804_INTERPOLATE_COMP_Z(1) |
1180 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1181 ms->pa_sc_mode_cntl_1 =
1182 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1183 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1184 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1185 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1186 /* always 1: */
1187 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1188 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1189 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1190 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1191 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1192 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1193 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1194 S_028A48_VPORT_SCISSOR_ENABLE(1);
1195
1196 if (ms->num_samples > 1) {
1197 unsigned log_samples = util_logbase2(ms->num_samples);
1198 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1199 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1200 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1201 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1202 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1203 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1204 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1205 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1206 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1207 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1208 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1209 if (ps_iter_samples > 1)
1210 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1211 }
1212
1213 if (vkms && vkms->pSampleMask) {
1214 mask = vkms->pSampleMask[0] & 0xffff;
1215 }
1216
1217 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1218 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1219 }
1220
1221 static bool
1222 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1223 {
1224 switch (topology) {
1225 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1230 return false;
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1236 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1237 return true;
1238 default:
1239 unreachable("unhandled primitive type");
1240 }
1241 }
1242
1243 static uint32_t
1244 si_translate_prim(enum VkPrimitiveTopology topology)
1245 {
1246 switch (topology) {
1247 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1248 return V_008958_DI_PT_POINTLIST;
1249 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1250 return V_008958_DI_PT_LINELIST;
1251 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1252 return V_008958_DI_PT_LINESTRIP;
1253 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1254 return V_008958_DI_PT_TRILIST;
1255 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1256 return V_008958_DI_PT_TRISTRIP;
1257 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1258 return V_008958_DI_PT_TRIFAN;
1259 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1260 return V_008958_DI_PT_LINELIST_ADJ;
1261 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1262 return V_008958_DI_PT_LINESTRIP_ADJ;
1263 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1264 return V_008958_DI_PT_TRILIST_ADJ;
1265 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1266 return V_008958_DI_PT_TRISTRIP_ADJ;
1267 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1268 return V_008958_DI_PT_PATCH;
1269 default:
1270 assert(0);
1271 return 0;
1272 }
1273 }
1274
1275 static uint32_t
1276 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1277 {
1278 switch (gl_prim) {
1279 case 0: /* GL_POINTS */
1280 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1281 case 1: /* GL_LINES */
1282 case 3: /* GL_LINE_STRIP */
1283 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1284 case 0x8E7A: /* GL_ISOLINES */
1285 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1286
1287 case 4: /* GL_TRIANGLES */
1288 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1289 case 5: /* GL_TRIANGLE_STRIP */
1290 case 7: /* GL_QUADS */
1291 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1292 default:
1293 assert(0);
1294 return 0;
1295 }
1296 }
1297
1298 static uint32_t
1299 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1300 {
1301 switch (topology) {
1302 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1303 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1304 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1305 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1306 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1307 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1308 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1309 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1310 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1311 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1312 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1313 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1314 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1315 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1316 default:
1317 assert(0);
1318 return 0;
1319 }
1320 }
1321
1322 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1323 {
1324 switch(state) {
1325 case VK_DYNAMIC_STATE_VIEWPORT:
1326 return RADV_DYNAMIC_VIEWPORT;
1327 case VK_DYNAMIC_STATE_SCISSOR:
1328 return RADV_DYNAMIC_SCISSOR;
1329 case VK_DYNAMIC_STATE_LINE_WIDTH:
1330 return RADV_DYNAMIC_LINE_WIDTH;
1331 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1332 return RADV_DYNAMIC_DEPTH_BIAS;
1333 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1334 return RADV_DYNAMIC_BLEND_CONSTANTS;
1335 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1336 return RADV_DYNAMIC_DEPTH_BOUNDS;
1337 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1338 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1339 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1340 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1341 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1342 return RADV_DYNAMIC_STENCIL_REFERENCE;
1343 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1344 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1345 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1346 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1347 default:
1348 unreachable("Unhandled dynamic state");
1349 }
1350 }
1351
1352 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1353 {
1354 uint32_t states = RADV_DYNAMIC_ALL;
1355
1356 /* If rasterization is disabled we do not care about any of the dynamic states,
1357 * since they are all rasterization related only. */
1358 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1359 return 0;
1360
1361 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1362 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1363
1364 if (!pCreateInfo->pDepthStencilState ||
1365 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1366 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1367
1368 if (!pCreateInfo->pDepthStencilState ||
1369 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1370 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1371 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1372 RADV_DYNAMIC_STENCIL_REFERENCE);
1373
1374 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1375 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1376
1377 if (!pCreateInfo->pMultisampleState ||
1378 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1379 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1380 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1381
1382 /* TODO: blend constants & line width. */
1383
1384 return states;
1385 }
1386
1387
1388 static void
1389 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1390 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1391 {
1392 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1393 uint32_t states = needed_states;
1394 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1395 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1396
1397 pipeline->dynamic_state = default_dynamic_state;
1398 pipeline->graphics.needed_dynamic_state = needed_states;
1399
1400 if (pCreateInfo->pDynamicState) {
1401 /* Remove all of the states that are marked as dynamic */
1402 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1403 for (uint32_t s = 0; s < count; s++)
1404 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1405 }
1406
1407 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1408
1409 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1410 assert(pCreateInfo->pViewportState);
1411
1412 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1413 if (states & RADV_DYNAMIC_VIEWPORT) {
1414 typed_memcpy(dynamic->viewport.viewports,
1415 pCreateInfo->pViewportState->pViewports,
1416 pCreateInfo->pViewportState->viewportCount);
1417 }
1418 }
1419
1420 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1421 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1422 if (states & RADV_DYNAMIC_SCISSOR) {
1423 typed_memcpy(dynamic->scissor.scissors,
1424 pCreateInfo->pViewportState->pScissors,
1425 pCreateInfo->pViewportState->scissorCount);
1426 }
1427 }
1428
1429 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1430 assert(pCreateInfo->pRasterizationState);
1431 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1432 }
1433
1434 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1435 assert(pCreateInfo->pRasterizationState);
1436 dynamic->depth_bias.bias =
1437 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1438 dynamic->depth_bias.clamp =
1439 pCreateInfo->pRasterizationState->depthBiasClamp;
1440 dynamic->depth_bias.slope =
1441 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1442 }
1443
1444 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1445 *
1446 * pColorBlendState is [...] NULL if the pipeline has rasterization
1447 * disabled or if the subpass of the render pass the pipeline is
1448 * created against does not use any color attachments.
1449 */
1450 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1451 assert(pCreateInfo->pColorBlendState);
1452 typed_memcpy(dynamic->blend_constants,
1453 pCreateInfo->pColorBlendState->blendConstants, 4);
1454 }
1455
1456 /* If there is no depthstencil attachment, then don't read
1457 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1458 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1459 * no need to override the depthstencil defaults in
1460 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1461 *
1462 * Section 9.2 of the Vulkan 1.0.15 spec says:
1463 *
1464 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1465 * disabled or if the subpass of the render pass the pipeline is created
1466 * against does not use a depth/stencil attachment.
1467 */
1468 if (needed_states && subpass->depth_stencil_attachment) {
1469 assert(pCreateInfo->pDepthStencilState);
1470
1471 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1472 dynamic->depth_bounds.min =
1473 pCreateInfo->pDepthStencilState->minDepthBounds;
1474 dynamic->depth_bounds.max =
1475 pCreateInfo->pDepthStencilState->maxDepthBounds;
1476 }
1477
1478 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1479 dynamic->stencil_compare_mask.front =
1480 pCreateInfo->pDepthStencilState->front.compareMask;
1481 dynamic->stencil_compare_mask.back =
1482 pCreateInfo->pDepthStencilState->back.compareMask;
1483 }
1484
1485 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1486 dynamic->stencil_write_mask.front =
1487 pCreateInfo->pDepthStencilState->front.writeMask;
1488 dynamic->stencil_write_mask.back =
1489 pCreateInfo->pDepthStencilState->back.writeMask;
1490 }
1491
1492 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1493 dynamic->stencil_reference.front =
1494 pCreateInfo->pDepthStencilState->front.reference;
1495 dynamic->stencil_reference.back =
1496 pCreateInfo->pDepthStencilState->back.reference;
1497 }
1498 }
1499
1500 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1501 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1502 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1503 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1504 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1505 typed_memcpy(dynamic->discard_rectangle.rectangles,
1506 discard_rectangle_info->pDiscardRectangles,
1507 discard_rectangle_info->discardRectangleCount);
1508 }
1509 }
1510
1511 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1512 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1513 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1514 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1515 /* If sampleLocationsEnable is VK_FALSE, the default sample
1516 * locations are used and the values specified in
1517 * sampleLocationsInfo are ignored.
1518 */
1519 if (sample_location_info->sampleLocationsEnable) {
1520 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1521 &sample_location_info->sampleLocationsInfo;
1522
1523 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1524
1525 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1526 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1527 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1528 typed_memcpy(&dynamic->sample_location.locations[0],
1529 pSampleLocationsInfo->pSampleLocations,
1530 pSampleLocationsInfo->sampleLocationsCount);
1531 }
1532 }
1533
1534 pipeline->dynamic_state.mask = states;
1535 }
1536
1537 static void
1538 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1539 const struct radv_pipeline *pipeline,
1540 nir_shader **nir,
1541 struct radv_shader_info *infos,
1542 struct gfx9_gs_info *out)
1543 {
1544 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1545 struct radv_es_output_info *es_info;
1546 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1547 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1548 else
1549 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1550 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1551 &infos[MESA_SHADER_VERTEX].vs.es_info;
1552
1553 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1554 bool uses_adjacency;
1555 switch(key->topology) {
1556 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1557 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1558 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1559 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1560 uses_adjacency = true;
1561 break;
1562 default:
1563 uses_adjacency = false;
1564 break;
1565 }
1566
1567 /* All these are in dwords: */
1568 /* We can't allow using the whole LDS, because GS waves compete with
1569 * other shader stages for LDS space. */
1570 const unsigned max_lds_size = 8 * 1024;
1571 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1572 unsigned esgs_lds_size;
1573
1574 /* All these are per subgroup: */
1575 const unsigned max_out_prims = 32 * 1024;
1576 const unsigned max_es_verts = 255;
1577 const unsigned ideal_gs_prims = 64;
1578 unsigned max_gs_prims, gs_prims;
1579 unsigned min_es_verts, es_verts, worst_case_es_verts;
1580
1581 if (uses_adjacency || gs_num_invocations > 1)
1582 max_gs_prims = 127 / gs_num_invocations;
1583 else
1584 max_gs_prims = 255;
1585
1586 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1587 * Make sure we don't go over the maximum value.
1588 */
1589 if (gs_info->gs.vertices_out > 0) {
1590 max_gs_prims = MIN2(max_gs_prims,
1591 max_out_prims /
1592 (gs_info->gs.vertices_out * gs_num_invocations));
1593 }
1594 assert(max_gs_prims > 0);
1595
1596 /* If the primitive has adjacency, halve the number of vertices
1597 * that will be reused in multiple primitives.
1598 */
1599 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1600
1601 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1602 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1603
1604 /* Compute ESGS LDS size based on the worst case number of ES vertices
1605 * needed to create the target number of GS prims per subgroup.
1606 */
1607 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1608
1609 /* If total LDS usage is too big, refactor partitions based on ratio
1610 * of ESGS item sizes.
1611 */
1612 if (esgs_lds_size > max_lds_size) {
1613 /* Our target GS Prims Per Subgroup was too large. Calculate
1614 * the maximum number of GS Prims Per Subgroup that will fit
1615 * into LDS, capped by the maximum that the hardware can support.
1616 */
1617 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1618 max_gs_prims);
1619 assert(gs_prims > 0);
1620 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1621 max_es_verts);
1622
1623 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1624 assert(esgs_lds_size <= max_lds_size);
1625 }
1626
1627 /* Now calculate remaining ESGS information. */
1628 if (esgs_lds_size)
1629 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1630 else
1631 es_verts = max_es_verts;
1632
1633 /* Vertices for adjacency primitives are not always reused, so restore
1634 * it for ES_VERTS_PER_SUBGRP.
1635 */
1636 min_es_verts = gs_info->gs.vertices_in;
1637
1638 /* For normal primitives, the VGT only checks if they are past the ES
1639 * verts per subgroup after allocating a full GS primitive and if they
1640 * are, kick off a new subgroup. But if those additional ES verts are
1641 * unique (e.g. not reused) we need to make sure there is enough LDS
1642 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1643 */
1644 es_verts -= min_es_verts - 1;
1645
1646 uint32_t es_verts_per_subgroup = es_verts;
1647 uint32_t gs_prims_per_subgroup = gs_prims;
1648 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1649 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1650 out->lds_size = align(esgs_lds_size, 128) / 128;
1651 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1652 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1653 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1654 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1655 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1656 assert(max_prims_per_subgroup <= max_out_prims);
1657 }
1658
1659 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1660 unsigned min_verts_per_prim, bool use_adjacency)
1661 {
1662 unsigned max_reuse = max_esverts - min_verts_per_prim;
1663 if (use_adjacency)
1664 max_reuse /= 2;
1665 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1666 }
1667
1668 static unsigned
1669 radv_get_num_input_vertices(nir_shader **nir)
1670 {
1671 if (nir[MESA_SHADER_GEOMETRY]) {
1672 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1673
1674 return gs->info.gs.vertices_in;
1675 }
1676
1677 if (nir[MESA_SHADER_TESS_CTRL]) {
1678 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1679
1680 if (tes->info.tess.point_mode)
1681 return 1;
1682 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1683 return 2;
1684 return 3;
1685 }
1686
1687 return 3;
1688 }
1689
1690 static void
1691 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1692 struct radv_pipeline *pipeline,
1693 nir_shader **nir,
1694 struct radv_shader_info *infos,
1695 struct gfx10_ngg_info *ngg)
1696 {
1697 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1698 struct radv_es_output_info *es_info =
1699 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1700 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1701 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1702 unsigned min_verts_per_prim =
1703 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1704 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1705 bool uses_adjacency;
1706 switch(key->topology) {
1707 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1708 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1709 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1710 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1711 uses_adjacency = true;
1712 break;
1713 default:
1714 uses_adjacency = false;
1715 break;
1716 }
1717
1718 /* All these are in dwords: */
1719 /* We can't allow using the whole LDS, because GS waves compete with
1720 * other shader stages for LDS space.
1721 *
1722 * TODO: We should really take the shader's internal LDS use into
1723 * account. The linker will fail if the size is greater than
1724 * 8K dwords.
1725 */
1726 const unsigned max_lds_size = 8 * 1024 - 768;
1727 const unsigned target_lds_size = max_lds_size;
1728 unsigned esvert_lds_size = 0;
1729 unsigned gsprim_lds_size = 0;
1730
1731 /* All these are per subgroup: */
1732 bool max_vert_out_per_gs_instance = false;
1733 unsigned max_esverts_base = 256;
1734 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1735
1736 /* Hardware has the following non-natural restrictions on the value
1737 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1738 * the draw:
1739 * - at most 252 for any line input primitive type
1740 * - at most 251 for any quad input primitive type
1741 * - at most 251 for triangle strips with adjacency (this happens to
1742 * be the natural limit for triangle *lists* with adjacency)
1743 */
1744 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1745
1746 if (gs_type == MESA_SHADER_GEOMETRY) {
1747 unsigned max_out_verts_per_gsprim =
1748 gs_info->gs.vertices_out * gs_num_invocations;
1749
1750 if (max_out_verts_per_gsprim <= 256) {
1751 if (max_out_verts_per_gsprim) {
1752 max_gsprims_base = MIN2(max_gsprims_base,
1753 256 / max_out_verts_per_gsprim);
1754 }
1755 } else {
1756 /* Use special multi-cycling mode in which each GS
1757 * instance gets its own subgroup. Does not work with
1758 * tessellation. */
1759 max_vert_out_per_gs_instance = true;
1760 max_gsprims_base = 1;
1761 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1762 }
1763
1764 esvert_lds_size = es_info->esgs_itemsize / 4;
1765 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1766 } else {
1767 /* VS and TES. */
1768 /* LDS size for passing data from GS to ES. */
1769 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1770 ? &infos[MESA_SHADER_TESS_EVAL].so
1771 : &infos[MESA_SHADER_VERTEX].so;
1772
1773 if (so_info->num_outputs)
1774 esvert_lds_size = 4 * so_info->num_outputs + 1;
1775
1776 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1777 * corresponding to the ES thread of the provoking vertex. All
1778 * ES threads load and export PrimitiveID for their thread.
1779 */
1780 if (!nir[MESA_SHADER_TESS_CTRL] &&
1781 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1782 esvert_lds_size = MAX2(esvert_lds_size, 1);
1783 }
1784
1785 unsigned max_gsprims = max_gsprims_base;
1786 unsigned max_esverts = max_esverts_base;
1787
1788 if (esvert_lds_size)
1789 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1790 if (gsprim_lds_size)
1791 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1792
1793 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1794 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1795 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1796
1797 if (esvert_lds_size || gsprim_lds_size) {
1798 /* Now that we have a rough proportionality between esverts
1799 * and gsprims based on the primitive type, scale both of them
1800 * down simultaneously based on required LDS space.
1801 *
1802 * We could be smarter about this if we knew how much vertex
1803 * reuse to expect.
1804 */
1805 unsigned lds_total = max_esverts * esvert_lds_size +
1806 max_gsprims * gsprim_lds_size;
1807 if (lds_total > target_lds_size) {
1808 max_esverts = max_esverts * target_lds_size / lds_total;
1809 max_gsprims = max_gsprims * target_lds_size / lds_total;
1810
1811 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1812 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1813 min_verts_per_prim, uses_adjacency);
1814 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1815 }
1816 }
1817
1818 /* Round up towards full wave sizes for better ALU utilization. */
1819 if (!max_vert_out_per_gs_instance) {
1820 unsigned orig_max_esverts;
1821 unsigned orig_max_gsprims;
1822 unsigned wavesize;
1823
1824 if (gs_type == MESA_SHADER_GEOMETRY) {
1825 wavesize = gs_info->wave_size;
1826 } else {
1827 wavesize = nir[MESA_SHADER_TESS_CTRL]
1828 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1829 : infos[MESA_SHADER_VERTEX].wave_size;
1830 }
1831
1832 do {
1833 orig_max_esverts = max_esverts;
1834 orig_max_gsprims = max_gsprims;
1835
1836 max_esverts = align(max_esverts, wavesize);
1837 max_esverts = MIN2(max_esverts, max_esverts_base);
1838 if (esvert_lds_size)
1839 max_esverts = MIN2(max_esverts,
1840 (max_lds_size - max_gsprims * gsprim_lds_size) /
1841 esvert_lds_size);
1842 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1843
1844 max_gsprims = align(max_gsprims, wavesize);
1845 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1846 if (gsprim_lds_size)
1847 max_gsprims = MIN2(max_gsprims,
1848 (max_lds_size - max_esverts * esvert_lds_size) /
1849 gsprim_lds_size);
1850 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1851 min_verts_per_prim, uses_adjacency);
1852 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1853 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1854 }
1855
1856 /* Hardware restriction: minimum value of max_esverts */
1857 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1858
1859 unsigned max_out_vertices =
1860 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1861 gs_type == MESA_SHADER_GEOMETRY ?
1862 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1863 max_esverts;
1864 assert(max_out_vertices <= 256);
1865
1866 unsigned prim_amp_factor = 1;
1867 if (gs_type == MESA_SHADER_GEOMETRY) {
1868 /* Number of output primitives per GS input primitive after
1869 * GS instancing. */
1870 prim_amp_factor = gs_info->gs.vertices_out;
1871 }
1872
1873 /* The GE only checks against the maximum number of ES verts after
1874 * allocating a full GS primitive. So we need to ensure that whenever
1875 * this check passes, there is enough space for a full primitive without
1876 * vertex reuse.
1877 */
1878 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1879 ngg->max_gsprims = max_gsprims;
1880 ngg->max_out_verts = max_out_vertices;
1881 ngg->prim_amp_factor = prim_amp_factor;
1882 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1883 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1884 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1885
1886 if (gs_type == MESA_SHADER_GEOMETRY) {
1887 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1888 } else {
1889 ngg->vgt_esgs_ring_itemsize = 1;
1890 }
1891
1892 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1893
1894 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1895 }
1896
1897 static void
1898 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1899 const struct gfx9_gs_info *gs)
1900 {
1901 struct radv_device *device = pipeline->device;
1902 unsigned num_se = device->physical_device->rad_info.max_se;
1903 unsigned wave_size = 64;
1904 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1905 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1906 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1907 */
1908 unsigned gs_vertex_reuse =
1909 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1910 unsigned alignment = 256 * num_se;
1911 /* The maximum size is 63.999 MB per SE. */
1912 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1913 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1914
1915 /* Calculate the minimum size. */
1916 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1917 wave_size, alignment);
1918 /* These are recommended sizes, not minimum sizes. */
1919 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1920 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1921 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1922 gs_info->gs.max_gsvs_emit_size;
1923
1924 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1925 esgs_ring_size = align(esgs_ring_size, alignment);
1926 gsvs_ring_size = align(gsvs_ring_size, alignment);
1927
1928 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1929 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1930
1931 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1932 }
1933
1934 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1935 unsigned *lds_size)
1936 {
1937 /* If tessellation is all offchip and on-chip GS isn't used, this
1938 * workaround is not needed.
1939 */
1940 return;
1941
1942 /* SPI barrier management bug:
1943 * Make sure we have at least 4k of LDS in use to avoid the bug.
1944 * It applies to workgroup sizes of more than one wavefront.
1945 */
1946 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1947 device->physical_device->rad_info.family == CHIP_KABINI)
1948 *lds_size = MAX2(*lds_size, 8);
1949 }
1950
1951 struct radv_shader_variant *
1952 radv_get_shader(struct radv_pipeline *pipeline,
1953 gl_shader_stage stage)
1954 {
1955 if (stage == MESA_SHADER_VERTEX) {
1956 if (pipeline->shaders[MESA_SHADER_VERTEX])
1957 return pipeline->shaders[MESA_SHADER_VERTEX];
1958 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1959 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1960 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1961 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1962 } else if (stage == MESA_SHADER_TESS_EVAL) {
1963 if (!radv_pipeline_has_tess(pipeline))
1964 return NULL;
1965 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1966 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1967 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1968 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1969 }
1970 return pipeline->shaders[stage];
1971 }
1972
1973 static struct radv_tessellation_state
1974 calculate_tess_state(struct radv_pipeline *pipeline,
1975 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1976 {
1977 unsigned num_tcs_input_cp;
1978 unsigned num_tcs_output_cp;
1979 unsigned lds_size;
1980 unsigned num_patches;
1981 struct radv_tessellation_state tess = {0};
1982
1983 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1984 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1985 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1986
1987 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1988
1989 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1990 assert(lds_size <= 65536);
1991 lds_size = align(lds_size, 512) / 512;
1992 } else {
1993 assert(lds_size <= 32768);
1994 lds_size = align(lds_size, 256) / 256;
1995 }
1996 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1997
1998 tess.lds_size = lds_size;
1999
2000 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
2001 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
2002 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
2003 tess.num_patches = num_patches;
2004
2005 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
2006 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
2007
2008 switch (tes->info.tes.primitive_mode) {
2009 case GL_TRIANGLES:
2010 type = V_028B6C_TESS_TRIANGLE;
2011 break;
2012 case GL_QUADS:
2013 type = V_028B6C_TESS_QUAD;
2014 break;
2015 case GL_ISOLINES:
2016 type = V_028B6C_TESS_ISOLINE;
2017 break;
2018 }
2019
2020 switch (tes->info.tes.spacing) {
2021 case TESS_SPACING_EQUAL:
2022 partitioning = V_028B6C_PART_INTEGER;
2023 break;
2024 case TESS_SPACING_FRACTIONAL_ODD:
2025 partitioning = V_028B6C_PART_FRAC_ODD;
2026 break;
2027 case TESS_SPACING_FRACTIONAL_EVEN:
2028 partitioning = V_028B6C_PART_FRAC_EVEN;
2029 break;
2030 default:
2031 break;
2032 }
2033
2034 bool ccw = tes->info.tes.ccw;
2035 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2036 vk_find_struct_const(pCreateInfo->pTessellationState,
2037 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2038
2039 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2040 ccw = !ccw;
2041
2042 if (tes->info.tes.point_mode)
2043 topology = V_028B6C_OUTPUT_POINT;
2044 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2045 topology = V_028B6C_OUTPUT_LINE;
2046 else if (ccw)
2047 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2048 else
2049 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2050
2051 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2052 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2053 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2054 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2055 else
2056 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2057 } else
2058 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2059
2060 tess.tf_param = S_028B6C_TYPE(type) |
2061 S_028B6C_PARTITIONING(partitioning) |
2062 S_028B6C_TOPOLOGY(topology) |
2063 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2064
2065 return tess;
2066 }
2067
2068 static const struct radv_prim_vertex_count prim_size_table[] = {
2069 [V_008958_DI_PT_NONE] = {0, 0},
2070 [V_008958_DI_PT_POINTLIST] = {1, 1},
2071 [V_008958_DI_PT_LINELIST] = {2, 2},
2072 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2073 [V_008958_DI_PT_TRILIST] = {3, 3},
2074 [V_008958_DI_PT_TRIFAN] = {3, 1},
2075 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2076 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2077 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2078 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2079 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2080 [V_008958_DI_PT_RECTLIST] = {3, 3},
2081 [V_008958_DI_PT_LINELOOP] = {2, 1},
2082 [V_008958_DI_PT_POLYGON] = {3, 1},
2083 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2084 };
2085
2086 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2087 {
2088 if (radv_pipeline_has_gs(pipeline))
2089 if (radv_pipeline_has_ngg(pipeline))
2090 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2091 else
2092 return &pipeline->gs_copy_shader->info.vs.outinfo;
2093 else if (radv_pipeline_has_tess(pipeline))
2094 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2095 else
2096 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2097 }
2098
2099 static void
2100 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2101 {
2102 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2103 int shader_count = 0;
2104
2105 if(shaders[MESA_SHADER_FRAGMENT]) {
2106 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2107 }
2108 if(shaders[MESA_SHADER_GEOMETRY]) {
2109 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2110 }
2111 if(shaders[MESA_SHADER_TESS_EVAL]) {
2112 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2113 }
2114 if(shaders[MESA_SHADER_TESS_CTRL]) {
2115 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2116 }
2117 if(shaders[MESA_SHADER_VERTEX]) {
2118 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2119 }
2120
2121 if (shader_count > 1) {
2122 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2123 unsigned last = ordered_shaders[0]->info.stage;
2124
2125 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2126 ordered_shaders[1]->info.has_transform_feedback_varyings)
2127 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2128
2129 for (int i = 0; i < shader_count; ++i) {
2130 nir_variable_mode mask = 0;
2131
2132 if (ordered_shaders[i]->info.stage != first)
2133 mask = mask | nir_var_shader_in;
2134
2135 if (ordered_shaders[i]->info.stage != last)
2136 mask = mask | nir_var_shader_out;
2137
2138 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2139 radv_optimize_nir(ordered_shaders[i], false, false);
2140 }
2141 }
2142
2143 for (int i = 1; i < shader_count; ++i) {
2144 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2145 ordered_shaders[i - 1]);
2146
2147 if (nir_link_opt_varyings(ordered_shaders[i],
2148 ordered_shaders[i - 1]))
2149 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2150
2151 nir_remove_dead_variables(ordered_shaders[i],
2152 nir_var_shader_out);
2153 nir_remove_dead_variables(ordered_shaders[i - 1],
2154 nir_var_shader_in);
2155
2156 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2157 ordered_shaders[i - 1]);
2158
2159 nir_compact_varyings(ordered_shaders[i],
2160 ordered_shaders[i - 1], true);
2161
2162 if (progress) {
2163 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2164 ac_lower_indirect_derefs(ordered_shaders[i],
2165 pipeline->device->physical_device->rad_info.chip_class);
2166 }
2167 radv_optimize_nir(ordered_shaders[i], false, false);
2168
2169 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2170 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2171 pipeline->device->physical_device->rad_info.chip_class);
2172 }
2173 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2174 }
2175 }
2176 }
2177
2178 static uint32_t
2179 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2180 uint32_t attrib_binding)
2181 {
2182 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2183 const VkVertexInputBindingDescription *input_binding =
2184 &input_state->pVertexBindingDescriptions[i];
2185
2186 if (input_binding->binding == attrib_binding)
2187 return input_binding->stride;
2188 }
2189
2190 return 0;
2191 }
2192
2193 static struct radv_pipeline_key
2194 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2195 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2196 const struct radv_blend_state *blend,
2197 bool has_view_index)
2198 {
2199 const VkPipelineVertexInputStateCreateInfo *input_state =
2200 pCreateInfo->pVertexInputState;
2201 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2202 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2203
2204 struct radv_pipeline_key key;
2205 memset(&key, 0, sizeof(key));
2206
2207 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2208 key.optimisations_disabled = 1;
2209
2210 key.has_multiview_view_index = has_view_index;
2211
2212 uint32_t binding_input_rate = 0;
2213 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2214 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2215 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2216 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2217 binding_input_rate |= 1u << binding;
2218 instance_rate_divisors[binding] = 1;
2219 }
2220 }
2221 if (divisor_state) {
2222 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2223 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2224 divisor_state->pVertexBindingDivisors[i].divisor;
2225 }
2226 }
2227
2228 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2229 const VkVertexInputAttributeDescription *desc =
2230 &input_state->pVertexAttributeDescriptions[i];
2231 const struct vk_format_description *format_desc;
2232 unsigned location = desc->location;
2233 unsigned binding = desc->binding;
2234 unsigned num_format, data_format;
2235 int first_non_void;
2236
2237 if (binding_input_rate & (1u << binding)) {
2238 key.instance_rate_inputs |= 1u << location;
2239 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2240 }
2241
2242 format_desc = vk_format_description(desc->format);
2243 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2244
2245 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2246 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2247
2248 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2249 key.vertex_attribute_bindings[location] = desc->binding;
2250 key.vertex_attribute_offsets[location] = desc->offset;
2251 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2252
2253 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2254 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2255 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2256 uint64_t adjust;
2257 switch(format) {
2258 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2259 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2260 adjust = RADV_ALPHA_ADJUST_SNORM;
2261 break;
2262 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2263 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2264 adjust = RADV_ALPHA_ADJUST_SSCALED;
2265 break;
2266 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2267 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2268 adjust = RADV_ALPHA_ADJUST_SINT;
2269 break;
2270 default:
2271 adjust = 0;
2272 break;
2273 }
2274 key.vertex_alpha_adjust |= adjust << (2 * location);
2275 }
2276
2277 switch (desc->format) {
2278 case VK_FORMAT_B8G8R8A8_UNORM:
2279 case VK_FORMAT_B8G8R8A8_SNORM:
2280 case VK_FORMAT_B8G8R8A8_USCALED:
2281 case VK_FORMAT_B8G8R8A8_SSCALED:
2282 case VK_FORMAT_B8G8R8A8_UINT:
2283 case VK_FORMAT_B8G8R8A8_SINT:
2284 case VK_FORMAT_B8G8R8A8_SRGB:
2285 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2286 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2287 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2288 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2289 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2290 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2291 key.vertex_post_shuffle |= 1 << location;
2292 break;
2293 default:
2294 break;
2295 }
2296 }
2297
2298 const VkPipelineTessellationStateCreateInfo *tess =
2299 radv_pipeline_get_tessellation_state(pCreateInfo);
2300 if (tess)
2301 key.tess_input_vertices = tess->patchControlPoints;
2302
2303 const VkPipelineMultisampleStateCreateInfo *vkms =
2304 radv_pipeline_get_multisample_state(pCreateInfo);
2305 if (vkms && vkms->rasterizationSamples > 1) {
2306 uint32_t num_samples = vkms->rasterizationSamples;
2307 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
2308 key.num_samples = num_samples;
2309 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2310 }
2311
2312 key.col_format = blend->spi_shader_col_format;
2313 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2314 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2315
2316 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2317 key.topology = pCreateInfo->pInputAssemblyState->topology;
2318
2319 return key;
2320 }
2321
2322 static bool
2323 radv_nir_stage_uses_xfb(const nir_shader *nir)
2324 {
2325 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2326 bool uses_xfb = !!xfb;
2327
2328 ralloc_free(xfb);
2329 return uses_xfb;
2330 }
2331
2332 static void
2333 radv_fill_shader_keys(struct radv_device *device,
2334 struct radv_shader_variant_key *keys,
2335 const struct radv_pipeline_key *key,
2336 nir_shader **nir)
2337 {
2338 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2339 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2340 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2341 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2342 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2343 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2344 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2345 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2346 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2347 }
2348 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2349
2350 if (nir[MESA_SHADER_TESS_CTRL]) {
2351 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2352 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2353 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2354 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2355
2356 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2357 }
2358
2359 if (nir[MESA_SHADER_GEOMETRY]) {
2360 if (nir[MESA_SHADER_TESS_CTRL])
2361 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2362 else
2363 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2364 }
2365
2366 if (device->physical_device->use_ngg) {
2367 if (nir[MESA_SHADER_TESS_CTRL]) {
2368 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2369 } else {
2370 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2371 }
2372
2373 if (nir[MESA_SHADER_TESS_CTRL] &&
2374 nir[MESA_SHADER_GEOMETRY] &&
2375 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2376 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2377 /* Fallback to the legacy path if tessellation is
2378 * enabled with extreme geometry because
2379 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2380 * might hang.
2381 */
2382 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2383 }
2384
2385 /*
2386 * Disable NGG with geometry shaders. There are a bunch of
2387 * issues still:
2388 * * GS primitives in pipeline statistic queries do not get
2389 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2390 *
2391 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2392 */
2393 if (nir[MESA_SHADER_GEOMETRY]) {
2394 if (nir[MESA_SHADER_TESS_CTRL])
2395 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2396 else
2397 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2398 }
2399
2400 if (!device->physical_device->use_ngg_streamout) {
2401 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2402
2403 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2404 if (nir[i])
2405 last_xfb_stage = i;
2406 }
2407
2408 if (nir[last_xfb_stage] &&
2409 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2410 if (nir[MESA_SHADER_TESS_CTRL])
2411 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2412 else
2413 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2414 }
2415 }
2416 }
2417
2418 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2419 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2420
2421 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2422 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2423 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2424 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2425 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2426
2427 if (nir[MESA_SHADER_COMPUTE]) {
2428 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2429 }
2430 }
2431
2432 static uint8_t
2433 radv_get_wave_size(struct radv_device *device,
2434 const VkPipelineShaderStageCreateInfo *pStage,
2435 gl_shader_stage stage,
2436 const struct radv_shader_variant_key *key)
2437 {
2438 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2439 return 64;
2440 else if (stage == MESA_SHADER_COMPUTE) {
2441 if (key->cs.subgroup_size) {
2442 /* Return the required subgroup size if specified. */
2443 return key->cs.subgroup_size;
2444 }
2445 return device->physical_device->cs_wave_size;
2446 }
2447 else if (stage == MESA_SHADER_FRAGMENT)
2448 return device->physical_device->ps_wave_size;
2449 else
2450 return device->physical_device->ge_wave_size;
2451 }
2452
2453 static void
2454 radv_fill_shader_info(struct radv_pipeline *pipeline,
2455 const VkPipelineShaderStageCreateInfo **pStages,
2456 struct radv_shader_variant_key *keys,
2457 struct radv_shader_info *infos,
2458 nir_shader **nir)
2459 {
2460 unsigned active_stages = 0;
2461 unsigned filled_stages = 0;
2462
2463 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2464 if (nir[i])
2465 active_stages |= (1 << i);
2466 }
2467
2468 if (nir[MESA_SHADER_FRAGMENT]) {
2469 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2470 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2471 pipeline->layout,
2472 &keys[MESA_SHADER_FRAGMENT],
2473 &infos[MESA_SHADER_FRAGMENT]);
2474
2475 /* TODO: These are no longer used as keys we should refactor this */
2476 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2477 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2478 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2479 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2480 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2481 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2482 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2483 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2484 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2485 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2486 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2487 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2488
2489 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2490 }
2491
2492 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2493 nir[MESA_SHADER_TESS_CTRL]) {
2494 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2495 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2496 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2497
2498 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2499
2500 for (int i = 0; i < 2; i++) {
2501 radv_nir_shader_info_pass(combined_nir[i],
2502 pipeline->layout, &key,
2503 &infos[MESA_SHADER_TESS_CTRL]);
2504 }
2505
2506 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2507 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2508 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2509 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2510
2511 filled_stages |= (1 << MESA_SHADER_VERTEX);
2512 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2513 }
2514
2515 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2516 nir[MESA_SHADER_GEOMETRY]) {
2517 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2518 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2519
2520 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2521
2522 for (int i = 0; i < 2; i++) {
2523 radv_nir_shader_info_pass(combined_nir[i],
2524 pipeline->layout,
2525 &keys[pre_stage],
2526 &infos[MESA_SHADER_GEOMETRY]);
2527 }
2528
2529 filled_stages |= (1 << pre_stage);
2530 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2531 }
2532
2533 active_stages ^= filled_stages;
2534 while (active_stages) {
2535 int i = u_bit_scan(&active_stages);
2536
2537 if (i == MESA_SHADER_TESS_CTRL) {
2538 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2539 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2540 }
2541
2542 if (i == MESA_SHADER_TESS_EVAL) {
2543 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2544 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2545 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2546 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2547 }
2548
2549 radv_nir_shader_info_init(&infos[i]);
2550 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2551 &keys[i], &infos[i]);
2552 }
2553
2554 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2555 if (nir[i])
2556 infos[i].wave_size =
2557 radv_get_wave_size(pipeline->device, pStages[i],
2558 i, &keys[i]);
2559 }
2560 }
2561
2562 static void
2563 merge_tess_info(struct shader_info *tes_info,
2564 const struct shader_info *tcs_info)
2565 {
2566 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2567 *
2568 * "PointMode. Controls generation of points rather than triangles
2569 * or lines. This functionality defaults to disabled, and is
2570 * enabled if either shader stage includes the execution mode.
2571 *
2572 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2573 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2574 * and OutputVertices, it says:
2575 *
2576 * "One mode must be set in at least one of the tessellation
2577 * shader stages."
2578 *
2579 * So, the fields can be set in either the TCS or TES, but they must
2580 * agree if set in both. Our backend looks at TES, so bitwise-or in
2581 * the values from the TCS.
2582 */
2583 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2584 tes_info->tess.tcs_vertices_out == 0 ||
2585 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2586 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2587
2588 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2589 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2590 tcs_info->tess.spacing == tes_info->tess.spacing);
2591 tes_info->tess.spacing |= tcs_info->tess.spacing;
2592
2593 assert(tcs_info->tess.primitive_mode == 0 ||
2594 tes_info->tess.primitive_mode == 0 ||
2595 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2596 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2597 tes_info->tess.ccw |= tcs_info->tess.ccw;
2598 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2599 }
2600
2601 static
2602 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2603 {
2604 if (!ext)
2605 return;
2606
2607 if (ext->pPipelineCreationFeedback) {
2608 ext->pPipelineCreationFeedback->flags = 0;
2609 ext->pPipelineCreationFeedback->duration = 0;
2610 }
2611
2612 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2613 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2614 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2615 }
2616 }
2617
2618 static
2619 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2620 {
2621 if (!feedback)
2622 return;
2623
2624 feedback->duration -= radv_get_current_time();
2625 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2626 }
2627
2628 static
2629 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2630 {
2631 if (!feedback)
2632 return;
2633
2634 feedback->duration += radv_get_current_time();
2635 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2636 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2637 }
2638
2639 static
2640 bool radv_aco_supported_stage(gl_shader_stage stage, bool has_gs, bool has_ts)
2641 {
2642 return (stage == MESA_SHADER_VERTEX && !has_gs && !has_ts) ||
2643 stage == MESA_SHADER_FRAGMENT ||
2644 stage == MESA_SHADER_COMPUTE;
2645 }
2646
2647 void radv_create_shaders(struct radv_pipeline *pipeline,
2648 struct radv_device *device,
2649 struct radv_pipeline_cache *cache,
2650 const struct radv_pipeline_key *key,
2651 const VkPipelineShaderStageCreateInfo **pStages,
2652 const VkPipelineCreateFlags flags,
2653 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2654 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2655 {
2656 struct radv_shader_module fs_m = {0};
2657 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2658 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2659 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2660 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2661 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2662 unsigned char hash[20], gs_copy_hash[20];
2663 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2664
2665 radv_start_feedback(pipeline_feedback);
2666
2667 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2668 if (pStages[i]) {
2669 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2670 if (modules[i]->nir)
2671 _mesa_sha1_compute(modules[i]->nir->info.name,
2672 strlen(modules[i]->nir->info.name),
2673 modules[i]->sha1);
2674
2675 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2676 }
2677 }
2678
2679 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2680 memcpy(gs_copy_hash, hash, 20);
2681 gs_copy_hash[0] ^= 1;
2682
2683 bool found_in_application_cache = true;
2684 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2685 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2686 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2687 &found_in_application_cache);
2688 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2689 }
2690
2691 if (!keep_executable_info &&
2692 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2693 &found_in_application_cache) &&
2694 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2695 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2696 return;
2697 }
2698
2699 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2700 nir_builder fs_b;
2701 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2702 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2703 fs_m.nir = fs_b.shader;
2704 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2705 }
2706
2707 bool has_gs = modules[MESA_SHADER_GEOMETRY];
2708 bool has_ts = modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL];
2709 bool use_aco = device->physical_device->use_aco;
2710
2711 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2712 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2713
2714 if (!modules[i])
2715 continue;
2716
2717 radv_start_feedback(stage_feedbacks[i]);
2718
2719 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2720 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2721 stage ? stage->pName : "main", i,
2722 stage ? stage->pSpecializationInfo : NULL,
2723 flags, pipeline->layout, aco);
2724
2725 /* We don't want to alter meta shaders IR directly so clone it
2726 * first.
2727 */
2728 if (nir[i]->info.name) {
2729 nir[i] = nir_shader_clone(NULL, nir[i]);
2730 }
2731
2732 radv_stop_feedback(stage_feedbacks[i], false);
2733 }
2734
2735 if (nir[MESA_SHADER_TESS_CTRL]) {
2736 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2737 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2738 }
2739
2740 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2741 radv_link_shaders(pipeline, nir);
2742
2743 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2744 if (nir[i]) {
2745 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2746 nir_lower_non_uniform_ubo_access |
2747 nir_lower_non_uniform_ssbo_access |
2748 nir_lower_non_uniform_texture_access |
2749 nir_lower_non_uniform_image_access);
2750
2751 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2752 if (!aco)
2753 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2754 }
2755
2756 if (radv_can_dump_shader(device, modules[i], false))
2757 nir_print_shader(nir[i], stderr);
2758 }
2759
2760 if (nir[MESA_SHADER_FRAGMENT])
2761 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2762
2763 radv_fill_shader_keys(device, keys, key, nir);
2764
2765 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2766
2767 if ((nir[MESA_SHADER_VERTEX] &&
2768 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2769 (nir[MESA_SHADER_TESS_EVAL] &&
2770 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2771 struct gfx10_ngg_info *ngg_info;
2772
2773 if (nir[MESA_SHADER_GEOMETRY])
2774 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2775 else if (nir[MESA_SHADER_TESS_CTRL])
2776 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2777 else
2778 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2779
2780 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2781 } else if (nir[MESA_SHADER_GEOMETRY]) {
2782 struct gfx9_gs_info *gs_info =
2783 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2784
2785 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2786 }
2787
2788 if (nir[MESA_SHADER_FRAGMENT]) {
2789 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2790 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2791
2792 bool aco = use_aco && radv_aco_supported_stage(MESA_SHADER_FRAGMENT, has_gs, has_ts);
2793 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2794 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2795 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2796 infos + MESA_SHADER_FRAGMENT,
2797 keep_executable_info, aco,
2798 &binaries[MESA_SHADER_FRAGMENT]);
2799
2800 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2801 }
2802
2803 /* TODO: These are no longer used as keys we should refactor this */
2804 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2805 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2806 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2807 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2808 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2809 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2810 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2811 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2812 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2813 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2814 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2815 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2816 }
2817
2818 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2819 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2820 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2821 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2822 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2823
2824 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2825
2826 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2827 pipeline->layout,
2828 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2829 false, &binaries[MESA_SHADER_TESS_CTRL]);
2830
2831 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2832 }
2833 modules[MESA_SHADER_VERTEX] = NULL;
2834 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2835 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2836 }
2837
2838 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2839 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2840 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2841 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2842
2843 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2844
2845 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2846 pipeline->layout,
2847 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2848 false, &binaries[MESA_SHADER_GEOMETRY]);
2849
2850 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2851 }
2852 modules[pre_stage] = NULL;
2853 }
2854
2855 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2856 if(modules[i] && !pipeline->shaders[i]) {
2857 if (i == MESA_SHADER_TESS_CTRL) {
2858 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2859 }
2860 if (i == MESA_SHADER_TESS_EVAL) {
2861 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2862 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2863 }
2864
2865 radv_start_feedback(stage_feedbacks[i]);
2866
2867 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2868 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2869 pipeline->layout,
2870 keys + i, infos + i,keep_executable_info,
2871 aco, &binaries[i]);
2872
2873 radv_stop_feedback(stage_feedbacks[i], false);
2874 }
2875 }
2876
2877 if(modules[MESA_SHADER_GEOMETRY]) {
2878 struct radv_shader_binary *gs_copy_binary = NULL;
2879 if (!pipeline->gs_copy_shader &&
2880 !radv_pipeline_has_ngg(pipeline)) {
2881 struct radv_shader_info info = {};
2882 struct radv_shader_variant_key key = {};
2883
2884 key.has_multiview_view_index =
2885 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2886
2887 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2888 pipeline->layout, &key,
2889 &info);
2890 info.wave_size = 64; /* Wave32 not supported. */
2891
2892 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2893 device, nir[MESA_SHADER_GEOMETRY], &info,
2894 &gs_copy_binary, keep_executable_info,
2895 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2896 }
2897
2898 if (!keep_executable_info && pipeline->gs_copy_shader) {
2899 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2900 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2901
2902 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2903 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2904
2905 radv_pipeline_cache_insert_shaders(device, cache,
2906 gs_copy_hash,
2907 variants,
2908 binaries);
2909 }
2910 free(gs_copy_binary);
2911 }
2912
2913 if (!keep_executable_info) {
2914 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2915 binaries);
2916 }
2917
2918 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2919 free(binaries[i]);
2920 if (nir[i]) {
2921 ralloc_free(nir[i]);
2922
2923 if (radv_can_dump_shader_stats(device, modules[i]))
2924 radv_shader_dump_stats(device,
2925 pipeline->shaders[i],
2926 i, stderr);
2927 }
2928 }
2929
2930 if (fs_m.nir)
2931 ralloc_free(fs_m.nir);
2932
2933 radv_stop_feedback(pipeline_feedback, false);
2934 }
2935
2936 static uint32_t
2937 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2938 gl_shader_stage stage, enum chip_class chip_class)
2939 {
2940 bool has_gs = radv_pipeline_has_gs(pipeline);
2941 bool has_tess = radv_pipeline_has_tess(pipeline);
2942 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2943
2944 switch (stage) {
2945 case MESA_SHADER_FRAGMENT:
2946 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2947 case MESA_SHADER_VERTEX:
2948 if (has_tess) {
2949 if (chip_class >= GFX10) {
2950 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2951 } else if (chip_class == GFX9) {
2952 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2953 } else {
2954 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2955 }
2956
2957 }
2958
2959 if (has_gs) {
2960 if (chip_class >= GFX10) {
2961 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2962 } else {
2963 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2964 }
2965 }
2966
2967 if (has_ngg)
2968 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2969
2970 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2971 case MESA_SHADER_GEOMETRY:
2972 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2973 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2974 case MESA_SHADER_COMPUTE:
2975 return R_00B900_COMPUTE_USER_DATA_0;
2976 case MESA_SHADER_TESS_CTRL:
2977 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2978 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2979 case MESA_SHADER_TESS_EVAL:
2980 if (has_gs) {
2981 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2982 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2983 } else if (has_ngg) {
2984 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2985 } else {
2986 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2987 }
2988 default:
2989 unreachable("unknown shader");
2990 }
2991 }
2992
2993 struct radv_bin_size_entry {
2994 unsigned bpp;
2995 VkExtent2D extent;
2996 };
2997
2998 static VkExtent2D
2999 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3000 {
3001 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3002 {
3003 /* One RB / SE */
3004 {
3005 /* One shader engine */
3006 { 0, {128, 128}},
3007 { 1, { 64, 128}},
3008 { 2, { 32, 128}},
3009 { 3, { 16, 128}},
3010 { 17, { 0, 0}},
3011 { UINT_MAX, { 0, 0}},
3012 },
3013 {
3014 /* Two shader engines */
3015 { 0, {128, 128}},
3016 { 2, { 64, 128}},
3017 { 3, { 32, 128}},
3018 { 5, { 16, 128}},
3019 { 17, { 0, 0}},
3020 { UINT_MAX, { 0, 0}},
3021 },
3022 {
3023 /* Four shader engines */
3024 { 0, {128, 128}},
3025 { 3, { 64, 128}},
3026 { 5, { 16, 128}},
3027 { 17, { 0, 0}},
3028 { UINT_MAX, { 0, 0}},
3029 },
3030 },
3031 {
3032 /* Two RB / SE */
3033 {
3034 /* One shader engine */
3035 { 0, {128, 128}},
3036 { 2, { 64, 128}},
3037 { 3, { 32, 128}},
3038 { 5, { 16, 128}},
3039 { 33, { 0, 0}},
3040 { UINT_MAX, { 0, 0}},
3041 },
3042 {
3043 /* Two shader engines */
3044 { 0, {128, 128}},
3045 { 3, { 64, 128}},
3046 { 5, { 32, 128}},
3047 { 9, { 16, 128}},
3048 { 33, { 0, 0}},
3049 { UINT_MAX, { 0, 0}},
3050 },
3051 {
3052 /* Four shader engines */
3053 { 0, {256, 256}},
3054 { 2, {128, 256}},
3055 { 3, {128, 128}},
3056 { 5, { 64, 128}},
3057 { 9, { 16, 128}},
3058 { 33, { 0, 0}},
3059 { UINT_MAX, { 0, 0}},
3060 },
3061 },
3062 {
3063 /* Four RB / SE */
3064 {
3065 /* One shader engine */
3066 { 0, {128, 256}},
3067 { 2, {128, 128}},
3068 { 3, { 64, 128}},
3069 { 5, { 32, 128}},
3070 { 9, { 16, 128}},
3071 { 33, { 0, 0}},
3072 { UINT_MAX, { 0, 0}},
3073 },
3074 {
3075 /* Two shader engines */
3076 { 0, {256, 256}},
3077 { 2, {128, 256}},
3078 { 3, {128, 128}},
3079 { 5, { 64, 128}},
3080 { 9, { 32, 128}},
3081 { 17, { 16, 128}},
3082 { 33, { 0, 0}},
3083 { UINT_MAX, { 0, 0}},
3084 },
3085 {
3086 /* Four shader engines */
3087 { 0, {256, 512}},
3088 { 2, {256, 256}},
3089 { 3, {128, 256}},
3090 { 5, {128, 128}},
3091 { 9, { 64, 128}},
3092 { 17, { 16, 128}},
3093 { 33, { 0, 0}},
3094 { UINT_MAX, { 0, 0}},
3095 },
3096 },
3097 };
3098 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3099 {
3100 // One RB / SE
3101 {
3102 // One shader engine
3103 { 0, {128, 256}},
3104 { 2, {128, 128}},
3105 { 4, { 64, 128}},
3106 { 7, { 32, 128}},
3107 { 13, { 16, 128}},
3108 { 49, { 0, 0}},
3109 { UINT_MAX, { 0, 0}},
3110 },
3111 {
3112 // Two shader engines
3113 { 0, {256, 256}},
3114 { 2, {128, 256}},
3115 { 4, {128, 128}},
3116 { 7, { 64, 128}},
3117 { 13, { 32, 128}},
3118 { 25, { 16, 128}},
3119 { 49, { 0, 0}},
3120 { UINT_MAX, { 0, 0}},
3121 },
3122 {
3123 // Four shader engines
3124 { 0, {256, 512}},
3125 { 2, {256, 256}},
3126 { 4, {128, 256}},
3127 { 7, {128, 128}},
3128 { 13, { 64, 128}},
3129 { 25, { 16, 128}},
3130 { 49, { 0, 0}},
3131 { UINT_MAX, { 0, 0}},
3132 },
3133 },
3134 {
3135 // Two RB / SE
3136 {
3137 // One shader engine
3138 { 0, {256, 256}},
3139 { 2, {128, 256}},
3140 { 4, {128, 128}},
3141 { 7, { 64, 128}},
3142 { 13, { 32, 128}},
3143 { 25, { 16, 128}},
3144 { 97, { 0, 0}},
3145 { UINT_MAX, { 0, 0}},
3146 },
3147 {
3148 // Two shader engines
3149 { 0, {256, 512}},
3150 { 2, {256, 256}},
3151 { 4, {128, 256}},
3152 { 7, {128, 128}},
3153 { 13, { 64, 128}},
3154 { 25, { 32, 128}},
3155 { 49, { 16, 128}},
3156 { 97, { 0, 0}},
3157 { UINT_MAX, { 0, 0}},
3158 },
3159 {
3160 // Four shader engines
3161 { 0, {512, 512}},
3162 { 2, {256, 512}},
3163 { 4, {256, 256}},
3164 { 7, {128, 256}},
3165 { 13, {128, 128}},
3166 { 25, { 64, 128}},
3167 { 49, { 16, 128}},
3168 { 97, { 0, 0}},
3169 { UINT_MAX, { 0, 0}},
3170 },
3171 },
3172 {
3173 // Four RB / SE
3174 {
3175 // One shader engine
3176 { 0, {256, 512}},
3177 { 2, {256, 256}},
3178 { 4, {128, 256}},
3179 { 7, {128, 128}},
3180 { 13, { 64, 128}},
3181 { 25, { 32, 128}},
3182 { 49, { 16, 128}},
3183 { UINT_MAX, { 0, 0}},
3184 },
3185 {
3186 // Two shader engines
3187 { 0, {512, 512}},
3188 { 2, {256, 512}},
3189 { 4, {256, 256}},
3190 { 7, {128, 256}},
3191 { 13, {128, 128}},
3192 { 25, { 64, 128}},
3193 { 49, { 32, 128}},
3194 { 97, { 16, 128}},
3195 { UINT_MAX, { 0, 0}},
3196 },
3197 {
3198 // Four shader engines
3199 { 0, {512, 512}},
3200 { 4, {256, 512}},
3201 { 7, {256, 256}},
3202 { 13, {128, 256}},
3203 { 25, {128, 128}},
3204 { 49, { 64, 128}},
3205 { 97, { 16, 128}},
3206 { UINT_MAX, { 0, 0}},
3207 },
3208 },
3209 };
3210
3211 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3212 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3213 VkExtent2D extent = {512, 512};
3214
3215 unsigned log_num_rb_per_se =
3216 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3217 pipeline->device->physical_device->rad_info.max_se);
3218 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3219
3220 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3221 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3222 unsigned effective_samples = total_samples;
3223 unsigned color_bytes_per_pixel = 0;
3224
3225 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3226 if (vkblend) {
3227 for (unsigned i = 0; i < subpass->color_count; i++) {
3228 if (!vkblend->pAttachments[i].colorWriteMask)
3229 continue;
3230
3231 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3232 continue;
3233
3234 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3235 color_bytes_per_pixel += vk_format_get_blocksize(format);
3236 }
3237
3238 /* MSAA images typically don't use all samples all the time. */
3239 if (effective_samples >= 2 && ps_iter_samples <= 1)
3240 effective_samples = 2;
3241 color_bytes_per_pixel *= effective_samples;
3242 }
3243
3244 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3245 while(color_entry[1].bpp <= color_bytes_per_pixel)
3246 ++color_entry;
3247
3248 extent = color_entry->extent;
3249
3250 if (subpass->depth_stencil_attachment) {
3251 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3252
3253 /* Coefficients taken from AMDVLK */
3254 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3255 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3256 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3257
3258 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3259 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3260 ++ds_entry;
3261
3262 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3263 extent = ds_entry->extent;
3264 }
3265
3266 return extent;
3267 }
3268
3269 static VkExtent2D
3270 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3271 {
3272 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3273 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3274 VkExtent2D extent = {512, 512};
3275
3276 const unsigned db_tag_size = 64;
3277 const unsigned db_tag_count = 312;
3278 const unsigned color_tag_size = 1024;
3279 const unsigned color_tag_count = 31;
3280 const unsigned fmask_tag_size = 256;
3281 const unsigned fmask_tag_count = 44;
3282
3283 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3284 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3285
3286 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3287 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3288 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3289
3290 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3291 const unsigned samples_log = util_logbase2_ceil(total_samples);
3292
3293 unsigned color_bytes_per_pixel = 0;
3294 unsigned fmask_bytes_per_pixel = 0;
3295
3296 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3297 if (vkblend) {
3298 for (unsigned i = 0; i < subpass->color_count; i++) {
3299 if (!vkblend->pAttachments[i].colorWriteMask)
3300 continue;
3301
3302 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3303 continue;
3304
3305 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3306 color_bytes_per_pixel += vk_format_get_blocksize(format);
3307
3308 if (total_samples > 1) {
3309 assert(samples_log <= 3);
3310 const unsigned fmask_array[] = {0, 1, 1, 4};
3311 fmask_bytes_per_pixel += fmask_array[samples_log];
3312 }
3313 }
3314
3315 color_bytes_per_pixel *= total_samples;
3316 }
3317 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3318
3319 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3320 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3321 extent.height = 1ull << (color_pixel_count_log / 2);
3322
3323 if (fmask_bytes_per_pixel) {
3324 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3325
3326 const VkExtent2D fmask_extent = (VkExtent2D){
3327 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3328 .height = 1ull << (color_pixel_count_log / 2)
3329 };
3330
3331 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3332 extent = fmask_extent;
3333 }
3334
3335 if (subpass->depth_stencil_attachment) {
3336 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3337
3338 /* Coefficients taken from AMDVLK */
3339 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3340 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3341 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3342
3343 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3344
3345 const VkExtent2D db_extent = (VkExtent2D){
3346 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3347 .height = 1ull << (color_pixel_count_log / 2)
3348 };
3349
3350 if (db_extent.width * db_extent.height < extent.width * extent.height)
3351 extent = db_extent;
3352 }
3353
3354 extent.width = MAX2(extent.width, 128);
3355 extent.height = MAX2(extent.width, 64);
3356
3357 return extent;
3358 }
3359
3360 static void
3361 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3362 struct radv_pipeline *pipeline,
3363 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3364 {
3365 uint32_t pa_sc_binner_cntl_0 =
3366 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3367 S_028C44_DISABLE_START_OF_PRIM(1);
3368 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3369
3370 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3371 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3372 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3373 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3374 unsigned min_bytes_per_pixel = 0;
3375
3376 if (vkblend) {
3377 for (unsigned i = 0; i < subpass->color_count; i++) {
3378 if (!vkblend->pAttachments[i].colorWriteMask)
3379 continue;
3380
3381 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3382 continue;
3383
3384 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3385 unsigned bytes = vk_format_get_blocksize(format);
3386 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3387 min_bytes_per_pixel = bytes;
3388 }
3389 }
3390
3391 pa_sc_binner_cntl_0 =
3392 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3393 S_028C44_BIN_SIZE_X(0) |
3394 S_028C44_BIN_SIZE_Y(0) |
3395 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3396 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3397 S_028C44_DISABLE_START_OF_PRIM(1);
3398 }
3399
3400 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3401 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3402 }
3403
3404 static void
3405 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3406 struct radv_pipeline *pipeline,
3407 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3408 const struct radv_blend_state *blend)
3409 {
3410 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3411 return;
3412
3413 VkExtent2D bin_size;
3414 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3415 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3416 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3417 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3418 } else
3419 unreachable("Unhandled generation for binning bin size calculation");
3420
3421 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3422 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3423 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3424 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3425
3426 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3427 context_states_per_bin = 1;
3428 persistent_states_per_bin = 1;
3429 fpovs_per_batch = 63;
3430 } else {
3431 /* The context states are affected by the scissor bug. */
3432 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3433 /* 32 causes hangs for RAVEN. */
3434 persistent_states_per_bin = 16;
3435 fpovs_per_batch = 63;
3436 }
3437
3438 bool disable_start_of_prim = true;
3439 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3440
3441 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3442
3443 if (pipeline->device->dfsm_allowed && ps &&
3444 !ps->info.ps.can_discard &&
3445 !ps->info.ps.writes_memory &&
3446 blend->cb_target_enabled_4bit) {
3447 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3448 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3449 }
3450
3451 const uint32_t pa_sc_binner_cntl_0 =
3452 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3453 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3454 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3455 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3456 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3457 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3458 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3459 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3460 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3461 S_028C44_OPTIMAL_BIN_SELECTION(1);
3462
3463 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3464 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3465 } else
3466 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3467 }
3468
3469
3470 static void
3471 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3472 struct radv_pipeline *pipeline,
3473 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3474 const struct radv_graphics_pipeline_create_info *extra)
3475 {
3476 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3477 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3478 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3479 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3480 struct radv_render_pass_attachment *attachment = NULL;
3481 uint32_t db_depth_control = 0, db_stencil_control = 0;
3482 uint32_t db_render_control = 0, db_render_override2 = 0;
3483 uint32_t db_render_override = 0;
3484
3485 if (subpass->depth_stencil_attachment)
3486 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3487
3488 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3489 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3490
3491 if (vkds && has_depth_attachment) {
3492 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3493 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3494 S_028800_ZFUNC(vkds->depthCompareOp) |
3495 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3496
3497 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3498 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3499 }
3500
3501 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3502 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3503 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3504 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3505 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3506 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3507
3508 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3509 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3510 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3511 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3512 }
3513
3514 if (attachment && extra) {
3515 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3516 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3517
3518 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3519 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3520 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3521 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3522 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3523 }
3524
3525 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3526 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3527
3528 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3529 ps->info.ps.writes_z) {
3530 /* From VK_EXT_depth_range_unrestricted spec:
3531 *
3532 * "The behavior described in Primitive Clipping still applies.
3533 * If depth clamping is disabled the depth values are still
3534 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3535 * depth clamping is enabled the above equation is ignored and
3536 * the depth values are instead clamped to the VkViewport
3537 * minDepth and maxDepth values, which in the case of this
3538 * extension can be outside of the 0.0 to 1.0 range."
3539 */
3540 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3541 }
3542
3543 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3544 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3545
3546 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3547 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3548 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3549 }
3550
3551 static void
3552 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3553 struct radv_pipeline *pipeline,
3554 const struct radv_blend_state *blend)
3555 {
3556 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3557 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3558 8);
3559 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3560 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3561
3562 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3563
3564 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3565 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3566 }
3567
3568 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3569
3570 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3571 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3572
3573 pipeline->graphics.col_format = blend->spi_shader_col_format;
3574 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3575 }
3576
3577 static const VkConservativeRasterizationModeEXT
3578 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3579 {
3580 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3581 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3582
3583 if (!conservative_raster)
3584 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3585 return conservative_raster->conservativeRasterizationMode;
3586 }
3587
3588 static void
3589 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3590 struct radv_pipeline *pipeline,
3591 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3592 {
3593 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3594 const VkConservativeRasterizationModeEXT mode =
3595 radv_get_conservative_raster_mode(vkraster);
3596 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3597 bool depth_clip_disable = vkraster->depthClampEnable;
3598
3599 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3600 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3601 if (depth_clip_state) {
3602 depth_clip_disable = !depth_clip_state->depthClipEnable;
3603 }
3604
3605 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3606 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3607 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3608 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3609 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3610 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3611
3612 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3613 S_0286D4_FLAT_SHADE_ENA(1) |
3614 S_0286D4_PNT_SPRITE_ENA(1) |
3615 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3616 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3617 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3618 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3619 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3620
3621 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3622 S_028BE4_PIX_CENTER(1) | // TODO verify
3623 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3624 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3625
3626 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3627 S_028814_FACE(vkraster->frontFace) |
3628 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3629 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3630 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3631 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3632 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3633 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3634 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3635 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3636
3637 /* Conservative rasterization. */
3638 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3639 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3640
3641 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3642 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3643 S_028804_OVERRASTERIZATION_AMOUNT(4);
3644
3645 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3646 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3647 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3648
3649 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3650 pa_sc_conservative_rast |=
3651 S_028C4C_OVER_RAST_ENABLE(1) |
3652 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3653 S_028C4C_UNDER_RAST_ENABLE(0) |
3654 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3655 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3656 } else {
3657 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3658 pa_sc_conservative_rast |=
3659 S_028C4C_OVER_RAST_ENABLE(0) |
3660 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3661 S_028C4C_UNDER_RAST_ENABLE(1) |
3662 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3663 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3664 }
3665 }
3666
3667 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3668 pa_sc_conservative_rast);
3669 }
3670
3671
3672 static void
3673 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3674 struct radv_pipeline *pipeline)
3675 {
3676 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3677
3678 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3679 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3680 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3681
3682 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3683 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3684 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3685 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3686 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3687
3688 /* The exclusion bits can be set to improve rasterization efficiency
3689 * if no sample lies on the pixel boundary (-8 sample offset). It's
3690 * currently always TRUE because the driver doesn't support 16 samples.
3691 */
3692 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3693 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3694 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3695 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3696
3697 /* GFX9: Flush DFSM when the AA mode changes. */
3698 if (pipeline->device->dfsm_allowed) {
3699 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3700 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3701 }
3702 }
3703
3704 static void
3705 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3706 struct radv_pipeline *pipeline)
3707 {
3708 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3709 const struct radv_shader_variant *vs =
3710 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3711 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3712 pipeline->shaders[MESA_SHADER_VERTEX];
3713 unsigned vgt_primitiveid_en = 0;
3714 uint32_t vgt_gs_mode = 0;
3715
3716 if (radv_pipeline_has_ngg(pipeline))
3717 return;
3718
3719 if (radv_pipeline_has_gs(pipeline)) {
3720 const struct radv_shader_variant *gs =
3721 pipeline->shaders[MESA_SHADER_GEOMETRY];
3722
3723 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3724 pipeline->device->physical_device->rad_info.chip_class);
3725 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3726 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3727 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3728 }
3729
3730 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3731 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3732 }
3733
3734 static void
3735 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3736 struct radeon_cmdbuf *cs,
3737 struct radv_pipeline *pipeline,
3738 struct radv_shader_variant *shader)
3739 {
3740 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3741
3742 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3743 radeon_emit(cs, va >> 8);
3744 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3745 radeon_emit(cs, shader->config.rsrc1);
3746 radeon_emit(cs, shader->config.rsrc2);
3747
3748 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3749 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3750 clip_dist_mask = outinfo->clip_dist_mask;
3751 cull_dist_mask = outinfo->cull_dist_mask;
3752 total_mask = clip_dist_mask | cull_dist_mask;
3753 bool misc_vec_ena = outinfo->writes_pointsize ||
3754 outinfo->writes_layer ||
3755 outinfo->writes_viewport_index;
3756 unsigned spi_vs_out_config, nparams;
3757
3758 /* VS is required to export at least one param. */
3759 nparams = MAX2(outinfo->param_exports, 1);
3760 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3761
3762 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3763 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3764 }
3765
3766 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3767
3768 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3769 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3770 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3771 V_02870C_SPI_SHADER_4COMP :
3772 V_02870C_SPI_SHADER_NONE) |
3773 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3774 V_02870C_SPI_SHADER_4COMP :
3775 V_02870C_SPI_SHADER_NONE) |
3776 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3777 V_02870C_SPI_SHADER_4COMP :
3778 V_02870C_SPI_SHADER_NONE));
3779
3780 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3781 S_028818_VTX_W0_FMT(1) |
3782 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3783 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3784 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3785
3786 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3787 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3788 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3789 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3790 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3791 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3792 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3793 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3794 cull_dist_mask << 8 |
3795 clip_dist_mask);
3796
3797 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3798 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3799 outinfo->writes_viewport_index);
3800 }
3801
3802 static void
3803 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3804 struct radv_pipeline *pipeline,
3805 struct radv_shader_variant *shader)
3806 {
3807 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3808
3809 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3810 radeon_emit(cs, va >> 8);
3811 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3812 radeon_emit(cs, shader->config.rsrc1);
3813 radeon_emit(cs, shader->config.rsrc2);
3814 }
3815
3816 static void
3817 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3818 struct radv_pipeline *pipeline,
3819 struct radv_shader_variant *shader,
3820 const struct radv_tessellation_state *tess)
3821 {
3822 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3823 uint32_t rsrc2 = shader->config.rsrc2;
3824
3825 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3826 radeon_emit(cs, va >> 8);
3827 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3828
3829 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3830 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3831 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3832 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3833
3834 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3835 radeon_emit(cs, shader->config.rsrc1);
3836 radeon_emit(cs, rsrc2);
3837 }
3838
3839 static void
3840 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3841 struct radeon_cmdbuf *cs,
3842 struct radv_pipeline *pipeline,
3843 struct radv_shader_variant *shader)
3844 {
3845 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3846 gl_shader_stage es_type =
3847 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3848 struct radv_shader_variant *es =
3849 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3850 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3851
3852 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3853 radeon_emit(cs, va >> 8);
3854 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3855 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3856 radeon_emit(cs, shader->config.rsrc1);
3857 radeon_emit(cs, shader->config.rsrc2);
3858
3859 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3860 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3861 clip_dist_mask = outinfo->clip_dist_mask;
3862 cull_dist_mask = outinfo->cull_dist_mask;
3863 total_mask = clip_dist_mask | cull_dist_mask;
3864 bool misc_vec_ena = outinfo->writes_pointsize ||
3865 outinfo->writes_layer ||
3866 outinfo->writes_viewport_index;
3867 bool es_enable_prim_id = outinfo->export_prim_id ||
3868 (es && es->info.uses_prim_id);
3869 bool break_wave_at_eoi = false;
3870 unsigned ge_cntl;
3871 unsigned nparams;
3872
3873 if (es_type == MESA_SHADER_TESS_EVAL) {
3874 struct radv_shader_variant *gs =
3875 pipeline->shaders[MESA_SHADER_GEOMETRY];
3876
3877 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3878 break_wave_at_eoi = true;
3879 }
3880
3881 nparams = MAX2(outinfo->param_exports, 1);
3882 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3883 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3884 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3885
3886 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3887 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3888 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3889 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3890 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3891 V_02870C_SPI_SHADER_4COMP :
3892 V_02870C_SPI_SHADER_NONE) |
3893 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3894 V_02870C_SPI_SHADER_4COMP :
3895 V_02870C_SPI_SHADER_NONE) |
3896 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3897 V_02870C_SPI_SHADER_4COMP :
3898 V_02870C_SPI_SHADER_NONE));
3899
3900 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3901 S_028818_VTX_W0_FMT(1) |
3902 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3903 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3904 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3905 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3906 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3907 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3908 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3909 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3910 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3911 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3912 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3913 cull_dist_mask << 8 |
3914 clip_dist_mask);
3915
3916 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3917 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3918 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3919
3920 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3921 ngg_state->vgt_esgs_ring_itemsize);
3922
3923 /* NGG specific registers. */
3924 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3925 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3926
3927 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3928 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3929 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3930 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3931 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3932 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3933 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3934 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3935 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3936 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3937 S_028B90_CNT(gs_num_invocations) |
3938 S_028B90_ENABLE(gs_num_invocations > 1) |
3939 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3940
3941 /* User edge flags are set by the pos exports. If user edge flags are
3942 * not used, we must use hw-generated edge flags and pass them via
3943 * the prim export to prevent drawing lines on internal edges of
3944 * decomposed primitives (such as quads) with polygon mode = lines.
3945 *
3946 * TODO: We should combine hw-generated edge flags with user edge
3947 * flags in the shader.
3948 */
3949 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3950 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3951 !radv_pipeline_has_gs(pipeline)));
3952
3953 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3954 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3955 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3956
3957 /* Bug workaround for a possible hang with non-tessellation cases.
3958 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3959 *
3960 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3961 */
3962 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3963 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3964 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3965 !radv_pipeline_has_tess(pipeline) &&
3966 ngg_state->hw_max_esverts != 256) {
3967 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3968
3969 if (ngg_state->hw_max_esverts > 5) {
3970 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3971 }
3972 }
3973
3974 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3975 }
3976
3977 static void
3978 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3979 struct radv_pipeline *pipeline,
3980 struct radv_shader_variant *shader,
3981 const struct radv_tessellation_state *tess)
3982 {
3983 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3984
3985 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3986 unsigned hs_rsrc2 = shader->config.rsrc2;
3987
3988 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3989 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3990 } else {
3991 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3992 }
3993
3994 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3995 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3996 radeon_emit(cs, va >> 8);
3997 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3998 } else {
3999 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4000 radeon_emit(cs, va >> 8);
4001 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4002 }
4003
4004 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4005 radeon_emit(cs, shader->config.rsrc1);
4006 radeon_emit(cs, hs_rsrc2);
4007 } else {
4008 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4009 radeon_emit(cs, va >> 8);
4010 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4011 radeon_emit(cs, shader->config.rsrc1);
4012 radeon_emit(cs, shader->config.rsrc2);
4013 }
4014 }
4015
4016 static void
4017 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4018 struct radeon_cmdbuf *cs,
4019 struct radv_pipeline *pipeline,
4020 const struct radv_tessellation_state *tess)
4021 {
4022 struct radv_shader_variant *vs;
4023
4024 /* Skip shaders merged into HS/GS */
4025 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4026 if (!vs)
4027 return;
4028
4029 if (vs->info.vs.as_ls)
4030 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4031 else if (vs->info.vs.as_es)
4032 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4033 else if (vs->info.is_ngg)
4034 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4035 else
4036 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4037 }
4038
4039 static void
4040 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4041 struct radeon_cmdbuf *cs,
4042 struct radv_pipeline *pipeline,
4043 const struct radv_tessellation_state *tess)
4044 {
4045 if (!radv_pipeline_has_tess(pipeline))
4046 return;
4047
4048 struct radv_shader_variant *tes, *tcs;
4049
4050 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4051 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4052
4053 if (tes) {
4054 if (tes->info.is_ngg) {
4055 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4056 } else if (tes->info.tes.as_es)
4057 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4058 else
4059 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4060 }
4061
4062 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4063
4064 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4065 tess->tf_param);
4066
4067 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4068 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4069 tess->ls_hs_config);
4070 else
4071 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4072 tess->ls_hs_config);
4073
4074 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4075 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4076 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4077 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4078 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4079 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4080 }
4081 }
4082
4083 static void
4084 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4085 struct radeon_cmdbuf *cs,
4086 struct radv_pipeline *pipeline,
4087 struct radv_shader_variant *gs)
4088 {
4089 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4090 unsigned gs_max_out_vertices;
4091 uint8_t *num_components;
4092 uint8_t max_stream;
4093 unsigned offset;
4094 uint64_t va;
4095
4096 gs_max_out_vertices = gs->info.gs.vertices_out;
4097 max_stream = gs->info.gs.max_stream;
4098 num_components = gs->info.gs.num_stream_output_components;
4099
4100 offset = num_components[0] * gs_max_out_vertices;
4101
4102 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4103 radeon_emit(ctx_cs, offset);
4104 if (max_stream >= 1)
4105 offset += num_components[1] * gs_max_out_vertices;
4106 radeon_emit(ctx_cs, offset);
4107 if (max_stream >= 2)
4108 offset += num_components[2] * gs_max_out_vertices;
4109 radeon_emit(ctx_cs, offset);
4110 if (max_stream >= 3)
4111 offset += num_components[3] * gs_max_out_vertices;
4112 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4113
4114 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4115 radeon_emit(ctx_cs, num_components[0]);
4116 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4117 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4118 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4119
4120 uint32_t gs_num_invocations = gs->info.gs.invocations;
4121 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4122 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4123 S_028B90_ENABLE(gs_num_invocations > 0));
4124
4125 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4126 gs_state->vgt_esgs_ring_itemsize);
4127
4128 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4129
4130 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4131 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4132 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4133 radeon_emit(cs, va >> 8);
4134 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4135 } else {
4136 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4137 radeon_emit(cs, va >> 8);
4138 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4139 }
4140
4141 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4142 radeon_emit(cs, gs->config.rsrc1);
4143 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4144
4145 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4146 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4147 } else {
4148 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4149 radeon_emit(cs, va >> 8);
4150 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4151 radeon_emit(cs, gs->config.rsrc1);
4152 radeon_emit(cs, gs->config.rsrc2);
4153 }
4154
4155 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4156 }
4157
4158 static void
4159 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4160 struct radeon_cmdbuf *cs,
4161 struct radv_pipeline *pipeline)
4162 {
4163 struct radv_shader_variant *gs;
4164
4165 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4166 if (!gs)
4167 return;
4168
4169 if (gs->info.is_ngg)
4170 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4171 else
4172 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4173
4174 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4175 gs->info.gs.vertices_out);
4176 }
4177
4178 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4179 {
4180 uint32_t ps_input_cntl;
4181 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4182 ps_input_cntl = S_028644_OFFSET(offset);
4183 if (flat_shade)
4184 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4185 if (float16) {
4186 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4187 S_028644_ATTR0_VALID(1);
4188 }
4189 } else {
4190 /* The input is a DEFAULT_VAL constant. */
4191 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4192 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4193 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4194 ps_input_cntl = S_028644_OFFSET(0x20) |
4195 S_028644_DEFAULT_VAL(offset);
4196 }
4197 return ps_input_cntl;
4198 }
4199
4200 static void
4201 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4202 struct radv_pipeline *pipeline)
4203 {
4204 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4205 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4206 uint32_t ps_input_cntl[32];
4207
4208 unsigned ps_offset = 0;
4209
4210 if (ps->info.ps.prim_id_input) {
4211 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4212 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4213 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4214 ++ps_offset;
4215 }
4216 }
4217
4218 if (ps->info.ps.layer_input ||
4219 ps->info.needs_multiview_view_index) {
4220 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4221 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4222 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4223 else
4224 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4225 ++ps_offset;
4226 }
4227
4228 if (ps->info.ps.has_pcoord) {
4229 unsigned val;
4230 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4231 ps_input_cntl[ps_offset] = val;
4232 ps_offset++;
4233 }
4234
4235 if (ps->info.ps.num_input_clips_culls) {
4236 unsigned vs_offset;
4237
4238 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4239 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4240 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4241 ++ps_offset;
4242 }
4243
4244 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4245 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4246 ps->info.ps.num_input_clips_culls > 4) {
4247 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4248 ++ps_offset;
4249 }
4250 }
4251
4252 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4253 unsigned vs_offset;
4254 bool flat_shade;
4255 bool float16;
4256 if (!(ps->info.ps.input_mask & (1u << i)))
4257 continue;
4258
4259 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4260 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4261 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4262 ++ps_offset;
4263 continue;
4264 }
4265
4266 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4267 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4268
4269 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4270 ++ps_offset;
4271 }
4272
4273 if (ps_offset) {
4274 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4275 for (unsigned i = 0; i < ps_offset; i++) {
4276 radeon_emit(ctx_cs, ps_input_cntl[i]);
4277 }
4278 }
4279 }
4280
4281 static uint32_t
4282 radv_compute_db_shader_control(const struct radv_device *device,
4283 const struct radv_pipeline *pipeline,
4284 const struct radv_shader_variant *ps)
4285 {
4286 unsigned z_order;
4287 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4288 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4289 else
4290 z_order = V_02880C_LATE_Z;
4291
4292 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4293 !device->physical_device->rad_info.rbplus_allowed;
4294
4295 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4296 * but this appears to break Project Cars (DXVK). See
4297 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4298 */
4299 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4300
4301 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4302 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4303 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4304 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4305 S_02880C_Z_ORDER(z_order) |
4306 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4307 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4308 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4309 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4310 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4311 }
4312
4313 static void
4314 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4315 struct radeon_cmdbuf *cs,
4316 struct radv_pipeline *pipeline)
4317 {
4318 struct radv_shader_variant *ps;
4319 uint64_t va;
4320 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4321
4322 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4323 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4324
4325 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4326 radeon_emit(cs, va >> 8);
4327 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4328 radeon_emit(cs, ps->config.rsrc1);
4329 radeon_emit(cs, ps->config.rsrc2);
4330
4331 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4332 radv_compute_db_shader_control(pipeline->device,
4333 pipeline, ps));
4334
4335 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4336 ps->config.spi_ps_input_ena);
4337
4338 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4339 ps->config.spi_ps_input_addr);
4340
4341 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4342 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4343 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4344
4345 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4346
4347 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4348 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4349 ps->info.ps.writes_stencil,
4350 ps->info.ps.writes_sample_mask));
4351
4352 if (pipeline->device->dfsm_allowed) {
4353 /* optimise this? */
4354 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4355 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4356 }
4357 }
4358
4359 static void
4360 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4361 struct radv_pipeline *pipeline)
4362 {
4363 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4364 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4365 return;
4366
4367 unsigned vtx_reuse_depth = 30;
4368 if (radv_pipeline_has_tess(pipeline) &&
4369 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4370 vtx_reuse_depth = 14;
4371 }
4372 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4373 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4374 }
4375
4376 static uint32_t
4377 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4378 {
4379 uint32_t stages = 0;
4380 if (radv_pipeline_has_tess(pipeline)) {
4381 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4382 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4383
4384 if (radv_pipeline_has_gs(pipeline))
4385 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4386 S_028B54_GS_EN(1);
4387 else if (radv_pipeline_has_ngg(pipeline))
4388 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4389 else
4390 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4391 } else if (radv_pipeline_has_gs(pipeline)) {
4392 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4393 S_028B54_GS_EN(1);
4394 } else if (radv_pipeline_has_ngg(pipeline)) {
4395 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4396 }
4397
4398 if (radv_pipeline_has_ngg(pipeline)) {
4399 stages |= S_028B54_PRIMGEN_EN(1);
4400 if (pipeline->streamout_shader)
4401 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4402 } else if (radv_pipeline_has_gs(pipeline)) {
4403 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4404 }
4405
4406 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4407 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4408
4409 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4410 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4411
4412 if (radv_pipeline_has_tess(pipeline))
4413 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4414
4415 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4416 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4417 if (pipeline->gs_copy_shader)
4418 vs_size = pipeline->gs_copy_shader->info.wave_size;
4419 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4420 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4421 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4422 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4423
4424 if (radv_pipeline_has_ngg(pipeline))
4425 gs_size = vs_size;
4426
4427 /* legacy GS only supports Wave64 */
4428 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4429 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4430 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4431 }
4432
4433 return stages;
4434 }
4435
4436 static uint32_t
4437 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4438 {
4439 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4440 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4441
4442 if (!discard_rectangle_info)
4443 return 0xffff;
4444
4445 unsigned mask = 0;
4446
4447 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4448 /* Interpret i as a bitmask, and then set the bit in the mask if
4449 * that combination of rectangles in which the pixel is contained
4450 * should pass the cliprect test. */
4451 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4452
4453 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4454 !relevant_subset)
4455 continue;
4456
4457 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4458 relevant_subset)
4459 continue;
4460
4461 mask |= 1u << i;
4462 }
4463
4464 return mask;
4465 }
4466
4467 static void
4468 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4469 struct radv_pipeline *pipeline,
4470 const struct radv_tessellation_state *tess)
4471 {
4472 bool break_wave_at_eoi = false;
4473 unsigned primgroup_size;
4474 unsigned vertgroup_size;
4475
4476 if (radv_pipeline_has_tess(pipeline)) {
4477 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4478 vertgroup_size = 0;
4479 } else if (radv_pipeline_has_gs(pipeline)) {
4480 const struct gfx9_gs_info *gs_state =
4481 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4482 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4483 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4484 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4485 } else {
4486 primgroup_size = 128; /* recommended without a GS and tess */
4487 vertgroup_size = 0;
4488 }
4489
4490 if (radv_pipeline_has_tess(pipeline)) {
4491 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4492 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4493 break_wave_at_eoi = true;
4494 }
4495
4496 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4497 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4498 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4499 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4500 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4501 }
4502
4503 static void
4504 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4505 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4506 const struct radv_graphics_pipeline_create_info *extra,
4507 const struct radv_blend_state *blend,
4508 const struct radv_tessellation_state *tess,
4509 unsigned prim, unsigned gs_out)
4510 {
4511 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4512 struct radeon_cmdbuf *cs = &pipeline->cs;
4513
4514 cs->max_dw = 64;
4515 ctx_cs->max_dw = 256;
4516 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4517 ctx_cs->buf = cs->buf + cs->max_dw;
4518
4519 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4520 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4521 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4522 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4523 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4524 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4525 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4526 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4527 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4528 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4529 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4530 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4531
4532 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4533 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4534
4535 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4536
4537 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4538 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4539 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4540 } else {
4541 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4542 }
4543 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4544
4545 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4546
4547 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4548
4549 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4550 assert(cs->cdw <= cs->max_dw);
4551 }
4552
4553 static struct radv_ia_multi_vgt_param_helpers
4554 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4555 const struct radv_tessellation_state *tess,
4556 uint32_t prim)
4557 {
4558 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4559 const struct radv_device *device = pipeline->device;
4560
4561 if (radv_pipeline_has_tess(pipeline))
4562 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4563 else if (radv_pipeline_has_gs(pipeline))
4564 ia_multi_vgt_param.primgroup_size = 64;
4565 else
4566 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4567
4568 /* GS requirement. */
4569 ia_multi_vgt_param.partial_es_wave = false;
4570 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4571 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4572 ia_multi_vgt_param.partial_es_wave = true;
4573
4574 ia_multi_vgt_param.wd_switch_on_eop = false;
4575 if (device->physical_device->rad_info.chip_class >= GFX7) {
4576 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4577 * 4 shader engines. Set 1 to pass the assertion below.
4578 * The other cases are hardware requirements. */
4579 if (device->physical_device->rad_info.max_se < 4 ||
4580 prim == V_008958_DI_PT_POLYGON ||
4581 prim == V_008958_DI_PT_LINELOOP ||
4582 prim == V_008958_DI_PT_TRIFAN ||
4583 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4584 (pipeline->graphics.prim_restart_enable &&
4585 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4586 (prim != V_008958_DI_PT_POINTLIST &&
4587 prim != V_008958_DI_PT_LINESTRIP))))
4588 ia_multi_vgt_param.wd_switch_on_eop = true;
4589 }
4590
4591 ia_multi_vgt_param.ia_switch_on_eoi = false;
4592 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4593 ia_multi_vgt_param.ia_switch_on_eoi = true;
4594 if (radv_pipeline_has_gs(pipeline) &&
4595 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4596 ia_multi_vgt_param.ia_switch_on_eoi = true;
4597 if (radv_pipeline_has_tess(pipeline)) {
4598 /* SWITCH_ON_EOI must be set if PrimID is used. */
4599 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4600 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4601 ia_multi_vgt_param.ia_switch_on_eoi = true;
4602 }
4603
4604 ia_multi_vgt_param.partial_vs_wave = false;
4605 if (radv_pipeline_has_tess(pipeline)) {
4606 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4607 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4608 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4609 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4610 radv_pipeline_has_gs(pipeline))
4611 ia_multi_vgt_param.partial_vs_wave = true;
4612 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4613 if (device->physical_device->rad_info.has_distributed_tess) {
4614 if (radv_pipeline_has_gs(pipeline)) {
4615 if (device->physical_device->rad_info.chip_class <= GFX8)
4616 ia_multi_vgt_param.partial_es_wave = true;
4617 } else {
4618 ia_multi_vgt_param.partial_vs_wave = true;
4619 }
4620 }
4621 }
4622
4623 /* Workaround for a VGT hang when strip primitive types are used with
4624 * primitive restart.
4625 */
4626 if (pipeline->graphics.prim_restart_enable &&
4627 (prim == V_008958_DI_PT_LINESTRIP ||
4628 prim == V_008958_DI_PT_TRISTRIP ||
4629 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4630 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4631 ia_multi_vgt_param.partial_vs_wave = true;
4632 }
4633
4634 if (radv_pipeline_has_gs(pipeline)) {
4635 /* On these chips there is the possibility of a hang if the
4636 * pipeline uses a GS and partial_vs_wave is not set.
4637 *
4638 * This mostly does not hit 4-SE chips, as those typically set
4639 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4640 * with GS due to another workaround.
4641 *
4642 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4643 */
4644 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4645 device->physical_device->rad_info.family == CHIP_FIJI ||
4646 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4647 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4648 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4649 device->physical_device->rad_info.family == CHIP_VEGAM) {
4650 ia_multi_vgt_param.partial_vs_wave = true;
4651 }
4652 }
4653
4654 ia_multi_vgt_param.base =
4655 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4656 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4657 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4658 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4659 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4660
4661 return ia_multi_vgt_param;
4662 }
4663
4664
4665 static void
4666 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4667 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4668 {
4669 const VkPipelineVertexInputStateCreateInfo *vi_info =
4670 pCreateInfo->pVertexInputState;
4671 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4672
4673 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4674 const VkVertexInputAttributeDescription *desc =
4675 &vi_info->pVertexAttributeDescriptions[i];
4676 unsigned loc = desc->location;
4677 const struct vk_format_description *format_desc;
4678
4679 format_desc = vk_format_description(desc->format);
4680
4681 velems->format_size[loc] = format_desc->block.bits / 8;
4682 }
4683
4684 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4685 const VkVertexInputBindingDescription *desc =
4686 &vi_info->pVertexBindingDescriptions[i];
4687
4688 pipeline->binding_stride[desc->binding] = desc->stride;
4689 pipeline->num_vertex_bindings =
4690 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4691 }
4692 }
4693
4694 static struct radv_shader_variant *
4695 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4696 {
4697 int i;
4698
4699 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4700 struct radv_shader_variant *shader =
4701 radv_get_shader(pipeline, i);
4702
4703 if (shader && shader->info.so.num_outputs > 0)
4704 return shader;
4705 }
4706
4707 return NULL;
4708 }
4709
4710 static VkResult
4711 radv_secure_compile(struct radv_pipeline *pipeline,
4712 struct radv_device *device,
4713 const struct radv_pipeline_key *key,
4714 const VkPipelineShaderStageCreateInfo **pStages,
4715 const VkPipelineCreateFlags flags,
4716 unsigned num_stages)
4717 {
4718 uint8_t allowed_pipeline_hashes[2][20];
4719 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4720 pipeline->layout, key, get_hash_flags(device));
4721
4722 /* Generate the GC copy hash */
4723 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4724 allowed_pipeline_hashes[1][0] ^= 1;
4725
4726 uint8_t allowed_hashes[2][20];
4727 for (unsigned i = 0; i < 2; ++i) {
4728 disk_cache_compute_key(device->physical_device->disk_cache,
4729 allowed_pipeline_hashes[i], 20,
4730 allowed_hashes[i]);
4731 }
4732
4733 /* Do an early exit if all cache entries are already there. */
4734 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4735 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4736 void *copy_entry = NULL;
4737 if (may_need_copy_shader)
4738 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4739
4740 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4741 free(main_entry);
4742 free(copy_entry);
4743
4744 if(has_all_cache_entries)
4745 return VK_SUCCESS;
4746
4747 unsigned process = 0;
4748 uint8_t sc_threads = device->instance->num_sc_threads;
4749 while (true) {
4750 mtx_lock(&device->sc_state->secure_compile_mutex);
4751 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4752 device->sc_state->secure_compile_thread_counter++;
4753 for (unsigned i = 0; i < sc_threads; i++) {
4754 if (!device->sc_state->secure_compile_processes[i].in_use) {
4755 device->sc_state->secure_compile_processes[i].in_use = true;
4756 process = i;
4757 break;
4758 }
4759 }
4760 mtx_unlock(&device->sc_state->secure_compile_mutex);
4761 break;
4762 }
4763 mtx_unlock(&device->sc_state->secure_compile_mutex);
4764 }
4765
4766 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4767 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4768
4769 /* Fork a copy of the slim untainted secure compile process */
4770 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4771 write(fd_secure_input, &sc_type, sizeof(sc_type));
4772
4773 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4774 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4775 return VK_ERROR_DEVICE_LOST;
4776
4777 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4778 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4779
4780 /* Write pipeline / shader module out to secure process via pipe */
4781 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4782 write(fd_secure_input, &sc_type, sizeof(sc_type));
4783
4784 /* Write pipeline layout out to secure process */
4785 struct radv_pipeline_layout *layout = pipeline->layout;
4786 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4787 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4788 for (uint32_t set = 0; set < layout->num_sets; set++) {
4789 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4790 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4791 }
4792
4793 /* Write pipeline key out to secure process */
4794 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4795
4796 /* Write pipeline create flags out to secure process */
4797 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4798
4799 /* Write stage and shader information out to secure process */
4800 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4801 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4802 if (!pStages[i])
4803 continue;
4804
4805 /* Write stage out to secure process */
4806 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4807 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4808
4809 /* Write entry point name out to secure process */
4810 size_t name_size = strlen(pStages[i]->pName) + 1;
4811 write(fd_secure_input, &name_size, sizeof(size_t));
4812 write(fd_secure_input, pStages[i]->pName, name_size);
4813
4814 /* Write shader module out to secure process */
4815 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4816 assert(!module->nir);
4817 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4818 write(fd_secure_input, &module_size, sizeof(size_t));
4819 write(fd_secure_input, module, module_size);
4820
4821 /* Write specialization info out to secure process */
4822 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4823 bool has_spec_info = specInfo ? true : false;
4824 write(fd_secure_input, &has_spec_info, sizeof(bool));
4825 if (specInfo) {
4826 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4827 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4828
4829 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4830 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4831 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4832 }
4833 }
4834
4835 /* Read the data returned from the secure process */
4836 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4837 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4838 return VK_ERROR_DEVICE_LOST;
4839
4840 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4841 assert(device->physical_device->disk_cache);
4842
4843 uint8_t disk_sha1[20];
4844 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4845 return VK_ERROR_DEVICE_LOST;
4846
4847 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4848 memcmp(disk_sha1, allowed_hashes[1], 20))
4849 return VK_ERROR_DEVICE_LOST;
4850
4851 uint32_t entry_size;
4852 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4853 return VK_ERROR_DEVICE_LOST;
4854
4855 struct cache_entry *entry = malloc(entry_size);
4856 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4857 return VK_ERROR_DEVICE_LOST;
4858
4859 disk_cache_put(device->physical_device->disk_cache,
4860 disk_sha1, entry, entry_size,
4861 NULL);
4862
4863 free(entry);
4864 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4865 uint8_t disk_sha1[20];
4866 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4867 return VK_ERROR_DEVICE_LOST;
4868
4869 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4870 memcmp(disk_sha1, allowed_hashes[1], 20))
4871 return VK_ERROR_DEVICE_LOST;
4872
4873 size_t size;
4874 struct cache_entry *entry = (struct cache_entry *)
4875 disk_cache_get(device->physical_device->disk_cache,
4876 disk_sha1, &size);
4877
4878 uint8_t found = entry ? 1 : 0;
4879 write(fd_secure_input, &found, sizeof(uint8_t));
4880
4881 if (found) {
4882 write(fd_secure_input, &size, sizeof(size_t));
4883 write(fd_secure_input, entry, size);
4884 }
4885
4886 free(entry);
4887 }
4888 }
4889
4890 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
4891 write(fd_secure_input, &sc_type, sizeof(sc_type));
4892
4893 mtx_lock(&device->sc_state->secure_compile_mutex);
4894 device->sc_state->secure_compile_thread_counter--;
4895 device->sc_state->secure_compile_processes[process].in_use = false;
4896 mtx_unlock(&device->sc_state->secure_compile_mutex);
4897
4898 return VK_SUCCESS;
4899 }
4900
4901 static VkResult
4902 radv_pipeline_init(struct radv_pipeline *pipeline,
4903 struct radv_device *device,
4904 struct radv_pipeline_cache *cache,
4905 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4906 const struct radv_graphics_pipeline_create_info *extra)
4907 {
4908 VkResult result;
4909 bool has_view_index = false;
4910
4911 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4912 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4913 if (subpass->view_mask)
4914 has_view_index = true;
4915
4916 pipeline->device = device;
4917 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4918 assert(pipeline->layout);
4919
4920 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4921
4922 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4923 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4924 radv_init_feedback(creation_feedback);
4925
4926 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4927
4928 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4929 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4930 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4931 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4932 pStages[stage] = &pCreateInfo->pStages[i];
4933 if(creation_feedback)
4934 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4935 }
4936
4937 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4938 if (radv_device_use_secure_compile(device->instance)) {
4939 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
4940 } else {
4941 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4942 }
4943
4944 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4945 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4946 uint32_t gs_out;
4947 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4948
4949 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4950
4951 if (radv_pipeline_has_gs(pipeline)) {
4952 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4953 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4954 } else if (radv_pipeline_has_tess(pipeline)) {
4955 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4956 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4957 else
4958 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4959 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4960 } else {
4961 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4962 }
4963 if (extra && extra->use_rectlist) {
4964 prim = V_008958_DI_PT_RECTLIST;
4965 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4966 pipeline->graphics.can_use_guardband = true;
4967 if (radv_pipeline_has_ngg(pipeline))
4968 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4969 }
4970 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4971 /* prim vertex count will need TESS changes */
4972 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4973
4974 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4975
4976 /* Ensure that some export memory is always allocated, for two reasons:
4977 *
4978 * 1) Correctness: The hardware ignores the EXEC mask if no export
4979 * memory is allocated, so KILL and alpha test do not work correctly
4980 * without this.
4981 * 2) Performance: Every shader needs at least a NULL export, even when
4982 * it writes no color/depth output. The NULL export instruction
4983 * stalls without this setting.
4984 *
4985 * Don't add this to CB_SHADER_MASK.
4986 *
4987 * GFX10 supports pixel shaders without exports by setting both the
4988 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4989 * instructions if any are present.
4990 */
4991 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4992 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4993 ps->info.ps.can_discard) &&
4994 !blend.spi_shader_col_format) {
4995 if (!ps->info.ps.writes_z &&
4996 !ps->info.ps.writes_stencil &&
4997 !ps->info.ps.writes_sample_mask)
4998 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4999 }
5000
5001 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5002 if (pipeline->shaders[i]) {
5003 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5004 }
5005 }
5006
5007 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5008 struct radv_shader_variant *gs =
5009 pipeline->shaders[MESA_SHADER_GEOMETRY];
5010
5011 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5012 }
5013
5014 struct radv_tessellation_state tess = {0};
5015 if (radv_pipeline_has_tess(pipeline)) {
5016 if (prim == V_008958_DI_PT_PATCH) {
5017 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5018 pipeline->graphics.prim_vertex_count.incr = 1;
5019 }
5020 tess = calculate_tess_state(pipeline, pCreateInfo);
5021 }
5022
5023 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5024
5025 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5026
5027 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5028 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5029
5030 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5031 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5032 if (loc->sgpr_idx != -1) {
5033 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5034 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5035 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5036 pipeline->graphics.vtx_emit_num = 3;
5037 else
5038 pipeline->graphics.vtx_emit_num = 2;
5039 }
5040
5041 /* Find the last vertex shader stage that eventually uses streamout. */
5042 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5043
5044 result = radv_pipeline_scratch_init(device, pipeline);
5045 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5046
5047 return result;
5048 }
5049
5050 VkResult
5051 radv_graphics_pipeline_create(
5052 VkDevice _device,
5053 VkPipelineCache _cache,
5054 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5055 const struct radv_graphics_pipeline_create_info *extra,
5056 const VkAllocationCallbacks *pAllocator,
5057 VkPipeline *pPipeline)
5058 {
5059 RADV_FROM_HANDLE(radv_device, device, _device);
5060 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5061 struct radv_pipeline *pipeline;
5062 VkResult result;
5063
5064 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5065 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5066 if (pipeline == NULL)
5067 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5068
5069 result = radv_pipeline_init(pipeline, device, cache,
5070 pCreateInfo, extra);
5071 if (result != VK_SUCCESS) {
5072 radv_pipeline_destroy(device, pipeline, pAllocator);
5073 return result;
5074 }
5075
5076 *pPipeline = radv_pipeline_to_handle(pipeline);
5077
5078 return VK_SUCCESS;
5079 }
5080
5081 VkResult radv_CreateGraphicsPipelines(
5082 VkDevice _device,
5083 VkPipelineCache pipelineCache,
5084 uint32_t count,
5085 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5086 const VkAllocationCallbacks* pAllocator,
5087 VkPipeline* pPipelines)
5088 {
5089 VkResult result = VK_SUCCESS;
5090 unsigned i = 0;
5091
5092 for (; i < count; i++) {
5093 VkResult r;
5094 r = radv_graphics_pipeline_create(_device,
5095 pipelineCache,
5096 &pCreateInfos[i],
5097 NULL, pAllocator, &pPipelines[i]);
5098 if (r != VK_SUCCESS) {
5099 result = r;
5100 pPipelines[i] = VK_NULL_HANDLE;
5101 }
5102 }
5103
5104 return result;
5105 }
5106
5107
5108 static void
5109 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5110 {
5111 struct radv_shader_variant *compute_shader;
5112 struct radv_device *device = pipeline->device;
5113 unsigned threads_per_threadgroup;
5114 unsigned threadgroups_per_cu = 1;
5115 unsigned waves_per_threadgroup;
5116 unsigned max_waves_per_sh = 0;
5117 uint64_t va;
5118
5119 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5120 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5121
5122 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5123 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5124
5125 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5126 radeon_emit(&pipeline->cs, va >> 8);
5127 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5128
5129 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5130 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5131 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5132 if (device->physical_device->rad_info.chip_class >= GFX10) {
5133 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5134 }
5135
5136 /* Calculate best compute resource limits. */
5137 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5138 compute_shader->info.cs.block_size[1] *
5139 compute_shader->info.cs.block_size[2];
5140 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5141 compute_shader->info.wave_size);
5142
5143 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5144 waves_per_threadgroup == 1)
5145 threadgroups_per_cu = 2;
5146
5147 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5148 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5149 waves_per_threadgroup,
5150 max_waves_per_sh,
5151 threadgroups_per_cu));
5152
5153 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5154 radeon_emit(&pipeline->cs,
5155 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5156 radeon_emit(&pipeline->cs,
5157 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5158 radeon_emit(&pipeline->cs,
5159 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5160
5161 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5162 }
5163
5164 static struct radv_pipeline_key
5165 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5166 const VkComputePipelineCreateInfo *pCreateInfo)
5167 {
5168 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5169 struct radv_pipeline_key key;
5170 memset(&key, 0, sizeof(key));
5171
5172 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5173 key.optimisations_disabled = 1;
5174
5175 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5176 vk_find_struct_const(stage->pNext,
5177 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5178
5179 if (subgroup_size) {
5180 assert(subgroup_size->requiredSubgroupSize == 32 ||
5181 subgroup_size->requiredSubgroupSize == 64);
5182 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5183 }
5184
5185 return key;
5186 }
5187
5188 static VkResult radv_compute_pipeline_create(
5189 VkDevice _device,
5190 VkPipelineCache _cache,
5191 const VkComputePipelineCreateInfo* pCreateInfo,
5192 const VkAllocationCallbacks* pAllocator,
5193 VkPipeline* pPipeline)
5194 {
5195 RADV_FROM_HANDLE(radv_device, device, _device);
5196 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5197 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5198 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5199 struct radv_pipeline *pipeline;
5200 VkResult result;
5201
5202 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5203 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5204 if (pipeline == NULL)
5205 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5206
5207 pipeline->device = device;
5208 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5209 assert(pipeline->layout);
5210
5211 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5212 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5213 radv_init_feedback(creation_feedback);
5214
5215 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5216 if (creation_feedback)
5217 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5218
5219 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5220
5221 struct radv_pipeline_key key =
5222 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5223
5224 if (radv_device_use_secure_compile(device->instance)) {
5225 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5226 *pPipeline = radv_pipeline_to_handle(pipeline);
5227
5228 return result;
5229 } else {
5230 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5231 }
5232
5233 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5234 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5235 result = radv_pipeline_scratch_init(device, pipeline);
5236 if (result != VK_SUCCESS) {
5237 radv_pipeline_destroy(device, pipeline, pAllocator);
5238 return result;
5239 }
5240
5241 radv_compute_generate_pm4(pipeline);
5242
5243 *pPipeline = radv_pipeline_to_handle(pipeline);
5244
5245 return VK_SUCCESS;
5246 }
5247
5248 VkResult radv_CreateComputePipelines(
5249 VkDevice _device,
5250 VkPipelineCache pipelineCache,
5251 uint32_t count,
5252 const VkComputePipelineCreateInfo* pCreateInfos,
5253 const VkAllocationCallbacks* pAllocator,
5254 VkPipeline* pPipelines)
5255 {
5256 VkResult result = VK_SUCCESS;
5257
5258 unsigned i = 0;
5259 for (; i < count; i++) {
5260 VkResult r;
5261 r = radv_compute_pipeline_create(_device, pipelineCache,
5262 &pCreateInfos[i],
5263 pAllocator, &pPipelines[i]);
5264 if (r != VK_SUCCESS) {
5265 result = r;
5266 pPipelines[i] = VK_NULL_HANDLE;
5267 }
5268 }
5269
5270 return result;
5271 }
5272
5273
5274 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5275 {
5276 uint32_t ret = 0;
5277 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5278 if (!pipeline->shaders[i])
5279 continue;
5280
5281 if (i == MESA_SHADER_GEOMETRY &&
5282 !radv_pipeline_has_ngg(pipeline)) {
5283 ret += 2u;
5284 } else {
5285 ret += 1u;
5286 }
5287
5288 }
5289 return ret;
5290 }
5291
5292 static struct radv_shader_variant *
5293 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5294 {
5295 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5296 if (!pipeline->shaders[i])
5297 continue;
5298 if (!index) {
5299 *stage = i;
5300 return pipeline->shaders[i];
5301 }
5302
5303 --index;
5304
5305 if (i == MESA_SHADER_GEOMETRY &&
5306 !radv_pipeline_has_ngg(pipeline)) {
5307 if (!index) {
5308 *stage = i;
5309 return pipeline->gs_copy_shader;
5310 }
5311 --index;
5312 }
5313 }
5314
5315 *stage = -1;
5316 return NULL;
5317 }
5318
5319 /* Basically strlcpy (which does not exist on linux) specialized for
5320 * descriptions. */
5321 static void desc_copy(char *desc, const char *src) {
5322 int len = strlen(src);
5323 assert(len < VK_MAX_DESCRIPTION_SIZE);
5324 memcpy(desc, src, len);
5325 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5326 }
5327
5328 VkResult radv_GetPipelineExecutablePropertiesKHR(
5329 VkDevice _device,
5330 const VkPipelineInfoKHR* pPipelineInfo,
5331 uint32_t* pExecutableCount,
5332 VkPipelineExecutablePropertiesKHR* pProperties)
5333 {
5334 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5335 const uint32_t total_count = radv_get_executable_count(pipeline);
5336
5337 if (!pProperties) {
5338 *pExecutableCount = total_count;
5339 return VK_SUCCESS;
5340 }
5341
5342 const uint32_t count = MIN2(total_count, *pExecutableCount);
5343 for (unsigned i = 0, executable_idx = 0;
5344 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5345 if (!pipeline->shaders[i])
5346 continue;
5347 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5348 const char *name = NULL;
5349 const char *description = NULL;
5350 switch(i) {
5351 case MESA_SHADER_VERTEX:
5352 name = "Vertex Shader";
5353 description = "Vulkan Vertex Shader";
5354 break;
5355 case MESA_SHADER_TESS_CTRL:
5356 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5357 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5358 name = "Vertex + Tessellation Control Shaders";
5359 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5360 } else {
5361 name = "Tessellation Control Shader";
5362 description = "Vulkan Tessellation Control Shader";
5363 }
5364 break;
5365 case MESA_SHADER_TESS_EVAL:
5366 name = "Tessellation Evaluation Shader";
5367 description = "Vulkan Tessellation Evaluation Shader";
5368 break;
5369 case MESA_SHADER_GEOMETRY:
5370 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5371 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5372 name = "Tessellation Evaluation + Geometry Shaders";
5373 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5374 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5375 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5376 name = "Vertex + Geometry Shader";
5377 description = "Combined Vulkan Vertex and Geometry Shaders";
5378 } else {
5379 name = "Geometry Shader";
5380 description = "Vulkan Geometry Shader";
5381 }
5382 break;
5383 case MESA_SHADER_FRAGMENT:
5384 name = "Fragment Shader";
5385 description = "Vulkan Fragment Shader";
5386 break;
5387 case MESA_SHADER_COMPUTE:
5388 name = "Compute Shader";
5389 description = "Vulkan Compute Shader";
5390 break;
5391 }
5392
5393 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5394 desc_copy(pProperties[executable_idx].name, name);
5395 desc_copy(pProperties[executable_idx].description, description);
5396
5397 ++executable_idx;
5398 if (i == MESA_SHADER_GEOMETRY &&
5399 !radv_pipeline_has_ngg(pipeline)) {
5400 assert(pipeline->gs_copy_shader);
5401 if (executable_idx >= count)
5402 break;
5403
5404 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5405 pProperties[executable_idx].subgroupSize = 64;
5406 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5407 desc_copy(pProperties[executable_idx].description,
5408 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5409
5410 ++executable_idx;
5411 }
5412 }
5413
5414 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5415 *pExecutableCount = count;
5416 return result;
5417 }
5418
5419 VkResult radv_GetPipelineExecutableStatisticsKHR(
5420 VkDevice _device,
5421 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5422 uint32_t* pStatisticCount,
5423 VkPipelineExecutableStatisticKHR* pStatistics)
5424 {
5425 RADV_FROM_HANDLE(radv_device, device, _device);
5426 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5427 gl_shader_stage stage;
5428 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5429
5430 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5431 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5432 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5433
5434 VkPipelineExecutableStatisticKHR *s = pStatistics;
5435 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5436 VkResult result = VK_SUCCESS;
5437
5438 if (s < end) {
5439 desc_copy(s->name, "SGPRs");
5440 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5441 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5442 s->value.u64 = shader->config.num_sgprs;
5443 }
5444 ++s;
5445
5446 if (s < end) {
5447 desc_copy(s->name, "VGPRs");
5448 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5449 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5450 s->value.u64 = shader->config.num_vgprs;
5451 }
5452 ++s;
5453
5454 if (s < end) {
5455 desc_copy(s->name, "Spilled SGPRs");
5456 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5457 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5458 s->value.u64 = shader->config.spilled_sgprs;
5459 }
5460 ++s;
5461
5462 if (s < end) {
5463 desc_copy(s->name, "Spilled VGPRs");
5464 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5465 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5466 s->value.u64 = shader->config.spilled_vgprs;
5467 }
5468 ++s;
5469
5470 if (s < end) {
5471 desc_copy(s->name, "PrivMem VGPRs");
5472 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5473 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5474 s->value.u64 = shader->info.private_mem_vgprs;
5475 }
5476 ++s;
5477
5478 if (s < end) {
5479 desc_copy(s->name, "Code size");
5480 desc_copy(s->description, "Code size in bytes");
5481 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5482 s->value.u64 = shader->exec_size;
5483 }
5484 ++s;
5485
5486 if (s < end) {
5487 desc_copy(s->name, "LDS size");
5488 desc_copy(s->description, "LDS size in bytes per workgroup");
5489 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5490 s->value.u64 = shader->config.lds_size * lds_increment;
5491 }
5492 ++s;
5493
5494 if (s < end) {
5495 desc_copy(s->name, "Scratch size");
5496 desc_copy(s->description, "Private memory in bytes per subgroup");
5497 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5498 s->value.u64 = shader->config.scratch_bytes_per_wave;
5499 }
5500 ++s;
5501
5502 if (s < end) {
5503 desc_copy(s->name, "Subgroups per SIMD");
5504 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5505 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5506 s->value.u64 = max_waves;
5507 }
5508 ++s;
5509
5510 if (!pStatistics)
5511 *pStatisticCount = s - pStatistics;
5512 else if (s > end) {
5513 *pStatisticCount = end - pStatistics;
5514 result = VK_INCOMPLETE;
5515 } else {
5516 *pStatisticCount = s - pStatistics;
5517 }
5518
5519 return result;
5520 }
5521
5522 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5523 {
5524 size_t total_size = strlen(src) + 1;
5525
5526 if (!data) {
5527 *data_size = total_size;
5528 return VK_SUCCESS;
5529 }
5530
5531 size_t size = MIN2(total_size, *data_size);
5532
5533 memcpy(data, src, size);
5534 if (size)
5535 *((char*)data + size - 1) = 0;
5536 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5537 }
5538
5539 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5540 VkDevice device,
5541 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5542 uint32_t* pInternalRepresentationCount,
5543 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5544 {
5545 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5546 gl_shader_stage stage;
5547 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5548
5549 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5550 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5551 VkResult result = VK_SUCCESS;
5552 /* optimized NIR */
5553 if (p < end) {
5554 p->isText = true;
5555 desc_copy(p->name, "NIR Shader(s)");
5556 desc_copy(p->description, "The optimized NIR shader(s)");
5557 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5558 result = VK_INCOMPLETE;
5559 }
5560 ++p;
5561
5562 /* backend IR */
5563 if (p < end) {
5564 p->isText = true;
5565 if (shader->aco_used) {
5566 desc_copy(p->name, "ACO IR");
5567 desc_copy(p->description, "The ACO IR after some optimizations");
5568 } else {
5569 desc_copy(p->name, "LLVM IR");
5570 desc_copy(p->description, "The LLVM IR after some optimizations");
5571 }
5572 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5573 result = VK_INCOMPLETE;
5574 }
5575 ++p;
5576
5577 /* Disassembler */
5578 if (p < end) {
5579 p->isText = true;
5580 desc_copy(p->name, "Assembly");
5581 desc_copy(p->description, "Final Assembly");
5582 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5583 result = VK_INCOMPLETE;
5584 }
5585 ++p;
5586
5587 if (!pInternalRepresentations)
5588 *pInternalRepresentationCount = p - pInternalRepresentations;
5589 else if(p > end) {
5590 result = VK_INCOMPLETE;
5591 *pInternalRepresentationCount = end - pInternalRepresentations;
5592 } else {
5593 *pInternalRepresentationCount = p - pInternalRepresentations;
5594 }
5595
5596 return result;
5597 }