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radv: drop tcs_out_offsets
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t cb_color_control;
54 uint32_t cb_target_mask;
55 uint32_t sx_mrt_blend_opt[8];
56 uint32_t cb_blend_control[8];
57
58 uint32_t spi_shader_col_format;
59 uint32_t cb_shader_mask;
60 uint32_t db_alpha_to_mask;
61 };
62
63 struct radv_tessellation_state {
64 uint32_t ls_hs_config;
65 uint32_t offchip_layout;
66 unsigned num_patches;
67 unsigned lds_size;
68 uint32_t tf_param;
69 };
70
71 struct radv_gs_state {
72 uint32_t vgt_gs_onchip_cntl;
73 uint32_t vgt_gs_max_prims_per_subgroup;
74 uint32_t vgt_esgs_ring_itemsize;
75 uint32_t lds_size;
76 };
77
78 static void
79 radv_pipeline_destroy(struct radv_device *device,
80 struct radv_pipeline *pipeline,
81 const VkAllocationCallbacks* allocator)
82 {
83 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
84 if (pipeline->shaders[i])
85 radv_shader_variant_destroy(device, pipeline->shaders[i]);
86
87 if (pipeline->gs_copy_shader)
88 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
89
90 if(pipeline->cs.buf)
91 free(pipeline->cs.buf);
92 vk_free2(&device->alloc, allocator, pipeline);
93 }
94
95 void radv_DestroyPipeline(
96 VkDevice _device,
97 VkPipeline _pipeline,
98 const VkAllocationCallbacks* pAllocator)
99 {
100 RADV_FROM_HANDLE(radv_device, device, _device);
101 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
102
103 if (!_pipeline)
104 return;
105
106 radv_pipeline_destroy(device, pipeline, pAllocator);
107 }
108
109 static uint32_t get_hash_flags(struct radv_device *device)
110 {
111 uint32_t hash_flags = 0;
112
113 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
114 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
115 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
116 hash_flags |= RADV_HASH_SHADER_SISCHED;
117 return hash_flags;
118 }
119
120 static VkResult
121 radv_pipeline_scratch_init(struct radv_device *device,
122 struct radv_pipeline *pipeline)
123 {
124 unsigned scratch_bytes_per_wave = 0;
125 unsigned max_waves = 0;
126 unsigned min_waves = 1;
127
128 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
129 if (pipeline->shaders[i]) {
130 unsigned max_stage_waves = device->scratch_waves;
131
132 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
133 pipeline->shaders[i]->config.scratch_bytes_per_wave);
134
135 max_stage_waves = MIN2(max_stage_waves,
136 4 * device->physical_device->rad_info.num_good_compute_units *
137 (256 / pipeline->shaders[i]->config.num_vgprs));
138 max_waves = MAX2(max_waves, max_stage_waves);
139 }
140 }
141
142 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
143 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
144 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
145 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
146 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
147 }
148
149 if (scratch_bytes_per_wave)
150 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
151
152 if (scratch_bytes_per_wave && max_waves < min_waves) {
153 /* Not really true at this moment, but will be true on first
154 * execution. Avoid having hanging shaders. */
155 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
156 }
157 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
158 pipeline->max_waves = max_waves;
159 return VK_SUCCESS;
160 }
161
162 static uint32_t si_translate_blend_function(VkBlendOp op)
163 {
164 switch (op) {
165 case VK_BLEND_OP_ADD:
166 return V_028780_COMB_DST_PLUS_SRC;
167 case VK_BLEND_OP_SUBTRACT:
168 return V_028780_COMB_SRC_MINUS_DST;
169 case VK_BLEND_OP_REVERSE_SUBTRACT:
170 return V_028780_COMB_DST_MINUS_SRC;
171 case VK_BLEND_OP_MIN:
172 return V_028780_COMB_MIN_DST_SRC;
173 case VK_BLEND_OP_MAX:
174 return V_028780_COMB_MAX_DST_SRC;
175 default:
176 return 0;
177 }
178 }
179
180 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
181 {
182 switch (factor) {
183 case VK_BLEND_FACTOR_ZERO:
184 return V_028780_BLEND_ZERO;
185 case VK_BLEND_FACTOR_ONE:
186 return V_028780_BLEND_ONE;
187 case VK_BLEND_FACTOR_SRC_COLOR:
188 return V_028780_BLEND_SRC_COLOR;
189 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
190 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
191 case VK_BLEND_FACTOR_DST_COLOR:
192 return V_028780_BLEND_DST_COLOR;
193 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
194 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
195 case VK_BLEND_FACTOR_SRC_ALPHA:
196 return V_028780_BLEND_SRC_ALPHA;
197 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
198 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
199 case VK_BLEND_FACTOR_DST_ALPHA:
200 return V_028780_BLEND_DST_ALPHA;
201 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
202 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
203 case VK_BLEND_FACTOR_CONSTANT_COLOR:
204 return V_028780_BLEND_CONSTANT_COLOR;
205 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
206 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
207 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
208 return V_028780_BLEND_CONSTANT_ALPHA;
209 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
210 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
211 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
212 return V_028780_BLEND_SRC_ALPHA_SATURATE;
213 case VK_BLEND_FACTOR_SRC1_COLOR:
214 return V_028780_BLEND_SRC1_COLOR;
215 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
216 return V_028780_BLEND_INV_SRC1_COLOR;
217 case VK_BLEND_FACTOR_SRC1_ALPHA:
218 return V_028780_BLEND_SRC1_ALPHA;
219 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
220 return V_028780_BLEND_INV_SRC1_ALPHA;
221 default:
222 return 0;
223 }
224 }
225
226 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
227 {
228 switch (op) {
229 case VK_BLEND_OP_ADD:
230 return V_028760_OPT_COMB_ADD;
231 case VK_BLEND_OP_SUBTRACT:
232 return V_028760_OPT_COMB_SUBTRACT;
233 case VK_BLEND_OP_REVERSE_SUBTRACT:
234 return V_028760_OPT_COMB_REVSUBTRACT;
235 case VK_BLEND_OP_MIN:
236 return V_028760_OPT_COMB_MIN;
237 case VK_BLEND_OP_MAX:
238 return V_028760_OPT_COMB_MAX;
239 default:
240 return V_028760_OPT_COMB_BLEND_DISABLED;
241 }
242 }
243
244 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
245 {
246 switch (factor) {
247 case VK_BLEND_FACTOR_ZERO:
248 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
249 case VK_BLEND_FACTOR_ONE:
250 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
251 case VK_BLEND_FACTOR_SRC_COLOR:
252 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
253 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
254 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
255 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
256 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
257 case VK_BLEND_FACTOR_SRC_ALPHA:
258 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
259 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
260 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
261 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
262 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
263 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
264 default:
265 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
266 }
267 }
268
269 /**
270 * Get rid of DST in the blend factors by commuting the operands:
271 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
272 */
273 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
274 unsigned *dst_factor, unsigned expected_dst,
275 unsigned replacement_src)
276 {
277 if (*src_factor == expected_dst &&
278 *dst_factor == VK_BLEND_FACTOR_ZERO) {
279 *src_factor = VK_BLEND_FACTOR_ZERO;
280 *dst_factor = replacement_src;
281
282 /* Commuting the operands requires reversing subtractions. */
283 if (*func == VK_BLEND_OP_SUBTRACT)
284 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
285 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
286 *func = VK_BLEND_OP_SUBTRACT;
287 }
288 }
289
290 static bool si_blend_factor_uses_dst(unsigned factor)
291 {
292 return factor == VK_BLEND_FACTOR_DST_COLOR ||
293 factor == VK_BLEND_FACTOR_DST_ALPHA ||
294 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
295 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
296 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
297 }
298
299 static bool is_dual_src(VkBlendFactor factor)
300 {
301 switch (factor) {
302 case VK_BLEND_FACTOR_SRC1_COLOR:
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
304 case VK_BLEND_FACTOR_SRC1_ALPHA:
305 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
306 return true;
307 default:
308 return false;
309 }
310 }
311
312 static unsigned si_choose_spi_color_format(VkFormat vk_format,
313 bool blend_enable,
314 bool blend_need_alpha)
315 {
316 const struct vk_format_description *desc = vk_format_description(vk_format);
317 unsigned format, ntype, swap;
318
319 /* Alpha is needed for alpha-to-coverage.
320 * Blending may be with or without alpha.
321 */
322 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
323 unsigned alpha = 0; /* exports alpha, but may not support blending */
324 unsigned blend = 0; /* supports blending, but may not export alpha */
325 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
326
327 format = radv_translate_colorformat(vk_format);
328 ntype = radv_translate_color_numformat(vk_format, desc,
329 vk_format_get_first_non_void_channel(vk_format));
330 swap = radv_translate_colorswap(vk_format, false);
331
332 /* Choose the SPI color formats. These are required values for Stoney/RB+.
333 * Other chips have multiple choices, though they are not necessarily better.
334 */
335 switch (format) {
336 case V_028C70_COLOR_5_6_5:
337 case V_028C70_COLOR_1_5_5_5:
338 case V_028C70_COLOR_5_5_5_1:
339 case V_028C70_COLOR_4_4_4_4:
340 case V_028C70_COLOR_10_11_11:
341 case V_028C70_COLOR_11_11_10:
342 case V_028C70_COLOR_8:
343 case V_028C70_COLOR_8_8:
344 case V_028C70_COLOR_8_8_8_8:
345 case V_028C70_COLOR_10_10_10_2:
346 case V_028C70_COLOR_2_10_10_10:
347 if (ntype == V_028C70_NUMBER_UINT)
348 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
349 else if (ntype == V_028C70_NUMBER_SINT)
350 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
351 else
352 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
353 break;
354
355 case V_028C70_COLOR_16:
356 case V_028C70_COLOR_16_16:
357 case V_028C70_COLOR_16_16_16_16:
358 if (ntype == V_028C70_NUMBER_UNORM ||
359 ntype == V_028C70_NUMBER_SNORM) {
360 /* UNORM16 and SNORM16 don't support blending */
361 if (ntype == V_028C70_NUMBER_UNORM)
362 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
363 else
364 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
365
366 /* Use 32 bits per channel for blending. */
367 if (format == V_028C70_COLOR_16) {
368 if (swap == V_028C70_SWAP_STD) { /* R */
369 blend = V_028714_SPI_SHADER_32_R;
370 blend_alpha = V_028714_SPI_SHADER_32_AR;
371 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
372 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
373 else
374 assert(0);
375 } else if (format == V_028C70_COLOR_16_16) {
376 if (swap == V_028C70_SWAP_STD) { /* RG */
377 blend = V_028714_SPI_SHADER_32_GR;
378 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
379 } else if (swap == V_028C70_SWAP_ALT) /* RA */
380 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
381 else
382 assert(0);
383 } else /* 16_16_16_16 */
384 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
385 } else if (ntype == V_028C70_NUMBER_UINT)
386 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
387 else if (ntype == V_028C70_NUMBER_SINT)
388 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
389 else if (ntype == V_028C70_NUMBER_FLOAT)
390 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
391 else
392 assert(0);
393 break;
394
395 case V_028C70_COLOR_32:
396 if (swap == V_028C70_SWAP_STD) { /* R */
397 blend = normal = V_028714_SPI_SHADER_32_R;
398 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
399 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
400 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
401 else
402 assert(0);
403 break;
404
405 case V_028C70_COLOR_32_32:
406 if (swap == V_028C70_SWAP_STD) { /* RG */
407 blend = normal = V_028714_SPI_SHADER_32_GR;
408 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
409 } else if (swap == V_028C70_SWAP_ALT) /* RA */
410 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
411 else
412 assert(0);
413 break;
414
415 case V_028C70_COLOR_32_32_32_32:
416 case V_028C70_COLOR_8_24:
417 case V_028C70_COLOR_24_8:
418 case V_028C70_COLOR_X24_8_32_FLOAT:
419 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
420 break;
421
422 default:
423 unreachable("unhandled blend format");
424 }
425
426 if (blend_enable && blend_need_alpha)
427 return blend_alpha;
428 else if(blend_need_alpha)
429 return alpha;
430 else if(blend_enable)
431 return blend;
432 else
433 return normal;
434 }
435
436 static void
437 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
438 const VkGraphicsPipelineCreateInfo *pCreateInfo,
439 uint32_t blend_enable,
440 uint32_t blend_need_alpha,
441 bool single_cb_enable,
442 bool blend_mrt0_is_dual_src,
443 struct radv_blend_state *blend)
444 {
445 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
446 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
447 unsigned col_format = 0;
448
449 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
450 unsigned cf;
451
452 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
453 cf = V_028714_SPI_SHADER_ZERO;
454 } else {
455 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
456
457 cf = si_choose_spi_color_format(attachment->format,
458 blend_enable & (1 << i),
459 blend_need_alpha & (1 << i));
460 }
461
462 col_format |= cf << (4 * i);
463 }
464
465 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
466
467 if (blend_mrt0_is_dual_src)
468 col_format |= (col_format & 0xf) << 4;
469 blend->spi_shader_col_format = col_format;
470 }
471
472 static bool
473 format_is_int8(VkFormat format)
474 {
475 const struct vk_format_description *desc = vk_format_description(format);
476 int channel = vk_format_get_first_non_void_channel(format);
477
478 return channel >= 0 && desc->channel[channel].pure_integer &&
479 desc->channel[channel].size == 8;
480 }
481
482 static bool
483 format_is_int10(VkFormat format)
484 {
485 const struct vk_format_description *desc = vk_format_description(format);
486
487 if (desc->nr_channels != 4)
488 return false;
489 for (unsigned i = 0; i < 4; i++) {
490 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
491 return true;
492 }
493 return false;
494 }
495
496 unsigned radv_format_meta_fs_key(VkFormat format)
497 {
498 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
499 bool is_int8 = format_is_int8(format);
500 bool is_int10 = format_is_int10(format);
501
502 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
503 }
504
505 static void
506 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
507 unsigned *is_int8, unsigned *is_int10)
508 {
509 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
510 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
511 *is_int8 = 0;
512 *is_int10 = 0;
513
514 for (unsigned i = 0; i < subpass->color_count; ++i) {
515 struct radv_render_pass_attachment *attachment;
516
517 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
518 continue;
519
520 attachment = pass->attachments + subpass->color_attachments[i].attachment;
521
522 if (format_is_int8(attachment->format))
523 *is_int8 |= 1 << i;
524 if (format_is_int10(attachment->format))
525 *is_int10 |= 1 << i;
526 }
527 }
528
529 static struct radv_blend_state
530 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
531 const VkGraphicsPipelineCreateInfo *pCreateInfo,
532 const struct radv_graphics_pipeline_create_info *extra)
533 {
534 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
535 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
536 struct radv_blend_state blend = {0};
537 unsigned mode = V_028808_CB_NORMAL;
538 uint32_t blend_enable = 0, blend_need_alpha = 0;
539 bool blend_mrt0_is_dual_src = false;
540 int i;
541 bool single_cb_enable = false;
542
543 if (!vkblend)
544 return blend;
545
546 if (extra && extra->custom_blend_mode) {
547 single_cb_enable = true;
548 mode = extra->custom_blend_mode;
549 }
550 blend.cb_color_control = 0;
551 if (vkblend->logicOpEnable)
552 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
553 else
554 blend.cb_color_control |= S_028808_ROP3(0xcc);
555
556 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
557 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
558 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
559 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
560
561 if (vkms && vkms->alphaToCoverageEnable) {
562 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
563 }
564
565 blend.cb_target_mask = 0;
566 for (i = 0; i < vkblend->attachmentCount; i++) {
567 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
568 unsigned blend_cntl = 0;
569 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
570 VkBlendOp eqRGB = att->colorBlendOp;
571 VkBlendFactor srcRGB = att->srcColorBlendFactor;
572 VkBlendFactor dstRGB = att->dstColorBlendFactor;
573 VkBlendOp eqA = att->alphaBlendOp;
574 VkBlendFactor srcA = att->srcAlphaBlendFactor;
575 VkBlendFactor dstA = att->dstAlphaBlendFactor;
576
577 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
578
579 if (!att->colorWriteMask)
580 continue;
581
582 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
583 if (!att->blendEnable) {
584 blend.cb_blend_control[i] = blend_cntl;
585 continue;
586 }
587
588 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
589 if (i == 0)
590 blend_mrt0_is_dual_src = true;
591
592 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
593 srcRGB = VK_BLEND_FACTOR_ONE;
594 dstRGB = VK_BLEND_FACTOR_ONE;
595 }
596 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
597 srcA = VK_BLEND_FACTOR_ONE;
598 dstA = VK_BLEND_FACTOR_ONE;
599 }
600
601 /* Blending optimizations for RB+.
602 * These transformations don't change the behavior.
603 *
604 * First, get rid of DST in the blend factors:
605 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
606 */
607 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
608 VK_BLEND_FACTOR_DST_COLOR,
609 VK_BLEND_FACTOR_SRC_COLOR);
610
611 si_blend_remove_dst(&eqA, &srcA, &dstA,
612 VK_BLEND_FACTOR_DST_COLOR,
613 VK_BLEND_FACTOR_SRC_COLOR);
614
615 si_blend_remove_dst(&eqA, &srcA, &dstA,
616 VK_BLEND_FACTOR_DST_ALPHA,
617 VK_BLEND_FACTOR_SRC_ALPHA);
618
619 /* Look up the ideal settings from tables. */
620 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
621 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
622 srcA_opt = si_translate_blend_opt_factor(srcA, true);
623 dstA_opt = si_translate_blend_opt_factor(dstA, true);
624
625 /* Handle interdependencies. */
626 if (si_blend_factor_uses_dst(srcRGB))
627 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
628 if (si_blend_factor_uses_dst(srcA))
629 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
630
631 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
632 (dstRGB == VK_BLEND_FACTOR_ZERO ||
633 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
634 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
635 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
636
637 /* Set the final value. */
638 blend.sx_mrt_blend_opt[i] =
639 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
640 S_028760_COLOR_DST_OPT(dstRGB_opt) |
641 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
642 S_028760_ALPHA_SRC_OPT(srcA_opt) |
643 S_028760_ALPHA_DST_OPT(dstA_opt) |
644 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
645 blend_cntl |= S_028780_ENABLE(1);
646
647 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
648 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
649 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
650 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
651 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
652 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
653 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
654 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
655 }
656 blend.cb_blend_control[i] = blend_cntl;
657
658 blend_enable |= 1 << i;
659
660 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
661 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
662 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
663 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
664 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
665 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
666 blend_need_alpha |= 1 << i;
667 }
668 for (i = vkblend->attachmentCount; i < 8; i++) {
669 blend.cb_blend_control[i] = 0;
670 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
671 }
672
673 /* disable RB+ for now */
674 if (pipeline->device->physical_device->has_rbplus)
675 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
676
677 if (blend.cb_target_mask)
678 blend.cb_color_control |= S_028808_MODE(mode);
679 else
680 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
681
682 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
683 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src,
684 &blend);
685 return blend;
686 }
687
688 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
689 {
690 switch (op) {
691 case VK_STENCIL_OP_KEEP:
692 return V_02842C_STENCIL_KEEP;
693 case VK_STENCIL_OP_ZERO:
694 return V_02842C_STENCIL_ZERO;
695 case VK_STENCIL_OP_REPLACE:
696 return V_02842C_STENCIL_REPLACE_TEST;
697 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
698 return V_02842C_STENCIL_ADD_CLAMP;
699 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
700 return V_02842C_STENCIL_SUB_CLAMP;
701 case VK_STENCIL_OP_INVERT:
702 return V_02842C_STENCIL_INVERT;
703 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
704 return V_02842C_STENCIL_ADD_WRAP;
705 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
706 return V_02842C_STENCIL_SUB_WRAP;
707 default:
708 return 0;
709 }
710 }
711
712 static uint32_t si_translate_fill(VkPolygonMode func)
713 {
714 switch(func) {
715 case VK_POLYGON_MODE_FILL:
716 return V_028814_X_DRAW_TRIANGLES;
717 case VK_POLYGON_MODE_LINE:
718 return V_028814_X_DRAW_LINES;
719 case VK_POLYGON_MODE_POINT:
720 return V_028814_X_DRAW_POINTS;
721 default:
722 assert(0);
723 return V_028814_X_DRAW_POINTS;
724 }
725 }
726
727 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
728 {
729 uint32_t num_samples = vkms->rasterizationSamples;
730 uint32_t ps_iter_samples = 1;
731
732 if (vkms->sampleShadingEnable) {
733 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
734 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
735 }
736 return ps_iter_samples;
737 }
738
739 static void
740 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
741 const VkGraphicsPipelineCreateInfo *pCreateInfo)
742 {
743 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
744 struct radv_multisample_state *ms = &pipeline->graphics.ms;
745 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
746 int ps_iter_samples = 1;
747 uint32_t mask = 0xffff;
748
749 if (vkms)
750 ms->num_samples = vkms->rasterizationSamples;
751 else
752 ms->num_samples = 1;
753
754 if (vkms)
755 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
756 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
757 ps_iter_samples = ms->num_samples;
758 }
759
760 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
761 ms->pa_sc_aa_config = 0;
762 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
763 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
764 ms->pa_sc_mode_cntl_1 =
765 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
766 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
767 /* always 1: */
768 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
769 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
770 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
771 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
772 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
773 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
774 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
775 S_028A48_VPORT_SCISSOR_ENABLE(1);
776
777 if (ms->num_samples > 1) {
778 unsigned log_samples = util_logbase2(ms->num_samples);
779 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
780 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
781 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
782 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
783 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
784 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
785 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
786 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
787 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
788 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
789 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
790 if (ps_iter_samples > 1)
791 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
792 }
793
794 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
795 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
796 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
797 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
798 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
799 }
800
801 if (vkms && vkms->pSampleMask) {
802 mask = vkms->pSampleMask[0] & 0xffff;
803 }
804
805 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
806 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
807 }
808
809 static bool
810 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
811 {
812 switch (topology) {
813 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
814 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
815 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
816 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
817 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
818 return false;
819 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
820 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
821 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
822 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
823 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
824 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
825 return true;
826 default:
827 unreachable("unhandled primitive type");
828 }
829 }
830
831 static uint32_t
832 si_translate_prim(enum VkPrimitiveTopology topology)
833 {
834 switch (topology) {
835 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
836 return V_008958_DI_PT_POINTLIST;
837 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
838 return V_008958_DI_PT_LINELIST;
839 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
840 return V_008958_DI_PT_LINESTRIP;
841 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
842 return V_008958_DI_PT_TRILIST;
843 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
844 return V_008958_DI_PT_TRISTRIP;
845 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
846 return V_008958_DI_PT_TRIFAN;
847 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
848 return V_008958_DI_PT_LINELIST_ADJ;
849 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
850 return V_008958_DI_PT_LINESTRIP_ADJ;
851 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
852 return V_008958_DI_PT_TRILIST_ADJ;
853 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
854 return V_008958_DI_PT_TRISTRIP_ADJ;
855 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
856 return V_008958_DI_PT_PATCH;
857 default:
858 assert(0);
859 return 0;
860 }
861 }
862
863 static uint32_t
864 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
865 {
866 switch (gl_prim) {
867 case 0: /* GL_POINTS */
868 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
869 case 1: /* GL_LINES */
870 case 3: /* GL_LINE_STRIP */
871 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
872 case 0x8E7A: /* GL_ISOLINES */
873 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
874
875 case 4: /* GL_TRIANGLES */
876 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
877 case 5: /* GL_TRIANGLE_STRIP */
878 case 7: /* GL_QUADS */
879 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
880 default:
881 assert(0);
882 return 0;
883 }
884 }
885
886 static uint32_t
887 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
888 {
889 switch (topology) {
890 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
891 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
892 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
893 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
894 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
895 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
896 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
897 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
898 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
899 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
900 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
901 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
902 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
903 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
904 default:
905 assert(0);
906 return 0;
907 }
908 }
909
910 static unsigned si_map_swizzle(unsigned swizzle)
911 {
912 switch (swizzle) {
913 case VK_SWIZZLE_Y:
914 return V_008F0C_SQ_SEL_Y;
915 case VK_SWIZZLE_Z:
916 return V_008F0C_SQ_SEL_Z;
917 case VK_SWIZZLE_W:
918 return V_008F0C_SQ_SEL_W;
919 case VK_SWIZZLE_0:
920 return V_008F0C_SQ_SEL_0;
921 case VK_SWIZZLE_1:
922 return V_008F0C_SQ_SEL_1;
923 default: /* VK_SWIZZLE_X */
924 return V_008F0C_SQ_SEL_X;
925 }
926 }
927
928
929 static unsigned radv_dynamic_state_mask(VkDynamicState state)
930 {
931 switch(state) {
932 case VK_DYNAMIC_STATE_VIEWPORT:
933 return RADV_DYNAMIC_VIEWPORT;
934 case VK_DYNAMIC_STATE_SCISSOR:
935 return RADV_DYNAMIC_SCISSOR;
936 case VK_DYNAMIC_STATE_LINE_WIDTH:
937 return RADV_DYNAMIC_LINE_WIDTH;
938 case VK_DYNAMIC_STATE_DEPTH_BIAS:
939 return RADV_DYNAMIC_DEPTH_BIAS;
940 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
941 return RADV_DYNAMIC_BLEND_CONSTANTS;
942 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
943 return RADV_DYNAMIC_DEPTH_BOUNDS;
944 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
945 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
946 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
947 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
948 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
949 return RADV_DYNAMIC_STENCIL_REFERENCE;
950 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
951 return RADV_DYNAMIC_DISCARD_RECTANGLE;
952 default:
953 unreachable("Unhandled dynamic state");
954 }
955 }
956
957 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
958 {
959 uint32_t states = RADV_DYNAMIC_ALL;
960
961 /* If rasterization is disabled we do not care about any of the dynamic states,
962 * since they are all rasterization related only. */
963 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
964 return 0;
965
966 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
967 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
968
969 if (!pCreateInfo->pDepthStencilState ||
970 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
971 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
972
973 if (!pCreateInfo->pDepthStencilState ||
974 !pCreateInfo->pDepthStencilState->stencilTestEnable)
975 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
976 RADV_DYNAMIC_STENCIL_WRITE_MASK |
977 RADV_DYNAMIC_STENCIL_REFERENCE);
978
979 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
980 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
981
982 /* TODO: blend constants & line width. */
983
984 return states;
985 }
986
987
988 static void
989 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
990 const VkGraphicsPipelineCreateInfo *pCreateInfo)
991 {
992 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
993 uint32_t states = needed_states;
994 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
995 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
996
997 pipeline->dynamic_state = default_dynamic_state;
998 pipeline->graphics.needed_dynamic_state = needed_states;
999
1000 if (pCreateInfo->pDynamicState) {
1001 /* Remove all of the states that are marked as dynamic */
1002 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1003 for (uint32_t s = 0; s < count; s++)
1004 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1005 }
1006
1007 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1008
1009 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1010 assert(pCreateInfo->pViewportState);
1011
1012 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1013 if (states & RADV_DYNAMIC_VIEWPORT) {
1014 typed_memcpy(dynamic->viewport.viewports,
1015 pCreateInfo->pViewportState->pViewports,
1016 pCreateInfo->pViewportState->viewportCount);
1017 }
1018 }
1019
1020 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1021 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1022 if (states & RADV_DYNAMIC_SCISSOR) {
1023 typed_memcpy(dynamic->scissor.scissors,
1024 pCreateInfo->pViewportState->pScissors,
1025 pCreateInfo->pViewportState->scissorCount);
1026 }
1027 }
1028
1029 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1030 assert(pCreateInfo->pRasterizationState);
1031 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1032 }
1033
1034 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1035 assert(pCreateInfo->pRasterizationState);
1036 dynamic->depth_bias.bias =
1037 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1038 dynamic->depth_bias.clamp =
1039 pCreateInfo->pRasterizationState->depthBiasClamp;
1040 dynamic->depth_bias.slope =
1041 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1042 }
1043
1044 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1045 *
1046 * pColorBlendState is [...] NULL if the pipeline has rasterization
1047 * disabled or if the subpass of the render pass the pipeline is
1048 * created against does not use any color attachments.
1049 */
1050 bool uses_color_att = false;
1051 for (unsigned i = 0; i < subpass->color_count; ++i) {
1052 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1053 uses_color_att = true;
1054 break;
1055 }
1056 }
1057
1058 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1059 assert(pCreateInfo->pColorBlendState);
1060 typed_memcpy(dynamic->blend_constants,
1061 pCreateInfo->pColorBlendState->blendConstants, 4);
1062 }
1063
1064 /* If there is no depthstencil attachment, then don't read
1065 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1066 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1067 * no need to override the depthstencil defaults in
1068 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1069 *
1070 * Section 9.2 of the Vulkan 1.0.15 spec says:
1071 *
1072 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1073 * disabled or if the subpass of the render pass the pipeline is created
1074 * against does not use a depth/stencil attachment.
1075 */
1076 if (needed_states &&
1077 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1078 assert(pCreateInfo->pDepthStencilState);
1079
1080 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1081 dynamic->depth_bounds.min =
1082 pCreateInfo->pDepthStencilState->minDepthBounds;
1083 dynamic->depth_bounds.max =
1084 pCreateInfo->pDepthStencilState->maxDepthBounds;
1085 }
1086
1087 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1088 dynamic->stencil_compare_mask.front =
1089 pCreateInfo->pDepthStencilState->front.compareMask;
1090 dynamic->stencil_compare_mask.back =
1091 pCreateInfo->pDepthStencilState->back.compareMask;
1092 }
1093
1094 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1095 dynamic->stencil_write_mask.front =
1096 pCreateInfo->pDepthStencilState->front.writeMask;
1097 dynamic->stencil_write_mask.back =
1098 pCreateInfo->pDepthStencilState->back.writeMask;
1099 }
1100
1101 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1102 dynamic->stencil_reference.front =
1103 pCreateInfo->pDepthStencilState->front.reference;
1104 dynamic->stencil_reference.back =
1105 pCreateInfo->pDepthStencilState->back.reference;
1106 }
1107 }
1108
1109 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1110 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1111 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1112 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1113 typed_memcpy(dynamic->discard_rectangle.rectangles,
1114 discard_rectangle_info->pDiscardRectangles,
1115 discard_rectangle_info->discardRectangleCount);
1116 }
1117
1118 pipeline->dynamic_state.mask = states;
1119 }
1120
1121 static struct radv_gs_state
1122 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1123 const struct radv_pipeline *pipeline)
1124 {
1125 struct radv_gs_state gs = {0};
1126 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1127 struct radv_es_output_info *es_info;
1128 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1129 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1130 else
1131 es_info = radv_pipeline_has_tess(pipeline) ?
1132 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1133 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1134
1135 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1136 bool uses_adjacency;
1137 switch(pCreateInfo->pInputAssemblyState->topology) {
1138 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1139 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1140 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1141 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1142 uses_adjacency = true;
1143 break;
1144 default:
1145 uses_adjacency = false;
1146 break;
1147 }
1148
1149 /* All these are in dwords: */
1150 /* We can't allow using the whole LDS, because GS waves compete with
1151 * other shader stages for LDS space. */
1152 const unsigned max_lds_size = 8 * 1024;
1153 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1154 unsigned esgs_lds_size;
1155
1156 /* All these are per subgroup: */
1157 const unsigned max_out_prims = 32 * 1024;
1158 const unsigned max_es_verts = 255;
1159 const unsigned ideal_gs_prims = 64;
1160 unsigned max_gs_prims, gs_prims;
1161 unsigned min_es_verts, es_verts, worst_case_es_verts;
1162
1163 if (uses_adjacency || gs_num_invocations > 1)
1164 max_gs_prims = 127 / gs_num_invocations;
1165 else
1166 max_gs_prims = 255;
1167
1168 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1169 * Make sure we don't go over the maximum value.
1170 */
1171 if (gs_info->gs.vertices_out > 0) {
1172 max_gs_prims = MIN2(max_gs_prims,
1173 max_out_prims /
1174 (gs_info->gs.vertices_out * gs_num_invocations));
1175 }
1176 assert(max_gs_prims > 0);
1177
1178 /* If the primitive has adjacency, halve the number of vertices
1179 * that will be reused in multiple primitives.
1180 */
1181 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1182
1183 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1184 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1185
1186 /* Compute ESGS LDS size based on the worst case number of ES vertices
1187 * needed to create the target number of GS prims per subgroup.
1188 */
1189 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1190
1191 /* If total LDS usage is too big, refactor partitions based on ratio
1192 * of ESGS item sizes.
1193 */
1194 if (esgs_lds_size > max_lds_size) {
1195 /* Our target GS Prims Per Subgroup was too large. Calculate
1196 * the maximum number of GS Prims Per Subgroup that will fit
1197 * into LDS, capped by the maximum that the hardware can support.
1198 */
1199 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1200 max_gs_prims);
1201 assert(gs_prims > 0);
1202 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1203 max_es_verts);
1204
1205 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1206 assert(esgs_lds_size <= max_lds_size);
1207 }
1208
1209 /* Now calculate remaining ESGS information. */
1210 if (esgs_lds_size)
1211 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1212 else
1213 es_verts = max_es_verts;
1214
1215 /* Vertices for adjacency primitives are not always reused, so restore
1216 * it for ES_VERTS_PER_SUBGRP.
1217 */
1218 min_es_verts = gs_info->gs.vertices_in;
1219
1220 /* For normal primitives, the VGT only checks if they are past the ES
1221 * verts per subgroup after allocating a full GS primitive and if they
1222 * are, kick off a new subgroup. But if those additional ES verts are
1223 * unique (e.g. not reused) we need to make sure there is enough LDS
1224 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1225 */
1226 es_verts -= min_es_verts - 1;
1227
1228 uint32_t es_verts_per_subgroup = es_verts;
1229 uint32_t gs_prims_per_subgroup = gs_prims;
1230 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1231 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1232 gs.lds_size = align(esgs_lds_size, 128) / 128;
1233 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1234 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1235 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1236 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1237 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1238 assert(max_prims_per_subgroup <= max_out_prims);
1239
1240 return gs;
1241 }
1242
1243 static void
1244 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1245 {
1246 struct radv_device *device = pipeline->device;
1247 unsigned num_se = device->physical_device->rad_info.max_se;
1248 unsigned wave_size = 64;
1249 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1250 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1251 unsigned alignment = 256 * num_se;
1252 /* The maximum size is 63.999 MB per SE. */
1253 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1254 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1255
1256 /* Calculate the minimum size. */
1257 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1258 wave_size, alignment);
1259 /* These are recommended sizes, not minimum sizes. */
1260 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1261 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1262 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1263 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1264
1265 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1266 esgs_ring_size = align(esgs_ring_size, alignment);
1267 gsvs_ring_size = align(gsvs_ring_size, alignment);
1268
1269 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1270 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1271
1272 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1273 }
1274
1275 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1276 unsigned *lds_size)
1277 {
1278 /* SPI barrier management bug:
1279 * Make sure we have at least 4k of LDS in use to avoid the bug.
1280 * It applies to workgroup sizes of more than one wavefront.
1281 */
1282 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1283 device->physical_device->rad_info.family == CHIP_KABINI ||
1284 device->physical_device->rad_info.family == CHIP_MULLINS)
1285 *lds_size = MAX2(*lds_size, 8);
1286 }
1287
1288 struct radv_shader_variant *
1289 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1290 {
1291 if (pipeline->shaders[MESA_SHADER_VERTEX])
1292 return pipeline->shaders[MESA_SHADER_VERTEX];
1293 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1294 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1295 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1296 }
1297
1298 static struct radv_shader_variant *
1299 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1300 {
1301 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1302 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1303 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1304 }
1305
1306 static struct radv_tessellation_state
1307 calculate_tess_state(struct radv_pipeline *pipeline,
1308 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1309 {
1310 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1311 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1312 unsigned num_tcs_patch_outputs;
1313 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1314 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1315 unsigned lds_size, hardware_lds_size;
1316 unsigned num_patches;
1317 struct radv_tessellation_state tess = {0};
1318
1319 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1320 * are laid out in LDS. */
1321 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1322
1323 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1324 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1325 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1326
1327 /* Ensure that we only need one wave per SIMD so we don't need to check
1328 * resource usage. Also ensures that the number of tcs in and out
1329 * vertices per threadgroup are at most 256.
1330 */
1331 input_vertex_size = num_tcs_inputs * 16;
1332 output_vertex_size = num_tcs_outputs * 16;
1333
1334 input_patch_size = num_tcs_input_cp * input_vertex_size;
1335
1336 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1337 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1338 /* Ensure that we only need one wave per SIMD so we don't need to check
1339 * resource usage. Also ensures that the number of tcs in and out
1340 * vertices per threadgroup are at most 256.
1341 */
1342 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1343
1344 /* Make sure that the data fits in LDS. This assumes the shaders only
1345 * use LDS for the inputs and outputs.
1346 */
1347 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1348 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1349
1350 /* Make sure the output data fits in the offchip buffer */
1351 num_patches = MIN2(num_patches,
1352 (pipeline->device->tess_offchip_block_dw_size * 4) /
1353 output_patch_size);
1354
1355 /* Not necessary for correctness, but improves performance. The
1356 * specific value is taken from the proprietary driver.
1357 */
1358 num_patches = MIN2(num_patches, 40);
1359
1360 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1361 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1362 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1363 num_patches = MIN2(num_patches, one_wave);
1364 }
1365
1366 output_patch0_offset = input_patch_size * num_patches;
1367
1368 lds_size = output_patch0_offset + output_patch_size * num_patches;
1369
1370 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1371 assert(lds_size <= 65536);
1372 lds_size = align(lds_size, 512) / 512;
1373 } else {
1374 assert(lds_size <= 32768);
1375 lds_size = align(lds_size, 256) / 256;
1376 }
1377 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1378
1379 tess.lds_size = lds_size;
1380
1381 tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1382 num_patches;
1383
1384 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1385 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1386 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1387 tess.num_patches = num_patches;
1388
1389 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1390 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1391
1392 switch (tes->info.tes.primitive_mode) {
1393 case GL_TRIANGLES:
1394 type = V_028B6C_TESS_TRIANGLE;
1395 break;
1396 case GL_QUADS:
1397 type = V_028B6C_TESS_QUAD;
1398 break;
1399 case GL_ISOLINES:
1400 type = V_028B6C_TESS_ISOLINE;
1401 break;
1402 }
1403
1404 switch (tes->info.tes.spacing) {
1405 case TESS_SPACING_EQUAL:
1406 partitioning = V_028B6C_PART_INTEGER;
1407 break;
1408 case TESS_SPACING_FRACTIONAL_ODD:
1409 partitioning = V_028B6C_PART_FRAC_ODD;
1410 break;
1411 case TESS_SPACING_FRACTIONAL_EVEN:
1412 partitioning = V_028B6C_PART_FRAC_EVEN;
1413 break;
1414 default:
1415 break;
1416 }
1417
1418 bool ccw = tes->info.tes.ccw;
1419 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1420 vk_find_struct_const(pCreateInfo->pTessellationState,
1421 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1422
1423 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1424 ccw = !ccw;
1425
1426 if (tes->info.tes.point_mode)
1427 topology = V_028B6C_OUTPUT_POINT;
1428 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1429 topology = V_028B6C_OUTPUT_LINE;
1430 else if (ccw)
1431 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1432 else
1433 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1434
1435 if (pipeline->device->has_distributed_tess) {
1436 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1437 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1438 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1439 else
1440 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1441 } else
1442 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1443
1444 tess.tf_param = S_028B6C_TYPE(type) |
1445 S_028B6C_PARTITIONING(partitioning) |
1446 S_028B6C_TOPOLOGY(topology) |
1447 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1448
1449 return tess;
1450 }
1451
1452 static const struct radv_prim_vertex_count prim_size_table[] = {
1453 [V_008958_DI_PT_NONE] = {0, 0},
1454 [V_008958_DI_PT_POINTLIST] = {1, 1},
1455 [V_008958_DI_PT_LINELIST] = {2, 2},
1456 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1457 [V_008958_DI_PT_TRILIST] = {3, 3},
1458 [V_008958_DI_PT_TRIFAN] = {3, 1},
1459 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1460 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1461 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1462 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1463 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1464 [V_008958_DI_PT_RECTLIST] = {3, 3},
1465 [V_008958_DI_PT_LINELOOP] = {2, 1},
1466 [V_008958_DI_PT_POLYGON] = {3, 1},
1467 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1468 };
1469
1470 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1471 {
1472 if (radv_pipeline_has_gs(pipeline))
1473 return &pipeline->gs_copy_shader->info.vs.outinfo;
1474 else if (radv_pipeline_has_tess(pipeline))
1475 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1476 else
1477 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1478 }
1479
1480 static void
1481 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1482 {
1483 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1484 int shader_count = 0;
1485
1486 if(shaders[MESA_SHADER_FRAGMENT]) {
1487 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1488 }
1489 if(shaders[MESA_SHADER_GEOMETRY]) {
1490 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1491 }
1492 if(shaders[MESA_SHADER_TESS_EVAL]) {
1493 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1494 }
1495 if(shaders[MESA_SHADER_TESS_CTRL]) {
1496 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1497 }
1498 if(shaders[MESA_SHADER_VERTEX]) {
1499 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1500 }
1501
1502 for (int i = 1; i < shader_count; ++i) {
1503 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1504 ordered_shaders[i - 1]);
1505
1506 nir_remove_dead_variables(ordered_shaders[i],
1507 nir_var_shader_out);
1508 nir_remove_dead_variables(ordered_shaders[i - 1],
1509 nir_var_shader_in);
1510
1511 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1512 ordered_shaders[i - 1]);
1513
1514 nir_compact_varyings(ordered_shaders[i],
1515 ordered_shaders[i - 1], true);
1516
1517 if (progress) {
1518 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1519 ac_lower_indirect_derefs(ordered_shaders[i],
1520 pipeline->device->physical_device->rad_info.chip_class);
1521 }
1522 radv_optimize_nir(ordered_shaders[i]);
1523
1524 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1525 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1526 pipeline->device->physical_device->rad_info.chip_class);
1527 }
1528 radv_optimize_nir(ordered_shaders[i - 1]);
1529 }
1530 }
1531 }
1532
1533
1534 static struct radv_pipeline_key
1535 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1536 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1537 const struct radv_blend_state *blend,
1538 bool has_view_index)
1539 {
1540 const VkPipelineVertexInputStateCreateInfo *input_state =
1541 pCreateInfo->pVertexInputState;
1542 struct radv_pipeline_key key;
1543 memset(&key, 0, sizeof(key));
1544
1545 key.has_multiview_view_index = has_view_index;
1546
1547 uint32_t binding_input_rate = 0;
1548 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1549 if (input_state->pVertexBindingDescriptions[i].inputRate)
1550 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1551 }
1552
1553 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1554 unsigned binding;
1555 binding = input_state->pVertexAttributeDescriptions[i].binding;
1556 if (binding_input_rate & (1u << binding))
1557 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1558 }
1559
1560 if (pCreateInfo->pTessellationState)
1561 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1562
1563
1564 if (pCreateInfo->pMultisampleState &&
1565 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1566 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1567 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1568 key.multisample = true;
1569 key.log2_num_samples = util_logbase2(num_samples);
1570 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1571 }
1572
1573 key.col_format = blend->spi_shader_col_format;
1574 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1575 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1576
1577 return key;
1578 }
1579
1580 static void
1581 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1582 const struct radv_pipeline_key *key,
1583 nir_shader **nir)
1584 {
1585 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1586
1587 if (nir[MESA_SHADER_TESS_CTRL]) {
1588 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1589 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1590 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1591 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1592
1593 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1594 }
1595
1596 if (nir[MESA_SHADER_GEOMETRY]) {
1597 if (nir[MESA_SHADER_TESS_CTRL])
1598 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1599 else
1600 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1601 }
1602
1603 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1604 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1605
1606 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1607 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1608 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1609 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1610 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1611 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1612 }
1613
1614 static void
1615 merge_tess_info(struct shader_info *tes_info,
1616 const struct shader_info *tcs_info)
1617 {
1618 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1619 *
1620 * "PointMode. Controls generation of points rather than triangles
1621 * or lines. This functionality defaults to disabled, and is
1622 * enabled if either shader stage includes the execution mode.
1623 *
1624 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1625 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1626 * and OutputVertices, it says:
1627 *
1628 * "One mode must be set in at least one of the tessellation
1629 * shader stages."
1630 *
1631 * So, the fields can be set in either the TCS or TES, but they must
1632 * agree if set in both. Our backend looks at TES, so bitwise-or in
1633 * the values from the TCS.
1634 */
1635 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1636 tes_info->tess.tcs_vertices_out == 0 ||
1637 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1638 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1639
1640 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1641 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1642 tcs_info->tess.spacing == tes_info->tess.spacing);
1643 tes_info->tess.spacing |= tcs_info->tess.spacing;
1644
1645 assert(tcs_info->tess.primitive_mode == 0 ||
1646 tes_info->tess.primitive_mode == 0 ||
1647 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1648 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1649 tes_info->tess.ccw |= tcs_info->tess.ccw;
1650 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1651 }
1652
1653 static
1654 void radv_create_shaders(struct radv_pipeline *pipeline,
1655 struct radv_device *device,
1656 struct radv_pipeline_cache *cache,
1657 struct radv_pipeline_key key,
1658 const VkPipelineShaderStageCreateInfo **pStages)
1659 {
1660 struct radv_shader_module fs_m = {0};
1661 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1662 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1663 void *codes[MESA_SHADER_STAGES] = {0};
1664 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1665 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1666 unsigned char hash[20], gs_copy_hash[20];
1667
1668 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1669 if (pStages[i]) {
1670 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1671 if (modules[i]->nir)
1672 _mesa_sha1_compute(modules[i]->nir->info.name,
1673 strlen(modules[i]->nir->info.name),
1674 modules[i]->sha1);
1675 }
1676 }
1677
1678 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1679 memcpy(gs_copy_hash, hash, 20);
1680 gs_copy_hash[0] ^= 1;
1681
1682 if (modules[MESA_SHADER_GEOMETRY]) {
1683 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1684 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1685 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1686 }
1687
1688 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1689 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1690 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1691 if (pipeline->shaders[i])
1692 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1693 }
1694 return;
1695 }
1696
1697 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1698 nir_builder fs_b;
1699 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1700 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1701 fs_m.nir = fs_b.shader;
1702 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1703 }
1704
1705 /* Determine first and last stage. */
1706 unsigned first = MESA_SHADER_STAGES;
1707 unsigned last = 0;
1708 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1709 if (!pStages[i])
1710 continue;
1711 if (first == MESA_SHADER_STAGES)
1712 first = i;
1713 last = i;
1714 }
1715
1716 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1717 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1718
1719 if (!modules[i])
1720 continue;
1721
1722 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1723 stage ? stage->pName : "main", i,
1724 stage ? stage->pSpecializationInfo : NULL);
1725 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1726
1727 /* We don't want to alter meta shaders IR directly so clone it
1728 * first.
1729 */
1730 if (nir[i]->info.name) {
1731 nir[i] = nir_shader_clone(NULL, nir[i]);
1732 }
1733
1734 if (first != last) {
1735 nir_variable_mode mask = 0;
1736
1737 if (i != first)
1738 mask = mask | nir_var_shader_in;
1739
1740 if (i != last)
1741 mask = mask | nir_var_shader_out;
1742
1743 nir_lower_io_to_scalar_early(nir[i], mask);
1744 radv_optimize_nir(nir[i]);
1745 }
1746 }
1747
1748 if (nir[MESA_SHADER_TESS_CTRL]) {
1749 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1750 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1751 }
1752
1753 radv_link_shaders(pipeline, nir);
1754
1755 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1756 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1757 nir_print_shader(nir[i], stderr);
1758 }
1759
1760 radv_fill_shader_keys(keys, &key, nir);
1761
1762 if (nir[MESA_SHADER_FRAGMENT]) {
1763 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1764 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1765 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1766 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1767 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1768 }
1769
1770 /* TODO: These are no longer used as keys we should refactor this */
1771 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1772 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1773 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1774 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1775 }
1776
1777 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1778 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1779 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1780 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1781 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1782 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1783 pipeline->layout,
1784 &key, &codes[MESA_SHADER_TESS_CTRL],
1785 &code_sizes[MESA_SHADER_TESS_CTRL]);
1786 }
1787 modules[MESA_SHADER_VERTEX] = NULL;
1788 }
1789
1790 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1791 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1792 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1793 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1794 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1795 pipeline->layout,
1796 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1797 &code_sizes[MESA_SHADER_GEOMETRY]);
1798 }
1799 modules[pre_stage] = NULL;
1800 }
1801
1802 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1803 if(modules[i] && !pipeline->shaders[i]) {
1804 if (i == MESA_SHADER_TESS_CTRL) {
1805 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
1806 }
1807 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1808 pipeline->layout,
1809 keys + i, &codes[i],
1810 &code_sizes[i]);
1811 }
1812 }
1813
1814 if(modules[MESA_SHADER_GEOMETRY]) {
1815 void *gs_copy_code = NULL;
1816 unsigned gs_copy_code_size = 0;
1817 if (!pipeline->gs_copy_shader) {
1818 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1819 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1820 &gs_copy_code_size,
1821 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1822 }
1823
1824 if (pipeline->gs_copy_shader) {
1825 void *code[MESA_SHADER_STAGES] = {0};
1826 unsigned code_size[MESA_SHADER_STAGES] = {0};
1827 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1828
1829 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1830 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1831 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1832
1833 radv_pipeline_cache_insert_shaders(device, cache,
1834 gs_copy_hash,
1835 variants,
1836 (const void**)code,
1837 code_size);
1838 }
1839 free(gs_copy_code);
1840 }
1841
1842 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1843 (const void**)codes, code_sizes);
1844
1845 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1846 free(codes[i]);
1847 if (modules[i]) {
1848 if (!pipeline->device->keep_shader_info)
1849 ralloc_free(nir[i]);
1850
1851 if (radv_can_dump_shader_stats(device, modules[i]))
1852 radv_shader_dump_stats(device,
1853 pipeline->shaders[i],
1854 i, stderr);
1855 }
1856 }
1857
1858 if (fs_m.nir)
1859 ralloc_free(fs_m.nir);
1860 }
1861
1862 static uint32_t
1863 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1864 gl_shader_stage stage, enum chip_class chip_class)
1865 {
1866 bool has_gs = radv_pipeline_has_gs(pipeline);
1867 bool has_tess = radv_pipeline_has_tess(pipeline);
1868 switch (stage) {
1869 case MESA_SHADER_FRAGMENT:
1870 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1871 case MESA_SHADER_VERTEX:
1872 if (chip_class >= GFX9) {
1873 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1874 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1875 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1876 }
1877 if (has_tess)
1878 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1879 else
1880 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1881 case MESA_SHADER_GEOMETRY:
1882 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1883 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1884 case MESA_SHADER_COMPUTE:
1885 return R_00B900_COMPUTE_USER_DATA_0;
1886 case MESA_SHADER_TESS_CTRL:
1887 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1888 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1889 case MESA_SHADER_TESS_EVAL:
1890 if (chip_class >= GFX9) {
1891 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1892 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1893 }
1894 if (has_gs)
1895 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1896 else
1897 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1898 default:
1899 unreachable("unknown shader");
1900 }
1901 }
1902
1903 struct radv_bin_size_entry {
1904 unsigned bpp;
1905 VkExtent2D extent;
1906 };
1907
1908 static VkExtent2D
1909 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1910 {
1911 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1912 {
1913 /* One RB / SE */
1914 {
1915 /* One shader engine */
1916 { 0, {128, 128}},
1917 { 1, { 64, 128}},
1918 { 2, { 32, 128}},
1919 { 3, { 16, 128}},
1920 { 17, { 0, 0}},
1921 { UINT_MAX, { 0, 0}},
1922 },
1923 {
1924 /* Two shader engines */
1925 { 0, {128, 128}},
1926 { 2, { 64, 128}},
1927 { 3, { 32, 128}},
1928 { 5, { 16, 128}},
1929 { 17, { 0, 0}},
1930 { UINT_MAX, { 0, 0}},
1931 },
1932 {
1933 /* Four shader engines */
1934 { 0, {128, 128}},
1935 { 3, { 64, 128}},
1936 { 5, { 16, 128}},
1937 { 17, { 0, 0}},
1938 { UINT_MAX, { 0, 0}},
1939 },
1940 },
1941 {
1942 /* Two RB / SE */
1943 {
1944 /* One shader engine */
1945 { 0, {128, 128}},
1946 { 2, { 64, 128}},
1947 { 3, { 32, 128}},
1948 { 5, { 16, 128}},
1949 { 33, { 0, 0}},
1950 { UINT_MAX, { 0, 0}},
1951 },
1952 {
1953 /* Two shader engines */
1954 { 0, {128, 128}},
1955 { 3, { 64, 128}},
1956 { 5, { 32, 128}},
1957 { 9, { 16, 128}},
1958 { 33, { 0, 0}},
1959 { UINT_MAX, { 0, 0}},
1960 },
1961 {
1962 /* Four shader engines */
1963 { 0, {256, 256}},
1964 { 2, {128, 256}},
1965 { 3, {128, 128}},
1966 { 5, { 64, 128}},
1967 { 9, { 16, 128}},
1968 { 33, { 0, 0}},
1969 { UINT_MAX, { 0, 0}},
1970 },
1971 },
1972 {
1973 /* Four RB / SE */
1974 {
1975 /* One shader engine */
1976 { 0, {128, 256}},
1977 { 2, {128, 128}},
1978 { 3, { 64, 128}},
1979 { 5, { 32, 128}},
1980 { 9, { 16, 128}},
1981 { 33, { 0, 0}},
1982 { UINT_MAX, { 0, 0}},
1983 },
1984 {
1985 /* Two shader engines */
1986 { 0, {256, 256}},
1987 { 2, {128, 256}},
1988 { 3, {128, 128}},
1989 { 5, { 64, 128}},
1990 { 9, { 32, 128}},
1991 { 17, { 16, 128}},
1992 { 33, { 0, 0}},
1993 { UINT_MAX, { 0, 0}},
1994 },
1995 {
1996 /* Four shader engines */
1997 { 0, {256, 512}},
1998 { 2, {256, 256}},
1999 { 3, {128, 256}},
2000 { 5, {128, 128}},
2001 { 9, { 64, 128}},
2002 { 17, { 16, 128}},
2003 { 33, { 0, 0}},
2004 { UINT_MAX, { 0, 0}},
2005 },
2006 },
2007 };
2008 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2009 {
2010 // One RB / SE
2011 {
2012 // One shader engine
2013 { 0, {128, 256}},
2014 { 2, {128, 128}},
2015 { 4, { 64, 128}},
2016 { 7, { 32, 128}},
2017 { 13, { 16, 128}},
2018 { 49, { 0, 0}},
2019 { UINT_MAX, { 0, 0}},
2020 },
2021 {
2022 // Two shader engines
2023 { 0, {256, 256}},
2024 { 2, {128, 256}},
2025 { 4, {128, 128}},
2026 { 7, { 64, 128}},
2027 { 13, { 32, 128}},
2028 { 25, { 16, 128}},
2029 { 49, { 0, 0}},
2030 { UINT_MAX, { 0, 0}},
2031 },
2032 {
2033 // Four shader engines
2034 { 0, {256, 512}},
2035 { 2, {256, 256}},
2036 { 4, {128, 256}},
2037 { 7, {128, 128}},
2038 { 13, { 64, 128}},
2039 { 25, { 16, 128}},
2040 { 49, { 0, 0}},
2041 { UINT_MAX, { 0, 0}},
2042 },
2043 },
2044 {
2045 // Two RB / SE
2046 {
2047 // One shader engine
2048 { 0, {256, 256}},
2049 { 2, {128, 256}},
2050 { 4, {128, 128}},
2051 { 7, { 64, 128}},
2052 { 13, { 32, 128}},
2053 { 25, { 16, 128}},
2054 { 97, { 0, 0}},
2055 { UINT_MAX, { 0, 0}},
2056 },
2057 {
2058 // Two shader engines
2059 { 0, {256, 512}},
2060 { 2, {256, 256}},
2061 { 4, {128, 256}},
2062 { 7, {128, 128}},
2063 { 13, { 64, 128}},
2064 { 25, { 32, 128}},
2065 { 49, { 16, 128}},
2066 { 97, { 0, 0}},
2067 { UINT_MAX, { 0, 0}},
2068 },
2069 {
2070 // Four shader engines
2071 { 0, {512, 512}},
2072 { 2, {256, 512}},
2073 { 4, {256, 256}},
2074 { 7, {128, 256}},
2075 { 13, {128, 128}},
2076 { 25, { 64, 128}},
2077 { 49, { 16, 128}},
2078 { 97, { 0, 0}},
2079 { UINT_MAX, { 0, 0}},
2080 },
2081 },
2082 {
2083 // Four RB / SE
2084 {
2085 // One shader engine
2086 { 0, {256, 512}},
2087 { 2, {256, 256}},
2088 { 4, {128, 256}},
2089 { 7, {128, 128}},
2090 { 13, { 64, 128}},
2091 { 25, { 32, 128}},
2092 { 49, { 16, 128}},
2093 { UINT_MAX, { 0, 0}},
2094 },
2095 {
2096 // Two shader engines
2097 { 0, {512, 512}},
2098 { 2, {256, 512}},
2099 { 4, {256, 256}},
2100 { 7, {128, 256}},
2101 { 13, {128, 128}},
2102 { 25, { 64, 128}},
2103 { 49, { 32, 128}},
2104 { 97, { 16, 128}},
2105 { UINT_MAX, { 0, 0}},
2106 },
2107 {
2108 // Four shader engines
2109 { 0, {512, 512}},
2110 { 4, {256, 512}},
2111 { 7, {256, 256}},
2112 { 13, {128, 256}},
2113 { 25, {128, 128}},
2114 { 49, { 64, 128}},
2115 { 97, { 16, 128}},
2116 { UINT_MAX, { 0, 0}},
2117 },
2118 },
2119 };
2120
2121 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2122 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2123 VkExtent2D extent = {512, 512};
2124
2125 unsigned log_num_rb_per_se =
2126 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2127 pipeline->device->physical_device->rad_info.max_se);
2128 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2129
2130 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2131 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2132 unsigned effective_samples = total_samples;
2133 unsigned color_bytes_per_pixel = 0;
2134
2135 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2136 if (vkblend) {
2137 for (unsigned i = 0; i < subpass->color_count; i++) {
2138 if (!vkblend->pAttachments[i].colorWriteMask)
2139 continue;
2140
2141 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2142 continue;
2143
2144 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2145 color_bytes_per_pixel += vk_format_get_blocksize(format);
2146 }
2147
2148 /* MSAA images typically don't use all samples all the time. */
2149 if (effective_samples >= 2 && ps_iter_samples <= 1)
2150 effective_samples = 2;
2151 color_bytes_per_pixel *= effective_samples;
2152 }
2153
2154 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2155 while(color_entry->bpp <= color_bytes_per_pixel)
2156 ++color_entry;
2157
2158 extent = color_entry->extent;
2159
2160 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2161 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2162
2163 /* Coefficients taken from AMDVLK */
2164 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2165 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2166 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2167
2168 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2169 while(ds_entry->bpp <= ds_bytes_per_pixel)
2170 ++ds_entry;
2171
2172 extent.width = MIN2(extent.width, ds_entry->extent.width);
2173 extent.height = MIN2(extent.height, ds_entry->extent.height);
2174 }
2175
2176 return extent;
2177 }
2178
2179 static void
2180 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2181 struct radv_pipeline *pipeline,
2182 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2183 {
2184 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2185 return;
2186
2187 uint32_t pa_sc_binner_cntl_0 =
2188 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2189 S_028C44_DISABLE_START_OF_PRIM(1);
2190 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2191
2192 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2193
2194 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2195 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2196 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2197
2198 switch (pipeline->device->physical_device->rad_info.family) {
2199 case CHIP_VEGA10:
2200 context_states_per_bin = 1;
2201 persistent_states_per_bin = 1;
2202 fpovs_per_batch = 63;
2203 break;
2204 case CHIP_RAVEN:
2205 context_states_per_bin = 6;
2206 persistent_states_per_bin = 32;
2207 fpovs_per_batch = 63;
2208 break;
2209 default:
2210 unreachable("unhandled family while determining binning state.");
2211 }
2212
2213 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2214 pa_sc_binner_cntl_0 =
2215 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2216 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2217 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2218 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2219 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2220 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2221 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2222 S_028C44_DISABLE_START_OF_PRIM(1) |
2223 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2224 S_028C44_OPTIMAL_BIN_SELECTION(1);
2225 }
2226
2227 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2228 pa_sc_binner_cntl_0);
2229 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2230 db_dfsm_control);
2231 }
2232
2233
2234 static void
2235 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2236 struct radv_pipeline *pipeline,
2237 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2238 const struct radv_graphics_pipeline_create_info *extra)
2239 {
2240 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2241 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2242 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2243 struct radv_render_pass_attachment *attachment = NULL;
2244 uint32_t db_depth_control = 0, db_stencil_control = 0;
2245 uint32_t db_render_control = 0, db_render_override2 = 0;
2246
2247 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2248 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2249
2250 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2251 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2252
2253 if (vkds && has_depth_attachment) {
2254 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2255 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2256 S_028800_ZFUNC(vkds->depthCompareOp) |
2257 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2258
2259 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2260 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2261 }
2262
2263 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2264 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2265 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2266 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2267 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2268 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2269
2270 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2271 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2272 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2273 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2274 }
2275
2276 if (attachment && extra) {
2277 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2278 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2279
2280 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2281 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2282 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2283 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2284 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2285 }
2286
2287 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2288 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2289
2290 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2291 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2292 }
2293
2294 static void
2295 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2296 struct radv_pipeline *pipeline,
2297 const struct radv_blend_state *blend)
2298 {
2299 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2300 radeon_emit_array(cs, blend->cb_blend_control,
2301 8);
2302 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2303 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2304
2305 if (pipeline->device->physical_device->has_rbplus) {
2306
2307 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2308 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2309
2310 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2311 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2312 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2313 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2314 }
2315
2316 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2317
2318 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2319 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2320 }
2321
2322
2323 static void
2324 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2325 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2326 {
2327 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2328
2329 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2330 S_028810_PS_UCP_MODE(3) |
2331 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2332 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2333 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2334 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2335 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2336
2337 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2338 S_0286D4_FLAT_SHADE_ENA(1) |
2339 S_0286D4_PNT_SPRITE_ENA(1) |
2340 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2341 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2342 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2343 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2344 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2345
2346 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2347 S_028BE4_PIX_CENTER(1) | // TODO verify
2348 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2349 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2350
2351 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2352 S_028814_FACE(vkraster->frontFace) |
2353 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2354 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2355 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2356 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2357 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2358 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2359 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2360 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2361 }
2362
2363
2364 static void
2365 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2366 struct radv_pipeline *pipeline)
2367 {
2368 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2369
2370 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2371 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2372 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2373
2374 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2375 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2376
2377 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2378 uint32_t offset;
2379 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2380 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2381 if (loc->sgpr_idx == -1)
2382 return;
2383 assert(loc->num_sgprs == 1);
2384 assert(!loc->indirect);
2385 switch (pipeline->graphics.ms.num_samples) {
2386 default:
2387 offset = 0;
2388 break;
2389 case 2:
2390 offset = 1;
2391 break;
2392 case 4:
2393 offset = 3;
2394 break;
2395 case 8:
2396 offset = 7;
2397 break;
2398 case 16:
2399 offset = 15;
2400 break;
2401 }
2402
2403 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2404 }
2405 }
2406
2407 static void
2408 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2409 const struct radv_pipeline *pipeline)
2410 {
2411 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2412
2413 uint32_t vgt_primitiveid_en = false;
2414 uint32_t vgt_gs_mode = 0;
2415
2416 if (radv_pipeline_has_gs(pipeline)) {
2417 const struct radv_shader_variant *gs =
2418 pipeline->shaders[MESA_SHADER_GEOMETRY];
2419
2420 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2421 pipeline->device->physical_device->rad_info.chip_class);
2422 } else if (outinfo->export_prim_id) {
2423 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2424 vgt_primitiveid_en = true;
2425 }
2426
2427 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2428 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2429 }
2430
2431 static void
2432 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2433 struct radv_pipeline *pipeline,
2434 struct radv_shader_variant *shader)
2435 {
2436 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2437
2438 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2439 radeon_emit(cs, va >> 8);
2440 radeon_emit(cs, va >> 40);
2441 radeon_emit(cs, shader->rsrc1);
2442 radeon_emit(cs, shader->rsrc2);
2443
2444 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2445 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2446 clip_dist_mask = outinfo->clip_dist_mask;
2447 cull_dist_mask = outinfo->cull_dist_mask;
2448 total_mask = clip_dist_mask | cull_dist_mask;
2449 bool misc_vec_ena = outinfo->writes_pointsize ||
2450 outinfo->writes_layer ||
2451 outinfo->writes_viewport_index;
2452
2453 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2454 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2455
2456 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2457 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2458 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2459 V_02870C_SPI_SHADER_4COMP :
2460 V_02870C_SPI_SHADER_NONE) |
2461 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2462 V_02870C_SPI_SHADER_4COMP :
2463 V_02870C_SPI_SHADER_NONE) |
2464 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2465 V_02870C_SPI_SHADER_4COMP :
2466 V_02870C_SPI_SHADER_NONE));
2467
2468 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2469 S_028818_VTX_W0_FMT(1) |
2470 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2471 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2472 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2473
2474 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2475 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2476 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2477 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2478 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2479 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2480 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2481 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2482 cull_dist_mask << 8 |
2483 clip_dist_mask);
2484
2485 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2486 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2487 outinfo->writes_viewport_index);
2488 }
2489
2490 static void
2491 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2492 struct radv_pipeline *pipeline,
2493 struct radv_shader_variant *shader)
2494 {
2495 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2496
2497 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2498 radeon_emit(cs, va >> 8);
2499 radeon_emit(cs, va >> 40);
2500 radeon_emit(cs, shader->rsrc1);
2501 radeon_emit(cs, shader->rsrc2);
2502 }
2503
2504 static void
2505 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2506 struct radv_pipeline *pipeline,
2507 struct radv_shader_variant *shader,
2508 const struct radv_tessellation_state *tess)
2509 {
2510 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2511 uint32_t rsrc2 = shader->rsrc2;
2512
2513 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2514 radeon_emit(cs, va >> 8);
2515 radeon_emit(cs, va >> 40);
2516
2517 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2518 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2519 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2520 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2521
2522 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2523 radeon_emit(cs, shader->rsrc1);
2524 radeon_emit(cs, rsrc2);
2525 }
2526
2527 static void
2528 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2529 struct radv_pipeline *pipeline,
2530 struct radv_shader_variant *shader,
2531 const struct radv_tessellation_state *tess)
2532 {
2533 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2534
2535 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2536 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2537 radeon_emit(cs, va >> 8);
2538 radeon_emit(cs, va >> 40);
2539
2540 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2541 radeon_emit(cs, shader->rsrc1);
2542 radeon_emit(cs, shader->rsrc2 |
2543 S_00B42C_LDS_SIZE(tess->lds_size));
2544 } else {
2545 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2546 radeon_emit(cs, va >> 8);
2547 radeon_emit(cs, va >> 40);
2548 radeon_emit(cs, shader->rsrc1);
2549 radeon_emit(cs, shader->rsrc2);
2550 }
2551 }
2552
2553 static void
2554 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2555 struct radv_pipeline *pipeline,
2556 const struct radv_tessellation_state *tess)
2557 {
2558 struct radv_shader_variant *vs;
2559
2560 /* Skip shaders merged into HS/GS */
2561 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2562 if (!vs)
2563 return;
2564
2565 if (vs->info.vs.as_ls)
2566 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2567 else if (vs->info.vs.as_es)
2568 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2569 else
2570 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2571 }
2572
2573 static void
2574 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2575 struct radv_pipeline *pipeline,
2576 const struct radv_tessellation_state *tess)
2577 {
2578 if (!radv_pipeline_has_tess(pipeline))
2579 return;
2580
2581 struct radv_shader_variant *tes, *tcs;
2582
2583 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2584 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2585
2586 if (tes) {
2587 if (tes->info.tes.as_es)
2588 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2589 else
2590 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2591 }
2592
2593 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2594
2595 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2596 tess->tf_param);
2597
2598 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2599 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2600 tess->ls_hs_config);
2601 else
2602 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2603 tess->ls_hs_config);
2604
2605 struct radv_userdata_info *loc;
2606
2607 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
2608 if (loc->sgpr_idx != -1) {
2609 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
2610 assert(loc->num_sgprs == 1);
2611 assert(!loc->indirect);
2612 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 1);
2613 radeon_emit(cs, tess->offchip_layout);
2614 }
2615
2616 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
2617 if (loc->sgpr_idx != -1) {
2618 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
2619 assert(loc->num_sgprs == 1);
2620 assert(!loc->indirect);
2621
2622 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2623 tess->offchip_layout);
2624 }
2625 }
2626
2627 static void
2628 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2629 struct radv_pipeline *pipeline,
2630 const struct radv_gs_state *gs_state)
2631 {
2632 struct radv_shader_variant *gs;
2633 uint64_t va;
2634
2635 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2636 if (!gs)
2637 return;
2638
2639 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2640
2641 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2642 radeon_emit(cs, gsvs_itemsize);
2643 radeon_emit(cs, gsvs_itemsize);
2644 radeon_emit(cs, gsvs_itemsize);
2645
2646 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2647
2648 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2649
2650 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2651 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2652 radeon_emit(cs, gs_vert_itemsize >> 2);
2653 radeon_emit(cs, 0);
2654 radeon_emit(cs, 0);
2655 radeon_emit(cs, 0);
2656
2657 uint32_t gs_num_invocations = gs->info.gs.invocations;
2658 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2659 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2660 S_028B90_ENABLE(gs_num_invocations > 0));
2661
2662 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2663 gs_state->vgt_esgs_ring_itemsize);
2664
2665 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2666
2667 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2668 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2669 radeon_emit(cs, va >> 8);
2670 radeon_emit(cs, va >> 40);
2671
2672 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2673 radeon_emit(cs, gs->rsrc1);
2674 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2675
2676 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2677 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2678 } else {
2679 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2680 radeon_emit(cs, va >> 8);
2681 radeon_emit(cs, va >> 40);
2682 radeon_emit(cs, gs->rsrc1);
2683 radeon_emit(cs, gs->rsrc2);
2684 }
2685
2686 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2687
2688 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2689 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
2690 if (loc->sgpr_idx != -1) {
2691 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
2692 uint32_t num_entries = 64;
2693 bool is_vi = pipeline->device->physical_device->rad_info.chip_class >= VI;
2694
2695 if (is_vi)
2696 num_entries *= stride;
2697
2698 stride = S_008F04_STRIDE(stride);
2699 radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
2700 radeon_emit(cs, stride);
2701 radeon_emit(cs, num_entries);
2702 }
2703 }
2704
2705 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2706 {
2707 uint32_t ps_input_cntl;
2708 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2709 ps_input_cntl = S_028644_OFFSET(offset);
2710 if (flat_shade)
2711 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2712 } else {
2713 /* The input is a DEFAULT_VAL constant. */
2714 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2715 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2716 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2717 ps_input_cntl = S_028644_OFFSET(0x20) |
2718 S_028644_DEFAULT_VAL(offset);
2719 }
2720 return ps_input_cntl;
2721 }
2722
2723 static void
2724 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2725 struct radv_pipeline *pipeline)
2726 {
2727 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2728 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2729 uint32_t ps_input_cntl[32];
2730
2731 unsigned ps_offset = 0;
2732
2733 if (ps->info.info.ps.prim_id_input) {
2734 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2735 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2736 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2737 ++ps_offset;
2738 }
2739 }
2740
2741 if (ps->info.info.ps.layer_input ||
2742 ps->info.info.ps.uses_input_attachments ||
2743 ps->info.info.needs_multiview_view_index) {
2744 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2745 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2746 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2747 else
2748 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2749 ++ps_offset;
2750 }
2751
2752 if (ps->info.info.ps.has_pcoord) {
2753 unsigned val;
2754 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2755 ps_input_cntl[ps_offset] = val;
2756 ps_offset++;
2757 }
2758
2759 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2760 unsigned vs_offset;
2761 bool flat_shade;
2762 if (!(ps->info.fs.input_mask & (1u << i)))
2763 continue;
2764
2765 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2766 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2767 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2768 ++ps_offset;
2769 continue;
2770 }
2771
2772 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2773
2774 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2775 ++ps_offset;
2776 }
2777
2778 if (ps_offset) {
2779 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2780 for (unsigned i = 0; i < ps_offset; i++) {
2781 radeon_emit(cs, ps_input_cntl[i]);
2782 }
2783 }
2784 }
2785
2786 static uint32_t
2787 radv_compute_db_shader_control(const struct radv_device *device,
2788 const struct radv_shader_variant *ps)
2789 {
2790 unsigned z_order;
2791 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2792 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2793 else
2794 z_order = V_02880C_LATE_Z;
2795
2796 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
2797 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
2798 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2799 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
2800 S_02880C_Z_ORDER(z_order) |
2801 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2802 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2803 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
2804 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
2805 }
2806
2807 static void
2808 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2809 struct radv_pipeline *pipeline)
2810 {
2811 struct radv_shader_variant *ps;
2812 uint64_t va;
2813 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2814
2815 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2816 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2817
2818 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2819 radeon_emit(cs, va >> 8);
2820 radeon_emit(cs, va >> 40);
2821 radeon_emit(cs, ps->rsrc1);
2822 radeon_emit(cs, ps->rsrc2);
2823
2824 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2825 radv_compute_db_shader_control(pipeline->device, ps));
2826
2827 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2828 ps->config.spi_ps_input_ena);
2829
2830 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2831 ps->config.spi_ps_input_addr);
2832
2833 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2834 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2835
2836 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2837
2838 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2839 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
2840 ps->info.info.ps.writes_stencil,
2841 ps->info.info.ps.writes_sample_mask));
2842
2843 if (pipeline->device->dfsm_allowed) {
2844 /* optimise this? */
2845 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2846 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2847 }
2848 }
2849
2850 static void
2851 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2852 struct radv_pipeline *pipeline)
2853 {
2854 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2855 return;
2856
2857 unsigned vtx_reuse_depth = 30;
2858 if (radv_pipeline_has_tess(pipeline) &&
2859 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2860 vtx_reuse_depth = 14;
2861 }
2862 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2863 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2864 }
2865
2866 static uint32_t
2867 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
2868 {
2869 uint32_t stages = 0;
2870 if (radv_pipeline_has_tess(pipeline)) {
2871 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2872 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2873
2874 if (radv_pipeline_has_gs(pipeline))
2875 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2876 S_028B54_GS_EN(1) |
2877 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2878 else
2879 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2880
2881 } else if (radv_pipeline_has_gs(pipeline))
2882 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2883 S_028B54_GS_EN(1) |
2884 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2885
2886 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
2887 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2888
2889 return stages;
2890 }
2891
2892 static uint32_t
2893 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
2894 {
2895 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
2896 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
2897
2898 if (!discard_rectangle_info)
2899 return 0xffff;
2900
2901 unsigned mask = 0;
2902
2903 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
2904 /* Interpret i as a bitmask, and then set the bit in the mask if
2905 * that combination of rectangles in which the pixel is contained
2906 * should pass the cliprect test. */
2907 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
2908
2909 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
2910 !relevant_subset)
2911 continue;
2912
2913 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
2914 relevant_subset)
2915 continue;
2916
2917 mask |= 1u << i;
2918 }
2919
2920 return mask;
2921 }
2922
2923 static void
2924 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2925 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2926 const struct radv_graphics_pipeline_create_info *extra,
2927 const struct radv_blend_state *blend,
2928 const struct radv_tessellation_state *tess,
2929 const struct radv_gs_state *gs,
2930 unsigned prim, unsigned gs_out)
2931 {
2932 pipeline->cs.buf = malloc(4 * 256);
2933 pipeline->cs.max_dw = 256;
2934
2935 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2936 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
2937 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
2938 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2939 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
2940 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
2941 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
2942 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
2943 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2944 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2945 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2946 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2947
2948 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2949 S_0286E8_WAVES(pipeline->max_waves) |
2950 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2951
2952 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
2953
2954 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2955 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
2956 } else {
2957 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
2958 }
2959 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
2960
2961 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
2962
2963 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2964 }
2965
2966 static struct radv_ia_multi_vgt_param_helpers
2967 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
2968 const struct radv_tessellation_state *tess,
2969 uint32_t prim)
2970 {
2971 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
2972 const struct radv_device *device = pipeline->device;
2973
2974 if (radv_pipeline_has_tess(pipeline))
2975 ia_multi_vgt_param.primgroup_size = tess->num_patches;
2976 else if (radv_pipeline_has_gs(pipeline))
2977 ia_multi_vgt_param.primgroup_size = 64;
2978 else
2979 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
2980
2981 ia_multi_vgt_param.partial_es_wave = false;
2982 if (pipeline->device->has_distributed_tess) {
2983 if (radv_pipeline_has_gs(pipeline)) {
2984 if (device->physical_device->rad_info.chip_class <= VI)
2985 ia_multi_vgt_param.partial_es_wave = true;
2986 }
2987 }
2988 /* GS requirement. */
2989 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
2990 ia_multi_vgt_param.partial_es_wave = true;
2991
2992 ia_multi_vgt_param.wd_switch_on_eop = false;
2993 if (device->physical_device->rad_info.chip_class >= CIK) {
2994 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2995 * 4 shader engines. Set 1 to pass the assertion below.
2996 * The other cases are hardware requirements. */
2997 if (device->physical_device->rad_info.max_se < 4 ||
2998 prim == V_008958_DI_PT_POLYGON ||
2999 prim == V_008958_DI_PT_LINELOOP ||
3000 prim == V_008958_DI_PT_TRIFAN ||
3001 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3002 (pipeline->graphics.prim_restart_enable &&
3003 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3004 (prim != V_008958_DI_PT_POINTLIST &&
3005 prim != V_008958_DI_PT_LINESTRIP &&
3006 prim != V_008958_DI_PT_TRISTRIP))))
3007 ia_multi_vgt_param.wd_switch_on_eop = true;
3008 }
3009
3010 ia_multi_vgt_param.ia_switch_on_eoi = false;
3011 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3012 ia_multi_vgt_param.ia_switch_on_eoi = true;
3013 if (radv_pipeline_has_gs(pipeline) &&
3014 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3015 ia_multi_vgt_param.ia_switch_on_eoi = true;
3016 if (radv_pipeline_has_tess(pipeline)) {
3017 /* SWITCH_ON_EOI must be set if PrimID is used. */
3018 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3019 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3020 ia_multi_vgt_param.ia_switch_on_eoi = true;
3021 }
3022
3023 ia_multi_vgt_param.partial_vs_wave = false;
3024 if (radv_pipeline_has_tess(pipeline)) {
3025 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3026 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3027 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3028 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3029 radv_pipeline_has_gs(pipeline))
3030 ia_multi_vgt_param.partial_vs_wave = true;
3031 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3032 if (device->has_distributed_tess) {
3033 if (radv_pipeline_has_gs(pipeline)) {
3034 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3035 device->physical_device->rad_info.family == CHIP_FIJI ||
3036 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3037 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3038 device->physical_device->rad_info.family == CHIP_POLARIS12)
3039 ia_multi_vgt_param.partial_vs_wave = true;
3040 } else {
3041 ia_multi_vgt_param.partial_vs_wave = true;
3042 }
3043 }
3044 }
3045
3046 ia_multi_vgt_param.base =
3047 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3048 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3049 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3050 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3051 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3052
3053 return ia_multi_vgt_param;
3054 }
3055
3056
3057 static void
3058 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3059 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3060 {
3061 const VkPipelineVertexInputStateCreateInfo *vi_info =
3062 pCreateInfo->pVertexInputState;
3063 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3064
3065 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3066 const VkVertexInputAttributeDescription *desc =
3067 &vi_info->pVertexAttributeDescriptions[i];
3068 unsigned loc = desc->location;
3069 const struct vk_format_description *format_desc;
3070 int first_non_void;
3071 uint32_t num_format, data_format;
3072 format_desc = vk_format_description(desc->format);
3073 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3074
3075 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3076 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3077
3078 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3079 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3080 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3081 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3082 S_008F0C_NUM_FORMAT(num_format) |
3083 S_008F0C_DATA_FORMAT(data_format);
3084 velems->format_size[loc] = format_desc->block.bits / 8;
3085 velems->offset[loc] = desc->offset;
3086 velems->binding[loc] = desc->binding;
3087 velems->count = MAX2(velems->count, loc + 1);
3088 }
3089
3090 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3091 const VkVertexInputBindingDescription *desc =
3092 &vi_info->pVertexBindingDescriptions[i];
3093
3094 pipeline->binding_stride[desc->binding] = desc->stride;
3095 }
3096 }
3097
3098 static VkResult
3099 radv_pipeline_init(struct radv_pipeline *pipeline,
3100 struct radv_device *device,
3101 struct radv_pipeline_cache *cache,
3102 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3103 const struct radv_graphics_pipeline_create_info *extra,
3104 const VkAllocationCallbacks *alloc)
3105 {
3106 VkResult result;
3107 bool has_view_index = false;
3108
3109 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3110 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3111 if (subpass->view_mask)
3112 has_view_index = true;
3113 if (alloc == NULL)
3114 alloc = &device->alloc;
3115
3116 pipeline->device = device;
3117 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3118 assert(pipeline->layout);
3119
3120 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3121
3122 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3123 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3124 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3125 pStages[stage] = &pCreateInfo->pStages[i];
3126 }
3127
3128 radv_create_shaders(pipeline, device, cache,
3129 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3130 pStages);
3131
3132 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3133 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
3134 uint32_t gs_out;
3135 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3136
3137 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3138
3139 if (radv_pipeline_has_gs(pipeline)) {
3140 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3141 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3142 } else {
3143 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3144 }
3145 if (extra && extra->use_rectlist) {
3146 prim = V_008958_DI_PT_RECTLIST;
3147 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3148 pipeline->graphics.can_use_guardband = true;
3149 }
3150 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3151 /* prim vertex count will need TESS changes */
3152 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3153
3154 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3155
3156 /* Ensure that some export memory is always allocated, for two reasons:
3157 *
3158 * 1) Correctness: The hardware ignores the EXEC mask if no export
3159 * memory is allocated, so KILL and alpha test do not work correctly
3160 * without this.
3161 * 2) Performance: Every shader needs at least a NULL export, even when
3162 * it writes no color/depth output. The NULL export instruction
3163 * stalls without this setting.
3164 *
3165 * Don't add this to CB_SHADER_MASK.
3166 */
3167 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3168 if (!blend.spi_shader_col_format) {
3169 if (!ps->info.info.ps.writes_z &&
3170 !ps->info.info.ps.writes_stencil &&
3171 !ps->info.info.ps.writes_sample_mask)
3172 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3173 }
3174
3175 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3176 if (pipeline->shaders[i]) {
3177 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3178 }
3179 }
3180
3181 struct radv_gs_state gs = {0};
3182 if (radv_pipeline_has_gs(pipeline)) {
3183 gs = calculate_gs_info(pCreateInfo, pipeline);
3184 calculate_gs_ring_sizes(pipeline, &gs);
3185 }
3186
3187 struct radv_tessellation_state tess = {0};
3188 if (radv_pipeline_has_tess(pipeline)) {
3189 if (prim == V_008958_DI_PT_PATCH) {
3190 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3191 pipeline->graphics.prim_vertex_count.incr = 1;
3192 }
3193 tess = calculate_tess_state(pipeline, pCreateInfo);
3194 }
3195
3196 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3197
3198 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3199
3200 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3201 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3202
3203 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3204 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3205 if (loc->sgpr_idx != -1) {
3206 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3207 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3208 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3209 pipeline->graphics.vtx_emit_num = 3;
3210 else
3211 pipeline->graphics.vtx_emit_num = 2;
3212 }
3213
3214 result = radv_pipeline_scratch_init(device, pipeline);
3215 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3216
3217 return result;
3218 }
3219
3220 VkResult
3221 radv_graphics_pipeline_create(
3222 VkDevice _device,
3223 VkPipelineCache _cache,
3224 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3225 const struct radv_graphics_pipeline_create_info *extra,
3226 const VkAllocationCallbacks *pAllocator,
3227 VkPipeline *pPipeline)
3228 {
3229 RADV_FROM_HANDLE(radv_device, device, _device);
3230 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3231 struct radv_pipeline *pipeline;
3232 VkResult result;
3233
3234 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3235 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3236 if (pipeline == NULL)
3237 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3238
3239 result = radv_pipeline_init(pipeline, device, cache,
3240 pCreateInfo, extra, pAllocator);
3241 if (result != VK_SUCCESS) {
3242 radv_pipeline_destroy(device, pipeline, pAllocator);
3243 return result;
3244 }
3245
3246 *pPipeline = radv_pipeline_to_handle(pipeline);
3247
3248 return VK_SUCCESS;
3249 }
3250
3251 VkResult radv_CreateGraphicsPipelines(
3252 VkDevice _device,
3253 VkPipelineCache pipelineCache,
3254 uint32_t count,
3255 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3256 const VkAllocationCallbacks* pAllocator,
3257 VkPipeline* pPipelines)
3258 {
3259 VkResult result = VK_SUCCESS;
3260 unsigned i = 0;
3261
3262 for (; i < count; i++) {
3263 VkResult r;
3264 r = radv_graphics_pipeline_create(_device,
3265 pipelineCache,
3266 &pCreateInfos[i],
3267 NULL, pAllocator, &pPipelines[i]);
3268 if (r != VK_SUCCESS) {
3269 result = r;
3270 pPipelines[i] = VK_NULL_HANDLE;
3271 }
3272 }
3273
3274 return result;
3275 }
3276
3277
3278 static void
3279 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3280 {
3281 struct radv_shader_variant *compute_shader;
3282 struct radv_device *device = pipeline->device;
3283 unsigned compute_resource_limits;
3284 unsigned waves_per_threadgroup;
3285 uint64_t va;
3286
3287 pipeline->cs.buf = malloc(20 * 4);
3288 pipeline->cs.max_dw = 20;
3289
3290 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3291 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3292
3293 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3294 radeon_emit(&pipeline->cs, va >> 8);
3295 radeon_emit(&pipeline->cs, va >> 40);
3296
3297 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3298 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3299 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3300
3301 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3302 S_00B860_WAVES(pipeline->max_waves) |
3303 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3304
3305 /* Calculate best compute resource limits. */
3306 waves_per_threadgroup =
3307 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3308 compute_shader->info.cs.block_size[1] *
3309 compute_shader->info.cs.block_size[2], 64);
3310 compute_resource_limits =
3311 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3312
3313 if (device->physical_device->rad_info.chip_class >= CIK) {
3314 unsigned num_cu_per_se =
3315 device->physical_device->rad_info.num_good_compute_units /
3316 device->physical_device->rad_info.max_se;
3317
3318 /* Force even distribution on all SIMDs in CU if the workgroup
3319 * size is 64. This has shown some good improvements if # of
3320 * CUs per SE is not a multiple of 4.
3321 */
3322 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3323 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3324 }
3325
3326 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3327 compute_resource_limits);
3328
3329 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3330 radeon_emit(&pipeline->cs,
3331 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3332 radeon_emit(&pipeline->cs,
3333 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3334 radeon_emit(&pipeline->cs,
3335 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3336
3337 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3338 }
3339
3340 static VkResult radv_compute_pipeline_create(
3341 VkDevice _device,
3342 VkPipelineCache _cache,
3343 const VkComputePipelineCreateInfo* pCreateInfo,
3344 const VkAllocationCallbacks* pAllocator,
3345 VkPipeline* pPipeline)
3346 {
3347 RADV_FROM_HANDLE(radv_device, device, _device);
3348 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3349 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3350 struct radv_pipeline *pipeline;
3351 VkResult result;
3352
3353 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3354 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3355 if (pipeline == NULL)
3356 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3357
3358 pipeline->device = device;
3359 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3360 assert(pipeline->layout);
3361
3362 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3363 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3364
3365 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3366 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3367 result = radv_pipeline_scratch_init(device, pipeline);
3368 if (result != VK_SUCCESS) {
3369 radv_pipeline_destroy(device, pipeline, pAllocator);
3370 return result;
3371 }
3372
3373 radv_compute_generate_pm4(pipeline);
3374
3375 *pPipeline = radv_pipeline_to_handle(pipeline);
3376
3377 return VK_SUCCESS;
3378 }
3379
3380 VkResult radv_CreateComputePipelines(
3381 VkDevice _device,
3382 VkPipelineCache pipelineCache,
3383 uint32_t count,
3384 const VkComputePipelineCreateInfo* pCreateInfos,
3385 const VkAllocationCallbacks* pAllocator,
3386 VkPipeline* pPipelines)
3387 {
3388 VkResult result = VK_SUCCESS;
3389
3390 unsigned i = 0;
3391 for (; i < count; i++) {
3392 VkResult r;
3393 r = radv_compute_pipeline_create(_device, pipelineCache,
3394 &pCreateInfos[i],
3395 pAllocator, &pPipelines[i]);
3396 if (r != VK_SUCCESS) {
3397 result = r;
3398 pPipelines[i] = VK_NULL_HANDLE;
3399 }
3400 }
3401
3402 return result;
3403 }