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radv/ac: eliminate unused vertex shader outputs. (v2)
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 #include "ac_exp_param.h"
45
46 void radv_shader_variant_destroy(struct radv_device *device,
47 struct radv_shader_variant *variant);
48
49 static const struct nir_shader_compiler_options nir_options = {
50 .vertex_id_zero_based = true,
51 .lower_scmp = true,
52 .lower_flrp32 = true,
53 .lower_fsat = true,
54 .lower_fdiv = true,
55 .lower_pack_snorm_2x16 = true,
56 .lower_pack_snorm_4x8 = true,
57 .lower_pack_unorm_2x16 = true,
58 .lower_pack_unorm_4x8 = true,
59 .lower_unpack_snorm_2x16 = true,
60 .lower_unpack_snorm_4x8 = true,
61 .lower_unpack_unorm_2x16 = true,
62 .lower_unpack_unorm_4x8 = true,
63 .lower_extract_byte = true,
64 .lower_extract_word = true,
65 };
66
67 VkResult radv_CreateShaderModule(
68 VkDevice _device,
69 const VkShaderModuleCreateInfo* pCreateInfo,
70 const VkAllocationCallbacks* pAllocator,
71 VkShaderModule* pShaderModule)
72 {
73 RADV_FROM_HANDLE(radv_device, device, _device);
74 struct radv_shader_module *module;
75
76 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
77 assert(pCreateInfo->flags == 0);
78
79 module = vk_alloc2(&device->alloc, pAllocator,
80 sizeof(*module) + pCreateInfo->codeSize, 8,
81 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
82 if (module == NULL)
83 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
84
85 module->nir = NULL;
86 module->size = pCreateInfo->codeSize;
87 memcpy(module->data, pCreateInfo->pCode, module->size);
88
89 _mesa_sha1_compute(module->data, module->size, module->sha1);
90
91 *pShaderModule = radv_shader_module_to_handle(module);
92
93 return VK_SUCCESS;
94 }
95
96 void radv_DestroyShaderModule(
97 VkDevice _device,
98 VkShaderModule _module,
99 const VkAllocationCallbacks* pAllocator)
100 {
101 RADV_FROM_HANDLE(radv_device, device, _device);
102 RADV_FROM_HANDLE(radv_shader_module, module, _module);
103
104 if (!module)
105 return;
106
107 vk_free2(&device->alloc, pAllocator, module);
108 }
109
110
111 static void
112 radv_pipeline_destroy(struct radv_device *device,
113 struct radv_pipeline *pipeline,
114 const VkAllocationCallbacks* allocator)
115 {
116 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
117 if (pipeline->shaders[i])
118 radv_shader_variant_destroy(device, pipeline->shaders[i]);
119
120 if (pipeline->gs_copy_shader)
121 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
122
123 vk_free2(&device->alloc, allocator, pipeline);
124 }
125
126 void radv_DestroyPipeline(
127 VkDevice _device,
128 VkPipeline _pipeline,
129 const VkAllocationCallbacks* pAllocator)
130 {
131 RADV_FROM_HANDLE(radv_device, device, _device);
132 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
133
134 if (!_pipeline)
135 return;
136
137 radv_pipeline_destroy(device, pipeline, pAllocator);
138 }
139
140
141 static void
142 radv_optimize_nir(struct nir_shader *shader)
143 {
144 bool progress;
145
146 do {
147 progress = false;
148
149 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
150 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
151 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
152
153 NIR_PASS(progress, shader, nir_copy_prop);
154 NIR_PASS(progress, shader, nir_opt_remove_phis);
155 NIR_PASS(progress, shader, nir_opt_dce);
156 NIR_PASS(progress, shader, nir_opt_dead_cf);
157 NIR_PASS(progress, shader, nir_opt_cse);
158 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
159 NIR_PASS(progress, shader, nir_opt_algebraic);
160 NIR_PASS(progress, shader, nir_opt_constant_folding);
161 NIR_PASS(progress, shader, nir_opt_undef);
162 NIR_PASS(progress, shader, nir_opt_conditional_discard);
163 } while (progress);
164 }
165
166 static nir_shader *
167 radv_shader_compile_to_nir(struct radv_device *device,
168 struct radv_shader_module *module,
169 const char *entrypoint_name,
170 gl_shader_stage stage,
171 const VkSpecializationInfo *spec_info,
172 bool dump)
173 {
174 if (strcmp(entrypoint_name, "main") != 0) {
175 radv_finishme("Multiple shaders per module not really supported");
176 }
177
178 nir_shader *nir;
179 nir_function *entry_point;
180 if (module->nir) {
181 /* Some things such as our meta clear/blit code will give us a NIR
182 * shader directly. In that case, we just ignore the SPIR-V entirely
183 * and just use the NIR shader */
184 nir = module->nir;
185 nir->options = &nir_options;
186 nir_validate_shader(nir);
187
188 assert(exec_list_length(&nir->functions) == 1);
189 struct exec_node *node = exec_list_get_head(&nir->functions);
190 entry_point = exec_node_data(nir_function, node, node);
191 } else {
192 uint32_t *spirv = (uint32_t *) module->data;
193 assert(module->size % 4 == 0);
194
195 uint32_t num_spec_entries = 0;
196 struct nir_spirv_specialization *spec_entries = NULL;
197 if (spec_info && spec_info->mapEntryCount > 0) {
198 num_spec_entries = spec_info->mapEntryCount;
199 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
200 for (uint32_t i = 0; i < num_spec_entries; i++) {
201 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
202 const void *data = spec_info->pData + entry.offset;
203 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
204
205 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
206 if (spec_info->dataSize == 8)
207 spec_entries[i].data64 = *(const uint64_t *)data;
208 else
209 spec_entries[i].data32 = *(const uint32_t *)data;
210 }
211 }
212 const struct nir_spirv_supported_extensions supported_ext = {
213 .draw_parameters = true,
214 .float64 = true,
215 .image_read_without_format = true,
216 .image_write_without_format = true,
217 .tessellation = true,
218 };
219 entry_point = spirv_to_nir(spirv, module->size / 4,
220 spec_entries, num_spec_entries,
221 stage, entrypoint_name, &supported_ext, &nir_options);
222 nir = entry_point->shader;
223 assert(nir->stage == stage);
224 nir_validate_shader(nir);
225
226 free(spec_entries);
227
228 /* We have to lower away local constant initializers right before we
229 * inline functions. That way they get properly initialized at the top
230 * of the function and not at the top of its caller.
231 */
232 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
233 NIR_PASS_V(nir, nir_lower_returns);
234 NIR_PASS_V(nir, nir_inline_functions);
235
236 /* Pick off the single entrypoint that we want */
237 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
238 if (func != entry_point)
239 exec_node_remove(&func->node);
240 }
241 assert(exec_list_length(&nir->functions) == 1);
242 entry_point->name = ralloc_strdup(entry_point, "main");
243
244 NIR_PASS_V(nir, nir_remove_dead_variables,
245 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
246
247 /* Now that we've deleted all but the main function, we can go ahead and
248 * lower the rest of the constant initializers.
249 */
250 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
251 NIR_PASS_V(nir, nir_lower_system_values);
252 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
253 }
254
255 /* Vulkan uses the separate-shader linking model */
256 nir->info->separate_shader = true;
257
258 nir_shader_gather_info(nir, entry_point->impl);
259
260 nir_variable_mode indirect_mask = 0;
261 indirect_mask |= nir_var_shader_in;
262 indirect_mask |= nir_var_local;
263
264 nir_lower_indirect_derefs(nir, indirect_mask);
265
266 static const nir_lower_tex_options tex_options = {
267 .lower_txp = ~0,
268 };
269
270 nir_lower_tex(nir, &tex_options);
271
272 nir_lower_vars_to_ssa(nir);
273 nir_lower_var_copies(nir);
274 nir_lower_global_vars_to_local(nir);
275 nir_remove_dead_variables(nir, nir_var_local);
276 radv_optimize_nir(nir);
277
278 if (dump)
279 nir_print_shader(nir, stderr);
280
281 return nir;
282 }
283
284 static const char *radv_get_shader_name(struct radv_shader_variant *var,
285 gl_shader_stage stage)
286 {
287 switch (stage) {
288 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
289 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
290 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
291 case MESA_SHADER_COMPUTE: return "Compute Shader";
292 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
293 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
294 default:
295 return "Unknown shader";
296 };
297
298 }
299 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
300 {
301 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
302 struct radv_shader_variant *var;
303 struct ac_shader_config *conf;
304 int i;
305 FILE *file = stderr;
306 unsigned max_simd_waves = 10;
307 unsigned lds_per_wave = 0;
308
309 for (i = 0; i < MESA_SHADER_STAGES; i++) {
310 if (!pipeline->shaders[i])
311 continue;
312 var = pipeline->shaders[i];
313
314 conf = &var->config;
315
316 if (i == MESA_SHADER_FRAGMENT) {
317 lds_per_wave = conf->lds_size * lds_increment +
318 align(var->info.fs.num_interp * 48, lds_increment);
319 }
320
321 if (conf->num_sgprs) {
322 if (device->physical_device->rad_info.chip_class >= VI)
323 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
324 else
325 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
326 }
327
328 if (conf->num_vgprs)
329 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
330
331 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
332 * that PS can use.
333 */
334 if (lds_per_wave)
335 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
336
337 fprintf(file, "\n%s:\n",
338 radv_get_shader_name(var, i));
339 if (i == MESA_SHADER_FRAGMENT) {
340 fprintf(file, "*** SHADER CONFIG ***\n"
341 "SPI_PS_INPUT_ADDR = 0x%04x\n"
342 "SPI_PS_INPUT_ENA = 0x%04x\n",
343 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
344 }
345 fprintf(file, "*** SHADER STATS ***\n"
346 "SGPRS: %d\n"
347 "VGPRS: %d\n"
348 "Spilled SGPRs: %d\n"
349 "Spilled VGPRs: %d\n"
350 "Code Size: %d bytes\n"
351 "LDS: %d blocks\n"
352 "Scratch: %d bytes per wave\n"
353 "Max Waves: %d\n"
354 "********************\n\n\n",
355 conf->num_sgprs, conf->num_vgprs,
356 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
357 conf->lds_size, conf->scratch_bytes_per_wave,
358 max_simd_waves);
359 }
360 }
361
362 void radv_shader_variant_destroy(struct radv_device *device,
363 struct radv_shader_variant *variant)
364 {
365 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
366 return;
367
368 device->ws->buffer_destroy(variant->bo);
369 free(variant);
370 }
371
372 static void radv_fill_shader_variant(struct radv_device *device,
373 struct radv_shader_variant *variant,
374 struct ac_shader_binary *binary,
375 gl_shader_stage stage)
376 {
377 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
378 unsigned vgpr_comp_cnt = 0;
379
380 if (scratch_enabled && !device->llvm_supports_spill)
381 radv_finishme("shader scratch support only available with LLVM 4.0");
382
383 variant->code_size = binary->code_size;
384 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
385 S_00B12C_SCRATCH_EN(scratch_enabled);
386
387 switch (stage) {
388 case MESA_SHADER_TESS_EVAL:
389 vgpr_comp_cnt = 3;
390 /* fallthrough */
391 case MESA_SHADER_TESS_CTRL:
392 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
393 break;
394 case MESA_SHADER_VERTEX:
395 case MESA_SHADER_GEOMETRY:
396 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
397 break;
398 case MESA_SHADER_FRAGMENT:
399 break;
400 case MESA_SHADER_COMPUTE:
401 variant->rsrc2 |=
402 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
403 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
404 S_00B84C_TG_SIZE_EN(1) |
405 S_00B84C_LDS_SIZE(variant->config.lds_size);
406 break;
407 default:
408 unreachable("unsupported shader type");
409 break;
410 }
411
412 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
413 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
414 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
415 S_00B848_DX10_CLAMP(1) |
416 S_00B848_FLOAT_MODE(variant->config.float_mode);
417
418 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
419 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
420
421 void *ptr = device->ws->buffer_map(variant->bo);
422 memcpy(ptr, binary->code, binary->code_size);
423 device->ws->buffer_unmap(variant->bo);
424
425
426 }
427
428 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
429 struct nir_shader *shader,
430 struct radv_pipeline_layout *layout,
431 const union ac_shader_variant_key *key,
432 void** code_out,
433 unsigned *code_size_out,
434 bool dump)
435 {
436 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
437 enum radeon_family chip_family = device->physical_device->rad_info.family;
438 LLVMTargetMachineRef tm;
439 if (!variant)
440 return NULL;
441
442 struct ac_nir_compiler_options options = {0};
443 options.layout = layout;
444 if (key)
445 options.key = *key;
446
447 struct ac_shader_binary binary;
448
449 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
450 options.family = chip_family;
451 options.chip_class = device->physical_device->rad_info.chip_class;
452 options.supports_spill = device->llvm_supports_spill;
453 tm = ac_create_target_machine(chip_family, options.supports_spill);
454 ac_compile_nir_shader(tm, &binary, &variant->config,
455 &variant->info, shader, &options, dump);
456 LLVMDisposeTargetMachine(tm);
457
458 radv_fill_shader_variant(device, variant, &binary, shader->stage);
459
460 if (code_out) {
461 *code_out = binary.code;
462 *code_size_out = binary.code_size;
463 } else
464 free(binary.code);
465 free(binary.config);
466 free(binary.rodata);
467 free(binary.global_symbol_offsets);
468 free(binary.relocs);
469 free(binary.disasm_string);
470 variant->ref_count = 1;
471 return variant;
472 }
473
474 static struct radv_shader_variant *
475 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
476 struct nir_shader *nir,
477 void** code_out,
478 unsigned *code_size_out,
479 bool dump_shader)
480 {
481 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
482 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
483 LLVMTargetMachineRef tm;
484 if (!variant)
485 return NULL;
486
487 struct ac_nir_compiler_options options = {0};
488 struct ac_shader_binary binary;
489 options.family = chip_family;
490 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
491 options.supports_spill = pipeline->device->llvm_supports_spill;
492 tm = ac_create_target_machine(chip_family, options.supports_spill);
493 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
494 LLVMDisposeTargetMachine(tm);
495
496 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
497
498 if (code_out) {
499 *code_out = binary.code;
500 *code_size_out = binary.code_size;
501 } else
502 free(binary.code);
503 free(binary.config);
504 free(binary.rodata);
505 free(binary.global_symbol_offsets);
506 free(binary.relocs);
507 free(binary.disasm_string);
508 variant->ref_count = 1;
509 return variant;
510 }
511
512 static struct radv_shader_variant *
513 radv_pipeline_compile(struct radv_pipeline *pipeline,
514 struct radv_pipeline_cache *cache,
515 struct radv_shader_module *module,
516 const char *entrypoint,
517 gl_shader_stage stage,
518 const VkSpecializationInfo *spec_info,
519 struct radv_pipeline_layout *layout,
520 const union ac_shader_variant_key *key)
521 {
522 unsigned char sha1[20];
523 unsigned char gs_copy_sha1[20];
524 struct radv_shader_variant *variant;
525 nir_shader *nir;
526 void *code = NULL;
527 unsigned code_size = 0;
528 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
529
530 if (module->nir)
531 _mesa_sha1_compute(module->nir->info->name,
532 strlen(module->nir->info->name),
533 module->sha1);
534
535 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
536 if (stage == MESA_SHADER_GEOMETRY)
537 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
538 layout, key, 1);
539
540 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
541 cache,
542 sha1);
543
544 if (stage == MESA_SHADER_GEOMETRY) {
545 pipeline->gs_copy_shader =
546 radv_create_shader_variant_from_pipeline_cache(
547 pipeline->device,
548 cache,
549 gs_copy_sha1);
550 }
551
552 if (variant &&
553 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
554 return variant;
555
556 nir = radv_shader_compile_to_nir(pipeline->device,
557 module, entrypoint, stage,
558 spec_info, dump);
559 if (nir == NULL)
560 return NULL;
561
562 if (!variant) {
563 variant = radv_shader_variant_create(pipeline->device, nir,
564 layout, key, &code,
565 &code_size, dump);
566 }
567
568 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
569 void *gs_copy_code = NULL;
570 unsigned gs_copy_code_size = 0;
571 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
572 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
573
574 if (pipeline->gs_copy_shader) {
575 pipeline->gs_copy_shader =
576 radv_pipeline_cache_insert_shader(cache,
577 gs_copy_sha1,
578 pipeline->gs_copy_shader,
579 gs_copy_code,
580 gs_copy_code_size);
581 }
582 }
583 if (!module->nir)
584 ralloc_free(nir);
585
586 if (variant)
587 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
588 code, code_size);
589
590 if (code)
591 free(code);
592 return variant;
593 }
594
595 static union ac_shader_variant_key
596 radv_compute_tes_key(bool as_es)
597 {
598 union ac_shader_variant_key key;
599 memset(&key, 0, sizeof(key));
600 key.tes.as_es = as_es;
601 return key;
602 }
603
604 static union ac_shader_variant_key
605 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
606 {
607 union ac_shader_variant_key key;
608 memset(&key, 0, sizeof(key));
609 key.tcs.primitive_mode = primitive_mode;
610 key.tcs.input_vertices = input_vertices;
611 return key;
612 }
613
614 static void
615 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
616 struct radv_pipeline_cache *cache,
617 struct radv_shader_module *tcs_module,
618 struct radv_shader_module *tes_module,
619 const char *tcs_entrypoint,
620 const char *tes_entrypoint,
621 const VkSpecializationInfo *tcs_spec_info,
622 const VkSpecializationInfo *tes_spec_info,
623 struct radv_pipeline_layout *layout,
624 unsigned input_vertices)
625 {
626 unsigned char tcs_sha1[20], tes_sha1[20];
627 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
628 nir_shader *tes_nir, *tcs_nir;
629 void *tes_code = NULL, *tcs_code = NULL;
630 unsigned tes_code_size = 0, tcs_code_size = 0;
631 union ac_shader_variant_key tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline));
632 union ac_shader_variant_key tcs_key;
633 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
634
635 if (tes_module->nir)
636 _mesa_sha1_compute(tes_module->nir->info->name,
637 strlen(tes_module->nir->info->name),
638 tes_module->sha1);
639 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
640
641 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
642 cache,
643 tes_sha1);
644
645 if (tes_variant) {
646 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
647
648 if (tcs_module->nir)
649 _mesa_sha1_compute(tcs_module->nir->info->name,
650 strlen(tcs_module->nir->info->name),
651 tcs_module->sha1);
652
653 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
654
655 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
656 cache,
657 tcs_sha1);
658 }
659
660 if (tcs_variant && tes_variant) {
661 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
662 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
663 return;
664 }
665
666 tes_nir = radv_shader_compile_to_nir(pipeline->device,
667 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
668 tes_spec_info, dump);
669 if (tes_nir == NULL)
670 return;
671
672 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
673 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
674 tcs_spec_info, dump);
675 if (tcs_nir == NULL)
676 return;
677
678 nir_lower_tes_patch_vertices(tes_nir,
679 tcs_nir->info->tess.tcs_vertices_out);
680
681 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
682 layout, &tes_key, &tes_code,
683 &tes_code_size, dump);
684
685 tcs_key = radv_compute_tcs_key(tes_nir->info->tess.primitive_mode, input_vertices);
686 if (tcs_module->nir)
687 _mesa_sha1_compute(tcs_module->nir->info->name,
688 strlen(tcs_module->nir->info->name),
689 tcs_module->sha1);
690
691 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
692
693 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
694 layout, &tcs_key, &tcs_code,
695 &tcs_code_size, dump);
696
697 if (!tes_module->nir)
698 ralloc_free(tes_nir);
699
700 if (!tcs_module->nir)
701 ralloc_free(tcs_nir);
702
703 if (tes_variant)
704 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
705 tes_code, tes_code_size);
706
707 if (tcs_variant)
708 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
709 tcs_code, tcs_code_size);
710
711 if (tes_code)
712 free(tes_code);
713 if (tcs_code)
714 free(tcs_code);
715 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
716 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
717 return;
718 }
719
720 static VkResult
721 radv_pipeline_scratch_init(struct radv_device *device,
722 struct radv_pipeline *pipeline)
723 {
724 unsigned scratch_bytes_per_wave = 0;
725 unsigned max_waves = 0;
726 unsigned min_waves = 1;
727
728 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
729 if (pipeline->shaders[i]) {
730 unsigned max_stage_waves = device->scratch_waves;
731
732 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
733 pipeline->shaders[i]->config.scratch_bytes_per_wave);
734
735 max_stage_waves = MIN2(max_stage_waves,
736 4 * device->physical_device->rad_info.num_good_compute_units *
737 (256 / pipeline->shaders[i]->config.num_vgprs));
738 max_waves = MAX2(max_waves, max_stage_waves);
739 }
740 }
741
742 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
743 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
744 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
745 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
746 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
747 }
748
749 if (scratch_bytes_per_wave)
750 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
751
752 if (scratch_bytes_per_wave && max_waves < min_waves) {
753 /* Not really true at this moment, but will be true on first
754 * execution. Avoid having hanging shaders. */
755 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
756 }
757 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
758 pipeline->max_waves = max_waves;
759 return VK_SUCCESS;
760 }
761
762 static uint32_t si_translate_blend_function(VkBlendOp op)
763 {
764 switch (op) {
765 case VK_BLEND_OP_ADD:
766 return V_028780_COMB_DST_PLUS_SRC;
767 case VK_BLEND_OP_SUBTRACT:
768 return V_028780_COMB_SRC_MINUS_DST;
769 case VK_BLEND_OP_REVERSE_SUBTRACT:
770 return V_028780_COMB_DST_MINUS_SRC;
771 case VK_BLEND_OP_MIN:
772 return V_028780_COMB_MIN_DST_SRC;
773 case VK_BLEND_OP_MAX:
774 return V_028780_COMB_MAX_DST_SRC;
775 default:
776 return 0;
777 }
778 }
779
780 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
781 {
782 switch (factor) {
783 case VK_BLEND_FACTOR_ZERO:
784 return V_028780_BLEND_ZERO;
785 case VK_BLEND_FACTOR_ONE:
786 return V_028780_BLEND_ONE;
787 case VK_BLEND_FACTOR_SRC_COLOR:
788 return V_028780_BLEND_SRC_COLOR;
789 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
790 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
791 case VK_BLEND_FACTOR_DST_COLOR:
792 return V_028780_BLEND_DST_COLOR;
793 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
794 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
795 case VK_BLEND_FACTOR_SRC_ALPHA:
796 return V_028780_BLEND_SRC_ALPHA;
797 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
798 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
799 case VK_BLEND_FACTOR_DST_ALPHA:
800 return V_028780_BLEND_DST_ALPHA;
801 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
802 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
803 case VK_BLEND_FACTOR_CONSTANT_COLOR:
804 return V_028780_BLEND_CONSTANT_COLOR;
805 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
806 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
807 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
808 return V_028780_BLEND_CONSTANT_ALPHA;
809 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
810 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
811 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
812 return V_028780_BLEND_SRC_ALPHA_SATURATE;
813 case VK_BLEND_FACTOR_SRC1_COLOR:
814 return V_028780_BLEND_SRC1_COLOR;
815 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
816 return V_028780_BLEND_INV_SRC1_COLOR;
817 case VK_BLEND_FACTOR_SRC1_ALPHA:
818 return V_028780_BLEND_SRC1_ALPHA;
819 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
820 return V_028780_BLEND_INV_SRC1_ALPHA;
821 default:
822 return 0;
823 }
824 }
825
826 static bool is_dual_src(VkBlendFactor factor)
827 {
828 switch (factor) {
829 case VK_BLEND_FACTOR_SRC1_COLOR:
830 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
831 case VK_BLEND_FACTOR_SRC1_ALPHA:
832 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
833 return true;
834 default:
835 return false;
836 }
837 }
838
839 static unsigned si_choose_spi_color_format(VkFormat vk_format,
840 bool blend_enable,
841 bool blend_need_alpha)
842 {
843 const struct vk_format_description *desc = vk_format_description(vk_format);
844 unsigned format, ntype, swap;
845
846 /* Alpha is needed for alpha-to-coverage.
847 * Blending may be with or without alpha.
848 */
849 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
850 unsigned alpha = 0; /* exports alpha, but may not support blending */
851 unsigned blend = 0; /* supports blending, but may not export alpha */
852 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
853
854 format = radv_translate_colorformat(vk_format);
855 ntype = radv_translate_color_numformat(vk_format, desc,
856 vk_format_get_first_non_void_channel(vk_format));
857 swap = radv_translate_colorswap(vk_format, false);
858
859 /* Choose the SPI color formats. These are required values for Stoney/RB+.
860 * Other chips have multiple choices, though they are not necessarily better.
861 */
862 switch (format) {
863 case V_028C70_COLOR_5_6_5:
864 case V_028C70_COLOR_1_5_5_5:
865 case V_028C70_COLOR_5_5_5_1:
866 case V_028C70_COLOR_4_4_4_4:
867 case V_028C70_COLOR_10_11_11:
868 case V_028C70_COLOR_11_11_10:
869 case V_028C70_COLOR_8:
870 case V_028C70_COLOR_8_8:
871 case V_028C70_COLOR_8_8_8_8:
872 case V_028C70_COLOR_10_10_10_2:
873 case V_028C70_COLOR_2_10_10_10:
874 if (ntype == V_028C70_NUMBER_UINT)
875 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
876 else if (ntype == V_028C70_NUMBER_SINT)
877 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
878 else
879 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
880 break;
881
882 case V_028C70_COLOR_16:
883 case V_028C70_COLOR_16_16:
884 case V_028C70_COLOR_16_16_16_16:
885 if (ntype == V_028C70_NUMBER_UNORM ||
886 ntype == V_028C70_NUMBER_SNORM) {
887 /* UNORM16 and SNORM16 don't support blending */
888 if (ntype == V_028C70_NUMBER_UNORM)
889 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
890 else
891 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
892
893 /* Use 32 bits per channel for blending. */
894 if (format == V_028C70_COLOR_16) {
895 if (swap == V_028C70_SWAP_STD) { /* R */
896 blend = V_028714_SPI_SHADER_32_R;
897 blend_alpha = V_028714_SPI_SHADER_32_AR;
898 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
899 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
900 else
901 assert(0);
902 } else if (format == V_028C70_COLOR_16_16) {
903 if (swap == V_028C70_SWAP_STD) { /* RG */
904 blend = V_028714_SPI_SHADER_32_GR;
905 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
906 } else if (swap == V_028C70_SWAP_ALT) /* RA */
907 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
908 else
909 assert(0);
910 } else /* 16_16_16_16 */
911 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
912 } else if (ntype == V_028C70_NUMBER_UINT)
913 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
914 else if (ntype == V_028C70_NUMBER_SINT)
915 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
916 else if (ntype == V_028C70_NUMBER_FLOAT)
917 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
918 else
919 assert(0);
920 break;
921
922 case V_028C70_COLOR_32:
923 if (swap == V_028C70_SWAP_STD) { /* R */
924 blend = normal = V_028714_SPI_SHADER_32_R;
925 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
926 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
927 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
928 else
929 assert(0);
930 break;
931
932 case V_028C70_COLOR_32_32:
933 if (swap == V_028C70_SWAP_STD) { /* RG */
934 blend = normal = V_028714_SPI_SHADER_32_GR;
935 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
936 } else if (swap == V_028C70_SWAP_ALT) /* RA */
937 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
938 else
939 assert(0);
940 break;
941
942 case V_028C70_COLOR_32_32_32_32:
943 case V_028C70_COLOR_8_24:
944 case V_028C70_COLOR_24_8:
945 case V_028C70_COLOR_X24_8_32_FLOAT:
946 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
947 break;
948
949 default:
950 unreachable("unhandled blend format");
951 }
952
953 if (blend_enable && blend_need_alpha)
954 return blend_alpha;
955 else if(blend_need_alpha)
956 return alpha;
957 else if(blend_enable)
958 return blend;
959 else
960 return normal;
961 }
962
963 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
964 {
965 unsigned i, cb_shader_mask = 0;
966
967 for (i = 0; i < 8; i++) {
968 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
969 case V_028714_SPI_SHADER_ZERO:
970 break;
971 case V_028714_SPI_SHADER_32_R:
972 cb_shader_mask |= 0x1 << (i * 4);
973 break;
974 case V_028714_SPI_SHADER_32_GR:
975 cb_shader_mask |= 0x3 << (i * 4);
976 break;
977 case V_028714_SPI_SHADER_32_AR:
978 cb_shader_mask |= 0x9 << (i * 4);
979 break;
980 case V_028714_SPI_SHADER_FP16_ABGR:
981 case V_028714_SPI_SHADER_UNORM16_ABGR:
982 case V_028714_SPI_SHADER_SNORM16_ABGR:
983 case V_028714_SPI_SHADER_UINT16_ABGR:
984 case V_028714_SPI_SHADER_SINT16_ABGR:
985 case V_028714_SPI_SHADER_32_ABGR:
986 cb_shader_mask |= 0xf << (i * 4);
987 break;
988 default:
989 assert(0);
990 }
991 }
992 return cb_shader_mask;
993 }
994
995 static void
996 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
997 const VkGraphicsPipelineCreateInfo *pCreateInfo,
998 uint32_t blend_enable,
999 uint32_t blend_need_alpha,
1000 bool single_cb_enable,
1001 bool blend_mrt0_is_dual_src)
1002 {
1003 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1004 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1005 struct radv_blend_state *blend = &pipeline->graphics.blend;
1006 unsigned col_format = 0;
1007
1008 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1009 struct radv_render_pass_attachment *attachment;
1010 unsigned cf;
1011
1012 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1013
1014 cf = si_choose_spi_color_format(attachment->format,
1015 blend_enable & (1 << i),
1016 blend_need_alpha & (1 << i));
1017
1018 col_format |= cf << (4 * i);
1019 }
1020
1021 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1022
1023 if (blend_mrt0_is_dual_src)
1024 col_format |= (col_format & 0xf) << 4;
1025 blend->spi_shader_col_format = col_format;
1026 }
1027
1028 static bool
1029 format_is_int8(VkFormat format)
1030 {
1031 const struct vk_format_description *desc = vk_format_description(format);
1032 int channel = vk_format_get_first_non_void_channel(format);
1033
1034 return channel >= 0 && desc->channel[channel].pure_integer &&
1035 desc->channel[channel].size == 8;
1036 }
1037
1038 unsigned radv_format_meta_fs_key(VkFormat format)
1039 {
1040 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1041 bool is_int8 = format_is_int8(format);
1042
1043 return col_format + (is_int8 ? 3 : 0);
1044 }
1045
1046 static unsigned
1047 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1048 {
1049 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1050 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1051 unsigned is_int8 = 0;
1052
1053 for (unsigned i = 0; i < subpass->color_count; ++i) {
1054 struct radv_render_pass_attachment *attachment;
1055
1056 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1057
1058 if (format_is_int8(attachment->format))
1059 is_int8 |= 1 << i;
1060 }
1061
1062 return is_int8;
1063 }
1064
1065 static void
1066 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1067 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1068 const struct radv_graphics_pipeline_create_info *extra)
1069 {
1070 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1071 struct radv_blend_state *blend = &pipeline->graphics.blend;
1072 unsigned mode = V_028808_CB_NORMAL;
1073 uint32_t blend_enable = 0, blend_need_alpha = 0;
1074 bool blend_mrt0_is_dual_src = false;
1075 int i;
1076 bool single_cb_enable = false;
1077
1078 if (!vkblend)
1079 return;
1080
1081 if (extra && extra->custom_blend_mode) {
1082 single_cb_enable = true;
1083 mode = extra->custom_blend_mode;
1084 }
1085 blend->cb_color_control = 0;
1086 if (vkblend->logicOpEnable)
1087 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1088 else
1089 blend->cb_color_control |= S_028808_ROP3(0xcc);
1090
1091 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1092 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1093 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1094 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1095
1096 blend->cb_target_mask = 0;
1097 for (i = 0; i < vkblend->attachmentCount; i++) {
1098 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1099 unsigned blend_cntl = 0;
1100 VkBlendOp eqRGB = att->colorBlendOp;
1101 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1102 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1103 VkBlendOp eqA = att->alphaBlendOp;
1104 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1105 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1106
1107 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1108
1109 if (!att->colorWriteMask)
1110 continue;
1111
1112 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1113 if (!att->blendEnable) {
1114 blend->cb_blend_control[i] = blend_cntl;
1115 continue;
1116 }
1117
1118 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1119 if (i == 0)
1120 blend_mrt0_is_dual_src = true;
1121
1122 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1123 srcRGB = VK_BLEND_FACTOR_ONE;
1124 dstRGB = VK_BLEND_FACTOR_ONE;
1125 }
1126 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1127 srcA = VK_BLEND_FACTOR_ONE;
1128 dstA = VK_BLEND_FACTOR_ONE;
1129 }
1130
1131 blend_cntl |= S_028780_ENABLE(1);
1132
1133 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1134 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1135 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1136 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1137 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1138 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1139 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1140 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1141 }
1142 blend->cb_blend_control[i] = blend_cntl;
1143
1144 blend_enable |= 1 << i;
1145
1146 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1147 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1148 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1149 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1150 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1151 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1152 blend_need_alpha |= 1 << i;
1153 }
1154 for (i = vkblend->attachmentCount; i < 8; i++)
1155 blend->cb_blend_control[i] = 0;
1156
1157 if (blend->cb_target_mask)
1158 blend->cb_color_control |= S_028808_MODE(mode);
1159 else
1160 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1161
1162 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1163 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1164 }
1165
1166 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1167 {
1168 switch (op) {
1169 case VK_STENCIL_OP_KEEP:
1170 return V_02842C_STENCIL_KEEP;
1171 case VK_STENCIL_OP_ZERO:
1172 return V_02842C_STENCIL_ZERO;
1173 case VK_STENCIL_OP_REPLACE:
1174 return V_02842C_STENCIL_REPLACE_TEST;
1175 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1176 return V_02842C_STENCIL_ADD_CLAMP;
1177 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1178 return V_02842C_STENCIL_SUB_CLAMP;
1179 case VK_STENCIL_OP_INVERT:
1180 return V_02842C_STENCIL_INVERT;
1181 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1182 return V_02842C_STENCIL_ADD_WRAP;
1183 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1184 return V_02842C_STENCIL_SUB_WRAP;
1185 default:
1186 return 0;
1187 }
1188 }
1189 static void
1190 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1191 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1192 const struct radv_graphics_pipeline_create_info *extra)
1193 {
1194 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1195 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1196
1197 memset(ds, 0, sizeof(*ds));
1198 if (!vkds)
1199 return;
1200 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1201 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1202 S_028800_ZFUNC(vkds->depthCompareOp) |
1203 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1204
1205 if (vkds->stencilTestEnable) {
1206 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1207 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1208 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1209 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1210 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1211
1212 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1213 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1214 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1215 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1216 }
1217
1218 if (extra) {
1219
1220 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1221 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1222
1223 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1224 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1225 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1226 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1227 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1228 }
1229 }
1230
1231 static uint32_t si_translate_fill(VkPolygonMode func)
1232 {
1233 switch(func) {
1234 case VK_POLYGON_MODE_FILL:
1235 return V_028814_X_DRAW_TRIANGLES;
1236 case VK_POLYGON_MODE_LINE:
1237 return V_028814_X_DRAW_LINES;
1238 case VK_POLYGON_MODE_POINT:
1239 return V_028814_X_DRAW_POINTS;
1240 default:
1241 assert(0);
1242 return V_028814_X_DRAW_POINTS;
1243 }
1244 }
1245 static void
1246 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1247 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1248 {
1249 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1250 struct radv_raster_state *raster = &pipeline->graphics.raster;
1251
1252 memset(raster, 0, sizeof(*raster));
1253
1254 raster->spi_interp_control =
1255 S_0286D4_FLAT_SHADE_ENA(1) |
1256 S_0286D4_PNT_SPRITE_ENA(1) |
1257 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1258 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1259 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1260 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1261 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1262
1263
1264 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1265 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1266 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1267 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1268 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1269 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1270
1271 raster->pa_su_vtx_cntl =
1272 S_028BE4_PIX_CENTER(1) | // TODO verify
1273 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1274 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1275
1276 raster->pa_su_sc_mode_cntl =
1277 S_028814_FACE(vkraster->frontFace) |
1278 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1279 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1280 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1281 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1282 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1283 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1284 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1285 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1286
1287 }
1288
1289 static void
1290 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1291 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1292 {
1293 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1294 struct radv_blend_state *blend = &pipeline->graphics.blend;
1295 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1296 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1297 int ps_iter_samples = 1;
1298 uint32_t mask = 0xffff;
1299
1300 if (vkms)
1301 ms->num_samples = vkms->rasterizationSamples;
1302 else
1303 ms->num_samples = 1;
1304
1305 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1306 ps_iter_samples = ms->num_samples;
1307 }
1308
1309 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1310 ms->pa_sc_aa_config = 0;
1311 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1312 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1313 ms->pa_sc_mode_cntl_1 =
1314 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1315 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1316 /* always 1: */
1317 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1318 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1319 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1320 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1321 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1322 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1323
1324 if (ms->num_samples > 1) {
1325 unsigned log_samples = util_logbase2(ms->num_samples);
1326 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1327 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1328 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1329 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1330 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1331 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1332 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1333 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1334 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1335 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1336 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1337 }
1338
1339 if (vkms) {
1340 if (vkms->alphaToCoverageEnable)
1341 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1342
1343 if (vkms->pSampleMask)
1344 mask = vkms->pSampleMask[0] & 0xffff;
1345 }
1346
1347 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1348 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1349 }
1350
1351 static bool
1352 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1353 {
1354 switch (topology) {
1355 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1356 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1357 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1358 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1359 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1360 return false;
1361 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1362 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1363 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1364 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1365 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1366 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1367 return true;
1368 default:
1369 unreachable("unhandled primitive type");
1370 }
1371 }
1372
1373 static uint32_t
1374 si_translate_prim(enum VkPrimitiveTopology topology)
1375 {
1376 switch (topology) {
1377 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1378 return V_008958_DI_PT_POINTLIST;
1379 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1380 return V_008958_DI_PT_LINELIST;
1381 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1382 return V_008958_DI_PT_LINESTRIP;
1383 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1384 return V_008958_DI_PT_TRILIST;
1385 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1386 return V_008958_DI_PT_TRISTRIP;
1387 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1388 return V_008958_DI_PT_TRIFAN;
1389 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1390 return V_008958_DI_PT_LINELIST_ADJ;
1391 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1392 return V_008958_DI_PT_LINESTRIP_ADJ;
1393 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1394 return V_008958_DI_PT_TRILIST_ADJ;
1395 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1396 return V_008958_DI_PT_TRISTRIP_ADJ;
1397 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1398 return V_008958_DI_PT_PATCH;
1399 default:
1400 assert(0);
1401 return 0;
1402 }
1403 }
1404
1405 static uint32_t
1406 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1407 {
1408 switch (gl_prim) {
1409 case 0: /* GL_POINTS */
1410 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1411 case 1: /* GL_LINES */
1412 case 3: /* GL_LINE_STRIP */
1413 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1414 case 0x8E7A: /* GL_ISOLINES */
1415 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1416
1417 case 4: /* GL_TRIANGLES */
1418 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1419 case 5: /* GL_TRIANGLE_STRIP */
1420 case 7: /* GL_QUADS */
1421 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1422 default:
1423 assert(0);
1424 return 0;
1425 }
1426 }
1427
1428 static uint32_t
1429 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1430 {
1431 switch (topology) {
1432 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1433 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1434 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1435 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1436 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1437 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1438 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1439 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1440 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1441 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1442 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1443 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1444 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1445 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1446 default:
1447 assert(0);
1448 return 0;
1449 }
1450 }
1451
1452 static unsigned si_map_swizzle(unsigned swizzle)
1453 {
1454 switch (swizzle) {
1455 case VK_SWIZZLE_Y:
1456 return V_008F0C_SQ_SEL_Y;
1457 case VK_SWIZZLE_Z:
1458 return V_008F0C_SQ_SEL_Z;
1459 case VK_SWIZZLE_W:
1460 return V_008F0C_SQ_SEL_W;
1461 case VK_SWIZZLE_0:
1462 return V_008F0C_SQ_SEL_0;
1463 case VK_SWIZZLE_1:
1464 return V_008F0C_SQ_SEL_1;
1465 default: /* VK_SWIZZLE_X */
1466 return V_008F0C_SQ_SEL_X;
1467 }
1468 }
1469
1470 static void
1471 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1472 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1473 {
1474 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1475 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1476 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1477
1478 pipeline->dynamic_state = default_dynamic_state;
1479
1480 if (pCreateInfo->pDynamicState) {
1481 /* Remove all of the states that are marked as dynamic */
1482 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1483 for (uint32_t s = 0; s < count; s++)
1484 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1485 }
1486
1487 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1488
1489 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1490 *
1491 * pViewportState is [...] NULL if the pipeline
1492 * has rasterization disabled.
1493 */
1494 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1495 assert(pCreateInfo->pViewportState);
1496
1497 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1498 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1499 typed_memcpy(dynamic->viewport.viewports,
1500 pCreateInfo->pViewportState->pViewports,
1501 pCreateInfo->pViewportState->viewportCount);
1502 }
1503
1504 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1505 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1506 typed_memcpy(dynamic->scissor.scissors,
1507 pCreateInfo->pViewportState->pScissors,
1508 pCreateInfo->pViewportState->scissorCount);
1509 }
1510 }
1511
1512 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1513 assert(pCreateInfo->pRasterizationState);
1514 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1515 }
1516
1517 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1518 assert(pCreateInfo->pRasterizationState);
1519 dynamic->depth_bias.bias =
1520 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1521 dynamic->depth_bias.clamp =
1522 pCreateInfo->pRasterizationState->depthBiasClamp;
1523 dynamic->depth_bias.slope =
1524 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1525 }
1526
1527 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1528 *
1529 * pColorBlendState is [...] NULL if the pipeline has rasterization
1530 * disabled or if the subpass of the render pass the pipeline is
1531 * created against does not use any color attachments.
1532 */
1533 bool uses_color_att = false;
1534 for (unsigned i = 0; i < subpass->color_count; ++i) {
1535 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1536 uses_color_att = true;
1537 break;
1538 }
1539 }
1540
1541 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1542 assert(pCreateInfo->pColorBlendState);
1543 typed_memcpy(dynamic->blend_constants,
1544 pCreateInfo->pColorBlendState->blendConstants, 4);
1545 }
1546
1547 /* If there is no depthstencil attachment, then don't read
1548 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1549 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1550 * no need to override the depthstencil defaults in
1551 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1552 *
1553 * Section 9.2 of the Vulkan 1.0.15 spec says:
1554 *
1555 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1556 * disabled or if the subpass of the render pass the pipeline is created
1557 * against does not use a depth/stencil attachment.
1558 */
1559 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1560 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1561 assert(pCreateInfo->pDepthStencilState);
1562
1563 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1564 dynamic->depth_bounds.min =
1565 pCreateInfo->pDepthStencilState->minDepthBounds;
1566 dynamic->depth_bounds.max =
1567 pCreateInfo->pDepthStencilState->maxDepthBounds;
1568 }
1569
1570 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1571 dynamic->stencil_compare_mask.front =
1572 pCreateInfo->pDepthStencilState->front.compareMask;
1573 dynamic->stencil_compare_mask.back =
1574 pCreateInfo->pDepthStencilState->back.compareMask;
1575 }
1576
1577 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1578 dynamic->stencil_write_mask.front =
1579 pCreateInfo->pDepthStencilState->front.writeMask;
1580 dynamic->stencil_write_mask.back =
1581 pCreateInfo->pDepthStencilState->back.writeMask;
1582 }
1583
1584 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1585 dynamic->stencil_reference.front =
1586 pCreateInfo->pDepthStencilState->front.reference;
1587 dynamic->stencil_reference.back =
1588 pCreateInfo->pDepthStencilState->back.reference;
1589 }
1590 }
1591
1592 pipeline->dynamic_state_mask = states;
1593 }
1594
1595 static union ac_shader_variant_key
1596 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls)
1597 {
1598 union ac_shader_variant_key key;
1599 const VkPipelineVertexInputStateCreateInfo *input_state =
1600 pCreateInfo->pVertexInputState;
1601
1602 memset(&key, 0, sizeof(key));
1603 key.vs.instance_rate_inputs = 0;
1604 key.vs.as_es = as_es;
1605 key.vs.as_ls = as_ls;
1606
1607 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1608 unsigned binding;
1609 binding = input_state->pVertexAttributeDescriptions[i].binding;
1610 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1611 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1612 }
1613 return key;
1614 }
1615
1616 static void
1617 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1618 {
1619 struct radv_device *device = pipeline->device;
1620 unsigned num_se = device->physical_device->rad_info.max_se;
1621 unsigned wave_size = 64;
1622 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1623 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1624 unsigned alignment = 256 * num_se;
1625 /* The maximum size is 63.999 MB per SE. */
1626 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1627 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1628 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1629 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1630 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1631
1632 /* Calculate the minimum size. */
1633 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1634 wave_size, alignment);
1635 /* These are recommended sizes, not minimum sizes. */
1636 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1637 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1638 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1639 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1640
1641 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1642 esgs_ring_size = align(esgs_ring_size, alignment);
1643 gsvs_ring_size = align(gsvs_ring_size, alignment);
1644
1645 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1646 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1647 }
1648
1649 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1650 unsigned *lds_size)
1651 {
1652 /* SPI barrier management bug:
1653 * Make sure we have at least 4k of LDS in use to avoid the bug.
1654 * It applies to workgroup sizes of more than one wavefront.
1655 */
1656 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1657 device->physical_device->rad_info.family == CHIP_KABINI ||
1658 device->physical_device->rad_info.family == CHIP_MULLINS)
1659 *lds_size = MAX2(*lds_size, 8);
1660 }
1661
1662 static void
1663 calculate_tess_state(struct radv_pipeline *pipeline,
1664 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1665 {
1666 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1667 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1668 unsigned num_tcs_patch_outputs;
1669 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1670 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1671 unsigned lds_size, hardware_lds_size;
1672 unsigned perpatch_output_offset;
1673 unsigned num_patches;
1674 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1675
1676 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1677 * are laid out in LDS. */
1678 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1679
1680 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1681 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1682 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1683
1684 /* Ensure that we only need one wave per SIMD so we don't need to check
1685 * resource usage. Also ensures that the number of tcs in and out
1686 * vertices per threadgroup are at most 256.
1687 */
1688 input_vertex_size = num_tcs_inputs * 16;
1689 output_vertex_size = num_tcs_outputs * 16;
1690
1691 input_patch_size = num_tcs_input_cp * input_vertex_size;
1692
1693 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1694 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1695 /* Ensure that we only need one wave per SIMD so we don't need to check
1696 * resource usage. Also ensures that the number of tcs in and out
1697 * vertices per threadgroup are at most 256.
1698 */
1699 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1700
1701 /* Make sure that the data fits in LDS. This assumes the shaders only
1702 * use LDS for the inputs and outputs.
1703 */
1704 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1705 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1706
1707 /* Make sure the output data fits in the offchip buffer */
1708 num_patches = MIN2(num_patches,
1709 (pipeline->device->tess_offchip_block_dw_size * 4) /
1710 output_patch_size);
1711
1712 /* Not necessary for correctness, but improves performance. The
1713 * specific value is taken from the proprietary driver.
1714 */
1715 num_patches = MIN2(num_patches, 40);
1716
1717 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1718 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1719 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1720 num_patches = MIN2(num_patches, one_wave);
1721 }
1722
1723 output_patch0_offset = input_patch_size * num_patches;
1724 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1725
1726 lds_size = output_patch0_offset + output_patch_size * num_patches;
1727
1728 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1729 assert(lds_size <= 65536);
1730 lds_size = align(lds_size, 512) / 512;
1731 } else {
1732 assert(lds_size <= 32768);
1733 lds_size = align(lds_size, 256) / 256;
1734 }
1735 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1736
1737 tess->lds_size = lds_size;
1738
1739 tess->tcs_in_layout = (input_patch_size / 4) |
1740 ((input_vertex_size / 4) << 13);
1741 tess->tcs_out_layout = (output_patch_size / 4) |
1742 ((output_vertex_size / 4) << 13);
1743 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1744 ((perpatch_output_offset / 16) << 16);
1745 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1746 (num_tcs_output_cp << 9) | num_patches;
1747
1748 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1749 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1750 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1751 tess->num_patches = num_patches;
1752 tess->num_tcs_input_cp = num_tcs_input_cp;
1753
1754 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1755 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1756
1757 switch (tes->info.tes.primitive_mode) {
1758 case GL_TRIANGLES:
1759 type = V_028B6C_TESS_TRIANGLE;
1760 break;
1761 case GL_QUADS:
1762 type = V_028B6C_TESS_QUAD;
1763 break;
1764 case GL_ISOLINES:
1765 type = V_028B6C_TESS_ISOLINE;
1766 break;
1767 }
1768
1769 switch (tes->info.tes.spacing) {
1770 case TESS_SPACING_EQUAL:
1771 partitioning = V_028B6C_PART_INTEGER;
1772 break;
1773 case TESS_SPACING_FRACTIONAL_ODD:
1774 partitioning = V_028B6C_PART_FRAC_ODD;
1775 break;
1776 case TESS_SPACING_FRACTIONAL_EVEN:
1777 partitioning = V_028B6C_PART_FRAC_EVEN;
1778 break;
1779 default:
1780 break;
1781 }
1782
1783 if (tes->info.tes.point_mode)
1784 topology = V_028B6C_OUTPUT_POINT;
1785 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1786 topology = V_028B6C_OUTPUT_LINE;
1787 else if (tes->info.tes.ccw)
1788 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1789 else
1790 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1791
1792 if (pipeline->device->has_distributed_tess) {
1793 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1794 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1795 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1796 else
1797 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1798 } else
1799 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1800
1801 tess->tf_param = S_028B6C_TYPE(type) |
1802 S_028B6C_PARTITIONING(partitioning) |
1803 S_028B6C_TOPOLOGY(topology) |
1804 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1805 }
1806
1807 static const struct radv_prim_vertex_count prim_size_table[] = {
1808 [V_008958_DI_PT_NONE] = {0, 0},
1809 [V_008958_DI_PT_POINTLIST] = {1, 1},
1810 [V_008958_DI_PT_LINELIST] = {2, 2},
1811 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1812 [V_008958_DI_PT_TRILIST] = {3, 3},
1813 [V_008958_DI_PT_TRIFAN] = {3, 1},
1814 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1815 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1816 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1817 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1818 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1819 [V_008958_DI_PT_RECTLIST] = {3, 3},
1820 [V_008958_DI_PT_LINELOOP] = {2, 1},
1821 [V_008958_DI_PT_POLYGON] = {3, 1},
1822 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1823 };
1824
1825 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1826 {
1827 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1828 unsigned cut_mode;
1829
1830 if (gs_max_vert_out <= 128) {
1831 cut_mode = V_028A40_GS_CUT_128;
1832 } else if (gs_max_vert_out <= 256) {
1833 cut_mode = V_028A40_GS_CUT_256;
1834 } else if (gs_max_vert_out <= 512) {
1835 cut_mode = V_028A40_GS_CUT_512;
1836 } else {
1837 assert(gs_max_vert_out <= 1024);
1838 cut_mode = V_028A40_GS_CUT_1024;
1839 }
1840
1841 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1842 S_028A40_CUT_MODE(cut_mode)|
1843 S_028A40_ES_WRITE_OPTIMIZE(1) |
1844 S_028A40_GS_WRITE_OPTIMIZE(1);
1845 }
1846
1847 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1848 {
1849 struct radv_shader_variant *vs;
1850 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1851
1852 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1853
1854 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1855 clip_dist_mask = outinfo->clip_dist_mask;
1856 cull_dist_mask = outinfo->cull_dist_mask;
1857 total_mask = clip_dist_mask | cull_dist_mask;
1858
1859 bool misc_vec_ena = outinfo->writes_pointsize ||
1860 outinfo->writes_layer ||
1861 outinfo->writes_viewport_index;
1862 pipeline->graphics.pa_cl_vs_out_cntl =
1863 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1864 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1865 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1866 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1867 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1868 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1869 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1870 cull_dist_mask << 8 |
1871 clip_dist_mask;
1872
1873 }
1874
1875 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1876 {
1877 uint32_t ps_input_cntl;
1878 if (offset <= AC_EXP_PARAM_OFFSET_31)
1879 ps_input_cntl = S_028644_OFFSET(offset);
1880 else {
1881 /* The input is a DEFAULT_VAL constant. */
1882 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1883 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1884 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1885 ps_input_cntl = S_028644_OFFSET(0x20) |
1886 S_028644_DEFAULT_VAL(offset);
1887 }
1888 if (flat_shade)
1889 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1890 return ps_input_cntl;
1891 }
1892
1893 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1894 {
1895 struct radv_shader_variant *ps, *vs;
1896 struct ac_vs_output_info *outinfo;
1897
1898 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1899 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1900
1901 outinfo = &vs->info.vs.outinfo;
1902
1903 unsigned ps_offset = 0;
1904
1905 if (ps->info.fs.prim_id_input) {
1906 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1907 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1908 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1909 ++ps_offset;
1910 }
1911 }
1912
1913 if (ps->info.fs.layer_input) {
1914 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1915 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1916 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1917 ++ps_offset;
1918 }
1919 }
1920
1921 if (ps->info.fs.has_pcoord) {
1922 unsigned val;
1923 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1924 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1925 ps_offset++;
1926 }
1927
1928 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1929 unsigned vs_offset;
1930 bool flat_shade;
1931 if (!(ps->info.fs.input_mask & (1u << i)))
1932 continue;
1933
1934 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1935 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1936 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1937 ++ps_offset;
1938 continue;
1939 }
1940
1941 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1942
1943 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1944 ++ps_offset;
1945 }
1946
1947 pipeline->graphics.ps_input_cntl_num = ps_offset;
1948 }
1949
1950 VkResult
1951 radv_pipeline_init(struct radv_pipeline *pipeline,
1952 struct radv_device *device,
1953 struct radv_pipeline_cache *cache,
1954 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1955 const struct radv_graphics_pipeline_create_info *extra,
1956 const VkAllocationCallbacks *alloc)
1957 {
1958 struct radv_shader_module fs_m = {0};
1959 VkResult result;
1960
1961 if (alloc == NULL)
1962 alloc = &device->alloc;
1963
1964 pipeline->device = device;
1965 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1966
1967 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1968 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1969 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1970 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1971 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1972 pStages[stage] = &pCreateInfo->pStages[i];
1973 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1974 }
1975
1976 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1977
1978 if (modules[MESA_SHADER_VERTEX]) {
1979 bool as_es = false;
1980 bool as_ls = false;
1981 if (modules[MESA_SHADER_TESS_CTRL])
1982 as_ls = true;
1983 else if (modules[MESA_SHADER_GEOMETRY])
1984 as_es = true;
1985 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls);
1986
1987 pipeline->shaders[MESA_SHADER_VERTEX] =
1988 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1989 pStages[MESA_SHADER_VERTEX]->pName,
1990 MESA_SHADER_VERTEX,
1991 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1992 pipeline->layout, &key);
1993
1994 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1995 }
1996
1997 if (modules[MESA_SHADER_GEOMETRY]) {
1998 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false);
1999
2000 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2001 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2002 pStages[MESA_SHADER_GEOMETRY]->pName,
2003 MESA_SHADER_GEOMETRY,
2004 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2005 pipeline->layout, &key);
2006
2007 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2008
2009 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2010 } else
2011 pipeline->graphics.vgt_gs_mode = 0;
2012
2013 if (modules[MESA_SHADER_TESS_EVAL]) {
2014 assert(modules[MESA_SHADER_TESS_CTRL]);
2015
2016 radv_tess_pipeline_compile(pipeline,
2017 cache,
2018 modules[MESA_SHADER_TESS_CTRL],
2019 modules[MESA_SHADER_TESS_EVAL],
2020 pStages[MESA_SHADER_TESS_CTRL]->pName,
2021 pStages[MESA_SHADER_TESS_EVAL]->pName,
2022 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2023 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2024 pipeline->layout,
2025 pCreateInfo->pTessellationState->patchControlPoints);
2026 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2027 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2028 }
2029
2030 if (!modules[MESA_SHADER_FRAGMENT]) {
2031 nir_builder fs_b;
2032 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2033 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
2034 fs_m.nir = fs_b.shader;
2035 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2036 }
2037
2038 if (modules[MESA_SHADER_FRAGMENT]) {
2039 union ac_shader_variant_key key;
2040 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2041 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
2042
2043 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2044
2045 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2046 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2047 stage ? stage->pName : "main",
2048 MESA_SHADER_FRAGMENT,
2049 stage ? stage->pSpecializationInfo : NULL,
2050 pipeline->layout, &key);
2051 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2052 }
2053
2054 if (fs_m.nir)
2055 ralloc_free(fs_m.nir);
2056
2057 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2058 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2059 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2060 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2061 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2062
2063 if (radv_pipeline_has_gs(pipeline)) {
2064 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2065 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2066 } else {
2067 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2068 }
2069 if (extra && extra->use_rectlist) {
2070 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2071 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2072 pipeline->graphics.can_use_guardband = true;
2073 }
2074 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2075 /* prim vertex count will need TESS changes */
2076 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2077
2078 /* Ensure that some export memory is always allocated, for two reasons:
2079 *
2080 * 1) Correctness: The hardware ignores the EXEC mask if no export
2081 * memory is allocated, so KILL and alpha test do not work correctly
2082 * without this.
2083 * 2) Performance: Every shader needs at least a NULL export, even when
2084 * it writes no color/depth output. The NULL export instruction
2085 * stalls without this setting.
2086 *
2087 * Don't add this to CB_SHADER_MASK.
2088 */
2089 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2090 if (!pipeline->graphics.blend.spi_shader_col_format) {
2091 if (!ps->info.fs.writes_z &&
2092 !ps->info.fs.writes_stencil &&
2093 !ps->info.fs.writes_sample_mask)
2094 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2095 }
2096
2097 unsigned z_order;
2098 pipeline->graphics.db_shader_control = 0;
2099 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2100 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2101 else
2102 z_order = V_02880C_LATE_Z;
2103
2104 pipeline->graphics.db_shader_control =
2105 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2106 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2107 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2108 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2109 S_02880C_Z_ORDER(z_order) |
2110 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2111 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2112 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2113
2114 pipeline->graphics.shader_z_format =
2115 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2116 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2117 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2118 V_028710_SPI_SHADER_ZERO;
2119
2120 calculate_pa_cl_vs_out_cntl(pipeline);
2121 calculate_ps_inputs(pipeline);
2122
2123 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2124 if (pipeline->shaders[i]) {
2125 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2126 }
2127 }
2128
2129 uint32_t stages = 0;
2130 if (radv_pipeline_has_tess(pipeline)) {
2131 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2132 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2133
2134 if (radv_pipeline_has_gs(pipeline))
2135 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2136 S_028B54_GS_EN(1) |
2137 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2138 else
2139 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2140 } else if (radv_pipeline_has_gs(pipeline))
2141 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2142 S_028B54_GS_EN(1) |
2143 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2144 pipeline->graphics.vgt_shader_stages_en = stages;
2145
2146 if (radv_pipeline_has_gs(pipeline))
2147 calculate_gs_ring_sizes(pipeline);
2148
2149 if (radv_pipeline_has_tess(pipeline)) {
2150 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2151 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2152 pipeline->graphics.prim_vertex_count.incr = 1;
2153 }
2154 calculate_tess_state(pipeline, pCreateInfo);
2155 }
2156
2157 const VkPipelineVertexInputStateCreateInfo *vi_info =
2158 pCreateInfo->pVertexInputState;
2159 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2160 const VkVertexInputAttributeDescription *desc =
2161 &vi_info->pVertexAttributeDescriptions[i];
2162 unsigned loc = desc->location;
2163 const struct vk_format_description *format_desc;
2164 int first_non_void;
2165 uint32_t num_format, data_format;
2166 format_desc = vk_format_description(desc->format);
2167 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2168
2169 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2170 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2171
2172 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2173 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2174 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2175 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2176 S_008F0C_NUM_FORMAT(num_format) |
2177 S_008F0C_DATA_FORMAT(data_format);
2178 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2179 pipeline->va_offset[loc] = desc->offset;
2180 pipeline->va_binding[loc] = desc->binding;
2181 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2182 }
2183
2184 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2185 const VkVertexInputBindingDescription *desc =
2186 &vi_info->pVertexBindingDescriptions[i];
2187
2188 pipeline->binding_stride[desc->binding] = desc->stride;
2189 }
2190
2191 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2192 radv_dump_pipeline_stats(device, pipeline);
2193 }
2194
2195 result = radv_pipeline_scratch_init(device, pipeline);
2196 return result;
2197 }
2198
2199 VkResult
2200 radv_graphics_pipeline_create(
2201 VkDevice _device,
2202 VkPipelineCache _cache,
2203 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2204 const struct radv_graphics_pipeline_create_info *extra,
2205 const VkAllocationCallbacks *pAllocator,
2206 VkPipeline *pPipeline)
2207 {
2208 RADV_FROM_HANDLE(radv_device, device, _device);
2209 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2210 struct radv_pipeline *pipeline;
2211 VkResult result;
2212
2213 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2214 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2215 if (pipeline == NULL)
2216 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2217
2218 memset(pipeline, 0, sizeof(*pipeline));
2219 result = radv_pipeline_init(pipeline, device, cache,
2220 pCreateInfo, extra, pAllocator);
2221 if (result != VK_SUCCESS) {
2222 radv_pipeline_destroy(device, pipeline, pAllocator);
2223 return result;
2224 }
2225
2226 *pPipeline = radv_pipeline_to_handle(pipeline);
2227
2228 return VK_SUCCESS;
2229 }
2230
2231 VkResult radv_CreateGraphicsPipelines(
2232 VkDevice _device,
2233 VkPipelineCache pipelineCache,
2234 uint32_t count,
2235 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2236 const VkAllocationCallbacks* pAllocator,
2237 VkPipeline* pPipelines)
2238 {
2239 VkResult result = VK_SUCCESS;
2240 unsigned i = 0;
2241
2242 for (; i < count; i++) {
2243 VkResult r;
2244 r = radv_graphics_pipeline_create(_device,
2245 pipelineCache,
2246 &pCreateInfos[i],
2247 NULL, pAllocator, &pPipelines[i]);
2248 if (r != VK_SUCCESS) {
2249 result = r;
2250 pPipelines[i] = VK_NULL_HANDLE;
2251 }
2252 }
2253
2254 return result;
2255 }
2256
2257 static VkResult radv_compute_pipeline_create(
2258 VkDevice _device,
2259 VkPipelineCache _cache,
2260 const VkComputePipelineCreateInfo* pCreateInfo,
2261 const VkAllocationCallbacks* pAllocator,
2262 VkPipeline* pPipeline)
2263 {
2264 RADV_FROM_HANDLE(radv_device, device, _device);
2265 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2266 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2267 struct radv_pipeline *pipeline;
2268 VkResult result;
2269
2270 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2271 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2272 if (pipeline == NULL)
2273 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2274
2275 memset(pipeline, 0, sizeof(*pipeline));
2276 pipeline->device = device;
2277 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2278
2279 pipeline->shaders[MESA_SHADER_COMPUTE] =
2280 radv_pipeline_compile(pipeline, cache, module,
2281 pCreateInfo->stage.pName,
2282 MESA_SHADER_COMPUTE,
2283 pCreateInfo->stage.pSpecializationInfo,
2284 pipeline->layout, NULL);
2285
2286
2287 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2288 result = radv_pipeline_scratch_init(device, pipeline);
2289 if (result != VK_SUCCESS) {
2290 radv_pipeline_destroy(device, pipeline, pAllocator);
2291 return result;
2292 }
2293
2294 *pPipeline = radv_pipeline_to_handle(pipeline);
2295
2296 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2297 radv_dump_pipeline_stats(device, pipeline);
2298 }
2299 return VK_SUCCESS;
2300 }
2301 VkResult radv_CreateComputePipelines(
2302 VkDevice _device,
2303 VkPipelineCache pipelineCache,
2304 uint32_t count,
2305 const VkComputePipelineCreateInfo* pCreateInfos,
2306 const VkAllocationCallbacks* pAllocator,
2307 VkPipeline* pPipelines)
2308 {
2309 VkResult result = VK_SUCCESS;
2310
2311 unsigned i = 0;
2312 for (; i < count; i++) {
2313 VkResult r;
2314 r = radv_compute_pipeline_create(_device, pipelineCache,
2315 &pCreateInfos[i],
2316 pAllocator, &pPipelines[i]);
2317 if (r != VK_SUCCESS) {
2318 result = r;
2319 pPipelines[i] = VK_NULL_HANDLE;
2320 }
2321 }
2322
2323 return result;
2324 }