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radv: drop ls_out_layout const.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t cb_color_control;
54 uint32_t cb_target_mask;
55 uint32_t sx_mrt_blend_opt[8];
56 uint32_t cb_blend_control[8];
57
58 uint32_t spi_shader_col_format;
59 uint32_t cb_shader_mask;
60 uint32_t db_alpha_to_mask;
61 };
62
63 struct radv_tessellation_state {
64 uint32_t ls_hs_config;
65 uint32_t tcs_in_layout;
66 uint32_t tcs_out_layout;
67 uint32_t tcs_out_offsets;
68 uint32_t offchip_layout;
69 unsigned num_patches;
70 unsigned lds_size;
71 uint32_t tf_param;
72 };
73
74 struct radv_gs_state {
75 uint32_t vgt_gs_onchip_cntl;
76 uint32_t vgt_gs_max_prims_per_subgroup;
77 uint32_t vgt_esgs_ring_itemsize;
78 uint32_t lds_size;
79 };
80
81 static void
82 radv_pipeline_destroy(struct radv_device *device,
83 struct radv_pipeline *pipeline,
84 const VkAllocationCallbacks* allocator)
85 {
86 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
87 if (pipeline->shaders[i])
88 radv_shader_variant_destroy(device, pipeline->shaders[i]);
89
90 if (pipeline->gs_copy_shader)
91 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
92
93 if(pipeline->cs.buf)
94 free(pipeline->cs.buf);
95 vk_free2(&device->alloc, allocator, pipeline);
96 }
97
98 void radv_DestroyPipeline(
99 VkDevice _device,
100 VkPipeline _pipeline,
101 const VkAllocationCallbacks* pAllocator)
102 {
103 RADV_FROM_HANDLE(radv_device, device, _device);
104 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
105
106 if (!_pipeline)
107 return;
108
109 radv_pipeline_destroy(device, pipeline, pAllocator);
110 }
111
112 static uint32_t get_hash_flags(struct radv_device *device)
113 {
114 uint32_t hash_flags = 0;
115
116 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
117 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
118 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
119 hash_flags |= RADV_HASH_SHADER_SISCHED;
120 return hash_flags;
121 }
122
123 static VkResult
124 radv_pipeline_scratch_init(struct radv_device *device,
125 struct radv_pipeline *pipeline)
126 {
127 unsigned scratch_bytes_per_wave = 0;
128 unsigned max_waves = 0;
129 unsigned min_waves = 1;
130
131 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
132 if (pipeline->shaders[i]) {
133 unsigned max_stage_waves = device->scratch_waves;
134
135 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
136 pipeline->shaders[i]->config.scratch_bytes_per_wave);
137
138 max_stage_waves = MIN2(max_stage_waves,
139 4 * device->physical_device->rad_info.num_good_compute_units *
140 (256 / pipeline->shaders[i]->config.num_vgprs));
141 max_waves = MAX2(max_waves, max_stage_waves);
142 }
143 }
144
145 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
146 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
147 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
148 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
149 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
150 }
151
152 if (scratch_bytes_per_wave)
153 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
154
155 if (scratch_bytes_per_wave && max_waves < min_waves) {
156 /* Not really true at this moment, but will be true on first
157 * execution. Avoid having hanging shaders. */
158 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
159 }
160 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
161 pipeline->max_waves = max_waves;
162 return VK_SUCCESS;
163 }
164
165 static uint32_t si_translate_blend_function(VkBlendOp op)
166 {
167 switch (op) {
168 case VK_BLEND_OP_ADD:
169 return V_028780_COMB_DST_PLUS_SRC;
170 case VK_BLEND_OP_SUBTRACT:
171 return V_028780_COMB_SRC_MINUS_DST;
172 case VK_BLEND_OP_REVERSE_SUBTRACT:
173 return V_028780_COMB_DST_MINUS_SRC;
174 case VK_BLEND_OP_MIN:
175 return V_028780_COMB_MIN_DST_SRC;
176 case VK_BLEND_OP_MAX:
177 return V_028780_COMB_MAX_DST_SRC;
178 default:
179 return 0;
180 }
181 }
182
183 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
184 {
185 switch (factor) {
186 case VK_BLEND_FACTOR_ZERO:
187 return V_028780_BLEND_ZERO;
188 case VK_BLEND_FACTOR_ONE:
189 return V_028780_BLEND_ONE;
190 case VK_BLEND_FACTOR_SRC_COLOR:
191 return V_028780_BLEND_SRC_COLOR;
192 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
193 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
194 case VK_BLEND_FACTOR_DST_COLOR:
195 return V_028780_BLEND_DST_COLOR;
196 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
197 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
198 case VK_BLEND_FACTOR_SRC_ALPHA:
199 return V_028780_BLEND_SRC_ALPHA;
200 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
201 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
202 case VK_BLEND_FACTOR_DST_ALPHA:
203 return V_028780_BLEND_DST_ALPHA;
204 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
205 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
206 case VK_BLEND_FACTOR_CONSTANT_COLOR:
207 return V_028780_BLEND_CONSTANT_COLOR;
208 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
209 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
210 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
211 return V_028780_BLEND_CONSTANT_ALPHA;
212 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
213 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
214 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
215 return V_028780_BLEND_SRC_ALPHA_SATURATE;
216 case VK_BLEND_FACTOR_SRC1_COLOR:
217 return V_028780_BLEND_SRC1_COLOR;
218 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
219 return V_028780_BLEND_INV_SRC1_COLOR;
220 case VK_BLEND_FACTOR_SRC1_ALPHA:
221 return V_028780_BLEND_SRC1_ALPHA;
222 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
223 return V_028780_BLEND_INV_SRC1_ALPHA;
224 default:
225 return 0;
226 }
227 }
228
229 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
230 {
231 switch (op) {
232 case VK_BLEND_OP_ADD:
233 return V_028760_OPT_COMB_ADD;
234 case VK_BLEND_OP_SUBTRACT:
235 return V_028760_OPT_COMB_SUBTRACT;
236 case VK_BLEND_OP_REVERSE_SUBTRACT:
237 return V_028760_OPT_COMB_REVSUBTRACT;
238 case VK_BLEND_OP_MIN:
239 return V_028760_OPT_COMB_MIN;
240 case VK_BLEND_OP_MAX:
241 return V_028760_OPT_COMB_MAX;
242 default:
243 return V_028760_OPT_COMB_BLEND_DISABLED;
244 }
245 }
246
247 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
248 {
249 switch (factor) {
250 case VK_BLEND_FACTOR_ZERO:
251 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
252 case VK_BLEND_FACTOR_ONE:
253 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
254 case VK_BLEND_FACTOR_SRC_COLOR:
255 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
256 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
257 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
258 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
259 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
260 case VK_BLEND_FACTOR_SRC_ALPHA:
261 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
262 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
263 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
264 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
265 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
266 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
267 default:
268 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
269 }
270 }
271
272 /**
273 * Get rid of DST in the blend factors by commuting the operands:
274 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
275 */
276 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
277 unsigned *dst_factor, unsigned expected_dst,
278 unsigned replacement_src)
279 {
280 if (*src_factor == expected_dst &&
281 *dst_factor == VK_BLEND_FACTOR_ZERO) {
282 *src_factor = VK_BLEND_FACTOR_ZERO;
283 *dst_factor = replacement_src;
284
285 /* Commuting the operands requires reversing subtractions. */
286 if (*func == VK_BLEND_OP_SUBTRACT)
287 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
288 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
289 *func = VK_BLEND_OP_SUBTRACT;
290 }
291 }
292
293 static bool si_blend_factor_uses_dst(unsigned factor)
294 {
295 return factor == VK_BLEND_FACTOR_DST_COLOR ||
296 factor == VK_BLEND_FACTOR_DST_ALPHA ||
297 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
298 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
299 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
300 }
301
302 static bool is_dual_src(VkBlendFactor factor)
303 {
304 switch (factor) {
305 case VK_BLEND_FACTOR_SRC1_COLOR:
306 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
307 case VK_BLEND_FACTOR_SRC1_ALPHA:
308 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
309 return true;
310 default:
311 return false;
312 }
313 }
314
315 static unsigned si_choose_spi_color_format(VkFormat vk_format,
316 bool blend_enable,
317 bool blend_need_alpha)
318 {
319 const struct vk_format_description *desc = vk_format_description(vk_format);
320 unsigned format, ntype, swap;
321
322 /* Alpha is needed for alpha-to-coverage.
323 * Blending may be with or without alpha.
324 */
325 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
326 unsigned alpha = 0; /* exports alpha, but may not support blending */
327 unsigned blend = 0; /* supports blending, but may not export alpha */
328 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
329
330 format = radv_translate_colorformat(vk_format);
331 ntype = radv_translate_color_numformat(vk_format, desc,
332 vk_format_get_first_non_void_channel(vk_format));
333 swap = radv_translate_colorswap(vk_format, false);
334
335 /* Choose the SPI color formats. These are required values for Stoney/RB+.
336 * Other chips have multiple choices, though they are not necessarily better.
337 */
338 switch (format) {
339 case V_028C70_COLOR_5_6_5:
340 case V_028C70_COLOR_1_5_5_5:
341 case V_028C70_COLOR_5_5_5_1:
342 case V_028C70_COLOR_4_4_4_4:
343 case V_028C70_COLOR_10_11_11:
344 case V_028C70_COLOR_11_11_10:
345 case V_028C70_COLOR_8:
346 case V_028C70_COLOR_8_8:
347 case V_028C70_COLOR_8_8_8_8:
348 case V_028C70_COLOR_10_10_10_2:
349 case V_028C70_COLOR_2_10_10_10:
350 if (ntype == V_028C70_NUMBER_UINT)
351 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
352 else if (ntype == V_028C70_NUMBER_SINT)
353 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
354 else
355 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
356 break;
357
358 case V_028C70_COLOR_16:
359 case V_028C70_COLOR_16_16:
360 case V_028C70_COLOR_16_16_16_16:
361 if (ntype == V_028C70_NUMBER_UNORM ||
362 ntype == V_028C70_NUMBER_SNORM) {
363 /* UNORM16 and SNORM16 don't support blending */
364 if (ntype == V_028C70_NUMBER_UNORM)
365 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
366 else
367 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
368
369 /* Use 32 bits per channel for blending. */
370 if (format == V_028C70_COLOR_16) {
371 if (swap == V_028C70_SWAP_STD) { /* R */
372 blend = V_028714_SPI_SHADER_32_R;
373 blend_alpha = V_028714_SPI_SHADER_32_AR;
374 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
375 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
376 else
377 assert(0);
378 } else if (format == V_028C70_COLOR_16_16) {
379 if (swap == V_028C70_SWAP_STD) { /* RG */
380 blend = V_028714_SPI_SHADER_32_GR;
381 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
382 } else if (swap == V_028C70_SWAP_ALT) /* RA */
383 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
384 else
385 assert(0);
386 } else /* 16_16_16_16 */
387 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
388 } else if (ntype == V_028C70_NUMBER_UINT)
389 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
390 else if (ntype == V_028C70_NUMBER_SINT)
391 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
392 else if (ntype == V_028C70_NUMBER_FLOAT)
393 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
394 else
395 assert(0);
396 break;
397
398 case V_028C70_COLOR_32:
399 if (swap == V_028C70_SWAP_STD) { /* R */
400 blend = normal = V_028714_SPI_SHADER_32_R;
401 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
402 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
403 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
404 else
405 assert(0);
406 break;
407
408 case V_028C70_COLOR_32_32:
409 if (swap == V_028C70_SWAP_STD) { /* RG */
410 blend = normal = V_028714_SPI_SHADER_32_GR;
411 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
412 } else if (swap == V_028C70_SWAP_ALT) /* RA */
413 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
414 else
415 assert(0);
416 break;
417
418 case V_028C70_COLOR_32_32_32_32:
419 case V_028C70_COLOR_8_24:
420 case V_028C70_COLOR_24_8:
421 case V_028C70_COLOR_X24_8_32_FLOAT:
422 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
423 break;
424
425 default:
426 unreachable("unhandled blend format");
427 }
428
429 if (blend_enable && blend_need_alpha)
430 return blend_alpha;
431 else if(blend_need_alpha)
432 return alpha;
433 else if(blend_enable)
434 return blend;
435 else
436 return normal;
437 }
438
439 static void
440 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
441 const VkGraphicsPipelineCreateInfo *pCreateInfo,
442 uint32_t blend_enable,
443 uint32_t blend_need_alpha,
444 bool single_cb_enable,
445 bool blend_mrt0_is_dual_src,
446 struct radv_blend_state *blend)
447 {
448 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
449 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
450 unsigned col_format = 0;
451
452 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
453 unsigned cf;
454
455 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
456 cf = V_028714_SPI_SHADER_ZERO;
457 } else {
458 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
459
460 cf = si_choose_spi_color_format(attachment->format,
461 blend_enable & (1 << i),
462 blend_need_alpha & (1 << i));
463 }
464
465 col_format |= cf << (4 * i);
466 }
467
468 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
469
470 if (blend_mrt0_is_dual_src)
471 col_format |= (col_format & 0xf) << 4;
472 blend->spi_shader_col_format = col_format;
473 }
474
475 static bool
476 format_is_int8(VkFormat format)
477 {
478 const struct vk_format_description *desc = vk_format_description(format);
479 int channel = vk_format_get_first_non_void_channel(format);
480
481 return channel >= 0 && desc->channel[channel].pure_integer &&
482 desc->channel[channel].size == 8;
483 }
484
485 static bool
486 format_is_int10(VkFormat format)
487 {
488 const struct vk_format_description *desc = vk_format_description(format);
489
490 if (desc->nr_channels != 4)
491 return false;
492 for (unsigned i = 0; i < 4; i++) {
493 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
494 return true;
495 }
496 return false;
497 }
498
499 unsigned radv_format_meta_fs_key(VkFormat format)
500 {
501 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
502 bool is_int8 = format_is_int8(format);
503 bool is_int10 = format_is_int10(format);
504
505 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
506 }
507
508 static void
509 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
510 unsigned *is_int8, unsigned *is_int10)
511 {
512 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
513 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
514 *is_int8 = 0;
515 *is_int10 = 0;
516
517 for (unsigned i = 0; i < subpass->color_count; ++i) {
518 struct radv_render_pass_attachment *attachment;
519
520 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
521 continue;
522
523 attachment = pass->attachments + subpass->color_attachments[i].attachment;
524
525 if (format_is_int8(attachment->format))
526 *is_int8 |= 1 << i;
527 if (format_is_int10(attachment->format))
528 *is_int10 |= 1 << i;
529 }
530 }
531
532 static struct radv_blend_state
533 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
534 const VkGraphicsPipelineCreateInfo *pCreateInfo,
535 const struct radv_graphics_pipeline_create_info *extra)
536 {
537 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
538 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
539 struct radv_blend_state blend = {0};
540 unsigned mode = V_028808_CB_NORMAL;
541 uint32_t blend_enable = 0, blend_need_alpha = 0;
542 bool blend_mrt0_is_dual_src = false;
543 int i;
544 bool single_cb_enable = false;
545
546 if (!vkblend)
547 return blend;
548
549 if (extra && extra->custom_blend_mode) {
550 single_cb_enable = true;
551 mode = extra->custom_blend_mode;
552 }
553 blend.cb_color_control = 0;
554 if (vkblend->logicOpEnable)
555 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
556 else
557 blend.cb_color_control |= S_028808_ROP3(0xcc);
558
559 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
560 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
561 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
562 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
563
564 if (vkms && vkms->alphaToCoverageEnable) {
565 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
566 }
567
568 blend.cb_target_mask = 0;
569 for (i = 0; i < vkblend->attachmentCount; i++) {
570 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
571 unsigned blend_cntl = 0;
572 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
573 VkBlendOp eqRGB = att->colorBlendOp;
574 VkBlendFactor srcRGB = att->srcColorBlendFactor;
575 VkBlendFactor dstRGB = att->dstColorBlendFactor;
576 VkBlendOp eqA = att->alphaBlendOp;
577 VkBlendFactor srcA = att->srcAlphaBlendFactor;
578 VkBlendFactor dstA = att->dstAlphaBlendFactor;
579
580 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
581
582 if (!att->colorWriteMask)
583 continue;
584
585 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
586 if (!att->blendEnable) {
587 blend.cb_blend_control[i] = blend_cntl;
588 continue;
589 }
590
591 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
592 if (i == 0)
593 blend_mrt0_is_dual_src = true;
594
595 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
596 srcRGB = VK_BLEND_FACTOR_ONE;
597 dstRGB = VK_BLEND_FACTOR_ONE;
598 }
599 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
600 srcA = VK_BLEND_FACTOR_ONE;
601 dstA = VK_BLEND_FACTOR_ONE;
602 }
603
604 /* Blending optimizations for RB+.
605 * These transformations don't change the behavior.
606 *
607 * First, get rid of DST in the blend factors:
608 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
609 */
610 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
611 VK_BLEND_FACTOR_DST_COLOR,
612 VK_BLEND_FACTOR_SRC_COLOR);
613
614 si_blend_remove_dst(&eqA, &srcA, &dstA,
615 VK_BLEND_FACTOR_DST_COLOR,
616 VK_BLEND_FACTOR_SRC_COLOR);
617
618 si_blend_remove_dst(&eqA, &srcA, &dstA,
619 VK_BLEND_FACTOR_DST_ALPHA,
620 VK_BLEND_FACTOR_SRC_ALPHA);
621
622 /* Look up the ideal settings from tables. */
623 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
624 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
625 srcA_opt = si_translate_blend_opt_factor(srcA, true);
626 dstA_opt = si_translate_blend_opt_factor(dstA, true);
627
628 /* Handle interdependencies. */
629 if (si_blend_factor_uses_dst(srcRGB))
630 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
631 if (si_blend_factor_uses_dst(srcA))
632 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
633
634 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
635 (dstRGB == VK_BLEND_FACTOR_ZERO ||
636 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
637 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
638 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
639
640 /* Set the final value. */
641 blend.sx_mrt_blend_opt[i] =
642 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
643 S_028760_COLOR_DST_OPT(dstRGB_opt) |
644 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
645 S_028760_ALPHA_SRC_OPT(srcA_opt) |
646 S_028760_ALPHA_DST_OPT(dstA_opt) |
647 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
648 blend_cntl |= S_028780_ENABLE(1);
649
650 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
651 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
652 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
653 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
654 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
655 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
656 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
657 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
658 }
659 blend.cb_blend_control[i] = blend_cntl;
660
661 blend_enable |= 1 << i;
662
663 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
664 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
665 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
666 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
667 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
668 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
669 blend_need_alpha |= 1 << i;
670 }
671 for (i = vkblend->attachmentCount; i < 8; i++) {
672 blend.cb_blend_control[i] = 0;
673 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
674 }
675
676 /* disable RB+ for now */
677 if (pipeline->device->physical_device->has_rbplus)
678 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
679
680 if (blend.cb_target_mask)
681 blend.cb_color_control |= S_028808_MODE(mode);
682 else
683 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
684
685 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
686 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src,
687 &blend);
688 return blend;
689 }
690
691 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
692 {
693 switch (op) {
694 case VK_STENCIL_OP_KEEP:
695 return V_02842C_STENCIL_KEEP;
696 case VK_STENCIL_OP_ZERO:
697 return V_02842C_STENCIL_ZERO;
698 case VK_STENCIL_OP_REPLACE:
699 return V_02842C_STENCIL_REPLACE_TEST;
700 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
701 return V_02842C_STENCIL_ADD_CLAMP;
702 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
703 return V_02842C_STENCIL_SUB_CLAMP;
704 case VK_STENCIL_OP_INVERT:
705 return V_02842C_STENCIL_INVERT;
706 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
707 return V_02842C_STENCIL_ADD_WRAP;
708 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
709 return V_02842C_STENCIL_SUB_WRAP;
710 default:
711 return 0;
712 }
713 }
714
715 static uint32_t si_translate_fill(VkPolygonMode func)
716 {
717 switch(func) {
718 case VK_POLYGON_MODE_FILL:
719 return V_028814_X_DRAW_TRIANGLES;
720 case VK_POLYGON_MODE_LINE:
721 return V_028814_X_DRAW_LINES;
722 case VK_POLYGON_MODE_POINT:
723 return V_028814_X_DRAW_POINTS;
724 default:
725 assert(0);
726 return V_028814_X_DRAW_POINTS;
727 }
728 }
729
730 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
731 {
732 uint32_t num_samples = vkms->rasterizationSamples;
733 uint32_t ps_iter_samples = 1;
734
735 if (vkms->sampleShadingEnable) {
736 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
737 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
738 }
739 return ps_iter_samples;
740 }
741
742 static void
743 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
744 const VkGraphicsPipelineCreateInfo *pCreateInfo)
745 {
746 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
747 struct radv_multisample_state *ms = &pipeline->graphics.ms;
748 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
749 int ps_iter_samples = 1;
750 uint32_t mask = 0xffff;
751
752 if (vkms)
753 ms->num_samples = vkms->rasterizationSamples;
754 else
755 ms->num_samples = 1;
756
757 if (vkms)
758 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
759 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
760 ps_iter_samples = ms->num_samples;
761 }
762
763 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
764 ms->pa_sc_aa_config = 0;
765 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
766 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
767 ms->pa_sc_mode_cntl_1 =
768 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
769 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
770 /* always 1: */
771 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
772 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
773 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
774 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
775 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
776 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
777 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
778 S_028A48_VPORT_SCISSOR_ENABLE(1);
779
780 if (ms->num_samples > 1) {
781 unsigned log_samples = util_logbase2(ms->num_samples);
782 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
783 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
784 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
785 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
786 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
787 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
788 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
789 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
790 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
791 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
792 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
793 if (ps_iter_samples > 1)
794 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
795 }
796
797 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
798 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
799 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
800 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
801 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
802 }
803
804 if (vkms && vkms->pSampleMask) {
805 mask = vkms->pSampleMask[0] & 0xffff;
806 }
807
808 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
809 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
810 }
811
812 static bool
813 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
814 {
815 switch (topology) {
816 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
817 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
818 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
819 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
820 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
821 return false;
822 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
823 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
824 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
825 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
826 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
827 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
828 return true;
829 default:
830 unreachable("unhandled primitive type");
831 }
832 }
833
834 static uint32_t
835 si_translate_prim(enum VkPrimitiveTopology topology)
836 {
837 switch (topology) {
838 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
839 return V_008958_DI_PT_POINTLIST;
840 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
841 return V_008958_DI_PT_LINELIST;
842 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
843 return V_008958_DI_PT_LINESTRIP;
844 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
845 return V_008958_DI_PT_TRILIST;
846 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
847 return V_008958_DI_PT_TRISTRIP;
848 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
849 return V_008958_DI_PT_TRIFAN;
850 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
851 return V_008958_DI_PT_LINELIST_ADJ;
852 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
853 return V_008958_DI_PT_LINESTRIP_ADJ;
854 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
855 return V_008958_DI_PT_TRILIST_ADJ;
856 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
857 return V_008958_DI_PT_TRISTRIP_ADJ;
858 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
859 return V_008958_DI_PT_PATCH;
860 default:
861 assert(0);
862 return 0;
863 }
864 }
865
866 static uint32_t
867 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
868 {
869 switch (gl_prim) {
870 case 0: /* GL_POINTS */
871 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
872 case 1: /* GL_LINES */
873 case 3: /* GL_LINE_STRIP */
874 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
875 case 0x8E7A: /* GL_ISOLINES */
876 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
877
878 case 4: /* GL_TRIANGLES */
879 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
880 case 5: /* GL_TRIANGLE_STRIP */
881 case 7: /* GL_QUADS */
882 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
883 default:
884 assert(0);
885 return 0;
886 }
887 }
888
889 static uint32_t
890 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
891 {
892 switch (topology) {
893 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
894 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
895 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
896 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
897 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
898 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
899 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
900 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
901 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
902 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
903 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
904 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
905 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
906 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
907 default:
908 assert(0);
909 return 0;
910 }
911 }
912
913 static unsigned si_map_swizzle(unsigned swizzle)
914 {
915 switch (swizzle) {
916 case VK_SWIZZLE_Y:
917 return V_008F0C_SQ_SEL_Y;
918 case VK_SWIZZLE_Z:
919 return V_008F0C_SQ_SEL_Z;
920 case VK_SWIZZLE_W:
921 return V_008F0C_SQ_SEL_W;
922 case VK_SWIZZLE_0:
923 return V_008F0C_SQ_SEL_0;
924 case VK_SWIZZLE_1:
925 return V_008F0C_SQ_SEL_1;
926 default: /* VK_SWIZZLE_X */
927 return V_008F0C_SQ_SEL_X;
928 }
929 }
930
931
932 static unsigned radv_dynamic_state_mask(VkDynamicState state)
933 {
934 switch(state) {
935 case VK_DYNAMIC_STATE_VIEWPORT:
936 return RADV_DYNAMIC_VIEWPORT;
937 case VK_DYNAMIC_STATE_SCISSOR:
938 return RADV_DYNAMIC_SCISSOR;
939 case VK_DYNAMIC_STATE_LINE_WIDTH:
940 return RADV_DYNAMIC_LINE_WIDTH;
941 case VK_DYNAMIC_STATE_DEPTH_BIAS:
942 return RADV_DYNAMIC_DEPTH_BIAS;
943 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
944 return RADV_DYNAMIC_BLEND_CONSTANTS;
945 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
946 return RADV_DYNAMIC_DEPTH_BOUNDS;
947 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
948 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
949 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
950 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
951 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
952 return RADV_DYNAMIC_STENCIL_REFERENCE;
953 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
954 return RADV_DYNAMIC_DISCARD_RECTANGLE;
955 default:
956 unreachable("Unhandled dynamic state");
957 }
958 }
959
960 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
961 {
962 uint32_t states = RADV_DYNAMIC_ALL;
963
964 /* If rasterization is disabled we do not care about any of the dynamic states,
965 * since they are all rasterization related only. */
966 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
967 return 0;
968
969 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
970 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
971
972 if (!pCreateInfo->pDepthStencilState ||
973 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
974 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
975
976 if (!pCreateInfo->pDepthStencilState ||
977 !pCreateInfo->pDepthStencilState->stencilTestEnable)
978 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
979 RADV_DYNAMIC_STENCIL_WRITE_MASK |
980 RADV_DYNAMIC_STENCIL_REFERENCE);
981
982 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
983 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
984
985 /* TODO: blend constants & line width. */
986
987 return states;
988 }
989
990
991 static void
992 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
993 const VkGraphicsPipelineCreateInfo *pCreateInfo)
994 {
995 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
996 uint32_t states = needed_states;
997 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
998 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
999
1000 pipeline->dynamic_state = default_dynamic_state;
1001 pipeline->graphics.needed_dynamic_state = needed_states;
1002
1003 if (pCreateInfo->pDynamicState) {
1004 /* Remove all of the states that are marked as dynamic */
1005 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1006 for (uint32_t s = 0; s < count; s++)
1007 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1008 }
1009
1010 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1011
1012 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1013 assert(pCreateInfo->pViewportState);
1014
1015 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1016 if (states & RADV_DYNAMIC_VIEWPORT) {
1017 typed_memcpy(dynamic->viewport.viewports,
1018 pCreateInfo->pViewportState->pViewports,
1019 pCreateInfo->pViewportState->viewportCount);
1020 }
1021 }
1022
1023 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1024 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1025 if (states & RADV_DYNAMIC_SCISSOR) {
1026 typed_memcpy(dynamic->scissor.scissors,
1027 pCreateInfo->pViewportState->pScissors,
1028 pCreateInfo->pViewportState->scissorCount);
1029 }
1030 }
1031
1032 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1033 assert(pCreateInfo->pRasterizationState);
1034 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1035 }
1036
1037 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1038 assert(pCreateInfo->pRasterizationState);
1039 dynamic->depth_bias.bias =
1040 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1041 dynamic->depth_bias.clamp =
1042 pCreateInfo->pRasterizationState->depthBiasClamp;
1043 dynamic->depth_bias.slope =
1044 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1045 }
1046
1047 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1048 *
1049 * pColorBlendState is [...] NULL if the pipeline has rasterization
1050 * disabled or if the subpass of the render pass the pipeline is
1051 * created against does not use any color attachments.
1052 */
1053 bool uses_color_att = false;
1054 for (unsigned i = 0; i < subpass->color_count; ++i) {
1055 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1056 uses_color_att = true;
1057 break;
1058 }
1059 }
1060
1061 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1062 assert(pCreateInfo->pColorBlendState);
1063 typed_memcpy(dynamic->blend_constants,
1064 pCreateInfo->pColorBlendState->blendConstants, 4);
1065 }
1066
1067 /* If there is no depthstencil attachment, then don't read
1068 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1069 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1070 * no need to override the depthstencil defaults in
1071 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1072 *
1073 * Section 9.2 of the Vulkan 1.0.15 spec says:
1074 *
1075 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1076 * disabled or if the subpass of the render pass the pipeline is created
1077 * against does not use a depth/stencil attachment.
1078 */
1079 if (needed_states &&
1080 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1081 assert(pCreateInfo->pDepthStencilState);
1082
1083 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1084 dynamic->depth_bounds.min =
1085 pCreateInfo->pDepthStencilState->minDepthBounds;
1086 dynamic->depth_bounds.max =
1087 pCreateInfo->pDepthStencilState->maxDepthBounds;
1088 }
1089
1090 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1091 dynamic->stencil_compare_mask.front =
1092 pCreateInfo->pDepthStencilState->front.compareMask;
1093 dynamic->stencil_compare_mask.back =
1094 pCreateInfo->pDepthStencilState->back.compareMask;
1095 }
1096
1097 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1098 dynamic->stencil_write_mask.front =
1099 pCreateInfo->pDepthStencilState->front.writeMask;
1100 dynamic->stencil_write_mask.back =
1101 pCreateInfo->pDepthStencilState->back.writeMask;
1102 }
1103
1104 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1105 dynamic->stencil_reference.front =
1106 pCreateInfo->pDepthStencilState->front.reference;
1107 dynamic->stencil_reference.back =
1108 pCreateInfo->pDepthStencilState->back.reference;
1109 }
1110 }
1111
1112 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1113 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1114 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1115 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1116 typed_memcpy(dynamic->discard_rectangle.rectangles,
1117 discard_rectangle_info->pDiscardRectangles,
1118 discard_rectangle_info->discardRectangleCount);
1119 }
1120
1121 pipeline->dynamic_state.mask = states;
1122 }
1123
1124 static struct radv_gs_state
1125 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1126 const struct radv_pipeline *pipeline)
1127 {
1128 struct radv_gs_state gs = {0};
1129 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1130 struct radv_es_output_info *es_info;
1131 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1132 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1133 else
1134 es_info = radv_pipeline_has_tess(pipeline) ?
1135 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1136 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1137
1138 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1139 bool uses_adjacency;
1140 switch(pCreateInfo->pInputAssemblyState->topology) {
1141 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1142 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1143 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1144 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1145 uses_adjacency = true;
1146 break;
1147 default:
1148 uses_adjacency = false;
1149 break;
1150 }
1151
1152 /* All these are in dwords: */
1153 /* We can't allow using the whole LDS, because GS waves compete with
1154 * other shader stages for LDS space. */
1155 const unsigned max_lds_size = 8 * 1024;
1156 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1157 unsigned esgs_lds_size;
1158
1159 /* All these are per subgroup: */
1160 const unsigned max_out_prims = 32 * 1024;
1161 const unsigned max_es_verts = 255;
1162 const unsigned ideal_gs_prims = 64;
1163 unsigned max_gs_prims, gs_prims;
1164 unsigned min_es_verts, es_verts, worst_case_es_verts;
1165
1166 if (uses_adjacency || gs_num_invocations > 1)
1167 max_gs_prims = 127 / gs_num_invocations;
1168 else
1169 max_gs_prims = 255;
1170
1171 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1172 * Make sure we don't go over the maximum value.
1173 */
1174 if (gs_info->gs.vertices_out > 0) {
1175 max_gs_prims = MIN2(max_gs_prims,
1176 max_out_prims /
1177 (gs_info->gs.vertices_out * gs_num_invocations));
1178 }
1179 assert(max_gs_prims > 0);
1180
1181 /* If the primitive has adjacency, halve the number of vertices
1182 * that will be reused in multiple primitives.
1183 */
1184 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1185
1186 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1187 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1188
1189 /* Compute ESGS LDS size based on the worst case number of ES vertices
1190 * needed to create the target number of GS prims per subgroup.
1191 */
1192 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1193
1194 /* If total LDS usage is too big, refactor partitions based on ratio
1195 * of ESGS item sizes.
1196 */
1197 if (esgs_lds_size > max_lds_size) {
1198 /* Our target GS Prims Per Subgroup was too large. Calculate
1199 * the maximum number of GS Prims Per Subgroup that will fit
1200 * into LDS, capped by the maximum that the hardware can support.
1201 */
1202 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1203 max_gs_prims);
1204 assert(gs_prims > 0);
1205 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1206 max_es_verts);
1207
1208 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1209 assert(esgs_lds_size <= max_lds_size);
1210 }
1211
1212 /* Now calculate remaining ESGS information. */
1213 if (esgs_lds_size)
1214 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1215 else
1216 es_verts = max_es_verts;
1217
1218 /* Vertices for adjacency primitives are not always reused, so restore
1219 * it for ES_VERTS_PER_SUBGRP.
1220 */
1221 min_es_verts = gs_info->gs.vertices_in;
1222
1223 /* For normal primitives, the VGT only checks if they are past the ES
1224 * verts per subgroup after allocating a full GS primitive and if they
1225 * are, kick off a new subgroup. But if those additional ES verts are
1226 * unique (e.g. not reused) we need to make sure there is enough LDS
1227 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1228 */
1229 es_verts -= min_es_verts - 1;
1230
1231 uint32_t es_verts_per_subgroup = es_verts;
1232 uint32_t gs_prims_per_subgroup = gs_prims;
1233 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1234 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1235 gs.lds_size = align(esgs_lds_size, 128) / 128;
1236 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1237 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1238 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1239 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1240 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1241 assert(max_prims_per_subgroup <= max_out_prims);
1242
1243 return gs;
1244 }
1245
1246 static void
1247 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1248 {
1249 struct radv_device *device = pipeline->device;
1250 unsigned num_se = device->physical_device->rad_info.max_se;
1251 unsigned wave_size = 64;
1252 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1253 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1254 unsigned alignment = 256 * num_se;
1255 /* The maximum size is 63.999 MB per SE. */
1256 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1257 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1258
1259 /* Calculate the minimum size. */
1260 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1261 wave_size, alignment);
1262 /* These are recommended sizes, not minimum sizes. */
1263 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1264 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1265 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1266 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1267
1268 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1269 esgs_ring_size = align(esgs_ring_size, alignment);
1270 gsvs_ring_size = align(gsvs_ring_size, alignment);
1271
1272 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1273 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1274
1275 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1276 }
1277
1278 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1279 unsigned *lds_size)
1280 {
1281 /* SPI barrier management bug:
1282 * Make sure we have at least 4k of LDS in use to avoid the bug.
1283 * It applies to workgroup sizes of more than one wavefront.
1284 */
1285 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1286 device->physical_device->rad_info.family == CHIP_KABINI ||
1287 device->physical_device->rad_info.family == CHIP_MULLINS)
1288 *lds_size = MAX2(*lds_size, 8);
1289 }
1290
1291 struct radv_shader_variant *
1292 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1293 {
1294 if (pipeline->shaders[MESA_SHADER_VERTEX])
1295 return pipeline->shaders[MESA_SHADER_VERTEX];
1296 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1297 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1298 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1299 }
1300
1301 static struct radv_shader_variant *
1302 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1303 {
1304 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1305 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1306 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1307 }
1308
1309 static struct radv_tessellation_state
1310 calculate_tess_state(struct radv_pipeline *pipeline,
1311 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1312 {
1313 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1314 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1315 unsigned num_tcs_patch_outputs;
1316 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1317 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1318 unsigned lds_size, hardware_lds_size;
1319 unsigned perpatch_output_offset;
1320 unsigned num_patches;
1321 struct radv_tessellation_state tess = {0};
1322
1323 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1324 * are laid out in LDS. */
1325 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1326
1327 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1328 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1329 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1330
1331 /* Ensure that we only need one wave per SIMD so we don't need to check
1332 * resource usage. Also ensures that the number of tcs in and out
1333 * vertices per threadgroup are at most 256.
1334 */
1335 input_vertex_size = num_tcs_inputs * 16;
1336 output_vertex_size = num_tcs_outputs * 16;
1337
1338 input_patch_size = num_tcs_input_cp * input_vertex_size;
1339
1340 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1341 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1342 /* Ensure that we only need one wave per SIMD so we don't need to check
1343 * resource usage. Also ensures that the number of tcs in and out
1344 * vertices per threadgroup are at most 256.
1345 */
1346 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1347
1348 /* Make sure that the data fits in LDS. This assumes the shaders only
1349 * use LDS for the inputs and outputs.
1350 */
1351 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1352 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1353
1354 /* Make sure the output data fits in the offchip buffer */
1355 num_patches = MIN2(num_patches,
1356 (pipeline->device->tess_offchip_block_dw_size * 4) /
1357 output_patch_size);
1358
1359 /* Not necessary for correctness, but improves performance. The
1360 * specific value is taken from the proprietary driver.
1361 */
1362 num_patches = MIN2(num_patches, 40);
1363
1364 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1365 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1366 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1367 num_patches = MIN2(num_patches, one_wave);
1368 }
1369
1370 output_patch0_offset = input_patch_size * num_patches;
1371 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1372
1373 lds_size = output_patch0_offset + output_patch_size * num_patches;
1374
1375 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1376 assert(lds_size <= 65536);
1377 lds_size = align(lds_size, 512) / 512;
1378 } else {
1379 assert(lds_size <= 32768);
1380 lds_size = align(lds_size, 256) / 256;
1381 }
1382 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1383
1384 tess.lds_size = lds_size;
1385
1386 tess.tcs_in_layout = (input_patch_size / 4) |
1387 ((input_vertex_size / 4) << 13);
1388 tess.tcs_out_layout = (output_patch_size / 4) |
1389 ((output_vertex_size / 4) << 13);
1390 tess.tcs_out_offsets = (output_patch0_offset / 16) |
1391 ((perpatch_output_offset / 16) << 16);
1392 tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1393 num_patches;
1394
1395 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1396 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1397 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1398 tess.num_patches = num_patches;
1399
1400 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1401 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1402
1403 switch (tes->info.tes.primitive_mode) {
1404 case GL_TRIANGLES:
1405 type = V_028B6C_TESS_TRIANGLE;
1406 break;
1407 case GL_QUADS:
1408 type = V_028B6C_TESS_QUAD;
1409 break;
1410 case GL_ISOLINES:
1411 type = V_028B6C_TESS_ISOLINE;
1412 break;
1413 }
1414
1415 switch (tes->info.tes.spacing) {
1416 case TESS_SPACING_EQUAL:
1417 partitioning = V_028B6C_PART_INTEGER;
1418 break;
1419 case TESS_SPACING_FRACTIONAL_ODD:
1420 partitioning = V_028B6C_PART_FRAC_ODD;
1421 break;
1422 case TESS_SPACING_FRACTIONAL_EVEN:
1423 partitioning = V_028B6C_PART_FRAC_EVEN;
1424 break;
1425 default:
1426 break;
1427 }
1428
1429 bool ccw = tes->info.tes.ccw;
1430 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1431 vk_find_struct_const(pCreateInfo->pTessellationState,
1432 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1433
1434 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1435 ccw = !ccw;
1436
1437 if (tes->info.tes.point_mode)
1438 topology = V_028B6C_OUTPUT_POINT;
1439 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1440 topology = V_028B6C_OUTPUT_LINE;
1441 else if (ccw)
1442 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1443 else
1444 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1445
1446 if (pipeline->device->has_distributed_tess) {
1447 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1448 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1449 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1450 else
1451 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1452 } else
1453 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1454
1455 tess.tf_param = S_028B6C_TYPE(type) |
1456 S_028B6C_PARTITIONING(partitioning) |
1457 S_028B6C_TOPOLOGY(topology) |
1458 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1459
1460 return tess;
1461 }
1462
1463 static const struct radv_prim_vertex_count prim_size_table[] = {
1464 [V_008958_DI_PT_NONE] = {0, 0},
1465 [V_008958_DI_PT_POINTLIST] = {1, 1},
1466 [V_008958_DI_PT_LINELIST] = {2, 2},
1467 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1468 [V_008958_DI_PT_TRILIST] = {3, 3},
1469 [V_008958_DI_PT_TRIFAN] = {3, 1},
1470 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1471 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1472 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1473 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1474 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1475 [V_008958_DI_PT_RECTLIST] = {3, 3},
1476 [V_008958_DI_PT_LINELOOP] = {2, 1},
1477 [V_008958_DI_PT_POLYGON] = {3, 1},
1478 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1479 };
1480
1481 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1482 {
1483 if (radv_pipeline_has_gs(pipeline))
1484 return &pipeline->gs_copy_shader->info.vs.outinfo;
1485 else if (radv_pipeline_has_tess(pipeline))
1486 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1487 else
1488 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1489 }
1490
1491 static void
1492 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1493 {
1494 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1495 int shader_count = 0;
1496
1497 if(shaders[MESA_SHADER_FRAGMENT]) {
1498 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1499 }
1500 if(shaders[MESA_SHADER_GEOMETRY]) {
1501 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1502 }
1503 if(shaders[MESA_SHADER_TESS_EVAL]) {
1504 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1505 }
1506 if(shaders[MESA_SHADER_TESS_CTRL]) {
1507 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1508 }
1509 if(shaders[MESA_SHADER_VERTEX]) {
1510 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1511 }
1512
1513 for (int i = 1; i < shader_count; ++i) {
1514 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1515 ordered_shaders[i - 1]);
1516
1517 nir_remove_dead_variables(ordered_shaders[i],
1518 nir_var_shader_out);
1519 nir_remove_dead_variables(ordered_shaders[i - 1],
1520 nir_var_shader_in);
1521
1522 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1523 ordered_shaders[i - 1]);
1524
1525 nir_compact_varyings(ordered_shaders[i],
1526 ordered_shaders[i - 1], true);
1527
1528 if (progress) {
1529 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1530 ac_lower_indirect_derefs(ordered_shaders[i],
1531 pipeline->device->physical_device->rad_info.chip_class);
1532 }
1533 radv_optimize_nir(ordered_shaders[i]);
1534
1535 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1536 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1537 pipeline->device->physical_device->rad_info.chip_class);
1538 }
1539 radv_optimize_nir(ordered_shaders[i - 1]);
1540 }
1541 }
1542 }
1543
1544
1545 static struct radv_pipeline_key
1546 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1547 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1548 const struct radv_blend_state *blend,
1549 bool has_view_index)
1550 {
1551 const VkPipelineVertexInputStateCreateInfo *input_state =
1552 pCreateInfo->pVertexInputState;
1553 struct radv_pipeline_key key;
1554 memset(&key, 0, sizeof(key));
1555
1556 key.has_multiview_view_index = has_view_index;
1557
1558 uint32_t binding_input_rate = 0;
1559 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1560 if (input_state->pVertexBindingDescriptions[i].inputRate)
1561 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1562 }
1563
1564 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1565 unsigned binding;
1566 binding = input_state->pVertexAttributeDescriptions[i].binding;
1567 if (binding_input_rate & (1u << binding))
1568 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1569 }
1570
1571 if (pCreateInfo->pTessellationState)
1572 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1573
1574
1575 if (pCreateInfo->pMultisampleState &&
1576 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1577 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1578 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1579 key.multisample = true;
1580 key.log2_num_samples = util_logbase2(num_samples);
1581 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1582 }
1583
1584 key.col_format = blend->spi_shader_col_format;
1585 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1586 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1587
1588 return key;
1589 }
1590
1591 static void
1592 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1593 const struct radv_pipeline_key *key,
1594 nir_shader **nir)
1595 {
1596 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1597
1598 if (nir[MESA_SHADER_TESS_CTRL]) {
1599 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1600 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1601 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1602
1603 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1604 }
1605
1606 if (nir[MESA_SHADER_GEOMETRY]) {
1607 if (nir[MESA_SHADER_TESS_CTRL])
1608 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1609 else
1610 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1611 }
1612
1613 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1614 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1615
1616 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1617 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1618 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1619 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1620 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1621 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1622 }
1623
1624 static void
1625 merge_tess_info(struct shader_info *tes_info,
1626 const struct shader_info *tcs_info)
1627 {
1628 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1629 *
1630 * "PointMode. Controls generation of points rather than triangles
1631 * or lines. This functionality defaults to disabled, and is
1632 * enabled if either shader stage includes the execution mode.
1633 *
1634 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1635 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1636 * and OutputVertices, it says:
1637 *
1638 * "One mode must be set in at least one of the tessellation
1639 * shader stages."
1640 *
1641 * So, the fields can be set in either the TCS or TES, but they must
1642 * agree if set in both. Our backend looks at TES, so bitwise-or in
1643 * the values from the TCS.
1644 */
1645 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1646 tes_info->tess.tcs_vertices_out == 0 ||
1647 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1648 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1649
1650 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1651 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1652 tcs_info->tess.spacing == tes_info->tess.spacing);
1653 tes_info->tess.spacing |= tcs_info->tess.spacing;
1654
1655 assert(tcs_info->tess.primitive_mode == 0 ||
1656 tes_info->tess.primitive_mode == 0 ||
1657 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1658 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1659 tes_info->tess.ccw |= tcs_info->tess.ccw;
1660 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1661 }
1662
1663 static
1664 void radv_create_shaders(struct radv_pipeline *pipeline,
1665 struct radv_device *device,
1666 struct radv_pipeline_cache *cache,
1667 struct radv_pipeline_key key,
1668 const VkPipelineShaderStageCreateInfo **pStages)
1669 {
1670 struct radv_shader_module fs_m = {0};
1671 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1672 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1673 void *codes[MESA_SHADER_STAGES] = {0};
1674 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1675 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1676 unsigned char hash[20], gs_copy_hash[20];
1677
1678 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1679 if (pStages[i]) {
1680 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1681 if (modules[i]->nir)
1682 _mesa_sha1_compute(modules[i]->nir->info.name,
1683 strlen(modules[i]->nir->info.name),
1684 modules[i]->sha1);
1685 }
1686 }
1687
1688 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1689 memcpy(gs_copy_hash, hash, 20);
1690 gs_copy_hash[0] ^= 1;
1691
1692 if (modules[MESA_SHADER_GEOMETRY]) {
1693 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1694 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1695 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1696 }
1697
1698 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1699 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1700 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1701 if (pipeline->shaders[i])
1702 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1703 }
1704 return;
1705 }
1706
1707 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1708 nir_builder fs_b;
1709 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1710 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1711 fs_m.nir = fs_b.shader;
1712 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1713 }
1714
1715 /* Determine first and last stage. */
1716 unsigned first = MESA_SHADER_STAGES;
1717 unsigned last = 0;
1718 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1719 if (!pStages[i])
1720 continue;
1721 if (first == MESA_SHADER_STAGES)
1722 first = i;
1723 last = i;
1724 }
1725
1726 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1727 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1728
1729 if (!modules[i])
1730 continue;
1731
1732 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1733 stage ? stage->pName : "main", i,
1734 stage ? stage->pSpecializationInfo : NULL);
1735 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1736
1737 /* We don't want to alter meta shaders IR directly so clone it
1738 * first.
1739 */
1740 if (nir[i]->info.name) {
1741 nir[i] = nir_shader_clone(NULL, nir[i]);
1742 }
1743
1744 if (first != last) {
1745 nir_variable_mode mask = 0;
1746
1747 if (i != first)
1748 mask = mask | nir_var_shader_in;
1749
1750 if (i != last)
1751 mask = mask | nir_var_shader_out;
1752
1753 nir_lower_io_to_scalar_early(nir[i], mask);
1754 radv_optimize_nir(nir[i]);
1755 }
1756 }
1757
1758 if (nir[MESA_SHADER_TESS_CTRL]) {
1759 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1760 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1761 }
1762
1763 radv_link_shaders(pipeline, nir);
1764
1765 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1766 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1767 nir_print_shader(nir[i], stderr);
1768 }
1769
1770 radv_fill_shader_keys(keys, &key, nir);
1771
1772 if (nir[MESA_SHADER_FRAGMENT]) {
1773 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1774 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1775 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1776 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1777 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1778 }
1779
1780 /* TODO: These are no longer used as keys we should refactor this */
1781 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1782 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1783 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1784 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1785 }
1786
1787 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1788 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1789 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1790 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1791 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1792 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1793 pipeline->layout,
1794 &key, &codes[MESA_SHADER_TESS_CTRL],
1795 &code_sizes[MESA_SHADER_TESS_CTRL]);
1796 }
1797 modules[MESA_SHADER_VERTEX] = NULL;
1798 }
1799
1800 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1801 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1802 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1803 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1804 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1805 pipeline->layout,
1806 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1807 &code_sizes[MESA_SHADER_GEOMETRY]);
1808 }
1809 modules[pre_stage] = NULL;
1810 }
1811
1812 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1813 if(modules[i] && !pipeline->shaders[i]) {
1814 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1815 pipeline->layout,
1816 keys + i, &codes[i],
1817 &code_sizes[i]);
1818 }
1819 }
1820
1821 if(modules[MESA_SHADER_GEOMETRY]) {
1822 void *gs_copy_code = NULL;
1823 unsigned gs_copy_code_size = 0;
1824 if (!pipeline->gs_copy_shader) {
1825 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1826 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1827 &gs_copy_code_size,
1828 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1829 }
1830
1831 if (pipeline->gs_copy_shader) {
1832 void *code[MESA_SHADER_STAGES] = {0};
1833 unsigned code_size[MESA_SHADER_STAGES] = {0};
1834 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1835
1836 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1837 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1838 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1839
1840 radv_pipeline_cache_insert_shaders(device, cache,
1841 gs_copy_hash,
1842 variants,
1843 (const void**)code,
1844 code_size);
1845 }
1846 free(gs_copy_code);
1847 }
1848
1849 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1850 (const void**)codes, code_sizes);
1851
1852 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1853 free(codes[i]);
1854 if (modules[i]) {
1855 if (!pipeline->device->keep_shader_info)
1856 ralloc_free(nir[i]);
1857
1858 if (radv_can_dump_shader_stats(device, modules[i]))
1859 radv_shader_dump_stats(device,
1860 pipeline->shaders[i],
1861 i, stderr);
1862 }
1863 }
1864
1865 if (fs_m.nir)
1866 ralloc_free(fs_m.nir);
1867 }
1868
1869 static uint32_t
1870 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1871 gl_shader_stage stage, enum chip_class chip_class)
1872 {
1873 bool has_gs = radv_pipeline_has_gs(pipeline);
1874 bool has_tess = radv_pipeline_has_tess(pipeline);
1875 switch (stage) {
1876 case MESA_SHADER_FRAGMENT:
1877 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1878 case MESA_SHADER_VERTEX:
1879 if (chip_class >= GFX9) {
1880 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1881 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1882 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1883 }
1884 if (has_tess)
1885 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1886 else
1887 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1888 case MESA_SHADER_GEOMETRY:
1889 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1890 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1891 case MESA_SHADER_COMPUTE:
1892 return R_00B900_COMPUTE_USER_DATA_0;
1893 case MESA_SHADER_TESS_CTRL:
1894 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1895 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1896 case MESA_SHADER_TESS_EVAL:
1897 if (chip_class >= GFX9) {
1898 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1899 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1900 }
1901 if (has_gs)
1902 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1903 else
1904 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1905 default:
1906 unreachable("unknown shader");
1907 }
1908 }
1909
1910 struct radv_bin_size_entry {
1911 unsigned bpp;
1912 VkExtent2D extent;
1913 };
1914
1915 static VkExtent2D
1916 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1917 {
1918 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1919 {
1920 /* One RB / SE */
1921 {
1922 /* One shader engine */
1923 { 0, {128, 128}},
1924 { 1, { 64, 128}},
1925 { 2, { 32, 128}},
1926 { 3, { 16, 128}},
1927 { 17, { 0, 0}},
1928 { UINT_MAX, { 0, 0}},
1929 },
1930 {
1931 /* Two shader engines */
1932 { 0, {128, 128}},
1933 { 2, { 64, 128}},
1934 { 3, { 32, 128}},
1935 { 5, { 16, 128}},
1936 { 17, { 0, 0}},
1937 { UINT_MAX, { 0, 0}},
1938 },
1939 {
1940 /* Four shader engines */
1941 { 0, {128, 128}},
1942 { 3, { 64, 128}},
1943 { 5, { 16, 128}},
1944 { 17, { 0, 0}},
1945 { UINT_MAX, { 0, 0}},
1946 },
1947 },
1948 {
1949 /* Two RB / SE */
1950 {
1951 /* One shader engine */
1952 { 0, {128, 128}},
1953 { 2, { 64, 128}},
1954 { 3, { 32, 128}},
1955 { 5, { 16, 128}},
1956 { 33, { 0, 0}},
1957 { UINT_MAX, { 0, 0}},
1958 },
1959 {
1960 /* Two shader engines */
1961 { 0, {128, 128}},
1962 { 3, { 64, 128}},
1963 { 5, { 32, 128}},
1964 { 9, { 16, 128}},
1965 { 33, { 0, 0}},
1966 { UINT_MAX, { 0, 0}},
1967 },
1968 {
1969 /* Four shader engines */
1970 { 0, {256, 256}},
1971 { 2, {128, 256}},
1972 { 3, {128, 128}},
1973 { 5, { 64, 128}},
1974 { 9, { 16, 128}},
1975 { 33, { 0, 0}},
1976 { UINT_MAX, { 0, 0}},
1977 },
1978 },
1979 {
1980 /* Four RB / SE */
1981 {
1982 /* One shader engine */
1983 { 0, {128, 256}},
1984 { 2, {128, 128}},
1985 { 3, { 64, 128}},
1986 { 5, { 32, 128}},
1987 { 9, { 16, 128}},
1988 { 33, { 0, 0}},
1989 { UINT_MAX, { 0, 0}},
1990 },
1991 {
1992 /* Two shader engines */
1993 { 0, {256, 256}},
1994 { 2, {128, 256}},
1995 { 3, {128, 128}},
1996 { 5, { 64, 128}},
1997 { 9, { 32, 128}},
1998 { 17, { 16, 128}},
1999 { 33, { 0, 0}},
2000 { UINT_MAX, { 0, 0}},
2001 },
2002 {
2003 /* Four shader engines */
2004 { 0, {256, 512}},
2005 { 2, {256, 256}},
2006 { 3, {128, 256}},
2007 { 5, {128, 128}},
2008 { 9, { 64, 128}},
2009 { 17, { 16, 128}},
2010 { 33, { 0, 0}},
2011 { UINT_MAX, { 0, 0}},
2012 },
2013 },
2014 };
2015 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2016 {
2017 // One RB / SE
2018 {
2019 // One shader engine
2020 { 0, {128, 256}},
2021 { 2, {128, 128}},
2022 { 4, { 64, 128}},
2023 { 7, { 32, 128}},
2024 { 13, { 16, 128}},
2025 { 49, { 0, 0}},
2026 { UINT_MAX, { 0, 0}},
2027 },
2028 {
2029 // Two shader engines
2030 { 0, {256, 256}},
2031 { 2, {128, 256}},
2032 { 4, {128, 128}},
2033 { 7, { 64, 128}},
2034 { 13, { 32, 128}},
2035 { 25, { 16, 128}},
2036 { 49, { 0, 0}},
2037 { UINT_MAX, { 0, 0}},
2038 },
2039 {
2040 // Four shader engines
2041 { 0, {256, 512}},
2042 { 2, {256, 256}},
2043 { 4, {128, 256}},
2044 { 7, {128, 128}},
2045 { 13, { 64, 128}},
2046 { 25, { 16, 128}},
2047 { 49, { 0, 0}},
2048 { UINT_MAX, { 0, 0}},
2049 },
2050 },
2051 {
2052 // Two RB / SE
2053 {
2054 // One shader engine
2055 { 0, {256, 256}},
2056 { 2, {128, 256}},
2057 { 4, {128, 128}},
2058 { 7, { 64, 128}},
2059 { 13, { 32, 128}},
2060 { 25, { 16, 128}},
2061 { 97, { 0, 0}},
2062 { UINT_MAX, { 0, 0}},
2063 },
2064 {
2065 // Two shader engines
2066 { 0, {256, 512}},
2067 { 2, {256, 256}},
2068 { 4, {128, 256}},
2069 { 7, {128, 128}},
2070 { 13, { 64, 128}},
2071 { 25, { 32, 128}},
2072 { 49, { 16, 128}},
2073 { 97, { 0, 0}},
2074 { UINT_MAX, { 0, 0}},
2075 },
2076 {
2077 // Four shader engines
2078 { 0, {512, 512}},
2079 { 2, {256, 512}},
2080 { 4, {256, 256}},
2081 { 7, {128, 256}},
2082 { 13, {128, 128}},
2083 { 25, { 64, 128}},
2084 { 49, { 16, 128}},
2085 { 97, { 0, 0}},
2086 { UINT_MAX, { 0, 0}},
2087 },
2088 },
2089 {
2090 // Four RB / SE
2091 {
2092 // One shader engine
2093 { 0, {256, 512}},
2094 { 2, {256, 256}},
2095 { 4, {128, 256}},
2096 { 7, {128, 128}},
2097 { 13, { 64, 128}},
2098 { 25, { 32, 128}},
2099 { 49, { 16, 128}},
2100 { UINT_MAX, { 0, 0}},
2101 },
2102 {
2103 // Two shader engines
2104 { 0, {512, 512}},
2105 { 2, {256, 512}},
2106 { 4, {256, 256}},
2107 { 7, {128, 256}},
2108 { 13, {128, 128}},
2109 { 25, { 64, 128}},
2110 { 49, { 32, 128}},
2111 { 97, { 16, 128}},
2112 { UINT_MAX, { 0, 0}},
2113 },
2114 {
2115 // Four shader engines
2116 { 0, {512, 512}},
2117 { 4, {256, 512}},
2118 { 7, {256, 256}},
2119 { 13, {128, 256}},
2120 { 25, {128, 128}},
2121 { 49, { 64, 128}},
2122 { 97, { 16, 128}},
2123 { UINT_MAX, { 0, 0}},
2124 },
2125 },
2126 };
2127
2128 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2129 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2130 VkExtent2D extent = {512, 512};
2131
2132 unsigned log_num_rb_per_se =
2133 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2134 pipeline->device->physical_device->rad_info.max_se);
2135 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2136
2137 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2138 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2139 unsigned effective_samples = total_samples;
2140 unsigned color_bytes_per_pixel = 0;
2141
2142 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2143 if (vkblend) {
2144 for (unsigned i = 0; i < subpass->color_count; i++) {
2145 if (!vkblend->pAttachments[i].colorWriteMask)
2146 continue;
2147
2148 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2149 continue;
2150
2151 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2152 color_bytes_per_pixel += vk_format_get_blocksize(format);
2153 }
2154
2155 /* MSAA images typically don't use all samples all the time. */
2156 if (effective_samples >= 2 && ps_iter_samples <= 1)
2157 effective_samples = 2;
2158 color_bytes_per_pixel *= effective_samples;
2159 }
2160
2161 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2162 while(color_entry->bpp <= color_bytes_per_pixel)
2163 ++color_entry;
2164
2165 extent = color_entry->extent;
2166
2167 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2168 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2169
2170 /* Coefficients taken from AMDVLK */
2171 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2172 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2173 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2174
2175 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2176 while(ds_entry->bpp <= ds_bytes_per_pixel)
2177 ++ds_entry;
2178
2179 extent.width = MIN2(extent.width, ds_entry->extent.width);
2180 extent.height = MIN2(extent.height, ds_entry->extent.height);
2181 }
2182
2183 return extent;
2184 }
2185
2186 static void
2187 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2188 struct radv_pipeline *pipeline,
2189 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2190 {
2191 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2192 return;
2193
2194 uint32_t pa_sc_binner_cntl_0 =
2195 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2196 S_028C44_DISABLE_START_OF_PRIM(1);
2197 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2198
2199 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2200
2201 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2202 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2203 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2204
2205 switch (pipeline->device->physical_device->rad_info.family) {
2206 case CHIP_VEGA10:
2207 context_states_per_bin = 1;
2208 persistent_states_per_bin = 1;
2209 fpovs_per_batch = 63;
2210 break;
2211 case CHIP_RAVEN:
2212 context_states_per_bin = 6;
2213 persistent_states_per_bin = 32;
2214 fpovs_per_batch = 63;
2215 break;
2216 default:
2217 unreachable("unhandled family while determining binning state.");
2218 }
2219
2220 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2221 pa_sc_binner_cntl_0 =
2222 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2223 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2224 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2225 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2226 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2227 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2228 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2229 S_028C44_DISABLE_START_OF_PRIM(1) |
2230 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2231 S_028C44_OPTIMAL_BIN_SELECTION(1);
2232 }
2233
2234 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2235 pa_sc_binner_cntl_0);
2236 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2237 db_dfsm_control);
2238 }
2239
2240
2241 static void
2242 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2243 struct radv_pipeline *pipeline,
2244 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2245 const struct radv_graphics_pipeline_create_info *extra)
2246 {
2247 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2248 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2249 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2250 struct radv_render_pass_attachment *attachment = NULL;
2251 uint32_t db_depth_control = 0, db_stencil_control = 0;
2252 uint32_t db_render_control = 0, db_render_override2 = 0;
2253
2254 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2255 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2256
2257 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2258 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2259
2260 if (vkds && has_depth_attachment) {
2261 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2262 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2263 S_028800_ZFUNC(vkds->depthCompareOp) |
2264 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2265
2266 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2267 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2268 }
2269
2270 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2271 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2272 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2273 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2274 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2275 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2276
2277 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2278 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2279 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2280 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2281 }
2282
2283 if (attachment && extra) {
2284 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2285 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2286
2287 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2288 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2289 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2290 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2291 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2292 }
2293
2294 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2295 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2296
2297 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2298 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2299 }
2300
2301 static void
2302 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2303 struct radv_pipeline *pipeline,
2304 const struct radv_blend_state *blend)
2305 {
2306 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2307 radeon_emit_array(cs, blend->cb_blend_control,
2308 8);
2309 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2310 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2311
2312 if (pipeline->device->physical_device->has_rbplus) {
2313
2314 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2315 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2316
2317 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2318 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2319 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2320 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2321 }
2322
2323 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2324
2325 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2326 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2327 }
2328
2329
2330 static void
2331 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2332 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2333 {
2334 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2335
2336 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2337 S_028810_PS_UCP_MODE(3) |
2338 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2339 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2340 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2341 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2342 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2343
2344 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2345 S_0286D4_FLAT_SHADE_ENA(1) |
2346 S_0286D4_PNT_SPRITE_ENA(1) |
2347 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2348 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2349 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2350 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2351 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2352
2353 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2354 S_028BE4_PIX_CENTER(1) | // TODO verify
2355 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2356 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2357
2358 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2359 S_028814_FACE(vkraster->frontFace) |
2360 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2361 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2362 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2363 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2364 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2365 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2366 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2367 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2368 }
2369
2370
2371 static void
2372 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2373 struct radv_pipeline *pipeline)
2374 {
2375 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2376
2377 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2378 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2379 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2380
2381 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2382 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2383
2384 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2385 uint32_t offset;
2386 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2387 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2388 if (loc->sgpr_idx == -1)
2389 return;
2390 assert(loc->num_sgprs == 1);
2391 assert(!loc->indirect);
2392 switch (pipeline->graphics.ms.num_samples) {
2393 default:
2394 offset = 0;
2395 break;
2396 case 2:
2397 offset = 1;
2398 break;
2399 case 4:
2400 offset = 3;
2401 break;
2402 case 8:
2403 offset = 7;
2404 break;
2405 case 16:
2406 offset = 15;
2407 break;
2408 }
2409
2410 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2411 }
2412 }
2413
2414 static void
2415 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2416 const struct radv_pipeline *pipeline)
2417 {
2418 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2419
2420 uint32_t vgt_primitiveid_en = false;
2421 uint32_t vgt_gs_mode = 0;
2422
2423 if (radv_pipeline_has_gs(pipeline)) {
2424 const struct radv_shader_variant *gs =
2425 pipeline->shaders[MESA_SHADER_GEOMETRY];
2426
2427 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2428 pipeline->device->physical_device->rad_info.chip_class);
2429 } else if (outinfo->export_prim_id) {
2430 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2431 vgt_primitiveid_en = true;
2432 }
2433
2434 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2435 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2436 }
2437
2438 static void
2439 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2440 struct radv_pipeline *pipeline,
2441 struct radv_shader_variant *shader)
2442 {
2443 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2444
2445 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2446 radeon_emit(cs, va >> 8);
2447 radeon_emit(cs, va >> 40);
2448 radeon_emit(cs, shader->rsrc1);
2449 radeon_emit(cs, shader->rsrc2);
2450
2451 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2452 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2453 clip_dist_mask = outinfo->clip_dist_mask;
2454 cull_dist_mask = outinfo->cull_dist_mask;
2455 total_mask = clip_dist_mask | cull_dist_mask;
2456 bool misc_vec_ena = outinfo->writes_pointsize ||
2457 outinfo->writes_layer ||
2458 outinfo->writes_viewport_index;
2459
2460 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2461 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2462
2463 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2464 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2465 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2466 V_02870C_SPI_SHADER_4COMP :
2467 V_02870C_SPI_SHADER_NONE) |
2468 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2469 V_02870C_SPI_SHADER_4COMP :
2470 V_02870C_SPI_SHADER_NONE) |
2471 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2472 V_02870C_SPI_SHADER_4COMP :
2473 V_02870C_SPI_SHADER_NONE));
2474
2475 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2476 S_028818_VTX_W0_FMT(1) |
2477 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2478 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2479 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2480
2481 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2482 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2483 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2484 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2485 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2486 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2487 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2488 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2489 cull_dist_mask << 8 |
2490 clip_dist_mask);
2491
2492 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2493 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2494 outinfo->writes_viewport_index);
2495 }
2496
2497 static void
2498 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2499 struct radv_pipeline *pipeline,
2500 struct radv_shader_variant *shader)
2501 {
2502 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2503
2504 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2505 radeon_emit(cs, va >> 8);
2506 radeon_emit(cs, va >> 40);
2507 radeon_emit(cs, shader->rsrc1);
2508 radeon_emit(cs, shader->rsrc2);
2509 }
2510
2511 static void
2512 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2513 struct radv_pipeline *pipeline,
2514 struct radv_shader_variant *shader,
2515 const struct radv_tessellation_state *tess)
2516 {
2517 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2518 uint32_t rsrc2 = shader->rsrc2;
2519
2520 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2521 radeon_emit(cs, va >> 8);
2522 radeon_emit(cs, va >> 40);
2523
2524 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2525 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2526 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2527 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2528
2529 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2530 radeon_emit(cs, shader->rsrc1);
2531 radeon_emit(cs, rsrc2);
2532 }
2533
2534 static void
2535 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2536 struct radv_pipeline *pipeline,
2537 struct radv_shader_variant *shader,
2538 const struct radv_tessellation_state *tess)
2539 {
2540 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2541
2542 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2543 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2544 radeon_emit(cs, va >> 8);
2545 radeon_emit(cs, va >> 40);
2546
2547 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2548 radeon_emit(cs, shader->rsrc1);
2549 radeon_emit(cs, shader->rsrc2 |
2550 S_00B42C_LDS_SIZE(tess->lds_size));
2551 } else {
2552 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2553 radeon_emit(cs, va >> 8);
2554 radeon_emit(cs, va >> 40);
2555 radeon_emit(cs, shader->rsrc1);
2556 radeon_emit(cs, shader->rsrc2);
2557 }
2558 }
2559
2560 static void
2561 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2562 struct radv_pipeline *pipeline,
2563 const struct radv_tessellation_state *tess)
2564 {
2565 struct radv_shader_variant *vs;
2566
2567 /* Skip shaders merged into HS/GS */
2568 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2569 if (!vs)
2570 return;
2571
2572 if (vs->info.vs.as_ls)
2573 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2574 else if (vs->info.vs.as_es)
2575 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2576 else
2577 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2578 }
2579
2580 static void
2581 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2582 struct radv_pipeline *pipeline,
2583 const struct radv_tessellation_state *tess)
2584 {
2585 if (!radv_pipeline_has_tess(pipeline))
2586 return;
2587
2588 struct radv_shader_variant *tes, *tcs;
2589
2590 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2591 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2592
2593 if (tes) {
2594 if (tes->info.tes.as_es)
2595 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2596 else
2597 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2598 }
2599
2600 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2601
2602 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2603 tess->tf_param);
2604
2605 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2606 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2607 tess->ls_hs_config);
2608 else
2609 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2610 tess->ls_hs_config);
2611
2612 struct radv_userdata_info *loc;
2613
2614 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
2615 if (loc->sgpr_idx != -1) {
2616 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
2617 assert(loc->num_sgprs == 4);
2618 assert(!loc->indirect);
2619 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
2620 radeon_emit(cs, tess->offchip_layout);
2621 radeon_emit(cs, tess->tcs_out_offsets);
2622 radeon_emit(cs, tess->tcs_out_layout);
2623 radeon_emit(cs, tess->tcs_in_layout);
2624 }
2625
2626 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
2627 if (loc->sgpr_idx != -1) {
2628 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
2629 assert(loc->num_sgprs == 1);
2630 assert(!loc->indirect);
2631
2632 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2633 tess->offchip_layout);
2634 }
2635 }
2636
2637 static void
2638 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2639 struct radv_pipeline *pipeline,
2640 const struct radv_gs_state *gs_state)
2641 {
2642 struct radv_shader_variant *gs;
2643 uint64_t va;
2644
2645 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2646 if (!gs)
2647 return;
2648
2649 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2650
2651 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2652 radeon_emit(cs, gsvs_itemsize);
2653 radeon_emit(cs, gsvs_itemsize);
2654 radeon_emit(cs, gsvs_itemsize);
2655
2656 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2657
2658 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2659
2660 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2661 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2662 radeon_emit(cs, gs_vert_itemsize >> 2);
2663 radeon_emit(cs, 0);
2664 radeon_emit(cs, 0);
2665 radeon_emit(cs, 0);
2666
2667 uint32_t gs_num_invocations = gs->info.gs.invocations;
2668 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2669 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2670 S_028B90_ENABLE(gs_num_invocations > 0));
2671
2672 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2673 gs_state->vgt_esgs_ring_itemsize);
2674
2675 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2676
2677 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2678 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2679 radeon_emit(cs, va >> 8);
2680 radeon_emit(cs, va >> 40);
2681
2682 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2683 radeon_emit(cs, gs->rsrc1);
2684 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2685
2686 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2687 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2688 } else {
2689 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2690 radeon_emit(cs, va >> 8);
2691 radeon_emit(cs, va >> 40);
2692 radeon_emit(cs, gs->rsrc1);
2693 radeon_emit(cs, gs->rsrc2);
2694 }
2695
2696 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2697
2698 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2699 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
2700 if (loc->sgpr_idx != -1) {
2701 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
2702 uint32_t num_entries = 64;
2703 bool is_vi = pipeline->device->physical_device->rad_info.chip_class >= VI;
2704
2705 if (is_vi)
2706 num_entries *= stride;
2707
2708 stride = S_008F04_STRIDE(stride);
2709 radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
2710 radeon_emit(cs, stride);
2711 radeon_emit(cs, num_entries);
2712 }
2713 }
2714
2715 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2716 {
2717 uint32_t ps_input_cntl;
2718 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2719 ps_input_cntl = S_028644_OFFSET(offset);
2720 if (flat_shade)
2721 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2722 } else {
2723 /* The input is a DEFAULT_VAL constant. */
2724 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2725 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2726 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2727 ps_input_cntl = S_028644_OFFSET(0x20) |
2728 S_028644_DEFAULT_VAL(offset);
2729 }
2730 return ps_input_cntl;
2731 }
2732
2733 static void
2734 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2735 struct radv_pipeline *pipeline)
2736 {
2737 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2738 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2739 uint32_t ps_input_cntl[32];
2740
2741 unsigned ps_offset = 0;
2742
2743 if (ps->info.info.ps.prim_id_input) {
2744 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2745 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2746 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2747 ++ps_offset;
2748 }
2749 }
2750
2751 if (ps->info.info.ps.layer_input ||
2752 ps->info.info.ps.uses_input_attachments ||
2753 ps->info.info.needs_multiview_view_index) {
2754 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2755 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2756 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2757 else
2758 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2759 ++ps_offset;
2760 }
2761
2762 if (ps->info.info.ps.has_pcoord) {
2763 unsigned val;
2764 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2765 ps_input_cntl[ps_offset] = val;
2766 ps_offset++;
2767 }
2768
2769 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2770 unsigned vs_offset;
2771 bool flat_shade;
2772 if (!(ps->info.fs.input_mask & (1u << i)))
2773 continue;
2774
2775 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2776 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2777 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2778 ++ps_offset;
2779 continue;
2780 }
2781
2782 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2783
2784 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2785 ++ps_offset;
2786 }
2787
2788 if (ps_offset) {
2789 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2790 for (unsigned i = 0; i < ps_offset; i++) {
2791 radeon_emit(cs, ps_input_cntl[i]);
2792 }
2793 }
2794 }
2795
2796 static uint32_t
2797 radv_compute_db_shader_control(const struct radv_device *device,
2798 const struct radv_shader_variant *ps)
2799 {
2800 unsigned z_order;
2801 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2802 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2803 else
2804 z_order = V_02880C_LATE_Z;
2805
2806 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
2807 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
2808 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2809 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
2810 S_02880C_Z_ORDER(z_order) |
2811 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2812 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2813 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
2814 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
2815 }
2816
2817 static void
2818 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2819 struct radv_pipeline *pipeline)
2820 {
2821 struct radv_shader_variant *ps;
2822 uint64_t va;
2823 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2824
2825 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2826 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2827
2828 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2829 radeon_emit(cs, va >> 8);
2830 radeon_emit(cs, va >> 40);
2831 radeon_emit(cs, ps->rsrc1);
2832 radeon_emit(cs, ps->rsrc2);
2833
2834 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2835 radv_compute_db_shader_control(pipeline->device, ps));
2836
2837 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2838 ps->config.spi_ps_input_ena);
2839
2840 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2841 ps->config.spi_ps_input_addr);
2842
2843 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2844 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2845
2846 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2847
2848 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2849 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
2850 ps->info.info.ps.writes_stencil,
2851 ps->info.info.ps.writes_sample_mask));
2852
2853 if (pipeline->device->dfsm_allowed) {
2854 /* optimise this? */
2855 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2856 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2857 }
2858 }
2859
2860 static void
2861 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2862 struct radv_pipeline *pipeline)
2863 {
2864 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2865 return;
2866
2867 unsigned vtx_reuse_depth = 30;
2868 if (radv_pipeline_has_tess(pipeline) &&
2869 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2870 vtx_reuse_depth = 14;
2871 }
2872 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2873 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2874 }
2875
2876 static uint32_t
2877 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
2878 {
2879 uint32_t stages = 0;
2880 if (radv_pipeline_has_tess(pipeline)) {
2881 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2882 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2883
2884 if (radv_pipeline_has_gs(pipeline))
2885 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2886 S_028B54_GS_EN(1) |
2887 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2888 else
2889 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2890
2891 } else if (radv_pipeline_has_gs(pipeline))
2892 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2893 S_028B54_GS_EN(1) |
2894 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2895
2896 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
2897 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2898
2899 return stages;
2900 }
2901
2902 static uint32_t
2903 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
2904 {
2905 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
2906 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
2907
2908 if (!discard_rectangle_info)
2909 return 0xffff;
2910
2911 unsigned mask = 0;
2912
2913 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
2914 /* Interpret i as a bitmask, and then set the bit in the mask if
2915 * that combination of rectangles in which the pixel is contained
2916 * should pass the cliprect test. */
2917 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
2918
2919 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
2920 !relevant_subset)
2921 continue;
2922
2923 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
2924 relevant_subset)
2925 continue;
2926
2927 mask |= 1u << i;
2928 }
2929
2930 return mask;
2931 }
2932
2933 static void
2934 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2935 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2936 const struct radv_graphics_pipeline_create_info *extra,
2937 const struct radv_blend_state *blend,
2938 const struct radv_tessellation_state *tess,
2939 const struct radv_gs_state *gs,
2940 unsigned prim, unsigned gs_out)
2941 {
2942 pipeline->cs.buf = malloc(4 * 256);
2943 pipeline->cs.max_dw = 256;
2944
2945 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2946 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
2947 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
2948 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2949 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
2950 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
2951 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
2952 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
2953 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2954 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2955 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2956 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2957
2958 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2959 S_0286E8_WAVES(pipeline->max_waves) |
2960 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2961
2962 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
2963
2964 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2965 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
2966 } else {
2967 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
2968 }
2969 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
2970
2971 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
2972
2973 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2974 }
2975
2976 static struct radv_ia_multi_vgt_param_helpers
2977 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
2978 const struct radv_tessellation_state *tess,
2979 uint32_t prim)
2980 {
2981 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
2982 const struct radv_device *device = pipeline->device;
2983
2984 if (radv_pipeline_has_tess(pipeline))
2985 ia_multi_vgt_param.primgroup_size = tess->num_patches;
2986 else if (radv_pipeline_has_gs(pipeline))
2987 ia_multi_vgt_param.primgroup_size = 64;
2988 else
2989 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
2990
2991 ia_multi_vgt_param.partial_es_wave = false;
2992 if (pipeline->device->has_distributed_tess) {
2993 if (radv_pipeline_has_gs(pipeline)) {
2994 if (device->physical_device->rad_info.chip_class <= VI)
2995 ia_multi_vgt_param.partial_es_wave = true;
2996 }
2997 }
2998 /* GS requirement. */
2999 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3000 ia_multi_vgt_param.partial_es_wave = true;
3001
3002 ia_multi_vgt_param.wd_switch_on_eop = false;
3003 if (device->physical_device->rad_info.chip_class >= CIK) {
3004 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3005 * 4 shader engines. Set 1 to pass the assertion below.
3006 * The other cases are hardware requirements. */
3007 if (device->physical_device->rad_info.max_se < 4 ||
3008 prim == V_008958_DI_PT_POLYGON ||
3009 prim == V_008958_DI_PT_LINELOOP ||
3010 prim == V_008958_DI_PT_TRIFAN ||
3011 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3012 (pipeline->graphics.prim_restart_enable &&
3013 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3014 (prim != V_008958_DI_PT_POINTLIST &&
3015 prim != V_008958_DI_PT_LINESTRIP &&
3016 prim != V_008958_DI_PT_TRISTRIP))))
3017 ia_multi_vgt_param.wd_switch_on_eop = true;
3018 }
3019
3020 ia_multi_vgt_param.ia_switch_on_eoi = false;
3021 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3022 ia_multi_vgt_param.ia_switch_on_eoi = true;
3023 if (radv_pipeline_has_gs(pipeline) &&
3024 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3025 ia_multi_vgt_param.ia_switch_on_eoi = true;
3026 if (radv_pipeline_has_tess(pipeline)) {
3027 /* SWITCH_ON_EOI must be set if PrimID is used. */
3028 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3029 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3030 ia_multi_vgt_param.ia_switch_on_eoi = true;
3031 }
3032
3033 ia_multi_vgt_param.partial_vs_wave = false;
3034 if (radv_pipeline_has_tess(pipeline)) {
3035 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3036 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3037 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3038 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3039 radv_pipeline_has_gs(pipeline))
3040 ia_multi_vgt_param.partial_vs_wave = true;
3041 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3042 if (device->has_distributed_tess) {
3043 if (radv_pipeline_has_gs(pipeline)) {
3044 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3045 device->physical_device->rad_info.family == CHIP_FIJI ||
3046 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3047 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3048 device->physical_device->rad_info.family == CHIP_POLARIS12)
3049 ia_multi_vgt_param.partial_vs_wave = true;
3050 } else {
3051 ia_multi_vgt_param.partial_vs_wave = true;
3052 }
3053 }
3054 }
3055
3056 ia_multi_vgt_param.base =
3057 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3058 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3059 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3060 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3061 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3062
3063 return ia_multi_vgt_param;
3064 }
3065
3066
3067 static void
3068 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3069 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3070 {
3071 const VkPipelineVertexInputStateCreateInfo *vi_info =
3072 pCreateInfo->pVertexInputState;
3073 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3074
3075 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3076 const VkVertexInputAttributeDescription *desc =
3077 &vi_info->pVertexAttributeDescriptions[i];
3078 unsigned loc = desc->location;
3079 const struct vk_format_description *format_desc;
3080 int first_non_void;
3081 uint32_t num_format, data_format;
3082 format_desc = vk_format_description(desc->format);
3083 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3084
3085 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3086 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3087
3088 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3089 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3090 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3091 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3092 S_008F0C_NUM_FORMAT(num_format) |
3093 S_008F0C_DATA_FORMAT(data_format);
3094 velems->format_size[loc] = format_desc->block.bits / 8;
3095 velems->offset[loc] = desc->offset;
3096 velems->binding[loc] = desc->binding;
3097 velems->count = MAX2(velems->count, loc + 1);
3098 }
3099
3100 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3101 const VkVertexInputBindingDescription *desc =
3102 &vi_info->pVertexBindingDescriptions[i];
3103
3104 pipeline->binding_stride[desc->binding] = desc->stride;
3105 }
3106 }
3107
3108 static VkResult
3109 radv_pipeline_init(struct radv_pipeline *pipeline,
3110 struct radv_device *device,
3111 struct radv_pipeline_cache *cache,
3112 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3113 const struct radv_graphics_pipeline_create_info *extra,
3114 const VkAllocationCallbacks *alloc)
3115 {
3116 VkResult result;
3117 bool has_view_index = false;
3118
3119 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3120 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3121 if (subpass->view_mask)
3122 has_view_index = true;
3123 if (alloc == NULL)
3124 alloc = &device->alloc;
3125
3126 pipeline->device = device;
3127 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3128 assert(pipeline->layout);
3129
3130 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3131
3132 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3133 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3134 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3135 pStages[stage] = &pCreateInfo->pStages[i];
3136 }
3137
3138 radv_create_shaders(pipeline, device, cache,
3139 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3140 pStages);
3141
3142 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3143 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
3144 uint32_t gs_out;
3145 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3146
3147 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3148
3149 if (radv_pipeline_has_gs(pipeline)) {
3150 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3151 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3152 } else {
3153 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3154 }
3155 if (extra && extra->use_rectlist) {
3156 prim = V_008958_DI_PT_RECTLIST;
3157 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3158 pipeline->graphics.can_use_guardband = true;
3159 }
3160 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3161 /* prim vertex count will need TESS changes */
3162 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3163
3164 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3165
3166 /* Ensure that some export memory is always allocated, for two reasons:
3167 *
3168 * 1) Correctness: The hardware ignores the EXEC mask if no export
3169 * memory is allocated, so KILL and alpha test do not work correctly
3170 * without this.
3171 * 2) Performance: Every shader needs at least a NULL export, even when
3172 * it writes no color/depth output. The NULL export instruction
3173 * stalls without this setting.
3174 *
3175 * Don't add this to CB_SHADER_MASK.
3176 */
3177 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3178 if (!blend.spi_shader_col_format) {
3179 if (!ps->info.info.ps.writes_z &&
3180 !ps->info.info.ps.writes_stencil &&
3181 !ps->info.info.ps.writes_sample_mask)
3182 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3183 }
3184
3185 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3186 if (pipeline->shaders[i]) {
3187 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3188 }
3189 }
3190
3191 struct radv_gs_state gs = {0};
3192 if (radv_pipeline_has_gs(pipeline)) {
3193 gs = calculate_gs_info(pCreateInfo, pipeline);
3194 calculate_gs_ring_sizes(pipeline, &gs);
3195 }
3196
3197 struct radv_tessellation_state tess = {0};
3198 if (radv_pipeline_has_tess(pipeline)) {
3199 if (prim == V_008958_DI_PT_PATCH) {
3200 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3201 pipeline->graphics.prim_vertex_count.incr = 1;
3202 }
3203 tess = calculate_tess_state(pipeline, pCreateInfo);
3204 }
3205
3206 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3207
3208 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3209
3210 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3211 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3212
3213 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3214 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3215 if (loc->sgpr_idx != -1) {
3216 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3217 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3218 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3219 pipeline->graphics.vtx_emit_num = 3;
3220 else
3221 pipeline->graphics.vtx_emit_num = 2;
3222 }
3223
3224 result = radv_pipeline_scratch_init(device, pipeline);
3225 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3226
3227 return result;
3228 }
3229
3230 VkResult
3231 radv_graphics_pipeline_create(
3232 VkDevice _device,
3233 VkPipelineCache _cache,
3234 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3235 const struct radv_graphics_pipeline_create_info *extra,
3236 const VkAllocationCallbacks *pAllocator,
3237 VkPipeline *pPipeline)
3238 {
3239 RADV_FROM_HANDLE(radv_device, device, _device);
3240 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3241 struct radv_pipeline *pipeline;
3242 VkResult result;
3243
3244 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3245 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3246 if (pipeline == NULL)
3247 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3248
3249 result = radv_pipeline_init(pipeline, device, cache,
3250 pCreateInfo, extra, pAllocator);
3251 if (result != VK_SUCCESS) {
3252 radv_pipeline_destroy(device, pipeline, pAllocator);
3253 return result;
3254 }
3255
3256 *pPipeline = radv_pipeline_to_handle(pipeline);
3257
3258 return VK_SUCCESS;
3259 }
3260
3261 VkResult radv_CreateGraphicsPipelines(
3262 VkDevice _device,
3263 VkPipelineCache pipelineCache,
3264 uint32_t count,
3265 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3266 const VkAllocationCallbacks* pAllocator,
3267 VkPipeline* pPipelines)
3268 {
3269 VkResult result = VK_SUCCESS;
3270 unsigned i = 0;
3271
3272 for (; i < count; i++) {
3273 VkResult r;
3274 r = radv_graphics_pipeline_create(_device,
3275 pipelineCache,
3276 &pCreateInfos[i],
3277 NULL, pAllocator, &pPipelines[i]);
3278 if (r != VK_SUCCESS) {
3279 result = r;
3280 pPipelines[i] = VK_NULL_HANDLE;
3281 }
3282 }
3283
3284 return result;
3285 }
3286
3287
3288 static void
3289 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3290 {
3291 struct radv_shader_variant *compute_shader;
3292 struct radv_device *device = pipeline->device;
3293 unsigned compute_resource_limits;
3294 unsigned waves_per_threadgroup;
3295 uint64_t va;
3296
3297 pipeline->cs.buf = malloc(20 * 4);
3298 pipeline->cs.max_dw = 20;
3299
3300 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3301 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3302
3303 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3304 radeon_emit(&pipeline->cs, va >> 8);
3305 radeon_emit(&pipeline->cs, va >> 40);
3306
3307 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3308 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3309 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3310
3311 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3312 S_00B860_WAVES(pipeline->max_waves) |
3313 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3314
3315 /* Calculate best compute resource limits. */
3316 waves_per_threadgroup =
3317 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3318 compute_shader->info.cs.block_size[1] *
3319 compute_shader->info.cs.block_size[2], 64);
3320 compute_resource_limits =
3321 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3322
3323 if (device->physical_device->rad_info.chip_class >= CIK) {
3324 unsigned num_cu_per_se =
3325 device->physical_device->rad_info.num_good_compute_units /
3326 device->physical_device->rad_info.max_se;
3327
3328 /* Force even distribution on all SIMDs in CU if the workgroup
3329 * size is 64. This has shown some good improvements if # of
3330 * CUs per SE is not a multiple of 4.
3331 */
3332 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3333 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3334 }
3335
3336 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3337 compute_resource_limits);
3338
3339 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3340 radeon_emit(&pipeline->cs,
3341 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3342 radeon_emit(&pipeline->cs,
3343 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3344 radeon_emit(&pipeline->cs,
3345 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3346
3347 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3348 }
3349
3350 static VkResult radv_compute_pipeline_create(
3351 VkDevice _device,
3352 VkPipelineCache _cache,
3353 const VkComputePipelineCreateInfo* pCreateInfo,
3354 const VkAllocationCallbacks* pAllocator,
3355 VkPipeline* pPipeline)
3356 {
3357 RADV_FROM_HANDLE(radv_device, device, _device);
3358 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3359 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3360 struct radv_pipeline *pipeline;
3361 VkResult result;
3362
3363 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3364 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3365 if (pipeline == NULL)
3366 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3367
3368 pipeline->device = device;
3369 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3370 assert(pipeline->layout);
3371
3372 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3373 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3374
3375 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3376 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3377 result = radv_pipeline_scratch_init(device, pipeline);
3378 if (result != VK_SUCCESS) {
3379 radv_pipeline_destroy(device, pipeline, pAllocator);
3380 return result;
3381 }
3382
3383 radv_compute_generate_pm4(pipeline);
3384
3385 *pPipeline = radv_pipeline_to_handle(pipeline);
3386
3387 return VK_SUCCESS;
3388 }
3389
3390 VkResult radv_CreateComputePipelines(
3391 VkDevice _device,
3392 VkPipelineCache pipelineCache,
3393 uint32_t count,
3394 const VkComputePipelineCreateInfo* pCreateInfos,
3395 const VkAllocationCallbacks* pAllocator,
3396 VkPipeline* pPipelines)
3397 {
3398 VkResult result = VK_SUCCESS;
3399
3400 unsigned i = 0;
3401 for (; i < count; i++) {
3402 VkResult r;
3403 r = radv_compute_pipeline_create(_device, pipelineCache,
3404 &pCreateInfos[i],
3405 pAllocator, &pPipelines[i]);
3406 if (r != VK_SUCCESS) {
3407 result = r;
3408 pPipelines[i] = VK_NULL_HANDLE;
3409 }
3410 }
3411
3412 return result;
3413 }