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radv: force persample shading when required.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107 void radv_DestroyPipeline(
108 VkDevice _device,
109 VkPipeline _pipeline,
110 const VkAllocationCallbacks* pAllocator)
111 {
112 RADV_FROM_HANDLE(radv_device, device, _device);
113 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
114
115 if (!_pipeline)
116 return;
117
118 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
119 if (pipeline->shaders[i])
120 radv_shader_variant_destroy(device, pipeline->shaders[i]);
121
122 vk_free2(&device->alloc, pAllocator, pipeline);
123 }
124
125
126 static void
127 radv_optimize_nir(struct nir_shader *shader)
128 {
129 bool progress;
130
131 do {
132 progress = false;
133
134 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
135 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
136 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
137
138 NIR_PASS(progress, shader, nir_copy_prop);
139 NIR_PASS(progress, shader, nir_opt_remove_phis);
140 NIR_PASS(progress, shader, nir_opt_dce);
141 NIR_PASS(progress, shader, nir_opt_dead_cf);
142 NIR_PASS(progress, shader, nir_opt_cse);
143 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
144 NIR_PASS(progress, shader, nir_opt_algebraic);
145 NIR_PASS(progress, shader, nir_opt_constant_folding);
146 NIR_PASS(progress, shader, nir_opt_undef);
147 NIR_PASS(progress, shader, nir_opt_conditional_discard);
148 } while (progress);
149 }
150
151 static nir_shader *
152 radv_shader_compile_to_nir(struct radv_device *device,
153 struct radv_shader_module *module,
154 const char *entrypoint_name,
155 gl_shader_stage stage,
156 const VkSpecializationInfo *spec_info,
157 bool dump)
158 {
159 if (strcmp(entrypoint_name, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
161 }
162
163 nir_shader *nir;
164 nir_function *entry_point;
165 if (module->nir) {
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
169 nir = module->nir;
170 nir->options = &nir_options;
171 nir_validate_shader(nir);
172
173 assert(exec_list_length(&nir->functions) == 1);
174 struct exec_node *node = exec_list_get_head(&nir->functions);
175 entry_point = exec_node_data(nir_function, node, node);
176 } else {
177 uint32_t *spirv = (uint32_t *) module->data;
178 assert(module->size % 4 == 0);
179
180 uint32_t num_spec_entries = 0;
181 struct nir_spirv_specialization *spec_entries = NULL;
182 if (spec_info && spec_info->mapEntryCount > 0) {
183 num_spec_entries = spec_info->mapEntryCount;
184 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
185 for (uint32_t i = 0; i < num_spec_entries; i++) {
186 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
187 const void *data = spec_info->pData + entry.offset;
188 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
189
190 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
191 spec_entries[i].data = *(const uint32_t *)data;
192 }
193 }
194
195 entry_point = spirv_to_nir(spirv, module->size / 4,
196 spec_entries, num_spec_entries,
197 stage, entrypoint_name, &nir_options);
198 nir = entry_point->shader;
199 assert(nir->stage == stage);
200 nir_validate_shader(nir);
201
202 free(spec_entries);
203
204 nir_lower_returns(nir);
205 nir_validate_shader(nir);
206
207 nir_inline_functions(nir);
208 nir_validate_shader(nir);
209
210 /* Pick off the single entrypoint that we want */
211 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
212 if (func != entry_point)
213 exec_node_remove(&func->node);
214 }
215 assert(exec_list_length(&nir->functions) == 1);
216 entry_point->name = ralloc_strdup(entry_point, "main");
217
218 nir_remove_dead_variables(nir, nir_var_shader_in);
219 nir_remove_dead_variables(nir, nir_var_shader_out);
220 nir_remove_dead_variables(nir, nir_var_system_value);
221 nir_validate_shader(nir);
222
223 nir_lower_system_values(nir);
224 nir_validate_shader(nir);
225 }
226
227 /* Vulkan uses the separate-shader linking model */
228 nir->info->separate_shader = true;
229
230 // nir = brw_preprocess_nir(compiler, nir);
231
232 nir_shader_gather_info(nir, entry_point->impl);
233
234 nir_variable_mode indirect_mask = 0;
235 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
236 indirect_mask |= nir_var_shader_in;
237 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
238 indirect_mask |= nir_var_local;
239
240 nir_lower_indirect_derefs(nir, indirect_mask);
241
242 static const nir_lower_tex_options tex_options = {
243 .lower_txp = ~0,
244 };
245
246 nir_lower_tex(nir, &tex_options);
247
248 nir_lower_vars_to_ssa(nir);
249 nir_lower_var_copies(nir);
250 nir_lower_global_vars_to_local(nir);
251 nir_remove_dead_variables(nir, nir_var_local);
252 radv_optimize_nir(nir);
253
254 if (dump)
255 nir_print_shader(nir, stderr);
256
257 return nir;
258 }
259
260 static const char *radv_get_shader_name(struct radv_shader_variant *var,
261 gl_shader_stage stage)
262 {
263 switch (stage) {
264 case MESA_SHADER_VERTEX: return "Vertex Shader as VS";
265 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
266 case MESA_SHADER_COMPUTE: return "Compute Shader";
267 default:
268 return "Unknown shader";
269 };
270
271 }
272 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
273 {
274 unsigned lds_increment = device->instance->physicalDevice.rad_info.chip_class >= CIK ? 512 : 256;
275 struct radv_shader_variant *var;
276 struct ac_shader_config *conf;
277 int i;
278 FILE *file = stderr;
279 unsigned max_simd_waves = 10;
280 unsigned lds_per_wave = 0;
281
282 for (i = 0; i < MESA_SHADER_STAGES; i++) {
283 if (!pipeline->shaders[i])
284 continue;
285 var = pipeline->shaders[i];
286
287 conf = &var->config;
288
289 if (i == MESA_SHADER_FRAGMENT) {
290 lds_per_wave = conf->lds_size * lds_increment +
291 align(var->info.fs.num_interp * 48, lds_increment);
292 }
293
294 if (conf->num_sgprs) {
295 if (device->instance->physicalDevice.rad_info.chip_class >= VI)
296 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
297 else
298 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
299 }
300
301 if (conf->num_vgprs)
302 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
303
304 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
305 * that PS can use.
306 */
307 if (lds_per_wave)
308 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
309
310 fprintf(file, "\n%s:\n",
311 radv_get_shader_name(var, i));
312 if (i == MESA_SHADER_FRAGMENT) {
313 fprintf(file, "*** SHADER CONFIG ***\n"
314 "SPI_PS_INPUT_ADDR = 0x%04x\n"
315 "SPI_PS_INPUT_ENA = 0x%04x\n",
316 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
317 }
318 fprintf(file, "*** SHADER STATS ***\n"
319 "SGPRS: %d\n"
320 "VGPRS: %d\n"
321 "Spilled SGPRs: %d\n"
322 "Spilled VGPRs: %d\n"
323 "Code Size: %d bytes\n"
324 "LDS: %d blocks\n"
325 "Scratch: %d bytes per wave\n"
326 "Max Waves: %d\n"
327 "********************\n\n\n",
328 conf->num_sgprs, conf->num_vgprs,
329 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
330 conf->lds_size, conf->scratch_bytes_per_wave,
331 max_simd_waves);
332 }
333 }
334
335 void radv_shader_variant_destroy(struct radv_device *device,
336 struct radv_shader_variant *variant)
337 {
338 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
339 return;
340
341 device->ws->buffer_destroy(variant->bo);
342 free(variant);
343 }
344
345 static
346 struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
347 struct nir_shader *shader,
348 struct radv_pipeline_layout *layout,
349 const union ac_shader_variant_key *key,
350 void** code_out,
351 unsigned *code_size_out,
352 bool dump)
353 {
354 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
355 enum radeon_family chip_family = device->instance->physicalDevice.rad_info.family;
356 LLVMTargetMachineRef tm;
357 if (!variant)
358 return NULL;
359
360 struct ac_nir_compiler_options options = {0};
361 options.layout = layout;
362 if (key)
363 options.key = *key;
364
365 struct ac_shader_binary binary;
366
367 options.unsafe_math = env_var_as_boolean("RADV_UNSAFE_MATH", false);
368 options.family = chip_family;
369 options.chip_class = device->instance->physicalDevice.rad_info.chip_class;
370 tm = ac_create_target_machine(chip_family);
371 ac_compile_nir_shader(tm, &binary, &variant->config,
372 &variant->info, shader, &options, dump);
373 LLVMDisposeTargetMachine(tm);
374
375 variant->code_size = binary.code_size;
376 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
377 unsigned vgpr_comp_cnt = 0;
378
379 if (scratch_enabled)
380 radv_finishme("shader scratch space");
381 switch (shader->stage) {
382 case MESA_SHADER_VERTEX:
383 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
384 S_00B12C_SCRATCH_EN(scratch_enabled);
385 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
386 break;
387 case MESA_SHADER_FRAGMENT:
388 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
389 S_00B12C_SCRATCH_EN(scratch_enabled);
390 break;
391 case MESA_SHADER_COMPUTE:
392 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
393 S_00B84C_SCRATCH_EN(scratch_enabled) |
394 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
395 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
396 S_00B84C_TG_SIZE_EN(1) |
397 S_00B84C_LDS_SIZE(variant->config.lds_size);
398 break;
399 default:
400 unreachable("unsupported shader type");
401 break;
402 }
403
404 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
405 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
406 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
407 S_00B848_DX10_CLAMP(1) |
408 S_00B848_FLOAT_MODE(variant->config.float_mode);
409
410 variant->bo = device->ws->buffer_create(device->ws, binary.code_size, 256,
411 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
412
413 void *ptr = device->ws->buffer_map(variant->bo);
414 memcpy(ptr, binary.code, binary.code_size);
415 device->ws->buffer_unmap(variant->bo);
416
417 if (code_out) {
418 *code_out = binary.code;
419 *code_size_out = binary.code_size;
420 } else
421 free(binary.code);
422 free(binary.config);
423 free(binary.rodata);
424 free(binary.global_symbol_offsets);
425 free(binary.relocs);
426 free(binary.disasm_string);
427 variant->ref_count = 1;
428 return variant;
429 }
430
431
432 static struct radv_shader_variant *
433 radv_pipeline_compile(struct radv_pipeline *pipeline,
434 struct radv_pipeline_cache *cache,
435 struct radv_shader_module *module,
436 const char *entrypoint,
437 gl_shader_stage stage,
438 const VkSpecializationInfo *spec_info,
439 struct radv_pipeline_layout *layout,
440 const union ac_shader_variant_key *key,
441 bool dump)
442 {
443 unsigned char sha1[20];
444 struct radv_shader_variant *variant;
445 nir_shader *nir;
446 void *code = NULL;
447 unsigned code_size = 0;
448
449 if (module->nir)
450 _mesa_sha1_compute(module->nir->info->name,
451 strlen(module->nir->info->name),
452 module->sha1);
453
454 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key);
455
456 if (cache) {
457 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
458 cache,
459 sha1);
460 if (variant)
461 return variant;
462 }
463
464 nir = radv_shader_compile_to_nir(pipeline->device,
465 module, entrypoint, stage,
466 spec_info, dump);
467 if (nir == NULL)
468 return NULL;
469
470 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
471 &code, &code_size, dump);
472 if (!module->nir)
473 ralloc_free(nir);
474
475 if (variant && cache)
476 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
477 code, code_size);
478
479 if (code)
480 free(code);
481 return variant;
482 }
483
484 static uint32_t si_translate_blend_function(VkBlendOp op)
485 {
486 switch (op) {
487 case VK_BLEND_OP_ADD:
488 return V_028780_COMB_DST_PLUS_SRC;
489 case VK_BLEND_OP_SUBTRACT:
490 return V_028780_COMB_SRC_MINUS_DST;
491 case VK_BLEND_OP_REVERSE_SUBTRACT:
492 return V_028780_COMB_DST_MINUS_SRC;
493 case VK_BLEND_OP_MIN:
494 return V_028780_COMB_MIN_DST_SRC;
495 case VK_BLEND_OP_MAX:
496 return V_028780_COMB_MAX_DST_SRC;
497 default:
498 return 0;
499 }
500 }
501
502 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
503 {
504 switch (factor) {
505 case VK_BLEND_FACTOR_ZERO:
506 return V_028780_BLEND_ZERO;
507 case VK_BLEND_FACTOR_ONE:
508 return V_028780_BLEND_ONE;
509 case VK_BLEND_FACTOR_SRC_COLOR:
510 return V_028780_BLEND_SRC_COLOR;
511 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
512 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
513 case VK_BLEND_FACTOR_DST_COLOR:
514 return V_028780_BLEND_DST_COLOR;
515 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
516 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
517 case VK_BLEND_FACTOR_SRC_ALPHA:
518 return V_028780_BLEND_SRC_ALPHA;
519 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
520 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
521 case VK_BLEND_FACTOR_DST_ALPHA:
522 return V_028780_BLEND_DST_ALPHA;
523 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
524 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
525 case VK_BLEND_FACTOR_CONSTANT_COLOR:
526 return V_028780_BLEND_CONSTANT_COLOR;
527 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
528 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
529 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
530 return V_028780_BLEND_CONSTANT_ALPHA;
531 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
532 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
533 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
534 return V_028780_BLEND_SRC_ALPHA_SATURATE;
535 case VK_BLEND_FACTOR_SRC1_COLOR:
536 return V_028780_BLEND_SRC1_COLOR;
537 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
538 return V_028780_BLEND_INV_SRC1_COLOR;
539 case VK_BLEND_FACTOR_SRC1_ALPHA:
540 return V_028780_BLEND_SRC1_ALPHA;
541 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
542 return V_028780_BLEND_INV_SRC1_ALPHA;
543 default:
544 return 0;
545 }
546 }
547
548 static bool is_dual_src(VkBlendFactor factor)
549 {
550 switch (factor) {
551 case VK_BLEND_FACTOR_SRC1_COLOR:
552 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
553 case VK_BLEND_FACTOR_SRC1_ALPHA:
554 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
555 return true;
556 default:
557 return false;
558 }
559 }
560
561 static unsigned si_choose_spi_color_format(VkFormat vk_format,
562 bool blend_enable,
563 bool blend_need_alpha)
564 {
565 const struct vk_format_description *desc = vk_format_description(vk_format);
566 unsigned format, ntype, swap;
567
568 /* Alpha is needed for alpha-to-coverage.
569 * Blending may be with or without alpha.
570 */
571 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
572 unsigned alpha = 0; /* exports alpha, but may not support blending */
573 unsigned blend = 0; /* supports blending, but may not export alpha */
574 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
575
576 format = radv_translate_colorformat(vk_format);
577 ntype = radv_translate_color_numformat(vk_format, desc,
578 vk_format_get_first_non_void_channel(vk_format));
579 swap = radv_translate_colorswap(vk_format, false);
580
581 /* Choose the SPI color formats. These are required values for Stoney/RB+.
582 * Other chips have multiple choices, though they are not necessarily better.
583 */
584 switch (format) {
585 case V_028C70_COLOR_5_6_5:
586 case V_028C70_COLOR_1_5_5_5:
587 case V_028C70_COLOR_5_5_5_1:
588 case V_028C70_COLOR_4_4_4_4:
589 case V_028C70_COLOR_10_11_11:
590 case V_028C70_COLOR_11_11_10:
591 case V_028C70_COLOR_8:
592 case V_028C70_COLOR_8_8:
593 case V_028C70_COLOR_8_8_8_8:
594 case V_028C70_COLOR_10_10_10_2:
595 case V_028C70_COLOR_2_10_10_10:
596 if (ntype == V_028C70_NUMBER_UINT)
597 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
598 else if (ntype == V_028C70_NUMBER_SINT)
599 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
600 else
601 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
602 break;
603
604 case V_028C70_COLOR_16:
605 case V_028C70_COLOR_16_16:
606 case V_028C70_COLOR_16_16_16_16:
607 if (ntype == V_028C70_NUMBER_UNORM ||
608 ntype == V_028C70_NUMBER_SNORM) {
609 /* UNORM16 and SNORM16 don't support blending */
610 if (ntype == V_028C70_NUMBER_UNORM)
611 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
612 else
613 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
614
615 /* Use 32 bits per channel for blending. */
616 if (format == V_028C70_COLOR_16) {
617 if (swap == V_028C70_SWAP_STD) { /* R */
618 blend = V_028714_SPI_SHADER_32_R;
619 blend_alpha = V_028714_SPI_SHADER_32_AR;
620 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
621 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
622 else
623 assert(0);
624 } else if (format == V_028C70_COLOR_16_16) {
625 if (swap == V_028C70_SWAP_STD) { /* RG */
626 blend = V_028714_SPI_SHADER_32_GR;
627 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
628 } else if (swap == V_028C70_SWAP_ALT) /* RA */
629 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
630 else
631 assert(0);
632 } else /* 16_16_16_16 */
633 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
634 } else if (ntype == V_028C70_NUMBER_UINT)
635 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
636 else if (ntype == V_028C70_NUMBER_SINT)
637 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
638 else if (ntype == V_028C70_NUMBER_FLOAT)
639 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
640 else
641 assert(0);
642 break;
643
644 case V_028C70_COLOR_32:
645 if (swap == V_028C70_SWAP_STD) { /* R */
646 blend = normal = V_028714_SPI_SHADER_32_R;
647 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
648 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
649 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
650 else
651 assert(0);
652 break;
653
654 case V_028C70_COLOR_32_32:
655 if (swap == V_028C70_SWAP_STD) { /* RG */
656 blend = normal = V_028714_SPI_SHADER_32_GR;
657 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
658 } else if (swap == V_028C70_SWAP_ALT) /* RA */
659 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
660 else
661 assert(0);
662 break;
663
664 case V_028C70_COLOR_32_32_32_32:
665 case V_028C70_COLOR_8_24:
666 case V_028C70_COLOR_24_8:
667 case V_028C70_COLOR_X24_8_32_FLOAT:
668 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
669 break;
670
671 default:
672 unreachable("unhandled blend format");
673 }
674
675 if (blend_enable && blend_need_alpha)
676 return blend_alpha;
677 else if(blend_need_alpha)
678 return alpha;
679 else if(blend_enable)
680 return blend;
681 else
682 return normal;
683 }
684
685 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
686 {
687 unsigned i, cb_shader_mask = 0;
688
689 for (i = 0; i < 8; i++) {
690 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
691 case V_028714_SPI_SHADER_ZERO:
692 break;
693 case V_028714_SPI_SHADER_32_R:
694 cb_shader_mask |= 0x1 << (i * 4);
695 break;
696 case V_028714_SPI_SHADER_32_GR:
697 cb_shader_mask |= 0x3 << (i * 4);
698 break;
699 case V_028714_SPI_SHADER_32_AR:
700 cb_shader_mask |= 0x9 << (i * 4);
701 break;
702 case V_028714_SPI_SHADER_FP16_ABGR:
703 case V_028714_SPI_SHADER_UNORM16_ABGR:
704 case V_028714_SPI_SHADER_SNORM16_ABGR:
705 case V_028714_SPI_SHADER_UINT16_ABGR:
706 case V_028714_SPI_SHADER_SINT16_ABGR:
707 case V_028714_SPI_SHADER_32_ABGR:
708 cb_shader_mask |= 0xf << (i * 4);
709 break;
710 default:
711 assert(0);
712 }
713 }
714 return cb_shader_mask;
715 }
716
717 static void
718 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
719 const VkGraphicsPipelineCreateInfo *pCreateInfo,
720 uint32_t blend_enable,
721 uint32_t blend_need_alpha,
722 bool single_cb_enable,
723 bool blend_mrt0_is_dual_src)
724 {
725 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
726 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
727 struct radv_blend_state *blend = &pipeline->graphics.blend;
728 unsigned col_format = 0;
729
730 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
731 struct radv_render_pass_attachment *attachment;
732 unsigned cf;
733
734 attachment = pass->attachments + subpass->color_attachments[i].attachment;
735
736 cf = si_choose_spi_color_format(attachment->format,
737 blend_enable & (1 << i),
738 blend_need_alpha & (1 << i));
739
740 col_format |= cf << (4 * i);
741 }
742
743 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
744
745 if (blend_mrt0_is_dual_src)
746 col_format |= (col_format & 0xf) << 4;
747 if (!col_format)
748 col_format |= V_028714_SPI_SHADER_32_R;
749 blend->spi_shader_col_format = col_format;
750 }
751
752 static bool
753 format_is_int8(VkFormat format)
754 {
755 const struct vk_format_description *desc = vk_format_description(format);
756 int channel = vk_format_get_first_non_void_channel(format);
757
758 return channel >= 0 && desc->channel[channel].pure_integer &&
759 desc->channel[channel].size == 8;
760 }
761
762 unsigned radv_format_meta_fs_key(VkFormat format)
763 {
764 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
765 bool is_int8 = format_is_int8(format);
766
767 return col_format + (is_int8 ? 3 : 0);
768 }
769
770 static unsigned
771 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
772 {
773 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
774 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
775 unsigned is_int8 = 0;
776
777 for (unsigned i = 0; i < subpass->color_count; ++i) {
778 struct radv_render_pass_attachment *attachment;
779
780 attachment = pass->attachments + subpass->color_attachments[i].attachment;
781
782 if (format_is_int8(attachment->format))
783 is_int8 |= 1 << i;
784 }
785
786 return is_int8;
787 }
788
789 static void
790 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
791 const VkGraphicsPipelineCreateInfo *pCreateInfo,
792 const struct radv_graphics_pipeline_create_info *extra)
793 {
794 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
795 struct radv_blend_state *blend = &pipeline->graphics.blend;
796 unsigned mode = V_028808_CB_NORMAL;
797 uint32_t blend_enable = 0, blend_need_alpha = 0;
798 bool blend_mrt0_is_dual_src = false;
799 int i;
800 bool single_cb_enable = false;
801
802 if (!vkblend)
803 return;
804
805 if (extra && extra->custom_blend_mode) {
806 single_cb_enable = true;
807 mode = extra->custom_blend_mode;
808 }
809 blend->cb_color_control = 0;
810 if (vkblend->logicOpEnable)
811 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
812 else
813 blend->cb_color_control |= S_028808_ROP3(0xcc);
814
815 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
816 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
817 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
818 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
819
820 blend->cb_target_mask = 0;
821 for (i = 0; i < vkblend->attachmentCount; i++) {
822 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
823 unsigned blend_cntl = 0;
824 VkBlendOp eqRGB = att->colorBlendOp;
825 VkBlendFactor srcRGB = att->srcColorBlendFactor;
826 VkBlendFactor dstRGB = att->dstColorBlendFactor;
827 VkBlendOp eqA = att->alphaBlendOp;
828 VkBlendFactor srcA = att->srcAlphaBlendFactor;
829 VkBlendFactor dstA = att->dstAlphaBlendFactor;
830
831 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
832
833 if (!att->colorWriteMask)
834 continue;
835
836 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
837 if (!att->blendEnable) {
838 blend->cb_blend_control[i] = blend_cntl;
839 continue;
840 }
841
842 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
843 if (i == 0)
844 blend_mrt0_is_dual_src = true;
845
846 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
847 srcRGB = VK_BLEND_FACTOR_ONE;
848 dstRGB = VK_BLEND_FACTOR_ONE;
849 }
850 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
851 srcA = VK_BLEND_FACTOR_ONE;
852 dstA = VK_BLEND_FACTOR_ONE;
853 }
854
855 blend_cntl |= S_028780_ENABLE(1);
856
857 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
858 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
859 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
860 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
861 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
862 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
863 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
864 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
865 }
866 blend->cb_blend_control[i] = blend_cntl;
867
868 blend_enable |= 1 << i;
869
870 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
871 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
872 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
873 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
874 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
875 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
876 blend_need_alpha |= 1 << i;
877 }
878 for (i = vkblend->attachmentCount; i < 8; i++)
879 blend->cb_blend_control[i] = 0;
880
881 if (blend->cb_target_mask)
882 blend->cb_color_control |= S_028808_MODE(mode);
883 else
884 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
885
886 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
887 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
888 }
889
890 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
891 {
892 switch (op) {
893 case VK_STENCIL_OP_KEEP:
894 return V_02842C_STENCIL_KEEP;
895 case VK_STENCIL_OP_ZERO:
896 return V_02842C_STENCIL_ZERO;
897 case VK_STENCIL_OP_REPLACE:
898 return V_02842C_STENCIL_REPLACE_TEST;
899 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
900 return V_02842C_STENCIL_ADD_CLAMP;
901 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
902 return V_02842C_STENCIL_SUB_CLAMP;
903 case VK_STENCIL_OP_INVERT:
904 return V_02842C_STENCIL_INVERT;
905 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
906 return V_02842C_STENCIL_ADD_WRAP;
907 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
908 return V_02842C_STENCIL_SUB_WRAP;
909 default:
910 return 0;
911 }
912 }
913 static void
914 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
915 const VkGraphicsPipelineCreateInfo *pCreateInfo,
916 const struct radv_graphics_pipeline_create_info *extra)
917 {
918 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
919 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
920
921 memset(ds, 0, sizeof(*ds));
922 if (!vkds)
923 return;
924 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
925 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
926 S_028800_ZFUNC(vkds->depthCompareOp) |
927 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
928
929 if (vkds->stencilTestEnable) {
930 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
931 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
932 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
933 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
934 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
935
936 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
937 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
938 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
939 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
940 }
941
942 if (extra) {
943
944 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
945 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
946
947 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
948 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
949 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
950 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
951 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
952 }
953 }
954
955 static uint32_t si_translate_fill(VkPolygonMode func)
956 {
957 switch(func) {
958 case VK_POLYGON_MODE_FILL:
959 return V_028814_X_DRAW_TRIANGLES;
960 case VK_POLYGON_MODE_LINE:
961 return V_028814_X_DRAW_LINES;
962 case VK_POLYGON_MODE_POINT:
963 return V_028814_X_DRAW_POINTS;
964 default:
965 assert(0);
966 return V_028814_X_DRAW_POINTS;
967 }
968 }
969 static void
970 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
971 const VkGraphicsPipelineCreateInfo *pCreateInfo)
972 {
973 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
974 struct radv_raster_state *raster = &pipeline->graphics.raster;
975
976 memset(raster, 0, sizeof(*raster));
977
978 raster->spi_interp_control =
979 S_0286D4_FLAT_SHADE_ENA(1) |
980 S_0286D4_PNT_SPRITE_ENA(1) |
981 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
982 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
983 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
984 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
985 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
986
987 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
988 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
989 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
990 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
991 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
992 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
993 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
994
995 raster->pa_su_vtx_cntl =
996 S_028BE4_PIX_CENTER(1) | // TODO verify
997 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
998 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
999
1000 raster->pa_su_sc_mode_cntl =
1001 S_028814_FACE(vkraster->frontFace) |
1002 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1003 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1004 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1005 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1006 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1007 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1008 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1009 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1010
1011 }
1012
1013 static void
1014 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1015 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1016 {
1017 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1018 struct radv_blend_state *blend = &pipeline->graphics.blend;
1019 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1020 unsigned num_tile_pipes = pipeline->device->instance->physicalDevice.rad_info.num_tile_pipes;
1021 int ps_iter_samples = 1;
1022 uint32_t mask = 0xffff;
1023
1024 ms->num_samples = vkms->rasterizationSamples;
1025
1026 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1027 ps_iter_samples = vkms->rasterizationSamples;
1028 }
1029
1030 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1031 ms->pa_sc_aa_config = 0;
1032 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1033 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1034 ms->pa_sc_mode_cntl_1 =
1035 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1036 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1037 /* always 1: */
1038 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1039 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1040 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1041 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1042 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1043 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1044
1045 if (vkms->rasterizationSamples > 1) {
1046 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1047 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1048 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1049 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1050 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1051 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1052 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1053 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1054 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1055 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1056 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1057 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1058 }
1059
1060 if (vkms->alphaToCoverageEnable)
1061 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1062
1063 if (vkms->pSampleMask) {
1064 mask = vkms->pSampleMask[0] & 0xffff;
1065 }
1066
1067 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1068 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1069 }
1070
1071 static uint32_t
1072 si_translate_prim(enum VkPrimitiveTopology topology)
1073 {
1074 switch (topology) {
1075 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1076 return V_008958_DI_PT_POINTLIST;
1077 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1078 return V_008958_DI_PT_LINELIST;
1079 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1080 return V_008958_DI_PT_LINESTRIP;
1081 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1082 return V_008958_DI_PT_TRILIST;
1083 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1084 return V_008958_DI_PT_TRISTRIP;
1085 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1086 return V_008958_DI_PT_TRIFAN;
1087 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1088 return V_008958_DI_PT_LINELIST_ADJ;
1089 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1090 return V_008958_DI_PT_LINESTRIP_ADJ;
1091 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1092 return V_008958_DI_PT_TRILIST_ADJ;
1093 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1094 return V_008958_DI_PT_TRISTRIP_ADJ;
1095 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1096 return V_008958_DI_PT_PATCH;
1097 default:
1098 assert(0);
1099 return 0;
1100 }
1101 }
1102
1103 static uint32_t
1104 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1105 {
1106 switch (topology) {
1107 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1108 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1109 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1110 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1111 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1112 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1113 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1114 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1115 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1116 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1117 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1118 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1119 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1120 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1121 default:
1122 assert(0);
1123 return 0;
1124 }
1125 }
1126
1127 static unsigned si_map_swizzle(unsigned swizzle)
1128 {
1129 switch (swizzle) {
1130 case VK_SWIZZLE_Y:
1131 return V_008F0C_SQ_SEL_Y;
1132 case VK_SWIZZLE_Z:
1133 return V_008F0C_SQ_SEL_Z;
1134 case VK_SWIZZLE_W:
1135 return V_008F0C_SQ_SEL_W;
1136 case VK_SWIZZLE_0:
1137 return V_008F0C_SQ_SEL_0;
1138 case VK_SWIZZLE_1:
1139 return V_008F0C_SQ_SEL_1;
1140 default: /* VK_SWIZZLE_X */
1141 return V_008F0C_SQ_SEL_X;
1142 }
1143 }
1144
1145 static void
1146 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1147 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1148 {
1149 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1150 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1151 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1152
1153 pipeline->dynamic_state = default_dynamic_state;
1154
1155 if (pCreateInfo->pDynamicState) {
1156 /* Remove all of the states that are marked as dynamic */
1157 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1158 for (uint32_t s = 0; s < count; s++)
1159 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1160 }
1161
1162 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1163
1164 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1165 *
1166 * pViewportState is [...] NULL if the pipeline
1167 * has rasterization disabled.
1168 */
1169 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1170 assert(pCreateInfo->pViewportState);
1171
1172 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1173 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1174 typed_memcpy(dynamic->viewport.viewports,
1175 pCreateInfo->pViewportState->pViewports,
1176 pCreateInfo->pViewportState->viewportCount);
1177 }
1178
1179 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1180 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1181 typed_memcpy(dynamic->scissor.scissors,
1182 pCreateInfo->pViewportState->pScissors,
1183 pCreateInfo->pViewportState->scissorCount);
1184 }
1185 }
1186
1187 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1188 assert(pCreateInfo->pRasterizationState);
1189 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1190 }
1191
1192 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1193 assert(pCreateInfo->pRasterizationState);
1194 dynamic->depth_bias.bias =
1195 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1196 dynamic->depth_bias.clamp =
1197 pCreateInfo->pRasterizationState->depthBiasClamp;
1198 dynamic->depth_bias.slope =
1199 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1200 }
1201
1202 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1203 *
1204 * pColorBlendState is [...] NULL if the pipeline has rasterization
1205 * disabled or if the subpass of the render pass the pipeline is
1206 * created against does not use any color attachments.
1207 */
1208 bool uses_color_att = false;
1209 for (unsigned i = 0; i < subpass->color_count; ++i) {
1210 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1211 uses_color_att = true;
1212 break;
1213 }
1214 }
1215
1216 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1217 assert(pCreateInfo->pColorBlendState);
1218 typed_memcpy(dynamic->blend_constants,
1219 pCreateInfo->pColorBlendState->blendConstants, 4);
1220 }
1221
1222 /* If there is no depthstencil attachment, then don't read
1223 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1224 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1225 * no need to override the depthstencil defaults in
1226 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1227 *
1228 * Section 9.2 of the Vulkan 1.0.15 spec says:
1229 *
1230 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1231 * disabled or if the subpass of the render pass the pipeline is created
1232 * against does not use a depth/stencil attachment.
1233 */
1234 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1235 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1236 assert(pCreateInfo->pDepthStencilState);
1237
1238 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1239 dynamic->depth_bounds.min =
1240 pCreateInfo->pDepthStencilState->minDepthBounds;
1241 dynamic->depth_bounds.max =
1242 pCreateInfo->pDepthStencilState->maxDepthBounds;
1243 }
1244
1245 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1246 dynamic->stencil_compare_mask.front =
1247 pCreateInfo->pDepthStencilState->front.compareMask;
1248 dynamic->stencil_compare_mask.back =
1249 pCreateInfo->pDepthStencilState->back.compareMask;
1250 }
1251
1252 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1253 dynamic->stencil_write_mask.front =
1254 pCreateInfo->pDepthStencilState->front.writeMask;
1255 dynamic->stencil_write_mask.back =
1256 pCreateInfo->pDepthStencilState->back.writeMask;
1257 }
1258
1259 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1260 dynamic->stencil_reference.front =
1261 pCreateInfo->pDepthStencilState->front.reference;
1262 dynamic->stencil_reference.back =
1263 pCreateInfo->pDepthStencilState->back.reference;
1264 }
1265 }
1266
1267 pipeline->dynamic_state_mask = states;
1268 }
1269
1270 static union ac_shader_variant_key
1271 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1272 {
1273 union ac_shader_variant_key key;
1274 const VkPipelineVertexInputStateCreateInfo *input_state =
1275 pCreateInfo->pVertexInputState;
1276
1277 memset(&key, 0, sizeof(key));
1278 key.vs.instance_rate_inputs = 0;
1279
1280 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1281 unsigned binding;
1282 binding = input_state->pVertexAttributeDescriptions[i].binding;
1283 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1284 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1285 }
1286 return key;
1287 }
1288
1289 VkResult
1290 radv_pipeline_init(struct radv_pipeline *pipeline,
1291 struct radv_device *device,
1292 struct radv_pipeline_cache *cache,
1293 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1294 const struct radv_graphics_pipeline_create_info *extra,
1295 const VkAllocationCallbacks *alloc)
1296 {
1297 struct radv_shader_module fs_m = {0};
1298
1299 bool dump = getenv("RADV_DUMP_SHADERS");
1300 if (alloc == NULL)
1301 alloc = &device->alloc;
1302
1303 pipeline->device = device;
1304 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1305
1306 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1307 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1308 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1309 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1310 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1311 pStages[stage] = &pCreateInfo->pStages[i];
1312 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1313 }
1314
1315 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1316
1317 /* */
1318 if (modules[MESA_SHADER_VERTEX]) {
1319 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
1320
1321 pipeline->shaders[MESA_SHADER_VERTEX] =
1322 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1323 pStages[MESA_SHADER_VERTEX]->pName,
1324 MESA_SHADER_VERTEX,
1325 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1326 pipeline->layout, &key, dump);
1327
1328 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1329 }
1330
1331 if (!modules[MESA_SHADER_FRAGMENT]) {
1332 nir_builder fs_b;
1333 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1334 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1335 fs_m.nir = fs_b.shader;
1336 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1337 }
1338
1339 if (modules[MESA_SHADER_FRAGMENT]) {
1340 union ac_shader_variant_key key;
1341 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1342 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1343
1344 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1345
1346 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1347 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1348 stage ? stage->pName : "main",
1349 MESA_SHADER_FRAGMENT,
1350 stage ? stage->pSpecializationInfo : NULL,
1351 pipeline->layout, &key, dump);
1352 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1353 }
1354
1355 if (fs_m.nir)
1356 ralloc_free(fs_m.nir);
1357
1358 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1359 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1360 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1361 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1362 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1363 if (extra && extra->use_rectlist) {
1364 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1365 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1366 }
1367 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1368
1369 const VkPipelineVertexInputStateCreateInfo *vi_info =
1370 pCreateInfo->pVertexInputState;
1371 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1372 const VkVertexInputAttributeDescription *desc =
1373 &vi_info->pVertexAttributeDescriptions[i];
1374 unsigned loc = desc->location;
1375 const struct vk_format_description *format_desc;
1376 int first_non_void;
1377 uint32_t num_format, data_format;
1378 format_desc = vk_format_description(desc->format);
1379 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1380
1381 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1382 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1383
1384 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1385 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1386 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1387 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1388 S_008F0C_NUM_FORMAT(num_format) |
1389 S_008F0C_DATA_FORMAT(data_format);
1390 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1391 pipeline->va_offset[loc] = desc->offset;
1392 pipeline->va_binding[loc] = desc->binding;
1393 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1394 }
1395
1396 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1397 const VkVertexInputBindingDescription *desc =
1398 &vi_info->pVertexBindingDescriptions[i];
1399
1400 pipeline->binding_stride[desc->binding] = desc->stride;
1401 }
1402
1403 if (device->shader_stats_dump) {
1404 radv_dump_pipeline_stats(device, pipeline);
1405 }
1406
1407 return VK_SUCCESS;
1408 }
1409
1410 VkResult
1411 radv_graphics_pipeline_create(
1412 VkDevice _device,
1413 VkPipelineCache _cache,
1414 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1415 const struct radv_graphics_pipeline_create_info *extra,
1416 const VkAllocationCallbacks *pAllocator,
1417 VkPipeline *pPipeline)
1418 {
1419 RADV_FROM_HANDLE(radv_device, device, _device);
1420 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1421 struct radv_pipeline *pipeline;
1422 VkResult result;
1423
1424 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1425 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1426 if (pipeline == NULL)
1427 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1428
1429 memset(pipeline, 0, sizeof(*pipeline));
1430 result = radv_pipeline_init(pipeline, device, cache,
1431 pCreateInfo, extra, pAllocator);
1432 if (result != VK_SUCCESS) {
1433 vk_free2(&device->alloc, pAllocator, pipeline);
1434 return result;
1435 }
1436
1437 *pPipeline = radv_pipeline_to_handle(pipeline);
1438
1439 return VK_SUCCESS;
1440 }
1441
1442 VkResult radv_CreateGraphicsPipelines(
1443 VkDevice _device,
1444 VkPipelineCache pipelineCache,
1445 uint32_t count,
1446 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1447 const VkAllocationCallbacks* pAllocator,
1448 VkPipeline* pPipelines)
1449 {
1450 VkResult result = VK_SUCCESS;
1451 unsigned i = 0;
1452
1453 for (; i < count; i++) {
1454 result = radv_graphics_pipeline_create(_device,
1455 pipelineCache,
1456 &pCreateInfos[i],
1457 NULL, pAllocator, &pPipelines[i]);
1458 if (result != VK_SUCCESS) {
1459 for (unsigned j = 0; j < i; j++) {
1460 radv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1461 }
1462
1463 return result;
1464 }
1465 }
1466
1467 return VK_SUCCESS;
1468 }
1469
1470 static VkResult radv_compute_pipeline_create(
1471 VkDevice _device,
1472 VkPipelineCache _cache,
1473 const VkComputePipelineCreateInfo* pCreateInfo,
1474 const VkAllocationCallbacks* pAllocator,
1475 VkPipeline* pPipeline)
1476 {
1477 RADV_FROM_HANDLE(radv_device, device, _device);
1478 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1479 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1480 struct radv_pipeline *pipeline;
1481 bool dump = getenv("RADV_DUMP_SHADERS");
1482
1483 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1484 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1485 if (pipeline == NULL)
1486 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1487
1488 memset(pipeline, 0, sizeof(*pipeline));
1489 pipeline->device = device;
1490 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1491
1492 pipeline->shaders[MESA_SHADER_COMPUTE] =
1493 radv_pipeline_compile(pipeline, cache, module,
1494 pCreateInfo->stage.pName,
1495 MESA_SHADER_COMPUTE,
1496 pCreateInfo->stage.pSpecializationInfo,
1497 pipeline->layout, NULL, dump);
1498
1499 *pPipeline = radv_pipeline_to_handle(pipeline);
1500
1501 if (device->shader_stats_dump) {
1502 radv_dump_pipeline_stats(device, pipeline);
1503 }
1504 return VK_SUCCESS;
1505 }
1506 VkResult radv_CreateComputePipelines(
1507 VkDevice _device,
1508 VkPipelineCache pipelineCache,
1509 uint32_t count,
1510 const VkComputePipelineCreateInfo* pCreateInfos,
1511 const VkAllocationCallbacks* pAllocator,
1512 VkPipeline* pPipelines)
1513 {
1514 VkResult result = VK_SUCCESS;
1515
1516 unsigned i = 0;
1517 for (; i < count; i++) {
1518 result = radv_compute_pipeline_create(_device, pipelineCache,
1519 &pCreateInfos[i],
1520 pAllocator, &pPipelines[i]);
1521 if (result != VK_SUCCESS) {
1522 for (unsigned j = 0; j < i; j++) {
1523 radv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1524 }
1525
1526 return result;
1527 }
1528 }
1529
1530 return VK_SUCCESS;
1531 }