2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
36 unsigned char sha1
[20];
39 uint32_t binary_sizes
[MESA_SHADER_STAGES
];
40 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
45 radv_pipeline_cache_lock(struct radv_pipeline_cache
*cache
)
47 if (cache
->flags
& VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT
)
50 pthread_mutex_lock(&cache
->mutex
);
54 radv_pipeline_cache_unlock(struct radv_pipeline_cache
*cache
)
56 if (cache
->flags
& VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT
)
59 pthread_mutex_unlock(&cache
->mutex
);
63 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
64 struct radv_device
*device
)
66 cache
->device
= device
;
67 pthread_mutex_init(&cache
->mutex
, NULL
);
70 cache
->modified
= false;
71 cache
->kernel_count
= 0;
72 cache
->total_size
= 0;
73 cache
->table_size
= 1024;
74 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
75 cache
->hash_table
= malloc(byte_size
);
77 /* We don't consider allocation failure fatal, we just start with a 0-sized
78 * cache. Disable caching when we want to keep shader debug info, since
79 * we don't get the debug info on cached shaders. */
80 if (cache
->hash_table
== NULL
||
81 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
))
82 cache
->table_size
= 0;
84 memset(cache
->hash_table
, 0, byte_size
);
88 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
90 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
91 if (cache
->hash_table
[i
]) {
92 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
93 if (cache
->hash_table
[i
]->variants
[j
])
94 radv_shader_variant_destroy(cache
->device
,
95 cache
->hash_table
[i
]->variants
[j
]);
97 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
99 pthread_mutex_destroy(&cache
->mutex
);
100 free(cache
->hash_table
);
104 entry_size(struct cache_entry
*entry
)
106 size_t ret
= sizeof(*entry
);
107 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
108 if (entry
->binary_sizes
[i
])
109 ret
+= entry
->binary_sizes
[i
];
114 radv_hash_shaders(unsigned char *hash
,
115 const VkPipelineShaderStageCreateInfo
**stages
,
116 const struct radv_pipeline_layout
*layout
,
117 const struct radv_pipeline_key
*key
,
120 struct mesa_sha1 ctx
;
122 _mesa_sha1_init(&ctx
);
124 _mesa_sha1_update(&ctx
, key
, sizeof(*key
));
126 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
128 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
130 RADV_FROM_HANDLE(radv_shader_module
, module
, stages
[i
]->module
);
131 const VkSpecializationInfo
*spec_info
= stages
[i
]->pSpecializationInfo
;
133 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
134 _mesa_sha1_update(&ctx
, stages
[i
]->pName
, strlen(stages
[i
]->pName
));
136 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
137 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
138 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
142 _mesa_sha1_update(&ctx
, &flags
, 4);
143 _mesa_sha1_final(&ctx
, hash
);
147 static struct cache_entry
*
148 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
149 const unsigned char *sha1
)
151 const uint32_t mask
= cache
->table_size
- 1;
152 const uint32_t start
= (*(uint32_t *) sha1
);
154 if (cache
->table_size
== 0)
157 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
158 const uint32_t index
= (start
+ i
) & mask
;
159 struct cache_entry
*entry
= cache
->hash_table
[index
];
164 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
169 unreachable("hash table should never be full");
172 static struct cache_entry
*
173 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
174 const unsigned char *sha1
)
176 struct cache_entry
*entry
;
178 radv_pipeline_cache_lock(cache
);
180 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
182 radv_pipeline_cache_unlock(cache
);
188 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
189 struct cache_entry
*entry
)
191 const uint32_t mask
= cache
->table_size
- 1;
192 const uint32_t start
= entry
->sha1_dw
[0];
194 /* We'll always be able to insert when we get here. */
195 assert(cache
->kernel_count
< cache
->table_size
/ 2);
197 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
198 const uint32_t index
= (start
+ i
) & mask
;
199 if (!cache
->hash_table
[index
]) {
200 cache
->hash_table
[index
] = entry
;
205 cache
->total_size
+= entry_size(entry
);
206 cache
->kernel_count
++;
211 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
213 const uint32_t table_size
= cache
->table_size
* 2;
214 const uint32_t old_table_size
= cache
->table_size
;
215 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
216 struct cache_entry
**table
;
217 struct cache_entry
**old_table
= cache
->hash_table
;
219 table
= malloc(byte_size
);
221 return vk_error(cache
->device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
223 cache
->hash_table
= table
;
224 cache
->table_size
= table_size
;
225 cache
->kernel_count
= 0;
226 cache
->total_size
= 0;
228 memset(cache
->hash_table
, 0, byte_size
);
229 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
230 struct cache_entry
*entry
= old_table
[i
];
234 radv_pipeline_cache_set_entry(cache
, entry
);
243 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
244 struct cache_entry
*entry
)
246 if (cache
->kernel_count
== cache
->table_size
/ 2)
247 radv_pipeline_cache_grow(cache
);
249 /* Failing to grow that hash table isn't fatal, but may mean we don't
250 * have enough space to add this new kernel. Only add it if there's room.
252 if (cache
->kernel_count
< cache
->table_size
/ 2)
253 radv_pipeline_cache_set_entry(cache
, entry
);
257 radv_is_cache_disabled(struct radv_device
*device
)
259 /* Pipeline caches can be disabled with RADV_DEBUG=nocache, with
260 * MESA_GLSL_CACHE_DISABLE=1, and when VK_AMD_shader_info is requested.
262 return (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
);
266 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
267 struct radv_pipeline_cache
*cache
,
268 const unsigned char *sha1
,
269 struct radv_shader_variant
**variants
,
270 bool *found_in_application_cache
)
272 struct cache_entry
*entry
;
275 cache
= device
->mem_cache
;
276 *found_in_application_cache
= false;
279 radv_pipeline_cache_lock(cache
);
281 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
284 *found_in_application_cache
= false;
286 /* Don't cache when we want debug info, since this isn't
287 * present in the cache.
289 if (radv_is_cache_disabled(device
) || !device
->physical_device
->disk_cache
) {
290 radv_pipeline_cache_unlock(cache
);
294 uint8_t disk_sha1
[20];
295 disk_cache_compute_key(device
->physical_device
->disk_cache
,
296 sha1
, 20, disk_sha1
);
298 entry
= (struct cache_entry
*)
299 disk_cache_get(device
->physical_device
->disk_cache
,
302 radv_pipeline_cache_unlock(cache
);
305 size_t size
= entry_size(entry
);
306 struct cache_entry
*new_entry
= vk_alloc(&cache
->alloc
, size
, 8,
307 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
310 radv_pipeline_cache_unlock(cache
);
314 memcpy(new_entry
, entry
, entry_size(entry
));
318 if (!(device
->instance
->debug_flags
& RADV_DEBUG_NO_MEMORY_CACHE
) ||
319 cache
!= device
->mem_cache
)
320 radv_pipeline_cache_add_entry(cache
, new_entry
);
324 char *p
= entry
->code
;
325 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
326 if (!entry
->variants
[i
] && entry
->binary_sizes
[i
]) {
327 struct radv_shader_binary
*binary
= calloc(1, entry
->binary_sizes
[i
]);
328 memcpy(binary
, p
, entry
->binary_sizes
[i
]);
329 p
+= entry
->binary_sizes
[i
];
331 entry
->variants
[i
] = radv_shader_variant_create(device
, binary
, false);
333 } else if (entry
->binary_sizes
[i
]) {
334 p
+= entry
->binary_sizes
[i
];
339 memcpy(variants
, entry
->variants
, sizeof(entry
->variants
));
341 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_MEMORY_CACHE
&&
342 cache
== device
->mem_cache
)
343 vk_free(&cache
->alloc
, entry
);
345 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
346 if (entry
->variants
[i
])
347 p_atomic_inc(&entry
->variants
[i
]->ref_count
);
350 radv_pipeline_cache_unlock(cache
);
355 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
356 struct radv_pipeline_cache
*cache
,
357 const unsigned char *sha1
,
358 struct radv_shader_variant
**variants
,
359 struct radv_shader_binary
*const *binaries
)
362 cache
= device
->mem_cache
;
364 radv_pipeline_cache_lock(cache
);
365 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
367 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
368 if (entry
->variants
[i
]) {
369 radv_shader_variant_destroy(cache
->device
, variants
[i
]);
370 variants
[i
] = entry
->variants
[i
];
372 entry
->variants
[i
] = variants
[i
];
375 p_atomic_inc(&variants
[i
]->ref_count
);
377 radv_pipeline_cache_unlock(cache
);
381 /* Don't cache when we want debug info, since this isn't
382 * present in the cache.
384 if (radv_is_cache_disabled(device
)) {
385 radv_pipeline_cache_unlock(cache
);
389 size_t size
= sizeof(*entry
);
390 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
392 size
+= binaries
[i
]->total_size
;
395 entry
= vk_alloc(&cache
->alloc
, size
, 8,
396 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
398 radv_pipeline_cache_unlock(cache
);
402 memset(entry
, 0, sizeof(*entry
));
403 memcpy(entry
->sha1
, sha1
, 20);
405 char* p
= entry
->code
;
407 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
411 entry
->binary_sizes
[i
] = binaries
[i
]->total_size
;
413 memcpy(p
, binaries
[i
], binaries
[i
]->total_size
);
414 p
+= binaries
[i
]->total_size
;
417 /* Always add cache items to disk. This will allow collection of
418 * compiled shaders by third parties such as steam, even if the app
419 * implements its own pipeline cache.
421 if (device
->physical_device
->disk_cache
) {
422 uint8_t disk_sha1
[20];
423 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
426 disk_cache_put(device
->physical_device
->disk_cache
, disk_sha1
,
427 entry
, entry_size(entry
), NULL
);
430 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_MEMORY_CACHE
&&
431 cache
== device
->mem_cache
) {
432 vk_free2(&cache
->alloc
, NULL
, entry
);
433 radv_pipeline_cache_unlock(cache
);
437 /* We delay setting the variant so we have reproducible disk cache
440 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
444 entry
->variants
[i
] = variants
[i
];
445 p_atomic_inc(&variants
[i
]->ref_count
);
448 radv_pipeline_cache_add_entry(cache
, entry
);
450 cache
->modified
= true;
451 radv_pipeline_cache_unlock(cache
);
455 struct cache_header
{
456 uint32_t header_size
;
457 uint32_t header_version
;
460 uint8_t uuid
[VK_UUID_SIZE
];
464 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
465 const void *data
, size_t size
)
467 struct radv_device
*device
= cache
->device
;
468 struct cache_header header
;
470 if (size
< sizeof(header
))
472 memcpy(&header
, data
, sizeof(header
));
473 if (header
.header_size
< sizeof(header
))
475 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
477 if (header
.vendor_id
!= ATI_VENDOR_ID
)
479 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
481 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
484 char *end
= (void *) data
+ size
;
485 char *p
= (void *) data
+ header
.header_size
;
487 while (end
- p
>= sizeof(struct cache_entry
)) {
488 struct cache_entry
*entry
= (struct cache_entry
*)p
;
489 struct cache_entry
*dest_entry
;
490 size_t size
= entry_size(entry
);
494 dest_entry
= vk_alloc(&cache
->alloc
, size
,
495 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
497 memcpy(dest_entry
, entry
, size
);
498 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
499 dest_entry
->variants
[i
] = NULL
;
500 radv_pipeline_cache_add_entry(cache
, dest_entry
);
508 VkResult
radv_CreatePipelineCache(
510 const VkPipelineCacheCreateInfo
* pCreateInfo
,
511 const VkAllocationCallbacks
* pAllocator
,
512 VkPipelineCache
* pPipelineCache
)
514 RADV_FROM_HANDLE(radv_device
, device
, _device
);
515 struct radv_pipeline_cache
*cache
;
517 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
518 assert(pCreateInfo
->flags
== 0);
520 cache
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
522 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
524 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
526 vk_object_base_init(&device
->vk
, &cache
->base
,
527 VK_OBJECT_TYPE_PIPELINE_CACHE
);
530 cache
->alloc
= *pAllocator
;
532 cache
->alloc
= device
->vk
.alloc
;
534 radv_pipeline_cache_init(cache
, device
);
535 cache
->flags
= pCreateInfo
->flags
;
537 if (pCreateInfo
->initialDataSize
> 0) {
538 radv_pipeline_cache_load(cache
,
539 pCreateInfo
->pInitialData
,
540 pCreateInfo
->initialDataSize
);
543 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
548 void radv_DestroyPipelineCache(
550 VkPipelineCache _cache
,
551 const VkAllocationCallbacks
* pAllocator
)
553 RADV_FROM_HANDLE(radv_device
, device
, _device
);
554 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
558 radv_pipeline_cache_finish(cache
);
560 vk_object_base_finish(&cache
->base
);
561 vk_free2(&device
->vk
.alloc
, pAllocator
, cache
);
564 VkResult
radv_GetPipelineCacheData(
566 VkPipelineCache _cache
,
570 RADV_FROM_HANDLE(radv_device
, device
, _device
);
571 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
572 struct cache_header
*header
;
573 VkResult result
= VK_SUCCESS
;
575 radv_pipeline_cache_lock(cache
);
577 const size_t size
= sizeof(*header
) + cache
->total_size
;
579 radv_pipeline_cache_unlock(cache
);
583 if (*pDataSize
< sizeof(*header
)) {
584 radv_pipeline_cache_unlock(cache
);
586 return VK_INCOMPLETE
;
588 void *p
= pData
, *end
= pData
+ *pDataSize
;
590 header
->header_size
= sizeof(*header
);
591 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
592 header
->vendor_id
= ATI_VENDOR_ID
;
593 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
594 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
595 p
+= header
->header_size
;
597 struct cache_entry
*entry
;
598 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
599 if (!cache
->hash_table
[i
])
601 entry
= cache
->hash_table
[i
];
602 const uint32_t size
= entry_size(entry
);
603 if (end
< p
+ size
) {
604 result
= VK_INCOMPLETE
;
608 memcpy(p
, entry
, size
);
609 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
610 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
613 *pDataSize
= p
- pData
;
615 radv_pipeline_cache_unlock(cache
);
620 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
621 struct radv_pipeline_cache
*src
)
623 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
624 struct cache_entry
*entry
= src
->hash_table
[i
];
625 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
628 radv_pipeline_cache_add_entry(dst
, entry
);
630 src
->hash_table
[i
] = NULL
;
634 VkResult
radv_MergePipelineCaches(
636 VkPipelineCache destCache
,
637 uint32_t srcCacheCount
,
638 const VkPipelineCache
* pSrcCaches
)
640 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
642 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
643 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
645 radv_pipeline_cache_merge(dst
, src
);