2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
36 unsigned char sha1
[20];
39 uint32_t binary_sizes
[MESA_SHADER_STAGES
];
40 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
45 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
46 struct radv_device
*device
)
48 cache
->device
= device
;
49 pthread_mutex_init(&cache
->mutex
, NULL
);
51 cache
->modified
= false;
52 cache
->kernel_count
= 0;
53 cache
->total_size
= 0;
54 cache
->table_size
= 1024;
55 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
56 cache
->hash_table
= malloc(byte_size
);
58 /* We don't consider allocation failure fatal, we just start with a 0-sized
59 * cache. Disable caching when we want to keep shader debug info, since
60 * we don't get the debug info on cached shaders. */
61 if (cache
->hash_table
== NULL
||
62 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
) ||
63 device
->keep_shader_info
)
64 cache
->table_size
= 0;
66 memset(cache
->hash_table
, 0, byte_size
);
70 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
72 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
73 if (cache
->hash_table
[i
]) {
74 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
75 if (cache
->hash_table
[i
]->variants
[j
])
76 radv_shader_variant_destroy(cache
->device
,
77 cache
->hash_table
[i
]->variants
[j
]);
79 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
81 pthread_mutex_destroy(&cache
->mutex
);
82 free(cache
->hash_table
);
86 entry_size(struct cache_entry
*entry
)
88 size_t ret
= sizeof(*entry
);
89 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
90 if (entry
->binary_sizes
[i
])
91 ret
+= entry
->binary_sizes
[i
];
96 radv_hash_shaders(unsigned char *hash
,
97 const VkPipelineShaderStageCreateInfo
**stages
,
98 const struct radv_pipeline_layout
*layout
,
99 const struct radv_pipeline_key
*key
,
102 struct mesa_sha1 ctx
;
104 _mesa_sha1_init(&ctx
);
106 _mesa_sha1_update(&ctx
, key
, sizeof(*key
));
108 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
110 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
112 RADV_FROM_HANDLE(radv_shader_module
, module
, stages
[i
]->module
);
113 const VkSpecializationInfo
*spec_info
= stages
[i
]->pSpecializationInfo
;
115 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
116 _mesa_sha1_update(&ctx
, stages
[i
]->pName
, strlen(stages
[i
]->pName
));
118 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
119 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
120 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
124 _mesa_sha1_update(&ctx
, &flags
, 4);
125 _mesa_sha1_final(&ctx
, hash
);
129 static struct cache_entry
*
130 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
131 const unsigned char *sha1
)
133 const uint32_t mask
= cache
->table_size
- 1;
134 const uint32_t start
= (*(uint32_t *) sha1
);
136 if (cache
->table_size
== 0)
139 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
140 const uint32_t index
= (start
+ i
) & mask
;
141 struct cache_entry
*entry
= cache
->hash_table
[index
];
146 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
151 unreachable("hash table should never be full");
154 static struct cache_entry
*
155 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
156 const unsigned char *sha1
)
158 struct cache_entry
*entry
;
160 pthread_mutex_lock(&cache
->mutex
);
162 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
164 pthread_mutex_unlock(&cache
->mutex
);
170 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
171 struct cache_entry
*entry
)
173 const uint32_t mask
= cache
->table_size
- 1;
174 const uint32_t start
= entry
->sha1_dw
[0];
176 /* We'll always be able to insert when we get here. */
177 assert(cache
->kernel_count
< cache
->table_size
/ 2);
179 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
180 const uint32_t index
= (start
+ i
) & mask
;
181 if (!cache
->hash_table
[index
]) {
182 cache
->hash_table
[index
] = entry
;
187 cache
->total_size
+= entry_size(entry
);
188 cache
->kernel_count
++;
193 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
195 const uint32_t table_size
= cache
->table_size
* 2;
196 const uint32_t old_table_size
= cache
->table_size
;
197 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
198 struct cache_entry
**table
;
199 struct cache_entry
**old_table
= cache
->hash_table
;
201 table
= malloc(byte_size
);
203 return vk_error(cache
->device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
205 cache
->hash_table
= table
;
206 cache
->table_size
= table_size
;
207 cache
->kernel_count
= 0;
208 cache
->total_size
= 0;
210 memset(cache
->hash_table
, 0, byte_size
);
211 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
212 struct cache_entry
*entry
= old_table
[i
];
216 radv_pipeline_cache_set_entry(cache
, entry
);
225 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
226 struct cache_entry
*entry
)
228 if (cache
->kernel_count
== cache
->table_size
/ 2)
229 radv_pipeline_cache_grow(cache
);
231 /* Failing to grow that hash table isn't fatal, but may mean we don't
232 * have enough space to add this new kernel. Only add it if there's room.
234 if (cache
->kernel_count
< cache
->table_size
/ 2)
235 radv_pipeline_cache_set_entry(cache
, entry
);
239 radv_is_cache_disabled(struct radv_device
*device
)
241 /* Pipeline caches can be disabled with RADV_DEBUG=nocache, with
242 * MESA_GLSL_CACHE_DISABLE=1, and when VK_AMD_shader_info is requested.
244 return (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
) ||
245 device
->keep_shader_info
;
249 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
250 struct radv_pipeline_cache
*cache
,
251 const unsigned char *sha1
,
252 struct radv_shader_variant
**variants
,
253 bool *found_in_application_cache
)
255 struct cache_entry
*entry
;
258 cache
= device
->mem_cache
;
259 *found_in_application_cache
= false;
262 pthread_mutex_lock(&cache
->mutex
);
264 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
267 *found_in_application_cache
= false;
269 /* Don't cache when we want debug info, since this isn't
270 * present in the cache.
272 if (radv_is_cache_disabled(device
) || !device
->physical_device
->disk_cache
) {
273 pthread_mutex_unlock(&cache
->mutex
);
277 uint8_t disk_sha1
[20];
278 disk_cache_compute_key(device
->physical_device
->disk_cache
,
279 sha1
, 20, disk_sha1
);
280 entry
= (struct cache_entry
*)
281 disk_cache_get(device
->physical_device
->disk_cache
,
284 pthread_mutex_unlock(&cache
->mutex
);
287 size_t size
= entry_size(entry
);
288 struct cache_entry
*new_entry
= vk_alloc(&cache
->alloc
, size
, 8,
289 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
292 pthread_mutex_unlock(&cache
->mutex
);
296 memcpy(new_entry
, entry
, entry_size(entry
));
300 radv_pipeline_cache_add_entry(cache
, new_entry
);
304 char *p
= entry
->code
;
305 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
306 if (!entry
->variants
[i
] && entry
->binary_sizes
[i
]) {
307 struct radv_shader_binary
*binary
= calloc(1, entry
->binary_sizes
[i
]);
308 memcpy(binary
, p
, entry
->binary_sizes
[i
]);
309 p
+= entry
->binary_sizes
[i
];
311 entry
->variants
[i
] = radv_shader_variant_create(device
, binary
);
312 } else if (entry
->binary_sizes
[i
]) {
313 p
+= entry
->binary_sizes
[i
];
318 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
319 if (entry
->variants
[i
])
320 p_atomic_inc(&entry
->variants
[i
]->ref_count
);
322 memcpy(variants
, entry
->variants
, sizeof(entry
->variants
));
323 pthread_mutex_unlock(&cache
->mutex
);
328 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
329 struct radv_pipeline_cache
*cache
,
330 const unsigned char *sha1
,
331 struct radv_shader_variant
**variants
,
332 struct radv_shader_binary
*const *binaries
)
335 cache
= device
->mem_cache
;
337 pthread_mutex_lock(&cache
->mutex
);
338 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
340 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
341 if (entry
->variants
[i
]) {
342 radv_shader_variant_destroy(cache
->device
, variants
[i
]);
343 variants
[i
] = entry
->variants
[i
];
345 entry
->variants
[i
] = variants
[i
];
348 p_atomic_inc(&variants
[i
]->ref_count
);
350 pthread_mutex_unlock(&cache
->mutex
);
354 /* Don't cache when we want debug info, since this isn't
355 * present in the cache.
357 if (radv_is_cache_disabled(device
)) {
358 pthread_mutex_unlock(&cache
->mutex
);
362 size_t size
= sizeof(*entry
);
363 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
365 size
+= binaries
[i
]->total_size
;
368 entry
= vk_alloc(&cache
->alloc
, size
, 8,
369 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
371 pthread_mutex_unlock(&cache
->mutex
);
375 memset(entry
, 0, sizeof(*entry
));
376 memcpy(entry
->sha1
, sha1
, 20);
378 char* p
= entry
->code
;
380 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
384 entry
->binary_sizes
[i
] = binaries
[i
]->total_size
;
386 memcpy(p
, binaries
[i
], binaries
[i
]->total_size
);
387 p
+= binaries
[i
]->total_size
;
390 /* Always add cache items to disk. This will allow collection of
391 * compiled shaders by third parties such as steam, even if the app
392 * implements its own pipeline cache.
394 if (device
->physical_device
->disk_cache
) {
395 uint8_t disk_sha1
[20];
396 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
398 disk_cache_put(device
->physical_device
->disk_cache
,
399 disk_sha1
, entry
, entry_size(entry
), NULL
);
402 /* We delay setting the variant so we have reproducible disk cache
405 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
409 entry
->variants
[i
] = variants
[i
];
410 p_atomic_inc(&variants
[i
]->ref_count
);
413 radv_pipeline_cache_add_entry(cache
, entry
);
415 cache
->modified
= true;
416 pthread_mutex_unlock(&cache
->mutex
);
420 struct cache_header
{
421 uint32_t header_size
;
422 uint32_t header_version
;
425 uint8_t uuid
[VK_UUID_SIZE
];
429 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
430 const void *data
, size_t size
)
432 struct radv_device
*device
= cache
->device
;
433 struct cache_header header
;
435 if (size
< sizeof(header
))
437 memcpy(&header
, data
, sizeof(header
));
438 if (header
.header_size
< sizeof(header
))
440 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
442 if (header
.vendor_id
!= ATI_VENDOR_ID
)
444 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
446 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
449 char *end
= (void *) data
+ size
;
450 char *p
= (void *) data
+ header
.header_size
;
452 while (end
- p
>= sizeof(struct cache_entry
)) {
453 struct cache_entry
*entry
= (struct cache_entry
*)p
;
454 struct cache_entry
*dest_entry
;
455 size_t size
= entry_size(entry
);
459 dest_entry
= vk_alloc(&cache
->alloc
, size
,
460 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
462 memcpy(dest_entry
, entry
, size
);
463 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
464 dest_entry
->variants
[i
] = NULL
;
465 radv_pipeline_cache_add_entry(cache
, dest_entry
);
473 VkResult
radv_CreatePipelineCache(
475 const VkPipelineCacheCreateInfo
* pCreateInfo
,
476 const VkAllocationCallbacks
* pAllocator
,
477 VkPipelineCache
* pPipelineCache
)
479 RADV_FROM_HANDLE(radv_device
, device
, _device
);
480 struct radv_pipeline_cache
*cache
;
482 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
483 assert(pCreateInfo
->flags
== 0);
485 cache
= vk_alloc2(&device
->alloc
, pAllocator
,
487 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
489 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
492 cache
->alloc
= *pAllocator
;
494 cache
->alloc
= device
->alloc
;
496 radv_pipeline_cache_init(cache
, device
);
498 if (pCreateInfo
->initialDataSize
> 0) {
499 radv_pipeline_cache_load(cache
,
500 pCreateInfo
->pInitialData
,
501 pCreateInfo
->initialDataSize
);
504 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
509 void radv_DestroyPipelineCache(
511 VkPipelineCache _cache
,
512 const VkAllocationCallbacks
* pAllocator
)
514 RADV_FROM_HANDLE(radv_device
, device
, _device
);
515 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
519 radv_pipeline_cache_finish(cache
);
521 vk_free2(&device
->alloc
, pAllocator
, cache
);
524 VkResult
radv_GetPipelineCacheData(
526 VkPipelineCache _cache
,
530 RADV_FROM_HANDLE(radv_device
, device
, _device
);
531 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
532 struct cache_header
*header
;
533 VkResult result
= VK_SUCCESS
;
535 pthread_mutex_lock(&cache
->mutex
);
537 const size_t size
= sizeof(*header
) + cache
->total_size
;
539 pthread_mutex_unlock(&cache
->mutex
);
543 if (*pDataSize
< sizeof(*header
)) {
544 pthread_mutex_unlock(&cache
->mutex
);
546 return VK_INCOMPLETE
;
548 void *p
= pData
, *end
= pData
+ *pDataSize
;
550 header
->header_size
= sizeof(*header
);
551 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
552 header
->vendor_id
= ATI_VENDOR_ID
;
553 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
554 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
555 p
+= header
->header_size
;
557 struct cache_entry
*entry
;
558 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
559 if (!cache
->hash_table
[i
])
561 entry
= cache
->hash_table
[i
];
562 const uint32_t size
= entry_size(entry
);
563 if (end
< p
+ size
) {
564 result
= VK_INCOMPLETE
;
568 memcpy(p
, entry
, size
);
569 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
570 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
573 *pDataSize
= p
- pData
;
575 pthread_mutex_unlock(&cache
->mutex
);
580 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
581 struct radv_pipeline_cache
*src
)
583 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
584 struct cache_entry
*entry
= src
->hash_table
[i
];
585 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
588 radv_pipeline_cache_add_entry(dst
, entry
);
590 src
->hash_table
[i
] = NULL
;
594 VkResult
radv_MergePipelineCaches(
596 VkPipelineCache destCache
,
597 uint32_t srcCacheCount
,
598 const VkPipelineCache
* pSrcCaches
)
600 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
602 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
603 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
605 radv_pipeline_cache_merge(dst
, src
);