2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
34 struct cache_entry_variant_info
{
35 struct ac_shader_variant_info variant_info
;
36 struct ac_shader_config config
;
37 uint32_t rsrc1
, rsrc2
;
42 unsigned char sha1
[20];
45 uint32_t code_sizes
[MESA_SHADER_STAGES
];
46 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
51 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
52 struct radv_device
*device
)
54 cache
->device
= device
;
55 pthread_mutex_init(&cache
->mutex
, NULL
);
57 cache
->modified
= false;
58 cache
->kernel_count
= 0;
59 cache
->total_size
= 0;
60 cache
->table_size
= 1024;
61 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
62 cache
->hash_table
= malloc(byte_size
);
64 /* We don't consider allocation failure fatal, we just start with a 0-sized
65 * cache. Disable caching when we want to keep shader debug info, since
66 * we don't get the debug info on cached shaders. */
67 if (cache
->hash_table
== NULL
||
68 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
) ||
69 device
->keep_shader_info
)
70 cache
->table_size
= 0;
72 memset(cache
->hash_table
, 0, byte_size
);
76 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
78 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
79 if (cache
->hash_table
[i
]) {
80 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
81 if (cache
->hash_table
[i
]->variants
[j
])
82 radv_shader_variant_destroy(cache
->device
,
83 cache
->hash_table
[i
]->variants
[j
]);
85 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
87 pthread_mutex_destroy(&cache
->mutex
);
88 free(cache
->hash_table
);
92 entry_size(struct cache_entry
*entry
)
94 size_t ret
= sizeof(*entry
);
95 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
96 if (entry
->code_sizes
[i
])
97 ret
+= sizeof(struct cache_entry_variant_info
) + entry
->code_sizes
[i
];
102 radv_hash_shaders(unsigned char *hash
,
103 const VkPipelineShaderStageCreateInfo
**stages
,
104 const struct radv_pipeline_layout
*layout
,
105 const struct radv_pipeline_key
*key
,
108 struct mesa_sha1 ctx
;
110 _mesa_sha1_init(&ctx
);
112 _mesa_sha1_update(&ctx
, key
, sizeof(*key
));
114 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
116 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
118 RADV_FROM_HANDLE(radv_shader_module
, module
, stages
[i
]->module
);
119 const VkSpecializationInfo
*spec_info
= stages
[i
]->pSpecializationInfo
;
121 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
122 _mesa_sha1_update(&ctx
, stages
[i
]->pName
, strlen(stages
[i
]->pName
));
124 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
125 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
126 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
130 _mesa_sha1_update(&ctx
, &flags
, 4);
131 _mesa_sha1_final(&ctx
, hash
);
135 static struct cache_entry
*
136 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
137 const unsigned char *sha1
)
139 const uint32_t mask
= cache
->table_size
- 1;
140 const uint32_t start
= (*(uint32_t *) sha1
);
142 if (cache
->table_size
== 0)
145 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
146 const uint32_t index
= (start
+ i
) & mask
;
147 struct cache_entry
*entry
= cache
->hash_table
[index
];
152 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
157 unreachable("hash table should never be full");
160 static struct cache_entry
*
161 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
162 const unsigned char *sha1
)
164 struct cache_entry
*entry
;
166 pthread_mutex_lock(&cache
->mutex
);
168 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
170 pthread_mutex_unlock(&cache
->mutex
);
176 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
177 struct radv_pipeline_cache
*cache
,
178 const unsigned char *sha1
,
179 struct radv_shader_variant
**variants
)
181 struct cache_entry
*entry
;
184 cache
= device
->mem_cache
;
186 pthread_mutex_lock(&cache
->mutex
);
188 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
191 /* Again, don't cache when we want debug info, since this isn't
192 * present in the cache. */
193 if (!device
->physical_device
->disk_cache
||
194 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
) ||
195 device
->keep_shader_info
) {
196 pthread_mutex_unlock(&cache
->mutex
);
200 uint8_t disk_sha1
[20];
201 disk_cache_compute_key(device
->physical_device
->disk_cache
,
202 sha1
, 20, disk_sha1
);
203 entry
= (struct cache_entry
*)
204 disk_cache_get(device
->physical_device
->disk_cache
,
207 pthread_mutex_unlock(&cache
->mutex
);
212 char *p
= entry
->code
;
213 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
214 if (!entry
->variants
[i
] && entry
->code_sizes
[i
]) {
215 struct radv_shader_variant
*variant
;
216 struct cache_entry_variant_info info
;
218 variant
= calloc(1, sizeof(struct radv_shader_variant
));
220 pthread_mutex_unlock(&cache
->mutex
);
224 memcpy(&info
, p
, sizeof(struct cache_entry_variant_info
));
225 p
+= sizeof(struct cache_entry_variant_info
);
227 variant
->config
= info
.config
;
228 variant
->info
= info
.variant_info
;
229 variant
->rsrc1
= info
.rsrc1
;
230 variant
->rsrc2
= info
.rsrc2
;
231 variant
->code_size
= entry
->code_sizes
[i
];
232 variant
->ref_count
= 1;
234 void *ptr
= radv_alloc_shader_memory(device
, variant
);
235 memcpy(ptr
, p
, entry
->code_sizes
[i
]);
236 p
+= entry
->code_sizes
[i
];
238 entry
->variants
[i
] = variant
;
239 } else if (entry
->code_sizes
[i
]) {
240 p
+= sizeof(struct cache_entry_variant_info
) + entry
->code_sizes
[i
];
245 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
246 if (entry
->variants
[i
])
247 p_atomic_inc(&entry
->variants
[i
]->ref_count
);
249 memcpy(variants
, entry
->variants
, sizeof(entry
->variants
));
250 pthread_mutex_unlock(&cache
->mutex
);
256 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
257 struct cache_entry
*entry
)
259 const uint32_t mask
= cache
->table_size
- 1;
260 const uint32_t start
= entry
->sha1_dw
[0];
262 /* We'll always be able to insert when we get here. */
263 assert(cache
->kernel_count
< cache
->table_size
/ 2);
265 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
266 const uint32_t index
= (start
+ i
) & mask
;
267 if (!cache
->hash_table
[index
]) {
268 cache
->hash_table
[index
] = entry
;
273 cache
->total_size
+= entry_size(entry
);
274 cache
->kernel_count
++;
279 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
281 const uint32_t table_size
= cache
->table_size
* 2;
282 const uint32_t old_table_size
= cache
->table_size
;
283 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
284 struct cache_entry
**table
;
285 struct cache_entry
**old_table
= cache
->hash_table
;
287 table
= malloc(byte_size
);
289 return VK_ERROR_OUT_OF_HOST_MEMORY
;
291 cache
->hash_table
= table
;
292 cache
->table_size
= table_size
;
293 cache
->kernel_count
= 0;
294 cache
->total_size
= 0;
296 memset(cache
->hash_table
, 0, byte_size
);
297 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
298 struct cache_entry
*entry
= old_table
[i
];
302 radv_pipeline_cache_set_entry(cache
, entry
);
311 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
312 struct cache_entry
*entry
)
314 if (cache
->kernel_count
== cache
->table_size
/ 2)
315 radv_pipeline_cache_grow(cache
);
317 /* Failing to grow that hash table isn't fatal, but may mean we don't
318 * have enough space to add this new kernel. Only add it if there's room.
320 if (cache
->kernel_count
< cache
->table_size
/ 2)
321 radv_pipeline_cache_set_entry(cache
, entry
);
325 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
326 struct radv_pipeline_cache
*cache
,
327 const unsigned char *sha1
,
328 struct radv_shader_variant
**variants
,
329 const void *const *codes
,
330 const unsigned *code_sizes
)
333 cache
= device
->mem_cache
;
335 pthread_mutex_lock(&cache
->mutex
);
336 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
338 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
339 if (entry
->variants
[i
]) {
340 radv_shader_variant_destroy(cache
->device
, variants
[i
]);
341 variants
[i
] = entry
->variants
[i
];
343 entry
->variants
[i
] = variants
[i
];
346 p_atomic_inc(&variants
[i
]->ref_count
);
348 pthread_mutex_unlock(&cache
->mutex
);
351 size_t size
= sizeof(*entry
);
352 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
354 size
+= sizeof(struct cache_entry_variant_info
) + code_sizes
[i
];
357 entry
= vk_alloc(&cache
->alloc
, size
, 8,
358 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
360 pthread_mutex_unlock(&cache
->mutex
);
364 memset(entry
, 0, sizeof(*entry
));
365 memcpy(entry
->sha1
, sha1
, 20);
367 char* p
= entry
->code
;
368 struct cache_entry_variant_info info
;
370 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
374 entry
->code_sizes
[i
] = code_sizes
[i
];
376 info
.config
= variants
[i
]->config
;
377 info
.variant_info
= variants
[i
]->info
;
378 info
.rsrc1
= variants
[i
]->rsrc1
;
379 info
.rsrc2
= variants
[i
]->rsrc2
;
380 memcpy(p
, &info
, sizeof(struct cache_entry_variant_info
));
381 p
+= sizeof(struct cache_entry_variant_info
);
383 memcpy(p
, codes
[i
], code_sizes
[i
]);
387 /* Always add cache items to disk. This will allow collection of
388 * compiled shaders by third parties such as steam, even if the app
389 * implements its own pipeline cache.
391 if (device
->physical_device
->disk_cache
) {
392 uint8_t disk_sha1
[20];
393 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
395 disk_cache_put(device
->physical_device
->disk_cache
,
396 disk_sha1
, entry
, entry_size(entry
), NULL
);
399 /* We delay setting the variant so we have reproducible disk cache
402 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
406 entry
->variants
[i
] = variants
[i
];
407 p_atomic_inc(&variants
[i
]->ref_count
);
410 radv_pipeline_cache_add_entry(cache
, entry
);
412 cache
->modified
= true;
413 pthread_mutex_unlock(&cache
->mutex
);
417 struct cache_header
{
418 uint32_t header_size
;
419 uint32_t header_version
;
422 uint8_t uuid
[VK_UUID_SIZE
];
426 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
427 const void *data
, size_t size
)
429 struct radv_device
*device
= cache
->device
;
430 struct cache_header header
;
432 if (size
< sizeof(header
))
434 memcpy(&header
, data
, sizeof(header
));
435 if (header
.header_size
< sizeof(header
))
437 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
439 if (header
.vendor_id
!= ATI_VENDOR_ID
)
441 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
443 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
446 char *end
= (void *) data
+ size
;
447 char *p
= (void *) data
+ header
.header_size
;
449 while (end
- p
>= sizeof(struct cache_entry
)) {
450 struct cache_entry
*entry
= (struct cache_entry
*)p
;
451 struct cache_entry
*dest_entry
;
452 size_t size
= entry_size(entry
);
456 dest_entry
= vk_alloc(&cache
->alloc
, size
,
457 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
459 memcpy(dest_entry
, entry
, size
);
460 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
461 dest_entry
->variants
[i
] = NULL
;
462 radv_pipeline_cache_add_entry(cache
, dest_entry
);
468 VkResult
radv_CreatePipelineCache(
470 const VkPipelineCacheCreateInfo
* pCreateInfo
,
471 const VkAllocationCallbacks
* pAllocator
,
472 VkPipelineCache
* pPipelineCache
)
474 RADV_FROM_HANDLE(radv_device
, device
, _device
);
475 struct radv_pipeline_cache
*cache
;
477 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
478 assert(pCreateInfo
->flags
== 0);
480 cache
= vk_alloc2(&device
->alloc
, pAllocator
,
482 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
484 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
487 cache
->alloc
= *pAllocator
;
489 cache
->alloc
= device
->alloc
;
491 radv_pipeline_cache_init(cache
, device
);
493 if (pCreateInfo
->initialDataSize
> 0) {
494 radv_pipeline_cache_load(cache
,
495 pCreateInfo
->pInitialData
,
496 pCreateInfo
->initialDataSize
);
499 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
504 void radv_DestroyPipelineCache(
506 VkPipelineCache _cache
,
507 const VkAllocationCallbacks
* pAllocator
)
509 RADV_FROM_HANDLE(radv_device
, device
, _device
);
510 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
514 radv_pipeline_cache_finish(cache
);
516 vk_free2(&device
->alloc
, pAllocator
, cache
);
519 VkResult
radv_GetPipelineCacheData(
521 VkPipelineCache _cache
,
525 RADV_FROM_HANDLE(radv_device
, device
, _device
);
526 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
527 struct cache_header
*header
;
528 VkResult result
= VK_SUCCESS
;
530 pthread_mutex_lock(&cache
->mutex
);
532 const size_t size
= sizeof(*header
) + cache
->total_size
;
534 pthread_mutex_unlock(&cache
->mutex
);
538 if (*pDataSize
< sizeof(*header
)) {
539 pthread_mutex_unlock(&cache
->mutex
);
541 return VK_INCOMPLETE
;
543 void *p
= pData
, *end
= pData
+ *pDataSize
;
545 header
->header_size
= sizeof(*header
);
546 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
547 header
->vendor_id
= ATI_VENDOR_ID
;
548 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
549 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
550 p
+= header
->header_size
;
552 struct cache_entry
*entry
;
553 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
554 if (!cache
->hash_table
[i
])
556 entry
= cache
->hash_table
[i
];
557 const uint32_t size
= entry_size(entry
);
558 if (end
< p
+ size
) {
559 result
= VK_INCOMPLETE
;
563 memcpy(p
, entry
, size
);
564 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
565 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
568 *pDataSize
= p
- pData
;
570 pthread_mutex_unlock(&cache
->mutex
);
575 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
576 struct radv_pipeline_cache
*src
)
578 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
579 struct cache_entry
*entry
= src
->hash_table
[i
];
580 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
583 radv_pipeline_cache_add_entry(dst
, entry
);
585 src
->hash_table
[i
] = NULL
;
589 VkResult
radv_MergePipelineCaches(
591 VkPipelineCache destCache
,
592 uint32_t srcCacheCount
,
593 const VkPipelineCache
* pSrcCaches
)
595 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
597 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
598 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
600 radv_pipeline_cache_merge(dst
, src
);