2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
36 unsigned char sha1
[20];
39 uint32_t binary_sizes
[MESA_SHADER_STAGES
];
40 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
45 radv_pipeline_cache_lock(struct radv_pipeline_cache
*cache
)
47 if (cache
->flags
& VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT
)
50 pthread_mutex_lock(&cache
->mutex
);
54 radv_pipeline_cache_unlock(struct radv_pipeline_cache
*cache
)
56 if (cache
->flags
& VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT
)
59 pthread_mutex_unlock(&cache
->mutex
);
63 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
64 struct radv_device
*device
)
66 cache
->device
= device
;
67 pthread_mutex_init(&cache
->mutex
, NULL
);
70 cache
->modified
= false;
71 cache
->kernel_count
= 0;
72 cache
->total_size
= 0;
73 cache
->table_size
= 1024;
74 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
75 cache
->hash_table
= malloc(byte_size
);
77 /* We don't consider allocation failure fatal, we just start with a 0-sized
78 * cache. Disable caching when we want to keep shader debug info, since
79 * we don't get the debug info on cached shaders. */
80 if (cache
->hash_table
== NULL
||
81 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
))
82 cache
->table_size
= 0;
84 memset(cache
->hash_table
, 0, byte_size
);
88 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
90 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
91 if (cache
->hash_table
[i
]) {
92 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
93 if (cache
->hash_table
[i
]->variants
[j
])
94 radv_shader_variant_destroy(cache
->device
,
95 cache
->hash_table
[i
]->variants
[j
]);
97 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
99 pthread_mutex_destroy(&cache
->mutex
);
100 free(cache
->hash_table
);
104 entry_size(struct cache_entry
*entry
)
106 size_t ret
= sizeof(*entry
);
107 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
108 if (entry
->binary_sizes
[i
])
109 ret
+= entry
->binary_sizes
[i
];
114 radv_hash_shaders(unsigned char *hash
,
115 const VkPipelineShaderStageCreateInfo
**stages
,
116 const struct radv_pipeline_layout
*layout
,
117 const struct radv_pipeline_key
*key
,
120 struct mesa_sha1 ctx
;
122 _mesa_sha1_init(&ctx
);
124 _mesa_sha1_update(&ctx
, key
, sizeof(*key
));
126 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
128 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
130 RADV_FROM_HANDLE(radv_shader_module
, module
, stages
[i
]->module
);
131 const VkSpecializationInfo
*spec_info
= stages
[i
]->pSpecializationInfo
;
133 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
134 _mesa_sha1_update(&ctx
, stages
[i
]->pName
, strlen(stages
[i
]->pName
));
136 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
137 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
138 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
142 _mesa_sha1_update(&ctx
, &flags
, 4);
143 _mesa_sha1_final(&ctx
, hash
);
147 static struct cache_entry
*
148 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
149 const unsigned char *sha1
)
151 const uint32_t mask
= cache
->table_size
- 1;
152 const uint32_t start
= (*(uint32_t *) sha1
);
154 if (cache
->table_size
== 0)
157 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
158 const uint32_t index
= (start
+ i
) & mask
;
159 struct cache_entry
*entry
= cache
->hash_table
[index
];
164 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
169 unreachable("hash table should never be full");
172 static struct cache_entry
*
173 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
174 const unsigned char *sha1
)
176 struct cache_entry
*entry
;
178 radv_pipeline_cache_lock(cache
);
180 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
182 radv_pipeline_cache_unlock(cache
);
188 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
189 struct cache_entry
*entry
)
191 const uint32_t mask
= cache
->table_size
- 1;
192 const uint32_t start
= entry
->sha1_dw
[0];
194 /* We'll always be able to insert when we get here. */
195 assert(cache
->kernel_count
< cache
->table_size
/ 2);
197 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
198 const uint32_t index
= (start
+ i
) & mask
;
199 if (!cache
->hash_table
[index
]) {
200 cache
->hash_table
[index
] = entry
;
205 cache
->total_size
+= entry_size(entry
);
206 cache
->kernel_count
++;
211 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
213 const uint32_t table_size
= cache
->table_size
* 2;
214 const uint32_t old_table_size
= cache
->table_size
;
215 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
216 struct cache_entry
**table
;
217 struct cache_entry
**old_table
= cache
->hash_table
;
219 table
= malloc(byte_size
);
221 return vk_error(cache
->device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
223 cache
->hash_table
= table
;
224 cache
->table_size
= table_size
;
225 cache
->kernel_count
= 0;
226 cache
->total_size
= 0;
228 memset(cache
->hash_table
, 0, byte_size
);
229 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
230 struct cache_entry
*entry
= old_table
[i
];
234 radv_pipeline_cache_set_entry(cache
, entry
);
243 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
244 struct cache_entry
*entry
)
246 if (cache
->kernel_count
== cache
->table_size
/ 2)
247 radv_pipeline_cache_grow(cache
);
249 /* Failing to grow that hash table isn't fatal, but may mean we don't
250 * have enough space to add this new kernel. Only add it if there's room.
252 if (cache
->kernel_count
< cache
->table_size
/ 2)
253 radv_pipeline_cache_set_entry(cache
, entry
);
257 radv_is_cache_disabled(struct radv_device
*device
)
259 /* Pipeline caches can be disabled with RADV_DEBUG=nocache, with
260 * MESA_GLSL_CACHE_DISABLE=1, and when VK_AMD_shader_info is requested.
262 return (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
);
266 * Secure compiles cannot open files so we get the parent process to load the
267 * cache entry for us.
269 static struct cache_entry
*
270 radv_sc_read_from_disk_cache(struct radv_device
*device
, uint8_t *disk_sha1
)
272 struct cache_entry
*entry
;
273 unsigned process
= device
->sc_state
->secure_compile_thread_counter
;
274 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_READ_DISK_CACHE
;
276 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
,
277 &sc_type
, sizeof(enum radv_secure_compile_type
));
278 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
,
279 disk_sha1
, sizeof(uint8_t) * 20);
281 uint8_t found_cache_entry
;
282 if (!radv_sc_read(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
,
283 &found_cache_entry
, sizeof(uint8_t), true))
286 if (found_cache_entry
) {
288 if (!radv_sc_read(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
,
289 &entry_size
, sizeof(size_t), true))
292 entry
= malloc(entry_size
);
293 if (!radv_sc_read(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
,
294 entry
, entry_size
, true))
304 * Secure compiles cannot open files so we get the parent process to write to
305 * the disk cache for us.
308 radv_sc_write_to_disk_cache(struct radv_device
*device
, uint8_t *disk_sha1
,
309 struct cache_entry
*entry
)
311 unsigned process
= device
->sc_state
->secure_compile_thread_counter
;
312 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_WRITE_DISK_CACHE
;
314 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
,
315 &sc_type
, sizeof(enum radv_secure_compile_type
));
316 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
,
317 disk_sha1
, sizeof(uint8_t) * 20);
319 uint32_t size
= entry_size(entry
);
320 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
,
321 &size
, sizeof(uint32_t));
322 write(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
,
327 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
328 struct radv_pipeline_cache
*cache
,
329 const unsigned char *sha1
,
330 struct radv_shader_variant
**variants
,
331 bool *found_in_application_cache
)
333 struct cache_entry
*entry
;
336 cache
= device
->mem_cache
;
337 *found_in_application_cache
= false;
340 radv_pipeline_cache_lock(cache
);
342 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
345 *found_in_application_cache
= false;
347 /* Don't cache when we want debug info, since this isn't
348 * present in the cache.
350 if (radv_is_cache_disabled(device
) || !device
->physical_device
->disk_cache
) {
351 radv_pipeline_cache_unlock(cache
);
355 uint8_t disk_sha1
[20];
356 disk_cache_compute_key(device
->physical_device
->disk_cache
,
357 sha1
, 20, disk_sha1
);
359 if (radv_device_use_secure_compile(device
->instance
)) {
360 entry
= radv_sc_read_from_disk_cache(device
, disk_sha1
);
362 entry
= (struct cache_entry
*)
363 disk_cache_get(device
->physical_device
->disk_cache
,
368 radv_pipeline_cache_unlock(cache
);
371 size_t size
= entry_size(entry
);
372 struct cache_entry
*new_entry
= vk_alloc(&cache
->alloc
, size
, 8,
373 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
376 radv_pipeline_cache_unlock(cache
);
380 memcpy(new_entry
, entry
, entry_size(entry
));
384 if (!(device
->instance
->debug_flags
& RADV_DEBUG_NO_MEMORY_CACHE
) ||
385 cache
!= device
->mem_cache
)
386 radv_pipeline_cache_add_entry(cache
, new_entry
);
390 char *p
= entry
->code
;
391 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
392 if (!entry
->variants
[i
] && entry
->binary_sizes
[i
]) {
393 struct radv_shader_binary
*binary
= calloc(1, entry
->binary_sizes
[i
]);
394 memcpy(binary
, p
, entry
->binary_sizes
[i
]);
395 p
+= entry
->binary_sizes
[i
];
397 entry
->variants
[i
] = radv_shader_variant_create(device
, binary
, false);
399 } else if (entry
->binary_sizes
[i
]) {
400 p
+= entry
->binary_sizes
[i
];
405 memcpy(variants
, entry
->variants
, sizeof(entry
->variants
));
407 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_MEMORY_CACHE
&&
408 cache
== device
->mem_cache
)
409 vk_free(&cache
->alloc
, entry
);
411 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
412 if (entry
->variants
[i
])
413 p_atomic_inc(&entry
->variants
[i
]->ref_count
);
416 radv_pipeline_cache_unlock(cache
);
421 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
422 struct radv_pipeline_cache
*cache
,
423 const unsigned char *sha1
,
424 struct radv_shader_variant
**variants
,
425 struct radv_shader_binary
*const *binaries
)
428 cache
= device
->mem_cache
;
430 radv_pipeline_cache_lock(cache
);
431 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
433 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
434 if (entry
->variants
[i
]) {
435 radv_shader_variant_destroy(cache
->device
, variants
[i
]);
436 variants
[i
] = entry
->variants
[i
];
438 entry
->variants
[i
] = variants
[i
];
441 p_atomic_inc(&variants
[i
]->ref_count
);
443 radv_pipeline_cache_unlock(cache
);
447 /* Don't cache when we want debug info, since this isn't
448 * present in the cache.
450 if (radv_is_cache_disabled(device
)) {
451 radv_pipeline_cache_unlock(cache
);
455 size_t size
= sizeof(*entry
);
456 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
458 size
+= binaries
[i
]->total_size
;
461 entry
= vk_alloc(&cache
->alloc
, size
, 8,
462 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
464 radv_pipeline_cache_unlock(cache
);
468 memset(entry
, 0, sizeof(*entry
));
469 memcpy(entry
->sha1
, sha1
, 20);
471 char* p
= entry
->code
;
473 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
477 entry
->binary_sizes
[i
] = binaries
[i
]->total_size
;
479 memcpy(p
, binaries
[i
], binaries
[i
]->total_size
);
480 p
+= binaries
[i
]->total_size
;
483 /* Always add cache items to disk. This will allow collection of
484 * compiled shaders by third parties such as steam, even if the app
485 * implements its own pipeline cache.
487 if (device
->physical_device
->disk_cache
) {
488 uint8_t disk_sha1
[20];
489 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
492 /* Write the cache item out to the parent of this forked
495 if (radv_device_use_secure_compile(device
->instance
)) {
496 radv_sc_write_to_disk_cache(device
, disk_sha1
, entry
);
498 disk_cache_put(device
->physical_device
->disk_cache
,
499 disk_sha1
, entry
, entry_size(entry
),
504 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_MEMORY_CACHE
&&
505 cache
== device
->mem_cache
) {
506 vk_free2(&cache
->alloc
, NULL
, entry
);
507 radv_pipeline_cache_unlock(cache
);
511 /* We delay setting the variant so we have reproducible disk cache
514 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
518 entry
->variants
[i
] = variants
[i
];
519 p_atomic_inc(&variants
[i
]->ref_count
);
522 radv_pipeline_cache_add_entry(cache
, entry
);
524 cache
->modified
= true;
525 radv_pipeline_cache_unlock(cache
);
529 struct cache_header
{
530 uint32_t header_size
;
531 uint32_t header_version
;
534 uint8_t uuid
[VK_UUID_SIZE
];
538 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
539 const void *data
, size_t size
)
541 struct radv_device
*device
= cache
->device
;
542 struct cache_header header
;
544 if (size
< sizeof(header
))
546 memcpy(&header
, data
, sizeof(header
));
547 if (header
.header_size
< sizeof(header
))
549 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
551 if (header
.vendor_id
!= ATI_VENDOR_ID
)
553 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
555 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
558 char *end
= (void *) data
+ size
;
559 char *p
= (void *) data
+ header
.header_size
;
561 while (end
- p
>= sizeof(struct cache_entry
)) {
562 struct cache_entry
*entry
= (struct cache_entry
*)p
;
563 struct cache_entry
*dest_entry
;
564 size_t size
= entry_size(entry
);
568 dest_entry
= vk_alloc(&cache
->alloc
, size
,
569 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
571 memcpy(dest_entry
, entry
, size
);
572 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
573 dest_entry
->variants
[i
] = NULL
;
574 radv_pipeline_cache_add_entry(cache
, dest_entry
);
582 VkResult
radv_CreatePipelineCache(
584 const VkPipelineCacheCreateInfo
* pCreateInfo
,
585 const VkAllocationCallbacks
* pAllocator
,
586 VkPipelineCache
* pPipelineCache
)
588 RADV_FROM_HANDLE(radv_device
, device
, _device
);
589 struct radv_pipeline_cache
*cache
;
591 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
592 assert(pCreateInfo
->flags
== 0);
594 cache
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
596 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
598 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
600 vk_object_base_init(&device
->vk
, &cache
->base
,
601 VK_OBJECT_TYPE_PIPELINE_CACHE
);
604 cache
->alloc
= *pAllocator
;
606 cache
->alloc
= device
->vk
.alloc
;
608 radv_pipeline_cache_init(cache
, device
);
609 cache
->flags
= pCreateInfo
->flags
;
611 if (pCreateInfo
->initialDataSize
> 0) {
612 radv_pipeline_cache_load(cache
,
613 pCreateInfo
->pInitialData
,
614 pCreateInfo
->initialDataSize
);
617 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
622 void radv_DestroyPipelineCache(
624 VkPipelineCache _cache
,
625 const VkAllocationCallbacks
* pAllocator
)
627 RADV_FROM_HANDLE(radv_device
, device
, _device
);
628 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
632 radv_pipeline_cache_finish(cache
);
634 vk_object_base_finish(&cache
->base
);
635 vk_free2(&device
->vk
.alloc
, pAllocator
, cache
);
638 VkResult
radv_GetPipelineCacheData(
640 VkPipelineCache _cache
,
644 RADV_FROM_HANDLE(radv_device
, device
, _device
);
645 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
646 struct cache_header
*header
;
647 VkResult result
= VK_SUCCESS
;
649 radv_pipeline_cache_lock(cache
);
651 const size_t size
= sizeof(*header
) + cache
->total_size
;
653 radv_pipeline_cache_unlock(cache
);
657 if (*pDataSize
< sizeof(*header
)) {
658 radv_pipeline_cache_unlock(cache
);
660 return VK_INCOMPLETE
;
662 void *p
= pData
, *end
= pData
+ *pDataSize
;
664 header
->header_size
= sizeof(*header
);
665 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
666 header
->vendor_id
= ATI_VENDOR_ID
;
667 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
668 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
669 p
+= header
->header_size
;
671 struct cache_entry
*entry
;
672 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
673 if (!cache
->hash_table
[i
])
675 entry
= cache
->hash_table
[i
];
676 const uint32_t size
= entry_size(entry
);
677 if (end
< p
+ size
) {
678 result
= VK_INCOMPLETE
;
682 memcpy(p
, entry
, size
);
683 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
684 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
687 *pDataSize
= p
- pData
;
689 radv_pipeline_cache_unlock(cache
);
694 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
695 struct radv_pipeline_cache
*src
)
697 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
698 struct cache_entry
*entry
= src
->hash_table
[i
];
699 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
702 radv_pipeline_cache_add_entry(dst
, entry
);
704 src
->hash_table
[i
] = NULL
;
708 VkResult
radv_MergePipelineCaches(
710 VkPipelineCache destCache
,
711 uint32_t srcCacheCount
,
712 const VkPipelineCache
* pSrcCaches
)
714 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
716 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
717 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
719 radv_pipeline_cache_merge(dst
, src
);