2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
36 unsigned char sha1
[20];
39 uint32_t binary_sizes
[MESA_SHADER_STAGES
];
40 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
45 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
46 struct radv_device
*device
)
48 cache
->device
= device
;
49 pthread_mutex_init(&cache
->mutex
, NULL
);
51 cache
->modified
= false;
52 cache
->kernel_count
= 0;
53 cache
->total_size
= 0;
54 cache
->table_size
= 1024;
55 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
56 cache
->hash_table
= malloc(byte_size
);
58 /* We don't consider allocation failure fatal, we just start with a 0-sized
59 * cache. Disable caching when we want to keep shader debug info, since
60 * we don't get the debug info on cached shaders. */
61 if (cache
->hash_table
== NULL
||
62 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
))
63 cache
->table_size
= 0;
65 memset(cache
->hash_table
, 0, byte_size
);
69 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
71 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
72 if (cache
->hash_table
[i
]) {
73 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
74 if (cache
->hash_table
[i
]->variants
[j
])
75 radv_shader_variant_destroy(cache
->device
,
76 cache
->hash_table
[i
]->variants
[j
]);
78 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
80 pthread_mutex_destroy(&cache
->mutex
);
81 free(cache
->hash_table
);
85 entry_size(struct cache_entry
*entry
)
87 size_t ret
= sizeof(*entry
);
88 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
89 if (entry
->binary_sizes
[i
])
90 ret
+= entry
->binary_sizes
[i
];
95 radv_hash_shaders(unsigned char *hash
,
96 const VkPipelineShaderStageCreateInfo
**stages
,
97 const struct radv_pipeline_layout
*layout
,
98 const struct radv_pipeline_key
*key
,
101 struct mesa_sha1 ctx
;
103 _mesa_sha1_init(&ctx
);
105 _mesa_sha1_update(&ctx
, key
, sizeof(*key
));
107 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
109 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
111 RADV_FROM_HANDLE(radv_shader_module
, module
, stages
[i
]->module
);
112 const VkSpecializationInfo
*spec_info
= stages
[i
]->pSpecializationInfo
;
114 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
115 _mesa_sha1_update(&ctx
, stages
[i
]->pName
, strlen(stages
[i
]->pName
));
117 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
118 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
119 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
123 _mesa_sha1_update(&ctx
, &flags
, 4);
124 _mesa_sha1_final(&ctx
, hash
);
128 static struct cache_entry
*
129 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
130 const unsigned char *sha1
)
132 const uint32_t mask
= cache
->table_size
- 1;
133 const uint32_t start
= (*(uint32_t *) sha1
);
135 if (cache
->table_size
== 0)
138 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
139 const uint32_t index
= (start
+ i
) & mask
;
140 struct cache_entry
*entry
= cache
->hash_table
[index
];
145 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
150 unreachable("hash table should never be full");
153 static struct cache_entry
*
154 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
155 const unsigned char *sha1
)
157 struct cache_entry
*entry
;
159 pthread_mutex_lock(&cache
->mutex
);
161 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
163 pthread_mutex_unlock(&cache
->mutex
);
169 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
170 struct cache_entry
*entry
)
172 const uint32_t mask
= cache
->table_size
- 1;
173 const uint32_t start
= entry
->sha1_dw
[0];
175 /* We'll always be able to insert when we get here. */
176 assert(cache
->kernel_count
< cache
->table_size
/ 2);
178 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
179 const uint32_t index
= (start
+ i
) & mask
;
180 if (!cache
->hash_table
[index
]) {
181 cache
->hash_table
[index
] = entry
;
186 cache
->total_size
+= entry_size(entry
);
187 cache
->kernel_count
++;
192 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
194 const uint32_t table_size
= cache
->table_size
* 2;
195 const uint32_t old_table_size
= cache
->table_size
;
196 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
197 struct cache_entry
**table
;
198 struct cache_entry
**old_table
= cache
->hash_table
;
200 table
= malloc(byte_size
);
202 return vk_error(cache
->device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
204 cache
->hash_table
= table
;
205 cache
->table_size
= table_size
;
206 cache
->kernel_count
= 0;
207 cache
->total_size
= 0;
209 memset(cache
->hash_table
, 0, byte_size
);
210 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
211 struct cache_entry
*entry
= old_table
[i
];
215 radv_pipeline_cache_set_entry(cache
, entry
);
224 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
225 struct cache_entry
*entry
)
227 if (cache
->kernel_count
== cache
->table_size
/ 2)
228 radv_pipeline_cache_grow(cache
);
230 /* Failing to grow that hash table isn't fatal, but may mean we don't
231 * have enough space to add this new kernel. Only add it if there's room.
233 if (cache
->kernel_count
< cache
->table_size
/ 2)
234 radv_pipeline_cache_set_entry(cache
, entry
);
238 radv_is_cache_disabled(struct radv_device
*device
)
240 /* Pipeline caches can be disabled with RADV_DEBUG=nocache, with
241 * MESA_GLSL_CACHE_DISABLE=1, and when VK_AMD_shader_info is requested.
243 return (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
);
247 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
248 struct radv_pipeline_cache
*cache
,
249 const unsigned char *sha1
,
250 struct radv_shader_variant
**variants
,
251 bool *found_in_application_cache
)
253 struct cache_entry
*entry
;
256 cache
= device
->mem_cache
;
257 *found_in_application_cache
= false;
260 pthread_mutex_lock(&cache
->mutex
);
262 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
265 *found_in_application_cache
= false;
267 /* Don't cache when we want debug info, since this isn't
268 * present in the cache.
270 if (radv_is_cache_disabled(device
) || !device
->physical_device
->disk_cache
) {
271 pthread_mutex_unlock(&cache
->mutex
);
275 uint8_t disk_sha1
[20];
276 disk_cache_compute_key(device
->physical_device
->disk_cache
,
277 sha1
, 20, disk_sha1
);
278 entry
= (struct cache_entry
*)
279 disk_cache_get(device
->physical_device
->disk_cache
,
282 pthread_mutex_unlock(&cache
->mutex
);
285 size_t size
= entry_size(entry
);
286 struct cache_entry
*new_entry
= vk_alloc(&cache
->alloc
, size
, 8,
287 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
290 pthread_mutex_unlock(&cache
->mutex
);
294 memcpy(new_entry
, entry
, entry_size(entry
));
298 radv_pipeline_cache_add_entry(cache
, new_entry
);
302 char *p
= entry
->code
;
303 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
304 if (!entry
->variants
[i
] && entry
->binary_sizes
[i
]) {
305 struct radv_shader_binary
*binary
= calloc(1, entry
->binary_sizes
[i
]);
306 memcpy(binary
, p
, entry
->binary_sizes
[i
]);
307 p
+= entry
->binary_sizes
[i
];
309 entry
->variants
[i
] = radv_shader_variant_create(device
, binary
, false);
311 } else if (entry
->binary_sizes
[i
]) {
312 p
+= entry
->binary_sizes
[i
];
317 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
318 if (entry
->variants
[i
])
319 p_atomic_inc(&entry
->variants
[i
]->ref_count
);
321 memcpy(variants
, entry
->variants
, sizeof(entry
->variants
));
322 pthread_mutex_unlock(&cache
->mutex
);
327 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
328 struct radv_pipeline_cache
*cache
,
329 const unsigned char *sha1
,
330 struct radv_shader_variant
**variants
,
331 struct radv_shader_binary
*const *binaries
)
334 cache
= device
->mem_cache
;
336 pthread_mutex_lock(&cache
->mutex
);
337 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
339 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
340 if (entry
->variants
[i
]) {
341 radv_shader_variant_destroy(cache
->device
, variants
[i
]);
342 variants
[i
] = entry
->variants
[i
];
344 entry
->variants
[i
] = variants
[i
];
347 p_atomic_inc(&variants
[i
]->ref_count
);
349 pthread_mutex_unlock(&cache
->mutex
);
353 /* Don't cache when we want debug info, since this isn't
354 * present in the cache.
356 if (radv_is_cache_disabled(device
)) {
357 pthread_mutex_unlock(&cache
->mutex
);
361 size_t size
= sizeof(*entry
);
362 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
364 size
+= binaries
[i
]->total_size
;
367 entry
= vk_alloc(&cache
->alloc
, size
, 8,
368 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
370 pthread_mutex_unlock(&cache
->mutex
);
374 memset(entry
, 0, sizeof(*entry
));
375 memcpy(entry
->sha1
, sha1
, 20);
377 char* p
= entry
->code
;
379 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
383 entry
->binary_sizes
[i
] = binaries
[i
]->total_size
;
385 memcpy(p
, binaries
[i
], binaries
[i
]->total_size
);
386 p
+= binaries
[i
]->total_size
;
389 /* Always add cache items to disk. This will allow collection of
390 * compiled shaders by third parties such as steam, even if the app
391 * implements its own pipeline cache.
393 if (device
->physical_device
->disk_cache
) {
394 uint8_t disk_sha1
[20];
395 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
397 disk_cache_put(device
->physical_device
->disk_cache
,
398 disk_sha1
, entry
, entry_size(entry
), NULL
);
401 /* We delay setting the variant so we have reproducible disk cache
404 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
408 entry
->variants
[i
] = variants
[i
];
409 p_atomic_inc(&variants
[i
]->ref_count
);
412 radv_pipeline_cache_add_entry(cache
, entry
);
414 cache
->modified
= true;
415 pthread_mutex_unlock(&cache
->mutex
);
419 struct cache_header
{
420 uint32_t header_size
;
421 uint32_t header_version
;
424 uint8_t uuid
[VK_UUID_SIZE
];
428 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
429 const void *data
, size_t size
)
431 struct radv_device
*device
= cache
->device
;
432 struct cache_header header
;
434 if (size
< sizeof(header
))
436 memcpy(&header
, data
, sizeof(header
));
437 if (header
.header_size
< sizeof(header
))
439 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
441 if (header
.vendor_id
!= ATI_VENDOR_ID
)
443 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
445 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
448 char *end
= (void *) data
+ size
;
449 char *p
= (void *) data
+ header
.header_size
;
451 while (end
- p
>= sizeof(struct cache_entry
)) {
452 struct cache_entry
*entry
= (struct cache_entry
*)p
;
453 struct cache_entry
*dest_entry
;
454 size_t size
= entry_size(entry
);
458 dest_entry
= vk_alloc(&cache
->alloc
, size
,
459 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
461 memcpy(dest_entry
, entry
, size
);
462 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
463 dest_entry
->variants
[i
] = NULL
;
464 radv_pipeline_cache_add_entry(cache
, dest_entry
);
472 VkResult
radv_CreatePipelineCache(
474 const VkPipelineCacheCreateInfo
* pCreateInfo
,
475 const VkAllocationCallbacks
* pAllocator
,
476 VkPipelineCache
* pPipelineCache
)
478 RADV_FROM_HANDLE(radv_device
, device
, _device
);
479 struct radv_pipeline_cache
*cache
;
481 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
482 assert(pCreateInfo
->flags
== 0);
484 cache
= vk_alloc2(&device
->alloc
, pAllocator
,
486 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
488 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
491 cache
->alloc
= *pAllocator
;
493 cache
->alloc
= device
->alloc
;
495 radv_pipeline_cache_init(cache
, device
);
497 if (pCreateInfo
->initialDataSize
> 0) {
498 radv_pipeline_cache_load(cache
,
499 pCreateInfo
->pInitialData
,
500 pCreateInfo
->initialDataSize
);
503 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
508 void radv_DestroyPipelineCache(
510 VkPipelineCache _cache
,
511 const VkAllocationCallbacks
* pAllocator
)
513 RADV_FROM_HANDLE(radv_device
, device
, _device
);
514 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
518 radv_pipeline_cache_finish(cache
);
520 vk_free2(&device
->alloc
, pAllocator
, cache
);
523 VkResult
radv_GetPipelineCacheData(
525 VkPipelineCache _cache
,
529 RADV_FROM_HANDLE(radv_device
, device
, _device
);
530 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
531 struct cache_header
*header
;
532 VkResult result
= VK_SUCCESS
;
534 pthread_mutex_lock(&cache
->mutex
);
536 const size_t size
= sizeof(*header
) + cache
->total_size
;
538 pthread_mutex_unlock(&cache
->mutex
);
542 if (*pDataSize
< sizeof(*header
)) {
543 pthread_mutex_unlock(&cache
->mutex
);
545 return VK_INCOMPLETE
;
547 void *p
= pData
, *end
= pData
+ *pDataSize
;
549 header
->header_size
= sizeof(*header
);
550 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
551 header
->vendor_id
= ATI_VENDOR_ID
;
552 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
553 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
554 p
+= header
->header_size
;
556 struct cache_entry
*entry
;
557 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
558 if (!cache
->hash_table
[i
])
560 entry
= cache
->hash_table
[i
];
561 const uint32_t size
= entry_size(entry
);
562 if (end
< p
+ size
) {
563 result
= VK_INCOMPLETE
;
567 memcpy(p
, entry
, size
);
568 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
569 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
572 *pDataSize
= p
- pData
;
574 pthread_mutex_unlock(&cache
->mutex
);
579 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
580 struct radv_pipeline_cache
*src
)
582 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
583 struct cache_entry
*entry
= src
->hash_table
[i
];
584 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
587 radv_pipeline_cache_add_entry(dst
, entry
);
589 src
->hash_table
[i
] = NULL
;
593 VkResult
radv_MergePipelineCaches(
595 VkPipelineCache destCache
,
596 uint32_t srcCacheCount
,
597 const VkPipelineCache
* pSrcCaches
)
599 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
601 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
602 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
604 radv_pipeline_cache_merge(dst
, src
);