2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
58 #include <llvm-c/TargetMachine.h>
60 /* Pre-declarations needed for WSI entrypoints */
63 typedef struct xcb_connection_t xcb_connection_t
;
64 typedef uint32_t xcb_visualid_t
;
65 typedef uint32_t xcb_window_t
;
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
71 #include "radv_entrypoints.h"
73 #include "wsi_common.h"
76 #define MAX_VERTEX_ATTRIBS 32
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
84 #define NUM_META_FS_KEYS 11
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
99 RADV_MEM_TYPE_GTT_CACHED
,
103 #define radv_noreturn __attribute__((__noreturn__))
104 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
106 static inline uint32_t
107 align_u32(uint32_t v
, uint32_t a
)
109 assert(a
!= 0 && a
== (a
& -a
));
110 return (v
+ a
- 1) & ~(a
- 1);
113 static inline uint32_t
114 align_u32_npot(uint32_t v
, uint32_t a
)
116 return (v
+ a
- 1) / a
* a
;
119 static inline uint64_t
120 align_u64(uint64_t v
, uint64_t a
)
122 assert(a
!= 0 && a
== (a
& -a
));
123 return (v
+ a
- 1) & ~(a
- 1);
126 static inline int32_t
127 align_i32(int32_t v
, int32_t a
)
129 assert(a
!= 0 && a
== (a
& -a
));
130 return (v
+ a
- 1) & ~(a
- 1);
133 /** Alignment must be a power of 2. */
135 radv_is_aligned(uintmax_t n
, uintmax_t a
)
137 assert(a
== (a
& -a
));
138 return (n
& (a
- 1)) == 0;
141 static inline uint32_t
142 round_up_u32(uint32_t v
, uint32_t a
)
144 return (v
+ a
- 1) / a
;
147 static inline uint64_t
148 round_up_u64(uint64_t v
, uint64_t a
)
150 return (v
+ a
- 1) / a
;
153 static inline uint32_t
154 radv_minify(uint32_t n
, uint32_t levels
)
156 if (unlikely(n
== 0))
159 return MAX2(n
>> levels
, 1);
162 radv_clamp_f(float f
, float min
, float max
)
175 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
177 if (*inout_mask
& clear_mask
) {
178 *inout_mask
&= ~clear_mask
;
185 #define for_each_bit(b, dword) \
186 for (uint32_t __dword = (dword); \
187 (b) = __builtin_ffs(__dword) - 1, __dword; \
188 __dword &= ~(1 << (b)))
190 #define typed_memcpy(dest, src, count) ({ \
191 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
192 memcpy((dest), (src), (count) * sizeof(*(src))); \
195 #define zero(x) (memset(&(x), 0, sizeof(x)))
197 /* Whenever we generate an error, pass it through this function. Useful for
198 * debugging, where we can break on it. Only call at error site, not when
199 * propagating errors. Might be useful to plug in a stack trace here.
202 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
205 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
206 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
212 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
213 radv_printflike(3, 4);
214 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
215 void radv_loge_v(const char *format
, va_list va
);
218 * Print a FINISHME message, including its source location.
220 #define radv_finishme(format, ...) \
222 static bool reported = false; \
224 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
229 /* A non-fatal assert. Useful for debugging. */
231 #define radv_assert(x) ({ \
232 if (unlikely(!(x))) \
233 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
236 #define radv_assert(x)
239 void radv_abortf(const char *format
, ...) radv_noreturn
radv_printflike(1, 2);
240 void radv_abortfv(const char *format
, va_list va
) radv_noreturn
;
242 #define stub_return(v) \
244 radv_finishme("stub %s", __func__); \
250 radv_finishme("stub %s", __func__); \
254 void *radv_resolve_entrypoint(uint32_t index
);
255 void *radv_lookup_entrypoint(const char *name
);
257 extern struct radv_dispatch_table dtable
;
259 struct radv_physical_device
{
260 VK_LOADER_DATA _loader_data
;
262 struct radv_instance
* instance
;
264 struct radeon_winsys
*ws
;
265 struct radeon_info rad_info
;
269 uint64_t aperture_size
;
270 int cmd_parser_version
;
271 uint32_t pci_vendor_id
;
272 uint32_t pci_device_id
;
274 uint8_t uuid
[VK_UUID_SIZE
];
276 struct wsi_device wsi_device
;
279 struct radv_instance
{
280 VK_LOADER_DATA _loader_data
;
282 VkAllocationCallbacks alloc
;
285 int physicalDeviceCount
;
286 struct radv_physical_device physicalDevice
;
289 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
290 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
294 struct radv_pipeline_cache
{
295 struct radv_device
* device
;
296 pthread_mutex_t mutex
;
300 uint32_t kernel_count
;
301 struct cache_entry
** hash_table
;
304 VkAllocationCallbacks alloc
;
308 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
309 struct radv_device
*device
);
311 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
313 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
314 const void *data
, size_t size
);
316 struct radv_shader_variant
*
317 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
318 struct radv_pipeline_cache
*cache
,
319 const unsigned char *sha1
);
321 struct radv_shader_variant
*
322 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache
*cache
,
323 const unsigned char *sha1
,
324 struct radv_shader_variant
*variant
,
325 const void *code
, unsigned code_size
);
327 void radv_shader_variant_destroy(struct radv_device
*device
,
328 struct radv_shader_variant
*variant
);
330 struct radv_meta_state
{
331 VkAllocationCallbacks alloc
;
333 struct radv_pipeline_cache cache
;
336 * Use array element `i` for images with `2^i` samples.
339 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
340 struct radv_pipeline
*color_pipelines
[NUM_META_FS_KEYS
];
342 VkRenderPass depth_only_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
343 struct radv_pipeline
*depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
344 VkRenderPass stencil_only_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
345 struct radv_pipeline
*stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
346 VkRenderPass depthstencil_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
347 struct radv_pipeline
*depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
348 } clear
[1 + MAX_SAMPLES_LOG2
];
351 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
353 /** Pipeline that blits from a 1D image. */
354 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
356 /** Pipeline that blits from a 2D image. */
357 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
359 /** Pipeline that blits from a 3D image. */
360 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
362 VkRenderPass depth_only_rp
;
363 VkPipeline depth_only_1d_pipeline
;
364 VkPipeline depth_only_2d_pipeline
;
365 VkPipeline depth_only_3d_pipeline
;
367 VkRenderPass stencil_only_rp
;
368 VkPipeline stencil_only_1d_pipeline
;
369 VkPipeline stencil_only_2d_pipeline
;
370 VkPipeline stencil_only_3d_pipeline
;
371 VkPipelineLayout pipeline_layout
;
372 VkDescriptorSetLayout ds_layout
;
376 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
378 VkPipelineLayout p_layouts
[2];
379 VkDescriptorSetLayout ds_layouts
[2];
380 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
382 VkRenderPass depth_only_rp
;
383 VkPipeline depth_only_pipeline
[2];
385 VkRenderPass stencil_only_rp
;
386 VkPipeline stencil_only_pipeline
[2];
390 VkPipelineLayout img_p_layout
;
391 VkDescriptorSetLayout img_ds_layout
;
395 VkRenderPass render_pass
;
396 VkPipelineLayout img_p_layout
;
397 VkDescriptorSetLayout img_ds_layout
;
401 VkPipelineLayout img_p_layout
;
402 VkDescriptorSetLayout img_ds_layout
;
406 VkPipelineLayout img_p_layout
;
407 VkDescriptorSetLayout img_ds_layout
;
417 VkDescriptorSetLayout ds_layout
;
418 VkPipelineLayout p_layout
;
421 VkPipeline i_pipeline
;
422 } rc
[MAX_SAMPLES_LOG2
];
426 VkPipeline decompress_pipeline
;
427 VkPipeline resummarize_pipeline
;
432 VkPipeline cmask_eliminate_pipeline
;
433 VkPipeline fmask_decompress_pipeline
;
438 VkPipelineLayout fill_p_layout
;
439 VkPipelineLayout copy_p_layout
;
440 VkDescriptorSetLayout fill_ds_layout
;
441 VkDescriptorSetLayout copy_ds_layout
;
442 VkPipeline fill_pipeline
;
443 VkPipeline copy_pipeline
;
448 #define RADV_QUEUE_GENERAL 0
449 #define RADV_QUEUE_COMPUTE 1
450 #define RADV_QUEUE_TRANSFER 2
452 #define RADV_MAX_QUEUE_FAMILIES 3
454 enum ring_type
radv_queue_family_to_ring(int f
);
457 VK_LOADER_DATA _loader_data
;
458 struct radv_device
* device
;
459 int queue_family_index
;
464 VK_LOADER_DATA _loader_data
;
466 VkAllocationCallbacks alloc
;
468 struct radv_instance
* instance
;
469 struct radeon_winsys
*ws
;
470 struct radeon_winsys_ctx
*hw_ctx
;
472 struct radv_meta_state meta_state
;
474 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
475 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
476 struct radeon_winsys_cs
*empty_cs
;
478 bool allow_fast_clears
;
480 bool shader_stats_dump
;
482 /* MSAA sample locations.
483 * The first index is the sample index.
484 * The second index is the coordinate: X, Y. */
485 float sample_locations_1x
[1][2];
486 float sample_locations_2x
[2][2];
487 float sample_locations_4x
[4][2];
488 float sample_locations_8x
[8][2];
489 float sample_locations_16x
[16][2];
492 struct radv_device_memory
{
493 struct radeon_winsys_bo
*bo
;
495 VkDeviceSize map_size
;
500 struct radv_descriptor_range
{
505 struct radv_descriptor_set
{
506 const struct radv_descriptor_set_layout
*layout
;
507 struct list_head descriptor_pool
;
510 struct radv_buffer_view
*buffer_views
;
511 struct radeon_winsys_bo
*bo
;
513 uint32_t *mapped_ptr
;
514 struct radv_descriptor_range
*dynamic_descriptors
;
515 struct radeon_winsys_bo
*descriptors
[0];
518 struct radv_descriptor_pool_free_node
{
524 struct radv_descriptor_pool
{
525 struct list_head descriptor_sets
;
527 struct radeon_winsys_bo
*bo
;
529 uint64_t current_offset
;
535 struct radv_descriptor_pool_free_node free_nodes
[];
539 struct radv_device
* device
;
542 VkBufferUsageFlags usage
;
545 struct radeon_winsys_bo
* bo
;
550 enum radv_cmd_dirty_bits
{
551 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
552 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
553 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
554 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
555 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
556 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
557 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
558 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
559 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
560 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
561 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
562 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
563 RADV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
565 typedef uint32_t radv_cmd_dirty_mask_t
;
567 enum radv_cmd_flush_bits
{
568 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
569 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
570 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
571 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
572 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
573 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
574 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
575 /* Framebuffer caches */
576 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 4,
577 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 5,
578 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 6,
579 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 7,
580 /* Engine synchronization. */
581 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 8,
582 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 9,
583 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 10,
584 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 11,
586 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
587 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
588 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
589 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
592 struct radv_vertex_binding
{
593 struct radv_buffer
* buffer
;
597 struct radv_dynamic_state
{
600 VkViewport viewports
[MAX_VIEWPORTS
];
605 VkRect2D scissors
[MAX_SCISSORS
];
616 float blend_constants
[4];
626 } stencil_compare_mask
;
631 } stencil_write_mask
;
639 extern const struct radv_dynamic_state default_dynamic_state
;
641 void radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
642 const struct radv_dynamic_state
*src
,
645 * Attachment state when recording a renderpass instance.
647 * The clear value is valid only if there exists a pending clear.
649 struct radv_attachment_state
{
650 VkImageAspectFlags pending_clear_aspects
;
651 VkClearValue clear_value
;
652 VkImageLayout current_layout
;
655 struct radv_cmd_state
{
657 bool vertex_descriptors_dirty
;
658 radv_cmd_dirty_mask_t dirty
;
660 struct radv_pipeline
* pipeline
;
661 struct radv_pipeline
* emitted_pipeline
;
662 struct radv_pipeline
* compute_pipeline
;
663 struct radv_pipeline
* emitted_compute_pipeline
;
664 struct radv_framebuffer
* framebuffer
;
665 struct radv_render_pass
* pass
;
666 const struct radv_subpass
* subpass
;
667 struct radv_dynamic_state dynamic
;
668 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
669 struct radv_descriptor_set
* descriptors
[MAX_SETS
];
670 struct radv_attachment_state
* attachments
;
671 VkRect2D render_area
;
672 struct radv_buffer
* index_buffer
;
674 uint32_t index_offset
;
675 uint32_t last_primitive_reset_index
;
676 enum radv_cmd_flush_bits flush_bits
;
677 unsigned active_occlusion_queries
;
679 uint32_t descriptors_dirty
;
682 struct radv_cmd_pool
{
683 VkAllocationCallbacks alloc
;
684 struct list_head cmd_buffers
;
685 uint32_t queue_family_index
;
688 struct radv_cmd_buffer_upload
{
692 struct radeon_winsys_bo
*upload_bo
;
693 struct list_head list
;
696 struct radv_cmd_buffer
{
697 VK_LOADER_DATA _loader_data
;
699 struct radv_device
* device
;
701 struct radv_cmd_pool
* pool
;
702 struct list_head pool_link
;
704 VkCommandBufferUsageFlags usage_flags
;
705 VkCommandBufferLevel level
;
706 struct radeon_winsys_cs
*cs
;
707 struct radv_cmd_state state
;
708 uint32_t queue_family_index
;
710 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
711 uint32_t dynamic_buffers
[16 * MAX_DYNAMIC_BUFFERS
];
712 VkShaderStageFlags push_constant_stages
;
714 struct radv_cmd_buffer_upload upload
;
721 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
723 void si_init_compute(struct radv_physical_device
*physical_device
,
724 struct radv_cmd_buffer
*cmd_buffer
);
725 void si_init_config(struct radv_physical_device
*physical_device
,
726 struct radv_cmd_buffer
*cmd_buffer
);
727 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
728 int count
, const VkViewport
*viewports
);
729 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
730 int count
, const VkRect2D
*scissors
);
731 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
);
732 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
733 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
734 uint64_t src_va
, uint64_t dest_va
,
736 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
737 uint64_t size
, unsigned value
);
738 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
739 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
740 struct radv_descriptor_set
*set
,
743 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
746 unsigned *out_offset
,
749 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
750 const struct radv_subpass
*subpass
,
753 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
754 unsigned size
, unsigned alignmnet
,
755 const void *data
, unsigned *out_offset
);
757 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
758 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
759 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
760 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
761 unsigned radv_cayman_get_maxdist(int log_samples
);
762 void radv_device_init_msaa(struct radv_device
*device
);
763 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
764 struct radv_image
*image
,
765 VkClearDepthStencilValue ds_clear_value
,
766 VkImageAspectFlags aspects
);
767 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
768 struct radv_image
*image
,
770 uint32_t color_values
[2]);
771 void radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
772 struct radeon_winsys_bo
*bo
,
773 uint64_t offset
, uint64_t size
, uint32_t value
);
776 * Takes x,y,z as exact numbers of invocations, instead of blocks.
778 * Limitations: Can't call normal dispatch functions without binding or rebinding
779 * the compute pipeline.
781 void radv_unaligned_dispatch(
782 struct radv_cmd_buffer
*cmd_buffer
,
788 struct radeon_winsys_bo
*bo
;
794 struct radv_shader_module
{
795 struct nir_shader
* nir
;
796 unsigned char sha1
[20];
801 union ac_shader_variant_key
;
804 radv_hash_shader(unsigned char *hash
, struct radv_shader_module
*module
,
805 const char *entrypoint
,
806 const VkSpecializationInfo
*spec_info
,
807 const struct radv_pipeline_layout
*layout
,
808 const union ac_shader_variant_key
*key
);
810 static inline gl_shader_stage
811 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
813 assert(__builtin_popcount(vk_stage
) == 1);
814 return ffs(vk_stage
) - 1;
817 static inline VkShaderStageFlagBits
818 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
820 return (1 << mesa_stage
);
823 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
825 #define radv_foreach_stage(stage, stage_bits) \
826 for (gl_shader_stage stage, \
827 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
828 stage = __builtin_ffs(__tmp) - 1, __tmp; \
829 __tmp &= ~(1 << (stage)))
831 struct radv_shader_variant
{
834 struct radeon_winsys_bo
*bo
;
835 struct ac_shader_config config
;
836 struct ac_shader_variant_info info
;
842 struct radv_depth_stencil_state
{
843 uint32_t db_depth_control
;
844 uint32_t db_stencil_control
;
845 uint32_t db_render_control
;
846 uint32_t db_render_override2
;
849 struct radv_blend_state
{
850 uint32_t cb_color_control
;
851 uint32_t cb_target_mask
;
852 uint32_t sx_mrt0_blend_opt
[8];
853 uint32_t cb_blend_control
[8];
855 uint32_t spi_shader_col_format
;
856 uint32_t cb_shader_mask
;
857 uint32_t db_alpha_to_mask
;
860 unsigned radv_format_meta_fs_key(VkFormat format
);
862 struct radv_raster_state
{
863 uint32_t pa_cl_clip_cntl
;
864 uint32_t pa_cl_vs_out_cntl
;
865 uint32_t spi_interp_control
;
866 uint32_t pa_su_point_size
;
867 uint32_t pa_su_point_minmax
;
868 uint32_t pa_su_line_cntl
;
869 uint32_t pa_su_vtx_cntl
;
870 uint32_t pa_su_sc_mode_cntl
;
873 struct radv_multisample_state
{
875 uint32_t pa_sc_line_cntl
;
876 uint32_t pa_sc_mode_cntl_0
;
877 uint32_t pa_sc_mode_cntl_1
;
878 uint32_t pa_sc_aa_config
;
879 uint32_t pa_sc_aa_mask
[2];
880 unsigned num_samples
;
883 struct radv_pipeline
{
884 struct radv_device
* device
;
885 uint32_t dynamic_state_mask
;
886 struct radv_dynamic_state dynamic_state
;
888 struct radv_pipeline_layout
* layout
;
890 bool needs_data_cache
;
892 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
893 VkShaderStageFlags active_stages
;
895 uint32_t va_rsrc_word3
[MAX_VERTEX_ATTRIBS
];
896 uint32_t va_format_size
[MAX_VERTEX_ATTRIBS
];
897 uint32_t va_binding
[MAX_VERTEX_ATTRIBS
];
898 uint32_t va_offset
[MAX_VERTEX_ATTRIBS
];
899 uint32_t num_vertex_attribs
;
900 uint32_t binding_stride
[MAX_VBS
];
904 struct radv_blend_state blend
;
905 struct radv_depth_stencil_state ds
;
906 struct radv_raster_state raster
;
907 struct radv_multisample_state ms
;
910 bool prim_restart_enable
;
915 struct radv_graphics_pipeline_create_info
{
918 bool db_stencil_clear
;
919 bool db_depth_disable_expclear
;
920 bool db_stencil_disable_expclear
;
921 bool db_flush_depth_inplace
;
922 bool db_flush_stencil_inplace
;
924 uint32_t custom_blend_mode
;
928 radv_pipeline_init(struct radv_pipeline
*pipeline
, struct radv_device
*device
,
929 struct radv_pipeline_cache
*cache
,
930 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
931 const struct radv_graphics_pipeline_create_info
*extra
,
932 const VkAllocationCallbacks
*alloc
);
935 radv_graphics_pipeline_create(VkDevice device
,
936 VkPipelineCache cache
,
937 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
938 const struct radv_graphics_pipeline_create_info
*extra
,
939 const VkAllocationCallbacks
*alloc
,
940 VkPipeline
*pPipeline
);
942 struct vk_format_description
;
943 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
945 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
947 uint32_t radv_translate_colorformat(VkFormat format
);
948 uint32_t radv_translate_color_numformat(VkFormat format
,
949 const struct vk_format_description
*desc
,
951 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
952 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
953 uint32_t radv_translate_dbformat(VkFormat format
);
954 uint32_t radv_translate_tex_dataformat(VkFormat format
,
955 const struct vk_format_description
*desc
,
957 uint32_t radv_translate_tex_numformat(VkFormat format
,
958 const struct vk_format_description
*desc
,
960 bool radv_format_pack_clear_color(VkFormat format
,
961 uint32_t clear_vals
[2],
962 VkClearColorValue
*value
);
963 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
965 struct radv_fmask_info
{
969 unsigned pitch_in_pixels
;
970 unsigned bank_height
;
971 unsigned slice_tile_max
;
972 unsigned tile_mode_index
;
975 struct radv_cmask_info
{
979 unsigned slice_tile_max
;
980 unsigned base_address_reg
;
983 struct r600_htile_info
{
994 /* The original VkFormat provided by the client. This may not match any
995 * of the actual surface formats.
998 VkImageAspectFlags aspects
;
1001 uint32_t array_size
;
1002 uint32_t samples
; /**< VkImageCreateInfo::samples */
1003 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1004 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1010 unsigned queue_family_mask
;
1012 /* Set when bound */
1013 struct radeon_winsys_bo
*bo
;
1014 VkDeviceSize offset
;
1015 uint32_t dcc_offset
;
1016 struct radeon_surf surface
;
1018 struct radv_fmask_info fmask
;
1019 struct radv_cmask_info cmask
;
1020 uint32_t clear_value_offset
;
1022 /* Depth buffer compression and fast clear. */
1023 struct r600_htile_info htile
;
1026 bool radv_layout_has_htile(const struct radv_image
*image
,
1027 VkImageLayout layout
);
1028 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1029 VkImageLayout layout
);
1030 bool radv_layout_can_expclear(const struct radv_image
*image
,
1031 VkImageLayout layout
);
1032 bool radv_layout_has_cmask(const struct radv_image
*image
,
1033 VkImageLayout layout
,
1034 unsigned queue_mask
);
1037 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, int family
);
1039 static inline uint32_t
1040 radv_get_layerCount(const struct radv_image
*image
,
1041 const VkImageSubresourceRange
*range
)
1043 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1044 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1047 static inline uint32_t
1048 radv_get_levelCount(const struct radv_image
*image
,
1049 const VkImageSubresourceRange
*range
)
1051 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1052 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1055 struct radeon_bo_metadata
;
1057 radv_init_metadata(struct radv_device
*device
,
1058 struct radv_image
*image
,
1059 struct radeon_bo_metadata
*metadata
);
1061 struct radv_image_view
{
1062 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1063 struct radeon_winsys_bo
*bo
;
1065 VkImageViewType type
;
1066 VkImageAspectFlags aspect_mask
;
1068 uint32_t base_layer
;
1069 uint32_t layer_count
;
1071 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1073 uint32_t descriptor
[8];
1074 uint32_t fmask_descriptor
[8];
1077 struct radv_image_create_info
{
1078 const VkImageCreateInfo
*vk_info
;
1083 VkResult
radv_image_create(VkDevice _device
,
1084 const struct radv_image_create_info
*info
,
1085 const VkAllocationCallbacks
* alloc
,
1088 void radv_image_view_init(struct radv_image_view
*view
,
1089 struct radv_device
*device
,
1090 const VkImageViewCreateInfo
* pCreateInfo
,
1091 struct radv_cmd_buffer
*cmd_buffer
,
1092 VkImageUsageFlags usage_mask
);
1093 void radv_image_set_optimal_micro_tile_mode(struct radv_device
*device
,
1094 struct radv_image
*image
, uint32_t micro_tile_mode
);
1095 struct radv_buffer_view
{
1096 struct radeon_winsys_bo
*bo
;
1098 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1101 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1102 struct radv_device
*device
,
1103 const VkBufferViewCreateInfo
* pCreateInfo
,
1104 struct radv_cmd_buffer
*cmd_buffer
);
1106 static inline struct VkExtent3D
1107 radv_sanitize_image_extent(const VkImageType imageType
,
1108 const struct VkExtent3D imageExtent
)
1110 switch (imageType
) {
1111 case VK_IMAGE_TYPE_1D
:
1112 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1113 case VK_IMAGE_TYPE_2D
:
1114 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1115 case VK_IMAGE_TYPE_3D
:
1118 unreachable("invalid image type");
1122 static inline struct VkOffset3D
1123 radv_sanitize_image_offset(const VkImageType imageType
,
1124 const struct VkOffset3D imageOffset
)
1126 switch (imageType
) {
1127 case VK_IMAGE_TYPE_1D
:
1128 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1129 case VK_IMAGE_TYPE_2D
:
1130 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1131 case VK_IMAGE_TYPE_3D
:
1134 unreachable("invalid image type");
1138 struct radv_sampler
{
1142 struct radv_color_buffer_info
{
1143 uint32_t cb_color_base
;
1144 uint32_t cb_color_pitch
;
1145 uint32_t cb_color_slice
;
1146 uint32_t cb_color_view
;
1147 uint32_t cb_color_info
;
1148 uint32_t cb_color_attrib
;
1149 uint32_t cb_dcc_control
;
1150 uint32_t cb_color_cmask
;
1151 uint32_t cb_color_cmask_slice
;
1152 uint32_t cb_color_fmask
;
1153 uint32_t cb_color_fmask_slice
;
1154 uint32_t cb_clear_value0
;
1155 uint32_t cb_clear_value1
;
1156 uint32_t cb_dcc_base
;
1157 uint32_t micro_tile_mode
;
1160 struct radv_ds_buffer_info
{
1161 uint32_t db_depth_info
;
1163 uint32_t db_stencil_info
;
1164 uint32_t db_z_read_base
;
1165 uint32_t db_stencil_read_base
;
1166 uint32_t db_z_write_base
;
1167 uint32_t db_stencil_write_base
;
1168 uint32_t db_depth_view
;
1169 uint32_t db_depth_size
;
1170 uint32_t db_depth_slice
;
1171 uint32_t db_htile_surface
;
1172 uint32_t db_htile_data_base
;
1173 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1177 struct radv_attachment_info
{
1179 struct radv_color_buffer_info cb
;
1180 struct radv_ds_buffer_info ds
;
1182 struct radv_image_view
*attachment
;
1185 struct radv_framebuffer
{
1190 uint32_t attachment_count
;
1191 struct radv_attachment_info attachments
[0];
1194 struct radv_subpass_barrier
{
1195 VkPipelineStageFlags src_stage_mask
;
1196 VkAccessFlags src_access_mask
;
1197 VkAccessFlags dst_access_mask
;
1200 struct radv_subpass
{
1201 uint32_t input_count
;
1202 VkAttachmentReference
* input_attachments
;
1203 uint32_t color_count
;
1204 VkAttachmentReference
* color_attachments
;
1205 VkAttachmentReference
* resolve_attachments
;
1206 VkAttachmentReference depth_stencil_attachment
;
1208 /** Subpass has at least one resolve attachment */
1211 struct radv_subpass_barrier start_barrier
;
1214 struct radv_render_pass_attachment
{
1217 VkAttachmentLoadOp load_op
;
1218 VkAttachmentLoadOp stencil_load_op
;
1219 VkImageLayout initial_layout
;
1220 VkImageLayout final_layout
;
1223 struct radv_render_pass
{
1224 uint32_t attachment_count
;
1225 uint32_t subpass_count
;
1226 VkAttachmentReference
* subpass_attachments
;
1227 struct radv_render_pass_attachment
* attachments
;
1228 struct radv_subpass_barrier end_barrier
;
1229 struct radv_subpass subpasses
[0];
1232 VkResult
radv_device_init_meta(struct radv_device
*device
);
1233 void radv_device_finish_meta(struct radv_device
*device
);
1235 struct radv_query_pool
{
1236 struct radeon_winsys_bo
*bo
;
1238 uint32_t availability_offset
;
1244 radv_temp_descriptor_set_create(struct radv_device
*device
,
1245 struct radv_cmd_buffer
*cmd_buffer
,
1246 VkDescriptorSetLayout _layout
,
1247 VkDescriptorSet
*_set
);
1250 radv_temp_descriptor_set_destroy(struct radv_device
*device
,
1251 VkDescriptorSet _set
);
1252 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1253 struct radv_image
*image
, uint32_t value
);
1254 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1255 struct radv_image
*image
, uint32_t value
);
1258 struct radeon_winsys_fence
*fence
;
1263 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1265 static inline struct __radv_type * \
1266 __radv_type ## _from_handle(__VkType _handle) \
1268 return (struct __radv_type *) _handle; \
1271 static inline __VkType \
1272 __radv_type ## _to_handle(struct __radv_type *_obj) \
1274 return (__VkType) _obj; \
1277 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1279 static inline struct __radv_type * \
1280 __radv_type ## _from_handle(__VkType _handle) \
1282 return (struct __radv_type *)(uintptr_t) _handle; \
1285 static inline __VkType \
1286 __radv_type ## _to_handle(struct __radv_type *_obj) \
1288 return (__VkType)(uintptr_t) _obj; \
1291 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1292 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1294 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1295 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1296 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1297 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1298 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1300 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1301 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1302 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1303 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1304 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1305 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1306 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1307 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1308 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1309 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1310 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1311 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1312 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1313 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1314 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1315 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1316 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1317 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1318 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1320 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1322 static inline const __VkType * \
1323 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1325 return (const __VkType *) __radv_obj; \
1328 #endif /* RADV_PRIVATE_H */