2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_debug.h"
59 #include "radv_descriptor_set.h"
61 #include <llvm-c/TargetMachine.h>
63 /* Pre-declarations needed for WSI entrypoints */
66 typedef struct xcb_connection_t xcb_connection_t
;
67 typedef uint32_t xcb_visualid_t
;
68 typedef uint32_t xcb_window_t
;
70 #include <vulkan/vulkan.h>
71 #include <vulkan/vulkan_intel.h>
72 #include <vulkan/vk_icd.h>
74 #include "radv_entrypoints.h"
76 #include "wsi_common.h"
79 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_VIEWPORTS 16
82 #define MAX_SCISSORS 16
83 #define MAX_PUSH_CONSTANTS_SIZE 128
84 #define MAX_PUSH_DESCRIPTORS 32
85 #define MAX_DYNAMIC_BUFFERS 16
86 #define MAX_SAMPLES_LOG2 4
87 #define NUM_META_FS_KEYS 13
88 #define RADV_MAX_DRM_DEVICES 8
91 #define NUM_DEPTH_CLEAR_PIPELINES 3
95 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
102 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
103 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
104 RADV_MEM_TYPE_GTT_CACHED
,
108 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110 static inline uint32_t
111 align_u32(uint32_t v
, uint32_t a
)
113 assert(a
!= 0 && a
== (a
& -a
));
114 return (v
+ a
- 1) & ~(a
- 1);
117 static inline uint32_t
118 align_u32_npot(uint32_t v
, uint32_t a
)
120 return (v
+ a
- 1) / a
* a
;
123 static inline uint64_t
124 align_u64(uint64_t v
, uint64_t a
)
126 assert(a
!= 0 && a
== (a
& -a
));
127 return (v
+ a
- 1) & ~(a
- 1);
130 static inline int32_t
131 align_i32(int32_t v
, int32_t a
)
133 assert(a
!= 0 && a
== (a
& -a
));
134 return (v
+ a
- 1) & ~(a
- 1);
137 /** Alignment must be a power of 2. */
139 radv_is_aligned(uintmax_t n
, uintmax_t a
)
141 assert(a
== (a
& -a
));
142 return (n
& (a
- 1)) == 0;
145 static inline uint32_t
146 round_up_u32(uint32_t v
, uint32_t a
)
148 return (v
+ a
- 1) / a
;
151 static inline uint64_t
152 round_up_u64(uint64_t v
, uint64_t a
)
154 return (v
+ a
- 1) / a
;
157 static inline uint32_t
158 radv_minify(uint32_t n
, uint32_t levels
)
160 if (unlikely(n
== 0))
163 return MAX2(n
>> levels
, 1);
166 radv_clamp_f(float f
, float min
, float max
)
179 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
181 if (*inout_mask
& clear_mask
) {
182 *inout_mask
&= ~clear_mask
;
189 #define for_each_bit(b, dword) \
190 for (uint32_t __dword = (dword); \
191 (b) = __builtin_ffs(__dword) - 1, __dword; \
192 __dword &= ~(1 << (b)))
194 #define typed_memcpy(dest, src, count) ({ \
195 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
196 memcpy((dest), (src), (count) * sizeof(*(src))); \
199 #define zero(x) (memset(&(x), 0, sizeof(x)))
201 /* Whenever we generate an error, pass it through this function. Useful for
202 * debugging, where we can break on it. Only call at error site, not when
203 * propagating errors. Might be useful to plug in a stack trace here.
206 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
209 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
210 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
212 #define vk_error(error) error
213 #define vk_errorf(error, format, ...) error
216 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format
, va_list va
);
222 * Print a FINISHME message, including its source location.
224 #define radv_finishme(format, ...) \
226 static bool reported = false; \
228 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
233 /* A non-fatal assert. Useful for debugging. */
235 #define radv_assert(x) ({ \
236 if (unlikely(!(x))) \
237 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 #define radv_assert(x)
243 #define stub_return(v) \
245 radv_finishme("stub %s", __func__); \
251 radv_finishme("stub %s", __func__); \
255 void *radv_lookup_entrypoint(const char *name
);
257 struct radv_extensions
{
258 VkExtensionProperties
*ext_array
;
262 struct radv_physical_device
{
263 VK_LOADER_DATA _loader_data
;
265 struct radv_instance
* instance
;
267 struct radeon_winsys
*ws
;
268 struct radeon_info rad_info
;
271 uint8_t driver_uuid
[VK_UUID_SIZE
];
272 uint8_t device_uuid
[VK_UUID_SIZE
];
273 uint8_t cache_uuid
[VK_UUID_SIZE
];
276 struct wsi_device wsi_device
;
277 struct radv_extensions extensions
;
279 bool has_rbplus
; /* if RB+ register exist */
280 bool rbplus_allowed
; /* if RB+ is allowed */
283 struct radv_instance
{
284 VK_LOADER_DATA _loader_data
;
286 VkAllocationCallbacks alloc
;
289 int physicalDeviceCount
;
290 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
292 uint64_t debug_flags
;
293 uint64_t perftest_flags
;
296 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
297 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
301 struct radv_pipeline_cache
{
302 struct radv_device
* device
;
303 pthread_mutex_t mutex
;
307 uint32_t kernel_count
;
308 struct cache_entry
** hash_table
;
311 VkAllocationCallbacks alloc
;
315 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
316 struct radv_device
*device
);
318 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
320 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
321 const void *data
, size_t size
);
323 struct radv_shader_variant
*
324 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
325 struct radv_pipeline_cache
*cache
,
326 const unsigned char *sha1
);
328 struct radv_shader_variant
*
329 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache
*cache
,
330 const unsigned char *sha1
,
331 struct radv_shader_variant
*variant
,
332 const void *code
, unsigned code_size
);
334 void radv_shader_variant_destroy(struct radv_device
*device
,
335 struct radv_shader_variant
*variant
);
337 struct radv_meta_state
{
338 VkAllocationCallbacks alloc
;
340 struct radv_pipeline_cache cache
;
343 * Use array element `i` for images with `2^i` samples.
346 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
347 struct radv_pipeline
*color_pipelines
[NUM_META_FS_KEYS
];
349 VkRenderPass depthstencil_rp
;
350 struct radv_pipeline
*depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
351 struct radv_pipeline
*stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
352 struct radv_pipeline
*depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
353 } clear
[1 + MAX_SAMPLES_LOG2
];
355 VkPipelineLayout clear_color_p_layout
;
356 VkPipelineLayout clear_depth_p_layout
;
358 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
360 /** Pipeline that blits from a 1D image. */
361 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
363 /** Pipeline that blits from a 2D image. */
364 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
366 /** Pipeline that blits from a 3D image. */
367 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
369 VkRenderPass depth_only_rp
;
370 VkPipeline depth_only_1d_pipeline
;
371 VkPipeline depth_only_2d_pipeline
;
372 VkPipeline depth_only_3d_pipeline
;
374 VkRenderPass stencil_only_rp
;
375 VkPipeline stencil_only_1d_pipeline
;
376 VkPipeline stencil_only_2d_pipeline
;
377 VkPipeline stencil_only_3d_pipeline
;
378 VkPipelineLayout pipeline_layout
;
379 VkDescriptorSetLayout ds_layout
;
383 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
385 VkPipelineLayout p_layouts
[2];
386 VkDescriptorSetLayout ds_layouts
[2];
387 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
389 VkRenderPass depth_only_rp
;
390 VkPipeline depth_only_pipeline
[2];
392 VkRenderPass stencil_only_rp
;
393 VkPipeline stencil_only_pipeline
[2];
397 VkPipelineLayout img_p_layout
;
398 VkDescriptorSetLayout img_ds_layout
;
402 VkRenderPass render_pass
;
403 VkPipelineLayout img_p_layout
;
404 VkDescriptorSetLayout img_ds_layout
;
408 VkPipelineLayout img_p_layout
;
409 VkDescriptorSetLayout img_ds_layout
;
413 VkPipelineLayout img_p_layout
;
414 VkDescriptorSetLayout img_ds_layout
;
424 VkDescriptorSetLayout ds_layout
;
425 VkPipelineLayout p_layout
;
428 VkPipeline i_pipeline
;
429 VkPipeline srgb_pipeline
;
430 } rc
[MAX_SAMPLES_LOG2
];
434 VkDescriptorSetLayout ds_layout
;
435 VkPipelineLayout p_layout
;
438 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
439 VkPipeline pipeline
[NUM_META_FS_KEYS
];
440 } rc
[MAX_SAMPLES_LOG2
];
444 VkPipeline decompress_pipeline
;
445 VkPipeline resummarize_pipeline
;
447 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
450 VkPipeline cmask_eliminate_pipeline
;
451 VkPipeline fmask_decompress_pipeline
;
456 VkPipelineLayout fill_p_layout
;
457 VkPipelineLayout copy_p_layout
;
458 VkDescriptorSetLayout fill_ds_layout
;
459 VkDescriptorSetLayout copy_ds_layout
;
460 VkPipeline fill_pipeline
;
461 VkPipeline copy_pipeline
;
465 VkDescriptorSetLayout ds_layout
;
466 VkPipelineLayout p_layout
;
467 VkPipeline occlusion_query_pipeline
;
468 VkPipeline pipeline_statistics_query_pipeline
;
473 #define RADV_QUEUE_GENERAL 0
474 #define RADV_QUEUE_COMPUTE 1
475 #define RADV_QUEUE_TRANSFER 2
477 #define RADV_MAX_QUEUE_FAMILIES 3
479 enum ring_type
radv_queue_family_to_ring(int f
);
482 VK_LOADER_DATA _loader_data
;
483 struct radv_device
* device
;
484 struct radeon_winsys_ctx
*hw_ctx
;
485 int queue_family_index
;
488 uint32_t scratch_size
;
489 uint32_t compute_scratch_size
;
490 uint32_t esgs_ring_size
;
491 uint32_t gsvs_ring_size
;
493 bool has_sample_positions
;
495 struct radeon_winsys_bo
*scratch_bo
;
496 struct radeon_winsys_bo
*descriptor_bo
;
497 struct radeon_winsys_bo
*compute_scratch_bo
;
498 struct radeon_winsys_bo
*esgs_ring_bo
;
499 struct radeon_winsys_bo
*gsvs_ring_bo
;
500 struct radeon_winsys_bo
*tess_factor_ring_bo
;
501 struct radeon_winsys_bo
*tess_offchip_ring_bo
;
502 struct radeon_winsys_cs
*initial_preamble_cs
;
503 struct radeon_winsys_cs
*continue_preamble_cs
;
507 VK_LOADER_DATA _loader_data
;
509 VkAllocationCallbacks alloc
;
511 struct radv_instance
* instance
;
512 struct radeon_winsys
*ws
;
514 struct radv_meta_state meta_state
;
516 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
517 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
518 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
519 struct radeon_winsys_cs
*flush_cs
[RADV_MAX_QUEUE_FAMILIES
];
520 struct radeon_winsys_cs
*flush_shader_cs
[RADV_MAX_QUEUE_FAMILIES
];
521 uint64_t debug_flags
;
523 bool llvm_supports_spill
;
524 bool has_distributed_tess
;
525 uint32_t tess_offchip_block_dw_size
;
526 uint32_t scratch_waves
;
528 uint32_t gs_table_depth
;
530 /* MSAA sample locations.
531 * The first index is the sample index.
532 * The second index is the coordinate: X, Y. */
533 float sample_locations_1x
[1][2];
534 float sample_locations_2x
[2][2];
535 float sample_locations_4x
[4][2];
536 float sample_locations_8x
[8][2];
537 float sample_locations_16x
[16][2];
540 uint32_t gfx_init_size_dw
;
541 struct radeon_winsys_bo
*gfx_init
;
543 struct radeon_winsys_bo
*trace_bo
;
544 uint32_t *trace_id_ptr
;
546 struct radv_physical_device
*physical_device
;
548 /* Backup in-memory cache to be used if the app doesn't provide one */
549 struct radv_pipeline_cache
* mem_cache
;
552 * use different counters so MSAA MRTs get consecutive surface indices,
553 * even if MASK is allocated in between.
555 uint32_t image_mrt_offset_counter
;
556 uint32_t fmask_mrt_offset_counter
;
557 struct list_head shader_slabs
;
558 mtx_t shader_slab_mutex
;
561 struct radv_device_memory
{
562 struct radeon_winsys_bo
*bo
;
563 /* for dedicated allocations */
564 struct radv_image
*image
;
565 struct radv_buffer
*buffer
;
567 VkDeviceSize map_size
;
572 struct radv_descriptor_range
{
577 struct radv_descriptor_set
{
578 const struct radv_descriptor_set_layout
*layout
;
581 struct radeon_winsys_bo
*bo
;
583 uint32_t *mapped_ptr
;
584 struct radv_descriptor_range
*dynamic_descriptors
;
586 struct list_head vram_list
;
588 struct radeon_winsys_bo
*descriptors
[0];
591 struct radv_push_descriptor_set
593 struct radv_descriptor_set set
;
597 struct radv_descriptor_pool
{
598 struct radeon_winsys_bo
*bo
;
600 uint64_t current_offset
;
603 struct list_head vram_list
;
605 uint8_t *host_memory_base
;
606 uint8_t *host_memory_ptr
;
607 uint8_t *host_memory_end
;
610 struct radv_descriptor_update_template_entry
{
611 VkDescriptorType descriptor_type
;
613 /* The number of descriptors to update */
614 uint32_t descriptor_count
;
616 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
619 /* In dwords. Not valid/used for dynamic descriptors */
622 uint32_t buffer_offset
;
624 /* Only valid for combined image samplers and samplers */
625 uint16_t has_sampler
;
631 /* For push descriptors */
632 const uint32_t *immutable_samplers
;
635 struct radv_descriptor_update_template
{
636 uint32_t entry_count
;
637 struct radv_descriptor_update_template_entry entry
[0];
641 struct radv_device
* device
;
644 VkBufferUsageFlags usage
;
645 VkBufferCreateFlags flags
;
648 struct radeon_winsys_bo
* bo
;
653 enum radv_cmd_dirty_bits
{
654 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
655 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
656 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
657 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
658 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
659 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
660 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
661 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
662 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
663 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
664 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
665 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
666 RADV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
668 typedef uint32_t radv_cmd_dirty_mask_t
;
670 enum radv_cmd_flush_bits
{
671 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
672 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
673 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
674 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
675 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
676 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
677 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
678 /* Same as above, but only writes back and doesn't invalidate */
679 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
680 /* Framebuffer caches */
681 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
682 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
683 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
684 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
685 /* Engine synchronization. */
686 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
687 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
688 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
689 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
691 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
692 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
693 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
694 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
697 struct radv_vertex_binding
{
698 struct radv_buffer
* buffer
;
702 struct radv_dynamic_state
{
705 VkViewport viewports
[MAX_VIEWPORTS
];
710 VkRect2D scissors
[MAX_SCISSORS
];
721 float blend_constants
[4];
731 } stencil_compare_mask
;
736 } stencil_write_mask
;
744 extern const struct radv_dynamic_state default_dynamic_state
;
746 void radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
747 const struct radv_dynamic_state
*src
,
750 * Attachment state when recording a renderpass instance.
752 * The clear value is valid only if there exists a pending clear.
754 struct radv_attachment_state
{
755 VkImageAspectFlags pending_clear_aspects
;
756 uint32_t cleared_views
;
757 VkClearValue clear_value
;
758 VkImageLayout current_layout
;
761 struct radv_cmd_state
{
763 radv_cmd_dirty_mask_t dirty
;
764 bool push_descriptors_dirty
;
766 struct radv_pipeline
* pipeline
;
767 struct radv_pipeline
* emitted_pipeline
;
768 struct radv_pipeline
* compute_pipeline
;
769 struct radv_pipeline
* emitted_compute_pipeline
;
770 struct radv_framebuffer
* framebuffer
;
771 struct radv_render_pass
* pass
;
772 const struct radv_subpass
* subpass
;
773 struct radv_dynamic_state dynamic
;
774 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
775 struct radv_descriptor_set
* descriptors
[MAX_SETS
];
776 struct radv_attachment_state
* attachments
;
777 VkRect2D render_area
;
780 uint32_t max_index_count
;
781 int32_t last_primitive_reset_en
;
782 uint32_t last_primitive_reset_index
;
783 enum radv_cmd_flush_bits flush_bits
;
784 unsigned active_occlusion_queries
;
786 uint32_t descriptors_dirty
;
788 uint32_t last_ia_multi_vgt_param
;
792 struct radv_cmd_pool
{
793 VkAllocationCallbacks alloc
;
794 struct list_head cmd_buffers
;
795 struct list_head free_cmd_buffers
;
796 uint32_t queue_family_index
;
799 struct radv_cmd_buffer_upload
{
803 struct radeon_winsys_bo
*upload_bo
;
804 struct list_head list
;
807 struct radv_cmd_buffer
{
808 VK_LOADER_DATA _loader_data
;
810 struct radv_device
* device
;
812 struct radv_cmd_pool
* pool
;
813 struct list_head pool_link
;
815 VkCommandBufferUsageFlags usage_flags
;
816 VkCommandBufferLevel level
;
817 struct radeon_winsys_cs
*cs
;
818 struct radv_cmd_state state
;
819 uint32_t queue_family_index
;
821 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
822 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
823 VkShaderStageFlags push_constant_stages
;
824 struct radv_push_descriptor_set push_descriptors
;
825 struct radv_descriptor_set meta_push_descriptors
;
827 struct radv_cmd_buffer_upload upload
;
829 uint32_t scratch_size_needed
;
830 uint32_t compute_scratch_size_needed
;
831 uint32_t esgs_ring_size_needed
;
832 uint32_t gsvs_ring_size_needed
;
833 bool tess_rings_needed
;
834 bool sample_positions_needed
;
838 int ring_offsets_idx
; /* just used for verification */
839 uint32_t gfx9_fence_offset
;
840 struct radeon_winsys_bo
*gfx9_fence_bo
;
841 uint32_t gfx9_fence_idx
;
846 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
848 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
849 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
851 void cik_create_gfx_config(struct radv_device
*device
);
853 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
854 int count
, const VkViewport
*viewports
);
855 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
856 int count
, const VkRect2D
*scissors
,
857 const VkViewport
*viewports
, bool can_use_guardband
);
858 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
859 bool instanced_draw
, bool indirect_draw
,
860 uint32_t draw_vertex_count
);
861 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
863 enum chip_class chip_class
,
865 unsigned event
, unsigned event_flags
,
871 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
873 uint64_t va
, uint32_t ref
,
875 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
877 enum chip_class chip_class
,
878 uint32_t *fence_ptr
, uint64_t va
,
880 enum radv_cmd_flush_bits flush_bits
);
881 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
882 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
883 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
884 uint64_t src_va
, uint64_t dest_va
,
886 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
888 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
889 uint64_t size
, unsigned value
);
890 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
891 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
892 struct radv_descriptor_set
*set
,
895 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
898 unsigned *out_offset
,
901 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
902 const struct radv_subpass
*subpass
,
905 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
906 unsigned size
, unsigned alignmnet
,
907 const void *data
, unsigned *out_offset
);
909 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
910 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
911 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
912 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
913 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
914 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
915 unsigned radv_cayman_get_maxdist(int log_samples
);
916 void radv_device_init_msaa(struct radv_device
*device
);
917 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
918 struct radv_image
*image
,
919 VkClearDepthStencilValue ds_clear_value
,
920 VkImageAspectFlags aspects
);
921 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
922 struct radv_image
*image
,
924 uint32_t color_values
[2]);
925 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
926 struct radv_image
*image
,
928 void radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
929 struct radeon_winsys_bo
*bo
,
930 uint64_t offset
, uint64_t size
, uint32_t value
);
931 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
932 bool radv_get_memory_fd(struct radv_device
*device
,
933 struct radv_device_memory
*memory
,
936 * Takes x,y,z as exact numbers of invocations, instead of blocks.
938 * Limitations: Can't call normal dispatch functions without binding or rebinding
939 * the compute pipeline.
941 void radv_unaligned_dispatch(
942 struct radv_cmd_buffer
*cmd_buffer
,
948 struct radeon_winsys_bo
*bo
;
954 struct radv_shader_module
{
955 struct nir_shader
* nir
;
956 unsigned char sha1
[20];
961 struct ac_shader_variant_key
;
964 radv_hash_shader(unsigned char *hash
, struct radv_shader_module
*module
,
965 const char *entrypoint
,
966 const VkSpecializationInfo
*spec_info
,
967 const struct radv_pipeline_layout
*layout
,
968 const struct ac_shader_variant_key
*key
,
969 uint32_t is_geom_copy_shader
);
971 static inline gl_shader_stage
972 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
974 assert(__builtin_popcount(vk_stage
) == 1);
975 return ffs(vk_stage
) - 1;
978 static inline VkShaderStageFlagBits
979 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
981 return (1 << mesa_stage
);
984 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
986 #define radv_foreach_stage(stage, stage_bits) \
987 for (gl_shader_stage stage, \
988 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
989 stage = __builtin_ffs(__tmp) - 1, __tmp; \
990 __tmp &= ~(1 << (stage)))
993 struct radv_shader_slab
{
994 struct list_head slabs
;
995 struct list_head shaders
;
996 struct radeon_winsys_bo
*bo
;
1001 struct radv_shader_variant
{
1004 struct radeon_winsys_bo
*bo
;
1006 struct ac_shader_config config
;
1007 struct ac_shader_variant_info info
;
1012 struct list_head slab_list
;
1016 void *radv_alloc_shader_memory(struct radv_device
*device
,
1017 struct radv_shader_variant
*shader
);
1019 void radv_destroy_shader_slabs(struct radv_device
*device
);
1021 struct radv_depth_stencil_state
{
1022 uint32_t db_depth_control
;
1023 uint32_t db_stencil_control
;
1024 uint32_t db_render_control
;
1025 uint32_t db_render_override2
;
1028 struct radv_blend_state
{
1029 uint32_t cb_color_control
;
1030 uint32_t cb_target_mask
;
1031 uint32_t sx_mrt_blend_opt
[8];
1032 uint32_t cb_blend_control
[8];
1034 uint32_t spi_shader_col_format
;
1035 uint32_t cb_shader_mask
;
1036 uint32_t db_alpha_to_mask
;
1039 unsigned radv_format_meta_fs_key(VkFormat format
);
1041 struct radv_raster_state
{
1042 uint32_t pa_cl_clip_cntl
;
1043 uint32_t spi_interp_control
;
1044 uint32_t pa_su_point_size
;
1045 uint32_t pa_su_point_minmax
;
1046 uint32_t pa_su_line_cntl
;
1047 uint32_t pa_su_vtx_cntl
;
1048 uint32_t pa_su_sc_mode_cntl
;
1051 struct radv_multisample_state
{
1053 uint32_t pa_sc_line_cntl
;
1054 uint32_t pa_sc_mode_cntl_0
;
1055 uint32_t pa_sc_mode_cntl_1
;
1056 uint32_t pa_sc_aa_config
;
1057 uint32_t pa_sc_aa_mask
[2];
1058 unsigned num_samples
;
1061 struct radv_prim_vertex_count
{
1066 struct radv_tessellation_state
{
1067 uint32_t ls_hs_config
;
1068 uint32_t tcs_in_layout
;
1069 uint32_t tcs_out_layout
;
1070 uint32_t tcs_out_offsets
;
1071 uint32_t offchip_layout
;
1072 unsigned num_patches
;
1074 unsigned num_tcs_input_cp
;
1078 struct radv_pipeline
{
1079 struct radv_device
* device
;
1080 uint32_t dynamic_state_mask
;
1081 struct radv_dynamic_state dynamic_state
;
1083 struct radv_pipeline_layout
* layout
;
1085 bool needs_data_cache
;
1086 bool need_indirect_descriptor_sets
;
1087 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1088 struct radv_shader_variant
*gs_copy_shader
;
1089 VkShaderStageFlags active_stages
;
1091 uint32_t va_rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1092 uint32_t va_format_size
[MAX_VERTEX_ATTRIBS
];
1093 uint32_t va_binding
[MAX_VERTEX_ATTRIBS
];
1094 uint32_t va_offset
[MAX_VERTEX_ATTRIBS
];
1095 uint32_t num_vertex_attribs
;
1096 uint32_t binding_stride
[MAX_VBS
];
1100 struct radv_blend_state blend
;
1101 struct radv_depth_stencil_state ds
;
1102 struct radv_raster_state raster
;
1103 struct radv_multisample_state ms
;
1104 struct radv_tessellation_state tess
;
1105 uint32_t db_shader_control
;
1106 uint32_t shader_z_format
;
1109 uint32_t vgt_gs_mode
;
1110 bool vgt_primitiveid_en
;
1111 bool prim_restart_enable
;
1112 unsigned esgs_ring_size
;
1113 unsigned gsvs_ring_size
;
1114 uint32_t ps_input_cntl
[32];
1115 uint32_t ps_input_cntl_num
;
1116 uint32_t pa_cl_vs_out_cntl
;
1117 uint32_t vgt_shader_stages_en
;
1118 uint32_t vtx_base_sgpr
;
1119 uint8_t vtx_emit_num
;
1120 struct radv_prim_vertex_count prim_vertex_count
;
1121 bool can_use_guardband
;
1126 unsigned scratch_bytes_per_wave
;
1129 static inline bool radv_pipeline_has_gs(struct radv_pipeline
*pipeline
)
1131 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1134 static inline bool radv_pipeline_has_tess(struct radv_pipeline
*pipeline
)
1136 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ? true : false;
1139 uint32_t radv_shader_stage_to_user_data_0(gl_shader_stage stage
, bool has_gs
, bool has_tess
);
1140 struct ac_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1141 gl_shader_stage stage
,
1144 struct radv_graphics_pipeline_create_info
{
1146 bool db_depth_clear
;
1147 bool db_stencil_clear
;
1148 bool db_depth_disable_expclear
;
1149 bool db_stencil_disable_expclear
;
1150 bool db_flush_depth_inplace
;
1151 bool db_flush_stencil_inplace
;
1152 bool db_resummarize
;
1153 uint32_t custom_blend_mode
;
1157 radv_pipeline_init(struct radv_pipeline
*pipeline
, struct radv_device
*device
,
1158 struct radv_pipeline_cache
*cache
,
1159 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1160 const struct radv_graphics_pipeline_create_info
*extra
,
1161 const VkAllocationCallbacks
*alloc
);
1164 radv_graphics_pipeline_create(VkDevice device
,
1165 VkPipelineCache cache
,
1166 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1167 const struct radv_graphics_pipeline_create_info
*extra
,
1168 const VkAllocationCallbacks
*alloc
,
1169 VkPipeline
*pPipeline
);
1171 struct vk_format_description
;
1172 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1173 int first_non_void
);
1174 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1175 int first_non_void
);
1176 uint32_t radv_translate_colorformat(VkFormat format
);
1177 uint32_t radv_translate_color_numformat(VkFormat format
,
1178 const struct vk_format_description
*desc
,
1179 int first_non_void
);
1180 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1181 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1182 uint32_t radv_translate_dbformat(VkFormat format
);
1183 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1184 const struct vk_format_description
*desc
,
1185 int first_non_void
);
1186 uint32_t radv_translate_tex_numformat(VkFormat format
,
1187 const struct vk_format_description
*desc
,
1188 int first_non_void
);
1189 bool radv_format_pack_clear_color(VkFormat format
,
1190 uint32_t clear_vals
[2],
1191 VkClearColorValue
*value
);
1192 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1194 struct radv_fmask_info
{
1198 unsigned pitch_in_pixels
;
1199 unsigned bank_height
;
1200 unsigned slice_tile_max
;
1201 unsigned tile_mode_index
;
1202 unsigned tile_swizzle
;
1205 struct radv_cmask_info
{
1209 unsigned slice_tile_max
;
1210 unsigned base_address_reg
;
1213 struct r600_htile_info
{
1224 /* The original VkFormat provided by the client. This may not match any
1225 * of the actual surface formats.
1228 VkImageAspectFlags aspects
;
1229 struct ac_surf_info info
;
1230 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1231 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1232 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1238 unsigned queue_family_mask
;
1242 /* Set when bound */
1243 struct radeon_winsys_bo
*bo
;
1244 VkDeviceSize offset
;
1245 uint32_t dcc_offset
;
1246 uint32_t htile_offset
;
1247 struct radeon_surf surface
;
1249 struct radv_fmask_info fmask
;
1250 struct radv_cmask_info cmask
;
1251 uint32_t clear_value_offset
;
1252 uint32_t dcc_pred_offset
;
1255 /* Whether the image has a htile that is known consistent with the contents of
1257 bool radv_layout_has_htile(const struct radv_image
*image
,
1258 VkImageLayout layout
,
1259 unsigned queue_mask
);
1261 /* Whether the image has a htile that is known consistent with the contents of
1262 * the image and is allowed to be in compressed form.
1264 * If this is false reads that don't use the htile should be able to return
1267 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1268 VkImageLayout layout
,
1269 unsigned queue_mask
);
1271 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1272 VkImageLayout layout
,
1273 unsigned queue_mask
);
1276 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1278 static inline uint32_t
1279 radv_get_layerCount(const struct radv_image
*image
,
1280 const VkImageSubresourceRange
*range
)
1282 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1283 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1286 static inline uint32_t
1287 radv_get_levelCount(const struct radv_image
*image
,
1288 const VkImageSubresourceRange
*range
)
1290 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1291 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1294 struct radeon_bo_metadata
;
1296 radv_init_metadata(struct radv_device
*device
,
1297 struct radv_image
*image
,
1298 struct radeon_bo_metadata
*metadata
);
1300 struct radv_image_view
{
1301 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1302 struct radeon_winsys_bo
*bo
;
1304 VkImageViewType type
;
1305 VkImageAspectFlags aspect_mask
;
1307 uint32_t base_layer
;
1308 uint32_t layer_count
;
1310 uint32_t level_count
;
1311 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1313 uint32_t descriptor
[8];
1314 uint32_t fmask_descriptor
[8];
1316 /* Descriptor for use as a storage image as opposed to a sampled image.
1317 * This has a few differences for cube maps (e.g. type).
1319 uint32_t storage_descriptor
[8];
1320 uint32_t storage_fmask_descriptor
[8];
1323 struct radv_image_create_info
{
1324 const VkImageCreateInfo
*vk_info
;
1328 VkResult
radv_image_create(VkDevice _device
,
1329 const struct radv_image_create_info
*info
,
1330 const VkAllocationCallbacks
* alloc
,
1333 void radv_image_view_init(struct radv_image_view
*view
,
1334 struct radv_device
*device
,
1335 const VkImageViewCreateInfo
* pCreateInfo
);
1337 struct radv_buffer_view
{
1338 struct radeon_winsys_bo
*bo
;
1340 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1343 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1344 struct radv_device
*device
,
1345 const VkBufferViewCreateInfo
* pCreateInfo
,
1346 struct radv_cmd_buffer
*cmd_buffer
);
1348 static inline struct VkExtent3D
1349 radv_sanitize_image_extent(const VkImageType imageType
,
1350 const struct VkExtent3D imageExtent
)
1352 switch (imageType
) {
1353 case VK_IMAGE_TYPE_1D
:
1354 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1355 case VK_IMAGE_TYPE_2D
:
1356 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1357 case VK_IMAGE_TYPE_3D
:
1360 unreachable("invalid image type");
1364 static inline struct VkOffset3D
1365 radv_sanitize_image_offset(const VkImageType imageType
,
1366 const struct VkOffset3D imageOffset
)
1368 switch (imageType
) {
1369 case VK_IMAGE_TYPE_1D
:
1370 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1371 case VK_IMAGE_TYPE_2D
:
1372 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1373 case VK_IMAGE_TYPE_3D
:
1376 unreachable("invalid image type");
1381 radv_image_extent_compare(const struct radv_image
*image
,
1382 const VkExtent3D
*extent
)
1384 if (extent
->width
!= image
->info
.width
||
1385 extent
->height
!= image
->info
.height
||
1386 extent
->depth
!= image
->info
.depth
)
1391 struct radv_sampler
{
1395 struct radv_color_buffer_info
{
1396 uint64_t cb_color_base
;
1397 uint64_t cb_color_cmask
;
1398 uint64_t cb_color_fmask
;
1399 uint64_t cb_dcc_base
;
1400 uint32_t cb_color_pitch
;
1401 uint32_t cb_color_slice
;
1402 uint32_t cb_color_view
;
1403 uint32_t cb_color_info
;
1404 uint32_t cb_color_attrib
;
1405 uint32_t cb_color_attrib2
;
1406 uint32_t cb_dcc_control
;
1407 uint32_t cb_color_cmask_slice
;
1408 uint32_t cb_color_fmask_slice
;
1409 uint32_t cb_clear_value0
;
1410 uint32_t cb_clear_value1
;
1411 uint32_t micro_tile_mode
;
1412 uint32_t gfx9_epitch
;
1415 struct radv_ds_buffer_info
{
1416 uint64_t db_z_read_base
;
1417 uint64_t db_stencil_read_base
;
1418 uint64_t db_z_write_base
;
1419 uint64_t db_stencil_write_base
;
1420 uint64_t db_htile_data_base
;
1421 uint32_t db_depth_info
;
1423 uint32_t db_stencil_info
;
1424 uint32_t db_depth_view
;
1425 uint32_t db_depth_size
;
1426 uint32_t db_depth_slice
;
1427 uint32_t db_htile_surface
;
1428 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1429 uint32_t db_z_info2
;
1430 uint32_t db_stencil_info2
;
1434 struct radv_attachment_info
{
1436 struct radv_color_buffer_info cb
;
1437 struct radv_ds_buffer_info ds
;
1439 struct radv_image_view
*attachment
;
1442 struct radv_framebuffer
{
1447 uint32_t attachment_count
;
1448 struct radv_attachment_info attachments
[0];
1451 struct radv_subpass_barrier
{
1452 VkPipelineStageFlags src_stage_mask
;
1453 VkAccessFlags src_access_mask
;
1454 VkAccessFlags dst_access_mask
;
1457 struct radv_subpass
{
1458 uint32_t input_count
;
1459 uint32_t color_count
;
1460 VkAttachmentReference
* input_attachments
;
1461 VkAttachmentReference
* color_attachments
;
1462 VkAttachmentReference
* resolve_attachments
;
1463 VkAttachmentReference depth_stencil_attachment
;
1465 /** Subpass has at least one resolve attachment */
1468 struct radv_subpass_barrier start_barrier
;
1473 struct radv_render_pass_attachment
{
1476 VkAttachmentLoadOp load_op
;
1477 VkAttachmentLoadOp stencil_load_op
;
1478 VkImageLayout initial_layout
;
1479 VkImageLayout final_layout
;
1483 struct radv_render_pass
{
1484 uint32_t attachment_count
;
1485 uint32_t subpass_count
;
1486 VkAttachmentReference
* subpass_attachments
;
1487 struct radv_render_pass_attachment
* attachments
;
1488 struct radv_subpass_barrier end_barrier
;
1489 struct radv_subpass subpasses
[0];
1492 VkResult
radv_device_init_meta(struct radv_device
*device
);
1493 void radv_device_finish_meta(struct radv_device
*device
);
1495 struct radv_query_pool
{
1496 struct radeon_winsys_bo
*bo
;
1498 uint32_t availability_offset
;
1501 uint32_t pipeline_stats_mask
;
1504 struct radv_semaphore
{
1505 /* use a winsys sem for non-exportable */
1506 struct radeon_winsys_sem
*sem
;
1508 uint32_t temp_syncobj
;
1511 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1513 const VkSemaphore
*wait_sems
,
1514 int num_signal_sems
,
1515 const VkSemaphore
*signal_sems
);
1516 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1519 radv_update_descriptor_sets(struct radv_device
*device
,
1520 struct radv_cmd_buffer
*cmd_buffer
,
1521 VkDescriptorSet overrideSet
,
1522 uint32_t descriptorWriteCount
,
1523 const VkWriteDescriptorSet
*pDescriptorWrites
,
1524 uint32_t descriptorCopyCount
,
1525 const VkCopyDescriptorSet
*pDescriptorCopies
);
1528 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1529 struct radv_cmd_buffer
*cmd_buffer
,
1530 struct radv_descriptor_set
*set
,
1531 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1534 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1535 VkPipelineBindPoint pipelineBindPoint
,
1536 VkPipelineLayout _layout
,
1538 uint32_t descriptorWriteCount
,
1539 const VkWriteDescriptorSet
*pDescriptorWrites
);
1541 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1542 struct radv_image
*image
, uint32_t value
);
1543 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1544 struct radv_image
*image
, uint32_t value
);
1547 struct radeon_winsys_fence
*fence
;
1552 struct radeon_winsys_sem
;
1554 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1556 static inline struct __radv_type * \
1557 __radv_type ## _from_handle(__VkType _handle) \
1559 return (struct __radv_type *) _handle; \
1562 static inline __VkType \
1563 __radv_type ## _to_handle(struct __radv_type *_obj) \
1565 return (__VkType) _obj; \
1568 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1570 static inline struct __radv_type * \
1571 __radv_type ## _from_handle(__VkType _handle) \
1573 return (struct __radv_type *)(uintptr_t) _handle; \
1576 static inline __VkType \
1577 __radv_type ## _to_handle(struct __radv_type *_obj) \
1579 return (__VkType)(uintptr_t) _obj; \
1582 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1583 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1585 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1586 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1587 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1588 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1589 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1591 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1592 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1593 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1594 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1595 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1596 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1597 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1598 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1599 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1600 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1601 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1602 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1603 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1604 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1605 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1606 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1607 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1608 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1609 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1610 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1611 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1613 #endif /* RADV_PRIVATE_H */