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radv: pass sample locations for transitions before depth/stencil resolves
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
65 #include "radv_cs.h"
66
67 #include <llvm-c/TargetMachine.h>
68
69 /* Pre-declarations needed for WSI entrypoints */
70 struct wl_surface;
71 struct wl_display;
72 typedef struct xcb_connection_t xcb_connection_t;
73 typedef uint32_t xcb_visualid_t;
74 typedef uint32_t xcb_window_t;
75
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 #define ATI_VENDOR_ID 0x1002
87
88 #define MAX_VBS 32
89 #define MAX_VERTEX_ATTRIBS 32
90 #define MAX_RTS 8
91 #define MAX_VIEWPORTS 16
92 #define MAX_SCISSORS 16
93 #define MAX_DISCARD_RECTANGLES 4
94 #define MAX_SAMPLE_LOCATIONS 32
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_PUSH_DESCRIPTORS 32
97 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
98 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
99 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
100 #define MAX_SAMPLES_LOG2 4
101 #define NUM_META_FS_KEYS 12
102 #define RADV_MAX_DRM_DEVICES 8
103 #define MAX_VIEWS 8
104 #define MAX_SO_STREAMS 4
105 #define MAX_SO_BUFFERS 4
106 #define MAX_SO_OUTPUTS 64
107 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
108 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
109
110 #define NUM_DEPTH_CLEAR_PIPELINES 3
111
112 /*
113 * This is the point we switch from using CP to compute shader
114 * for certain buffer operations.
115 */
116 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
117
118 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
119
120 enum radv_mem_heap {
121 RADV_MEM_HEAP_VRAM,
122 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
123 RADV_MEM_HEAP_GTT,
124 RADV_MEM_HEAP_COUNT
125 };
126
127 enum radv_mem_type {
128 RADV_MEM_TYPE_VRAM,
129 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
130 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
131 RADV_MEM_TYPE_GTT_CACHED,
132 RADV_MEM_TYPE_COUNT
133 };
134
135 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
136
137 static inline uint32_t
138 align_u32(uint32_t v, uint32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 static inline uint32_t
145 align_u32_npot(uint32_t v, uint32_t a)
146 {
147 return (v + a - 1) / a * a;
148 }
149
150 static inline uint64_t
151 align_u64(uint64_t v, uint64_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 static inline int32_t
158 align_i32(int32_t v, int32_t a)
159 {
160 assert(a != 0 && a == (a & -a));
161 return (v + a - 1) & ~(a - 1);
162 }
163
164 /** Alignment must be a power of 2. */
165 static inline bool
166 radv_is_aligned(uintmax_t n, uintmax_t a)
167 {
168 assert(a == (a & -a));
169 return (n & (a - 1)) == 0;
170 }
171
172 static inline uint32_t
173 round_up_u32(uint32_t v, uint32_t a)
174 {
175 return (v + a - 1) / a;
176 }
177
178 static inline uint64_t
179 round_up_u64(uint64_t v, uint64_t a)
180 {
181 return (v + a - 1) / a;
182 }
183
184 static inline uint32_t
185 radv_minify(uint32_t n, uint32_t levels)
186 {
187 if (unlikely(n == 0))
188 return 0;
189 else
190 return MAX2(n >> levels, 1);
191 }
192 static inline float
193 radv_clamp_f(float f, float min, float max)
194 {
195 assert(min < max);
196
197 if (f > max)
198 return max;
199 else if (f < min)
200 return min;
201 else
202 return f;
203 }
204
205 static inline bool
206 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
207 {
208 if (*inout_mask & clear_mask) {
209 *inout_mask &= ~clear_mask;
210 return true;
211 } else {
212 return false;
213 }
214 }
215
216 #define for_each_bit(b, dword) \
217 for (uint32_t __dword = (dword); \
218 (b) = __builtin_ffs(__dword) - 1, __dword; \
219 __dword &= ~(1 << (b)))
220
221 #define typed_memcpy(dest, src, count) ({ \
222 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
223 memcpy((dest), (src), (count) * sizeof(*(src))); \
224 })
225
226 /* Whenever we generate an error, pass it through this function. Useful for
227 * debugging, where we can break on it. Only call at error site, not when
228 * propagating errors. Might be useful to plug in a stack trace here.
229 */
230
231 struct radv_instance;
232
233 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
234
235 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
236 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
237
238 void __radv_finishme(const char *file, int line, const char *format, ...)
239 radv_printflike(3, 4);
240 void radv_loge(const char *format, ...) radv_printflike(1, 2);
241 void radv_loge_v(const char *format, va_list va);
242 void radv_logi(const char *format, ...) radv_printflike(1, 2);
243 void radv_logi_v(const char *format, va_list va);
244
245 /**
246 * Print a FINISHME message, including its source location.
247 */
248 #define radv_finishme(format, ...) \
249 do { \
250 static bool reported = false; \
251 if (!reported) { \
252 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
253 reported = true; \
254 } \
255 } while (0)
256
257 /* A non-fatal assert. Useful for debugging. */
258 #ifdef DEBUG
259 #define radv_assert(x) ({ \
260 if (unlikely(!(x))) \
261 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
262 })
263 #else
264 #define radv_assert(x)
265 #endif
266
267 #define stub_return(v) \
268 do { \
269 radv_finishme("stub %s", __func__); \
270 return (v); \
271 } while (0)
272
273 #define stub() \
274 do { \
275 radv_finishme("stub %s", __func__); \
276 return; \
277 } while (0)
278
279 void *radv_lookup_entrypoint_unchecked(const char *name);
280 void *radv_lookup_entrypoint_checked(const char *name,
281 uint32_t core_version,
282 const struct radv_instance_extension_table *instance,
283 const struct radv_device_extension_table *device);
284 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
285 uint32_t core_version,
286 const struct radv_instance_extension_table *instance);
287
288 struct radv_physical_device {
289 VK_LOADER_DATA _loader_data;
290
291 struct radv_instance * instance;
292
293 struct radeon_winsys *ws;
294 struct radeon_info rad_info;
295 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
296 uint8_t driver_uuid[VK_UUID_SIZE];
297 uint8_t device_uuid[VK_UUID_SIZE];
298 uint8_t cache_uuid[VK_UUID_SIZE];
299
300 int local_fd;
301 int master_fd;
302 struct wsi_device wsi_device;
303
304 bool has_rbplus; /* if RB+ register exist */
305 bool rbplus_allowed; /* if RB+ is allowed */
306 bool has_clear_state;
307 bool cpdma_prefetch_writes_memory;
308 bool has_scissor_bug;
309
310 bool has_out_of_order_rast;
311 bool out_of_order_rast_allowed;
312
313 /* Whether DCC should be enabled for MSAA textures. */
314 bool dcc_msaa_allowed;
315
316 /* Whether LOAD_CONTEXT_REG packets are supported. */
317 bool has_load_ctx_reg_pkt;
318
319 /* Whether to enable the AMD_shader_ballot extension */
320 bool use_shader_ballot;
321
322 /* This is the drivers on-disk cache used as a fallback as opposed to
323 * the pipeline cache defined by apps.
324 */
325 struct disk_cache * disk_cache;
326
327 VkPhysicalDeviceMemoryProperties memory_properties;
328 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
329
330 drmPciBusInfo bus_info;
331
332 struct radv_device_extension_table supported_extensions;
333 };
334
335 struct radv_instance {
336 VK_LOADER_DATA _loader_data;
337
338 VkAllocationCallbacks alloc;
339
340 uint32_t apiVersion;
341 int physicalDeviceCount;
342 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
343
344 uint64_t debug_flags;
345 uint64_t perftest_flags;
346
347 struct vk_debug_report_instance debug_report_callbacks;
348
349 struct radv_instance_extension_table enabled_extensions;
350
351 struct driOptionCache dri_options;
352 struct driOptionCache available_dri_options;
353 };
354
355 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
356 void radv_finish_wsi(struct radv_physical_device *physical_device);
357
358 bool radv_instance_extension_supported(const char *name);
359 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
360 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
361 const char *name);
362
363 struct cache_entry;
364
365 struct radv_pipeline_cache {
366 struct radv_device * device;
367 pthread_mutex_t mutex;
368
369 uint32_t total_size;
370 uint32_t table_size;
371 uint32_t kernel_count;
372 struct cache_entry ** hash_table;
373 bool modified;
374
375 VkAllocationCallbacks alloc;
376 };
377
378 struct radv_pipeline_key {
379 uint32_t instance_rate_inputs;
380 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
381 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
382 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
383 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
384 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
385 uint64_t vertex_alpha_adjust;
386 uint32_t vertex_post_shuffle;
387 unsigned tess_input_vertices;
388 uint32_t col_format;
389 uint32_t is_int8;
390 uint32_t is_int10;
391 uint8_t log2_ps_iter_samples;
392 uint8_t num_samples;
393 uint32_t has_multiview_view_index : 1;
394 uint32_t optimisations_disabled : 1;
395 };
396
397 void
398 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
399 struct radv_device *device);
400 void
401 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
402 bool
403 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
404 const void *data, size_t size);
405
406 struct radv_shader_variant;
407
408 bool
409 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
410 struct radv_pipeline_cache *cache,
411 const unsigned char *sha1,
412 struct radv_shader_variant **variants,
413 bool *found_in_application_cache);
414
415 void
416 radv_pipeline_cache_insert_shaders(struct radv_device *device,
417 struct radv_pipeline_cache *cache,
418 const unsigned char *sha1,
419 struct radv_shader_variant **variants,
420 const void *const *codes,
421 const unsigned *code_sizes);
422
423 enum radv_blit_ds_layout {
424 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
425 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
426 RADV_BLIT_DS_LAYOUT_COUNT,
427 };
428
429 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
430 {
431 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
432 }
433
434 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
435 {
436 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
437 }
438
439 enum radv_meta_dst_layout {
440 RADV_META_DST_LAYOUT_GENERAL,
441 RADV_META_DST_LAYOUT_OPTIMAL,
442 RADV_META_DST_LAYOUT_COUNT,
443 };
444
445 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
446 {
447 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
448 }
449
450 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
451 {
452 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
453 }
454
455 struct radv_meta_state {
456 VkAllocationCallbacks alloc;
457
458 struct radv_pipeline_cache cache;
459
460 /*
461 * For on-demand pipeline creation, makes sure that
462 * only one thread tries to build a pipeline at the same time.
463 */
464 mtx_t mtx;
465
466 /**
467 * Use array element `i` for images with `2^i` samples.
468 */
469 struct {
470 VkRenderPass render_pass[NUM_META_FS_KEYS];
471 VkPipeline color_pipelines[NUM_META_FS_KEYS];
472
473 VkRenderPass depthstencil_rp;
474 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
475 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
476 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
477 } clear[1 + MAX_SAMPLES_LOG2];
478
479 VkPipelineLayout clear_color_p_layout;
480 VkPipelineLayout clear_depth_p_layout;
481
482 /* Optimized compute fast HTILE clear for stencil or depth only. */
483 VkPipeline clear_htile_mask_pipeline;
484 VkPipelineLayout clear_htile_mask_p_layout;
485 VkDescriptorSetLayout clear_htile_mask_ds_layout;
486
487 struct {
488 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
489
490 /** Pipeline that blits from a 1D image. */
491 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
492
493 /** Pipeline that blits from a 2D image. */
494 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
495
496 /** Pipeline that blits from a 3D image. */
497 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
498
499 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
500 VkPipeline depth_only_1d_pipeline;
501 VkPipeline depth_only_2d_pipeline;
502 VkPipeline depth_only_3d_pipeline;
503
504 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
505 VkPipeline stencil_only_1d_pipeline;
506 VkPipeline stencil_only_2d_pipeline;
507 VkPipeline stencil_only_3d_pipeline;
508 VkPipelineLayout pipeline_layout;
509 VkDescriptorSetLayout ds_layout;
510 } blit;
511
512 struct {
513 VkPipelineLayout p_layouts[5];
514 VkDescriptorSetLayout ds_layouts[5];
515 VkPipeline pipelines[5][NUM_META_FS_KEYS];
516
517 VkPipeline depth_only_pipeline[5];
518
519 VkPipeline stencil_only_pipeline[5];
520 } blit2d[1 + MAX_SAMPLES_LOG2];
521
522 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
523 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
524 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
525
526 struct {
527 VkPipelineLayout img_p_layout;
528 VkDescriptorSetLayout img_ds_layout;
529 VkPipeline pipeline;
530 VkPipeline pipeline_3d;
531 } itob;
532 struct {
533 VkPipelineLayout img_p_layout;
534 VkDescriptorSetLayout img_ds_layout;
535 VkPipeline pipeline;
536 VkPipeline pipeline_3d;
537 } btoi;
538 struct {
539 VkPipelineLayout img_p_layout;
540 VkDescriptorSetLayout img_ds_layout;
541 VkPipeline pipeline;
542 } btoi_r32g32b32;
543 struct {
544 VkPipelineLayout img_p_layout;
545 VkDescriptorSetLayout img_ds_layout;
546 VkPipeline pipeline;
547 VkPipeline pipeline_3d;
548 } itoi;
549 struct {
550 VkPipelineLayout img_p_layout;
551 VkDescriptorSetLayout img_ds_layout;
552 VkPipeline pipeline;
553 } itoi_r32g32b32;
554 struct {
555 VkPipelineLayout img_p_layout;
556 VkDescriptorSetLayout img_ds_layout;
557 VkPipeline pipeline;
558 VkPipeline pipeline_3d;
559 } cleari;
560 struct {
561 VkPipelineLayout img_p_layout;
562 VkDescriptorSetLayout img_ds_layout;
563 VkPipeline pipeline;
564 } cleari_r32g32b32;
565
566 struct {
567 VkPipelineLayout p_layout;
568 VkPipeline pipeline[NUM_META_FS_KEYS];
569 VkRenderPass pass[NUM_META_FS_KEYS];
570 } resolve;
571
572 struct {
573 VkDescriptorSetLayout ds_layout;
574 VkPipelineLayout p_layout;
575 struct {
576 VkPipeline pipeline;
577 VkPipeline i_pipeline;
578 VkPipeline srgb_pipeline;
579 } rc[MAX_SAMPLES_LOG2];
580
581 VkPipeline depth_zero_pipeline;
582 struct {
583 VkPipeline average_pipeline;
584 VkPipeline max_pipeline;
585 VkPipeline min_pipeline;
586 } depth[MAX_SAMPLES_LOG2];
587
588 VkPipeline stencil_zero_pipeline;
589 struct {
590 VkPipeline max_pipeline;
591 VkPipeline min_pipeline;
592 } stencil[MAX_SAMPLES_LOG2];
593 } resolve_compute;
594
595 struct {
596 VkDescriptorSetLayout ds_layout;
597 VkPipelineLayout p_layout;
598
599 struct {
600 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
601 VkPipeline pipeline[NUM_META_FS_KEYS];
602 } rc[MAX_SAMPLES_LOG2];
603
604 VkRenderPass depth_render_pass;
605 VkPipeline depth_zero_pipeline;
606 struct {
607 VkPipeline average_pipeline;
608 VkPipeline max_pipeline;
609 VkPipeline min_pipeline;
610 } depth[MAX_SAMPLES_LOG2];
611
612 VkRenderPass stencil_render_pass;
613 VkPipeline stencil_zero_pipeline;
614 struct {
615 VkPipeline max_pipeline;
616 VkPipeline min_pipeline;
617 } stencil[MAX_SAMPLES_LOG2];
618 } resolve_fragment;
619
620 struct {
621 VkPipelineLayout p_layout;
622 VkPipeline decompress_pipeline;
623 VkPipeline resummarize_pipeline;
624 VkRenderPass pass;
625 } depth_decomp[1 + MAX_SAMPLES_LOG2];
626
627 struct {
628 VkPipelineLayout p_layout;
629 VkPipeline cmask_eliminate_pipeline;
630 VkPipeline fmask_decompress_pipeline;
631 VkPipeline dcc_decompress_pipeline;
632 VkRenderPass pass;
633
634 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
635 VkPipelineLayout dcc_decompress_compute_p_layout;
636 VkPipeline dcc_decompress_compute_pipeline;
637 } fast_clear_flush;
638
639 struct {
640 VkPipelineLayout fill_p_layout;
641 VkPipelineLayout copy_p_layout;
642 VkDescriptorSetLayout fill_ds_layout;
643 VkDescriptorSetLayout copy_ds_layout;
644 VkPipeline fill_pipeline;
645 VkPipeline copy_pipeline;
646 } buffer;
647
648 struct {
649 VkDescriptorSetLayout ds_layout;
650 VkPipelineLayout p_layout;
651 VkPipeline occlusion_query_pipeline;
652 VkPipeline pipeline_statistics_query_pipeline;
653 VkPipeline tfb_query_pipeline;
654 } query;
655
656 struct {
657 VkDescriptorSetLayout ds_layout;
658 VkPipelineLayout p_layout;
659 VkPipeline pipeline[MAX_SAMPLES_LOG2];
660 } fmask_expand;
661 };
662
663 /* queue types */
664 #define RADV_QUEUE_GENERAL 0
665 #define RADV_QUEUE_COMPUTE 1
666 #define RADV_QUEUE_TRANSFER 2
667
668 #define RADV_MAX_QUEUE_FAMILIES 3
669
670 enum ring_type radv_queue_family_to_ring(int f);
671
672 struct radv_queue {
673 VK_LOADER_DATA _loader_data;
674 struct radv_device * device;
675 struct radeon_winsys_ctx *hw_ctx;
676 enum radeon_ctx_priority priority;
677 uint32_t queue_family_index;
678 int queue_idx;
679 VkDeviceQueueCreateFlags flags;
680
681 uint32_t scratch_size;
682 uint32_t compute_scratch_size;
683 uint32_t esgs_ring_size;
684 uint32_t gsvs_ring_size;
685 bool has_tess_rings;
686 bool has_sample_positions;
687
688 struct radeon_winsys_bo *scratch_bo;
689 struct radeon_winsys_bo *descriptor_bo;
690 struct radeon_winsys_bo *compute_scratch_bo;
691 struct radeon_winsys_bo *esgs_ring_bo;
692 struct radeon_winsys_bo *gsvs_ring_bo;
693 struct radeon_winsys_bo *tess_rings_bo;
694 struct radeon_cmdbuf *initial_preamble_cs;
695 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
696 struct radeon_cmdbuf *continue_preamble_cs;
697 };
698
699 struct radv_bo_list {
700 struct radv_winsys_bo_list list;
701 unsigned capacity;
702 pthread_mutex_t mutex;
703 };
704
705 struct radv_device {
706 VK_LOADER_DATA _loader_data;
707
708 VkAllocationCallbacks alloc;
709
710 struct radv_instance * instance;
711 struct radeon_winsys *ws;
712
713 struct radv_meta_state meta_state;
714
715 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
716 int queue_count[RADV_MAX_QUEUE_FAMILIES];
717 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
718
719 bool always_use_syncobj;
720 bool has_distributed_tess;
721 bool pbb_allowed;
722 bool dfsm_allowed;
723 uint32_t tess_offchip_block_dw_size;
724 uint32_t scratch_waves;
725 uint32_t dispatch_initiator;
726
727 uint32_t gs_table_depth;
728
729 /* MSAA sample locations.
730 * The first index is the sample index.
731 * The second index is the coordinate: X, Y. */
732 float sample_locations_1x[1][2];
733 float sample_locations_2x[2][2];
734 float sample_locations_4x[4][2];
735 float sample_locations_8x[8][2];
736
737 /* GFX7 and later */
738 uint32_t gfx_init_size_dw;
739 struct radeon_winsys_bo *gfx_init;
740
741 struct radeon_winsys_bo *trace_bo;
742 uint32_t *trace_id_ptr;
743
744 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
745 bool keep_shader_info;
746
747 struct radv_physical_device *physical_device;
748
749 /* Backup in-memory cache to be used if the app doesn't provide one */
750 struct radv_pipeline_cache * mem_cache;
751
752 /*
753 * use different counters so MSAA MRTs get consecutive surface indices,
754 * even if MASK is allocated in between.
755 */
756 uint32_t image_mrt_offset_counter;
757 uint32_t fmask_mrt_offset_counter;
758 struct list_head shader_slabs;
759 mtx_t shader_slab_mutex;
760
761 /* For detecting VM faults reported by dmesg. */
762 uint64_t dmesg_timestamp;
763
764 struct radv_device_extension_table enabled_extensions;
765
766 /* Whether the driver uses a global BO list. */
767 bool use_global_bo_list;
768
769 struct radv_bo_list bo_list;
770
771 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
772 int force_aniso;
773 };
774
775 struct radv_device_memory {
776 struct radeon_winsys_bo *bo;
777 /* for dedicated allocations */
778 struct radv_image *image;
779 struct radv_buffer *buffer;
780 uint32_t type_index;
781 VkDeviceSize map_size;
782 void * map;
783 void * user_ptr;
784 };
785
786
787 struct radv_descriptor_range {
788 uint64_t va;
789 uint32_t size;
790 };
791
792 struct radv_descriptor_set {
793 const struct radv_descriptor_set_layout *layout;
794 uint32_t size;
795
796 struct radeon_winsys_bo *bo;
797 uint64_t va;
798 uint32_t *mapped_ptr;
799 struct radv_descriptor_range *dynamic_descriptors;
800
801 struct radeon_winsys_bo *descriptors[0];
802 };
803
804 struct radv_push_descriptor_set
805 {
806 struct radv_descriptor_set set;
807 uint32_t capacity;
808 };
809
810 struct radv_descriptor_pool_entry {
811 uint32_t offset;
812 uint32_t size;
813 struct radv_descriptor_set *set;
814 };
815
816 struct radv_descriptor_pool {
817 struct radeon_winsys_bo *bo;
818 uint8_t *mapped_ptr;
819 uint64_t current_offset;
820 uint64_t size;
821
822 uint8_t *host_memory_base;
823 uint8_t *host_memory_ptr;
824 uint8_t *host_memory_end;
825
826 uint32_t entry_count;
827 uint32_t max_entry_count;
828 struct radv_descriptor_pool_entry entries[0];
829 };
830
831 struct radv_descriptor_update_template_entry {
832 VkDescriptorType descriptor_type;
833
834 /* The number of descriptors to update */
835 uint32_t descriptor_count;
836
837 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
838 uint32_t dst_offset;
839
840 /* In dwords. Not valid/used for dynamic descriptors */
841 uint32_t dst_stride;
842
843 uint32_t buffer_offset;
844
845 /* Only valid for combined image samplers and samplers */
846 uint8_t has_sampler;
847 uint8_t sampler_offset;
848
849 /* In bytes */
850 size_t src_offset;
851 size_t src_stride;
852
853 /* For push descriptors */
854 const uint32_t *immutable_samplers;
855 };
856
857 struct radv_descriptor_update_template {
858 uint32_t entry_count;
859 VkPipelineBindPoint bind_point;
860 struct radv_descriptor_update_template_entry entry[0];
861 };
862
863 struct radv_buffer {
864 VkDeviceSize size;
865
866 VkBufferUsageFlags usage;
867 VkBufferCreateFlags flags;
868
869 /* Set when bound */
870 struct radeon_winsys_bo * bo;
871 VkDeviceSize offset;
872
873 bool shareable;
874 };
875
876 enum radv_dynamic_state_bits {
877 RADV_DYNAMIC_VIEWPORT = 1 << 0,
878 RADV_DYNAMIC_SCISSOR = 1 << 1,
879 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
880 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
881 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
882 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
883 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
884 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
885 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
886 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
887 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
888 RADV_DYNAMIC_ALL = (1 << 11) - 1,
889 };
890
891 enum radv_cmd_dirty_bits {
892 /* Keep the dynamic state dirty bits in sync with
893 * enum radv_dynamic_state_bits */
894 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
895 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
896 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
897 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
898 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
899 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
900 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
901 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
902 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
903 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
904 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
905 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
906 RADV_CMD_DIRTY_PIPELINE = 1 << 11,
907 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
908 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
909 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
910 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
911 };
912
913 enum radv_cmd_flush_bits {
914 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
915 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
916 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
917 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
918 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
919 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
920 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
921 /* Same as above, but only writes back and doesn't invalidate */
922 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
923 /* Framebuffer caches */
924 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
925 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
926 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
927 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
928 /* Engine synchronization. */
929 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
930 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
931 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
932 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
933 /* Pipeline query controls. */
934 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
935 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
936 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
937
938 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
939 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
940 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
941 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
942 };
943
944 struct radv_vertex_binding {
945 struct radv_buffer * buffer;
946 VkDeviceSize offset;
947 };
948
949 struct radv_streamout_binding {
950 struct radv_buffer *buffer;
951 VkDeviceSize offset;
952 VkDeviceSize size;
953 };
954
955 struct radv_streamout_state {
956 /* Mask of bound streamout buffers. */
957 uint8_t enabled_mask;
958
959 /* External state that comes from the last vertex stage, it must be
960 * set explicitely when binding a new graphics pipeline.
961 */
962 uint16_t stride_in_dw[MAX_SO_BUFFERS];
963 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
964
965 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
966 uint32_t hw_enabled_mask;
967
968 /* State of VGT_STRMOUT_(CONFIG|EN) */
969 bool streamout_enabled;
970 };
971
972 struct radv_viewport_state {
973 uint32_t count;
974 VkViewport viewports[MAX_VIEWPORTS];
975 };
976
977 struct radv_scissor_state {
978 uint32_t count;
979 VkRect2D scissors[MAX_SCISSORS];
980 };
981
982 struct radv_discard_rectangle_state {
983 uint32_t count;
984 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
985 };
986
987 struct radv_sample_locations_state {
988 VkSampleCountFlagBits per_pixel;
989 VkExtent2D grid_size;
990 uint32_t count;
991 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
992 };
993
994 struct radv_dynamic_state {
995 /**
996 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
997 * Defines the set of saved dynamic state.
998 */
999 uint32_t mask;
1000
1001 struct radv_viewport_state viewport;
1002
1003 struct radv_scissor_state scissor;
1004
1005 float line_width;
1006
1007 struct {
1008 float bias;
1009 float clamp;
1010 float slope;
1011 } depth_bias;
1012
1013 float blend_constants[4];
1014
1015 struct {
1016 float min;
1017 float max;
1018 } depth_bounds;
1019
1020 struct {
1021 uint32_t front;
1022 uint32_t back;
1023 } stencil_compare_mask;
1024
1025 struct {
1026 uint32_t front;
1027 uint32_t back;
1028 } stencil_write_mask;
1029
1030 struct {
1031 uint32_t front;
1032 uint32_t back;
1033 } stencil_reference;
1034
1035 struct radv_discard_rectangle_state discard_rectangle;
1036
1037 struct radv_sample_locations_state sample_location;
1038 };
1039
1040 extern const struct radv_dynamic_state default_dynamic_state;
1041
1042 const char *
1043 radv_get_debug_option_name(int id);
1044
1045 const char *
1046 radv_get_perftest_option_name(int id);
1047
1048 /**
1049 * Attachment state when recording a renderpass instance.
1050 *
1051 * The clear value is valid only if there exists a pending clear.
1052 */
1053 struct radv_attachment_state {
1054 VkImageAspectFlags pending_clear_aspects;
1055 uint32_t cleared_views;
1056 VkClearValue clear_value;
1057 VkImageLayout current_layout;
1058 struct radv_sample_locations_state sample_location;
1059 };
1060
1061 struct radv_descriptor_state {
1062 struct radv_descriptor_set *sets[MAX_SETS];
1063 uint32_t dirty;
1064 uint32_t valid;
1065 struct radv_push_descriptor_set push_set;
1066 bool push_dirty;
1067 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1068 };
1069
1070 struct radv_subpass_sample_locs_state {
1071 uint32_t subpass_idx;
1072 struct radv_sample_locations_state sample_location;
1073 };
1074
1075 struct radv_cmd_state {
1076 /* Vertex descriptors */
1077 uint64_t vb_va;
1078 unsigned vb_size;
1079
1080 bool predicating;
1081 uint32_t dirty;
1082
1083 uint32_t prefetch_L2_mask;
1084
1085 struct radv_pipeline * pipeline;
1086 struct radv_pipeline * emitted_pipeline;
1087 struct radv_pipeline * compute_pipeline;
1088 struct radv_pipeline * emitted_compute_pipeline;
1089 struct radv_framebuffer * framebuffer;
1090 struct radv_render_pass * pass;
1091 const struct radv_subpass * subpass;
1092 struct radv_dynamic_state dynamic;
1093 struct radv_attachment_state * attachments;
1094 struct radv_streamout_state streamout;
1095 VkRect2D render_area;
1096
1097 uint32_t num_subpass_sample_locs;
1098 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1099
1100 /* Index buffer */
1101 struct radv_buffer *index_buffer;
1102 uint64_t index_offset;
1103 uint32_t index_type;
1104 uint32_t max_index_count;
1105 uint64_t index_va;
1106 int32_t last_index_type;
1107
1108 int32_t last_primitive_reset_en;
1109 uint32_t last_primitive_reset_index;
1110 enum radv_cmd_flush_bits flush_bits;
1111 unsigned active_occlusion_queries;
1112 bool perfect_occlusion_queries_enabled;
1113 unsigned active_pipeline_queries;
1114 float offset_scale;
1115 uint32_t trace_id;
1116 uint32_t last_ia_multi_vgt_param;
1117
1118 uint32_t last_num_instances;
1119 uint32_t last_first_instance;
1120 uint32_t last_vertex_offset;
1121
1122 /* Whether CP DMA is busy/idle. */
1123 bool dma_is_busy;
1124
1125 /* Conditional rendering info. */
1126 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1127 uint64_t predication_va;
1128
1129 bool context_roll_without_scissor_emitted;
1130 };
1131
1132 struct radv_cmd_pool {
1133 VkAllocationCallbacks alloc;
1134 struct list_head cmd_buffers;
1135 struct list_head free_cmd_buffers;
1136 uint32_t queue_family_index;
1137 };
1138
1139 struct radv_cmd_buffer_upload {
1140 uint8_t *map;
1141 unsigned offset;
1142 uint64_t size;
1143 struct radeon_winsys_bo *upload_bo;
1144 struct list_head list;
1145 };
1146
1147 enum radv_cmd_buffer_status {
1148 RADV_CMD_BUFFER_STATUS_INVALID,
1149 RADV_CMD_BUFFER_STATUS_INITIAL,
1150 RADV_CMD_BUFFER_STATUS_RECORDING,
1151 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1152 RADV_CMD_BUFFER_STATUS_PENDING,
1153 };
1154
1155 struct radv_cmd_buffer {
1156 VK_LOADER_DATA _loader_data;
1157
1158 struct radv_device * device;
1159
1160 struct radv_cmd_pool * pool;
1161 struct list_head pool_link;
1162
1163 VkCommandBufferUsageFlags usage_flags;
1164 VkCommandBufferLevel level;
1165 enum radv_cmd_buffer_status status;
1166 struct radeon_cmdbuf *cs;
1167 struct radv_cmd_state state;
1168 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1169 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1170 uint32_t queue_family_index;
1171
1172 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1173 VkShaderStageFlags push_constant_stages;
1174 struct radv_descriptor_set meta_push_descriptors;
1175
1176 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1177
1178 struct radv_cmd_buffer_upload upload;
1179
1180 uint32_t scratch_size_needed;
1181 uint32_t compute_scratch_size_needed;
1182 uint32_t esgs_ring_size_needed;
1183 uint32_t gsvs_ring_size_needed;
1184 bool tess_rings_needed;
1185 bool sample_positions_needed;
1186
1187 VkResult record_result;
1188
1189 uint64_t gfx9_fence_va;
1190 uint32_t gfx9_fence_idx;
1191 uint64_t gfx9_eop_bug_va;
1192
1193 /**
1194 * Whether a query pool has been resetted and we have to flush caches.
1195 */
1196 bool pending_reset_query;
1197
1198 /**
1199 * Bitmask of pending active query flushes.
1200 */
1201 enum radv_cmd_flush_bits active_query_flush_bits;
1202 };
1203
1204 struct radv_image;
1205 struct radv_image_view;
1206
1207 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1208
1209 void si_emit_graphics(struct radv_physical_device *physical_device,
1210 struct radeon_cmdbuf *cs);
1211 void si_emit_compute(struct radv_physical_device *physical_device,
1212 struct radeon_cmdbuf *cs);
1213
1214 void cik_create_gfx_config(struct radv_device *device);
1215
1216 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1217 int count, const VkViewport *viewports);
1218 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1219 int count, const VkRect2D *scissors,
1220 const VkViewport *viewports, bool can_use_guardband);
1221 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1222 bool instanced_draw, bool indirect_draw,
1223 bool count_from_stream_output,
1224 uint32_t draw_vertex_count);
1225 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1226 enum chip_class chip_class,
1227 bool is_mec,
1228 unsigned event, unsigned event_flags,
1229 unsigned data_sel,
1230 uint64_t va,
1231 uint32_t new_fence,
1232 uint64_t gfx9_eop_bug_va);
1233
1234 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1235 uint32_t ref, uint32_t mask);
1236 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1237 enum chip_class chip_class,
1238 uint32_t *fence_ptr, uint64_t va,
1239 bool is_mec,
1240 enum radv_cmd_flush_bits flush_bits,
1241 uint64_t gfx9_eop_bug_va);
1242 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1243 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1244 bool inverted, uint64_t va);
1245 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1246 uint64_t src_va, uint64_t dest_va,
1247 uint64_t size);
1248 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1249 unsigned size);
1250 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1251 uint64_t size, unsigned value);
1252 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1253
1254 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1255 bool
1256 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1257 unsigned size,
1258 unsigned alignment,
1259 unsigned *out_offset,
1260 void **ptr);
1261 void
1262 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1263 const struct radv_subpass *subpass);
1264 bool
1265 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1266 unsigned size, unsigned alignmnet,
1267 const void *data, unsigned *out_offset);
1268
1269 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1270 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1271 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1272 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1273 VkImageAspectFlags aspects,
1274 VkResolveModeFlagBitsKHR resolve_mode);
1275 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1276 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1277 VkImageAspectFlags aspects,
1278 VkResolveModeFlagBitsKHR resolve_mode);
1279 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1280 unsigned radv_get_default_max_sample_dist(int log_samples);
1281 void radv_device_init_msaa(struct radv_device *device);
1282
1283 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1284 struct radv_image *image,
1285 VkClearDepthStencilValue ds_clear_value,
1286 VkImageAspectFlags aspects);
1287
1288 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1289 const struct radv_image_view *iview,
1290 int cb_idx,
1291 uint32_t color_values[2]);
1292
1293 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1294 struct radv_image *image,
1295 const VkImageSubresourceRange *range, bool value);
1296
1297 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1298 struct radv_image *image,
1299 const VkImageSubresourceRange *range, bool value);
1300
1301 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1302 struct radeon_winsys_bo *bo,
1303 uint64_t offset, uint64_t size, uint32_t value);
1304 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1305 bool radv_get_memory_fd(struct radv_device *device,
1306 struct radv_device_memory *memory,
1307 int *pFD);
1308
1309 static inline void
1310 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1311 unsigned sh_offset, unsigned pointer_count,
1312 bool use_32bit_pointers)
1313 {
1314 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1315 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1316 }
1317
1318 static inline void
1319 radv_emit_shader_pointer_body(struct radv_device *device,
1320 struct radeon_cmdbuf *cs,
1321 uint64_t va, bool use_32bit_pointers)
1322 {
1323 radeon_emit(cs, va);
1324
1325 if (use_32bit_pointers) {
1326 assert(va == 0 ||
1327 (va >> 32) == device->physical_device->rad_info.address32_hi);
1328 } else {
1329 radeon_emit(cs, va >> 32);
1330 }
1331 }
1332
1333 static inline void
1334 radv_emit_shader_pointer(struct radv_device *device,
1335 struct radeon_cmdbuf *cs,
1336 uint32_t sh_offset, uint64_t va, bool global)
1337 {
1338 bool use_32bit_pointers = !global;
1339
1340 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1341 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1342 }
1343
1344 static inline struct radv_descriptor_state *
1345 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1346 VkPipelineBindPoint bind_point)
1347 {
1348 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1349 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1350 return &cmd_buffer->descriptors[bind_point];
1351 }
1352
1353 /*
1354 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1355 *
1356 * Limitations: Can't call normal dispatch functions without binding or rebinding
1357 * the compute pipeline.
1358 */
1359 void radv_unaligned_dispatch(
1360 struct radv_cmd_buffer *cmd_buffer,
1361 uint32_t x,
1362 uint32_t y,
1363 uint32_t z);
1364
1365 struct radv_event {
1366 struct radeon_winsys_bo *bo;
1367 uint64_t *map;
1368 };
1369
1370 struct radv_shader_module;
1371
1372 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1373 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1374 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1375 void
1376 radv_hash_shaders(unsigned char *hash,
1377 const VkPipelineShaderStageCreateInfo **stages,
1378 const struct radv_pipeline_layout *layout,
1379 const struct radv_pipeline_key *key,
1380 uint32_t flags);
1381
1382 static inline gl_shader_stage
1383 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1384 {
1385 assert(__builtin_popcount(vk_stage) == 1);
1386 return ffs(vk_stage) - 1;
1387 }
1388
1389 static inline VkShaderStageFlagBits
1390 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1391 {
1392 return (1 << mesa_stage);
1393 }
1394
1395 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1396
1397 #define radv_foreach_stage(stage, stage_bits) \
1398 for (gl_shader_stage stage, \
1399 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1400 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1401 __tmp &= ~(1 << (stage)))
1402
1403 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1404 unsigned radv_format_meta_fs_key(VkFormat format);
1405
1406 struct radv_multisample_state {
1407 uint32_t db_eqaa;
1408 uint32_t pa_sc_line_cntl;
1409 uint32_t pa_sc_mode_cntl_0;
1410 uint32_t pa_sc_mode_cntl_1;
1411 uint32_t pa_sc_aa_config;
1412 uint32_t pa_sc_aa_mask[2];
1413 unsigned num_samples;
1414 };
1415
1416 struct radv_prim_vertex_count {
1417 uint8_t min;
1418 uint8_t incr;
1419 };
1420
1421 struct radv_vertex_elements_info {
1422 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1423 };
1424
1425 struct radv_ia_multi_vgt_param_helpers {
1426 uint32_t base;
1427 bool partial_es_wave;
1428 uint8_t primgroup_size;
1429 bool wd_switch_on_eop;
1430 bool ia_switch_on_eoi;
1431 bool partial_vs_wave;
1432 };
1433
1434 #define SI_GS_PER_ES 128
1435
1436 struct radv_pipeline {
1437 struct radv_device * device;
1438 struct radv_dynamic_state dynamic_state;
1439
1440 struct radv_pipeline_layout * layout;
1441
1442 bool need_indirect_descriptor_sets;
1443 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1444 struct radv_shader_variant *gs_copy_shader;
1445 VkShaderStageFlags active_stages;
1446
1447 struct radeon_cmdbuf cs;
1448 uint32_t ctx_cs_hash;
1449 struct radeon_cmdbuf ctx_cs;
1450
1451 struct radv_vertex_elements_info vertex_elements;
1452
1453 uint32_t binding_stride[MAX_VBS];
1454 uint8_t num_vertex_bindings;
1455
1456 uint32_t user_data_0[MESA_SHADER_STAGES];
1457 union {
1458 struct {
1459 struct radv_multisample_state ms;
1460 uint32_t spi_baryc_cntl;
1461 bool prim_restart_enable;
1462 unsigned esgs_ring_size;
1463 unsigned gsvs_ring_size;
1464 uint32_t vtx_base_sgpr;
1465 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1466 uint8_t vtx_emit_num;
1467 struct radv_prim_vertex_count prim_vertex_count;
1468 bool can_use_guardband;
1469 uint32_t needed_dynamic_state;
1470 bool disable_out_of_order_rast_for_occlusion;
1471
1472 /* Used for rbplus */
1473 uint32_t col_format;
1474 uint32_t cb_target_mask;
1475 } graphics;
1476 };
1477
1478 unsigned max_waves;
1479 unsigned scratch_bytes_per_wave;
1480
1481 /* Not NULL if graphics pipeline uses streamout. */
1482 struct radv_shader_variant *streamout_shader;
1483 };
1484
1485 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1486 {
1487 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1488 }
1489
1490 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1491 {
1492 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1493 }
1494
1495 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1496 gl_shader_stage stage,
1497 int idx);
1498
1499 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1500 gl_shader_stage stage);
1501
1502 struct radv_graphics_pipeline_create_info {
1503 bool use_rectlist;
1504 bool db_depth_clear;
1505 bool db_stencil_clear;
1506 bool db_depth_disable_expclear;
1507 bool db_stencil_disable_expclear;
1508 bool db_flush_depth_inplace;
1509 bool db_flush_stencil_inplace;
1510 bool db_resummarize;
1511 uint32_t custom_blend_mode;
1512 };
1513
1514 VkResult
1515 radv_graphics_pipeline_create(VkDevice device,
1516 VkPipelineCache cache,
1517 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1518 const struct radv_graphics_pipeline_create_info *extra,
1519 const VkAllocationCallbacks *alloc,
1520 VkPipeline *pPipeline);
1521
1522 struct vk_format_description;
1523 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1524 int first_non_void);
1525 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1526 int first_non_void);
1527 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1528 uint32_t radv_translate_colorformat(VkFormat format);
1529 uint32_t radv_translate_color_numformat(VkFormat format,
1530 const struct vk_format_description *desc,
1531 int first_non_void);
1532 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1533 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1534 uint32_t radv_translate_dbformat(VkFormat format);
1535 uint32_t radv_translate_tex_dataformat(VkFormat format,
1536 const struct vk_format_description *desc,
1537 int first_non_void);
1538 uint32_t radv_translate_tex_numformat(VkFormat format,
1539 const struct vk_format_description *desc,
1540 int first_non_void);
1541 bool radv_format_pack_clear_color(VkFormat format,
1542 uint32_t clear_vals[2],
1543 VkClearColorValue *value);
1544 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1545 bool radv_dcc_formats_compatible(VkFormat format1,
1546 VkFormat format2);
1547 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1548
1549 struct radv_fmask_info {
1550 uint64_t offset;
1551 uint64_t size;
1552 unsigned alignment;
1553 unsigned pitch_in_pixels;
1554 unsigned bank_height;
1555 unsigned slice_tile_max;
1556 unsigned tile_mode_index;
1557 unsigned tile_swizzle;
1558 };
1559
1560 struct radv_cmask_info {
1561 uint64_t offset;
1562 uint64_t size;
1563 unsigned alignment;
1564 unsigned slice_tile_max;
1565 };
1566
1567
1568 struct radv_image_plane {
1569 VkFormat format;
1570 struct radeon_surf surface;
1571 uint64_t offset;
1572 };
1573
1574 struct radv_image {
1575 VkImageType type;
1576 /* The original VkFormat provided by the client. This may not match any
1577 * of the actual surface formats.
1578 */
1579 VkFormat vk_format;
1580 VkImageAspectFlags aspects;
1581 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1582 struct ac_surf_info info;
1583 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1584 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1585
1586 VkDeviceSize size;
1587 uint32_t alignment;
1588
1589 unsigned queue_family_mask;
1590 bool exclusive;
1591 bool shareable;
1592
1593 /* Set when bound */
1594 struct radeon_winsys_bo *bo;
1595 VkDeviceSize offset;
1596 uint64_t dcc_offset;
1597 uint64_t htile_offset;
1598 bool tc_compatible_htile;
1599 bool tc_compatible_cmask;
1600
1601 struct radv_fmask_info fmask;
1602 struct radv_cmask_info cmask;
1603 uint64_t clear_value_offset;
1604 uint64_t fce_pred_offset;
1605 uint64_t dcc_pred_offset;
1606
1607 /*
1608 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1609 * stored at this offset is UINT_MAX, the driver will emit
1610 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1611 * SET_CONTEXT_REG packet.
1612 */
1613 uint64_t tc_compat_zrange_offset;
1614
1615 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1616 VkDeviceMemory owned_memory;
1617
1618 unsigned plane_count;
1619 struct radv_image_plane planes[0];
1620 };
1621
1622 /* Whether the image has a htile that is known consistent with the contents of
1623 * the image. */
1624 bool radv_layout_has_htile(const struct radv_image *image,
1625 VkImageLayout layout,
1626 unsigned queue_mask);
1627
1628 /* Whether the image has a htile that is known consistent with the contents of
1629 * the image and is allowed to be in compressed form.
1630 *
1631 * If this is false reads that don't use the htile should be able to return
1632 * correct results.
1633 */
1634 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1635 VkImageLayout layout,
1636 unsigned queue_mask);
1637
1638 bool radv_layout_can_fast_clear(const struct radv_image *image,
1639 VkImageLayout layout,
1640 unsigned queue_mask);
1641
1642 bool radv_layout_dcc_compressed(const struct radv_image *image,
1643 VkImageLayout layout,
1644 unsigned queue_mask);
1645
1646 /**
1647 * Return whether the image has CMASK metadata for color surfaces.
1648 */
1649 static inline bool
1650 radv_image_has_cmask(const struct radv_image *image)
1651 {
1652 return image->cmask.size;
1653 }
1654
1655 /**
1656 * Return whether the image has FMASK metadata for color surfaces.
1657 */
1658 static inline bool
1659 radv_image_has_fmask(const struct radv_image *image)
1660 {
1661 return image->fmask.size;
1662 }
1663
1664 /**
1665 * Return whether the image has DCC metadata for color surfaces.
1666 */
1667 static inline bool
1668 radv_image_has_dcc(const struct radv_image *image)
1669 {
1670 return image->planes[0].surface.dcc_size;
1671 }
1672
1673 /**
1674 * Return whether the image is TC-compatible CMASK.
1675 */
1676 static inline bool
1677 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1678 {
1679 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1680 }
1681
1682 /**
1683 * Return whether DCC metadata is enabled for a level.
1684 */
1685 static inline bool
1686 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1687 {
1688 return radv_image_has_dcc(image) &&
1689 level < image->planes[0].surface.num_dcc_levels;
1690 }
1691
1692 /**
1693 * Return whether the image has CB metadata.
1694 */
1695 static inline bool
1696 radv_image_has_CB_metadata(const struct radv_image *image)
1697 {
1698 return radv_image_has_cmask(image) ||
1699 radv_image_has_fmask(image) ||
1700 radv_image_has_dcc(image);
1701 }
1702
1703 /**
1704 * Return whether the image has HTILE metadata for depth surfaces.
1705 */
1706 static inline bool
1707 radv_image_has_htile(const struct radv_image *image)
1708 {
1709 return image->planes[0].surface.htile_size;
1710 }
1711
1712 /**
1713 * Return whether HTILE metadata is enabled for a level.
1714 */
1715 static inline bool
1716 radv_htile_enabled(const struct radv_image *image, unsigned level)
1717 {
1718 return radv_image_has_htile(image) && level == 0;
1719 }
1720
1721 /**
1722 * Return whether the image is TC-compatible HTILE.
1723 */
1724 static inline bool
1725 radv_image_is_tc_compat_htile(const struct radv_image *image)
1726 {
1727 return radv_image_has_htile(image) && image->tc_compatible_htile;
1728 }
1729
1730 static inline uint64_t
1731 radv_image_get_fast_clear_va(const struct radv_image *image,
1732 uint32_t base_level)
1733 {
1734 uint64_t va = radv_buffer_get_va(image->bo);
1735 va += image->offset + image->clear_value_offset + base_level * 8;
1736 return va;
1737 }
1738
1739 static inline uint64_t
1740 radv_image_get_fce_pred_va(const struct radv_image *image,
1741 uint32_t base_level)
1742 {
1743 uint64_t va = radv_buffer_get_va(image->bo);
1744 va += image->offset + image->fce_pred_offset + base_level * 8;
1745 return va;
1746 }
1747
1748 static inline uint64_t
1749 radv_image_get_dcc_pred_va(const struct radv_image *image,
1750 uint32_t base_level)
1751 {
1752 uint64_t va = radv_buffer_get_va(image->bo);
1753 va += image->offset + image->dcc_pred_offset + base_level * 8;
1754 return va;
1755 }
1756
1757 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1758
1759 static inline uint32_t
1760 radv_get_layerCount(const struct radv_image *image,
1761 const VkImageSubresourceRange *range)
1762 {
1763 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1764 image->info.array_size - range->baseArrayLayer : range->layerCount;
1765 }
1766
1767 static inline uint32_t
1768 radv_get_levelCount(const struct radv_image *image,
1769 const VkImageSubresourceRange *range)
1770 {
1771 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1772 image->info.levels - range->baseMipLevel : range->levelCount;
1773 }
1774
1775 struct radeon_bo_metadata;
1776 void
1777 radv_init_metadata(struct radv_device *device,
1778 struct radv_image *image,
1779 struct radeon_bo_metadata *metadata);
1780
1781 void
1782 radv_image_override_offset_stride(struct radv_device *device,
1783 struct radv_image *image,
1784 uint64_t offset, uint32_t stride);
1785
1786 union radv_descriptor {
1787 struct {
1788 uint32_t plane0_descriptor[8];
1789 uint32_t fmask_descriptor[8];
1790 };
1791 struct {
1792 uint32_t plane_descriptors[3][8];
1793 };
1794 };
1795
1796 struct radv_image_view {
1797 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1798 struct radeon_winsys_bo *bo;
1799
1800 VkImageViewType type;
1801 VkImageAspectFlags aspect_mask;
1802 VkFormat vk_format;
1803 unsigned plane_id;
1804 bool multiple_planes;
1805 uint32_t base_layer;
1806 uint32_t layer_count;
1807 uint32_t base_mip;
1808 uint32_t level_count;
1809 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1810
1811 union radv_descriptor descriptor;
1812
1813 /* Descriptor for use as a storage image as opposed to a sampled image.
1814 * This has a few differences for cube maps (e.g. type).
1815 */
1816 union radv_descriptor storage_descriptor;
1817 };
1818
1819 struct radv_image_create_info {
1820 const VkImageCreateInfo *vk_info;
1821 bool scanout;
1822 bool no_metadata_planes;
1823 const struct radeon_bo_metadata *bo_metadata;
1824 };
1825
1826 VkResult radv_image_create(VkDevice _device,
1827 const struct radv_image_create_info *info,
1828 const VkAllocationCallbacks* alloc,
1829 VkImage *pImage);
1830
1831 VkResult
1832 radv_image_from_gralloc(VkDevice device_h,
1833 const VkImageCreateInfo *base_info,
1834 const VkNativeBufferANDROID *gralloc_info,
1835 const VkAllocationCallbacks *alloc,
1836 VkImage *out_image_h);
1837
1838 void radv_image_view_init(struct radv_image_view *view,
1839 struct radv_device *device,
1840 const VkImageViewCreateInfo* pCreateInfo);
1841
1842 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1843
1844 struct radv_sampler_ycbcr_conversion {
1845 VkFormat format;
1846 VkSamplerYcbcrModelConversion ycbcr_model;
1847 VkSamplerYcbcrRange ycbcr_range;
1848 VkComponentMapping components;
1849 VkChromaLocation chroma_offsets[2];
1850 VkFilter chroma_filter;
1851 };
1852
1853 struct radv_buffer_view {
1854 struct radeon_winsys_bo *bo;
1855 VkFormat vk_format;
1856 uint64_t range; /**< VkBufferViewCreateInfo::range */
1857 uint32_t state[4];
1858 };
1859 void radv_buffer_view_init(struct radv_buffer_view *view,
1860 struct radv_device *device,
1861 const VkBufferViewCreateInfo* pCreateInfo);
1862
1863 static inline struct VkExtent3D
1864 radv_sanitize_image_extent(const VkImageType imageType,
1865 const struct VkExtent3D imageExtent)
1866 {
1867 switch (imageType) {
1868 case VK_IMAGE_TYPE_1D:
1869 return (VkExtent3D) { imageExtent.width, 1, 1 };
1870 case VK_IMAGE_TYPE_2D:
1871 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1872 case VK_IMAGE_TYPE_3D:
1873 return imageExtent;
1874 default:
1875 unreachable("invalid image type");
1876 }
1877 }
1878
1879 static inline struct VkOffset3D
1880 radv_sanitize_image_offset(const VkImageType imageType,
1881 const struct VkOffset3D imageOffset)
1882 {
1883 switch (imageType) {
1884 case VK_IMAGE_TYPE_1D:
1885 return (VkOffset3D) { imageOffset.x, 0, 0 };
1886 case VK_IMAGE_TYPE_2D:
1887 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1888 case VK_IMAGE_TYPE_3D:
1889 return imageOffset;
1890 default:
1891 unreachable("invalid image type");
1892 }
1893 }
1894
1895 static inline bool
1896 radv_image_extent_compare(const struct radv_image *image,
1897 const VkExtent3D *extent)
1898 {
1899 if (extent->width != image->info.width ||
1900 extent->height != image->info.height ||
1901 extent->depth != image->info.depth)
1902 return false;
1903 return true;
1904 }
1905
1906 struct radv_sampler {
1907 uint32_t state[4];
1908 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1909 };
1910
1911 struct radv_color_buffer_info {
1912 uint64_t cb_color_base;
1913 uint64_t cb_color_cmask;
1914 uint64_t cb_color_fmask;
1915 uint64_t cb_dcc_base;
1916 uint32_t cb_color_slice;
1917 uint32_t cb_color_view;
1918 uint32_t cb_color_info;
1919 uint32_t cb_color_attrib;
1920 uint32_t cb_color_attrib2;
1921 uint32_t cb_dcc_control;
1922 uint32_t cb_color_cmask_slice;
1923 uint32_t cb_color_fmask_slice;
1924 union {
1925 uint32_t cb_color_pitch; // GFX6-GFX8
1926 uint32_t cb_mrt_epitch; // GFX9+
1927 };
1928 };
1929
1930 struct radv_ds_buffer_info {
1931 uint64_t db_z_read_base;
1932 uint64_t db_stencil_read_base;
1933 uint64_t db_z_write_base;
1934 uint64_t db_stencil_write_base;
1935 uint64_t db_htile_data_base;
1936 uint32_t db_depth_info;
1937 uint32_t db_z_info;
1938 uint32_t db_stencil_info;
1939 uint32_t db_depth_view;
1940 uint32_t db_depth_size;
1941 uint32_t db_depth_slice;
1942 uint32_t db_htile_surface;
1943 uint32_t pa_su_poly_offset_db_fmt_cntl;
1944 uint32_t db_z_info2;
1945 uint32_t db_stencil_info2;
1946 float offset_scale;
1947 };
1948
1949 struct radv_attachment_info {
1950 union {
1951 struct radv_color_buffer_info cb;
1952 struct radv_ds_buffer_info ds;
1953 };
1954 struct radv_image_view *attachment;
1955 };
1956
1957 struct radv_framebuffer {
1958 uint32_t width;
1959 uint32_t height;
1960 uint32_t layers;
1961
1962 uint32_t attachment_count;
1963 struct radv_attachment_info attachments[0];
1964 };
1965
1966 struct radv_subpass_barrier {
1967 VkPipelineStageFlags src_stage_mask;
1968 VkAccessFlags src_access_mask;
1969 VkAccessFlags dst_access_mask;
1970 };
1971
1972 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1973 const struct radv_subpass_barrier *barrier);
1974
1975 struct radv_subpass_attachment {
1976 uint32_t attachment;
1977 VkImageLayout layout;
1978 };
1979
1980 struct radv_subpass {
1981 uint32_t attachment_count;
1982 struct radv_subpass_attachment * attachments;
1983
1984 uint32_t input_count;
1985 uint32_t color_count;
1986 struct radv_subpass_attachment * input_attachments;
1987 struct radv_subpass_attachment * color_attachments;
1988 struct radv_subpass_attachment * resolve_attachments;
1989 struct radv_subpass_attachment * depth_stencil_attachment;
1990 struct radv_subpass_attachment * ds_resolve_attachment;
1991 VkResolveModeFlagBitsKHR depth_resolve_mode;
1992 VkResolveModeFlagBitsKHR stencil_resolve_mode;
1993
1994 /** Subpass has at least one color resolve attachment */
1995 bool has_color_resolve;
1996
1997 /** Subpass has at least one color attachment */
1998 bool has_color_att;
1999
2000 struct radv_subpass_barrier start_barrier;
2001
2002 uint32_t view_mask;
2003 VkSampleCountFlagBits max_sample_count;
2004 };
2005
2006 uint32_t
2007 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2008
2009 struct radv_render_pass_attachment {
2010 VkFormat format;
2011 uint32_t samples;
2012 VkAttachmentLoadOp load_op;
2013 VkAttachmentLoadOp stencil_load_op;
2014 VkImageLayout initial_layout;
2015 VkImageLayout final_layout;
2016
2017 /* The subpass id in which the attachment will be used first/last. */
2018 uint32_t first_subpass_idx;
2019 uint32_t last_subpass_idx;
2020 };
2021
2022 struct radv_render_pass {
2023 uint32_t attachment_count;
2024 uint32_t subpass_count;
2025 struct radv_subpass_attachment * subpass_attachments;
2026 struct radv_render_pass_attachment * attachments;
2027 struct radv_subpass_barrier end_barrier;
2028 struct radv_subpass subpasses[0];
2029 };
2030
2031 VkResult radv_device_init_meta(struct radv_device *device);
2032 void radv_device_finish_meta(struct radv_device *device);
2033
2034 struct radv_query_pool {
2035 struct radeon_winsys_bo *bo;
2036 uint32_t stride;
2037 uint32_t availability_offset;
2038 uint64_t size;
2039 char *ptr;
2040 VkQueryType type;
2041 uint32_t pipeline_stats_mask;
2042 };
2043
2044 struct radv_semaphore {
2045 /* use a winsys sem for non-exportable */
2046 struct radeon_winsys_sem *sem;
2047 uint32_t syncobj;
2048 uint32_t temp_syncobj;
2049 };
2050
2051 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2052 VkPipelineBindPoint bind_point,
2053 struct radv_descriptor_set *set,
2054 unsigned idx);
2055
2056 void
2057 radv_update_descriptor_sets(struct radv_device *device,
2058 struct radv_cmd_buffer *cmd_buffer,
2059 VkDescriptorSet overrideSet,
2060 uint32_t descriptorWriteCount,
2061 const VkWriteDescriptorSet *pDescriptorWrites,
2062 uint32_t descriptorCopyCount,
2063 const VkCopyDescriptorSet *pDescriptorCopies);
2064
2065 void
2066 radv_update_descriptor_set_with_template(struct radv_device *device,
2067 struct radv_cmd_buffer *cmd_buffer,
2068 struct radv_descriptor_set *set,
2069 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2070 const void *pData);
2071
2072 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2073 VkPipelineBindPoint pipelineBindPoint,
2074 VkPipelineLayout _layout,
2075 uint32_t set,
2076 uint32_t descriptorWriteCount,
2077 const VkWriteDescriptorSet *pDescriptorWrites);
2078
2079 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2080 struct radv_image *image,
2081 const VkImageSubresourceRange *range, uint32_t value);
2082
2083 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2084 struct radv_image *image);
2085
2086 struct radv_fence {
2087 struct radeon_winsys_fence *fence;
2088 struct wsi_fence *fence_wsi;
2089
2090 uint32_t syncobj;
2091 uint32_t temp_syncobj;
2092 };
2093
2094 /* radv_nir_to_llvm.c */
2095 struct radv_shader_variant_info;
2096 struct radv_nir_compiler_options;
2097
2098 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2099 struct nir_shader *geom_shader,
2100 struct ac_shader_binary *binary,
2101 struct ac_shader_config *config,
2102 struct radv_shader_variant_info *shader_info,
2103 const struct radv_nir_compiler_options *option);
2104
2105 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2106 struct ac_shader_binary *binary,
2107 struct ac_shader_config *config,
2108 struct radv_shader_variant_info *shader_info,
2109 struct nir_shader *const *nir,
2110 int nir_count,
2111 const struct radv_nir_compiler_options *options);
2112
2113 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2114 const struct nir_shader *nir);
2115
2116 /* radv_shader_info.h */
2117 struct radv_shader_info;
2118
2119 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2120 const struct radv_nir_compiler_options *options,
2121 struct radv_shader_info *info);
2122
2123 void radv_nir_shader_info_init(struct radv_shader_info *info);
2124
2125 struct radeon_winsys_sem;
2126
2127 uint64_t radv_get_current_time(void);
2128
2129 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2130 \
2131 static inline struct __radv_type * \
2132 __radv_type ## _from_handle(__VkType _handle) \
2133 { \
2134 return (struct __radv_type *) _handle; \
2135 } \
2136 \
2137 static inline __VkType \
2138 __radv_type ## _to_handle(struct __radv_type *_obj) \
2139 { \
2140 return (__VkType) _obj; \
2141 }
2142
2143 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2144 \
2145 static inline struct __radv_type * \
2146 __radv_type ## _from_handle(__VkType _handle) \
2147 { \
2148 return (struct __radv_type *)(uintptr_t) _handle; \
2149 } \
2150 \
2151 static inline __VkType \
2152 __radv_type ## _to_handle(struct __radv_type *_obj) \
2153 { \
2154 return (__VkType)(uintptr_t) _obj; \
2155 }
2156
2157 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2158 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2159
2160 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2161 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2162 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2163 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2164 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2165
2166 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2167 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2168 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2169 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2170 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2171 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2172 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2173 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2174 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2175 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2176 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2177 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2178 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2179 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2180 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2181 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2182 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2183 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2184 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2185 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2186 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2187 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2188
2189 #endif /* RADV_PRIVATE_H */