2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
80 #include <vulkan/vk_android_native_buffer.h>
82 #include "radv_entrypoints.h"
84 #include "wsi_common.h"
85 #include "wsi_common_display.h"
88 unsigned img_format
:9;
90 /* Various formats are only supported with workarounds for vertex fetch,
91 * and some 32_32_32 formats are supported natively, but only for buffers
92 * (possibly with some image support, actually, but no filtering). */
96 #include "gfx10_format_table.h"
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
109 RADV_MEM_TYPE_GTT_CACHED
,
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115 static inline uint32_t
116 align_u32(uint32_t v
, uint32_t a
)
118 assert(a
!= 0 && a
== (a
& -a
));
119 return (v
+ a
- 1) & ~(a
- 1);
122 static inline uint32_t
123 align_u32_npot(uint32_t v
, uint32_t a
)
125 return (v
+ a
- 1) / a
* a
;
128 static inline uint64_t
129 align_u64(uint64_t v
, uint64_t a
)
131 assert(a
!= 0 && a
== (a
& -a
));
132 return (v
+ a
- 1) & ~(a
- 1);
135 static inline int32_t
136 align_i32(int32_t v
, int32_t a
)
138 assert(a
!= 0 && a
== (a
& -a
));
139 return (v
+ a
- 1) & ~(a
- 1);
142 /** Alignment must be a power of 2. */
144 radv_is_aligned(uintmax_t n
, uintmax_t a
)
146 assert(a
== (a
& -a
));
147 return (n
& (a
- 1)) == 0;
150 static inline uint32_t
151 round_up_u32(uint32_t v
, uint32_t a
)
153 return (v
+ a
- 1) / a
;
156 static inline uint64_t
157 round_up_u64(uint64_t v
, uint64_t a
)
159 return (v
+ a
- 1) / a
;
162 static inline uint32_t
163 radv_minify(uint32_t n
, uint32_t levels
)
165 if (unlikely(n
== 0))
168 return MAX2(n
>> levels
, 1);
171 radv_clamp_f(float f
, float min
, float max
)
184 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
186 if (*inout_mask
& clear_mask
) {
187 *inout_mask
&= ~clear_mask
;
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
209 struct radv_instance
;
211 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
213 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
216 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format
, va_list va
);
220 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
221 void radv_logi_v(const char *format
, va_list va
);
224 * Print a FINISHME message, including its source location.
226 #define radv_finishme(format, ...) \
228 static bool reported = false; \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
235 /* A non-fatal assert. Useful for debugging. */
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
242 #define radv_assert(x)
245 #define stub_return(v) \
247 radv_finishme("stub %s", __func__); \
253 radv_finishme("stub %s", __func__); \
257 void *radv_lookup_entrypoint_unchecked(const char *name
);
258 void *radv_lookup_entrypoint_checked(const char *name
,
259 uint32_t core_version
,
260 const struct radv_instance_extension_table
*instance
,
261 const struct radv_device_extension_table
*device
);
262 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
263 uint32_t core_version
,
264 const struct radv_instance_extension_table
*instance
);
266 struct radv_physical_device
{
267 VK_LOADER_DATA _loader_data
;
269 struct radv_instance
* instance
;
271 struct radeon_winsys
*ws
;
272 struct radeon_info rad_info
;
273 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
274 uint8_t driver_uuid
[VK_UUID_SIZE
];
275 uint8_t device_uuid
[VK_UUID_SIZE
];
276 uint8_t cache_uuid
[VK_UUID_SIZE
];
280 struct wsi_device wsi_device
;
282 bool has_rbplus
; /* if RB+ register exist */
283 bool rbplus_allowed
; /* if RB+ is allowed */
284 bool has_clear_state
;
285 bool cpdma_prefetch_writes_memory
;
286 bool has_scissor_bug
;
287 bool has_tc_compat_zrange_bug
;
289 bool has_out_of_order_rast
;
290 bool out_of_order_rast_allowed
;
292 /* Whether DCC should be enabled for MSAA textures. */
293 bool dcc_msaa_allowed
;
295 /* Whether LOAD_CONTEXT_REG packets are supported. */
296 bool has_load_ctx_reg_pkt
;
298 /* Whether to enable the AMD_shader_ballot extension */
299 bool use_shader_ballot
;
301 /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
302 bool has_dcc_constant_encode
;
304 /* Number of threads per wave. */
305 uint8_t cs_wave_size
;
307 /* This is the drivers on-disk cache used as a fallback as opposed to
308 * the pipeline cache defined by apps.
310 struct disk_cache
* disk_cache
;
312 VkPhysicalDeviceMemoryProperties memory_properties
;
313 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
315 drmPciBusInfo bus_info
;
317 struct radv_device_extension_table supported_extensions
;
320 struct radv_instance
{
321 VK_LOADER_DATA _loader_data
;
323 VkAllocationCallbacks alloc
;
326 int physicalDeviceCount
;
327 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
329 uint64_t debug_flags
;
330 uint64_t perftest_flags
;
332 struct vk_debug_report_instance debug_report_callbacks
;
334 struct radv_instance_extension_table enabled_extensions
;
336 struct driOptionCache dri_options
;
337 struct driOptionCache available_dri_options
;
340 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
341 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
343 bool radv_instance_extension_supported(const char *name
);
344 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
345 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
350 struct radv_pipeline_cache
{
351 struct radv_device
* device
;
352 pthread_mutex_t mutex
;
356 uint32_t kernel_count
;
357 struct cache_entry
** hash_table
;
360 VkAllocationCallbacks alloc
;
363 struct radv_pipeline_key
{
364 uint32_t instance_rate_inputs
;
365 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
366 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
367 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
368 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
369 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
370 uint64_t vertex_alpha_adjust
;
371 uint32_t vertex_post_shuffle
;
372 unsigned tess_input_vertices
;
376 uint8_t log2_ps_iter_samples
;
378 uint32_t has_multiview_view_index
: 1;
379 uint32_t optimisations_disabled
: 1;
382 struct radv_shader_binary
;
383 struct radv_shader_variant
;
386 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
387 struct radv_device
*device
);
389 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
391 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
392 const void *data
, size_t size
);
395 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
396 struct radv_pipeline_cache
*cache
,
397 const unsigned char *sha1
,
398 struct radv_shader_variant
**variants
,
399 bool *found_in_application_cache
);
402 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
403 struct radv_pipeline_cache
*cache
,
404 const unsigned char *sha1
,
405 struct radv_shader_variant
**variants
,
406 struct radv_shader_binary
*const *binaries
);
408 enum radv_blit_ds_layout
{
409 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
410 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
411 RADV_BLIT_DS_LAYOUT_COUNT
,
414 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
416 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
419 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
421 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
424 enum radv_meta_dst_layout
{
425 RADV_META_DST_LAYOUT_GENERAL
,
426 RADV_META_DST_LAYOUT_OPTIMAL
,
427 RADV_META_DST_LAYOUT_COUNT
,
430 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
432 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
435 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
437 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
440 struct radv_meta_state
{
441 VkAllocationCallbacks alloc
;
443 struct radv_pipeline_cache cache
;
446 * For on-demand pipeline creation, makes sure that
447 * only one thread tries to build a pipeline at the same time.
452 * Use array element `i` for images with `2^i` samples.
455 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
456 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
458 VkRenderPass depthstencil_rp
;
459 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
460 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
461 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
462 } clear
[1 + MAX_SAMPLES_LOG2
];
464 VkPipelineLayout clear_color_p_layout
;
465 VkPipelineLayout clear_depth_p_layout
;
467 /* Optimized compute fast HTILE clear for stencil or depth only. */
468 VkPipeline clear_htile_mask_pipeline
;
469 VkPipelineLayout clear_htile_mask_p_layout
;
470 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
473 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
475 /** Pipeline that blits from a 1D image. */
476 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
478 /** Pipeline that blits from a 2D image. */
479 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
481 /** Pipeline that blits from a 3D image. */
482 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
484 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
485 VkPipeline depth_only_1d_pipeline
;
486 VkPipeline depth_only_2d_pipeline
;
487 VkPipeline depth_only_3d_pipeline
;
489 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
490 VkPipeline stencil_only_1d_pipeline
;
491 VkPipeline stencil_only_2d_pipeline
;
492 VkPipeline stencil_only_3d_pipeline
;
493 VkPipelineLayout pipeline_layout
;
494 VkDescriptorSetLayout ds_layout
;
498 VkPipelineLayout p_layouts
[5];
499 VkDescriptorSetLayout ds_layouts
[5];
500 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
502 VkPipeline depth_only_pipeline
[5];
504 VkPipeline stencil_only_pipeline
[5];
505 } blit2d
[1 + MAX_SAMPLES_LOG2
];
507 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
508 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
509 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
512 VkPipelineLayout img_p_layout
;
513 VkDescriptorSetLayout img_ds_layout
;
515 VkPipeline pipeline_3d
;
518 VkPipelineLayout img_p_layout
;
519 VkDescriptorSetLayout img_ds_layout
;
521 VkPipeline pipeline_3d
;
524 VkPipelineLayout img_p_layout
;
525 VkDescriptorSetLayout img_ds_layout
;
529 VkPipelineLayout img_p_layout
;
530 VkDescriptorSetLayout img_ds_layout
;
532 VkPipeline pipeline_3d
;
535 VkPipelineLayout img_p_layout
;
536 VkDescriptorSetLayout img_ds_layout
;
540 VkPipelineLayout img_p_layout
;
541 VkDescriptorSetLayout img_ds_layout
;
543 VkPipeline pipeline_3d
;
546 VkPipelineLayout img_p_layout
;
547 VkDescriptorSetLayout img_ds_layout
;
552 VkPipelineLayout p_layout
;
553 VkPipeline pipeline
[NUM_META_FS_KEYS
];
554 VkRenderPass pass
[NUM_META_FS_KEYS
];
558 VkDescriptorSetLayout ds_layout
;
559 VkPipelineLayout p_layout
;
562 VkPipeline i_pipeline
;
563 VkPipeline srgb_pipeline
;
564 } rc
[MAX_SAMPLES_LOG2
];
566 VkPipeline depth_zero_pipeline
;
568 VkPipeline average_pipeline
;
569 VkPipeline max_pipeline
;
570 VkPipeline min_pipeline
;
571 } depth
[MAX_SAMPLES_LOG2
];
573 VkPipeline stencil_zero_pipeline
;
575 VkPipeline max_pipeline
;
576 VkPipeline min_pipeline
;
577 } stencil
[MAX_SAMPLES_LOG2
];
581 VkDescriptorSetLayout ds_layout
;
582 VkPipelineLayout p_layout
;
585 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
586 VkPipeline pipeline
[NUM_META_FS_KEYS
];
587 } rc
[MAX_SAMPLES_LOG2
];
589 VkRenderPass depth_render_pass
;
590 VkPipeline depth_zero_pipeline
;
592 VkPipeline average_pipeline
;
593 VkPipeline max_pipeline
;
594 VkPipeline min_pipeline
;
595 } depth
[MAX_SAMPLES_LOG2
];
597 VkRenderPass stencil_render_pass
;
598 VkPipeline stencil_zero_pipeline
;
600 VkPipeline max_pipeline
;
601 VkPipeline min_pipeline
;
602 } stencil
[MAX_SAMPLES_LOG2
];
606 VkPipelineLayout p_layout
;
607 VkPipeline decompress_pipeline
;
608 VkPipeline resummarize_pipeline
;
610 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
613 VkPipelineLayout p_layout
;
614 VkPipeline cmask_eliminate_pipeline
;
615 VkPipeline fmask_decompress_pipeline
;
616 VkPipeline dcc_decompress_pipeline
;
619 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
620 VkPipelineLayout dcc_decompress_compute_p_layout
;
621 VkPipeline dcc_decompress_compute_pipeline
;
625 VkPipelineLayout fill_p_layout
;
626 VkPipelineLayout copy_p_layout
;
627 VkDescriptorSetLayout fill_ds_layout
;
628 VkDescriptorSetLayout copy_ds_layout
;
629 VkPipeline fill_pipeline
;
630 VkPipeline copy_pipeline
;
634 VkDescriptorSetLayout ds_layout
;
635 VkPipelineLayout p_layout
;
636 VkPipeline occlusion_query_pipeline
;
637 VkPipeline pipeline_statistics_query_pipeline
;
638 VkPipeline tfb_query_pipeline
;
642 VkDescriptorSetLayout ds_layout
;
643 VkPipelineLayout p_layout
;
644 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
649 #define RADV_QUEUE_GENERAL 0
650 #define RADV_QUEUE_COMPUTE 1
651 #define RADV_QUEUE_TRANSFER 2
653 #define RADV_MAX_QUEUE_FAMILIES 3
655 enum ring_type
radv_queue_family_to_ring(int f
);
658 VK_LOADER_DATA _loader_data
;
659 struct radv_device
* device
;
660 struct radeon_winsys_ctx
*hw_ctx
;
661 enum radeon_ctx_priority priority
;
662 uint32_t queue_family_index
;
664 VkDeviceQueueCreateFlags flags
;
666 uint32_t scratch_size
;
667 uint32_t compute_scratch_size
;
668 uint32_t esgs_ring_size
;
669 uint32_t gsvs_ring_size
;
671 bool has_sample_positions
;
673 struct radeon_winsys_bo
*scratch_bo
;
674 struct radeon_winsys_bo
*descriptor_bo
;
675 struct radeon_winsys_bo
*compute_scratch_bo
;
676 struct radeon_winsys_bo
*esgs_ring_bo
;
677 struct radeon_winsys_bo
*gsvs_ring_bo
;
678 struct radeon_winsys_bo
*tess_rings_bo
;
679 struct radeon_cmdbuf
*initial_preamble_cs
;
680 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
681 struct radeon_cmdbuf
*continue_preamble_cs
;
684 struct radv_bo_list
{
685 struct radv_winsys_bo_list list
;
687 pthread_mutex_t mutex
;
691 VK_LOADER_DATA _loader_data
;
693 VkAllocationCallbacks alloc
;
695 struct radv_instance
* instance
;
696 struct radeon_winsys
*ws
;
698 struct radv_meta_state meta_state
;
700 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
701 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
702 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
704 bool always_use_syncobj
;
705 bool has_distributed_tess
;
708 uint32_t tess_offchip_block_dw_size
;
709 uint32_t scratch_waves
;
710 uint32_t dispatch_initiator
;
712 uint32_t gs_table_depth
;
714 /* MSAA sample locations.
715 * The first index is the sample index.
716 * The second index is the coordinate: X, Y. */
717 float sample_locations_1x
[1][2];
718 float sample_locations_2x
[2][2];
719 float sample_locations_4x
[4][2];
720 float sample_locations_8x
[8][2];
723 uint32_t gfx_init_size_dw
;
724 struct radeon_winsys_bo
*gfx_init
;
726 struct radeon_winsys_bo
*trace_bo
;
727 uint32_t *trace_id_ptr
;
729 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
730 bool keep_shader_info
;
732 struct radv_physical_device
*physical_device
;
734 /* Backup in-memory cache to be used if the app doesn't provide one */
735 struct radv_pipeline_cache
* mem_cache
;
738 * use different counters so MSAA MRTs get consecutive surface indices,
739 * even if MASK is allocated in between.
741 uint32_t image_mrt_offset_counter
;
742 uint32_t fmask_mrt_offset_counter
;
743 struct list_head shader_slabs
;
744 mtx_t shader_slab_mutex
;
746 /* For detecting VM faults reported by dmesg. */
747 uint64_t dmesg_timestamp
;
749 struct radv_device_extension_table enabled_extensions
;
751 /* Whether the driver uses a global BO list. */
752 bool use_global_bo_list
;
754 struct radv_bo_list bo_list
;
756 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
760 struct radv_device_memory
{
761 struct radeon_winsys_bo
*bo
;
762 /* for dedicated allocations */
763 struct radv_image
*image
;
764 struct radv_buffer
*buffer
;
766 VkDeviceSize map_size
;
772 struct radv_descriptor_range
{
777 struct radv_descriptor_set
{
778 const struct radv_descriptor_set_layout
*layout
;
781 struct radeon_winsys_bo
*bo
;
783 uint32_t *mapped_ptr
;
784 struct radv_descriptor_range
*dynamic_descriptors
;
786 struct radeon_winsys_bo
*descriptors
[0];
789 struct radv_push_descriptor_set
791 struct radv_descriptor_set set
;
795 struct radv_descriptor_pool_entry
{
798 struct radv_descriptor_set
*set
;
801 struct radv_descriptor_pool
{
802 struct radeon_winsys_bo
*bo
;
804 uint64_t current_offset
;
807 uint8_t *host_memory_base
;
808 uint8_t *host_memory_ptr
;
809 uint8_t *host_memory_end
;
811 uint32_t entry_count
;
812 uint32_t max_entry_count
;
813 struct radv_descriptor_pool_entry entries
[0];
816 struct radv_descriptor_update_template_entry
{
817 VkDescriptorType descriptor_type
;
819 /* The number of descriptors to update */
820 uint32_t descriptor_count
;
822 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
825 /* In dwords. Not valid/used for dynamic descriptors */
828 uint32_t buffer_offset
;
830 /* Only valid for combined image samplers and samplers */
832 uint8_t sampler_offset
;
838 /* For push descriptors */
839 const uint32_t *immutable_samplers
;
842 struct radv_descriptor_update_template
{
843 uint32_t entry_count
;
844 VkPipelineBindPoint bind_point
;
845 struct radv_descriptor_update_template_entry entry
[0];
851 VkBufferUsageFlags usage
;
852 VkBufferCreateFlags flags
;
855 struct radeon_winsys_bo
* bo
;
861 enum radv_dynamic_state_bits
{
862 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
863 RADV_DYNAMIC_SCISSOR
= 1 << 1,
864 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
865 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
866 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
867 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
868 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
869 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
870 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
871 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
872 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
873 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
876 enum radv_cmd_dirty_bits
{
877 /* Keep the dynamic state dirty bits in sync with
878 * enum radv_dynamic_state_bits */
879 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
880 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
881 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
882 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
883 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
884 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
885 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
886 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
887 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
888 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
889 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
890 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
891 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
892 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
893 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
894 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
895 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
898 enum radv_cmd_flush_bits
{
899 /* Instruction cache. */
900 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
901 /* Scalar L1 cache. */
902 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
903 /* Vector L1 cache. */
904 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
905 /* L2 cache + L2 metadata cache writeback & invalidate.
906 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
907 RADV_CMD_FLAG_INV_L2
= 1 << 3,
908 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
909 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
910 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
911 RADV_CMD_FLAG_WB_L2
= 1 << 4,
912 /* Framebuffer caches */
913 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
914 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
915 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
916 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
917 /* Engine synchronization. */
918 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
919 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
920 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
921 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
922 /* Pipeline query controls. */
923 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
924 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
925 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
927 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
928 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
929 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
930 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
933 struct radv_vertex_binding
{
934 struct radv_buffer
* buffer
;
938 struct radv_streamout_binding
{
939 struct radv_buffer
*buffer
;
944 struct radv_streamout_state
{
945 /* Mask of bound streamout buffers. */
946 uint8_t enabled_mask
;
948 /* External state that comes from the last vertex stage, it must be
949 * set explicitely when binding a new graphics pipeline.
951 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
952 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
954 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
955 uint32_t hw_enabled_mask
;
957 /* State of VGT_STRMOUT_(CONFIG|EN) */
958 bool streamout_enabled
;
961 struct radv_viewport_state
{
963 VkViewport viewports
[MAX_VIEWPORTS
];
966 struct radv_scissor_state
{
968 VkRect2D scissors
[MAX_SCISSORS
];
971 struct radv_discard_rectangle_state
{
973 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
976 struct radv_sample_locations_state
{
977 VkSampleCountFlagBits per_pixel
;
978 VkExtent2D grid_size
;
980 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
983 struct radv_dynamic_state
{
985 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
986 * Defines the set of saved dynamic state.
990 struct radv_viewport_state viewport
;
992 struct radv_scissor_state scissor
;
1002 float blend_constants
[4];
1012 } stencil_compare_mask
;
1017 } stencil_write_mask
;
1022 } stencil_reference
;
1024 struct radv_discard_rectangle_state discard_rectangle
;
1026 struct radv_sample_locations_state sample_location
;
1029 extern const struct radv_dynamic_state default_dynamic_state
;
1032 radv_get_debug_option_name(int id
);
1035 radv_get_perftest_option_name(int id
);
1038 * Attachment state when recording a renderpass instance.
1040 * The clear value is valid only if there exists a pending clear.
1042 struct radv_attachment_state
{
1043 VkImageAspectFlags pending_clear_aspects
;
1044 uint32_t cleared_views
;
1045 VkClearValue clear_value
;
1046 VkImageLayout current_layout
;
1047 struct radv_sample_locations_state sample_location
;
1050 struct radv_descriptor_state
{
1051 struct radv_descriptor_set
*sets
[MAX_SETS
];
1054 struct radv_push_descriptor_set push_set
;
1056 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1059 struct radv_subpass_sample_locs_state
{
1060 uint32_t subpass_idx
;
1061 struct radv_sample_locations_state sample_location
;
1064 struct radv_cmd_state
{
1065 /* Vertex descriptors */
1072 uint32_t prefetch_L2_mask
;
1074 struct radv_pipeline
* pipeline
;
1075 struct radv_pipeline
* emitted_pipeline
;
1076 struct radv_pipeline
* compute_pipeline
;
1077 struct radv_pipeline
* emitted_compute_pipeline
;
1078 struct radv_framebuffer
* framebuffer
;
1079 struct radv_render_pass
* pass
;
1080 const struct radv_subpass
* subpass
;
1081 struct radv_dynamic_state dynamic
;
1082 struct radv_attachment_state
* attachments
;
1083 struct radv_streamout_state streamout
;
1084 VkRect2D render_area
;
1086 uint32_t num_subpass_sample_locs
;
1087 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1090 struct radv_buffer
*index_buffer
;
1091 uint64_t index_offset
;
1092 uint32_t index_type
;
1093 uint32_t max_index_count
;
1095 int32_t last_index_type
;
1097 int32_t last_primitive_reset_en
;
1098 uint32_t last_primitive_reset_index
;
1099 enum radv_cmd_flush_bits flush_bits
;
1100 unsigned active_occlusion_queries
;
1101 bool perfect_occlusion_queries_enabled
;
1102 unsigned active_pipeline_queries
;
1105 uint32_t last_ia_multi_vgt_param
;
1107 uint32_t last_num_instances
;
1108 uint32_t last_first_instance
;
1109 uint32_t last_vertex_offset
;
1111 /* Whether CP DMA is busy/idle. */
1114 /* Conditional rendering info. */
1115 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1116 uint64_t predication_va
;
1118 bool context_roll_without_scissor_emitted
;
1121 struct radv_cmd_pool
{
1122 VkAllocationCallbacks alloc
;
1123 struct list_head cmd_buffers
;
1124 struct list_head free_cmd_buffers
;
1125 uint32_t queue_family_index
;
1128 struct radv_cmd_buffer_upload
{
1132 struct radeon_winsys_bo
*upload_bo
;
1133 struct list_head list
;
1136 enum radv_cmd_buffer_status
{
1137 RADV_CMD_BUFFER_STATUS_INVALID
,
1138 RADV_CMD_BUFFER_STATUS_INITIAL
,
1139 RADV_CMD_BUFFER_STATUS_RECORDING
,
1140 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1141 RADV_CMD_BUFFER_STATUS_PENDING
,
1144 struct radv_cmd_buffer
{
1145 VK_LOADER_DATA _loader_data
;
1147 struct radv_device
* device
;
1149 struct radv_cmd_pool
* pool
;
1150 struct list_head pool_link
;
1152 VkCommandBufferUsageFlags usage_flags
;
1153 VkCommandBufferLevel level
;
1154 enum radv_cmd_buffer_status status
;
1155 struct radeon_cmdbuf
*cs
;
1156 struct radv_cmd_state state
;
1157 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1158 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1159 uint32_t queue_family_index
;
1161 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1162 VkShaderStageFlags push_constant_stages
;
1163 struct radv_descriptor_set meta_push_descriptors
;
1165 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1167 struct radv_cmd_buffer_upload upload
;
1169 uint32_t scratch_size_needed
;
1170 uint32_t compute_scratch_size_needed
;
1171 uint32_t esgs_ring_size_needed
;
1172 uint32_t gsvs_ring_size_needed
;
1173 bool tess_rings_needed
;
1174 bool sample_positions_needed
;
1176 VkResult record_result
;
1178 uint64_t gfx9_fence_va
;
1179 uint32_t gfx9_fence_idx
;
1180 uint64_t gfx9_eop_bug_va
;
1183 * Whether a query pool has been resetted and we have to flush caches.
1185 bool pending_reset_query
;
1188 * Bitmask of pending active query flushes.
1190 enum radv_cmd_flush_bits active_query_flush_bits
;
1194 struct radv_image_view
;
1196 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1198 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1199 struct radeon_cmdbuf
*cs
);
1200 void si_emit_compute(struct radv_physical_device
*physical_device
,
1201 struct radeon_cmdbuf
*cs
);
1203 void cik_create_gfx_config(struct radv_device
*device
);
1205 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1206 int count
, const VkViewport
*viewports
);
1207 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1208 int count
, const VkRect2D
*scissors
,
1209 const VkViewport
*viewports
, bool can_use_guardband
);
1210 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1211 bool instanced_draw
, bool indirect_draw
,
1212 bool count_from_stream_output
,
1213 uint32_t draw_vertex_count
);
1214 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1215 enum chip_class chip_class
,
1217 unsigned event
, unsigned event_flags
,
1218 unsigned dst_sel
, unsigned data_sel
,
1221 uint64_t gfx9_eop_bug_va
);
1223 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1224 uint32_t ref
, uint32_t mask
);
1225 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1226 enum chip_class chip_class
,
1227 uint32_t *fence_ptr
, uint64_t va
,
1229 enum radv_cmd_flush_bits flush_bits
,
1230 uint64_t gfx9_eop_bug_va
);
1231 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1232 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1233 bool inverted
, uint64_t va
);
1234 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1235 uint64_t src_va
, uint64_t dest_va
,
1237 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1239 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1240 uint64_t size
, unsigned value
);
1241 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1243 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1245 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1248 unsigned *out_offset
,
1251 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1252 const struct radv_subpass
*subpass
);
1254 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1255 unsigned size
, unsigned alignmnet
,
1256 const void *data
, unsigned *out_offset
);
1258 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1259 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1260 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1261 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1262 VkImageAspectFlags aspects
,
1263 VkResolveModeFlagBitsKHR resolve_mode
);
1264 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1265 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1266 VkImageAspectFlags aspects
,
1267 VkResolveModeFlagBitsKHR resolve_mode
);
1268 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1269 unsigned radv_get_default_max_sample_dist(int log_samples
);
1270 void radv_device_init_msaa(struct radv_device
*device
);
1272 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1273 struct radv_image
*image
,
1274 VkClearDepthStencilValue ds_clear_value
,
1275 VkImageAspectFlags aspects
);
1277 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1278 const struct radv_image_view
*iview
,
1280 uint32_t color_values
[2]);
1282 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1283 struct radv_image
*image
,
1284 const VkImageSubresourceRange
*range
, bool value
);
1286 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1287 struct radv_image
*image
,
1288 const VkImageSubresourceRange
*range
, bool value
);
1290 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1291 struct radeon_winsys_bo
*bo
,
1292 uint64_t offset
, uint64_t size
, uint32_t value
);
1293 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1294 bool radv_get_memory_fd(struct radv_device
*device
,
1295 struct radv_device_memory
*memory
,
1299 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1300 unsigned sh_offset
, unsigned pointer_count
,
1301 bool use_32bit_pointers
)
1303 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1304 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1308 radv_emit_shader_pointer_body(struct radv_device
*device
,
1309 struct radeon_cmdbuf
*cs
,
1310 uint64_t va
, bool use_32bit_pointers
)
1312 radeon_emit(cs
, va
);
1314 if (use_32bit_pointers
) {
1316 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1318 radeon_emit(cs
, va
>> 32);
1323 radv_emit_shader_pointer(struct radv_device
*device
,
1324 struct radeon_cmdbuf
*cs
,
1325 uint32_t sh_offset
, uint64_t va
, bool global
)
1327 bool use_32bit_pointers
= !global
;
1329 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1330 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1333 static inline struct radv_descriptor_state
*
1334 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1335 VkPipelineBindPoint bind_point
)
1337 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1338 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1339 return &cmd_buffer
->descriptors
[bind_point
];
1343 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1345 * Limitations: Can't call normal dispatch functions without binding or rebinding
1346 * the compute pipeline.
1348 void radv_unaligned_dispatch(
1349 struct radv_cmd_buffer
*cmd_buffer
,
1355 struct radeon_winsys_bo
*bo
;
1359 struct radv_shader_module
;
1361 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1362 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1363 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1364 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1367 radv_hash_shaders(unsigned char *hash
,
1368 const VkPipelineShaderStageCreateInfo
**stages
,
1369 const struct radv_pipeline_layout
*layout
,
1370 const struct radv_pipeline_key
*key
,
1373 static inline gl_shader_stage
1374 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1376 assert(__builtin_popcount(vk_stage
) == 1);
1377 return ffs(vk_stage
) - 1;
1380 static inline VkShaderStageFlagBits
1381 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1383 return (1 << mesa_stage
);
1386 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1388 #define radv_foreach_stage(stage, stage_bits) \
1389 for (gl_shader_stage stage, \
1390 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1391 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1392 __tmp &= ~(1 << (stage)))
1394 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1395 unsigned radv_format_meta_fs_key(VkFormat format
);
1397 struct radv_multisample_state
{
1399 uint32_t pa_sc_line_cntl
;
1400 uint32_t pa_sc_mode_cntl_0
;
1401 uint32_t pa_sc_mode_cntl_1
;
1402 uint32_t pa_sc_aa_config
;
1403 uint32_t pa_sc_aa_mask
[2];
1404 unsigned num_samples
;
1407 struct radv_prim_vertex_count
{
1412 struct radv_vertex_elements_info
{
1413 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1416 struct radv_ia_multi_vgt_param_helpers
{
1418 bool partial_es_wave
;
1419 uint8_t primgroup_size
;
1420 bool wd_switch_on_eop
;
1421 bool ia_switch_on_eoi
;
1422 bool partial_vs_wave
;
1425 struct radv_binning_state
{
1426 uint32_t pa_sc_binner_cntl_0
;
1427 uint32_t db_dfsm_control
;
1430 #define SI_GS_PER_ES 128
1432 struct radv_pipeline
{
1433 struct radv_device
* device
;
1434 struct radv_dynamic_state dynamic_state
;
1436 struct radv_pipeline_layout
* layout
;
1438 bool need_indirect_descriptor_sets
;
1439 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1440 struct radv_shader_variant
*gs_copy_shader
;
1441 VkShaderStageFlags active_stages
;
1443 struct radeon_cmdbuf cs
;
1444 uint32_t ctx_cs_hash
;
1445 struct radeon_cmdbuf ctx_cs
;
1447 struct radv_vertex_elements_info vertex_elements
;
1449 uint32_t binding_stride
[MAX_VBS
];
1450 uint8_t num_vertex_bindings
;
1452 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1455 struct radv_multisample_state ms
;
1456 struct radv_binning_state binning
;
1457 uint32_t spi_baryc_cntl
;
1458 bool prim_restart_enable
;
1459 unsigned esgs_ring_size
;
1460 unsigned gsvs_ring_size
;
1461 uint32_t vtx_base_sgpr
;
1462 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1463 uint8_t vtx_emit_num
;
1464 struct radv_prim_vertex_count prim_vertex_count
;
1465 bool can_use_guardband
;
1466 uint32_t needed_dynamic_state
;
1467 bool disable_out_of_order_rast_for_occlusion
;
1469 /* Used for rbplus */
1470 uint32_t col_format
;
1471 uint32_t cb_target_mask
;
1476 unsigned scratch_bytes_per_wave
;
1478 /* Not NULL if graphics pipeline uses streamout. */
1479 struct radv_shader_variant
*streamout_shader
;
1482 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1484 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1487 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1489 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1492 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1494 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1496 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1497 gl_shader_stage stage
,
1500 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1501 gl_shader_stage stage
);
1503 struct radv_graphics_pipeline_create_info
{
1505 bool db_depth_clear
;
1506 bool db_stencil_clear
;
1507 bool db_depth_disable_expclear
;
1508 bool db_stencil_disable_expclear
;
1509 bool db_flush_depth_inplace
;
1510 bool db_flush_stencil_inplace
;
1511 bool db_resummarize
;
1512 uint32_t custom_blend_mode
;
1516 radv_graphics_pipeline_create(VkDevice device
,
1517 VkPipelineCache cache
,
1518 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1519 const struct radv_graphics_pipeline_create_info
*extra
,
1520 const VkAllocationCallbacks
*alloc
,
1521 VkPipeline
*pPipeline
);
1523 struct vk_format_description
;
1524 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1525 int first_non_void
);
1526 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1527 int first_non_void
);
1528 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1529 uint32_t radv_translate_colorformat(VkFormat format
);
1530 uint32_t radv_translate_color_numformat(VkFormat format
,
1531 const struct vk_format_description
*desc
,
1532 int first_non_void
);
1533 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1534 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1535 uint32_t radv_translate_dbformat(VkFormat format
);
1536 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1537 const struct vk_format_description
*desc
,
1538 int first_non_void
);
1539 uint32_t radv_translate_tex_numformat(VkFormat format
,
1540 const struct vk_format_description
*desc
,
1541 int first_non_void
);
1542 bool radv_format_pack_clear_color(VkFormat format
,
1543 uint32_t clear_vals
[2],
1544 VkClearColorValue
*value
);
1545 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1546 bool radv_dcc_formats_compatible(VkFormat format1
,
1548 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1550 struct radv_fmask_info
{
1554 unsigned pitch_in_pixels
;
1555 unsigned bank_height
;
1556 unsigned slice_tile_max
;
1557 unsigned tile_mode_index
;
1558 unsigned tile_swizzle
;
1559 uint64_t slice_size
;
1562 struct radv_cmask_info
{
1566 unsigned slice_tile_max
;
1567 unsigned slice_size
;
1571 struct radv_image_plane
{
1573 struct radeon_surf surface
;
1579 /* The original VkFormat provided by the client. This may not match any
1580 * of the actual surface formats.
1583 VkImageAspectFlags aspects
;
1584 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1585 struct ac_surf_info info
;
1586 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1587 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1592 unsigned queue_family_mask
;
1596 /* Set when bound */
1597 struct radeon_winsys_bo
*bo
;
1598 VkDeviceSize offset
;
1599 uint64_t dcc_offset
;
1600 uint64_t htile_offset
;
1601 bool tc_compatible_htile
;
1602 bool tc_compatible_cmask
;
1604 struct radv_fmask_info fmask
;
1605 struct radv_cmask_info cmask
;
1606 uint64_t clear_value_offset
;
1607 uint64_t fce_pred_offset
;
1608 uint64_t dcc_pred_offset
;
1611 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1612 * stored at this offset is UINT_MAX, the driver will emit
1613 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1614 * SET_CONTEXT_REG packet.
1616 uint64_t tc_compat_zrange_offset
;
1618 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1619 VkDeviceMemory owned_memory
;
1621 unsigned plane_count
;
1622 struct radv_image_plane planes
[0];
1625 /* Whether the image has a htile that is known consistent with the contents of
1627 bool radv_layout_has_htile(const struct radv_image
*image
,
1628 VkImageLayout layout
,
1629 unsigned queue_mask
);
1631 /* Whether the image has a htile that is known consistent with the contents of
1632 * the image and is allowed to be in compressed form.
1634 * If this is false reads that don't use the htile should be able to return
1637 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1638 VkImageLayout layout
,
1639 unsigned queue_mask
);
1641 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1642 VkImageLayout layout
,
1643 unsigned queue_mask
);
1645 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1646 VkImageLayout layout
,
1647 unsigned queue_mask
);
1650 * Return whether the image has CMASK metadata for color surfaces.
1653 radv_image_has_cmask(const struct radv_image
*image
)
1655 return image
->cmask
.size
;
1659 * Return whether the image has FMASK metadata for color surfaces.
1662 radv_image_has_fmask(const struct radv_image
*image
)
1664 return image
->fmask
.size
;
1668 * Return whether the image has DCC metadata for color surfaces.
1671 radv_image_has_dcc(const struct radv_image
*image
)
1673 return image
->planes
[0].surface
.dcc_size
;
1677 * Return whether the image is TC-compatible CMASK.
1680 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1682 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1686 * Return whether DCC metadata is enabled for a level.
1689 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1691 return radv_image_has_dcc(image
) &&
1692 level
< image
->planes
[0].surface
.num_dcc_levels
;
1696 * Return whether the image has CB metadata.
1699 radv_image_has_CB_metadata(const struct radv_image
*image
)
1701 return radv_image_has_cmask(image
) ||
1702 radv_image_has_fmask(image
) ||
1703 radv_image_has_dcc(image
);
1707 * Return whether the image has HTILE metadata for depth surfaces.
1710 radv_image_has_htile(const struct radv_image
*image
)
1712 return image
->planes
[0].surface
.htile_size
;
1716 * Return whether HTILE metadata is enabled for a level.
1719 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1721 return radv_image_has_htile(image
) && level
== 0;
1725 * Return whether the image is TC-compatible HTILE.
1728 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1730 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1733 static inline uint64_t
1734 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1735 uint32_t base_level
)
1737 uint64_t va
= radv_buffer_get_va(image
->bo
);
1738 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1742 static inline uint64_t
1743 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1744 uint32_t base_level
)
1746 uint64_t va
= radv_buffer_get_va(image
->bo
);
1747 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1751 static inline uint64_t
1752 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1753 uint32_t base_level
)
1755 uint64_t va
= radv_buffer_get_va(image
->bo
);
1756 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1760 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1762 static inline uint32_t
1763 radv_get_layerCount(const struct radv_image
*image
,
1764 const VkImageSubresourceRange
*range
)
1766 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1767 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1770 static inline uint32_t
1771 radv_get_levelCount(const struct radv_image
*image
,
1772 const VkImageSubresourceRange
*range
)
1774 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1775 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1778 struct radeon_bo_metadata
;
1780 radv_init_metadata(struct radv_device
*device
,
1781 struct radv_image
*image
,
1782 struct radeon_bo_metadata
*metadata
);
1785 radv_image_override_offset_stride(struct radv_device
*device
,
1786 struct radv_image
*image
,
1787 uint64_t offset
, uint32_t stride
);
1789 union radv_descriptor
{
1791 uint32_t plane0_descriptor
[8];
1792 uint32_t fmask_descriptor
[8];
1795 uint32_t plane_descriptors
[3][8];
1799 struct radv_image_view
{
1800 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1801 struct radeon_winsys_bo
*bo
;
1803 VkImageViewType type
;
1804 VkImageAspectFlags aspect_mask
;
1807 bool multiple_planes
;
1808 uint32_t base_layer
;
1809 uint32_t layer_count
;
1811 uint32_t level_count
;
1812 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1814 union radv_descriptor descriptor
;
1816 /* Descriptor for use as a storage image as opposed to a sampled image.
1817 * This has a few differences for cube maps (e.g. type).
1819 union radv_descriptor storage_descriptor
;
1822 struct radv_image_create_info
{
1823 const VkImageCreateInfo
*vk_info
;
1825 bool no_metadata_planes
;
1826 const struct radeon_bo_metadata
*bo_metadata
;
1829 VkResult
radv_image_create(VkDevice _device
,
1830 const struct radv_image_create_info
*info
,
1831 const VkAllocationCallbacks
* alloc
,
1835 radv_image_from_gralloc(VkDevice device_h
,
1836 const VkImageCreateInfo
*base_info
,
1837 const VkNativeBufferANDROID
*gralloc_info
,
1838 const VkAllocationCallbacks
*alloc
,
1839 VkImage
*out_image_h
);
1841 void radv_image_view_init(struct radv_image_view
*view
,
1842 struct radv_device
*device
,
1843 const VkImageViewCreateInfo
* pCreateInfo
);
1845 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
1847 struct radv_sampler_ycbcr_conversion
{
1849 VkSamplerYcbcrModelConversion ycbcr_model
;
1850 VkSamplerYcbcrRange ycbcr_range
;
1851 VkComponentMapping components
;
1852 VkChromaLocation chroma_offsets
[2];
1853 VkFilter chroma_filter
;
1856 struct radv_buffer_view
{
1857 struct radeon_winsys_bo
*bo
;
1859 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1862 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1863 struct radv_device
*device
,
1864 const VkBufferViewCreateInfo
* pCreateInfo
);
1866 static inline struct VkExtent3D
1867 radv_sanitize_image_extent(const VkImageType imageType
,
1868 const struct VkExtent3D imageExtent
)
1870 switch (imageType
) {
1871 case VK_IMAGE_TYPE_1D
:
1872 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1873 case VK_IMAGE_TYPE_2D
:
1874 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1875 case VK_IMAGE_TYPE_3D
:
1878 unreachable("invalid image type");
1882 static inline struct VkOffset3D
1883 radv_sanitize_image_offset(const VkImageType imageType
,
1884 const struct VkOffset3D imageOffset
)
1886 switch (imageType
) {
1887 case VK_IMAGE_TYPE_1D
:
1888 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1889 case VK_IMAGE_TYPE_2D
:
1890 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1891 case VK_IMAGE_TYPE_3D
:
1894 unreachable("invalid image type");
1899 radv_image_extent_compare(const struct radv_image
*image
,
1900 const VkExtent3D
*extent
)
1902 if (extent
->width
!= image
->info
.width
||
1903 extent
->height
!= image
->info
.height
||
1904 extent
->depth
!= image
->info
.depth
)
1909 struct radv_sampler
{
1911 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
1914 struct radv_color_buffer_info
{
1915 uint64_t cb_color_base
;
1916 uint64_t cb_color_cmask
;
1917 uint64_t cb_color_fmask
;
1918 uint64_t cb_dcc_base
;
1919 uint32_t cb_color_slice
;
1920 uint32_t cb_color_view
;
1921 uint32_t cb_color_info
;
1922 uint32_t cb_color_attrib
;
1923 uint32_t cb_color_attrib2
; /* GFX9 and later */
1924 uint32_t cb_color_attrib3
; /* GFX10 and later */
1925 uint32_t cb_dcc_control
;
1926 uint32_t cb_color_cmask_slice
;
1927 uint32_t cb_color_fmask_slice
;
1929 uint32_t cb_color_pitch
; // GFX6-GFX8
1930 uint32_t cb_mrt_epitch
; // GFX9+
1934 struct radv_ds_buffer_info
{
1935 uint64_t db_z_read_base
;
1936 uint64_t db_stencil_read_base
;
1937 uint64_t db_z_write_base
;
1938 uint64_t db_stencil_write_base
;
1939 uint64_t db_htile_data_base
;
1940 uint32_t db_depth_info
;
1942 uint32_t db_stencil_info
;
1943 uint32_t db_depth_view
;
1944 uint32_t db_depth_size
;
1945 uint32_t db_depth_slice
;
1946 uint32_t db_htile_surface
;
1947 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1948 uint32_t db_z_info2
; /* GFX9 only */
1949 uint32_t db_stencil_info2
; /* GFX9 only */
1953 struct radv_attachment_info
{
1955 struct radv_color_buffer_info cb
;
1956 struct radv_ds_buffer_info ds
;
1958 struct radv_image_view
*attachment
;
1961 struct radv_framebuffer
{
1966 uint32_t attachment_count
;
1967 struct radv_attachment_info attachments
[0];
1970 struct radv_subpass_barrier
{
1971 VkPipelineStageFlags src_stage_mask
;
1972 VkAccessFlags src_access_mask
;
1973 VkAccessFlags dst_access_mask
;
1976 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
1977 const struct radv_subpass_barrier
*barrier
);
1979 struct radv_subpass_attachment
{
1980 uint32_t attachment
;
1981 VkImageLayout layout
;
1984 struct radv_subpass
{
1985 uint32_t attachment_count
;
1986 struct radv_subpass_attachment
* attachments
;
1988 uint32_t input_count
;
1989 uint32_t color_count
;
1990 struct radv_subpass_attachment
* input_attachments
;
1991 struct radv_subpass_attachment
* color_attachments
;
1992 struct radv_subpass_attachment
* resolve_attachments
;
1993 struct radv_subpass_attachment
* depth_stencil_attachment
;
1994 struct radv_subpass_attachment
* ds_resolve_attachment
;
1995 VkResolveModeFlagBitsKHR depth_resolve_mode
;
1996 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
1998 /** Subpass has at least one color resolve attachment */
1999 bool has_color_resolve
;
2001 /** Subpass has at least one color attachment */
2004 struct radv_subpass_barrier start_barrier
;
2007 VkSampleCountFlagBits max_sample_count
;
2011 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2013 struct radv_render_pass_attachment
{
2016 VkAttachmentLoadOp load_op
;
2017 VkAttachmentLoadOp stencil_load_op
;
2018 VkImageLayout initial_layout
;
2019 VkImageLayout final_layout
;
2021 /* The subpass id in which the attachment will be used first/last. */
2022 uint32_t first_subpass_idx
;
2023 uint32_t last_subpass_idx
;
2026 struct radv_render_pass
{
2027 uint32_t attachment_count
;
2028 uint32_t subpass_count
;
2029 struct radv_subpass_attachment
* subpass_attachments
;
2030 struct radv_render_pass_attachment
* attachments
;
2031 struct radv_subpass_barrier end_barrier
;
2032 struct radv_subpass subpasses
[0];
2035 VkResult
radv_device_init_meta(struct radv_device
*device
);
2036 void radv_device_finish_meta(struct radv_device
*device
);
2038 struct radv_query_pool
{
2039 struct radeon_winsys_bo
*bo
;
2041 uint32_t availability_offset
;
2045 uint32_t pipeline_stats_mask
;
2048 struct radv_semaphore
{
2049 /* use a winsys sem for non-exportable */
2050 struct radeon_winsys_sem
*sem
;
2052 uint32_t temp_syncobj
;
2055 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2056 VkPipelineBindPoint bind_point
,
2057 struct radv_descriptor_set
*set
,
2061 radv_update_descriptor_sets(struct radv_device
*device
,
2062 struct radv_cmd_buffer
*cmd_buffer
,
2063 VkDescriptorSet overrideSet
,
2064 uint32_t descriptorWriteCount
,
2065 const VkWriteDescriptorSet
*pDescriptorWrites
,
2066 uint32_t descriptorCopyCount
,
2067 const VkCopyDescriptorSet
*pDescriptorCopies
);
2070 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2071 struct radv_cmd_buffer
*cmd_buffer
,
2072 struct radv_descriptor_set
*set
,
2073 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2076 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2077 VkPipelineBindPoint pipelineBindPoint
,
2078 VkPipelineLayout _layout
,
2080 uint32_t descriptorWriteCount
,
2081 const VkWriteDescriptorSet
*pDescriptorWrites
);
2083 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2084 struct radv_image
*image
,
2085 const VkImageSubresourceRange
*range
, uint32_t value
);
2087 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2088 struct radv_image
*image
,
2089 const VkImageSubresourceRange
*range
);
2092 struct radeon_winsys_fence
*fence
;
2093 struct wsi_fence
*fence_wsi
;
2096 uint32_t temp_syncobj
;
2099 /* radv_nir_to_llvm.c */
2100 struct radv_shader_variant_info
;
2101 struct radv_nir_compiler_options
;
2103 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2104 struct nir_shader
*geom_shader
,
2105 struct radv_shader_binary
**rbinary
,
2106 struct radv_shader_variant_info
*shader_info
,
2107 const struct radv_nir_compiler_options
*option
);
2109 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2110 struct radv_shader_binary
**rbinary
,
2111 struct radv_shader_variant_info
*shader_info
,
2112 struct nir_shader
*const *nir
,
2114 const struct radv_nir_compiler_options
*options
);
2116 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2117 gl_shader_stage stage
,
2118 const struct nir_shader
*nir
);
2120 /* radv_shader_info.h */
2121 struct radv_shader_info
;
2123 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2124 const struct radv_nir_compiler_options
*options
,
2125 struct radv_shader_info
*info
);
2127 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2129 struct radeon_winsys_sem
;
2131 uint64_t radv_get_current_time(void);
2133 static inline uint32_t
2134 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2137 case 0: /* GL_POINTS */
2139 case 1: /* GL_LINES */
2140 case 3: /* GL_LINE_STRIP */
2142 case 4: /* GL_TRIANGLES */
2143 case 5: /* GL_TRIANGLE_STRIP */
2145 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2147 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2149 case 7: /* GL_QUADS */
2150 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2157 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2159 static inline struct __radv_type * \
2160 __radv_type ## _from_handle(__VkType _handle) \
2162 return (struct __radv_type *) _handle; \
2165 static inline __VkType \
2166 __radv_type ## _to_handle(struct __radv_type *_obj) \
2168 return (__VkType) _obj; \
2171 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2173 static inline struct __radv_type * \
2174 __radv_type ## _from_handle(__VkType _handle) \
2176 return (struct __radv_type *)(uintptr_t) _handle; \
2179 static inline __VkType \
2180 __radv_type ## _to_handle(struct __radv_type *_obj) \
2182 return (__VkType)(uintptr_t) _obj; \
2185 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2186 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2188 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2189 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2190 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2191 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2192 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2194 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2195 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2196 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2197 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2198 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2199 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2200 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2201 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2202 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2203 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2204 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2205 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2206 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2207 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2208 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2209 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2210 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2211 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2212 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2213 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2214 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2215 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2217 #endif /* RADV_PRIVATE_H */