2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vulkan_android.h>
80 #include <vulkan/vk_icd.h>
81 #include <vulkan/vk_android_native_buffer.h>
83 #include "radv_entrypoints.h"
85 #include "wsi_common.h"
86 #include "wsi_common_display.h"
88 /* Helper to determine if we should compile
89 * any of the Android AHB support.
91 * To actually enable the ext we also need
92 * the necessary kernel support.
94 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
97 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
101 struct gfx10_format
{
102 unsigned img_format
:9;
104 /* Various formats are only supported with workarounds for vertex fetch,
105 * and some 32_32_32 formats are supported natively, but only for buffers
106 * (possibly with some image support, actually, but no filtering). */
110 #include "gfx10_format_table.h"
114 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
121 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
122 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
123 RADV_MEM_TYPE_GTT_CACHED
,
124 RADV_MEM_TYPE_VRAM_UNCACHED
,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
,
127 RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
,
131 enum radv_secure_compile_type
{
132 RADV_SC_TYPE_INIT_SUCCESS
,
133 RADV_SC_TYPE_INIT_FAILURE
,
134 RADV_SC_TYPE_COMPILE_PIPELINE
,
135 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
136 RADV_SC_TYPE_READ_DISK_CACHE
,
137 RADV_SC_TYPE_WRITE_DISK_CACHE
,
138 RADV_SC_TYPE_FORK_DEVICE
,
139 RADV_SC_TYPE_DESTROY_DEVICE
,
143 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
145 static inline uint32_t
146 align_u32(uint32_t v
, uint32_t a
)
148 assert(a
!= 0 && a
== (a
& -a
));
149 return (v
+ a
- 1) & ~(a
- 1);
152 static inline uint32_t
153 align_u32_npot(uint32_t v
, uint32_t a
)
155 return (v
+ a
- 1) / a
* a
;
158 static inline uint64_t
159 align_u64(uint64_t v
, uint64_t a
)
161 assert(a
!= 0 && a
== (a
& -a
));
162 return (v
+ a
- 1) & ~(a
- 1);
165 static inline int32_t
166 align_i32(int32_t v
, int32_t a
)
168 assert(a
!= 0 && a
== (a
& -a
));
169 return (v
+ a
- 1) & ~(a
- 1);
172 /** Alignment must be a power of 2. */
174 radv_is_aligned(uintmax_t n
, uintmax_t a
)
176 assert(a
== (a
& -a
));
177 return (n
& (a
- 1)) == 0;
180 static inline uint32_t
181 round_up_u32(uint32_t v
, uint32_t a
)
183 return (v
+ a
- 1) / a
;
186 static inline uint64_t
187 round_up_u64(uint64_t v
, uint64_t a
)
189 return (v
+ a
- 1) / a
;
192 static inline uint32_t
193 radv_minify(uint32_t n
, uint32_t levels
)
195 if (unlikely(n
== 0))
198 return MAX2(n
>> levels
, 1);
201 radv_clamp_f(float f
, float min
, float max
)
214 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
216 if (*inout_mask
& clear_mask
) {
217 *inout_mask
&= ~clear_mask
;
224 #define for_each_bit(b, dword) \
225 for (uint32_t __dword = (dword); \
226 (b) = __builtin_ffs(__dword) - 1, __dword; \
227 __dword &= ~(1 << (b)))
229 #define typed_memcpy(dest, src, count) ({ \
230 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
231 memcpy((dest), (src), (count) * sizeof(*(src))); \
234 /* Whenever we generate an error, pass it through this function. Useful for
235 * debugging, where we can break on it. Only call at error site, not when
236 * propagating errors. Might be useful to plug in a stack trace here.
239 struct radv_image_view
;
240 struct radv_instance
;
242 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
244 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
245 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
247 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
248 radv_printflike(3, 4);
249 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
250 void radv_loge_v(const char *format
, va_list va
);
251 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
252 void radv_logi_v(const char *format
, va_list va
);
255 * Print a FINISHME message, including its source location.
257 #define radv_finishme(format, ...) \
259 static bool reported = false; \
261 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
266 /* A non-fatal assert. Useful for debugging. */
268 #define radv_assert(x) ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
273 #define radv_assert(x) do {} while(0)
276 #define stub_return(v) \
278 radv_finishme("stub %s", __func__); \
284 radv_finishme("stub %s", __func__); \
288 void *radv_lookup_entrypoint_unchecked(const char *name
);
289 void *radv_lookup_entrypoint_checked(const char *name
,
290 uint32_t core_version
,
291 const struct radv_instance_extension_table
*instance
,
292 const struct radv_device_extension_table
*device
);
293 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
294 uint32_t core_version
,
295 const struct radv_instance_extension_table
*instance
);
297 struct radv_physical_device
{
298 VK_LOADER_DATA _loader_data
;
300 struct radv_instance
* instance
;
302 struct radeon_winsys
*ws
;
303 struct radeon_info rad_info
;
304 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
305 uint8_t driver_uuid
[VK_UUID_SIZE
];
306 uint8_t device_uuid
[VK_UUID_SIZE
];
307 uint8_t cache_uuid
[VK_UUID_SIZE
];
311 struct wsi_device wsi_device
;
313 bool out_of_order_rast_allowed
;
315 /* Whether DCC should be enabled for MSAA textures. */
316 bool dcc_msaa_allowed
;
318 /* Whether to enable the AMD_shader_ballot extension */
319 bool use_shader_ballot
;
321 /* Whether to enable NGG. */
324 /* Whether to enable NGG streamout. */
325 bool use_ngg_streamout
;
327 /* Number of threads per wave. */
328 uint8_t ps_wave_size
;
329 uint8_t cs_wave_size
;
330 uint8_t ge_wave_size
;
332 /* Whether to use the experimental compiler backend */
335 /* This is the drivers on-disk cache used as a fallback as opposed to
336 * the pipeline cache defined by apps.
338 struct disk_cache
* disk_cache
;
340 VkPhysicalDeviceMemoryProperties memory_properties
;
341 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
343 drmPciBusInfo bus_info
;
345 struct radv_device_extension_table supported_extensions
;
348 struct radv_instance
{
349 VK_LOADER_DATA _loader_data
;
351 VkAllocationCallbacks alloc
;
354 int physicalDeviceCount
;
355 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
358 uint32_t engineVersion
;
360 uint64_t debug_flags
;
361 uint64_t perftest_flags
;
362 uint8_t num_sc_threads
;
364 struct vk_debug_report_instance debug_report_callbacks
;
366 struct radv_instance_extension_table enabled_extensions
;
368 struct driOptionCache dri_options
;
369 struct driOptionCache available_dri_options
;
373 bool radv_device_use_secure_compile(struct radv_instance
*instance
)
375 return instance
->num_sc_threads
;
378 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
379 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
381 bool radv_instance_extension_supported(const char *name
);
382 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
383 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
388 struct radv_pipeline_cache
{
389 struct radv_device
* device
;
390 pthread_mutex_t mutex
;
394 uint32_t kernel_count
;
395 struct cache_entry
** hash_table
;
398 VkAllocationCallbacks alloc
;
401 struct radv_pipeline_key
{
402 uint32_t instance_rate_inputs
;
403 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
404 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
405 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
406 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
407 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
408 uint64_t vertex_alpha_adjust
;
409 uint32_t vertex_post_shuffle
;
410 unsigned tess_input_vertices
;
414 uint8_t log2_ps_iter_samples
;
416 uint32_t has_multiview_view_index
: 1;
417 uint32_t optimisations_disabled
: 1;
420 /* Non-zero if a required subgroup size is specified via
421 * VK_EXT_subgroup_size_control.
423 uint8_t compute_subgroup_size
;
426 struct radv_shader_binary
;
427 struct radv_shader_variant
;
430 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
431 struct radv_device
*device
);
433 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
435 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
436 const void *data
, size_t size
);
439 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
440 struct radv_pipeline_cache
*cache
,
441 const unsigned char *sha1
,
442 struct radv_shader_variant
**variants
,
443 bool *found_in_application_cache
);
446 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
447 struct radv_pipeline_cache
*cache
,
448 const unsigned char *sha1
,
449 struct radv_shader_variant
**variants
,
450 struct radv_shader_binary
*const *binaries
);
452 enum radv_blit_ds_layout
{
453 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
454 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
455 RADV_BLIT_DS_LAYOUT_COUNT
,
458 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
460 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
463 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
465 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
468 enum radv_meta_dst_layout
{
469 RADV_META_DST_LAYOUT_GENERAL
,
470 RADV_META_DST_LAYOUT_OPTIMAL
,
471 RADV_META_DST_LAYOUT_COUNT
,
474 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
476 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
479 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
481 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
484 struct radv_meta_state
{
485 VkAllocationCallbacks alloc
;
487 struct radv_pipeline_cache cache
;
490 * For on-demand pipeline creation, makes sure that
491 * only one thread tries to build a pipeline at the same time.
496 * Use array element `i` for images with `2^i` samples.
499 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
500 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
502 VkRenderPass depthstencil_rp
;
503 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
504 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
505 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
507 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
508 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
509 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
510 } clear
[MAX_SAMPLES_LOG2
];
512 VkPipelineLayout clear_color_p_layout
;
513 VkPipelineLayout clear_depth_p_layout
;
514 VkPipelineLayout clear_depth_unrestricted_p_layout
;
516 /* Optimized compute fast HTILE clear for stencil or depth only. */
517 VkPipeline clear_htile_mask_pipeline
;
518 VkPipelineLayout clear_htile_mask_p_layout
;
519 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
522 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
524 /** Pipeline that blits from a 1D image. */
525 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
527 /** Pipeline that blits from a 2D image. */
528 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
530 /** Pipeline that blits from a 3D image. */
531 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
533 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
534 VkPipeline depth_only_1d_pipeline
;
535 VkPipeline depth_only_2d_pipeline
;
536 VkPipeline depth_only_3d_pipeline
;
538 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
539 VkPipeline stencil_only_1d_pipeline
;
540 VkPipeline stencil_only_2d_pipeline
;
541 VkPipeline stencil_only_3d_pipeline
;
542 VkPipelineLayout pipeline_layout
;
543 VkDescriptorSetLayout ds_layout
;
547 VkPipelineLayout p_layouts
[5];
548 VkDescriptorSetLayout ds_layouts
[5];
549 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
551 VkPipeline depth_only_pipeline
[5];
553 VkPipeline stencil_only_pipeline
[5];
554 } blit2d
[MAX_SAMPLES_LOG2
];
556 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
557 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
558 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
561 VkPipelineLayout img_p_layout
;
562 VkDescriptorSetLayout img_ds_layout
;
564 VkPipeline pipeline_3d
;
567 VkPipelineLayout img_p_layout
;
568 VkDescriptorSetLayout img_ds_layout
;
570 VkPipeline pipeline_3d
;
573 VkPipelineLayout img_p_layout
;
574 VkDescriptorSetLayout img_ds_layout
;
578 VkPipelineLayout img_p_layout
;
579 VkDescriptorSetLayout img_ds_layout
;
581 VkPipeline pipeline_3d
;
584 VkPipelineLayout img_p_layout
;
585 VkDescriptorSetLayout img_ds_layout
;
589 VkPipelineLayout img_p_layout
;
590 VkDescriptorSetLayout img_ds_layout
;
592 VkPipeline pipeline_3d
;
595 VkPipelineLayout img_p_layout
;
596 VkDescriptorSetLayout img_ds_layout
;
601 VkPipelineLayout p_layout
;
602 VkPipeline pipeline
[NUM_META_FS_KEYS
];
603 VkRenderPass pass
[NUM_META_FS_KEYS
];
607 VkDescriptorSetLayout ds_layout
;
608 VkPipelineLayout p_layout
;
611 VkPipeline i_pipeline
;
612 VkPipeline srgb_pipeline
;
613 } rc
[MAX_SAMPLES_LOG2
];
615 VkPipeline depth_zero_pipeline
;
617 VkPipeline average_pipeline
;
618 VkPipeline max_pipeline
;
619 VkPipeline min_pipeline
;
620 } depth
[MAX_SAMPLES_LOG2
];
622 VkPipeline stencil_zero_pipeline
;
624 VkPipeline max_pipeline
;
625 VkPipeline min_pipeline
;
626 } stencil
[MAX_SAMPLES_LOG2
];
630 VkDescriptorSetLayout ds_layout
;
631 VkPipelineLayout p_layout
;
634 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
635 VkPipeline pipeline
[NUM_META_FS_KEYS
];
636 } rc
[MAX_SAMPLES_LOG2
];
638 VkRenderPass depth_render_pass
;
639 VkPipeline depth_zero_pipeline
;
641 VkPipeline average_pipeline
;
642 VkPipeline max_pipeline
;
643 VkPipeline min_pipeline
;
644 } depth
[MAX_SAMPLES_LOG2
];
646 VkRenderPass stencil_render_pass
;
647 VkPipeline stencil_zero_pipeline
;
649 VkPipeline max_pipeline
;
650 VkPipeline min_pipeline
;
651 } stencil
[MAX_SAMPLES_LOG2
];
655 VkPipelineLayout p_layout
;
656 VkPipeline decompress_pipeline
[NUM_DEPTH_DECOMPRESS_PIPELINES
];
657 VkPipeline resummarize_pipeline
;
659 } depth_decomp
[MAX_SAMPLES_LOG2
];
662 VkPipelineLayout p_layout
;
663 VkPipeline cmask_eliminate_pipeline
;
664 VkPipeline fmask_decompress_pipeline
;
665 VkPipeline dcc_decompress_pipeline
;
668 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
669 VkPipelineLayout dcc_decompress_compute_p_layout
;
670 VkPipeline dcc_decompress_compute_pipeline
;
674 VkPipelineLayout fill_p_layout
;
675 VkPipelineLayout copy_p_layout
;
676 VkDescriptorSetLayout fill_ds_layout
;
677 VkDescriptorSetLayout copy_ds_layout
;
678 VkPipeline fill_pipeline
;
679 VkPipeline copy_pipeline
;
683 VkDescriptorSetLayout ds_layout
;
684 VkPipelineLayout p_layout
;
685 VkPipeline occlusion_query_pipeline
;
686 VkPipeline pipeline_statistics_query_pipeline
;
687 VkPipeline tfb_query_pipeline
;
688 VkPipeline timestamp_query_pipeline
;
692 VkDescriptorSetLayout ds_layout
;
693 VkPipelineLayout p_layout
;
694 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
699 #define RADV_QUEUE_GENERAL 0
700 #define RADV_QUEUE_COMPUTE 1
701 #define RADV_QUEUE_TRANSFER 2
703 #define RADV_MAX_QUEUE_FAMILIES 3
705 enum ring_type
radv_queue_family_to_ring(int f
);
708 VK_LOADER_DATA _loader_data
;
709 struct radv_device
* device
;
710 struct radeon_winsys_ctx
*hw_ctx
;
711 enum radeon_ctx_priority priority
;
712 uint32_t queue_family_index
;
714 VkDeviceQueueCreateFlags flags
;
716 uint32_t scratch_size_per_wave
;
717 uint32_t scratch_waves
;
718 uint32_t compute_scratch_size_per_wave
;
719 uint32_t compute_scratch_waves
;
720 uint32_t esgs_ring_size
;
721 uint32_t gsvs_ring_size
;
725 bool has_sample_positions
;
727 struct radeon_winsys_bo
*scratch_bo
;
728 struct radeon_winsys_bo
*descriptor_bo
;
729 struct radeon_winsys_bo
*compute_scratch_bo
;
730 struct radeon_winsys_bo
*esgs_ring_bo
;
731 struct radeon_winsys_bo
*gsvs_ring_bo
;
732 struct radeon_winsys_bo
*tess_rings_bo
;
733 struct radeon_winsys_bo
*gds_bo
;
734 struct radeon_winsys_bo
*gds_oa_bo
;
735 struct radeon_cmdbuf
*initial_preamble_cs
;
736 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
737 struct radeon_cmdbuf
*continue_preamble_cs
;
739 struct list_head pending_submissions
;
740 pthread_mutex_t pending_mutex
;
743 struct radv_bo_list
{
744 struct radv_winsys_bo_list list
;
746 pthread_mutex_t mutex
;
749 struct radv_secure_compile_process
{
750 /* Secure process file descriptors. Used to communicate between the
751 * user facing device and the idle forked device used to fork a clean
752 * process for each new pipeline compile.
755 int fd_secure_output
;
757 /* FIFO file descriptors used to communicate between the user facing
758 * device and the secure process that does the actual secure compile.
763 /* Secure compile process id */
766 /* Is the secure compile process currently in use by a thread */
770 struct radv_secure_compile_state
{
771 struct radv_secure_compile_process
*secure_compile_processes
;
772 uint32_t secure_compile_thread_counter
;
773 mtx_t secure_compile_mutex
;
775 /* Unique process ID used to build name for FIFO file descriptor */
780 VK_LOADER_DATA _loader_data
;
782 VkAllocationCallbacks alloc
;
784 struct radv_instance
* instance
;
785 struct radeon_winsys
*ws
;
787 struct radv_meta_state meta_state
;
789 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
790 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
791 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
793 bool always_use_syncobj
;
796 uint32_t tess_offchip_block_dw_size
;
797 uint32_t scratch_waves
;
798 uint32_t dispatch_initiator
;
800 uint32_t gs_table_depth
;
802 /* MSAA sample locations.
803 * The first index is the sample index.
804 * The second index is the coordinate: X, Y. */
805 float sample_locations_1x
[1][2];
806 float sample_locations_2x
[2][2];
807 float sample_locations_4x
[4][2];
808 float sample_locations_8x
[8][2];
811 uint32_t gfx_init_size_dw
;
812 struct radeon_winsys_bo
*gfx_init
;
814 struct radeon_winsys_bo
*trace_bo
;
815 uint32_t *trace_id_ptr
;
817 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
818 bool keep_shader_info
;
820 struct radv_physical_device
*physical_device
;
822 /* Backup in-memory cache to be used if the app doesn't provide one */
823 struct radv_pipeline_cache
* mem_cache
;
826 * use different counters so MSAA MRTs get consecutive surface indices,
827 * even if MASK is allocated in between.
829 uint32_t image_mrt_offset_counter
;
830 uint32_t fmask_mrt_offset_counter
;
831 struct list_head shader_slabs
;
832 mtx_t shader_slab_mutex
;
834 /* For detecting VM faults reported by dmesg. */
835 uint64_t dmesg_timestamp
;
837 struct radv_device_extension_table enabled_extensions
;
839 /* Whether the app has enabled the robustBufferAccess feature. */
840 bool robust_buffer_access
;
842 /* Whether the driver uses a global BO list. */
843 bool use_global_bo_list
;
845 struct radv_bo_list bo_list
;
847 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
850 struct radv_secure_compile_state
*sc_state
;
852 /* Condition variable for legacy timelines, to notify waiters when a
853 * new point gets submitted. */
854 pthread_cond_t timeline_cond
;
857 struct radv_device_memory
{
858 struct radeon_winsys_bo
*bo
;
859 /* for dedicated allocations */
860 struct radv_image
*image
;
861 struct radv_buffer
*buffer
;
863 VkDeviceSize map_size
;
867 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
868 struct AHardwareBuffer
* android_hardware_buffer
;
873 struct radv_descriptor_range
{
878 struct radv_descriptor_set
{
879 const struct radv_descriptor_set_layout
*layout
;
882 struct radeon_winsys_bo
*bo
;
884 uint32_t *mapped_ptr
;
885 struct radv_descriptor_range
*dynamic_descriptors
;
887 struct radeon_winsys_bo
*descriptors
[0];
890 struct radv_push_descriptor_set
892 struct radv_descriptor_set set
;
896 struct radv_descriptor_pool_entry
{
899 struct radv_descriptor_set
*set
;
902 struct radv_descriptor_pool
{
903 struct radeon_winsys_bo
*bo
;
905 uint64_t current_offset
;
908 uint8_t *host_memory_base
;
909 uint8_t *host_memory_ptr
;
910 uint8_t *host_memory_end
;
912 uint32_t entry_count
;
913 uint32_t max_entry_count
;
914 struct radv_descriptor_pool_entry entries
[0];
917 struct radv_descriptor_update_template_entry
{
918 VkDescriptorType descriptor_type
;
920 /* The number of descriptors to update */
921 uint32_t descriptor_count
;
923 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
926 /* In dwords. Not valid/used for dynamic descriptors */
929 uint32_t buffer_offset
;
931 /* Only valid for combined image samplers and samplers */
933 uint8_t sampler_offset
;
939 /* For push descriptors */
940 const uint32_t *immutable_samplers
;
943 struct radv_descriptor_update_template
{
944 uint32_t entry_count
;
945 VkPipelineBindPoint bind_point
;
946 struct radv_descriptor_update_template_entry entry
[0];
952 VkBufferUsageFlags usage
;
953 VkBufferCreateFlags flags
;
956 struct radeon_winsys_bo
* bo
;
962 enum radv_dynamic_state_bits
{
963 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
964 RADV_DYNAMIC_SCISSOR
= 1 << 1,
965 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
966 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
967 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
968 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
969 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
970 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
971 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
972 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
973 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
974 RADV_DYNAMIC_LINE_STIPPLE
= 1 << 11,
975 RADV_DYNAMIC_ALL
= (1 << 12) - 1,
978 enum radv_cmd_dirty_bits
{
979 /* Keep the dynamic state dirty bits in sync with
980 * enum radv_dynamic_state_bits */
981 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
982 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
983 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
984 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
985 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
986 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
987 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
988 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
989 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
990 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
991 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
992 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 11,
993 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 12) - 1,
994 RADV_CMD_DIRTY_PIPELINE
= 1 << 12,
995 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 13,
996 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 14,
997 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 15,
998 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 16,
1001 enum radv_cmd_flush_bits
{
1002 /* Instruction cache. */
1003 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
1004 /* Scalar L1 cache. */
1005 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
1006 /* Vector L1 cache. */
1007 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
1008 /* L2 cache + L2 metadata cache writeback & invalidate.
1009 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1010 RADV_CMD_FLAG_INV_L2
= 1 << 3,
1011 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1012 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1013 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1014 RADV_CMD_FLAG_WB_L2
= 1 << 4,
1015 /* Framebuffer caches */
1016 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
1017 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
1018 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
1019 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
1020 /* Engine synchronization. */
1021 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1022 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1023 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1024 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1025 /* Pipeline query controls. */
1026 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1027 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1028 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1030 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1031 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1032 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1033 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1036 struct radv_vertex_binding
{
1037 struct radv_buffer
* buffer
;
1038 VkDeviceSize offset
;
1041 struct radv_streamout_binding
{
1042 struct radv_buffer
*buffer
;
1043 VkDeviceSize offset
;
1047 struct radv_streamout_state
{
1048 /* Mask of bound streamout buffers. */
1049 uint8_t enabled_mask
;
1051 /* External state that comes from the last vertex stage, it must be
1052 * set explicitely when binding a new graphics pipeline.
1054 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1055 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1057 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1058 uint32_t hw_enabled_mask
;
1060 /* State of VGT_STRMOUT_(CONFIG|EN) */
1061 bool streamout_enabled
;
1064 struct radv_viewport_state
{
1066 VkViewport viewports
[MAX_VIEWPORTS
];
1069 struct radv_scissor_state
{
1071 VkRect2D scissors
[MAX_SCISSORS
];
1074 struct radv_discard_rectangle_state
{
1076 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1079 struct radv_sample_locations_state
{
1080 VkSampleCountFlagBits per_pixel
;
1081 VkExtent2D grid_size
;
1083 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1086 struct radv_dynamic_state
{
1088 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1089 * Defines the set of saved dynamic state.
1093 struct radv_viewport_state viewport
;
1095 struct radv_scissor_state scissor
;
1105 float blend_constants
[4];
1115 } stencil_compare_mask
;
1120 } stencil_write_mask
;
1125 } stencil_reference
;
1127 struct radv_discard_rectangle_state discard_rectangle
;
1129 struct radv_sample_locations_state sample_location
;
1137 extern const struct radv_dynamic_state default_dynamic_state
;
1140 radv_get_debug_option_name(int id
);
1143 radv_get_perftest_option_name(int id
);
1145 struct radv_color_buffer_info
{
1146 uint64_t cb_color_base
;
1147 uint64_t cb_color_cmask
;
1148 uint64_t cb_color_fmask
;
1149 uint64_t cb_dcc_base
;
1150 uint32_t cb_color_slice
;
1151 uint32_t cb_color_view
;
1152 uint32_t cb_color_info
;
1153 uint32_t cb_color_attrib
;
1154 uint32_t cb_color_attrib2
; /* GFX9 and later */
1155 uint32_t cb_color_attrib3
; /* GFX10 and later */
1156 uint32_t cb_dcc_control
;
1157 uint32_t cb_color_cmask_slice
;
1158 uint32_t cb_color_fmask_slice
;
1160 uint32_t cb_color_pitch
; // GFX6-GFX8
1161 uint32_t cb_mrt_epitch
; // GFX9+
1165 struct radv_ds_buffer_info
{
1166 uint64_t db_z_read_base
;
1167 uint64_t db_stencil_read_base
;
1168 uint64_t db_z_write_base
;
1169 uint64_t db_stencil_write_base
;
1170 uint64_t db_htile_data_base
;
1171 uint32_t db_depth_info
;
1173 uint32_t db_stencil_info
;
1174 uint32_t db_depth_view
;
1175 uint32_t db_depth_size
;
1176 uint32_t db_depth_slice
;
1177 uint32_t db_htile_surface
;
1178 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1179 uint32_t db_z_info2
; /* GFX9 only */
1180 uint32_t db_stencil_info2
; /* GFX9 only */
1185 radv_initialise_color_surface(struct radv_device
*device
,
1186 struct radv_color_buffer_info
*cb
,
1187 struct radv_image_view
*iview
);
1189 radv_initialise_ds_surface(struct radv_device
*device
,
1190 struct radv_ds_buffer_info
*ds
,
1191 struct radv_image_view
*iview
);
1194 radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
);
1197 * Attachment state when recording a renderpass instance.
1199 * The clear value is valid only if there exists a pending clear.
1201 struct radv_attachment_state
{
1202 VkImageAspectFlags pending_clear_aspects
;
1203 uint32_t cleared_views
;
1204 VkClearValue clear_value
;
1205 VkImageLayout current_layout
;
1206 VkImageLayout current_stencil_layout
;
1207 bool current_in_render_loop
;
1208 struct radv_sample_locations_state sample_location
;
1211 struct radv_color_buffer_info cb
;
1212 struct radv_ds_buffer_info ds
;
1214 struct radv_image_view
*iview
;
1217 struct radv_descriptor_state
{
1218 struct radv_descriptor_set
*sets
[MAX_SETS
];
1221 struct radv_push_descriptor_set push_set
;
1223 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1226 struct radv_subpass_sample_locs_state
{
1227 uint32_t subpass_idx
;
1228 struct radv_sample_locations_state sample_location
;
1231 struct radv_cmd_state
{
1232 /* Vertex descriptors */
1239 uint32_t prefetch_L2_mask
;
1241 struct radv_pipeline
* pipeline
;
1242 struct radv_pipeline
* emitted_pipeline
;
1243 struct radv_pipeline
* compute_pipeline
;
1244 struct radv_pipeline
* emitted_compute_pipeline
;
1245 struct radv_framebuffer
* framebuffer
;
1246 struct radv_render_pass
* pass
;
1247 const struct radv_subpass
* subpass
;
1248 struct radv_dynamic_state dynamic
;
1249 struct radv_attachment_state
* attachments
;
1250 struct radv_streamout_state streamout
;
1251 VkRect2D render_area
;
1253 uint32_t num_subpass_sample_locs
;
1254 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1257 struct radv_buffer
*index_buffer
;
1258 uint64_t index_offset
;
1259 uint32_t index_type
;
1260 uint32_t max_index_count
;
1262 int32_t last_index_type
;
1264 int32_t last_primitive_reset_en
;
1265 uint32_t last_primitive_reset_index
;
1266 enum radv_cmd_flush_bits flush_bits
;
1267 unsigned active_occlusion_queries
;
1268 bool perfect_occlusion_queries_enabled
;
1269 unsigned active_pipeline_queries
;
1270 unsigned active_pipeline_gds_queries
;
1273 uint32_t last_ia_multi_vgt_param
;
1275 uint32_t last_num_instances
;
1276 uint32_t last_first_instance
;
1277 uint32_t last_vertex_offset
;
1279 uint32_t last_sx_ps_downconvert
;
1280 uint32_t last_sx_blend_opt_epsilon
;
1281 uint32_t last_sx_blend_opt_control
;
1283 /* Whether CP DMA is busy/idle. */
1286 /* Conditional rendering info. */
1287 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1288 uint64_t predication_va
;
1290 /* Inheritance info. */
1291 VkQueryPipelineStatisticFlags inherited_pipeline_statistics
;
1293 bool context_roll_without_scissor_emitted
;
1296 struct radv_cmd_pool
{
1297 VkAllocationCallbacks alloc
;
1298 struct list_head cmd_buffers
;
1299 struct list_head free_cmd_buffers
;
1300 uint32_t queue_family_index
;
1303 struct radv_cmd_buffer_upload
{
1307 struct radeon_winsys_bo
*upload_bo
;
1308 struct list_head list
;
1311 enum radv_cmd_buffer_status
{
1312 RADV_CMD_BUFFER_STATUS_INVALID
,
1313 RADV_CMD_BUFFER_STATUS_INITIAL
,
1314 RADV_CMD_BUFFER_STATUS_RECORDING
,
1315 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1316 RADV_CMD_BUFFER_STATUS_PENDING
,
1319 struct radv_cmd_buffer
{
1320 VK_LOADER_DATA _loader_data
;
1322 struct radv_device
* device
;
1324 struct radv_cmd_pool
* pool
;
1325 struct list_head pool_link
;
1327 VkCommandBufferUsageFlags usage_flags
;
1328 VkCommandBufferLevel level
;
1329 enum radv_cmd_buffer_status status
;
1330 struct radeon_cmdbuf
*cs
;
1331 struct radv_cmd_state state
;
1332 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1333 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1334 uint32_t queue_family_index
;
1336 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1337 VkShaderStageFlags push_constant_stages
;
1338 struct radv_descriptor_set meta_push_descriptors
;
1340 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1342 struct radv_cmd_buffer_upload upload
;
1344 uint32_t scratch_size_per_wave_needed
;
1345 uint32_t scratch_waves_wanted
;
1346 uint32_t compute_scratch_size_per_wave_needed
;
1347 uint32_t compute_scratch_waves_wanted
;
1348 uint32_t esgs_ring_size_needed
;
1349 uint32_t gsvs_ring_size_needed
;
1350 bool tess_rings_needed
;
1351 bool gds_needed
; /* for GFX10 streamout and NGG GS queries */
1352 bool gds_oa_needed
; /* for GFX10 streamout */
1353 bool sample_positions_needed
;
1355 VkResult record_result
;
1357 uint64_t gfx9_fence_va
;
1358 uint32_t gfx9_fence_idx
;
1359 uint64_t gfx9_eop_bug_va
;
1362 * Whether a query pool has been resetted and we have to flush caches.
1364 bool pending_reset_query
;
1367 * Bitmask of pending active query flushes.
1369 enum radv_cmd_flush_bits active_query_flush_bits
;
1373 struct radv_image_view
;
1375 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1377 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1378 struct radeon_cmdbuf
*cs
);
1379 void si_emit_compute(struct radv_physical_device
*physical_device
,
1380 struct radeon_cmdbuf
*cs
);
1382 void cik_create_gfx_config(struct radv_device
*device
);
1384 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1385 int count
, const VkViewport
*viewports
);
1386 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1387 int count
, const VkRect2D
*scissors
,
1388 const VkViewport
*viewports
, bool can_use_guardband
);
1389 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1390 bool instanced_draw
, bool indirect_draw
,
1391 bool count_from_stream_output
,
1392 uint32_t draw_vertex_count
);
1393 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1394 enum chip_class chip_class
,
1396 unsigned event
, unsigned event_flags
,
1397 unsigned dst_sel
, unsigned data_sel
,
1400 uint64_t gfx9_eop_bug_va
);
1402 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1403 uint32_t ref
, uint32_t mask
);
1404 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1405 enum chip_class chip_class
,
1406 uint32_t *fence_ptr
, uint64_t va
,
1408 enum radv_cmd_flush_bits flush_bits
,
1409 uint64_t gfx9_eop_bug_va
);
1410 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1411 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1412 bool inverted
, uint64_t va
);
1413 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1414 uint64_t src_va
, uint64_t dest_va
,
1416 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1418 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1419 uint64_t size
, unsigned value
);
1420 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1422 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1424 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1427 unsigned *out_offset
,
1430 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1431 const struct radv_subpass
*subpass
);
1433 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1434 unsigned size
, unsigned alignmnet
,
1435 const void *data
, unsigned *out_offset
);
1437 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1438 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1439 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1440 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1441 VkImageAspectFlags aspects
,
1442 VkResolveModeFlagBits resolve_mode
);
1443 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1444 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1445 VkImageAspectFlags aspects
,
1446 VkResolveModeFlagBits resolve_mode
);
1447 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1448 unsigned radv_get_default_max_sample_dist(int log_samples
);
1449 void radv_device_init_msaa(struct radv_device
*device
);
1451 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1452 const struct radv_image_view
*iview
,
1453 VkClearDepthStencilValue ds_clear_value
,
1454 VkImageAspectFlags aspects
);
1456 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1457 const struct radv_image_view
*iview
,
1459 uint32_t color_values
[2]);
1461 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1462 struct radv_image
*image
,
1463 const VkImageSubresourceRange
*range
, bool value
);
1465 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1466 struct radv_image
*image
,
1467 const VkImageSubresourceRange
*range
, bool value
);
1469 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1470 struct radeon_winsys_bo
*bo
,
1471 uint64_t offset
, uint64_t size
, uint32_t value
);
1472 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1473 bool radv_get_memory_fd(struct radv_device
*device
,
1474 struct radv_device_memory
*memory
,
1478 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1479 unsigned sh_offset
, unsigned pointer_count
,
1480 bool use_32bit_pointers
)
1482 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1483 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1487 radv_emit_shader_pointer_body(struct radv_device
*device
,
1488 struct radeon_cmdbuf
*cs
,
1489 uint64_t va
, bool use_32bit_pointers
)
1491 radeon_emit(cs
, va
);
1493 if (use_32bit_pointers
) {
1495 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1497 radeon_emit(cs
, va
>> 32);
1502 radv_emit_shader_pointer(struct radv_device
*device
,
1503 struct radeon_cmdbuf
*cs
,
1504 uint32_t sh_offset
, uint64_t va
, bool global
)
1506 bool use_32bit_pointers
= !global
;
1508 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1509 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1512 static inline struct radv_descriptor_state
*
1513 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1514 VkPipelineBindPoint bind_point
)
1516 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1517 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1518 return &cmd_buffer
->descriptors
[bind_point
];
1522 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1524 * Limitations: Can't call normal dispatch functions without binding or rebinding
1525 * the compute pipeline.
1527 void radv_unaligned_dispatch(
1528 struct radv_cmd_buffer
*cmd_buffer
,
1534 struct radeon_winsys_bo
*bo
;
1538 struct radv_shader_module
;
1540 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1541 #define RADV_HASH_SHADER_NO_NGG (1 << 1)
1542 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 2)
1543 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 3)
1544 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 4)
1545 #define RADV_HASH_SHADER_ACO (1 << 5)
1548 radv_hash_shaders(unsigned char *hash
,
1549 const VkPipelineShaderStageCreateInfo
**stages
,
1550 const struct radv_pipeline_layout
*layout
,
1551 const struct radv_pipeline_key
*key
,
1554 static inline gl_shader_stage
1555 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1557 assert(__builtin_popcount(vk_stage
) == 1);
1558 return ffs(vk_stage
) - 1;
1561 static inline VkShaderStageFlagBits
1562 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1564 return (1 << mesa_stage
);
1567 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1569 #define radv_foreach_stage(stage, stage_bits) \
1570 for (gl_shader_stage stage, \
1571 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1572 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1573 __tmp &= ~(1 << (stage)))
1575 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1576 unsigned radv_format_meta_fs_key(VkFormat format
);
1578 struct radv_multisample_state
{
1580 uint32_t pa_sc_line_cntl
;
1581 uint32_t pa_sc_mode_cntl_0
;
1582 uint32_t pa_sc_mode_cntl_1
;
1583 uint32_t pa_sc_aa_config
;
1584 uint32_t pa_sc_aa_mask
[2];
1585 unsigned num_samples
;
1588 struct radv_prim_vertex_count
{
1593 struct radv_vertex_elements_info
{
1594 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1597 struct radv_ia_multi_vgt_param_helpers
{
1599 bool partial_es_wave
;
1600 uint8_t primgroup_size
;
1601 bool wd_switch_on_eop
;
1602 bool ia_switch_on_eoi
;
1603 bool partial_vs_wave
;
1606 struct radv_binning_state
{
1607 uint32_t pa_sc_binner_cntl_0
;
1608 uint32_t db_dfsm_control
;
1611 #define SI_GS_PER_ES 128
1613 struct radv_pipeline
{
1614 struct radv_device
* device
;
1615 struct radv_dynamic_state dynamic_state
;
1617 struct radv_pipeline_layout
* layout
;
1619 bool need_indirect_descriptor_sets
;
1620 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1621 struct radv_shader_variant
*gs_copy_shader
;
1622 VkShaderStageFlags active_stages
;
1624 struct radeon_cmdbuf cs
;
1625 uint32_t ctx_cs_hash
;
1626 struct radeon_cmdbuf ctx_cs
;
1628 struct radv_vertex_elements_info vertex_elements
;
1630 uint32_t binding_stride
[MAX_VBS
];
1631 uint8_t num_vertex_bindings
;
1633 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1636 struct radv_multisample_state ms
;
1637 struct radv_binning_state binning
;
1638 uint32_t spi_baryc_cntl
;
1639 bool prim_restart_enable
;
1640 unsigned esgs_ring_size
;
1641 unsigned gsvs_ring_size
;
1642 uint32_t vtx_base_sgpr
;
1643 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1644 uint8_t vtx_emit_num
;
1645 struct radv_prim_vertex_count prim_vertex_count
;
1646 bool can_use_guardband
;
1647 uint32_t needed_dynamic_state
;
1648 bool disable_out_of_order_rast_for_occlusion
;
1651 /* Used for rbplus */
1652 uint32_t col_format
;
1653 uint32_t cb_target_mask
;
1658 unsigned scratch_bytes_per_wave
;
1660 /* Not NULL if graphics pipeline uses streamout. */
1661 struct radv_shader_variant
*streamout_shader
;
1664 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1666 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1669 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1671 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1674 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1676 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
);
1678 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1680 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1681 gl_shader_stage stage
,
1684 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1685 gl_shader_stage stage
);
1687 struct radv_graphics_pipeline_create_info
{
1689 bool db_depth_clear
;
1690 bool db_stencil_clear
;
1691 bool db_depth_disable_expclear
;
1692 bool db_stencil_disable_expclear
;
1693 bool db_flush_depth_inplace
;
1694 bool db_flush_stencil_inplace
;
1695 bool db_resummarize
;
1696 uint32_t custom_blend_mode
;
1700 radv_graphics_pipeline_create(VkDevice device
,
1701 VkPipelineCache cache
,
1702 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1703 const struct radv_graphics_pipeline_create_info
*extra
,
1704 const VkAllocationCallbacks
*alloc
,
1705 VkPipeline
*pPipeline
);
1707 struct radv_binning_settings
{
1708 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
1709 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
1710 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
1713 struct radv_binning_settings
1714 radv_get_binning_settings(const struct radv_physical_device
*pdev
);
1716 struct vk_format_description
;
1717 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1718 int first_non_void
);
1719 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1720 int first_non_void
);
1721 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1722 uint32_t radv_translate_colorformat(VkFormat format
);
1723 uint32_t radv_translate_color_numformat(VkFormat format
,
1724 const struct vk_format_description
*desc
,
1725 int first_non_void
);
1726 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1727 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1728 uint32_t radv_translate_dbformat(VkFormat format
);
1729 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1730 const struct vk_format_description
*desc
,
1731 int first_non_void
);
1732 uint32_t radv_translate_tex_numformat(VkFormat format
,
1733 const struct vk_format_description
*desc
,
1734 int first_non_void
);
1735 bool radv_format_pack_clear_color(VkFormat format
,
1736 uint32_t clear_vals
[2],
1737 VkClearColorValue
*value
);
1738 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1739 bool radv_dcc_formats_compatible(VkFormat format1
,
1741 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1743 struct radv_image_plane
{
1745 struct radeon_surf surface
;
1751 /* The original VkFormat provided by the client. This may not match any
1752 * of the actual surface formats.
1755 VkImageAspectFlags aspects
;
1756 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1757 struct ac_surf_info info
;
1758 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1759 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1764 unsigned queue_family_mask
;
1768 /* Set when bound */
1769 struct radeon_winsys_bo
*bo
;
1770 VkDeviceSize offset
;
1771 uint64_t dcc_offset
;
1772 uint64_t htile_offset
;
1773 bool tc_compatible_htile
;
1774 bool tc_compatible_cmask
;
1776 uint64_t cmask_offset
;
1777 uint64_t fmask_offset
;
1778 uint64_t clear_value_offset
;
1779 uint64_t fce_pred_offset
;
1780 uint64_t dcc_pred_offset
;
1783 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1784 * stored at this offset is UINT_MAX, the driver will emit
1785 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1786 * SET_CONTEXT_REG packet.
1788 uint64_t tc_compat_zrange_offset
;
1790 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1791 VkDeviceMemory owned_memory
;
1793 unsigned plane_count
;
1794 struct radv_image_plane planes
[0];
1797 /* Whether the image has a htile that is known consistent with the contents of
1799 bool radv_layout_has_htile(const struct radv_image
*image
,
1800 VkImageLayout layout
,
1801 bool in_render_loop
,
1802 unsigned queue_mask
);
1804 /* Whether the image has a htile that is known consistent with the contents of
1805 * the image and is allowed to be in compressed form.
1807 * If this is false reads that don't use the htile should be able to return
1810 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1811 VkImageLayout layout
,
1812 bool in_render_loop
,
1813 unsigned queue_mask
);
1815 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1816 VkImageLayout layout
,
1817 bool in_render_loop
,
1818 unsigned queue_mask
);
1820 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1821 const struct radv_image
*image
,
1822 VkImageLayout layout
,
1823 bool in_render_loop
,
1824 unsigned queue_mask
);
1827 * Return whether the image has CMASK metadata for color surfaces.
1830 radv_image_has_cmask(const struct radv_image
*image
)
1832 return image
->cmask_offset
;
1836 * Return whether the image has FMASK metadata for color surfaces.
1839 radv_image_has_fmask(const struct radv_image
*image
)
1841 return image
->fmask_offset
;
1845 * Return whether the image has DCC metadata for color surfaces.
1848 radv_image_has_dcc(const struct radv_image
*image
)
1850 return image
->planes
[0].surface
.dcc_size
;
1854 * Return whether the image is TC-compatible CMASK.
1857 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1859 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1863 * Return whether DCC metadata is enabled for a level.
1866 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1868 return radv_image_has_dcc(image
) &&
1869 level
< image
->planes
[0].surface
.num_dcc_levels
;
1873 * Return whether the image has CB metadata.
1876 radv_image_has_CB_metadata(const struct radv_image
*image
)
1878 return radv_image_has_cmask(image
) ||
1879 radv_image_has_fmask(image
) ||
1880 radv_image_has_dcc(image
);
1884 * Return whether the image has HTILE metadata for depth surfaces.
1887 radv_image_has_htile(const struct radv_image
*image
)
1889 return image
->planes
[0].surface
.htile_size
;
1893 * Return whether HTILE metadata is enabled for a level.
1896 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1898 return radv_image_has_htile(image
) && level
== 0;
1902 * Return whether the image is TC-compatible HTILE.
1905 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1907 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1910 static inline uint64_t
1911 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1912 uint32_t base_level
)
1914 uint64_t va
= radv_buffer_get_va(image
->bo
);
1915 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1919 static inline uint64_t
1920 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1921 uint32_t base_level
)
1923 uint64_t va
= radv_buffer_get_va(image
->bo
);
1924 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1928 static inline uint64_t
1929 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1930 uint32_t base_level
)
1932 uint64_t va
= radv_buffer_get_va(image
->bo
);
1933 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1937 static inline uint64_t
1938 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1939 uint32_t base_level
)
1941 uint64_t va
= radv_buffer_get_va(image
->bo
);
1942 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1946 static inline uint64_t
1947 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1948 uint32_t base_level
)
1950 uint64_t va
= radv_buffer_get_va(image
->bo
);
1951 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1955 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1957 static inline uint32_t
1958 radv_get_layerCount(const struct radv_image
*image
,
1959 const VkImageSubresourceRange
*range
)
1961 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1962 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1965 static inline uint32_t
1966 radv_get_levelCount(const struct radv_image
*image
,
1967 const VkImageSubresourceRange
*range
)
1969 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1970 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1973 struct radeon_bo_metadata
;
1975 radv_init_metadata(struct radv_device
*device
,
1976 struct radv_image
*image
,
1977 struct radeon_bo_metadata
*metadata
);
1980 radv_image_override_offset_stride(struct radv_device
*device
,
1981 struct radv_image
*image
,
1982 uint64_t offset
, uint32_t stride
);
1984 union radv_descriptor
{
1986 uint32_t plane0_descriptor
[8];
1987 uint32_t fmask_descriptor
[8];
1990 uint32_t plane_descriptors
[3][8];
1994 struct radv_image_view
{
1995 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1996 struct radeon_winsys_bo
*bo
;
1998 VkImageViewType type
;
1999 VkImageAspectFlags aspect_mask
;
2002 bool multiple_planes
;
2003 uint32_t base_layer
;
2004 uint32_t layer_count
;
2006 uint32_t level_count
;
2007 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2009 union radv_descriptor descriptor
;
2011 /* Descriptor for use as a storage image as opposed to a sampled image.
2012 * This has a few differences for cube maps (e.g. type).
2014 union radv_descriptor storage_descriptor
;
2017 struct radv_image_create_info
{
2018 const VkImageCreateInfo
*vk_info
;
2020 bool no_metadata_planes
;
2021 const struct radeon_bo_metadata
*bo_metadata
;
2025 radv_image_create_layout(struct radv_device
*device
,
2026 struct radv_image_create_info create_info
,
2027 struct radv_image
*image
);
2029 VkResult
radv_image_create(VkDevice _device
,
2030 const struct radv_image_create_info
*info
,
2031 const VkAllocationCallbacks
* alloc
,
2034 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
2037 radv_image_from_gralloc(VkDevice device_h
,
2038 const VkImageCreateInfo
*base_info
,
2039 const VkNativeBufferANDROID
*gralloc_info
,
2040 const VkAllocationCallbacks
*alloc
,
2041 VkImage
*out_image_h
);
2043 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
2044 const VkImageUsageFlags vk_usage
);
2046 radv_import_ahb_memory(struct radv_device
*device
,
2047 struct radv_device_memory
*mem
,
2049 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2051 radv_create_ahb_memory(struct radv_device
*device
,
2052 struct radv_device_memory
*mem
,
2054 const VkMemoryAllocateInfo
*pAllocateInfo
);
2057 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2059 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2061 struct radv_image_view_extra_create_info
{
2062 bool disable_compression
;
2065 void radv_image_view_init(struct radv_image_view
*view
,
2066 struct radv_device
*device
,
2067 const VkImageViewCreateInfo
*pCreateInfo
,
2068 const struct radv_image_view_extra_create_info
* extra_create_info
);
2070 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2072 struct radv_sampler_ycbcr_conversion
{
2074 VkSamplerYcbcrModelConversion ycbcr_model
;
2075 VkSamplerYcbcrRange ycbcr_range
;
2076 VkComponentMapping components
;
2077 VkChromaLocation chroma_offsets
[2];
2078 VkFilter chroma_filter
;
2081 struct radv_buffer_view
{
2082 struct radeon_winsys_bo
*bo
;
2084 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2087 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2088 struct radv_device
*device
,
2089 const VkBufferViewCreateInfo
* pCreateInfo
);
2091 static inline struct VkExtent3D
2092 radv_sanitize_image_extent(const VkImageType imageType
,
2093 const struct VkExtent3D imageExtent
)
2095 switch (imageType
) {
2096 case VK_IMAGE_TYPE_1D
:
2097 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2098 case VK_IMAGE_TYPE_2D
:
2099 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2100 case VK_IMAGE_TYPE_3D
:
2103 unreachable("invalid image type");
2107 static inline struct VkOffset3D
2108 radv_sanitize_image_offset(const VkImageType imageType
,
2109 const struct VkOffset3D imageOffset
)
2111 switch (imageType
) {
2112 case VK_IMAGE_TYPE_1D
:
2113 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2114 case VK_IMAGE_TYPE_2D
:
2115 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2116 case VK_IMAGE_TYPE_3D
:
2119 unreachable("invalid image type");
2124 radv_image_extent_compare(const struct radv_image
*image
,
2125 const VkExtent3D
*extent
)
2127 if (extent
->width
!= image
->info
.width
||
2128 extent
->height
!= image
->info
.height
||
2129 extent
->depth
!= image
->info
.depth
)
2134 struct radv_sampler
{
2136 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2139 struct radv_framebuffer
{
2144 uint32_t attachment_count
;
2145 struct radv_image_view
*attachments
[0];
2148 struct radv_subpass_barrier
{
2149 VkPipelineStageFlags src_stage_mask
;
2150 VkAccessFlags src_access_mask
;
2151 VkAccessFlags dst_access_mask
;
2154 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2155 const struct radv_subpass_barrier
*barrier
);
2157 struct radv_subpass_attachment
{
2158 uint32_t attachment
;
2159 VkImageLayout layout
;
2160 VkImageLayout stencil_layout
;
2161 bool in_render_loop
;
2164 struct radv_subpass
{
2165 uint32_t attachment_count
;
2166 struct radv_subpass_attachment
* attachments
;
2168 uint32_t input_count
;
2169 uint32_t color_count
;
2170 struct radv_subpass_attachment
* input_attachments
;
2171 struct radv_subpass_attachment
* color_attachments
;
2172 struct radv_subpass_attachment
* resolve_attachments
;
2173 struct radv_subpass_attachment
* depth_stencil_attachment
;
2174 struct radv_subpass_attachment
* ds_resolve_attachment
;
2175 VkResolveModeFlagBits depth_resolve_mode
;
2176 VkResolveModeFlagBits stencil_resolve_mode
;
2178 /** Subpass has at least one color resolve attachment */
2179 bool has_color_resolve
;
2181 /** Subpass has at least one color attachment */
2184 struct radv_subpass_barrier start_barrier
;
2188 VkSampleCountFlagBits color_sample_count
;
2189 VkSampleCountFlagBits depth_sample_count
;
2190 VkSampleCountFlagBits max_sample_count
;
2194 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2196 struct radv_render_pass_attachment
{
2199 VkAttachmentLoadOp load_op
;
2200 VkAttachmentLoadOp stencil_load_op
;
2201 VkImageLayout initial_layout
;
2202 VkImageLayout final_layout
;
2203 VkImageLayout stencil_initial_layout
;
2204 VkImageLayout stencil_final_layout
;
2206 /* The subpass id in which the attachment will be used first/last. */
2207 uint32_t first_subpass_idx
;
2208 uint32_t last_subpass_idx
;
2211 struct radv_render_pass
{
2212 uint32_t attachment_count
;
2213 uint32_t subpass_count
;
2214 struct radv_subpass_attachment
* subpass_attachments
;
2215 struct radv_render_pass_attachment
* attachments
;
2216 struct radv_subpass_barrier end_barrier
;
2217 struct radv_subpass subpasses
[0];
2220 VkResult
radv_device_init_meta(struct radv_device
*device
);
2221 void radv_device_finish_meta(struct radv_device
*device
);
2223 struct radv_query_pool
{
2224 struct radeon_winsys_bo
*bo
;
2226 uint32_t availability_offset
;
2230 uint32_t pipeline_stats_mask
;
2234 RADV_SEMAPHORE_NONE
,
2235 RADV_SEMAPHORE_WINSYS
,
2236 RADV_SEMAPHORE_SYNCOBJ
,
2237 RADV_SEMAPHORE_TIMELINE
,
2238 } radv_semaphore_kind
;
2240 struct radv_deferred_queue_submission
;
2242 struct radv_timeline_waiter
{
2243 struct list_head list
;
2244 struct radv_deferred_queue_submission
*submission
;
2248 struct radv_timeline_point
{
2249 struct list_head list
;
2254 /* Separate from the list to accomodate CPU wait being async, as well
2255 * as prevent point deletion during submission. */
2256 unsigned wait_count
;
2259 struct radv_timeline
{
2260 /* Using a pthread mutex to be compatible with condition variables. */
2261 pthread_mutex_t mutex
;
2263 uint64_t highest_signaled
;
2264 uint64_t highest_submitted
;
2266 struct list_head points
;
2268 /* Keep free points on hand so we do not have to recreate syncobjs all
2270 struct list_head free_points
;
2272 /* Submissions that are deferred waiting for a specific value to be
2274 struct list_head waiters
;
2277 struct radv_semaphore_part
{
2278 radv_semaphore_kind kind
;
2281 struct radeon_winsys_sem
*ws_sem
;
2282 struct radv_timeline timeline
;
2286 struct radv_semaphore
{
2287 struct radv_semaphore_part permanent
;
2288 struct radv_semaphore_part temporary
;
2291 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2292 VkPipelineBindPoint bind_point
,
2293 struct radv_descriptor_set
*set
,
2297 radv_update_descriptor_sets(struct radv_device
*device
,
2298 struct radv_cmd_buffer
*cmd_buffer
,
2299 VkDescriptorSet overrideSet
,
2300 uint32_t descriptorWriteCount
,
2301 const VkWriteDescriptorSet
*pDescriptorWrites
,
2302 uint32_t descriptorCopyCount
,
2303 const VkCopyDescriptorSet
*pDescriptorCopies
);
2306 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2307 struct radv_cmd_buffer
*cmd_buffer
,
2308 struct radv_descriptor_set
*set
,
2309 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2312 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2313 VkPipelineBindPoint pipelineBindPoint
,
2314 VkPipelineLayout _layout
,
2316 uint32_t descriptorWriteCount
,
2317 const VkWriteDescriptorSet
*pDescriptorWrites
);
2319 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2320 struct radv_image
*image
,
2321 const VkImageSubresourceRange
*range
, uint32_t value
);
2323 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2324 struct radv_image
*image
,
2325 const VkImageSubresourceRange
*range
);
2328 struct radeon_winsys_fence
*fence
;
2329 struct wsi_fence
*fence_wsi
;
2332 uint32_t temp_syncobj
;
2335 /* radv_nir_to_llvm.c */
2336 struct radv_shader_args
;
2338 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2339 struct nir_shader
*geom_shader
,
2340 struct radv_shader_binary
**rbinary
,
2341 const struct radv_shader_args
*args
);
2343 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2344 struct radv_shader_binary
**rbinary
,
2345 const struct radv_shader_args
*args
,
2346 struct nir_shader
*const *nir
,
2349 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2350 gl_shader_stage stage
,
2351 const struct nir_shader
*nir
);
2353 /* radv_shader_info.h */
2354 struct radv_shader_info
;
2355 struct radv_shader_variant_key
;
2357 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2358 const struct radv_pipeline_layout
*layout
,
2359 const struct radv_shader_variant_key
*key
,
2360 struct radv_shader_info
*info
);
2362 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2364 struct radeon_winsys_sem
;
2366 uint64_t radv_get_current_time(void);
2368 static inline uint32_t
2369 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2372 case 0: /* GL_POINTS */
2374 case 1: /* GL_LINES */
2375 case 3: /* GL_LINE_STRIP */
2377 case 4: /* GL_TRIANGLES */
2378 case 5: /* GL_TRIANGLE_STRIP */
2380 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2382 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2384 case 7: /* GL_QUADS */
2385 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2392 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2394 static inline struct __radv_type * \
2395 __radv_type ## _from_handle(__VkType _handle) \
2397 return (struct __radv_type *) _handle; \
2400 static inline __VkType \
2401 __radv_type ## _to_handle(struct __radv_type *_obj) \
2403 return (__VkType) _obj; \
2406 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2408 static inline struct __radv_type * \
2409 __radv_type ## _from_handle(__VkType _handle) \
2411 return (struct __radv_type *)(uintptr_t) _handle; \
2414 static inline __VkType \
2415 __radv_type ## _to_handle(struct __radv_type *_obj) \
2417 return (__VkType)(uintptr_t) _obj; \
2420 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2421 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2423 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2424 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2425 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2426 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2427 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2429 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2430 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2431 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2432 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2433 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2434 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2435 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2436 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2437 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2438 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2439 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2440 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2441 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2442 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2443 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2444 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2445 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2446 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2447 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2448 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2449 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2450 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2452 #endif /* RADV_PRIVATE_H */