2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
53 #include "vk_debug_report.h"
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
66 #include <llvm-c/TargetMachine.h>
68 /* Pre-declarations needed for WSI entrypoints */
71 typedef struct xcb_connection_t xcb_connection_t
;
72 typedef uint32_t xcb_visualid_t
;
73 typedef uint32_t xcb_window_t
;
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
80 #include "radv_entrypoints.h"
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
85 #define ATI_VENDOR_ID 0x1002
88 #define MAX_VERTEX_ATTRIBS 32
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 13
100 #define RADV_MAX_DRM_DEVICES 8
103 #define NUM_DEPTH_CLEAR_PIPELINES 3
106 * This is the point we switch from using CP to compute shader
107 * for certain buffer operations.
109 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
120 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
121 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
122 RADV_MEM_TYPE_GTT_CACHED
,
126 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
128 static inline uint32_t
129 align_u32(uint32_t v
, uint32_t a
)
131 assert(a
!= 0 && a
== (a
& -a
));
132 return (v
+ a
- 1) & ~(a
- 1);
135 static inline uint32_t
136 align_u32_npot(uint32_t v
, uint32_t a
)
138 return (v
+ a
- 1) / a
* a
;
141 static inline uint64_t
142 align_u64(uint64_t v
, uint64_t a
)
144 assert(a
!= 0 && a
== (a
& -a
));
145 return (v
+ a
- 1) & ~(a
- 1);
148 static inline int32_t
149 align_i32(int32_t v
, int32_t a
)
151 assert(a
!= 0 && a
== (a
& -a
));
152 return (v
+ a
- 1) & ~(a
- 1);
155 /** Alignment must be a power of 2. */
157 radv_is_aligned(uintmax_t n
, uintmax_t a
)
159 assert(a
== (a
& -a
));
160 return (n
& (a
- 1)) == 0;
163 static inline uint32_t
164 round_up_u32(uint32_t v
, uint32_t a
)
166 return (v
+ a
- 1) / a
;
169 static inline uint64_t
170 round_up_u64(uint64_t v
, uint64_t a
)
172 return (v
+ a
- 1) / a
;
175 static inline uint32_t
176 radv_minify(uint32_t n
, uint32_t levels
)
178 if (unlikely(n
== 0))
181 return MAX2(n
>> levels
, 1);
184 radv_clamp_f(float f
, float min
, float max
)
197 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
199 if (*inout_mask
& clear_mask
) {
200 *inout_mask
&= ~clear_mask
;
207 #define for_each_bit(b, dword) \
208 for (uint32_t __dword = (dword); \
209 (b) = __builtin_ffs(__dword) - 1, __dword; \
210 __dword &= ~(1 << (b)))
212 #define typed_memcpy(dest, src, count) ({ \
213 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
214 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 /* Whenever we generate an error, pass it through this function. Useful for
218 * debugging, where we can break on it. Only call at error site, not when
219 * propagating errors. Might be useful to plug in a stack trace here.
222 struct radv_instance
;
224 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
226 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
227 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
229 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
230 radv_printflike(3, 4);
231 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
232 void radv_loge_v(const char *format
, va_list va
);
233 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
234 void radv_logi_v(const char *format
, va_list va
);
237 * Print a FINISHME message, including its source location.
239 #define radv_finishme(format, ...) \
241 static bool reported = false; \
243 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
248 /* A non-fatal assert. Useful for debugging. */
250 #define radv_assert(x) ({ \
251 if (unlikely(!(x))) \
252 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
255 #define radv_assert(x)
258 #define stub_return(v) \
260 radv_finishme("stub %s", __func__); \
266 radv_finishme("stub %s", __func__); \
270 void *radv_lookup_entrypoint_unchecked(const char *name
);
271 void *radv_lookup_entrypoint_checked(const char *name
,
272 uint32_t core_version
,
273 const struct radv_instance_extension_table
*instance
,
274 const struct radv_device_extension_table
*device
);
276 struct radv_physical_device
{
277 VK_LOADER_DATA _loader_data
;
279 struct radv_instance
* instance
;
281 struct radeon_winsys
*ws
;
282 struct radeon_info rad_info
;
284 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
285 uint8_t driver_uuid
[VK_UUID_SIZE
];
286 uint8_t device_uuid
[VK_UUID_SIZE
];
287 uint8_t cache_uuid
[VK_UUID_SIZE
];
291 struct wsi_device wsi_device
;
293 bool has_rbplus
; /* if RB+ register exist */
294 bool rbplus_allowed
; /* if RB+ is allowed */
295 bool has_clear_state
;
296 bool cpdma_prefetch_writes_memory
;
297 bool has_scissor_bug
;
299 bool has_out_of_order_rast
;
300 bool out_of_order_rast_allowed
;
302 /* Whether DCC should be enabled for MSAA textures. */
303 bool dcc_msaa_allowed
;
305 /* This is the drivers on-disk cache used as a fallback as opposed to
306 * the pipeline cache defined by apps.
308 struct disk_cache
* disk_cache
;
310 VkPhysicalDeviceMemoryProperties memory_properties
;
311 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
313 struct radv_device_extension_table supported_extensions
;
316 struct radv_instance
{
317 VK_LOADER_DATA _loader_data
;
319 VkAllocationCallbacks alloc
;
322 int physicalDeviceCount
;
323 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
325 uint64_t debug_flags
;
326 uint64_t perftest_flags
;
328 struct vk_debug_report_instance debug_report_callbacks
;
330 struct radv_instance_extension_table enabled_extensions
;
333 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
334 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
336 bool radv_instance_extension_supported(const char *name
);
337 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
338 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
343 struct radv_pipeline_cache
{
344 struct radv_device
* device
;
345 pthread_mutex_t mutex
;
349 uint32_t kernel_count
;
350 struct cache_entry
** hash_table
;
353 VkAllocationCallbacks alloc
;
356 struct radv_pipeline_key
{
357 uint32_t instance_rate_inputs
;
358 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
359 uint64_t vertex_alpha_adjust
;
360 unsigned tess_input_vertices
;
364 uint8_t log2_ps_iter_samples
;
366 uint32_t has_multiview_view_index
: 1;
367 uint32_t optimisations_disabled
: 1;
371 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
372 struct radv_device
*device
);
374 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
376 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
377 const void *data
, size_t size
);
379 struct radv_shader_variant
;
382 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
383 struct radv_pipeline_cache
*cache
,
384 const unsigned char *sha1
,
385 struct radv_shader_variant
**variants
);
388 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
389 struct radv_pipeline_cache
*cache
,
390 const unsigned char *sha1
,
391 struct radv_shader_variant
**variants
,
392 const void *const *codes
,
393 const unsigned *code_sizes
);
395 enum radv_blit_ds_layout
{
396 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
397 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
398 RADV_BLIT_DS_LAYOUT_COUNT
,
401 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
403 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
406 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
408 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
411 enum radv_meta_dst_layout
{
412 RADV_META_DST_LAYOUT_GENERAL
,
413 RADV_META_DST_LAYOUT_OPTIMAL
,
414 RADV_META_DST_LAYOUT_COUNT
,
417 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
419 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
422 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
424 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
427 struct radv_meta_state
{
428 VkAllocationCallbacks alloc
;
430 struct radv_pipeline_cache cache
;
433 * Use array element `i` for images with `2^i` samples.
436 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
437 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
439 VkRenderPass depthstencil_rp
;
440 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
441 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
442 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
443 } clear
[1 + MAX_SAMPLES_LOG2
];
445 VkPipelineLayout clear_color_p_layout
;
446 VkPipelineLayout clear_depth_p_layout
;
448 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
450 /** Pipeline that blits from a 1D image. */
451 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
453 /** Pipeline that blits from a 2D image. */
454 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
456 /** Pipeline that blits from a 3D image. */
457 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
459 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
460 VkPipeline depth_only_1d_pipeline
;
461 VkPipeline depth_only_2d_pipeline
;
462 VkPipeline depth_only_3d_pipeline
;
464 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
465 VkPipeline stencil_only_1d_pipeline
;
466 VkPipeline stencil_only_2d_pipeline
;
467 VkPipeline stencil_only_3d_pipeline
;
468 VkPipelineLayout pipeline_layout
;
469 VkDescriptorSetLayout ds_layout
;
473 VkPipelineLayout p_layouts
[5];
474 VkDescriptorSetLayout ds_layouts
[5];
475 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
477 VkPipeline depth_only_pipeline
[5];
479 VkPipeline stencil_only_pipeline
[5];
480 } blit2d
[1 + MAX_SAMPLES_LOG2
];
482 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
483 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
484 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
487 VkPipelineLayout img_p_layout
;
488 VkDescriptorSetLayout img_ds_layout
;
490 VkPipeline pipeline_3d
;
493 VkPipelineLayout img_p_layout
;
494 VkDescriptorSetLayout img_ds_layout
;
496 VkPipeline pipeline_3d
;
499 VkPipelineLayout img_p_layout
;
500 VkDescriptorSetLayout img_ds_layout
;
502 VkPipeline pipeline_3d
;
505 VkPipelineLayout img_p_layout
;
506 VkDescriptorSetLayout img_ds_layout
;
508 VkPipeline pipeline_3d
;
512 VkPipelineLayout p_layout
;
513 VkPipeline pipeline
[NUM_META_FS_KEYS
];
514 VkRenderPass pass
[NUM_META_FS_KEYS
];
518 VkDescriptorSetLayout ds_layout
;
519 VkPipelineLayout p_layout
;
522 VkPipeline i_pipeline
;
523 VkPipeline srgb_pipeline
;
524 } rc
[MAX_SAMPLES_LOG2
];
528 VkDescriptorSetLayout ds_layout
;
529 VkPipelineLayout p_layout
;
532 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
533 VkPipeline pipeline
[NUM_META_FS_KEYS
];
534 } rc
[MAX_SAMPLES_LOG2
];
538 VkPipelineLayout p_layout
;
539 VkPipeline decompress_pipeline
;
540 VkPipeline resummarize_pipeline
;
542 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
545 VkPipelineLayout p_layout
;
546 VkPipeline cmask_eliminate_pipeline
;
547 VkPipeline fmask_decompress_pipeline
;
548 VkPipeline dcc_decompress_pipeline
;
551 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
552 VkPipelineLayout dcc_decompress_compute_p_layout
;
553 VkPipeline dcc_decompress_compute_pipeline
;
557 VkPipelineLayout fill_p_layout
;
558 VkPipelineLayout copy_p_layout
;
559 VkDescriptorSetLayout fill_ds_layout
;
560 VkDescriptorSetLayout copy_ds_layout
;
561 VkPipeline fill_pipeline
;
562 VkPipeline copy_pipeline
;
566 VkDescriptorSetLayout ds_layout
;
567 VkPipelineLayout p_layout
;
568 VkPipeline occlusion_query_pipeline
;
569 VkPipeline pipeline_statistics_query_pipeline
;
574 #define RADV_QUEUE_GENERAL 0
575 #define RADV_QUEUE_COMPUTE 1
576 #define RADV_QUEUE_TRANSFER 2
578 #define RADV_MAX_QUEUE_FAMILIES 3
580 enum ring_type
radv_queue_family_to_ring(int f
);
583 VK_LOADER_DATA _loader_data
;
584 struct radv_device
* device
;
585 struct radeon_winsys_ctx
*hw_ctx
;
586 enum radeon_ctx_priority priority
;
587 uint32_t queue_family_index
;
589 VkDeviceQueueCreateFlags flags
;
591 uint32_t scratch_size
;
592 uint32_t compute_scratch_size
;
593 uint32_t esgs_ring_size
;
594 uint32_t gsvs_ring_size
;
596 bool has_sample_positions
;
598 struct radeon_winsys_bo
*scratch_bo
;
599 struct radeon_winsys_bo
*descriptor_bo
;
600 struct radeon_winsys_bo
*compute_scratch_bo
;
601 struct radeon_winsys_bo
*esgs_ring_bo
;
602 struct radeon_winsys_bo
*gsvs_ring_bo
;
603 struct radeon_winsys_bo
*tess_rings_bo
;
604 struct radeon_cmdbuf
*initial_preamble_cs
;
605 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
606 struct radeon_cmdbuf
*continue_preamble_cs
;
609 struct radv_bo_list
{
610 struct radv_winsys_bo_list list
;
612 pthread_mutex_t mutex
;
616 VK_LOADER_DATA _loader_data
;
618 VkAllocationCallbacks alloc
;
620 struct radv_instance
* instance
;
621 struct radeon_winsys
*ws
;
623 struct radv_meta_state meta_state
;
625 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
626 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
627 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
629 bool always_use_syncobj
;
630 bool has_distributed_tess
;
633 uint32_t tess_offchip_block_dw_size
;
634 uint32_t scratch_waves
;
635 uint32_t dispatch_initiator
;
637 uint32_t gs_table_depth
;
639 /* MSAA sample locations.
640 * The first index is the sample index.
641 * The second index is the coordinate: X, Y. */
642 float sample_locations_1x
[1][2];
643 float sample_locations_2x
[2][2];
644 float sample_locations_4x
[4][2];
645 float sample_locations_8x
[8][2];
646 float sample_locations_16x
[16][2];
649 uint32_t gfx_init_size_dw
;
650 struct radeon_winsys_bo
*gfx_init
;
652 struct radeon_winsys_bo
*trace_bo
;
653 uint32_t *trace_id_ptr
;
655 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
656 bool keep_shader_info
;
658 struct radv_physical_device
*physical_device
;
660 /* Backup in-memory cache to be used if the app doesn't provide one */
661 struct radv_pipeline_cache
* mem_cache
;
664 * use different counters so MSAA MRTs get consecutive surface indices,
665 * even if MASK is allocated in between.
667 uint32_t image_mrt_offset_counter
;
668 uint32_t fmask_mrt_offset_counter
;
669 struct list_head shader_slabs
;
670 mtx_t shader_slab_mutex
;
672 /* For detecting VM faults reported by dmesg. */
673 uint64_t dmesg_timestamp
;
675 struct radv_device_extension_table enabled_extensions
;
677 /* Whether the driver uses a global BO list. */
678 bool use_global_bo_list
;
680 struct radv_bo_list bo_list
;
683 struct radv_device_memory
{
684 struct radeon_winsys_bo
*bo
;
685 /* for dedicated allocations */
686 struct radv_image
*image
;
687 struct radv_buffer
*buffer
;
689 VkDeviceSize map_size
;
695 struct radv_descriptor_range
{
700 struct radv_descriptor_set
{
701 const struct radv_descriptor_set_layout
*layout
;
704 struct radeon_winsys_bo
*bo
;
706 uint32_t *mapped_ptr
;
707 struct radv_descriptor_range
*dynamic_descriptors
;
709 struct radeon_winsys_bo
*descriptors
[0];
712 struct radv_push_descriptor_set
714 struct radv_descriptor_set set
;
718 struct radv_descriptor_pool_entry
{
721 struct radv_descriptor_set
*set
;
724 struct radv_descriptor_pool
{
725 struct radeon_winsys_bo
*bo
;
727 uint64_t current_offset
;
730 uint8_t *host_memory_base
;
731 uint8_t *host_memory_ptr
;
732 uint8_t *host_memory_end
;
734 uint32_t entry_count
;
735 uint32_t max_entry_count
;
736 struct radv_descriptor_pool_entry entries
[0];
739 struct radv_descriptor_update_template_entry
{
740 VkDescriptorType descriptor_type
;
742 /* The number of descriptors to update */
743 uint32_t descriptor_count
;
745 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
748 /* In dwords. Not valid/used for dynamic descriptors */
751 uint32_t buffer_offset
;
753 /* Only valid for combined image samplers and samplers */
754 uint16_t has_sampler
;
760 /* For push descriptors */
761 const uint32_t *immutable_samplers
;
764 struct radv_descriptor_update_template
{
765 uint32_t entry_count
;
766 VkPipelineBindPoint bind_point
;
767 struct radv_descriptor_update_template_entry entry
[0];
773 VkBufferUsageFlags usage
;
774 VkBufferCreateFlags flags
;
777 struct radeon_winsys_bo
* bo
;
783 enum radv_dynamic_state_bits
{
784 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
785 RADV_DYNAMIC_SCISSOR
= 1 << 1,
786 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
787 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
788 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
789 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
790 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
791 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
792 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
793 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
794 RADV_DYNAMIC_ALL
= (1 << 10) - 1,
797 enum radv_cmd_dirty_bits
{
798 /* Keep the dynamic state dirty bits in sync with
799 * enum radv_dynamic_state_bits */
800 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
801 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
802 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
803 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
804 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
805 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
806 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
807 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
808 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
809 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
810 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 10) - 1,
811 RADV_CMD_DIRTY_PIPELINE
= 1 << 10,
812 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 11,
813 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 12,
814 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 13,
817 enum radv_cmd_flush_bits
{
818 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
819 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
820 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
821 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
822 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
823 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
824 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
825 /* Same as above, but only writes back and doesn't invalidate */
826 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
827 /* Framebuffer caches */
828 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
829 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
830 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
831 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
832 /* Engine synchronization. */
833 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
834 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
835 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
836 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
837 /* Pipeline query controls. */
838 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
839 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
841 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
842 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
843 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
844 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
847 struct radv_vertex_binding
{
848 struct radv_buffer
* buffer
;
852 struct radv_viewport_state
{
854 VkViewport viewports
[MAX_VIEWPORTS
];
857 struct radv_scissor_state
{
859 VkRect2D scissors
[MAX_SCISSORS
];
862 struct radv_discard_rectangle_state
{
864 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
867 struct radv_dynamic_state
{
869 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
870 * Defines the set of saved dynamic state.
874 struct radv_viewport_state viewport
;
876 struct radv_scissor_state scissor
;
886 float blend_constants
[4];
896 } stencil_compare_mask
;
901 } stencil_write_mask
;
908 struct radv_discard_rectangle_state discard_rectangle
;
911 extern const struct radv_dynamic_state default_dynamic_state
;
914 radv_get_debug_option_name(int id
);
917 radv_get_perftest_option_name(int id
);
920 * Attachment state when recording a renderpass instance.
922 * The clear value is valid only if there exists a pending clear.
924 struct radv_attachment_state
{
925 VkImageAspectFlags pending_clear_aspects
;
926 uint32_t cleared_views
;
927 VkClearValue clear_value
;
928 VkImageLayout current_layout
;
931 struct radv_descriptor_state
{
932 struct radv_descriptor_set
*sets
[MAX_SETS
];
935 struct radv_push_descriptor_set push_set
;
937 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
940 struct radv_cmd_state
{
941 /* Vertex descriptors */
948 uint32_t prefetch_L2_mask
;
950 struct radv_pipeline
* pipeline
;
951 struct radv_pipeline
* emitted_pipeline
;
952 struct radv_pipeline
* compute_pipeline
;
953 struct radv_pipeline
* emitted_compute_pipeline
;
954 struct radv_framebuffer
* framebuffer
;
955 struct radv_render_pass
* pass
;
956 const struct radv_subpass
* subpass
;
957 struct radv_dynamic_state dynamic
;
958 struct radv_attachment_state
* attachments
;
959 VkRect2D render_area
;
962 struct radv_buffer
*index_buffer
;
963 uint64_t index_offset
;
965 uint32_t max_index_count
;
967 int32_t last_index_type
;
969 int32_t last_primitive_reset_en
;
970 uint32_t last_primitive_reset_index
;
971 enum radv_cmd_flush_bits flush_bits
;
972 unsigned active_occlusion_queries
;
973 bool perfect_occlusion_queries_enabled
;
974 unsigned active_pipeline_queries
;
977 uint32_t last_ia_multi_vgt_param
;
979 uint32_t last_num_instances
;
980 uint32_t last_first_instance
;
981 uint32_t last_vertex_offset
;
983 /* Whether CP DMA is busy/idle. */
987 struct radv_cmd_pool
{
988 VkAllocationCallbacks alloc
;
989 struct list_head cmd_buffers
;
990 struct list_head free_cmd_buffers
;
991 uint32_t queue_family_index
;
994 struct radv_cmd_buffer_upload
{
998 struct radeon_winsys_bo
*upload_bo
;
999 struct list_head list
;
1002 enum radv_cmd_buffer_status
{
1003 RADV_CMD_BUFFER_STATUS_INVALID
,
1004 RADV_CMD_BUFFER_STATUS_INITIAL
,
1005 RADV_CMD_BUFFER_STATUS_RECORDING
,
1006 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1007 RADV_CMD_BUFFER_STATUS_PENDING
,
1010 struct radv_cmd_buffer
{
1011 VK_LOADER_DATA _loader_data
;
1013 struct radv_device
* device
;
1015 struct radv_cmd_pool
* pool
;
1016 struct list_head pool_link
;
1018 VkCommandBufferUsageFlags usage_flags
;
1019 VkCommandBufferLevel level
;
1020 enum radv_cmd_buffer_status status
;
1021 struct radeon_cmdbuf
*cs
;
1022 struct radv_cmd_state state
;
1023 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1024 uint32_t queue_family_index
;
1026 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1027 VkShaderStageFlags push_constant_stages
;
1028 struct radv_descriptor_set meta_push_descriptors
;
1030 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1032 struct radv_cmd_buffer_upload upload
;
1034 uint32_t scratch_size_needed
;
1035 uint32_t compute_scratch_size_needed
;
1036 uint32_t esgs_ring_size_needed
;
1037 uint32_t gsvs_ring_size_needed
;
1038 bool tess_rings_needed
;
1039 bool sample_positions_needed
;
1041 VkResult record_result
;
1043 int ring_offsets_idx
; /* just used for verification */
1044 uint32_t gfx9_fence_offset
;
1045 struct radeon_winsys_bo
*gfx9_fence_bo
;
1046 uint32_t gfx9_fence_idx
;
1049 * Whether a query pool has been resetted and we have to flush caches.
1051 bool pending_reset_query
;
1056 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1058 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
1059 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
1061 void cik_create_gfx_config(struct radv_device
*device
);
1063 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1064 int count
, const VkViewport
*viewports
);
1065 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1066 int count
, const VkRect2D
*scissors
,
1067 const VkViewport
*viewports
, bool can_use_guardband
);
1068 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1069 bool instanced_draw
, bool indirect_draw
,
1070 uint32_t draw_vertex_count
);
1071 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1072 enum chip_class chip_class
,
1074 unsigned event
, unsigned event_flags
,
1078 uint32_t new_fence
);
1080 void si_emit_wait_fence(struct radeon_cmdbuf
*cs
,
1081 uint64_t va
, uint32_t ref
,
1083 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1084 enum chip_class chip_class
,
1085 uint32_t *fence_ptr
, uint64_t va
,
1087 enum radv_cmd_flush_bits flush_bits
);
1088 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1089 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
1090 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1091 uint64_t src_va
, uint64_t dest_va
,
1093 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1095 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1096 uint64_t size
, unsigned value
);
1097 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1099 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1101 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1104 unsigned *out_offset
,
1107 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1108 const struct radv_subpass
*subpass
,
1111 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1112 unsigned size
, unsigned alignmnet
,
1113 const void *data
, unsigned *out_offset
);
1115 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1116 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1117 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1118 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1119 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf
*cs
, int nr_samples
);
1120 unsigned radv_cayman_get_maxdist(int log_samples
);
1121 void radv_device_init_msaa(struct radv_device
*device
);
1123 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1124 struct radv_image
*image
,
1125 VkClearDepthStencilValue ds_clear_value
,
1126 VkImageAspectFlags aspects
);
1128 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1129 struct radv_image
*image
,
1131 uint32_t color_values
[2]);
1133 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1134 struct radv_image
*image
,
1136 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1137 struct radeon_winsys_bo
*bo
,
1138 uint64_t offset
, uint64_t size
, uint32_t value
);
1139 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1140 bool radv_get_memory_fd(struct radv_device
*device
,
1141 struct radv_device_memory
*memory
,
1145 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1146 unsigned sh_offset
, unsigned pointer_count
,
1147 bool use_32bit_pointers
)
1149 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1150 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1154 radv_emit_shader_pointer_body(struct radv_device
*device
,
1155 struct radeon_cmdbuf
*cs
,
1156 uint64_t va
, bool use_32bit_pointers
)
1158 radeon_emit(cs
, va
);
1160 if (use_32bit_pointers
) {
1162 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1164 radeon_emit(cs
, va
>> 32);
1169 radv_emit_shader_pointer(struct radv_device
*device
,
1170 struct radeon_cmdbuf
*cs
,
1171 uint32_t sh_offset
, uint64_t va
, bool global
)
1173 bool use_32bit_pointers
= HAVE_32BIT_POINTERS
&& !global
;
1175 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1176 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1179 static inline struct radv_descriptor_state
*
1180 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1181 VkPipelineBindPoint bind_point
)
1183 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1184 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1185 return &cmd_buffer
->descriptors
[bind_point
];
1189 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1191 * Limitations: Can't call normal dispatch functions without binding or rebinding
1192 * the compute pipeline.
1194 void radv_unaligned_dispatch(
1195 struct radv_cmd_buffer
*cmd_buffer
,
1201 struct radeon_winsys_bo
*bo
;
1205 struct radv_shader_module
;
1207 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1208 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1209 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1211 radv_hash_shaders(unsigned char *hash
,
1212 const VkPipelineShaderStageCreateInfo
**stages
,
1213 const struct radv_pipeline_layout
*layout
,
1214 const struct radv_pipeline_key
*key
,
1217 static inline gl_shader_stage
1218 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1220 assert(__builtin_popcount(vk_stage
) == 1);
1221 return ffs(vk_stage
) - 1;
1224 static inline VkShaderStageFlagBits
1225 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1227 return (1 << mesa_stage
);
1230 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1232 #define radv_foreach_stage(stage, stage_bits) \
1233 for (gl_shader_stage stage, \
1234 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1235 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1236 __tmp &= ~(1 << (stage)))
1238 unsigned radv_format_meta_fs_key(VkFormat format
);
1240 struct radv_multisample_state
{
1242 uint32_t pa_sc_line_cntl
;
1243 uint32_t pa_sc_mode_cntl_0
;
1244 uint32_t pa_sc_mode_cntl_1
;
1245 uint32_t pa_sc_aa_config
;
1246 uint32_t pa_sc_aa_mask
[2];
1247 unsigned num_samples
;
1250 struct radv_prim_vertex_count
{
1255 struct radv_vertex_elements_info
{
1256 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1257 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1258 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1259 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1263 struct radv_ia_multi_vgt_param_helpers
{
1265 bool partial_es_wave
;
1266 uint8_t primgroup_size
;
1267 bool wd_switch_on_eop
;
1268 bool ia_switch_on_eoi
;
1269 bool partial_vs_wave
;
1272 #define SI_GS_PER_ES 128
1274 struct radv_pipeline
{
1275 struct radv_device
* device
;
1276 struct radv_dynamic_state dynamic_state
;
1278 struct radv_pipeline_layout
* layout
;
1280 bool need_indirect_descriptor_sets
;
1281 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1282 struct radv_shader_variant
*gs_copy_shader
;
1283 VkShaderStageFlags active_stages
;
1285 struct radeon_cmdbuf cs
;
1287 struct radv_vertex_elements_info vertex_elements
;
1289 uint32_t binding_stride
[MAX_VBS
];
1291 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1294 struct radv_multisample_state ms
;
1295 uint32_t spi_baryc_cntl
;
1296 bool prim_restart_enable
;
1297 unsigned esgs_ring_size
;
1298 unsigned gsvs_ring_size
;
1299 uint32_t vtx_base_sgpr
;
1300 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1301 uint8_t vtx_emit_num
;
1302 struct radv_prim_vertex_count prim_vertex_count
;
1303 bool can_use_guardband
;
1304 uint32_t needed_dynamic_state
;
1305 bool disable_out_of_order_rast_for_occlusion
;
1307 /* Used for rbplus */
1308 uint32_t col_format
;
1309 uint32_t cb_target_mask
;
1314 unsigned scratch_bytes_per_wave
;
1317 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1319 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1322 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1324 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1327 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1328 gl_shader_stage stage
,
1331 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1332 gl_shader_stage stage
);
1334 struct radv_graphics_pipeline_create_info
{
1336 bool db_depth_clear
;
1337 bool db_stencil_clear
;
1338 bool db_depth_disable_expclear
;
1339 bool db_stencil_disable_expclear
;
1340 bool db_flush_depth_inplace
;
1341 bool db_flush_stencil_inplace
;
1342 bool db_resummarize
;
1343 uint32_t custom_blend_mode
;
1347 radv_graphics_pipeline_create(VkDevice device
,
1348 VkPipelineCache cache
,
1349 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1350 const struct radv_graphics_pipeline_create_info
*extra
,
1351 const VkAllocationCallbacks
*alloc
,
1352 VkPipeline
*pPipeline
);
1354 struct vk_format_description
;
1355 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1356 int first_non_void
);
1357 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1358 int first_non_void
);
1359 uint32_t radv_translate_colorformat(VkFormat format
);
1360 uint32_t radv_translate_color_numformat(VkFormat format
,
1361 const struct vk_format_description
*desc
,
1362 int first_non_void
);
1363 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1364 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1365 uint32_t radv_translate_dbformat(VkFormat format
);
1366 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1367 const struct vk_format_description
*desc
,
1368 int first_non_void
);
1369 uint32_t radv_translate_tex_numformat(VkFormat format
,
1370 const struct vk_format_description
*desc
,
1371 int first_non_void
);
1372 bool radv_format_pack_clear_color(VkFormat format
,
1373 uint32_t clear_vals
[2],
1374 VkClearColorValue
*value
);
1375 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1376 bool radv_dcc_formats_compatible(VkFormat format1
,
1379 struct radv_fmask_info
{
1383 unsigned pitch_in_pixels
;
1384 unsigned bank_height
;
1385 unsigned slice_tile_max
;
1386 unsigned tile_mode_index
;
1387 unsigned tile_swizzle
;
1390 struct radv_cmask_info
{
1394 unsigned slice_tile_max
;
1399 /* The original VkFormat provided by the client. This may not match any
1400 * of the actual surface formats.
1403 VkImageAspectFlags aspects
;
1404 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1405 struct ac_surf_info info
;
1406 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1407 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1412 unsigned queue_family_mask
;
1416 /* Set when bound */
1417 struct radeon_winsys_bo
*bo
;
1418 VkDeviceSize offset
;
1419 uint64_t dcc_offset
;
1420 uint64_t htile_offset
;
1421 bool tc_compatible_htile
;
1422 struct radeon_surf surface
;
1424 struct radv_fmask_info fmask
;
1425 struct radv_cmask_info cmask
;
1426 uint64_t clear_value_offset
;
1427 uint64_t dcc_pred_offset
;
1429 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1430 VkDeviceMemory owned_memory
;
1433 /* Whether the image has a htile that is known consistent with the contents of
1435 bool radv_layout_has_htile(const struct radv_image
*image
,
1436 VkImageLayout layout
,
1437 unsigned queue_mask
);
1439 /* Whether the image has a htile that is known consistent with the contents of
1440 * the image and is allowed to be in compressed form.
1442 * If this is false reads that don't use the htile should be able to return
1445 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1446 VkImageLayout layout
,
1447 unsigned queue_mask
);
1449 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1450 VkImageLayout layout
,
1451 unsigned queue_mask
);
1453 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1454 VkImageLayout layout
,
1455 unsigned queue_mask
);
1458 * Return whether the image has CMASK metadata for color surfaces.
1461 radv_image_has_cmask(const struct radv_image
*image
)
1463 return image
->cmask
.size
;
1467 * Return whether the image has FMASK metadata for color surfaces.
1470 radv_image_has_fmask(const struct radv_image
*image
)
1472 return image
->fmask
.size
;
1476 * Return whether the image has DCC metadata for color surfaces.
1479 radv_image_has_dcc(const struct radv_image
*image
)
1481 return image
->surface
.dcc_size
;
1485 * Return whether DCC metadata is enabled for a level.
1488 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1490 return radv_image_has_dcc(image
) &&
1491 level
< image
->surface
.num_dcc_levels
;
1495 * Return whether the image has CB metadata.
1498 radv_image_has_CB_metadata(const struct radv_image
*image
)
1500 return radv_image_has_cmask(image
) ||
1501 radv_image_has_fmask(image
) ||
1502 radv_image_has_dcc(image
);
1506 * Return whether the image has HTILE metadata for depth surfaces.
1509 radv_image_has_htile(const struct radv_image
*image
)
1511 return image
->surface
.htile_size
;
1515 * Return whether HTILE metadata is enabled for a level.
1518 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1520 return radv_image_has_htile(image
) && level
== 0;
1524 * Return whether the image is TC-compatible HTILE.
1527 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1529 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1532 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1534 static inline uint32_t
1535 radv_get_layerCount(const struct radv_image
*image
,
1536 const VkImageSubresourceRange
*range
)
1538 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1539 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1542 static inline uint32_t
1543 radv_get_levelCount(const struct radv_image
*image
,
1544 const VkImageSubresourceRange
*range
)
1546 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1547 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1550 struct radeon_bo_metadata
;
1552 radv_init_metadata(struct radv_device
*device
,
1553 struct radv_image
*image
,
1554 struct radeon_bo_metadata
*metadata
);
1556 struct radv_image_view
{
1557 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1558 struct radeon_winsys_bo
*bo
;
1560 VkImageViewType type
;
1561 VkImageAspectFlags aspect_mask
;
1563 uint32_t base_layer
;
1564 uint32_t layer_count
;
1566 uint32_t level_count
;
1567 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1569 uint32_t descriptor
[16];
1571 /* Descriptor for use as a storage image as opposed to a sampled image.
1572 * This has a few differences for cube maps (e.g. type).
1574 uint32_t storage_descriptor
[16];
1577 struct radv_image_create_info
{
1578 const VkImageCreateInfo
*vk_info
;
1580 bool no_metadata_planes
;
1583 VkResult
radv_image_create(VkDevice _device
,
1584 const struct radv_image_create_info
*info
,
1585 const VkAllocationCallbacks
* alloc
,
1589 radv_image_from_gralloc(VkDevice device_h
,
1590 const VkImageCreateInfo
*base_info
,
1591 const VkNativeBufferANDROID
*gralloc_info
,
1592 const VkAllocationCallbacks
*alloc
,
1593 VkImage
*out_image_h
);
1595 void radv_image_view_init(struct radv_image_view
*view
,
1596 struct radv_device
*device
,
1597 const VkImageViewCreateInfo
* pCreateInfo
);
1599 struct radv_buffer_view
{
1600 struct radeon_winsys_bo
*bo
;
1602 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1605 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1606 struct radv_device
*device
,
1607 const VkBufferViewCreateInfo
* pCreateInfo
);
1609 static inline struct VkExtent3D
1610 radv_sanitize_image_extent(const VkImageType imageType
,
1611 const struct VkExtent3D imageExtent
)
1613 switch (imageType
) {
1614 case VK_IMAGE_TYPE_1D
:
1615 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1616 case VK_IMAGE_TYPE_2D
:
1617 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1618 case VK_IMAGE_TYPE_3D
:
1621 unreachable("invalid image type");
1625 static inline struct VkOffset3D
1626 radv_sanitize_image_offset(const VkImageType imageType
,
1627 const struct VkOffset3D imageOffset
)
1629 switch (imageType
) {
1630 case VK_IMAGE_TYPE_1D
:
1631 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1632 case VK_IMAGE_TYPE_2D
:
1633 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1634 case VK_IMAGE_TYPE_3D
:
1637 unreachable("invalid image type");
1642 radv_image_extent_compare(const struct radv_image
*image
,
1643 const VkExtent3D
*extent
)
1645 if (extent
->width
!= image
->info
.width
||
1646 extent
->height
!= image
->info
.height
||
1647 extent
->depth
!= image
->info
.depth
)
1652 struct radv_sampler
{
1656 struct radv_color_buffer_info
{
1657 uint64_t cb_color_base
;
1658 uint64_t cb_color_cmask
;
1659 uint64_t cb_color_fmask
;
1660 uint64_t cb_dcc_base
;
1661 uint32_t cb_color_pitch
;
1662 uint32_t cb_color_slice
;
1663 uint32_t cb_color_view
;
1664 uint32_t cb_color_info
;
1665 uint32_t cb_color_attrib
;
1666 uint32_t cb_color_attrib2
;
1667 uint32_t cb_dcc_control
;
1668 uint32_t cb_color_cmask_slice
;
1669 uint32_t cb_color_fmask_slice
;
1672 struct radv_ds_buffer_info
{
1673 uint64_t db_z_read_base
;
1674 uint64_t db_stencil_read_base
;
1675 uint64_t db_z_write_base
;
1676 uint64_t db_stencil_write_base
;
1677 uint64_t db_htile_data_base
;
1678 uint32_t db_depth_info
;
1680 uint32_t db_stencil_info
;
1681 uint32_t db_depth_view
;
1682 uint32_t db_depth_size
;
1683 uint32_t db_depth_slice
;
1684 uint32_t db_htile_surface
;
1685 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1686 uint32_t db_z_info2
;
1687 uint32_t db_stencil_info2
;
1691 struct radv_attachment_info
{
1693 struct radv_color_buffer_info cb
;
1694 struct radv_ds_buffer_info ds
;
1696 struct radv_image_view
*attachment
;
1699 struct radv_framebuffer
{
1704 uint32_t attachment_count
;
1705 struct radv_attachment_info attachments
[0];
1708 struct radv_subpass_barrier
{
1709 VkPipelineStageFlags src_stage_mask
;
1710 VkAccessFlags src_access_mask
;
1711 VkAccessFlags dst_access_mask
;
1714 struct radv_subpass
{
1715 uint32_t input_count
;
1716 uint32_t color_count
;
1717 VkAttachmentReference
* input_attachments
;
1718 VkAttachmentReference
* color_attachments
;
1719 VkAttachmentReference
* resolve_attachments
;
1720 VkAttachmentReference depth_stencil_attachment
;
1722 /** Subpass has at least one resolve attachment */
1725 struct radv_subpass_barrier start_barrier
;
1728 VkSampleCountFlagBits max_sample_count
;
1731 struct radv_render_pass_attachment
{
1734 VkAttachmentLoadOp load_op
;
1735 VkAttachmentLoadOp stencil_load_op
;
1736 VkImageLayout initial_layout
;
1737 VkImageLayout final_layout
;
1741 struct radv_render_pass
{
1742 uint32_t attachment_count
;
1743 uint32_t subpass_count
;
1744 VkAttachmentReference
* subpass_attachments
;
1745 struct radv_render_pass_attachment
* attachments
;
1746 struct radv_subpass_barrier end_barrier
;
1747 struct radv_subpass subpasses
[0];
1750 VkResult
radv_device_init_meta(struct radv_device
*device
);
1751 void radv_device_finish_meta(struct radv_device
*device
);
1753 struct radv_query_pool
{
1754 struct radeon_winsys_bo
*bo
;
1756 uint32_t availability_offset
;
1760 uint32_t pipeline_stats_mask
;
1763 struct radv_semaphore
{
1764 /* use a winsys sem for non-exportable */
1765 struct radeon_winsys_sem
*sem
;
1767 uint32_t temp_syncobj
;
1770 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1771 VkPipelineBindPoint bind_point
,
1772 struct radv_descriptor_set
*set
,
1776 radv_update_descriptor_sets(struct radv_device
*device
,
1777 struct radv_cmd_buffer
*cmd_buffer
,
1778 VkDescriptorSet overrideSet
,
1779 uint32_t descriptorWriteCount
,
1780 const VkWriteDescriptorSet
*pDescriptorWrites
,
1781 uint32_t descriptorCopyCount
,
1782 const VkCopyDescriptorSet
*pDescriptorCopies
);
1785 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1786 struct radv_cmd_buffer
*cmd_buffer
,
1787 struct radv_descriptor_set
*set
,
1788 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1791 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1792 VkPipelineBindPoint pipelineBindPoint
,
1793 VkPipelineLayout _layout
,
1795 uint32_t descriptorWriteCount
,
1796 const VkWriteDescriptorSet
*pDescriptorWrites
);
1798 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1799 struct radv_image
*image
, uint32_t value
);
1802 struct radeon_winsys_fence
*fence
;
1803 struct wsi_fence
*fence_wsi
;
1808 uint32_t temp_syncobj
;
1811 /* radv_nir_to_llvm.c */
1812 struct radv_shader_variant_info
;
1813 struct radv_nir_compiler_options
;
1815 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
1816 struct nir_shader
*geom_shader
,
1817 struct ac_shader_binary
*binary
,
1818 struct ac_shader_config
*config
,
1819 struct radv_shader_variant_info
*shader_info
,
1820 const struct radv_nir_compiler_options
*option
);
1822 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
1823 struct ac_shader_binary
*binary
,
1824 struct ac_shader_config
*config
,
1825 struct radv_shader_variant_info
*shader_info
,
1826 struct nir_shader
*const *nir
,
1828 const struct radv_nir_compiler_options
*options
);
1830 /* radv_shader_info.h */
1831 struct radv_shader_info
;
1833 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
1834 const struct radv_nir_compiler_options
*options
,
1835 struct radv_shader_info
*info
);
1837 struct radeon_winsys_sem
;
1839 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1841 static inline struct __radv_type * \
1842 __radv_type ## _from_handle(__VkType _handle) \
1844 return (struct __radv_type *) _handle; \
1847 static inline __VkType \
1848 __radv_type ## _to_handle(struct __radv_type *_obj) \
1850 return (__VkType) _obj; \
1853 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1855 static inline struct __radv_type * \
1856 __radv_type ## _from_handle(__VkType _handle) \
1858 return (struct __radv_type *)(uintptr_t) _handle; \
1861 static inline __VkType \
1862 __radv_type ## _to_handle(struct __radv_type *_obj) \
1864 return (__VkType)(uintptr_t) _obj; \
1867 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1868 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1870 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1871 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1872 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1873 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1874 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1876 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1877 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1878 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1879 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1880 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1881 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1882 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1883 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1884 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1885 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1886 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1887 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1888 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1889 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1890 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1891 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1892 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1893 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1894 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1895 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1896 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1898 #endif /* RADV_PRIVATE_H */