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radv: add assertions to make sure pipeline layout objects are valid
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280
281 VkPhysicalDeviceMemoryProperties memory_properties;
282 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 uint64_t perftest_flags;
296 };
297
298 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
299 void radv_finish_wsi(struct radv_physical_device *physical_device);
300
301 bool radv_instance_extension_supported(const char *name);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
303 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
304 const char *name);
305
306 struct cache_entry;
307
308 struct radv_pipeline_cache {
309 struct radv_device * device;
310 pthread_mutex_t mutex;
311
312 uint32_t total_size;
313 uint32_t table_size;
314 uint32_t kernel_count;
315 struct cache_entry ** hash_table;
316 bool modified;
317
318 VkAllocationCallbacks alloc;
319 };
320
321 struct radv_pipeline_key {
322 uint32_t instance_rate_inputs;
323 unsigned tess_input_vertices;
324 uint32_t col_format;
325 uint32_t is_int8;
326 uint32_t is_int10;
327 uint32_t multisample : 1;
328 uint32_t has_multiview_view_index : 1;
329 };
330
331 void
332 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
333 struct radv_device *device);
334 void
335 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
336 void
337 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
338 const void *data, size_t size);
339
340 struct radv_shader_variant;
341
342 bool
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
344 struct radv_pipeline_cache *cache,
345 const unsigned char *sha1,
346 struct radv_shader_variant **variants);
347
348 void
349 radv_pipeline_cache_insert_shaders(struct radv_device *device,
350 struct radv_pipeline_cache *cache,
351 const unsigned char *sha1,
352 struct radv_shader_variant **variants,
353 const void *const *codes,
354 const unsigned *code_sizes);
355
356 struct radv_meta_state {
357 VkAllocationCallbacks alloc;
358
359 struct radv_pipeline_cache cache;
360
361 /**
362 * Use array element `i` for images with `2^i` samples.
363 */
364 struct {
365 VkRenderPass render_pass[NUM_META_FS_KEYS];
366 VkPipeline color_pipelines[NUM_META_FS_KEYS];
367
368 VkRenderPass depthstencil_rp;
369 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
370 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
371 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
372 } clear[1 + MAX_SAMPLES_LOG2];
373
374 VkPipelineLayout clear_color_p_layout;
375 VkPipelineLayout clear_depth_p_layout;
376 struct {
377 VkRenderPass render_pass[NUM_META_FS_KEYS];
378
379 /** Pipeline that blits from a 1D image. */
380 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
381
382 /** Pipeline that blits from a 2D image. */
383 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
384
385 /** Pipeline that blits from a 3D image. */
386 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
387
388 VkRenderPass depth_only_rp;
389 VkPipeline depth_only_1d_pipeline;
390 VkPipeline depth_only_2d_pipeline;
391 VkPipeline depth_only_3d_pipeline;
392
393 VkRenderPass stencil_only_rp;
394 VkPipeline stencil_only_1d_pipeline;
395 VkPipeline stencil_only_2d_pipeline;
396 VkPipeline stencil_only_3d_pipeline;
397 VkPipelineLayout pipeline_layout;
398 VkDescriptorSetLayout ds_layout;
399 } blit;
400
401 struct {
402 VkRenderPass render_passes[NUM_META_FS_KEYS];
403
404 VkPipelineLayout p_layouts[2];
405 VkDescriptorSetLayout ds_layouts[2];
406 VkPipeline pipelines[2][NUM_META_FS_KEYS];
407
408 VkRenderPass depth_only_rp;
409 VkPipeline depth_only_pipeline[2];
410
411 VkRenderPass stencil_only_rp;
412 VkPipeline stencil_only_pipeline[2];
413 } blit2d;
414
415 struct {
416 VkPipelineLayout img_p_layout;
417 VkDescriptorSetLayout img_ds_layout;
418 VkPipeline pipeline;
419 } itob;
420 struct {
421 VkPipelineLayout img_p_layout;
422 VkDescriptorSetLayout img_ds_layout;
423 VkPipeline pipeline;
424 } btoi;
425 struct {
426 VkPipelineLayout img_p_layout;
427 VkDescriptorSetLayout img_ds_layout;
428 VkPipeline pipeline;
429 } itoi;
430 struct {
431 VkPipelineLayout img_p_layout;
432 VkDescriptorSetLayout img_ds_layout;
433 VkPipeline pipeline;
434 } cleari;
435
436 struct {
437 VkPipelineLayout p_layout;
438 VkPipeline pipeline;
439 VkRenderPass pass;
440 } resolve;
441
442 struct {
443 VkDescriptorSetLayout ds_layout;
444 VkPipelineLayout p_layout;
445 struct {
446 VkPipeline pipeline;
447 VkPipeline i_pipeline;
448 VkPipeline srgb_pipeline;
449 } rc[MAX_SAMPLES_LOG2];
450 } resolve_compute;
451
452 struct {
453 VkDescriptorSetLayout ds_layout;
454 VkPipelineLayout p_layout;
455
456 struct {
457 VkRenderPass render_pass[NUM_META_FS_KEYS];
458 VkPipeline pipeline[NUM_META_FS_KEYS];
459 } rc[MAX_SAMPLES_LOG2];
460 } resolve_fragment;
461
462 struct {
463 VkPipelineLayout p_layout;
464 VkPipeline decompress_pipeline;
465 VkPipeline resummarize_pipeline;
466 VkRenderPass pass;
467 } depth_decomp[1 + MAX_SAMPLES_LOG2];
468
469 struct {
470 VkPipelineLayout p_layout;
471 VkPipeline cmask_eliminate_pipeline;
472 VkPipeline fmask_decompress_pipeline;
473 VkRenderPass pass;
474 } fast_clear_flush;
475
476 struct {
477 VkPipelineLayout fill_p_layout;
478 VkPipelineLayout copy_p_layout;
479 VkDescriptorSetLayout fill_ds_layout;
480 VkDescriptorSetLayout copy_ds_layout;
481 VkPipeline fill_pipeline;
482 VkPipeline copy_pipeline;
483 } buffer;
484
485 struct {
486 VkDescriptorSetLayout ds_layout;
487 VkPipelineLayout p_layout;
488 VkPipeline occlusion_query_pipeline;
489 VkPipeline pipeline_statistics_query_pipeline;
490 } query;
491 };
492
493 /* queue types */
494 #define RADV_QUEUE_GENERAL 0
495 #define RADV_QUEUE_COMPUTE 1
496 #define RADV_QUEUE_TRANSFER 2
497
498 #define RADV_MAX_QUEUE_FAMILIES 3
499
500 enum ring_type radv_queue_family_to_ring(int f);
501
502 struct radv_queue {
503 VK_LOADER_DATA _loader_data;
504 struct radv_device * device;
505 struct radeon_winsys_ctx *hw_ctx;
506 enum radeon_ctx_priority priority;
507 uint32_t queue_family_index;
508 int queue_idx;
509
510 uint32_t scratch_size;
511 uint32_t compute_scratch_size;
512 uint32_t esgs_ring_size;
513 uint32_t gsvs_ring_size;
514 bool has_tess_rings;
515 bool has_sample_positions;
516
517 struct radeon_winsys_bo *scratch_bo;
518 struct radeon_winsys_bo *descriptor_bo;
519 struct radeon_winsys_bo *compute_scratch_bo;
520 struct radeon_winsys_bo *esgs_ring_bo;
521 struct radeon_winsys_bo *gsvs_ring_bo;
522 struct radeon_winsys_bo *tess_factor_ring_bo;
523 struct radeon_winsys_bo *tess_offchip_ring_bo;
524 struct radeon_winsys_cs *initial_preamble_cs;
525 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
526 struct radeon_winsys_cs *continue_preamble_cs;
527 };
528
529 struct radv_device {
530 VK_LOADER_DATA _loader_data;
531
532 VkAllocationCallbacks alloc;
533
534 struct radv_instance * instance;
535 struct radeon_winsys *ws;
536
537 struct radv_meta_state meta_state;
538
539 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
540 int queue_count[RADV_MAX_QUEUE_FAMILIES];
541 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
542
543 bool llvm_supports_spill;
544 bool has_distributed_tess;
545 bool dfsm_allowed;
546 uint32_t tess_offchip_block_dw_size;
547 uint32_t scratch_waves;
548 uint32_t dispatch_initiator;
549
550 uint32_t gs_table_depth;
551
552 /* MSAA sample locations.
553 * The first index is the sample index.
554 * The second index is the coordinate: X, Y. */
555 float sample_locations_1x[1][2];
556 float sample_locations_2x[2][2];
557 float sample_locations_4x[4][2];
558 float sample_locations_8x[8][2];
559 float sample_locations_16x[16][2];
560
561 /* CIK and later */
562 uint32_t gfx_init_size_dw;
563 struct radeon_winsys_bo *gfx_init;
564
565 struct radeon_winsys_bo *trace_bo;
566 uint32_t *trace_id_ptr;
567
568 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
569 bool keep_shader_info;
570
571 struct radv_physical_device *physical_device;
572
573 /* Backup in-memory cache to be used if the app doesn't provide one */
574 struct radv_pipeline_cache * mem_cache;
575
576 /*
577 * use different counters so MSAA MRTs get consecutive surface indices,
578 * even if MASK is allocated in between.
579 */
580 uint32_t image_mrt_offset_counter;
581 uint32_t fmask_mrt_offset_counter;
582 struct list_head shader_slabs;
583 mtx_t shader_slab_mutex;
584
585 /* For detecting VM faults reported by dmesg. */
586 uint64_t dmesg_timestamp;
587 };
588
589 struct radv_device_memory {
590 struct radeon_winsys_bo *bo;
591 /* for dedicated allocations */
592 struct radv_image *image;
593 struct radv_buffer *buffer;
594 uint32_t type_index;
595 VkDeviceSize map_size;
596 void * map;
597 };
598
599
600 struct radv_descriptor_range {
601 uint64_t va;
602 uint32_t size;
603 };
604
605 struct radv_descriptor_set {
606 const struct radv_descriptor_set_layout *layout;
607 uint32_t size;
608
609 struct radeon_winsys_bo *bo;
610 uint64_t va;
611 uint32_t *mapped_ptr;
612 struct radv_descriptor_range *dynamic_descriptors;
613
614 struct radeon_winsys_bo *descriptors[0];
615 };
616
617 struct radv_push_descriptor_set
618 {
619 struct radv_descriptor_set set;
620 uint32_t capacity;
621 };
622
623 struct radv_descriptor_pool_entry {
624 uint32_t offset;
625 uint32_t size;
626 struct radv_descriptor_set *set;
627 };
628
629 struct radv_descriptor_pool {
630 struct radeon_winsys_bo *bo;
631 uint8_t *mapped_ptr;
632 uint64_t current_offset;
633 uint64_t size;
634
635 uint8_t *host_memory_base;
636 uint8_t *host_memory_ptr;
637 uint8_t *host_memory_end;
638
639 uint32_t entry_count;
640 uint32_t max_entry_count;
641 struct radv_descriptor_pool_entry entries[0];
642 };
643
644 struct radv_descriptor_update_template_entry {
645 VkDescriptorType descriptor_type;
646
647 /* The number of descriptors to update */
648 uint32_t descriptor_count;
649
650 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
651 uint32_t dst_offset;
652
653 /* In dwords. Not valid/used for dynamic descriptors */
654 uint32_t dst_stride;
655
656 uint32_t buffer_offset;
657
658 /* Only valid for combined image samplers and samplers */
659 uint16_t has_sampler;
660
661 /* In bytes */
662 size_t src_offset;
663 size_t src_stride;
664
665 /* For push descriptors */
666 const uint32_t *immutable_samplers;
667 };
668
669 struct radv_descriptor_update_template {
670 uint32_t entry_count;
671 struct radv_descriptor_update_template_entry entry[0];
672 };
673
674 struct radv_buffer {
675 struct radv_device * device;
676 VkDeviceSize size;
677
678 VkBufferUsageFlags usage;
679 VkBufferCreateFlags flags;
680
681 /* Set when bound */
682 struct radeon_winsys_bo * bo;
683 VkDeviceSize offset;
684
685 bool shareable;
686 };
687
688
689 enum radv_cmd_dirty_bits {
690 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
691 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
692 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
693 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
694 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
695 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
696 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
697 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
698 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
699 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
700 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
701 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
702 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
703 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
704 };
705
706 enum radv_cmd_flush_bits {
707 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
708 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
709 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
710 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
711 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
712 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
713 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
714 /* Same as above, but only writes back and doesn't invalidate */
715 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
716 /* Framebuffer caches */
717 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
718 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
719 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
720 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
721 /* Engine synchronization. */
722 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
723 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
724 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
725 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
726
727 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
728 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
729 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
730 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
731 };
732
733 struct radv_vertex_binding {
734 struct radv_buffer * buffer;
735 VkDeviceSize offset;
736 };
737
738 struct radv_viewport_state {
739 uint32_t count;
740 VkViewport viewports[MAX_VIEWPORTS];
741 };
742
743 struct radv_scissor_state {
744 uint32_t count;
745 VkRect2D scissors[MAX_SCISSORS];
746 };
747
748 struct radv_dynamic_state {
749 /**
750 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
751 * Defines the set of saved dynamic state.
752 */
753 uint32_t mask;
754
755 struct radv_viewport_state viewport;
756
757 struct radv_scissor_state scissor;
758
759 float line_width;
760
761 struct {
762 float bias;
763 float clamp;
764 float slope;
765 } depth_bias;
766
767 float blend_constants[4];
768
769 struct {
770 float min;
771 float max;
772 } depth_bounds;
773
774 struct {
775 uint32_t front;
776 uint32_t back;
777 } stencil_compare_mask;
778
779 struct {
780 uint32_t front;
781 uint32_t back;
782 } stencil_write_mask;
783
784 struct {
785 uint32_t front;
786 uint32_t back;
787 } stencil_reference;
788 };
789
790 extern const struct radv_dynamic_state default_dynamic_state;
791
792 const char *
793 radv_get_debug_option_name(int id);
794
795 const char *
796 radv_get_perftest_option_name(int id);
797
798 /**
799 * Attachment state when recording a renderpass instance.
800 *
801 * The clear value is valid only if there exists a pending clear.
802 */
803 struct radv_attachment_state {
804 VkImageAspectFlags pending_clear_aspects;
805 uint32_t cleared_views;
806 VkClearValue clear_value;
807 VkImageLayout current_layout;
808 };
809
810 struct radv_cmd_state {
811 /* Vertex descriptors */
812 bool vb_prefetch_dirty;
813 uint64_t vb_va;
814 unsigned vb_size;
815
816 bool push_descriptors_dirty;
817 bool predicating;
818 uint32_t dirty;
819
820 struct radv_pipeline * pipeline;
821 struct radv_pipeline * emitted_pipeline;
822 struct radv_pipeline * compute_pipeline;
823 struct radv_pipeline * emitted_compute_pipeline;
824 struct radv_framebuffer * framebuffer;
825 struct radv_render_pass * pass;
826 const struct radv_subpass * subpass;
827 struct radv_dynamic_state dynamic;
828 struct radv_attachment_state * attachments;
829 VkRect2D render_area;
830
831 /* Index buffer */
832 struct radv_buffer *index_buffer;
833 uint64_t index_offset;
834 uint32_t index_type;
835 uint32_t max_index_count;
836 uint64_t index_va;
837 int32_t last_index_type;
838
839 int32_t last_primitive_reset_en;
840 uint32_t last_primitive_reset_index;
841 enum radv_cmd_flush_bits flush_bits;
842 unsigned active_occlusion_queries;
843 float offset_scale;
844 uint32_t descriptors_dirty;
845 uint32_t valid_descriptors;
846 uint32_t trace_id;
847 uint32_t last_ia_multi_vgt_param;
848 };
849
850 struct radv_cmd_pool {
851 VkAllocationCallbacks alloc;
852 struct list_head cmd_buffers;
853 struct list_head free_cmd_buffers;
854 uint32_t queue_family_index;
855 };
856
857 struct radv_cmd_buffer_upload {
858 uint8_t *map;
859 unsigned offset;
860 uint64_t size;
861 struct radeon_winsys_bo *upload_bo;
862 struct list_head list;
863 };
864
865 enum radv_cmd_buffer_status {
866 RADV_CMD_BUFFER_STATUS_INVALID,
867 RADV_CMD_BUFFER_STATUS_INITIAL,
868 RADV_CMD_BUFFER_STATUS_RECORDING,
869 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
870 RADV_CMD_BUFFER_STATUS_PENDING,
871 };
872
873 struct radv_cmd_buffer {
874 VK_LOADER_DATA _loader_data;
875
876 struct radv_device * device;
877
878 struct radv_cmd_pool * pool;
879 struct list_head pool_link;
880
881 VkCommandBufferUsageFlags usage_flags;
882 VkCommandBufferLevel level;
883 enum radv_cmd_buffer_status status;
884 struct radeon_winsys_cs *cs;
885 struct radv_cmd_state state;
886 struct radv_vertex_binding vertex_bindings[MAX_VBS];
887 uint32_t queue_family_index;
888
889 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
890 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
891 VkShaderStageFlags push_constant_stages;
892 struct radv_push_descriptor_set push_descriptors;
893 struct radv_descriptor_set meta_push_descriptors;
894 struct radv_descriptor_set *descriptors[MAX_SETS];
895
896 struct radv_cmd_buffer_upload upload;
897
898 uint32_t scratch_size_needed;
899 uint32_t compute_scratch_size_needed;
900 uint32_t esgs_ring_size_needed;
901 uint32_t gsvs_ring_size_needed;
902 bool tess_rings_needed;
903 bool sample_positions_needed;
904
905 VkResult record_result;
906
907 int ring_offsets_idx; /* just used for verification */
908 uint32_t gfx9_fence_offset;
909 struct radeon_winsys_bo *gfx9_fence_bo;
910 uint32_t gfx9_fence_idx;
911 };
912
913 struct radv_image;
914
915 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
916
917 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
918 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
919
920 void cik_create_gfx_config(struct radv_device *device);
921
922 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
923 int count, const VkViewport *viewports);
924 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
925 int count, const VkRect2D *scissors,
926 const VkViewport *viewports, bool can_use_guardband);
927 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
928 bool instanced_draw, bool indirect_draw,
929 uint32_t draw_vertex_count);
930 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
931 bool predicated,
932 enum chip_class chip_class,
933 bool is_mec,
934 unsigned event, unsigned event_flags,
935 unsigned data_sel,
936 uint64_t va,
937 uint32_t old_fence,
938 uint32_t new_fence);
939
940 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
941 bool predicated,
942 uint64_t va, uint32_t ref,
943 uint32_t mask);
944 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
945 bool predicated,
946 enum chip_class chip_class,
947 uint32_t *fence_ptr, uint64_t va,
948 bool is_mec,
949 enum radv_cmd_flush_bits flush_bits);
950 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
951 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
952 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
953 uint64_t src_va, uint64_t dest_va,
954 uint64_t size);
955 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
956 unsigned size);
957 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
958 uint64_t size, unsigned value);
959 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
960 bool
961 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
962 unsigned size,
963 unsigned alignment,
964 unsigned *out_offset,
965 void **ptr);
966 void
967 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
968 const struct radv_subpass *subpass,
969 bool transitions);
970 bool
971 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
972 unsigned size, unsigned alignmnet,
973 const void *data, unsigned *out_offset);
974
975 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
976 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
977 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
978 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
979 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
980 unsigned radv_cayman_get_maxdist(int log_samples);
981 void radv_device_init_msaa(struct radv_device *device);
982 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
983 struct radv_image *image,
984 VkClearDepthStencilValue ds_clear_value,
985 VkImageAspectFlags aspects);
986 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
987 struct radv_image *image,
988 int idx,
989 uint32_t color_values[2]);
990 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
991 struct radv_image *image,
992 bool value);
993 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
994 struct radeon_winsys_bo *bo,
995 uint64_t offset, uint64_t size, uint32_t value);
996 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
997 bool radv_get_memory_fd(struct radv_device *device,
998 struct radv_device_memory *memory,
999 int *pFD);
1000
1001 /*
1002 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1003 *
1004 * Limitations: Can't call normal dispatch functions without binding or rebinding
1005 * the compute pipeline.
1006 */
1007 void radv_unaligned_dispatch(
1008 struct radv_cmd_buffer *cmd_buffer,
1009 uint32_t x,
1010 uint32_t y,
1011 uint32_t z);
1012
1013 struct radv_event {
1014 struct radeon_winsys_bo *bo;
1015 uint64_t *map;
1016 };
1017
1018 struct radv_shader_module;
1019
1020 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1021 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1022 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1023 void
1024 radv_hash_shaders(unsigned char *hash,
1025 const VkPipelineShaderStageCreateInfo **stages,
1026 const struct radv_pipeline_layout *layout,
1027 const struct radv_pipeline_key *key,
1028 uint32_t flags);
1029
1030 static inline gl_shader_stage
1031 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1032 {
1033 assert(__builtin_popcount(vk_stage) == 1);
1034 return ffs(vk_stage) - 1;
1035 }
1036
1037 static inline VkShaderStageFlagBits
1038 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1039 {
1040 return (1 << mesa_stage);
1041 }
1042
1043 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1044
1045 #define radv_foreach_stage(stage, stage_bits) \
1046 for (gl_shader_stage stage, \
1047 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1048 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1049 __tmp &= ~(1 << (stage)))
1050
1051 struct radv_depth_stencil_state {
1052 uint32_t db_depth_control;
1053 uint32_t db_stencil_control;
1054 uint32_t db_render_control;
1055 uint32_t db_render_override2;
1056 };
1057
1058 struct radv_blend_state {
1059 uint32_t cb_color_control;
1060 uint32_t cb_target_mask;
1061 uint32_t sx_mrt_blend_opt[8];
1062 uint32_t cb_blend_control[8];
1063
1064 uint32_t spi_shader_col_format;
1065 uint32_t cb_shader_mask;
1066 uint32_t db_alpha_to_mask;
1067 };
1068
1069 unsigned radv_format_meta_fs_key(VkFormat format);
1070
1071 struct radv_raster_state {
1072 uint32_t pa_cl_clip_cntl;
1073 uint32_t spi_interp_control;
1074 uint32_t pa_su_vtx_cntl;
1075 uint32_t pa_su_sc_mode_cntl;
1076 };
1077
1078 struct radv_multisample_state {
1079 uint32_t db_eqaa;
1080 uint32_t pa_sc_line_cntl;
1081 uint32_t pa_sc_mode_cntl_0;
1082 uint32_t pa_sc_mode_cntl_1;
1083 uint32_t pa_sc_aa_config;
1084 uint32_t pa_sc_aa_mask[2];
1085 unsigned num_samples;
1086 };
1087
1088 struct radv_prim_vertex_count {
1089 uint8_t min;
1090 uint8_t incr;
1091 };
1092
1093 struct radv_tessellation_state {
1094 uint32_t ls_hs_config;
1095 uint32_t tcs_in_layout;
1096 uint32_t tcs_out_layout;
1097 uint32_t tcs_out_offsets;
1098 uint32_t offchip_layout;
1099 unsigned num_patches;
1100 unsigned lds_size;
1101 unsigned num_tcs_input_cp;
1102 uint32_t tf_param;
1103 };
1104
1105 struct radv_gs_state {
1106 uint32_t vgt_gs_onchip_cntl;
1107 uint32_t vgt_gs_max_prims_per_subgroup;
1108 uint32_t vgt_esgs_ring_itemsize;
1109 uint32_t lds_size;
1110 };
1111
1112 struct radv_vertex_elements_info {
1113 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1114 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1115 uint32_t binding[MAX_VERTEX_ATTRIBS];
1116 uint32_t offset[MAX_VERTEX_ATTRIBS];
1117 uint32_t count;
1118 };
1119
1120 struct radv_vs_state {
1121 uint32_t pa_cl_vs_out_cntl;
1122 uint32_t spi_shader_pos_format;
1123 uint32_t spi_vs_out_config;
1124 uint32_t vgt_reuse_off;
1125 };
1126
1127 #define SI_GS_PER_ES 128
1128
1129 struct radv_pipeline {
1130 struct radv_device * device;
1131 struct radv_dynamic_state dynamic_state;
1132
1133 struct radv_pipeline_layout * layout;
1134
1135 bool needs_data_cache;
1136 bool need_indirect_descriptor_sets;
1137 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1138 struct radv_shader_variant *gs_copy_shader;
1139 VkShaderStageFlags active_stages;
1140
1141 struct radv_vertex_elements_info vertex_elements;
1142
1143 uint32_t binding_stride[MAX_VBS];
1144
1145 uint32_t user_data_0[MESA_SHADER_STAGES];
1146 union {
1147 struct {
1148 struct radv_blend_state blend;
1149 struct radv_depth_stencil_state ds;
1150 struct radv_raster_state raster;
1151 struct radv_multisample_state ms;
1152 struct radv_tessellation_state tess;
1153 struct radv_gs_state gs;
1154 struct radv_vs_state vs;
1155 uint32_t db_shader_control;
1156 uint32_t shader_z_format;
1157 unsigned prim;
1158 unsigned gs_out;
1159 uint32_t vgt_gs_mode;
1160 bool vgt_primitiveid_en;
1161 bool prim_restart_enable;
1162 bool partial_es_wave;
1163 uint8_t primgroup_size;
1164 unsigned esgs_ring_size;
1165 unsigned gsvs_ring_size;
1166 uint32_t ps_input_cntl[32];
1167 uint32_t ps_input_cntl_num;
1168 uint32_t vgt_shader_stages_en;
1169 uint32_t vtx_base_sgpr;
1170 uint32_t base_ia_multi_vgt_param;
1171 bool wd_switch_on_eop;
1172 bool ia_switch_on_eoi;
1173 bool partial_vs_wave;
1174 uint8_t vtx_emit_num;
1175 uint32_t vtx_reuse_depth;
1176 struct radv_prim_vertex_count prim_vertex_count;
1177 bool can_use_guardband;
1178 } graphics;
1179 };
1180
1181 unsigned max_waves;
1182 unsigned scratch_bytes_per_wave;
1183 };
1184
1185 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1186 {
1187 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1188 }
1189
1190 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1191 {
1192 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1193 }
1194
1195 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1196 gl_shader_stage stage,
1197 int idx);
1198
1199 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1200
1201 struct radv_graphics_pipeline_create_info {
1202 bool use_rectlist;
1203 bool db_depth_clear;
1204 bool db_stencil_clear;
1205 bool db_depth_disable_expclear;
1206 bool db_stencil_disable_expclear;
1207 bool db_flush_depth_inplace;
1208 bool db_flush_stencil_inplace;
1209 bool db_resummarize;
1210 uint32_t custom_blend_mode;
1211 };
1212
1213 VkResult
1214 radv_graphics_pipeline_create(VkDevice device,
1215 VkPipelineCache cache,
1216 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1217 const struct radv_graphics_pipeline_create_info *extra,
1218 const VkAllocationCallbacks *alloc,
1219 VkPipeline *pPipeline);
1220
1221 struct vk_format_description;
1222 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1223 int first_non_void);
1224 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1225 int first_non_void);
1226 uint32_t radv_translate_colorformat(VkFormat format);
1227 uint32_t radv_translate_color_numformat(VkFormat format,
1228 const struct vk_format_description *desc,
1229 int first_non_void);
1230 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1231 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1232 uint32_t radv_translate_dbformat(VkFormat format);
1233 uint32_t radv_translate_tex_dataformat(VkFormat format,
1234 const struct vk_format_description *desc,
1235 int first_non_void);
1236 uint32_t radv_translate_tex_numformat(VkFormat format,
1237 const struct vk_format_description *desc,
1238 int first_non_void);
1239 bool radv_format_pack_clear_color(VkFormat format,
1240 uint32_t clear_vals[2],
1241 VkClearColorValue *value);
1242 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1243 bool radv_dcc_formats_compatible(VkFormat format1,
1244 VkFormat format2);
1245
1246 struct radv_fmask_info {
1247 uint64_t offset;
1248 uint64_t size;
1249 unsigned alignment;
1250 unsigned pitch_in_pixels;
1251 unsigned bank_height;
1252 unsigned slice_tile_max;
1253 unsigned tile_mode_index;
1254 unsigned tile_swizzle;
1255 };
1256
1257 struct radv_cmask_info {
1258 uint64_t offset;
1259 uint64_t size;
1260 unsigned alignment;
1261 unsigned slice_tile_max;
1262 };
1263
1264 struct radv_image {
1265 VkImageType type;
1266 /* The original VkFormat provided by the client. This may not match any
1267 * of the actual surface formats.
1268 */
1269 VkFormat vk_format;
1270 VkImageAspectFlags aspects;
1271 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1272 struct ac_surf_info info;
1273 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1274 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1275
1276 VkDeviceSize size;
1277 uint32_t alignment;
1278
1279 unsigned queue_family_mask;
1280 bool exclusive;
1281 bool shareable;
1282
1283 /* Set when bound */
1284 struct radeon_winsys_bo *bo;
1285 VkDeviceSize offset;
1286 uint64_t dcc_offset;
1287 uint64_t htile_offset;
1288 bool tc_compatible_htile;
1289 struct radeon_surf surface;
1290
1291 struct radv_fmask_info fmask;
1292 struct radv_cmask_info cmask;
1293 uint64_t clear_value_offset;
1294 uint64_t dcc_pred_offset;
1295 };
1296
1297 /* Whether the image has a htile that is known consistent with the contents of
1298 * the image. */
1299 bool radv_layout_has_htile(const struct radv_image *image,
1300 VkImageLayout layout,
1301 unsigned queue_mask);
1302
1303 /* Whether the image has a htile that is known consistent with the contents of
1304 * the image and is allowed to be in compressed form.
1305 *
1306 * If this is false reads that don't use the htile should be able to return
1307 * correct results.
1308 */
1309 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1310 VkImageLayout layout,
1311 unsigned queue_mask);
1312
1313 bool radv_layout_can_fast_clear(const struct radv_image *image,
1314 VkImageLayout layout,
1315 unsigned queue_mask);
1316
1317 static inline bool
1318 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1319 {
1320 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1321 }
1322
1323 static inline bool
1324 radv_htile_enabled(const struct radv_image *image, unsigned level)
1325 {
1326 return image->surface.htile_size && level == 0;
1327 }
1328
1329 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1330
1331 static inline uint32_t
1332 radv_get_layerCount(const struct radv_image *image,
1333 const VkImageSubresourceRange *range)
1334 {
1335 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1336 image->info.array_size - range->baseArrayLayer : range->layerCount;
1337 }
1338
1339 static inline uint32_t
1340 radv_get_levelCount(const struct radv_image *image,
1341 const VkImageSubresourceRange *range)
1342 {
1343 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1344 image->info.levels - range->baseMipLevel : range->levelCount;
1345 }
1346
1347 struct radeon_bo_metadata;
1348 void
1349 radv_init_metadata(struct radv_device *device,
1350 struct radv_image *image,
1351 struct radeon_bo_metadata *metadata);
1352
1353 struct radv_image_view {
1354 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1355 struct radeon_winsys_bo *bo;
1356
1357 VkImageViewType type;
1358 VkImageAspectFlags aspect_mask;
1359 VkFormat vk_format;
1360 uint32_t base_layer;
1361 uint32_t layer_count;
1362 uint32_t base_mip;
1363 uint32_t level_count;
1364 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1365
1366 uint32_t descriptor[16];
1367
1368 /* Descriptor for use as a storage image as opposed to a sampled image.
1369 * This has a few differences for cube maps (e.g. type).
1370 */
1371 uint32_t storage_descriptor[16];
1372 };
1373
1374 struct radv_image_create_info {
1375 const VkImageCreateInfo *vk_info;
1376 bool scanout;
1377 };
1378
1379 VkResult radv_image_create(VkDevice _device,
1380 const struct radv_image_create_info *info,
1381 const VkAllocationCallbacks* alloc,
1382 VkImage *pImage);
1383
1384 void radv_image_view_init(struct radv_image_view *view,
1385 struct radv_device *device,
1386 const VkImageViewCreateInfo* pCreateInfo);
1387
1388 struct radv_buffer_view {
1389 struct radeon_winsys_bo *bo;
1390 VkFormat vk_format;
1391 uint64_t range; /**< VkBufferViewCreateInfo::range */
1392 uint32_t state[4];
1393 };
1394 void radv_buffer_view_init(struct radv_buffer_view *view,
1395 struct radv_device *device,
1396 const VkBufferViewCreateInfo* pCreateInfo);
1397
1398 static inline struct VkExtent3D
1399 radv_sanitize_image_extent(const VkImageType imageType,
1400 const struct VkExtent3D imageExtent)
1401 {
1402 switch (imageType) {
1403 case VK_IMAGE_TYPE_1D:
1404 return (VkExtent3D) { imageExtent.width, 1, 1 };
1405 case VK_IMAGE_TYPE_2D:
1406 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1407 case VK_IMAGE_TYPE_3D:
1408 return imageExtent;
1409 default:
1410 unreachable("invalid image type");
1411 }
1412 }
1413
1414 static inline struct VkOffset3D
1415 radv_sanitize_image_offset(const VkImageType imageType,
1416 const struct VkOffset3D imageOffset)
1417 {
1418 switch (imageType) {
1419 case VK_IMAGE_TYPE_1D:
1420 return (VkOffset3D) { imageOffset.x, 0, 0 };
1421 case VK_IMAGE_TYPE_2D:
1422 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1423 case VK_IMAGE_TYPE_3D:
1424 return imageOffset;
1425 default:
1426 unreachable("invalid image type");
1427 }
1428 }
1429
1430 static inline bool
1431 radv_image_extent_compare(const struct radv_image *image,
1432 const VkExtent3D *extent)
1433 {
1434 if (extent->width != image->info.width ||
1435 extent->height != image->info.height ||
1436 extent->depth != image->info.depth)
1437 return false;
1438 return true;
1439 }
1440
1441 struct radv_sampler {
1442 uint32_t state[4];
1443 };
1444
1445 struct radv_color_buffer_info {
1446 uint64_t cb_color_base;
1447 uint64_t cb_color_cmask;
1448 uint64_t cb_color_fmask;
1449 uint64_t cb_dcc_base;
1450 uint32_t cb_color_pitch;
1451 uint32_t cb_color_slice;
1452 uint32_t cb_color_view;
1453 uint32_t cb_color_info;
1454 uint32_t cb_color_attrib;
1455 uint32_t cb_color_attrib2;
1456 uint32_t cb_dcc_control;
1457 uint32_t cb_color_cmask_slice;
1458 uint32_t cb_color_fmask_slice;
1459 uint32_t cb_clear_value0;
1460 uint32_t cb_clear_value1;
1461 };
1462
1463 struct radv_ds_buffer_info {
1464 uint64_t db_z_read_base;
1465 uint64_t db_stencil_read_base;
1466 uint64_t db_z_write_base;
1467 uint64_t db_stencil_write_base;
1468 uint64_t db_htile_data_base;
1469 uint32_t db_depth_info;
1470 uint32_t db_z_info;
1471 uint32_t db_stencil_info;
1472 uint32_t db_depth_view;
1473 uint32_t db_depth_size;
1474 uint32_t db_depth_slice;
1475 uint32_t db_htile_surface;
1476 uint32_t pa_su_poly_offset_db_fmt_cntl;
1477 uint32_t db_z_info2;
1478 uint32_t db_stencil_info2;
1479 float offset_scale;
1480 };
1481
1482 struct radv_attachment_info {
1483 union {
1484 struct radv_color_buffer_info cb;
1485 struct radv_ds_buffer_info ds;
1486 };
1487 struct radv_image_view *attachment;
1488 };
1489
1490 struct radv_framebuffer {
1491 uint32_t width;
1492 uint32_t height;
1493 uint32_t layers;
1494
1495 uint32_t attachment_count;
1496 struct radv_attachment_info attachments[0];
1497 };
1498
1499 struct radv_subpass_barrier {
1500 VkPipelineStageFlags src_stage_mask;
1501 VkAccessFlags src_access_mask;
1502 VkAccessFlags dst_access_mask;
1503 };
1504
1505 struct radv_subpass {
1506 uint32_t input_count;
1507 uint32_t color_count;
1508 VkAttachmentReference * input_attachments;
1509 VkAttachmentReference * color_attachments;
1510 VkAttachmentReference * resolve_attachments;
1511 VkAttachmentReference depth_stencil_attachment;
1512
1513 /** Subpass has at least one resolve attachment */
1514 bool has_resolve;
1515
1516 struct radv_subpass_barrier start_barrier;
1517
1518 uint32_t view_mask;
1519 };
1520
1521 struct radv_render_pass_attachment {
1522 VkFormat format;
1523 uint32_t samples;
1524 VkAttachmentLoadOp load_op;
1525 VkAttachmentLoadOp stencil_load_op;
1526 VkImageLayout initial_layout;
1527 VkImageLayout final_layout;
1528 uint32_t view_mask;
1529 };
1530
1531 struct radv_render_pass {
1532 uint32_t attachment_count;
1533 uint32_t subpass_count;
1534 VkAttachmentReference * subpass_attachments;
1535 struct radv_render_pass_attachment * attachments;
1536 struct radv_subpass_barrier end_barrier;
1537 struct radv_subpass subpasses[0];
1538 };
1539
1540 VkResult radv_device_init_meta(struct radv_device *device);
1541 void radv_device_finish_meta(struct radv_device *device);
1542
1543 struct radv_query_pool {
1544 struct radeon_winsys_bo *bo;
1545 uint32_t stride;
1546 uint32_t availability_offset;
1547 char *ptr;
1548 VkQueryType type;
1549 uint32_t pipeline_stats_mask;
1550 };
1551
1552 struct radv_semaphore {
1553 /* use a winsys sem for non-exportable */
1554 struct radeon_winsys_sem *sem;
1555 uint32_t syncobj;
1556 uint32_t temp_syncobj;
1557 };
1558
1559 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1560 int num_wait_sems,
1561 const VkSemaphore *wait_sems,
1562 int num_signal_sems,
1563 const VkSemaphore *signal_sems,
1564 VkFence fence);
1565 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1566
1567 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1568 struct radv_descriptor_set *set,
1569 unsigned idx);
1570
1571 void
1572 radv_update_descriptor_sets(struct radv_device *device,
1573 struct radv_cmd_buffer *cmd_buffer,
1574 VkDescriptorSet overrideSet,
1575 uint32_t descriptorWriteCount,
1576 const VkWriteDescriptorSet *pDescriptorWrites,
1577 uint32_t descriptorCopyCount,
1578 const VkCopyDescriptorSet *pDescriptorCopies);
1579
1580 void
1581 radv_update_descriptor_set_with_template(struct radv_device *device,
1582 struct radv_cmd_buffer *cmd_buffer,
1583 struct radv_descriptor_set *set,
1584 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1585 const void *pData);
1586
1587 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1588 VkPipelineBindPoint pipelineBindPoint,
1589 VkPipelineLayout _layout,
1590 uint32_t set,
1591 uint32_t descriptorWriteCount,
1592 const VkWriteDescriptorSet *pDescriptorWrites);
1593
1594 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1595 struct radv_image *image, uint32_t value);
1596 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1597 struct radv_image *image, uint32_t value);
1598
1599 struct radv_fence {
1600 struct radeon_winsys_fence *fence;
1601 bool submitted;
1602 bool signalled;
1603
1604 uint32_t syncobj;
1605 uint32_t temp_syncobj;
1606 };
1607
1608 struct radeon_winsys_sem;
1609
1610 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1611 \
1612 static inline struct __radv_type * \
1613 __radv_type ## _from_handle(__VkType _handle) \
1614 { \
1615 return (struct __radv_type *) _handle; \
1616 } \
1617 \
1618 static inline __VkType \
1619 __radv_type ## _to_handle(struct __radv_type *_obj) \
1620 { \
1621 return (__VkType) _obj; \
1622 }
1623
1624 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1625 \
1626 static inline struct __radv_type * \
1627 __radv_type ## _from_handle(__VkType _handle) \
1628 { \
1629 return (struct __radv_type *)(uintptr_t) _handle; \
1630 } \
1631 \
1632 static inline __VkType \
1633 __radv_type ## _to_handle(struct __radv_type *_obj) \
1634 { \
1635 return (__VkType)(uintptr_t) _obj; \
1636 }
1637
1638 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1639 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1640
1641 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1642 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1643 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1644 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1645 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1646
1647 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1648 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1649 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1650 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1651 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1652 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1653 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1654 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1655 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1656 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1657 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1658 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1659 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1660 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1661 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1662 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1663 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1664 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1665 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1666 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1667 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1668
1669 #endif /* RADV_PRIVATE_H */