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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102 #define MAX_SO_STREAMS 4
103 #define MAX_SO_BUFFERS 4
104 #define MAX_SO_OUTPUTS 64
105
106 #define NUM_DEPTH_CLEAR_PIPELINES 3
107
108 /*
109 * This is the point we switch from using CP to compute shader
110 * for certain buffer operations.
111 */
112 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113
114 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
115
116 enum radv_mem_heap {
117 RADV_MEM_HEAP_VRAM,
118 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
119 RADV_MEM_HEAP_GTT,
120 RADV_MEM_HEAP_COUNT
121 };
122
123 enum radv_mem_type {
124 RADV_MEM_TYPE_VRAM,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
127 RADV_MEM_TYPE_GTT_CACHED,
128 RADV_MEM_TYPE_COUNT
129 };
130
131 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
132
133 static inline uint32_t
134 align_u32(uint32_t v, uint32_t a)
135 {
136 assert(a != 0 && a == (a & -a));
137 return (v + a - 1) & ~(a - 1);
138 }
139
140 static inline uint32_t
141 align_u32_npot(uint32_t v, uint32_t a)
142 {
143 return (v + a - 1) / a * a;
144 }
145
146 static inline uint64_t
147 align_u64(uint64_t v, uint64_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 static inline int32_t
154 align_i32(int32_t v, int32_t a)
155 {
156 assert(a != 0 && a == (a & -a));
157 return (v + a - 1) & ~(a - 1);
158 }
159
160 /** Alignment must be a power of 2. */
161 static inline bool
162 radv_is_aligned(uintmax_t n, uintmax_t a)
163 {
164 assert(a == (a & -a));
165 return (n & (a - 1)) == 0;
166 }
167
168 static inline uint32_t
169 round_up_u32(uint32_t v, uint32_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint64_t
175 round_up_u64(uint64_t v, uint64_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint32_t
181 radv_minify(uint32_t n, uint32_t levels)
182 {
183 if (unlikely(n == 0))
184 return 0;
185 else
186 return MAX2(n >> levels, 1);
187 }
188 static inline float
189 radv_clamp_f(float f, float min, float max)
190 {
191 assert(min < max);
192
193 if (f > max)
194 return max;
195 else if (f < min)
196 return min;
197 else
198 return f;
199 }
200
201 static inline bool
202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
203 {
204 if (*inout_mask & clear_mask) {
205 *inout_mask &= ~clear_mask;
206 return true;
207 } else {
208 return false;
209 }
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Whenever we generate an error, pass it through this function. Useful for
223 * debugging, where we can break on it. Only call at error site, not when
224 * propagating errors. Might be useful to plug in a stack trace here.
225 */
226
227 struct radv_instance;
228
229 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
230
231 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
232 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
233
234 void __radv_finishme(const char *file, int line, const char *format, ...)
235 radv_printflike(3, 4);
236 void radv_loge(const char *format, ...) radv_printflike(1, 2);
237 void radv_loge_v(const char *format, va_list va);
238 void radv_logi(const char *format, ...) radv_printflike(1, 2);
239 void radv_logi_v(const char *format, va_list va);
240
241 /**
242 * Print a FINISHME message, including its source location.
243 */
244 #define radv_finishme(format, ...) \
245 do { \
246 static bool reported = false; \
247 if (!reported) { \
248 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 reported = true; \
250 } \
251 } while (0)
252
253 /* A non-fatal assert. Useful for debugging. */
254 #ifdef DEBUG
255 #define radv_assert(x) ({ \
256 if (unlikely(!(x))) \
257 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
258 })
259 #else
260 #define radv_assert(x)
261 #endif
262
263 #define stub_return(v) \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return (v); \
267 } while (0)
268
269 #define stub() \
270 do { \
271 radv_finishme("stub %s", __func__); \
272 return; \
273 } while (0)
274
275 void *radv_lookup_entrypoint_unchecked(const char *name);
276 void *radv_lookup_entrypoint_checked(const char *name,
277 uint32_t core_version,
278 const struct radv_instance_extension_table *instance,
279 const struct radv_device_extension_table *device);
280
281 struct radv_physical_device {
282 VK_LOADER_DATA _loader_data;
283
284 struct radv_instance * instance;
285
286 struct radeon_winsys *ws;
287 struct radeon_info rad_info;
288 char path[20];
289 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
290 uint8_t driver_uuid[VK_UUID_SIZE];
291 uint8_t device_uuid[VK_UUID_SIZE];
292 uint8_t cache_uuid[VK_UUID_SIZE];
293
294 int local_fd;
295 int master_fd;
296 struct wsi_device wsi_device;
297
298 bool has_rbplus; /* if RB+ register exist */
299 bool rbplus_allowed; /* if RB+ is allowed */
300 bool has_clear_state;
301 bool cpdma_prefetch_writes_memory;
302 bool has_scissor_bug;
303
304 bool has_out_of_order_rast;
305 bool out_of_order_rast_allowed;
306
307 /* Whether DCC should be enabled for MSAA textures. */
308 bool dcc_msaa_allowed;
309
310 /* This is the drivers on-disk cache used as a fallback as opposed to
311 * the pipeline cache defined by apps.
312 */
313 struct disk_cache * disk_cache;
314
315 VkPhysicalDeviceMemoryProperties memory_properties;
316 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
317
318 drmPciBusInfo bus_info;
319
320 struct radv_device_extension_table supported_extensions;
321 };
322
323 struct radv_instance {
324 VK_LOADER_DATA _loader_data;
325
326 VkAllocationCallbacks alloc;
327
328 uint32_t apiVersion;
329 int physicalDeviceCount;
330 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
331
332 uint64_t debug_flags;
333 uint64_t perftest_flags;
334
335 struct vk_debug_report_instance debug_report_callbacks;
336
337 struct radv_instance_extension_table enabled_extensions;
338 };
339
340 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
341 void radv_finish_wsi(struct radv_physical_device *physical_device);
342
343 bool radv_instance_extension_supported(const char *name);
344 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
345 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
346 const char *name);
347
348 struct cache_entry;
349
350 struct radv_pipeline_cache {
351 struct radv_device * device;
352 pthread_mutex_t mutex;
353
354 uint32_t total_size;
355 uint32_t table_size;
356 uint32_t kernel_count;
357 struct cache_entry ** hash_table;
358 bool modified;
359
360 VkAllocationCallbacks alloc;
361 };
362
363 struct radv_pipeline_key {
364 uint32_t instance_rate_inputs;
365 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
366 uint64_t vertex_alpha_adjust;
367 unsigned tess_input_vertices;
368 uint32_t col_format;
369 uint32_t is_int8;
370 uint32_t is_int10;
371 uint8_t log2_ps_iter_samples;
372 uint8_t num_samples;
373 uint32_t has_multiview_view_index : 1;
374 uint32_t optimisations_disabled : 1;
375 };
376
377 void
378 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
379 struct radv_device *device);
380 void
381 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
382 bool
383 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
384 const void *data, size_t size);
385
386 struct radv_shader_variant;
387
388 bool
389 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
390 struct radv_pipeline_cache *cache,
391 const unsigned char *sha1,
392 struct radv_shader_variant **variants);
393
394 void
395 radv_pipeline_cache_insert_shaders(struct radv_device *device,
396 struct radv_pipeline_cache *cache,
397 const unsigned char *sha1,
398 struct radv_shader_variant **variants,
399 const void *const *codes,
400 const unsigned *code_sizes);
401
402 enum radv_blit_ds_layout {
403 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
404 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
405 RADV_BLIT_DS_LAYOUT_COUNT,
406 };
407
408 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
409 {
410 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
411 }
412
413 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
414 {
415 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
416 }
417
418 enum radv_meta_dst_layout {
419 RADV_META_DST_LAYOUT_GENERAL,
420 RADV_META_DST_LAYOUT_OPTIMAL,
421 RADV_META_DST_LAYOUT_COUNT,
422 };
423
424 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
425 {
426 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
427 }
428
429 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
430 {
431 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
432 }
433
434 struct radv_meta_state {
435 VkAllocationCallbacks alloc;
436
437 struct radv_pipeline_cache cache;
438
439 /*
440 * For on-demand pipeline creation, makes sure that
441 * only one thread tries to build a pipeline at the same time.
442 */
443 mtx_t mtx;
444
445 /**
446 * Use array element `i` for images with `2^i` samples.
447 */
448 struct {
449 VkRenderPass render_pass[NUM_META_FS_KEYS];
450 VkPipeline color_pipelines[NUM_META_FS_KEYS];
451
452 VkRenderPass depthstencil_rp;
453 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
454 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
455 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
456 } clear[1 + MAX_SAMPLES_LOG2];
457
458 VkPipelineLayout clear_color_p_layout;
459 VkPipelineLayout clear_depth_p_layout;
460 struct {
461 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
462
463 /** Pipeline that blits from a 1D image. */
464 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
465
466 /** Pipeline that blits from a 2D image. */
467 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
468
469 /** Pipeline that blits from a 3D image. */
470 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
471
472 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
473 VkPipeline depth_only_1d_pipeline;
474 VkPipeline depth_only_2d_pipeline;
475 VkPipeline depth_only_3d_pipeline;
476
477 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
478 VkPipeline stencil_only_1d_pipeline;
479 VkPipeline stencil_only_2d_pipeline;
480 VkPipeline stencil_only_3d_pipeline;
481 VkPipelineLayout pipeline_layout;
482 VkDescriptorSetLayout ds_layout;
483 } blit;
484
485 struct {
486 VkPipelineLayout p_layouts[5];
487 VkDescriptorSetLayout ds_layouts[5];
488 VkPipeline pipelines[5][NUM_META_FS_KEYS];
489
490 VkPipeline depth_only_pipeline[5];
491
492 VkPipeline stencil_only_pipeline[5];
493 } blit2d[1 + MAX_SAMPLES_LOG2];
494
495 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
496 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
497 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
498
499 struct {
500 VkPipelineLayout img_p_layout;
501 VkDescriptorSetLayout img_ds_layout;
502 VkPipeline pipeline;
503 VkPipeline pipeline_3d;
504 } itob;
505 struct {
506 VkPipelineLayout img_p_layout;
507 VkDescriptorSetLayout img_ds_layout;
508 VkPipeline pipeline;
509 VkPipeline pipeline_3d;
510 } btoi;
511 struct {
512 VkPipelineLayout img_p_layout;
513 VkDescriptorSetLayout img_ds_layout;
514 VkPipeline pipeline;
515 } btoi_r32g32b32;
516 struct {
517 VkPipelineLayout img_p_layout;
518 VkDescriptorSetLayout img_ds_layout;
519 VkPipeline pipeline;
520 VkPipeline pipeline_3d;
521 } itoi;
522 struct {
523 VkPipelineLayout img_p_layout;
524 VkDescriptorSetLayout img_ds_layout;
525 VkPipeline pipeline;
526 } itoi_r32g32b32;
527 struct {
528 VkPipelineLayout img_p_layout;
529 VkDescriptorSetLayout img_ds_layout;
530 VkPipeline pipeline;
531 VkPipeline pipeline_3d;
532 } cleari;
533 struct {
534 VkPipelineLayout img_p_layout;
535 VkDescriptorSetLayout img_ds_layout;
536 VkPipeline pipeline;
537 } cleari_r32g32b32;
538
539 struct {
540 VkPipelineLayout p_layout;
541 VkPipeline pipeline[NUM_META_FS_KEYS];
542 VkRenderPass pass[NUM_META_FS_KEYS];
543 } resolve;
544
545 struct {
546 VkDescriptorSetLayout ds_layout;
547 VkPipelineLayout p_layout;
548 struct {
549 VkPipeline pipeline;
550 VkPipeline i_pipeline;
551 VkPipeline srgb_pipeline;
552 } rc[MAX_SAMPLES_LOG2];
553 } resolve_compute;
554
555 struct {
556 VkDescriptorSetLayout ds_layout;
557 VkPipelineLayout p_layout;
558
559 struct {
560 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
561 VkPipeline pipeline[NUM_META_FS_KEYS];
562 } rc[MAX_SAMPLES_LOG2];
563 } resolve_fragment;
564
565 struct {
566 VkPipelineLayout p_layout;
567 VkPipeline decompress_pipeline;
568 VkPipeline resummarize_pipeline;
569 VkRenderPass pass;
570 } depth_decomp[1 + MAX_SAMPLES_LOG2];
571
572 struct {
573 VkPipelineLayout p_layout;
574 VkPipeline cmask_eliminate_pipeline;
575 VkPipeline fmask_decompress_pipeline;
576 VkPipeline dcc_decompress_pipeline;
577 VkRenderPass pass;
578
579 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
580 VkPipelineLayout dcc_decompress_compute_p_layout;
581 VkPipeline dcc_decompress_compute_pipeline;
582 } fast_clear_flush;
583
584 struct {
585 VkPipelineLayout fill_p_layout;
586 VkPipelineLayout copy_p_layout;
587 VkDescriptorSetLayout fill_ds_layout;
588 VkDescriptorSetLayout copy_ds_layout;
589 VkPipeline fill_pipeline;
590 VkPipeline copy_pipeline;
591 } buffer;
592
593 struct {
594 VkDescriptorSetLayout ds_layout;
595 VkPipelineLayout p_layout;
596 VkPipeline occlusion_query_pipeline;
597 VkPipeline pipeline_statistics_query_pipeline;
598 VkPipeline tfb_query_pipeline;
599 } query;
600 };
601
602 /* queue types */
603 #define RADV_QUEUE_GENERAL 0
604 #define RADV_QUEUE_COMPUTE 1
605 #define RADV_QUEUE_TRANSFER 2
606
607 #define RADV_MAX_QUEUE_FAMILIES 3
608
609 enum ring_type radv_queue_family_to_ring(int f);
610
611 struct radv_queue {
612 VK_LOADER_DATA _loader_data;
613 struct radv_device * device;
614 struct radeon_winsys_ctx *hw_ctx;
615 enum radeon_ctx_priority priority;
616 uint32_t queue_family_index;
617 int queue_idx;
618 VkDeviceQueueCreateFlags flags;
619
620 uint32_t scratch_size;
621 uint32_t compute_scratch_size;
622 uint32_t esgs_ring_size;
623 uint32_t gsvs_ring_size;
624 bool has_tess_rings;
625 bool has_sample_positions;
626
627 struct radeon_winsys_bo *scratch_bo;
628 struct radeon_winsys_bo *descriptor_bo;
629 struct radeon_winsys_bo *compute_scratch_bo;
630 struct radeon_winsys_bo *esgs_ring_bo;
631 struct radeon_winsys_bo *gsvs_ring_bo;
632 struct radeon_winsys_bo *tess_rings_bo;
633 struct radeon_cmdbuf *initial_preamble_cs;
634 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
635 struct radeon_cmdbuf *continue_preamble_cs;
636 };
637
638 struct radv_bo_list {
639 struct radv_winsys_bo_list list;
640 unsigned capacity;
641 pthread_mutex_t mutex;
642 };
643
644 struct radv_device {
645 VK_LOADER_DATA _loader_data;
646
647 VkAllocationCallbacks alloc;
648
649 struct radv_instance * instance;
650 struct radeon_winsys *ws;
651
652 struct radv_meta_state meta_state;
653
654 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
655 int queue_count[RADV_MAX_QUEUE_FAMILIES];
656 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
657
658 bool always_use_syncobj;
659 bool has_distributed_tess;
660 bool pbb_allowed;
661 bool dfsm_allowed;
662 uint32_t tess_offchip_block_dw_size;
663 uint32_t scratch_waves;
664 uint32_t dispatch_initiator;
665
666 uint32_t gs_table_depth;
667
668 /* MSAA sample locations.
669 * The first index is the sample index.
670 * The second index is the coordinate: X, Y. */
671 float sample_locations_1x[1][2];
672 float sample_locations_2x[2][2];
673 float sample_locations_4x[4][2];
674 float sample_locations_8x[8][2];
675 float sample_locations_16x[16][2];
676
677 /* CIK and later */
678 uint32_t gfx_init_size_dw;
679 struct radeon_winsys_bo *gfx_init;
680
681 struct radeon_winsys_bo *trace_bo;
682 uint32_t *trace_id_ptr;
683
684 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
685 bool keep_shader_info;
686
687 struct radv_physical_device *physical_device;
688
689 /* Backup in-memory cache to be used if the app doesn't provide one */
690 struct radv_pipeline_cache * mem_cache;
691
692 /*
693 * use different counters so MSAA MRTs get consecutive surface indices,
694 * even if MASK is allocated in between.
695 */
696 uint32_t image_mrt_offset_counter;
697 uint32_t fmask_mrt_offset_counter;
698 struct list_head shader_slabs;
699 mtx_t shader_slab_mutex;
700
701 /* For detecting VM faults reported by dmesg. */
702 uint64_t dmesg_timestamp;
703
704 struct radv_device_extension_table enabled_extensions;
705
706 /* Whether the driver uses a global BO list. */
707 bool use_global_bo_list;
708
709 struct radv_bo_list bo_list;
710
711 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
712 int force_aniso;
713 };
714
715 struct radv_device_memory {
716 struct radeon_winsys_bo *bo;
717 /* for dedicated allocations */
718 struct radv_image *image;
719 struct radv_buffer *buffer;
720 uint32_t type_index;
721 VkDeviceSize map_size;
722 void * map;
723 void * user_ptr;
724 };
725
726
727 struct radv_descriptor_range {
728 uint64_t va;
729 uint32_t size;
730 };
731
732 struct radv_descriptor_set {
733 const struct radv_descriptor_set_layout *layout;
734 uint32_t size;
735
736 struct radeon_winsys_bo *bo;
737 uint64_t va;
738 uint32_t *mapped_ptr;
739 struct radv_descriptor_range *dynamic_descriptors;
740
741 struct radeon_winsys_bo *descriptors[0];
742 };
743
744 struct radv_push_descriptor_set
745 {
746 struct radv_descriptor_set set;
747 uint32_t capacity;
748 };
749
750 struct radv_descriptor_pool_entry {
751 uint32_t offset;
752 uint32_t size;
753 struct radv_descriptor_set *set;
754 };
755
756 struct radv_descriptor_pool {
757 struct radeon_winsys_bo *bo;
758 uint8_t *mapped_ptr;
759 uint64_t current_offset;
760 uint64_t size;
761
762 uint8_t *host_memory_base;
763 uint8_t *host_memory_ptr;
764 uint8_t *host_memory_end;
765
766 uint32_t entry_count;
767 uint32_t max_entry_count;
768 struct radv_descriptor_pool_entry entries[0];
769 };
770
771 struct radv_descriptor_update_template_entry {
772 VkDescriptorType descriptor_type;
773
774 /* The number of descriptors to update */
775 uint32_t descriptor_count;
776
777 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
778 uint32_t dst_offset;
779
780 /* In dwords. Not valid/used for dynamic descriptors */
781 uint32_t dst_stride;
782
783 uint32_t buffer_offset;
784
785 /* Only valid for combined image samplers and samplers */
786 uint16_t has_sampler;
787
788 /* In bytes */
789 size_t src_offset;
790 size_t src_stride;
791
792 /* For push descriptors */
793 const uint32_t *immutable_samplers;
794 };
795
796 struct radv_descriptor_update_template {
797 uint32_t entry_count;
798 VkPipelineBindPoint bind_point;
799 struct radv_descriptor_update_template_entry entry[0];
800 };
801
802 struct radv_buffer {
803 VkDeviceSize size;
804
805 VkBufferUsageFlags usage;
806 VkBufferCreateFlags flags;
807
808 /* Set when bound */
809 struct radeon_winsys_bo * bo;
810 VkDeviceSize offset;
811
812 bool shareable;
813 };
814
815 enum radv_dynamic_state_bits {
816 RADV_DYNAMIC_VIEWPORT = 1 << 0,
817 RADV_DYNAMIC_SCISSOR = 1 << 1,
818 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
819 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
820 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
821 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
822 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
823 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
824 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
825 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
826 RADV_DYNAMIC_ALL = (1 << 10) - 1,
827 };
828
829 enum radv_cmd_dirty_bits {
830 /* Keep the dynamic state dirty bits in sync with
831 * enum radv_dynamic_state_bits */
832 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
833 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
834 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
835 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
836 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
837 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
838 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
839 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
840 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
841 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
842 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
843 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
844 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
845 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
846 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
847 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
848 };
849
850 enum radv_cmd_flush_bits {
851 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
852 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
853 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
854 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
855 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
856 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
857 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
858 /* Same as above, but only writes back and doesn't invalidate */
859 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
860 /* Framebuffer caches */
861 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
862 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
863 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
864 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
865 /* Engine synchronization. */
866 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
867 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
868 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
869 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
870 /* Pipeline query controls. */
871 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
872 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
873 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
874
875 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
876 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
877 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
878 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
879 };
880
881 struct radv_vertex_binding {
882 struct radv_buffer * buffer;
883 VkDeviceSize offset;
884 };
885
886 struct radv_streamout_binding {
887 struct radv_buffer *buffer;
888 VkDeviceSize offset;
889 VkDeviceSize size;
890 };
891
892 struct radv_streamout_state {
893 /* Mask of bound streamout buffers. */
894 uint8_t enabled_mask;
895
896 /* External state that comes from the last vertex stage, it must be
897 * set explicitely when binding a new graphics pipeline.
898 */
899 uint16_t stride_in_dw[MAX_SO_BUFFERS];
900 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
901
902 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
903 uint32_t hw_enabled_mask;
904
905 /* State of VGT_STRMOUT_(CONFIG|EN) */
906 bool streamout_enabled;
907 };
908
909 struct radv_viewport_state {
910 uint32_t count;
911 VkViewport viewports[MAX_VIEWPORTS];
912 };
913
914 struct radv_scissor_state {
915 uint32_t count;
916 VkRect2D scissors[MAX_SCISSORS];
917 };
918
919 struct radv_discard_rectangle_state {
920 uint32_t count;
921 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
922 };
923
924 struct radv_dynamic_state {
925 /**
926 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
927 * Defines the set of saved dynamic state.
928 */
929 uint32_t mask;
930
931 struct radv_viewport_state viewport;
932
933 struct radv_scissor_state scissor;
934
935 float line_width;
936
937 struct {
938 float bias;
939 float clamp;
940 float slope;
941 } depth_bias;
942
943 float blend_constants[4];
944
945 struct {
946 float min;
947 float max;
948 } depth_bounds;
949
950 struct {
951 uint32_t front;
952 uint32_t back;
953 } stencil_compare_mask;
954
955 struct {
956 uint32_t front;
957 uint32_t back;
958 } stencil_write_mask;
959
960 struct {
961 uint32_t front;
962 uint32_t back;
963 } stencil_reference;
964
965 struct radv_discard_rectangle_state discard_rectangle;
966 };
967
968 extern const struct radv_dynamic_state default_dynamic_state;
969
970 const char *
971 radv_get_debug_option_name(int id);
972
973 const char *
974 radv_get_perftest_option_name(int id);
975
976 /**
977 * Attachment state when recording a renderpass instance.
978 *
979 * The clear value is valid only if there exists a pending clear.
980 */
981 struct radv_attachment_state {
982 VkImageAspectFlags pending_clear_aspects;
983 uint32_t cleared_views;
984 VkClearValue clear_value;
985 VkImageLayout current_layout;
986 };
987
988 struct radv_descriptor_state {
989 struct radv_descriptor_set *sets[MAX_SETS];
990 uint32_t dirty;
991 uint32_t valid;
992 struct radv_push_descriptor_set push_set;
993 bool push_dirty;
994 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
995 };
996
997 struct radv_cmd_state {
998 /* Vertex descriptors */
999 uint64_t vb_va;
1000 unsigned vb_size;
1001
1002 bool predicating;
1003 uint32_t dirty;
1004
1005 uint32_t prefetch_L2_mask;
1006
1007 struct radv_pipeline * pipeline;
1008 struct radv_pipeline * emitted_pipeline;
1009 struct radv_pipeline * compute_pipeline;
1010 struct radv_pipeline * emitted_compute_pipeline;
1011 struct radv_framebuffer * framebuffer;
1012 struct radv_render_pass * pass;
1013 const struct radv_subpass * subpass;
1014 struct radv_dynamic_state dynamic;
1015 struct radv_attachment_state * attachments;
1016 struct radv_streamout_state streamout;
1017 VkRect2D render_area;
1018
1019 /* Index buffer */
1020 struct radv_buffer *index_buffer;
1021 uint64_t index_offset;
1022 uint32_t index_type;
1023 uint32_t max_index_count;
1024 uint64_t index_va;
1025 int32_t last_index_type;
1026
1027 int32_t last_primitive_reset_en;
1028 uint32_t last_primitive_reset_index;
1029 enum radv_cmd_flush_bits flush_bits;
1030 unsigned active_occlusion_queries;
1031 bool perfect_occlusion_queries_enabled;
1032 unsigned active_pipeline_queries;
1033 float offset_scale;
1034 uint32_t trace_id;
1035 uint32_t last_ia_multi_vgt_param;
1036
1037 uint32_t last_num_instances;
1038 uint32_t last_first_instance;
1039 uint32_t last_vertex_offset;
1040
1041 /* Whether CP DMA is busy/idle. */
1042 bool dma_is_busy;
1043
1044 /* Conditional rendering info. */
1045 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1046 uint64_t predication_va;
1047 };
1048
1049 struct radv_cmd_pool {
1050 VkAllocationCallbacks alloc;
1051 struct list_head cmd_buffers;
1052 struct list_head free_cmd_buffers;
1053 uint32_t queue_family_index;
1054 };
1055
1056 struct radv_cmd_buffer_upload {
1057 uint8_t *map;
1058 unsigned offset;
1059 uint64_t size;
1060 struct radeon_winsys_bo *upload_bo;
1061 struct list_head list;
1062 };
1063
1064 enum radv_cmd_buffer_status {
1065 RADV_CMD_BUFFER_STATUS_INVALID,
1066 RADV_CMD_BUFFER_STATUS_INITIAL,
1067 RADV_CMD_BUFFER_STATUS_RECORDING,
1068 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1069 RADV_CMD_BUFFER_STATUS_PENDING,
1070 };
1071
1072 struct radv_cmd_buffer {
1073 VK_LOADER_DATA _loader_data;
1074
1075 struct radv_device * device;
1076
1077 struct radv_cmd_pool * pool;
1078 struct list_head pool_link;
1079
1080 VkCommandBufferUsageFlags usage_flags;
1081 VkCommandBufferLevel level;
1082 enum radv_cmd_buffer_status status;
1083 struct radeon_cmdbuf *cs;
1084 struct radv_cmd_state state;
1085 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1086 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1087 uint32_t queue_family_index;
1088
1089 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1090 VkShaderStageFlags push_constant_stages;
1091 struct radv_descriptor_set meta_push_descriptors;
1092
1093 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1094
1095 struct radv_cmd_buffer_upload upload;
1096
1097 uint32_t scratch_size_needed;
1098 uint32_t compute_scratch_size_needed;
1099 uint32_t esgs_ring_size_needed;
1100 uint32_t gsvs_ring_size_needed;
1101 bool tess_rings_needed;
1102 bool sample_positions_needed;
1103
1104 VkResult record_result;
1105
1106 uint32_t gfx9_fence_offset;
1107 struct radeon_winsys_bo *gfx9_fence_bo;
1108 uint32_t gfx9_fence_idx;
1109 uint64_t gfx9_eop_bug_va;
1110
1111 /**
1112 * Whether a query pool has been resetted and we have to flush caches.
1113 */
1114 bool pending_reset_query;
1115 };
1116
1117 struct radv_image;
1118
1119 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1120
1121 void si_emit_graphics(struct radv_physical_device *physical_device,
1122 struct radeon_cmdbuf *cs);
1123 void si_emit_compute(struct radv_physical_device *physical_device,
1124 struct radeon_cmdbuf *cs);
1125
1126 void cik_create_gfx_config(struct radv_device *device);
1127
1128 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1129 int count, const VkViewport *viewports);
1130 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1131 int count, const VkRect2D *scissors,
1132 const VkViewport *viewports, bool can_use_guardband);
1133 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1134 bool instanced_draw, bool indirect_draw,
1135 uint32_t draw_vertex_count);
1136 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1137 enum chip_class chip_class,
1138 bool is_mec,
1139 unsigned event, unsigned event_flags,
1140 unsigned data_sel,
1141 uint64_t va,
1142 uint32_t old_fence,
1143 uint32_t new_fence,
1144 uint64_t gfx9_eop_bug_va);
1145
1146 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1147 uint32_t ref, uint32_t mask);
1148 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1149 enum chip_class chip_class,
1150 uint32_t *fence_ptr, uint64_t va,
1151 bool is_mec,
1152 enum radv_cmd_flush_bits flush_bits,
1153 uint64_t gfx9_eop_bug_va);
1154 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1155 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1156 bool inverted, uint64_t va);
1157 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1158 uint64_t src_va, uint64_t dest_va,
1159 uint64_t size);
1160 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1161 unsigned size);
1162 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1163 uint64_t size, unsigned value);
1164 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1165
1166 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1167 bool
1168 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1169 unsigned size,
1170 unsigned alignment,
1171 unsigned *out_offset,
1172 void **ptr);
1173 void
1174 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1175 const struct radv_subpass *subpass,
1176 bool transitions);
1177 bool
1178 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1179 unsigned size, unsigned alignmnet,
1180 const void *data, unsigned *out_offset);
1181
1182 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1183 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1184 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1185 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1186 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1187 unsigned radv_cayman_get_maxdist(int log_samples);
1188 void radv_device_init_msaa(struct radv_device *device);
1189
1190 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1191 struct radv_image *image,
1192 VkClearDepthStencilValue ds_clear_value,
1193 VkImageAspectFlags aspects);
1194
1195 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1196 struct radv_image *image,
1197 int cb_idx,
1198 uint32_t color_values[2]);
1199
1200 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1201 struct radv_image *image, bool value);
1202
1203 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1204 struct radeon_winsys_bo *bo,
1205 uint64_t offset, uint64_t size, uint32_t value);
1206 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1207 bool radv_get_memory_fd(struct radv_device *device,
1208 struct radv_device_memory *memory,
1209 int *pFD);
1210
1211 static inline void
1212 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1213 unsigned sh_offset, unsigned pointer_count,
1214 bool use_32bit_pointers)
1215 {
1216 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1217 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1218 }
1219
1220 static inline void
1221 radv_emit_shader_pointer_body(struct radv_device *device,
1222 struct radeon_cmdbuf *cs,
1223 uint64_t va, bool use_32bit_pointers)
1224 {
1225 radeon_emit(cs, va);
1226
1227 if (use_32bit_pointers) {
1228 assert(va == 0 ||
1229 (va >> 32) == device->physical_device->rad_info.address32_hi);
1230 } else {
1231 radeon_emit(cs, va >> 32);
1232 }
1233 }
1234
1235 static inline void
1236 radv_emit_shader_pointer(struct radv_device *device,
1237 struct radeon_cmdbuf *cs,
1238 uint32_t sh_offset, uint64_t va, bool global)
1239 {
1240 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1241
1242 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1243 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1244 }
1245
1246 static inline struct radv_descriptor_state *
1247 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1248 VkPipelineBindPoint bind_point)
1249 {
1250 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1251 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1252 return &cmd_buffer->descriptors[bind_point];
1253 }
1254
1255 /*
1256 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1257 *
1258 * Limitations: Can't call normal dispatch functions without binding or rebinding
1259 * the compute pipeline.
1260 */
1261 void radv_unaligned_dispatch(
1262 struct radv_cmd_buffer *cmd_buffer,
1263 uint32_t x,
1264 uint32_t y,
1265 uint32_t z);
1266
1267 struct radv_event {
1268 struct radeon_winsys_bo *bo;
1269 uint64_t *map;
1270 };
1271
1272 struct radv_shader_module;
1273
1274 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1275 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1276 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1277 void
1278 radv_hash_shaders(unsigned char *hash,
1279 const VkPipelineShaderStageCreateInfo **stages,
1280 const struct radv_pipeline_layout *layout,
1281 const struct radv_pipeline_key *key,
1282 uint32_t flags);
1283
1284 static inline gl_shader_stage
1285 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1286 {
1287 assert(__builtin_popcount(vk_stage) == 1);
1288 return ffs(vk_stage) - 1;
1289 }
1290
1291 static inline VkShaderStageFlagBits
1292 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1293 {
1294 return (1 << mesa_stage);
1295 }
1296
1297 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1298
1299 #define radv_foreach_stage(stage, stage_bits) \
1300 for (gl_shader_stage stage, \
1301 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1302 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1303 __tmp &= ~(1 << (stage)))
1304
1305 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1306 unsigned radv_format_meta_fs_key(VkFormat format);
1307
1308 struct radv_multisample_state {
1309 uint32_t db_eqaa;
1310 uint32_t pa_sc_line_cntl;
1311 uint32_t pa_sc_mode_cntl_0;
1312 uint32_t pa_sc_mode_cntl_1;
1313 uint32_t pa_sc_aa_config;
1314 uint32_t pa_sc_aa_mask[2];
1315 unsigned num_samples;
1316 };
1317
1318 struct radv_prim_vertex_count {
1319 uint8_t min;
1320 uint8_t incr;
1321 };
1322
1323 struct radv_vertex_elements_info {
1324 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1325 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1326 uint32_t binding[MAX_VERTEX_ATTRIBS];
1327 uint32_t offset[MAX_VERTEX_ATTRIBS];
1328 uint32_t count;
1329 };
1330
1331 struct radv_ia_multi_vgt_param_helpers {
1332 uint32_t base;
1333 bool partial_es_wave;
1334 uint8_t primgroup_size;
1335 bool wd_switch_on_eop;
1336 bool ia_switch_on_eoi;
1337 bool partial_vs_wave;
1338 };
1339
1340 #define SI_GS_PER_ES 128
1341
1342 struct radv_pipeline {
1343 struct radv_device * device;
1344 struct radv_dynamic_state dynamic_state;
1345
1346 struct radv_pipeline_layout * layout;
1347
1348 bool need_indirect_descriptor_sets;
1349 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1350 struct radv_shader_variant *gs_copy_shader;
1351 VkShaderStageFlags active_stages;
1352
1353 struct radeon_cmdbuf cs;
1354
1355 struct radv_vertex_elements_info vertex_elements;
1356
1357 uint32_t binding_stride[MAX_VBS];
1358
1359 uint32_t user_data_0[MESA_SHADER_STAGES];
1360 union {
1361 struct {
1362 struct radv_multisample_state ms;
1363 uint32_t spi_baryc_cntl;
1364 bool prim_restart_enable;
1365 unsigned esgs_ring_size;
1366 unsigned gsvs_ring_size;
1367 uint32_t vtx_base_sgpr;
1368 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1369 uint8_t vtx_emit_num;
1370 struct radv_prim_vertex_count prim_vertex_count;
1371 bool can_use_guardband;
1372 uint32_t needed_dynamic_state;
1373 bool disable_out_of_order_rast_for_occlusion;
1374
1375 /* Used for rbplus */
1376 uint32_t col_format;
1377 uint32_t cb_target_mask;
1378 } graphics;
1379 };
1380
1381 unsigned max_waves;
1382 unsigned scratch_bytes_per_wave;
1383
1384 /* Not NULL if graphics pipeline uses streamout. */
1385 struct radv_shader_variant *streamout_shader;
1386 };
1387
1388 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1389 {
1390 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1391 }
1392
1393 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1394 {
1395 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1396 }
1397
1398 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1399 gl_shader_stage stage,
1400 int idx);
1401
1402 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1403 gl_shader_stage stage);
1404
1405 struct radv_graphics_pipeline_create_info {
1406 bool use_rectlist;
1407 bool db_depth_clear;
1408 bool db_stencil_clear;
1409 bool db_depth_disable_expclear;
1410 bool db_stencil_disable_expclear;
1411 bool db_flush_depth_inplace;
1412 bool db_flush_stencil_inplace;
1413 bool db_resummarize;
1414 uint32_t custom_blend_mode;
1415 };
1416
1417 VkResult
1418 radv_graphics_pipeline_create(VkDevice device,
1419 VkPipelineCache cache,
1420 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1421 const struct radv_graphics_pipeline_create_info *extra,
1422 const VkAllocationCallbacks *alloc,
1423 VkPipeline *pPipeline);
1424
1425 struct vk_format_description;
1426 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1427 int first_non_void);
1428 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1429 int first_non_void);
1430 uint32_t radv_translate_colorformat(VkFormat format);
1431 uint32_t radv_translate_color_numformat(VkFormat format,
1432 const struct vk_format_description *desc,
1433 int first_non_void);
1434 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1435 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1436 uint32_t radv_translate_dbformat(VkFormat format);
1437 uint32_t radv_translate_tex_dataformat(VkFormat format,
1438 const struct vk_format_description *desc,
1439 int first_non_void);
1440 uint32_t radv_translate_tex_numformat(VkFormat format,
1441 const struct vk_format_description *desc,
1442 int first_non_void);
1443 bool radv_format_pack_clear_color(VkFormat format,
1444 uint32_t clear_vals[2],
1445 VkClearColorValue *value);
1446 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1447 bool radv_dcc_formats_compatible(VkFormat format1,
1448 VkFormat format2);
1449
1450 struct radv_fmask_info {
1451 uint64_t offset;
1452 uint64_t size;
1453 unsigned alignment;
1454 unsigned pitch_in_pixels;
1455 unsigned bank_height;
1456 unsigned slice_tile_max;
1457 unsigned tile_mode_index;
1458 unsigned tile_swizzle;
1459 };
1460
1461 struct radv_cmask_info {
1462 uint64_t offset;
1463 uint64_t size;
1464 unsigned alignment;
1465 unsigned slice_tile_max;
1466 };
1467
1468 struct radv_image {
1469 VkImageType type;
1470 /* The original VkFormat provided by the client. This may not match any
1471 * of the actual surface formats.
1472 */
1473 VkFormat vk_format;
1474 VkImageAspectFlags aspects;
1475 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1476 struct ac_surf_info info;
1477 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1478 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1479
1480 VkDeviceSize size;
1481 uint32_t alignment;
1482
1483 unsigned queue_family_mask;
1484 bool exclusive;
1485 bool shareable;
1486
1487 /* Set when bound */
1488 struct radeon_winsys_bo *bo;
1489 VkDeviceSize offset;
1490 uint64_t dcc_offset;
1491 uint64_t htile_offset;
1492 bool tc_compatible_htile;
1493 struct radeon_surf surface;
1494
1495 struct radv_fmask_info fmask;
1496 struct radv_cmask_info cmask;
1497 uint64_t clear_value_offset;
1498 uint64_t fce_pred_offset;
1499
1500 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1501 VkDeviceMemory owned_memory;
1502 };
1503
1504 /* Whether the image has a htile that is known consistent with the contents of
1505 * the image. */
1506 bool radv_layout_has_htile(const struct radv_image *image,
1507 VkImageLayout layout,
1508 unsigned queue_mask);
1509
1510 /* Whether the image has a htile that is known consistent with the contents of
1511 * the image and is allowed to be in compressed form.
1512 *
1513 * If this is false reads that don't use the htile should be able to return
1514 * correct results.
1515 */
1516 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1517 VkImageLayout layout,
1518 unsigned queue_mask);
1519
1520 bool radv_layout_can_fast_clear(const struct radv_image *image,
1521 VkImageLayout layout,
1522 unsigned queue_mask);
1523
1524 bool radv_layout_dcc_compressed(const struct radv_image *image,
1525 VkImageLayout layout,
1526 unsigned queue_mask);
1527
1528 /**
1529 * Return whether the image has CMASK metadata for color surfaces.
1530 */
1531 static inline bool
1532 radv_image_has_cmask(const struct radv_image *image)
1533 {
1534 return image->cmask.size;
1535 }
1536
1537 /**
1538 * Return whether the image has FMASK metadata for color surfaces.
1539 */
1540 static inline bool
1541 radv_image_has_fmask(const struct radv_image *image)
1542 {
1543 return image->fmask.size;
1544 }
1545
1546 /**
1547 * Return whether the image has DCC metadata for color surfaces.
1548 */
1549 static inline bool
1550 radv_image_has_dcc(const struct radv_image *image)
1551 {
1552 return image->surface.dcc_size;
1553 }
1554
1555 /**
1556 * Return whether DCC metadata is enabled for a level.
1557 */
1558 static inline bool
1559 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1560 {
1561 return radv_image_has_dcc(image) &&
1562 level < image->surface.num_dcc_levels;
1563 }
1564
1565 /**
1566 * Return whether the image has CB metadata.
1567 */
1568 static inline bool
1569 radv_image_has_CB_metadata(const struct radv_image *image)
1570 {
1571 return radv_image_has_cmask(image) ||
1572 radv_image_has_fmask(image) ||
1573 radv_image_has_dcc(image);
1574 }
1575
1576 /**
1577 * Return whether the image has HTILE metadata for depth surfaces.
1578 */
1579 static inline bool
1580 radv_image_has_htile(const struct radv_image *image)
1581 {
1582 return image->surface.htile_size;
1583 }
1584
1585 /**
1586 * Return whether HTILE metadata is enabled for a level.
1587 */
1588 static inline bool
1589 radv_htile_enabled(const struct radv_image *image, unsigned level)
1590 {
1591 return radv_image_has_htile(image) && level == 0;
1592 }
1593
1594 /**
1595 * Return whether the image is TC-compatible HTILE.
1596 */
1597 static inline bool
1598 radv_image_is_tc_compat_htile(const struct radv_image *image)
1599 {
1600 return radv_image_has_htile(image) && image->tc_compatible_htile;
1601 }
1602
1603 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1604
1605 static inline uint32_t
1606 radv_get_layerCount(const struct radv_image *image,
1607 const VkImageSubresourceRange *range)
1608 {
1609 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1610 image->info.array_size - range->baseArrayLayer : range->layerCount;
1611 }
1612
1613 static inline uint32_t
1614 radv_get_levelCount(const struct radv_image *image,
1615 const VkImageSubresourceRange *range)
1616 {
1617 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1618 image->info.levels - range->baseMipLevel : range->levelCount;
1619 }
1620
1621 struct radeon_bo_metadata;
1622 void
1623 radv_init_metadata(struct radv_device *device,
1624 struct radv_image *image,
1625 struct radeon_bo_metadata *metadata);
1626
1627 struct radv_image_view {
1628 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1629 struct radeon_winsys_bo *bo;
1630
1631 VkImageViewType type;
1632 VkImageAspectFlags aspect_mask;
1633 VkFormat vk_format;
1634 uint32_t base_layer;
1635 uint32_t layer_count;
1636 uint32_t base_mip;
1637 uint32_t level_count;
1638 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1639
1640 uint32_t descriptor[16];
1641
1642 /* Descriptor for use as a storage image as opposed to a sampled image.
1643 * This has a few differences for cube maps (e.g. type).
1644 */
1645 uint32_t storage_descriptor[16];
1646 };
1647
1648 struct radv_image_create_info {
1649 const VkImageCreateInfo *vk_info;
1650 bool scanout;
1651 bool no_metadata_planes;
1652 };
1653
1654 VkResult radv_image_create(VkDevice _device,
1655 const struct radv_image_create_info *info,
1656 const VkAllocationCallbacks* alloc,
1657 VkImage *pImage);
1658
1659 VkResult
1660 radv_image_from_gralloc(VkDevice device_h,
1661 const VkImageCreateInfo *base_info,
1662 const VkNativeBufferANDROID *gralloc_info,
1663 const VkAllocationCallbacks *alloc,
1664 VkImage *out_image_h);
1665
1666 void radv_image_view_init(struct radv_image_view *view,
1667 struct radv_device *device,
1668 const VkImageViewCreateInfo* pCreateInfo);
1669
1670 struct radv_buffer_view {
1671 struct radeon_winsys_bo *bo;
1672 VkFormat vk_format;
1673 uint64_t range; /**< VkBufferViewCreateInfo::range */
1674 uint32_t state[4];
1675 };
1676 void radv_buffer_view_init(struct radv_buffer_view *view,
1677 struct radv_device *device,
1678 const VkBufferViewCreateInfo* pCreateInfo);
1679
1680 static inline struct VkExtent3D
1681 radv_sanitize_image_extent(const VkImageType imageType,
1682 const struct VkExtent3D imageExtent)
1683 {
1684 switch (imageType) {
1685 case VK_IMAGE_TYPE_1D:
1686 return (VkExtent3D) { imageExtent.width, 1, 1 };
1687 case VK_IMAGE_TYPE_2D:
1688 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1689 case VK_IMAGE_TYPE_3D:
1690 return imageExtent;
1691 default:
1692 unreachable("invalid image type");
1693 }
1694 }
1695
1696 static inline struct VkOffset3D
1697 radv_sanitize_image_offset(const VkImageType imageType,
1698 const struct VkOffset3D imageOffset)
1699 {
1700 switch (imageType) {
1701 case VK_IMAGE_TYPE_1D:
1702 return (VkOffset3D) { imageOffset.x, 0, 0 };
1703 case VK_IMAGE_TYPE_2D:
1704 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1705 case VK_IMAGE_TYPE_3D:
1706 return imageOffset;
1707 default:
1708 unreachable("invalid image type");
1709 }
1710 }
1711
1712 static inline bool
1713 radv_image_extent_compare(const struct radv_image *image,
1714 const VkExtent3D *extent)
1715 {
1716 if (extent->width != image->info.width ||
1717 extent->height != image->info.height ||
1718 extent->depth != image->info.depth)
1719 return false;
1720 return true;
1721 }
1722
1723 struct radv_sampler {
1724 uint32_t state[4];
1725 };
1726
1727 struct radv_color_buffer_info {
1728 uint64_t cb_color_base;
1729 uint64_t cb_color_cmask;
1730 uint64_t cb_color_fmask;
1731 uint64_t cb_dcc_base;
1732 uint32_t cb_color_pitch;
1733 uint32_t cb_color_slice;
1734 uint32_t cb_color_view;
1735 uint32_t cb_color_info;
1736 uint32_t cb_color_attrib;
1737 uint32_t cb_color_attrib2;
1738 uint32_t cb_dcc_control;
1739 uint32_t cb_color_cmask_slice;
1740 uint32_t cb_color_fmask_slice;
1741 };
1742
1743 struct radv_ds_buffer_info {
1744 uint64_t db_z_read_base;
1745 uint64_t db_stencil_read_base;
1746 uint64_t db_z_write_base;
1747 uint64_t db_stencil_write_base;
1748 uint64_t db_htile_data_base;
1749 uint32_t db_depth_info;
1750 uint32_t db_z_info;
1751 uint32_t db_stencil_info;
1752 uint32_t db_depth_view;
1753 uint32_t db_depth_size;
1754 uint32_t db_depth_slice;
1755 uint32_t db_htile_surface;
1756 uint32_t pa_su_poly_offset_db_fmt_cntl;
1757 uint32_t db_z_info2;
1758 uint32_t db_stencil_info2;
1759 float offset_scale;
1760 };
1761
1762 struct radv_attachment_info {
1763 union {
1764 struct radv_color_buffer_info cb;
1765 struct radv_ds_buffer_info ds;
1766 };
1767 struct radv_image_view *attachment;
1768 };
1769
1770 struct radv_framebuffer {
1771 uint32_t width;
1772 uint32_t height;
1773 uint32_t layers;
1774
1775 uint32_t attachment_count;
1776 struct radv_attachment_info attachments[0];
1777 };
1778
1779 struct radv_subpass_barrier {
1780 VkPipelineStageFlags src_stage_mask;
1781 VkAccessFlags src_access_mask;
1782 VkAccessFlags dst_access_mask;
1783 };
1784
1785 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1786 const struct radv_subpass_barrier *barrier);
1787
1788 struct radv_subpass_attachment {
1789 uint32_t attachment;
1790 VkImageLayout layout;
1791 };
1792
1793 struct radv_subpass {
1794 uint32_t input_count;
1795 uint32_t color_count;
1796 struct radv_subpass_attachment * input_attachments;
1797 struct radv_subpass_attachment * color_attachments;
1798 struct radv_subpass_attachment * resolve_attachments;
1799 struct radv_subpass_attachment depth_stencil_attachment;
1800
1801 /** Subpass has at least one resolve attachment */
1802 bool has_resolve;
1803
1804 struct radv_subpass_barrier start_barrier;
1805
1806 uint32_t view_mask;
1807 VkSampleCountFlagBits max_sample_count;
1808 };
1809
1810 struct radv_render_pass_attachment {
1811 VkFormat format;
1812 uint32_t samples;
1813 VkAttachmentLoadOp load_op;
1814 VkAttachmentLoadOp stencil_load_op;
1815 VkImageLayout initial_layout;
1816 VkImageLayout final_layout;
1817 uint32_t view_mask;
1818 };
1819
1820 struct radv_render_pass {
1821 uint32_t attachment_count;
1822 uint32_t subpass_count;
1823 struct radv_subpass_attachment * subpass_attachments;
1824 struct radv_render_pass_attachment * attachments;
1825 struct radv_subpass_barrier end_barrier;
1826 struct radv_subpass subpasses[0];
1827 };
1828
1829 VkResult radv_device_init_meta(struct radv_device *device);
1830 void radv_device_finish_meta(struct radv_device *device);
1831
1832 struct radv_query_pool {
1833 struct radeon_winsys_bo *bo;
1834 uint32_t stride;
1835 uint32_t availability_offset;
1836 uint64_t size;
1837 char *ptr;
1838 VkQueryType type;
1839 uint32_t pipeline_stats_mask;
1840 };
1841
1842 struct radv_semaphore {
1843 /* use a winsys sem for non-exportable */
1844 struct radeon_winsys_sem *sem;
1845 uint32_t syncobj;
1846 uint32_t temp_syncobj;
1847 };
1848
1849 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1850 VkPipelineBindPoint bind_point,
1851 struct radv_descriptor_set *set,
1852 unsigned idx);
1853
1854 void
1855 radv_update_descriptor_sets(struct radv_device *device,
1856 struct radv_cmd_buffer *cmd_buffer,
1857 VkDescriptorSet overrideSet,
1858 uint32_t descriptorWriteCount,
1859 const VkWriteDescriptorSet *pDescriptorWrites,
1860 uint32_t descriptorCopyCount,
1861 const VkCopyDescriptorSet *pDescriptorCopies);
1862
1863 void
1864 radv_update_descriptor_set_with_template(struct radv_device *device,
1865 struct radv_cmd_buffer *cmd_buffer,
1866 struct radv_descriptor_set *set,
1867 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1868 const void *pData);
1869
1870 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1871 VkPipelineBindPoint pipelineBindPoint,
1872 VkPipelineLayout _layout,
1873 uint32_t set,
1874 uint32_t descriptorWriteCount,
1875 const VkWriteDescriptorSet *pDescriptorWrites);
1876
1877 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1878 struct radv_image *image, uint32_t value);
1879
1880 struct radv_fence {
1881 struct radeon_winsys_fence *fence;
1882 struct wsi_fence *fence_wsi;
1883 bool submitted;
1884 bool signalled;
1885
1886 uint32_t syncobj;
1887 uint32_t temp_syncobj;
1888 };
1889
1890 /* radv_nir_to_llvm.c */
1891 struct radv_shader_variant_info;
1892 struct radv_nir_compiler_options;
1893
1894 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1895 struct nir_shader *geom_shader,
1896 struct ac_shader_binary *binary,
1897 struct ac_shader_config *config,
1898 struct radv_shader_variant_info *shader_info,
1899 const struct radv_nir_compiler_options *option);
1900
1901 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1902 struct ac_shader_binary *binary,
1903 struct ac_shader_config *config,
1904 struct radv_shader_variant_info *shader_info,
1905 struct nir_shader *const *nir,
1906 int nir_count,
1907 const struct radv_nir_compiler_options *options);
1908
1909 /* radv_shader_info.h */
1910 struct radv_shader_info;
1911
1912 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1913 const struct radv_nir_compiler_options *options,
1914 struct radv_shader_info *info);
1915
1916 struct radeon_winsys_sem;
1917
1918 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1919 \
1920 static inline struct __radv_type * \
1921 __radv_type ## _from_handle(__VkType _handle) \
1922 { \
1923 return (struct __radv_type *) _handle; \
1924 } \
1925 \
1926 static inline __VkType \
1927 __radv_type ## _to_handle(struct __radv_type *_obj) \
1928 { \
1929 return (__VkType) _obj; \
1930 }
1931
1932 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1933 \
1934 static inline struct __radv_type * \
1935 __radv_type ## _from_handle(__VkType _handle) \
1936 { \
1937 return (struct __radv_type *)(uintptr_t) _handle; \
1938 } \
1939 \
1940 static inline __VkType \
1941 __radv_type ## _to_handle(struct __radv_type *_obj) \
1942 { \
1943 return (__VkType)(uintptr_t) _obj; \
1944 }
1945
1946 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1947 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1948
1949 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1950 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1951 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1952 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1953 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1954
1955 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1956 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1957 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1958 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1959 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1960 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1961 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1962 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1963 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1964 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1965 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1966 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1967 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1968 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1969 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1970 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1971 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1972 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1973 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1974 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1975 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1976
1977 #endif /* RADV_PRIVATE_H */