2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
60 #include <llvm-c/TargetMachine.h>
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t
;
66 typedef uint32_t xcb_visualid_t
;
67 typedef uint32_t xcb_window_t
;
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
73 #include "radv_entrypoints.h"
75 #include "wsi_common.h"
78 #define MAX_VERTEX_ATTRIBS 32
80 #define MAX_VIEWPORTS 16
81 #define MAX_SCISSORS 16
82 #define MAX_PUSH_CONSTANTS_SIZE 128
83 #define MAX_PUSH_DESCRIPTORS 32
84 #define MAX_DYNAMIC_BUFFERS 16
85 #define MAX_SAMPLES_LOG2 4
86 #define NUM_META_FS_KEYS 13
87 #define RADV_MAX_DRM_DEVICES 8
90 #define NUM_DEPTH_CLEAR_PIPELINES 3
94 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
101 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
102 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
103 RADV_MEM_TYPE_GTT_CACHED
,
107 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
109 static inline uint32_t
110 align_u32(uint32_t v
, uint32_t a
)
112 assert(a
!= 0 && a
== (a
& -a
));
113 return (v
+ a
- 1) & ~(a
- 1);
116 static inline uint32_t
117 align_u32_npot(uint32_t v
, uint32_t a
)
119 return (v
+ a
- 1) / a
* a
;
122 static inline uint64_t
123 align_u64(uint64_t v
, uint64_t a
)
125 assert(a
!= 0 && a
== (a
& -a
));
126 return (v
+ a
- 1) & ~(a
- 1);
129 static inline int32_t
130 align_i32(int32_t v
, int32_t a
)
132 assert(a
!= 0 && a
== (a
& -a
));
133 return (v
+ a
- 1) & ~(a
- 1);
136 /** Alignment must be a power of 2. */
138 radv_is_aligned(uintmax_t n
, uintmax_t a
)
140 assert(a
== (a
& -a
));
141 return (n
& (a
- 1)) == 0;
144 static inline uint32_t
145 round_up_u32(uint32_t v
, uint32_t a
)
147 return (v
+ a
- 1) / a
;
150 static inline uint64_t
151 round_up_u64(uint64_t v
, uint64_t a
)
153 return (v
+ a
- 1) / a
;
156 static inline uint32_t
157 radv_minify(uint32_t n
, uint32_t levels
)
159 if (unlikely(n
== 0))
162 return MAX2(n
>> levels
, 1);
165 radv_clamp_f(float f
, float min
, float max
)
178 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
180 if (*inout_mask
& clear_mask
) {
181 *inout_mask
&= ~clear_mask
;
188 #define for_each_bit(b, dword) \
189 for (uint32_t __dword = (dword); \
190 (b) = __builtin_ffs(__dword) - 1, __dword; \
191 __dword &= ~(1 << (b)))
193 #define typed_memcpy(dest, src, count) ({ \
194 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
195 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 #define zero(x) (memset(&(x), 0, sizeof(x)))
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
205 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
215 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format
, va_list va
);
221 * Print a FINISHME message, including its source location.
223 #define radv_finishme(format, ...) \
225 static bool reported = false; \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
232 /* A non-fatal assert. Useful for debugging. */
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
239 #define radv_assert(x)
242 #define stub_return(v) \
244 radv_finishme("stub %s", __func__); \
250 radv_finishme("stub %s", __func__); \
254 void *radv_lookup_entrypoint(const char *name
);
256 struct radv_extensions
{
257 VkExtensionProperties
*ext_array
;
261 struct radv_physical_device
{
262 VK_LOADER_DATA _loader_data
;
264 struct radv_instance
* instance
;
266 struct radeon_winsys
*ws
;
267 struct radeon_info rad_info
;
270 uint8_t driver_uuid
[VK_UUID_SIZE
];
271 uint8_t device_uuid
[VK_UUID_SIZE
];
272 uint8_t cache_uuid
[VK_UUID_SIZE
];
275 struct wsi_device wsi_device
;
276 struct radv_extensions extensions
;
278 bool has_rbplus
; /* if RB+ register exist */
279 bool rbplus_allowed
; /* if RB+ is allowed */
282 struct radv_instance
{
283 VK_LOADER_DATA _loader_data
;
285 VkAllocationCallbacks alloc
;
288 int physicalDeviceCount
;
289 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
291 uint64_t debug_flags
;
292 uint64_t perftest_flags
;
295 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
296 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
300 struct radv_pipeline_cache
{
301 struct radv_device
* device
;
302 pthread_mutex_t mutex
;
306 uint32_t kernel_count
;
307 struct cache_entry
** hash_table
;
310 VkAllocationCallbacks alloc
;
314 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
315 struct radv_device
*device
);
317 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
319 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
320 const void *data
, size_t size
);
322 struct radv_shader_variant
*
323 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
324 struct radv_pipeline_cache
*cache
,
325 const unsigned char *sha1
);
327 struct radv_shader_variant
*
328 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache
*cache
,
329 const unsigned char *sha1
,
330 struct radv_shader_variant
*variant
,
331 const void *code
, unsigned code_size
);
333 void radv_shader_variant_destroy(struct radv_device
*device
,
334 struct radv_shader_variant
*variant
);
336 struct radv_meta_state
{
337 VkAllocationCallbacks alloc
;
339 struct radv_pipeline_cache cache
;
342 * Use array element `i` for images with `2^i` samples.
345 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
346 struct radv_pipeline
*color_pipelines
[NUM_META_FS_KEYS
];
348 VkRenderPass depthstencil_rp
;
349 struct radv_pipeline
*depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
350 struct radv_pipeline
*stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
351 struct radv_pipeline
*depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
352 } clear
[1 + MAX_SAMPLES_LOG2
];
354 VkPipelineLayout clear_color_p_layout
;
355 VkPipelineLayout clear_depth_p_layout
;
357 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
359 /** Pipeline that blits from a 1D image. */
360 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
362 /** Pipeline that blits from a 2D image. */
363 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
365 /** Pipeline that blits from a 3D image. */
366 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
368 VkRenderPass depth_only_rp
;
369 VkPipeline depth_only_1d_pipeline
;
370 VkPipeline depth_only_2d_pipeline
;
371 VkPipeline depth_only_3d_pipeline
;
373 VkRenderPass stencil_only_rp
;
374 VkPipeline stencil_only_1d_pipeline
;
375 VkPipeline stencil_only_2d_pipeline
;
376 VkPipeline stencil_only_3d_pipeline
;
377 VkPipelineLayout pipeline_layout
;
378 VkDescriptorSetLayout ds_layout
;
382 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
384 VkPipelineLayout p_layouts
[2];
385 VkDescriptorSetLayout ds_layouts
[2];
386 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
388 VkRenderPass depth_only_rp
;
389 VkPipeline depth_only_pipeline
[2];
391 VkRenderPass stencil_only_rp
;
392 VkPipeline stencil_only_pipeline
[2];
396 VkPipelineLayout img_p_layout
;
397 VkDescriptorSetLayout img_ds_layout
;
401 VkRenderPass render_pass
;
402 VkPipelineLayout img_p_layout
;
403 VkDescriptorSetLayout img_ds_layout
;
407 VkPipelineLayout img_p_layout
;
408 VkDescriptorSetLayout img_ds_layout
;
412 VkPipelineLayout img_p_layout
;
413 VkDescriptorSetLayout img_ds_layout
;
423 VkDescriptorSetLayout ds_layout
;
424 VkPipelineLayout p_layout
;
427 VkPipeline i_pipeline
;
428 VkPipeline srgb_pipeline
;
429 } rc
[MAX_SAMPLES_LOG2
];
433 VkDescriptorSetLayout ds_layout
;
434 VkPipelineLayout p_layout
;
437 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
438 VkPipeline pipeline
[NUM_META_FS_KEYS
];
439 } rc
[MAX_SAMPLES_LOG2
];
443 VkPipeline decompress_pipeline
;
444 VkPipeline resummarize_pipeline
;
446 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
449 VkPipeline cmask_eliminate_pipeline
;
450 VkPipeline fmask_decompress_pipeline
;
455 VkPipelineLayout fill_p_layout
;
456 VkPipelineLayout copy_p_layout
;
457 VkDescriptorSetLayout fill_ds_layout
;
458 VkDescriptorSetLayout copy_ds_layout
;
459 VkPipeline fill_pipeline
;
460 VkPipeline copy_pipeline
;
464 VkDescriptorSetLayout ds_layout
;
465 VkPipelineLayout p_layout
;
466 VkPipeline occlusion_query_pipeline
;
467 VkPipeline pipeline_statistics_query_pipeline
;
472 #define RADV_QUEUE_GENERAL 0
473 #define RADV_QUEUE_COMPUTE 1
474 #define RADV_QUEUE_TRANSFER 2
476 #define RADV_MAX_QUEUE_FAMILIES 3
478 enum ring_type
radv_queue_family_to_ring(int f
);
481 VK_LOADER_DATA _loader_data
;
482 struct radv_device
* device
;
483 struct radeon_winsys_ctx
*hw_ctx
;
484 int queue_family_index
;
487 uint32_t scratch_size
;
488 uint32_t compute_scratch_size
;
489 uint32_t esgs_ring_size
;
490 uint32_t gsvs_ring_size
;
492 bool has_sample_positions
;
494 struct radeon_winsys_bo
*scratch_bo
;
495 struct radeon_winsys_bo
*descriptor_bo
;
496 struct radeon_winsys_bo
*compute_scratch_bo
;
497 struct radeon_winsys_bo
*esgs_ring_bo
;
498 struct radeon_winsys_bo
*gsvs_ring_bo
;
499 struct radeon_winsys_bo
*tess_factor_ring_bo
;
500 struct radeon_winsys_bo
*tess_offchip_ring_bo
;
501 struct radeon_winsys_cs
*initial_preamble_cs
;
502 struct radeon_winsys_cs
*continue_preamble_cs
;
506 VK_LOADER_DATA _loader_data
;
508 VkAllocationCallbacks alloc
;
510 struct radv_instance
* instance
;
511 struct radeon_winsys
*ws
;
513 struct radv_meta_state meta_state
;
515 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
516 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
517 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
518 struct radeon_winsys_cs
*flush_cs
[RADV_MAX_QUEUE_FAMILIES
];
519 struct radeon_winsys_cs
*flush_shader_cs
[RADV_MAX_QUEUE_FAMILIES
];
520 uint64_t debug_flags
;
522 bool llvm_supports_spill
;
523 bool has_distributed_tess
;
524 uint32_t tess_offchip_block_dw_size
;
525 uint32_t scratch_waves
;
527 uint32_t gs_table_depth
;
529 /* MSAA sample locations.
530 * The first index is the sample index.
531 * The second index is the coordinate: X, Y. */
532 float sample_locations_1x
[1][2];
533 float sample_locations_2x
[2][2];
534 float sample_locations_4x
[4][2];
535 float sample_locations_8x
[8][2];
536 float sample_locations_16x
[16][2];
539 uint32_t gfx_init_size_dw
;
540 struct radeon_winsys_bo
*gfx_init
;
542 struct radeon_winsys_bo
*trace_bo
;
543 uint32_t *trace_id_ptr
;
545 struct radv_physical_device
*physical_device
;
547 /* Backup in-memory cache to be used if the app doesn't provide one */
548 struct radv_pipeline_cache
* mem_cache
;
551 * use different counters so MSAA MRTs get consecutive surface indices,
552 * even if MASK is allocated in between.
554 uint32_t image_mrt_offset_counter
;
555 uint32_t fmask_mrt_offset_counter
;
556 struct list_head shader_slabs
;
557 mtx_t shader_slab_mutex
;
559 /* For detecting VM faults reported by dmesg. */
560 uint64_t dmesg_timestamp
;
563 struct radv_device_memory
{
564 struct radeon_winsys_bo
*bo
;
565 /* for dedicated allocations */
566 struct radv_image
*image
;
567 struct radv_buffer
*buffer
;
569 VkDeviceSize map_size
;
574 struct radv_descriptor_range
{
579 struct radv_descriptor_set
{
580 const struct radv_descriptor_set_layout
*layout
;
583 struct radeon_winsys_bo
*bo
;
585 uint32_t *mapped_ptr
;
586 struct radv_descriptor_range
*dynamic_descriptors
;
588 struct list_head vram_list
;
590 struct radeon_winsys_bo
*descriptors
[0];
593 struct radv_push_descriptor_set
595 struct radv_descriptor_set set
;
599 struct radv_descriptor_pool
{
600 struct radeon_winsys_bo
*bo
;
602 uint64_t current_offset
;
605 struct list_head vram_list
;
607 uint8_t *host_memory_base
;
608 uint8_t *host_memory_ptr
;
609 uint8_t *host_memory_end
;
612 struct radv_descriptor_update_template_entry
{
613 VkDescriptorType descriptor_type
;
615 /* The number of descriptors to update */
616 uint32_t descriptor_count
;
618 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
621 /* In dwords. Not valid/used for dynamic descriptors */
624 uint32_t buffer_offset
;
626 /* Only valid for combined image samplers and samplers */
627 uint16_t has_sampler
;
633 /* For push descriptors */
634 const uint32_t *immutable_samplers
;
637 struct radv_descriptor_update_template
{
638 uint32_t entry_count
;
639 struct radv_descriptor_update_template_entry entry
[0];
643 struct radv_device
* device
;
646 VkBufferUsageFlags usage
;
647 VkBufferCreateFlags flags
;
650 struct radeon_winsys_bo
* bo
;
655 enum radv_cmd_dirty_bits
{
656 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
657 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
658 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
659 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
660 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
661 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
662 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
663 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
664 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
665 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
666 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
667 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
668 RADV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
670 typedef uint32_t radv_cmd_dirty_mask_t
;
672 enum radv_cmd_flush_bits
{
673 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
674 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
675 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
676 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
677 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
678 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
679 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
680 /* Same as above, but only writes back and doesn't invalidate */
681 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
682 /* Framebuffer caches */
683 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
684 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
685 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
686 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
687 /* Engine synchronization. */
688 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
689 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
690 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
691 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
693 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
694 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
695 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
696 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
699 struct radv_vertex_binding
{
700 struct radv_buffer
* buffer
;
704 struct radv_dynamic_state
{
707 VkViewport viewports
[MAX_VIEWPORTS
];
712 VkRect2D scissors
[MAX_SCISSORS
];
723 float blend_constants
[4];
733 } stencil_compare_mask
;
738 } stencil_write_mask
;
746 extern const struct radv_dynamic_state default_dynamic_state
;
748 void radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
749 const struct radv_dynamic_state
*src
,
752 * Attachment state when recording a renderpass instance.
754 * The clear value is valid only if there exists a pending clear.
756 struct radv_attachment_state
{
757 VkImageAspectFlags pending_clear_aspects
;
758 uint32_t cleared_views
;
759 VkClearValue clear_value
;
760 VkImageLayout current_layout
;
763 struct radv_cmd_state
{
765 radv_cmd_dirty_mask_t dirty
;
766 bool push_descriptors_dirty
;
768 struct radv_pipeline
* pipeline
;
769 struct radv_pipeline
* emitted_pipeline
;
770 struct radv_pipeline
* compute_pipeline
;
771 struct radv_pipeline
* emitted_compute_pipeline
;
772 struct radv_framebuffer
* framebuffer
;
773 struct radv_render_pass
* pass
;
774 const struct radv_subpass
* subpass
;
775 struct radv_dynamic_state dynamic
;
776 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
777 struct radv_descriptor_set
* descriptors
[MAX_SETS
];
778 struct radv_attachment_state
* attachments
;
779 VkRect2D render_area
;
782 uint32_t max_index_count
;
783 int32_t last_primitive_reset_en
;
784 uint32_t last_primitive_reset_index
;
785 enum radv_cmd_flush_bits flush_bits
;
786 unsigned active_occlusion_queries
;
788 uint32_t descriptors_dirty
;
790 uint32_t last_ia_multi_vgt_param
;
794 struct radv_cmd_pool
{
795 VkAllocationCallbacks alloc
;
796 struct list_head cmd_buffers
;
797 struct list_head free_cmd_buffers
;
798 uint32_t queue_family_index
;
801 struct radv_cmd_buffer_upload
{
805 struct radeon_winsys_bo
*upload_bo
;
806 struct list_head list
;
809 struct radv_cmd_buffer
{
810 VK_LOADER_DATA _loader_data
;
812 struct radv_device
* device
;
814 struct radv_cmd_pool
* pool
;
815 struct list_head pool_link
;
817 VkCommandBufferUsageFlags usage_flags
;
818 VkCommandBufferLevel level
;
819 struct radeon_winsys_cs
*cs
;
820 struct radv_cmd_state state
;
821 uint32_t queue_family_index
;
823 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
824 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
825 VkShaderStageFlags push_constant_stages
;
826 struct radv_push_descriptor_set push_descriptors
;
827 struct radv_descriptor_set meta_push_descriptors
;
829 struct radv_cmd_buffer_upload upload
;
831 uint32_t scratch_size_needed
;
832 uint32_t compute_scratch_size_needed
;
833 uint32_t esgs_ring_size_needed
;
834 uint32_t gsvs_ring_size_needed
;
835 bool tess_rings_needed
;
836 bool sample_positions_needed
;
838 VkResult record_result
;
840 int ring_offsets_idx
; /* just used for verification */
841 uint32_t gfx9_fence_offset
;
842 struct radeon_winsys_bo
*gfx9_fence_bo
;
843 uint32_t gfx9_fence_idx
;
848 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
850 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
851 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
853 void cik_create_gfx_config(struct radv_device
*device
);
855 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
856 int count
, const VkViewport
*viewports
);
857 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
858 int count
, const VkRect2D
*scissors
,
859 const VkViewport
*viewports
, bool can_use_guardband
);
860 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
861 bool instanced_draw
, bool indirect_draw
,
862 uint32_t draw_vertex_count
);
863 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
865 enum chip_class chip_class
,
867 unsigned event
, unsigned event_flags
,
873 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
875 uint64_t va
, uint32_t ref
,
877 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
879 enum chip_class chip_class
,
880 uint32_t *fence_ptr
, uint64_t va
,
882 enum radv_cmd_flush_bits flush_bits
);
883 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
884 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
885 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
886 uint64_t src_va
, uint64_t dest_va
,
888 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
890 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
891 uint64_t size
, unsigned value
);
892 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
893 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
894 struct radv_descriptor_set
*set
,
897 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
900 unsigned *out_offset
,
903 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
904 const struct radv_subpass
*subpass
,
907 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
908 unsigned size
, unsigned alignmnet
,
909 const void *data
, unsigned *out_offset
);
911 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
912 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
913 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
914 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
915 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
916 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
917 unsigned radv_cayman_get_maxdist(int log_samples
);
918 void radv_device_init_msaa(struct radv_device
*device
);
919 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
920 struct radv_image
*image
,
921 VkClearDepthStencilValue ds_clear_value
,
922 VkImageAspectFlags aspects
);
923 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
924 struct radv_image
*image
,
926 uint32_t color_values
[2]);
927 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
928 struct radv_image
*image
,
930 void radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
931 struct radeon_winsys_bo
*bo
,
932 uint64_t offset
, uint64_t size
, uint32_t value
);
933 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
934 bool radv_get_memory_fd(struct radv_device
*device
,
935 struct radv_device_memory
*memory
,
938 * Takes x,y,z as exact numbers of invocations, instead of blocks.
940 * Limitations: Can't call normal dispatch functions without binding or rebinding
941 * the compute pipeline.
943 void radv_unaligned_dispatch(
944 struct radv_cmd_buffer
*cmd_buffer
,
950 struct radeon_winsys_bo
*bo
;
956 struct radv_shader_module
{
957 struct nir_shader
* nir
;
958 unsigned char sha1
[20];
963 struct ac_shader_variant_key
;
966 radv_hash_shader(unsigned char *hash
, struct radv_shader_module
*module
,
967 const char *entrypoint
,
968 const VkSpecializationInfo
*spec_info
,
969 const struct radv_pipeline_layout
*layout
,
970 const struct ac_shader_variant_key
*key
,
971 uint32_t is_geom_copy_shader
);
973 static inline gl_shader_stage
974 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
976 assert(__builtin_popcount(vk_stage
) == 1);
977 return ffs(vk_stage
) - 1;
980 static inline VkShaderStageFlagBits
981 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
983 return (1 << mesa_stage
);
986 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
988 #define radv_foreach_stage(stage, stage_bits) \
989 for (gl_shader_stage stage, \
990 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
991 stage = __builtin_ffs(__tmp) - 1, __tmp; \
992 __tmp &= ~(1 << (stage)))
995 struct radv_shader_slab
{
996 struct list_head slabs
;
997 struct list_head shaders
;
998 struct radeon_winsys_bo
*bo
;
1003 struct radv_shader_variant
{
1006 struct radeon_winsys_bo
*bo
;
1008 struct ac_shader_config config
;
1009 struct ac_shader_variant_info info
;
1014 struct list_head slab_list
;
1018 void *radv_alloc_shader_memory(struct radv_device
*device
,
1019 struct radv_shader_variant
*shader
);
1021 void radv_destroy_shader_slabs(struct radv_device
*device
);
1023 struct radv_depth_stencil_state
{
1024 uint32_t db_depth_control
;
1025 uint32_t db_stencil_control
;
1026 uint32_t db_render_control
;
1027 uint32_t db_render_override2
;
1030 struct radv_blend_state
{
1031 uint32_t cb_color_control
;
1032 uint32_t cb_target_mask
;
1033 uint32_t sx_mrt_blend_opt
[8];
1034 uint32_t cb_blend_control
[8];
1036 uint32_t spi_shader_col_format
;
1037 uint32_t cb_shader_mask
;
1038 uint32_t db_alpha_to_mask
;
1041 unsigned radv_format_meta_fs_key(VkFormat format
);
1043 struct radv_raster_state
{
1044 uint32_t pa_cl_clip_cntl
;
1045 uint32_t spi_interp_control
;
1046 uint32_t pa_su_point_size
;
1047 uint32_t pa_su_point_minmax
;
1048 uint32_t pa_su_line_cntl
;
1049 uint32_t pa_su_vtx_cntl
;
1050 uint32_t pa_su_sc_mode_cntl
;
1053 struct radv_multisample_state
{
1055 uint32_t pa_sc_line_cntl
;
1056 uint32_t pa_sc_mode_cntl_0
;
1057 uint32_t pa_sc_mode_cntl_1
;
1058 uint32_t pa_sc_aa_config
;
1059 uint32_t pa_sc_aa_mask
[2];
1060 unsigned num_samples
;
1063 struct radv_prim_vertex_count
{
1068 struct radv_tessellation_state
{
1069 uint32_t ls_hs_config
;
1070 uint32_t tcs_in_layout
;
1071 uint32_t tcs_out_layout
;
1072 uint32_t tcs_out_offsets
;
1073 uint32_t offchip_layout
;
1074 unsigned num_patches
;
1076 unsigned num_tcs_input_cp
;
1080 struct radv_pipeline
{
1081 struct radv_device
* device
;
1082 uint32_t dynamic_state_mask
;
1083 struct radv_dynamic_state dynamic_state
;
1085 struct radv_pipeline_layout
* layout
;
1087 bool needs_data_cache
;
1088 bool need_indirect_descriptor_sets
;
1089 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1090 struct radv_shader_variant
*gs_copy_shader
;
1091 VkShaderStageFlags active_stages
;
1093 uint32_t va_rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1094 uint32_t va_format_size
[MAX_VERTEX_ATTRIBS
];
1095 uint32_t va_binding
[MAX_VERTEX_ATTRIBS
];
1096 uint32_t va_offset
[MAX_VERTEX_ATTRIBS
];
1097 uint32_t num_vertex_attribs
;
1098 uint32_t binding_stride
[MAX_VBS
];
1102 struct radv_blend_state blend
;
1103 struct radv_depth_stencil_state ds
;
1104 struct radv_raster_state raster
;
1105 struct radv_multisample_state ms
;
1106 struct radv_tessellation_state tess
;
1107 uint32_t db_shader_control
;
1108 uint32_t shader_z_format
;
1111 uint32_t vgt_gs_mode
;
1112 bool vgt_primitiveid_en
;
1113 bool prim_restart_enable
;
1114 unsigned esgs_ring_size
;
1115 unsigned gsvs_ring_size
;
1116 uint32_t ps_input_cntl
[32];
1117 uint32_t ps_input_cntl_num
;
1118 uint32_t pa_cl_vs_out_cntl
;
1119 uint32_t vgt_shader_stages_en
;
1120 uint32_t vtx_base_sgpr
;
1121 uint8_t vtx_emit_num
;
1122 struct radv_prim_vertex_count prim_vertex_count
;
1123 bool can_use_guardband
;
1128 unsigned scratch_bytes_per_wave
;
1131 static inline bool radv_pipeline_has_gs(struct radv_pipeline
*pipeline
)
1133 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1136 static inline bool radv_pipeline_has_tess(struct radv_pipeline
*pipeline
)
1138 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ? true : false;
1141 uint32_t radv_shader_stage_to_user_data_0(gl_shader_stage stage
, bool has_gs
, bool has_tess
);
1142 struct ac_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1143 gl_shader_stage stage
,
1146 struct radv_graphics_pipeline_create_info
{
1148 bool db_depth_clear
;
1149 bool db_stencil_clear
;
1150 bool db_depth_disable_expclear
;
1151 bool db_stencil_disable_expclear
;
1152 bool db_flush_depth_inplace
;
1153 bool db_flush_stencil_inplace
;
1154 bool db_resummarize
;
1155 uint32_t custom_blend_mode
;
1159 radv_pipeline_init(struct radv_pipeline
*pipeline
, struct radv_device
*device
,
1160 struct radv_pipeline_cache
*cache
,
1161 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1162 const struct radv_graphics_pipeline_create_info
*extra
,
1163 const VkAllocationCallbacks
*alloc
);
1166 radv_graphics_pipeline_create(VkDevice device
,
1167 VkPipelineCache cache
,
1168 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1169 const struct radv_graphics_pipeline_create_info
*extra
,
1170 const VkAllocationCallbacks
*alloc
,
1171 VkPipeline
*pPipeline
);
1173 struct vk_format_description
;
1174 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1175 int first_non_void
);
1176 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1177 int first_non_void
);
1178 uint32_t radv_translate_colorformat(VkFormat format
);
1179 uint32_t radv_translate_color_numformat(VkFormat format
,
1180 const struct vk_format_description
*desc
,
1181 int first_non_void
);
1182 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1183 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1184 uint32_t radv_translate_dbformat(VkFormat format
);
1185 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1186 const struct vk_format_description
*desc
,
1187 int first_non_void
);
1188 uint32_t radv_translate_tex_numformat(VkFormat format
,
1189 const struct vk_format_description
*desc
,
1190 int first_non_void
);
1191 bool radv_format_pack_clear_color(VkFormat format
,
1192 uint32_t clear_vals
[2],
1193 VkClearColorValue
*value
);
1194 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1196 struct radv_fmask_info
{
1200 unsigned pitch_in_pixels
;
1201 unsigned bank_height
;
1202 unsigned slice_tile_max
;
1203 unsigned tile_mode_index
;
1204 unsigned tile_swizzle
;
1207 struct radv_cmask_info
{
1211 unsigned slice_tile_max
;
1212 unsigned base_address_reg
;
1215 struct r600_htile_info
{
1226 /* The original VkFormat provided by the client. This may not match any
1227 * of the actual surface formats.
1230 VkImageAspectFlags aspects
;
1231 struct ac_surf_info info
;
1232 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1233 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1234 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1240 unsigned queue_family_mask
;
1244 /* Set when bound */
1245 struct radeon_winsys_bo
*bo
;
1246 VkDeviceSize offset
;
1247 uint32_t dcc_offset
;
1248 uint32_t htile_offset
;
1249 struct radeon_surf surface
;
1251 struct radv_fmask_info fmask
;
1252 struct radv_cmask_info cmask
;
1253 uint32_t clear_value_offset
;
1254 uint32_t dcc_pred_offset
;
1257 /* Whether the image has a htile that is known consistent with the contents of
1259 bool radv_layout_has_htile(const struct radv_image
*image
,
1260 VkImageLayout layout
,
1261 unsigned queue_mask
);
1263 /* Whether the image has a htile that is known consistent with the contents of
1264 * the image and is allowed to be in compressed form.
1266 * If this is false reads that don't use the htile should be able to return
1269 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1270 VkImageLayout layout
,
1271 unsigned queue_mask
);
1273 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1274 VkImageLayout layout
,
1275 unsigned queue_mask
);
1278 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1280 static inline uint32_t
1281 radv_get_layerCount(const struct radv_image
*image
,
1282 const VkImageSubresourceRange
*range
)
1284 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1285 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1288 static inline uint32_t
1289 radv_get_levelCount(const struct radv_image
*image
,
1290 const VkImageSubresourceRange
*range
)
1292 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1293 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1296 struct radeon_bo_metadata
;
1298 radv_init_metadata(struct radv_device
*device
,
1299 struct radv_image
*image
,
1300 struct radeon_bo_metadata
*metadata
);
1302 struct radv_image_view
{
1303 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1304 struct radeon_winsys_bo
*bo
;
1306 VkImageViewType type
;
1307 VkImageAspectFlags aspect_mask
;
1309 uint32_t base_layer
;
1310 uint32_t layer_count
;
1312 uint32_t level_count
;
1313 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1315 uint32_t descriptor
[8];
1316 uint32_t fmask_descriptor
[8];
1318 /* Descriptor for use as a storage image as opposed to a sampled image.
1319 * This has a few differences for cube maps (e.g. type).
1321 uint32_t storage_descriptor
[8];
1322 uint32_t storage_fmask_descriptor
[8];
1325 struct radv_image_create_info
{
1326 const VkImageCreateInfo
*vk_info
;
1330 VkResult
radv_image_create(VkDevice _device
,
1331 const struct radv_image_create_info
*info
,
1332 const VkAllocationCallbacks
* alloc
,
1335 void radv_image_view_init(struct radv_image_view
*view
,
1336 struct radv_device
*device
,
1337 const VkImageViewCreateInfo
* pCreateInfo
);
1339 struct radv_buffer_view
{
1340 struct radeon_winsys_bo
*bo
;
1342 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1345 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1346 struct radv_device
*device
,
1347 const VkBufferViewCreateInfo
* pCreateInfo
,
1348 struct radv_cmd_buffer
*cmd_buffer
);
1350 static inline struct VkExtent3D
1351 radv_sanitize_image_extent(const VkImageType imageType
,
1352 const struct VkExtent3D imageExtent
)
1354 switch (imageType
) {
1355 case VK_IMAGE_TYPE_1D
:
1356 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1357 case VK_IMAGE_TYPE_2D
:
1358 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1359 case VK_IMAGE_TYPE_3D
:
1362 unreachable("invalid image type");
1366 static inline struct VkOffset3D
1367 radv_sanitize_image_offset(const VkImageType imageType
,
1368 const struct VkOffset3D imageOffset
)
1370 switch (imageType
) {
1371 case VK_IMAGE_TYPE_1D
:
1372 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1373 case VK_IMAGE_TYPE_2D
:
1374 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1375 case VK_IMAGE_TYPE_3D
:
1378 unreachable("invalid image type");
1383 radv_image_extent_compare(const struct radv_image
*image
,
1384 const VkExtent3D
*extent
)
1386 if (extent
->width
!= image
->info
.width
||
1387 extent
->height
!= image
->info
.height
||
1388 extent
->depth
!= image
->info
.depth
)
1393 struct radv_sampler
{
1397 struct radv_color_buffer_info
{
1398 uint64_t cb_color_base
;
1399 uint64_t cb_color_cmask
;
1400 uint64_t cb_color_fmask
;
1401 uint64_t cb_dcc_base
;
1402 uint32_t cb_color_pitch
;
1403 uint32_t cb_color_slice
;
1404 uint32_t cb_color_view
;
1405 uint32_t cb_color_info
;
1406 uint32_t cb_color_attrib
;
1407 uint32_t cb_color_attrib2
;
1408 uint32_t cb_dcc_control
;
1409 uint32_t cb_color_cmask_slice
;
1410 uint32_t cb_color_fmask_slice
;
1411 uint32_t cb_clear_value0
;
1412 uint32_t cb_clear_value1
;
1413 uint32_t micro_tile_mode
;
1414 uint32_t gfx9_epitch
;
1417 struct radv_ds_buffer_info
{
1418 uint64_t db_z_read_base
;
1419 uint64_t db_stencil_read_base
;
1420 uint64_t db_z_write_base
;
1421 uint64_t db_stencil_write_base
;
1422 uint64_t db_htile_data_base
;
1423 uint32_t db_depth_info
;
1425 uint32_t db_stencil_info
;
1426 uint32_t db_depth_view
;
1427 uint32_t db_depth_size
;
1428 uint32_t db_depth_slice
;
1429 uint32_t db_htile_surface
;
1430 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1431 uint32_t db_z_info2
;
1432 uint32_t db_stencil_info2
;
1436 struct radv_attachment_info
{
1438 struct radv_color_buffer_info cb
;
1439 struct radv_ds_buffer_info ds
;
1441 struct radv_image_view
*attachment
;
1444 struct radv_framebuffer
{
1449 uint32_t attachment_count
;
1450 struct radv_attachment_info attachments
[0];
1453 struct radv_subpass_barrier
{
1454 VkPipelineStageFlags src_stage_mask
;
1455 VkAccessFlags src_access_mask
;
1456 VkAccessFlags dst_access_mask
;
1459 struct radv_subpass
{
1460 uint32_t input_count
;
1461 uint32_t color_count
;
1462 VkAttachmentReference
* input_attachments
;
1463 VkAttachmentReference
* color_attachments
;
1464 VkAttachmentReference
* resolve_attachments
;
1465 VkAttachmentReference depth_stencil_attachment
;
1467 /** Subpass has at least one resolve attachment */
1470 struct radv_subpass_barrier start_barrier
;
1475 struct radv_render_pass_attachment
{
1478 VkAttachmentLoadOp load_op
;
1479 VkAttachmentLoadOp stencil_load_op
;
1480 VkImageLayout initial_layout
;
1481 VkImageLayout final_layout
;
1485 struct radv_render_pass
{
1486 uint32_t attachment_count
;
1487 uint32_t subpass_count
;
1488 VkAttachmentReference
* subpass_attachments
;
1489 struct radv_render_pass_attachment
* attachments
;
1490 struct radv_subpass_barrier end_barrier
;
1491 struct radv_subpass subpasses
[0];
1494 VkResult
radv_device_init_meta(struct radv_device
*device
);
1495 void radv_device_finish_meta(struct radv_device
*device
);
1497 struct radv_query_pool
{
1498 struct radeon_winsys_bo
*bo
;
1500 uint32_t availability_offset
;
1503 uint32_t pipeline_stats_mask
;
1506 struct radv_semaphore
{
1507 /* use a winsys sem for non-exportable */
1508 struct radeon_winsys_sem
*sem
;
1510 uint32_t temp_syncobj
;
1513 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1515 const VkSemaphore
*wait_sems
,
1516 int num_signal_sems
,
1517 const VkSemaphore
*signal_sems
);
1518 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1521 radv_update_descriptor_sets(struct radv_device
*device
,
1522 struct radv_cmd_buffer
*cmd_buffer
,
1523 VkDescriptorSet overrideSet
,
1524 uint32_t descriptorWriteCount
,
1525 const VkWriteDescriptorSet
*pDescriptorWrites
,
1526 uint32_t descriptorCopyCount
,
1527 const VkCopyDescriptorSet
*pDescriptorCopies
);
1530 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1531 struct radv_cmd_buffer
*cmd_buffer
,
1532 struct radv_descriptor_set
*set
,
1533 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1536 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1537 VkPipelineBindPoint pipelineBindPoint
,
1538 VkPipelineLayout _layout
,
1540 uint32_t descriptorWriteCount
,
1541 const VkWriteDescriptorSet
*pDescriptorWrites
);
1543 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1544 struct radv_image
*image
, uint32_t value
);
1545 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1546 struct radv_image
*image
, uint32_t value
);
1549 struct radeon_winsys_fence
*fence
;
1554 struct radeon_winsys_sem
;
1556 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1558 static inline struct __radv_type * \
1559 __radv_type ## _from_handle(__VkType _handle) \
1561 return (struct __radv_type *) _handle; \
1564 static inline __VkType \
1565 __radv_type ## _to_handle(struct __radv_type *_obj) \
1567 return (__VkType) _obj; \
1570 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1572 static inline struct __radv_type * \
1573 __radv_type ## _from_handle(__VkType _handle) \
1575 return (struct __radv_type *)(uintptr_t) _handle; \
1578 static inline __VkType \
1579 __radv_type ## _to_handle(struct __radv_type *_obj) \
1581 return (__VkType)(uintptr_t) _obj; \
1584 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1585 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1587 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1588 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1589 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1590 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1591 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1593 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1594 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1595 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1596 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1597 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1598 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1599 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1600 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1601 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1602 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1603 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1604 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1605 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1606 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1607 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1608 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1609 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1610 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1611 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1612 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1613 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1615 #endif /* RADV_PRIVATE_H */