2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
52 #include "vk_debug_report.h"
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
61 #include <llvm-c/TargetMachine.h>
63 /* Pre-declarations needed for WSI entrypoints */
66 typedef struct xcb_connection_t xcb_connection_t
;
67 typedef uint32_t xcb_visualid_t
;
68 typedef uint32_t xcb_window_t
;
70 #include <vulkan/vulkan.h>
71 #include <vulkan/vulkan_intel.h>
72 #include <vulkan/vk_icd.h>
73 #include <vulkan/vk_android_native_buffer.h>
75 #include "radv_entrypoints.h"
77 #include "wsi_common.h"
79 #define ATI_VENDOR_ID 0x1002
82 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_VIEWPORTS 16
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_BUFFERS 16
90 #define MAX_SAMPLES_LOG2 4
91 #define NUM_META_FS_KEYS 13
92 #define RADV_MAX_DRM_DEVICES 8
95 #define NUM_DEPTH_CLEAR_PIPELINES 3
99 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
106 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
107 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
108 RADV_MEM_TYPE_GTT_CACHED
,
112 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
114 static inline uint32_t
115 align_u32(uint32_t v
, uint32_t a
)
117 assert(a
!= 0 && a
== (a
& -a
));
118 return (v
+ a
- 1) & ~(a
- 1);
121 static inline uint32_t
122 align_u32_npot(uint32_t v
, uint32_t a
)
124 return (v
+ a
- 1) / a
* a
;
127 static inline uint64_t
128 align_u64(uint64_t v
, uint64_t a
)
130 assert(a
!= 0 && a
== (a
& -a
));
131 return (v
+ a
- 1) & ~(a
- 1);
134 static inline int32_t
135 align_i32(int32_t v
, int32_t a
)
137 assert(a
!= 0 && a
== (a
& -a
));
138 return (v
+ a
- 1) & ~(a
- 1);
141 /** Alignment must be a power of 2. */
143 radv_is_aligned(uintmax_t n
, uintmax_t a
)
145 assert(a
== (a
& -a
));
146 return (n
& (a
- 1)) == 0;
149 static inline uint32_t
150 round_up_u32(uint32_t v
, uint32_t a
)
152 return (v
+ a
- 1) / a
;
155 static inline uint64_t
156 round_up_u64(uint64_t v
, uint64_t a
)
158 return (v
+ a
- 1) / a
;
161 static inline uint32_t
162 radv_minify(uint32_t n
, uint32_t levels
)
164 if (unlikely(n
== 0))
167 return MAX2(n
>> levels
, 1);
170 radv_clamp_f(float f
, float min
, float max
)
183 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
185 if (*inout_mask
& clear_mask
) {
186 *inout_mask
&= ~clear_mask
;
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
203 /* Whenever we generate an error, pass it through this function. Useful for
204 * debugging, where we can break on it. Only call at error site, not when
205 * propagating errors. Might be useful to plug in a stack trace here.
208 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
211 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
212 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
214 #define vk_error(error) error
215 #define vk_errorf(error, format, ...) error
218 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
219 radv_printflike(3, 4);
220 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
221 void radv_loge_v(const char *format
, va_list va
);
224 * Print a FINISHME message, including its source location.
226 #define radv_finishme(format, ...) \
228 static bool reported = false; \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
235 /* A non-fatal assert. Useful for debugging. */
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
242 #define radv_assert(x)
245 #define stub_return(v) \
247 radv_finishme("stub %s", __func__); \
253 radv_finishme("stub %s", __func__); \
257 void *radv_lookup_entrypoint(const char *name
);
259 struct radv_physical_device
{
260 VK_LOADER_DATA _loader_data
;
262 struct radv_instance
* instance
;
264 struct radeon_winsys
*ws
;
265 struct radeon_info rad_info
;
267 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
268 uint8_t driver_uuid
[VK_UUID_SIZE
];
269 uint8_t device_uuid
[VK_UUID_SIZE
];
270 uint8_t cache_uuid
[VK_UUID_SIZE
];
273 struct wsi_device wsi_device
;
275 bool has_rbplus
; /* if RB+ register exist */
276 bool rbplus_allowed
; /* if RB+ is allowed */
277 bool has_clear_state
;
278 bool cpdma_prefetch_writes_memory
;
279 bool has_scissor_bug
;
281 /* This is the drivers on-disk cache used as a fallback as opposed to
282 * the pipeline cache defined by apps.
284 struct disk_cache
* disk_cache
;
286 VkPhysicalDeviceMemoryProperties memory_properties
;
287 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
290 struct radv_instance
{
291 VK_LOADER_DATA _loader_data
;
293 VkAllocationCallbacks alloc
;
296 int physicalDeviceCount
;
297 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
299 uint64_t debug_flags
;
300 uint64_t perftest_flags
;
302 struct vk_debug_report_instance debug_report_callbacks
;
305 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
306 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
308 bool radv_instance_extension_supported(const char *name
);
309 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
310 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
315 struct radv_pipeline_cache
{
316 struct radv_device
* device
;
317 pthread_mutex_t mutex
;
321 uint32_t kernel_count
;
322 struct cache_entry
** hash_table
;
325 VkAllocationCallbacks alloc
;
328 struct radv_pipeline_key
{
329 uint32_t instance_rate_inputs
;
330 unsigned tess_input_vertices
;
334 uint8_t log2_ps_iter_samples
;
335 uint8_t log2_num_samples
;
336 uint32_t multisample
: 1;
337 uint32_t has_multiview_view_index
: 1;
341 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
342 struct radv_device
*device
);
344 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
346 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
347 const void *data
, size_t size
);
349 struct radv_shader_variant
;
352 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
353 struct radv_pipeline_cache
*cache
,
354 const unsigned char *sha1
,
355 struct radv_shader_variant
**variants
);
358 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
359 struct radv_pipeline_cache
*cache
,
360 const unsigned char *sha1
,
361 struct radv_shader_variant
**variants
,
362 const void *const *codes
,
363 const unsigned *code_sizes
);
365 enum radv_blit_ds_layout
{
366 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
367 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
368 RADV_BLIT_DS_LAYOUT_COUNT
,
371 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
373 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
376 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
378 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
381 enum radv_meta_dst_layout
{
382 RADV_META_DST_LAYOUT_GENERAL
,
383 RADV_META_DST_LAYOUT_OPTIMAL
,
384 RADV_META_DST_LAYOUT_COUNT
,
387 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
389 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
392 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
394 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
397 struct radv_meta_state
{
398 VkAllocationCallbacks alloc
;
400 struct radv_pipeline_cache cache
;
403 * Use array element `i` for images with `2^i` samples.
406 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
407 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
409 VkRenderPass depthstencil_rp
;
410 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
411 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
412 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
413 } clear
[1 + MAX_SAMPLES_LOG2
];
415 VkPipelineLayout clear_color_p_layout
;
416 VkPipelineLayout clear_depth_p_layout
;
418 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
420 /** Pipeline that blits from a 1D image. */
421 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
423 /** Pipeline that blits from a 2D image. */
424 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
426 /** Pipeline that blits from a 3D image. */
427 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
429 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
430 VkPipeline depth_only_1d_pipeline
;
431 VkPipeline depth_only_2d_pipeline
;
432 VkPipeline depth_only_3d_pipeline
;
434 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
435 VkPipeline stencil_only_1d_pipeline
;
436 VkPipeline stencil_only_2d_pipeline
;
437 VkPipeline stencil_only_3d_pipeline
;
438 VkPipelineLayout pipeline_layout
;
439 VkDescriptorSetLayout ds_layout
;
443 VkRenderPass render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
445 VkPipelineLayout p_layouts
[3];
446 VkDescriptorSetLayout ds_layouts
[3];
447 VkPipeline pipelines
[3][NUM_META_FS_KEYS
];
449 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
450 VkPipeline depth_only_pipeline
[3];
452 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
453 VkPipeline stencil_only_pipeline
[3];
457 VkPipelineLayout img_p_layout
;
458 VkDescriptorSetLayout img_ds_layout
;
460 VkPipeline pipeline_3d
;
463 VkPipelineLayout img_p_layout
;
464 VkDescriptorSetLayout img_ds_layout
;
466 VkPipeline pipeline_3d
;
469 VkPipelineLayout img_p_layout
;
470 VkDescriptorSetLayout img_ds_layout
;
472 VkPipeline pipeline_3d
;
475 VkPipelineLayout img_p_layout
;
476 VkDescriptorSetLayout img_ds_layout
;
478 VkPipeline pipeline_3d
;
482 VkPipelineLayout p_layout
;
483 VkPipeline pipeline
[NUM_META_FS_KEYS
];
484 VkRenderPass pass
[NUM_META_FS_KEYS
];
488 VkDescriptorSetLayout ds_layout
;
489 VkPipelineLayout p_layout
;
492 VkPipeline i_pipeline
;
493 VkPipeline srgb_pipeline
;
494 } rc
[MAX_SAMPLES_LOG2
];
498 VkDescriptorSetLayout ds_layout
;
499 VkPipelineLayout p_layout
;
502 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
503 VkPipeline pipeline
[NUM_META_FS_KEYS
];
504 } rc
[MAX_SAMPLES_LOG2
];
508 VkPipelineLayout p_layout
;
509 VkPipeline decompress_pipeline
;
510 VkPipeline resummarize_pipeline
;
512 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
515 VkPipelineLayout p_layout
;
516 VkPipeline cmask_eliminate_pipeline
;
517 VkPipeline fmask_decompress_pipeline
;
518 VkPipeline dcc_decompress_pipeline
;
521 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
522 VkPipelineLayout dcc_decompress_compute_p_layout
;
523 VkPipeline dcc_decompress_compute_pipeline
;
527 VkPipelineLayout fill_p_layout
;
528 VkPipelineLayout copy_p_layout
;
529 VkDescriptorSetLayout fill_ds_layout
;
530 VkDescriptorSetLayout copy_ds_layout
;
531 VkPipeline fill_pipeline
;
532 VkPipeline copy_pipeline
;
536 VkDescriptorSetLayout ds_layout
;
537 VkPipelineLayout p_layout
;
538 VkPipeline occlusion_query_pipeline
;
539 VkPipeline pipeline_statistics_query_pipeline
;
544 #define RADV_QUEUE_GENERAL 0
545 #define RADV_QUEUE_COMPUTE 1
546 #define RADV_QUEUE_TRANSFER 2
548 #define RADV_MAX_QUEUE_FAMILIES 3
550 enum ring_type
radv_queue_family_to_ring(int f
);
553 VK_LOADER_DATA _loader_data
;
554 struct radv_device
* device
;
555 struct radeon_winsys_ctx
*hw_ctx
;
556 enum radeon_ctx_priority priority
;
557 uint32_t queue_family_index
;
560 uint32_t scratch_size
;
561 uint32_t compute_scratch_size
;
562 uint32_t esgs_ring_size
;
563 uint32_t gsvs_ring_size
;
565 bool has_sample_positions
;
567 struct radeon_winsys_bo
*scratch_bo
;
568 struct radeon_winsys_bo
*descriptor_bo
;
569 struct radeon_winsys_bo
*compute_scratch_bo
;
570 struct radeon_winsys_bo
*esgs_ring_bo
;
571 struct radeon_winsys_bo
*gsvs_ring_bo
;
572 struct radeon_winsys_bo
*tess_factor_ring_bo
;
573 struct radeon_winsys_bo
*tess_offchip_ring_bo
;
574 struct radeon_winsys_cs
*initial_preamble_cs
;
575 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
576 struct radeon_winsys_cs
*continue_preamble_cs
;
580 VK_LOADER_DATA _loader_data
;
582 VkAllocationCallbacks alloc
;
584 struct radv_instance
* instance
;
585 struct radeon_winsys
*ws
;
587 struct radv_meta_state meta_state
;
589 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
590 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
591 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
593 bool always_use_syncobj
;
594 bool llvm_supports_spill
;
595 bool has_distributed_tess
;
598 uint32_t tess_offchip_block_dw_size
;
599 uint32_t scratch_waves
;
600 uint32_t dispatch_initiator
;
602 uint32_t gs_table_depth
;
604 /* MSAA sample locations.
605 * The first index is the sample index.
606 * The second index is the coordinate: X, Y. */
607 float sample_locations_1x
[1][2];
608 float sample_locations_2x
[2][2];
609 float sample_locations_4x
[4][2];
610 float sample_locations_8x
[8][2];
611 float sample_locations_16x
[16][2];
614 uint32_t gfx_init_size_dw
;
615 struct radeon_winsys_bo
*gfx_init
;
617 struct radeon_winsys_bo
*trace_bo
;
618 uint32_t *trace_id_ptr
;
620 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
621 bool keep_shader_info
;
623 struct radv_physical_device
*physical_device
;
625 /* Backup in-memory cache to be used if the app doesn't provide one */
626 struct radv_pipeline_cache
* mem_cache
;
629 * use different counters so MSAA MRTs get consecutive surface indices,
630 * even if MASK is allocated in between.
632 uint32_t image_mrt_offset_counter
;
633 uint32_t fmask_mrt_offset_counter
;
634 struct list_head shader_slabs
;
635 mtx_t shader_slab_mutex
;
637 /* For detecting VM faults reported by dmesg. */
638 uint64_t dmesg_timestamp
;
641 struct radv_device_memory
{
642 struct radeon_winsys_bo
*bo
;
643 /* for dedicated allocations */
644 struct radv_image
*image
;
645 struct radv_buffer
*buffer
;
647 VkDeviceSize map_size
;
652 struct radv_descriptor_range
{
657 struct radv_descriptor_set
{
658 const struct radv_descriptor_set_layout
*layout
;
661 struct radeon_winsys_bo
*bo
;
663 uint32_t *mapped_ptr
;
664 struct radv_descriptor_range
*dynamic_descriptors
;
666 struct radeon_winsys_bo
*descriptors
[0];
669 struct radv_push_descriptor_set
671 struct radv_descriptor_set set
;
675 struct radv_descriptor_pool_entry
{
678 struct radv_descriptor_set
*set
;
681 struct radv_descriptor_pool
{
682 struct radeon_winsys_bo
*bo
;
684 uint64_t current_offset
;
687 uint8_t *host_memory_base
;
688 uint8_t *host_memory_ptr
;
689 uint8_t *host_memory_end
;
691 uint32_t entry_count
;
692 uint32_t max_entry_count
;
693 struct radv_descriptor_pool_entry entries
[0];
696 struct radv_descriptor_update_template_entry
{
697 VkDescriptorType descriptor_type
;
699 /* The number of descriptors to update */
700 uint32_t descriptor_count
;
702 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
705 /* In dwords. Not valid/used for dynamic descriptors */
708 uint32_t buffer_offset
;
710 /* Only valid for combined image samplers and samplers */
711 uint16_t has_sampler
;
717 /* For push descriptors */
718 const uint32_t *immutable_samplers
;
721 struct radv_descriptor_update_template
{
722 uint32_t entry_count
;
723 struct radv_descriptor_update_template_entry entry
[0];
727 struct radv_device
* device
;
730 VkBufferUsageFlags usage
;
731 VkBufferCreateFlags flags
;
734 struct radeon_winsys_bo
* bo
;
740 enum radv_dynamic_state_bits
{
741 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
742 RADV_DYNAMIC_SCISSOR
= 1 << 1,
743 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
744 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
745 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
746 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
747 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
748 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
749 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
750 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
751 RADV_DYNAMIC_ALL
= (1 << 10) - 1,
754 enum radv_cmd_dirty_bits
{
755 /* Keep the dynamic state dirty bits in sync with
756 * enum radv_dynamic_state_bits */
757 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
758 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
759 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
760 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
761 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
762 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
763 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
764 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
765 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
766 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
767 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 10) - 1,
768 RADV_CMD_DIRTY_PIPELINE
= 1 << 10,
769 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 11,
770 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 12,
771 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 13,
774 enum radv_cmd_flush_bits
{
775 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
776 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
777 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
778 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
779 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
780 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
781 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
782 /* Same as above, but only writes back and doesn't invalidate */
783 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
784 /* Framebuffer caches */
785 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
786 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
787 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
788 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
789 /* Engine synchronization. */
790 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
791 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
792 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
793 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
795 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
796 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
797 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
798 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
801 struct radv_vertex_binding
{
802 struct radv_buffer
* buffer
;
806 struct radv_viewport_state
{
808 VkViewport viewports
[MAX_VIEWPORTS
];
811 struct radv_scissor_state
{
813 VkRect2D scissors
[MAX_SCISSORS
];
816 struct radv_discard_rectangle_state
{
818 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
821 struct radv_dynamic_state
{
823 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
824 * Defines the set of saved dynamic state.
828 struct radv_viewport_state viewport
;
830 struct radv_scissor_state scissor
;
840 float blend_constants
[4];
850 } stencil_compare_mask
;
855 } stencil_write_mask
;
862 struct radv_discard_rectangle_state discard_rectangle
;
865 extern const struct radv_dynamic_state default_dynamic_state
;
868 radv_get_debug_option_name(int id
);
871 radv_get_perftest_option_name(int id
);
874 * Attachment state when recording a renderpass instance.
876 * The clear value is valid only if there exists a pending clear.
878 struct radv_attachment_state
{
879 VkImageAspectFlags pending_clear_aspects
;
880 uint32_t cleared_views
;
881 VkClearValue clear_value
;
882 VkImageLayout current_layout
;
885 struct radv_cmd_state
{
886 /* Vertex descriptors */
887 bool vb_prefetch_dirty
;
891 bool push_descriptors_dirty
;
895 struct radv_pipeline
* pipeline
;
896 struct radv_pipeline
* emitted_pipeline
;
897 struct radv_pipeline
* compute_pipeline
;
898 struct radv_pipeline
* emitted_compute_pipeline
;
899 struct radv_framebuffer
* framebuffer
;
900 struct radv_render_pass
* pass
;
901 const struct radv_subpass
* subpass
;
902 struct radv_dynamic_state dynamic
;
903 struct radv_attachment_state
* attachments
;
904 VkRect2D render_area
;
907 struct radv_buffer
*index_buffer
;
908 uint64_t index_offset
;
910 uint32_t max_index_count
;
912 int32_t last_index_type
;
914 int32_t last_primitive_reset_en
;
915 uint32_t last_primitive_reset_index
;
916 enum radv_cmd_flush_bits flush_bits
;
917 unsigned active_occlusion_queries
;
919 uint32_t descriptors_dirty
;
920 uint32_t valid_descriptors
;
922 uint32_t last_ia_multi_vgt_param
;
924 uint32_t last_num_instances
;
925 uint32_t last_first_instance
;
926 uint32_t last_vertex_offset
;
929 struct radv_cmd_pool
{
930 VkAllocationCallbacks alloc
;
931 struct list_head cmd_buffers
;
932 struct list_head free_cmd_buffers
;
933 uint32_t queue_family_index
;
936 struct radv_cmd_buffer_upload
{
940 struct radeon_winsys_bo
*upload_bo
;
941 struct list_head list
;
944 enum radv_cmd_buffer_status
{
945 RADV_CMD_BUFFER_STATUS_INVALID
,
946 RADV_CMD_BUFFER_STATUS_INITIAL
,
947 RADV_CMD_BUFFER_STATUS_RECORDING
,
948 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
949 RADV_CMD_BUFFER_STATUS_PENDING
,
952 struct radv_cmd_buffer
{
953 VK_LOADER_DATA _loader_data
;
955 struct radv_device
* device
;
957 struct radv_cmd_pool
* pool
;
958 struct list_head pool_link
;
960 VkCommandBufferUsageFlags usage_flags
;
961 VkCommandBufferLevel level
;
962 enum radv_cmd_buffer_status status
;
963 struct radeon_winsys_cs
*cs
;
964 struct radv_cmd_state state
;
965 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
966 uint32_t queue_family_index
;
968 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
969 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
970 VkShaderStageFlags push_constant_stages
;
971 struct radv_push_descriptor_set push_descriptors
;
972 struct radv_descriptor_set meta_push_descriptors
;
973 struct radv_descriptor_set
*descriptors
[MAX_SETS
];
975 struct radv_cmd_buffer_upload upload
;
977 uint32_t scratch_size_needed
;
978 uint32_t compute_scratch_size_needed
;
979 uint32_t esgs_ring_size_needed
;
980 uint32_t gsvs_ring_size_needed
;
981 bool tess_rings_needed
;
982 bool sample_positions_needed
;
984 VkResult record_result
;
986 int ring_offsets_idx
; /* just used for verification */
987 uint32_t gfx9_fence_offset
;
988 struct radeon_winsys_bo
*gfx9_fence_bo
;
989 uint32_t gfx9_fence_idx
;
994 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
996 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
997 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
999 void cik_create_gfx_config(struct radv_device
*device
);
1001 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
1002 int count
, const VkViewport
*viewports
);
1003 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
1004 int count
, const VkRect2D
*scissors
,
1005 const VkViewport
*viewports
, bool can_use_guardband
);
1006 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1007 bool instanced_draw
, bool indirect_draw
,
1008 uint32_t draw_vertex_count
);
1009 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
1011 enum chip_class chip_class
,
1013 unsigned event
, unsigned event_flags
,
1017 uint32_t new_fence
);
1019 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
1021 uint64_t va
, uint32_t ref
,
1023 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
1025 enum chip_class chip_class
,
1026 uint32_t *fence_ptr
, uint64_t va
,
1028 enum radv_cmd_flush_bits flush_bits
);
1029 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1030 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
1031 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1032 uint64_t src_va
, uint64_t dest_va
,
1034 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1036 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1037 uint64_t size
, unsigned value
);
1038 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1040 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1043 unsigned *out_offset
,
1046 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1047 const struct radv_subpass
*subpass
,
1050 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1051 unsigned size
, unsigned alignmnet
,
1052 const void *data
, unsigned *out_offset
);
1054 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1055 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1056 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1057 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1058 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
1059 unsigned radv_cayman_get_maxdist(int log_samples
);
1060 void radv_device_init_msaa(struct radv_device
*device
);
1061 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1062 struct radv_image
*image
,
1063 VkClearDepthStencilValue ds_clear_value
,
1064 VkImageAspectFlags aspects
);
1065 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1066 struct radv_image
*image
,
1068 uint32_t color_values
[2]);
1069 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1070 struct radv_image
*image
,
1072 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1073 struct radeon_winsys_bo
*bo
,
1074 uint64_t offset
, uint64_t size
, uint32_t value
);
1075 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1076 bool radv_get_memory_fd(struct radv_device
*device
,
1077 struct radv_device_memory
*memory
,
1081 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1083 * Limitations: Can't call normal dispatch functions without binding or rebinding
1084 * the compute pipeline.
1086 void radv_unaligned_dispatch(
1087 struct radv_cmd_buffer
*cmd_buffer
,
1093 struct radeon_winsys_bo
*bo
;
1097 struct radv_shader_module
;
1099 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1100 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1101 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1103 radv_hash_shaders(unsigned char *hash
,
1104 const VkPipelineShaderStageCreateInfo
**stages
,
1105 const struct radv_pipeline_layout
*layout
,
1106 const struct radv_pipeline_key
*key
,
1109 static inline gl_shader_stage
1110 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1112 assert(__builtin_popcount(vk_stage
) == 1);
1113 return ffs(vk_stage
) - 1;
1116 static inline VkShaderStageFlagBits
1117 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1119 return (1 << mesa_stage
);
1122 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1124 #define radv_foreach_stage(stage, stage_bits) \
1125 for (gl_shader_stage stage, \
1126 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1127 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1128 __tmp &= ~(1 << (stage)))
1130 struct radv_depth_stencil_state
{
1131 uint32_t db_depth_control
;
1132 uint32_t db_stencil_control
;
1133 uint32_t db_render_control
;
1134 uint32_t db_render_override2
;
1137 struct radv_blend_state
{
1138 uint32_t cb_color_control
;
1139 uint32_t cb_target_mask
;
1140 uint32_t sx_mrt_blend_opt
[8];
1141 uint32_t cb_blend_control
[8];
1143 uint32_t spi_shader_col_format
;
1144 uint32_t cb_shader_mask
;
1145 uint32_t db_alpha_to_mask
;
1148 unsigned radv_format_meta_fs_key(VkFormat format
);
1150 struct radv_raster_state
{
1151 uint32_t pa_cl_clip_cntl
;
1152 uint32_t spi_interp_control
;
1153 uint32_t pa_su_vtx_cntl
;
1154 uint32_t pa_su_sc_mode_cntl
;
1157 struct radv_multisample_state
{
1159 uint32_t pa_sc_line_cntl
;
1160 uint32_t pa_sc_mode_cntl_0
;
1161 uint32_t pa_sc_mode_cntl_1
;
1162 uint32_t pa_sc_aa_config
;
1163 uint32_t pa_sc_aa_mask
[2];
1164 unsigned num_samples
;
1167 struct radv_prim_vertex_count
{
1172 struct radv_tessellation_state
{
1173 uint32_t ls_hs_config
;
1174 uint32_t tcs_in_layout
;
1175 uint32_t tcs_out_layout
;
1176 uint32_t tcs_out_offsets
;
1177 uint32_t offchip_layout
;
1178 unsigned num_patches
;
1180 unsigned num_tcs_input_cp
;
1184 struct radv_gs_state
{
1185 uint32_t vgt_gs_onchip_cntl
;
1186 uint32_t vgt_gs_max_prims_per_subgroup
;
1187 uint32_t vgt_esgs_ring_itemsize
;
1191 struct radv_vertex_elements_info
{
1192 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1193 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1194 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1195 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1199 struct radv_vs_state
{
1200 uint32_t pa_cl_vs_out_cntl
;
1201 uint32_t spi_shader_pos_format
;
1202 uint32_t spi_vs_out_config
;
1203 uint32_t vgt_reuse_off
;
1206 struct radv_binning_state
{
1207 uint32_t pa_sc_binner_cntl_0
;
1208 uint32_t db_dfsm_control
;
1211 #define SI_GS_PER_ES 128
1213 struct radv_pipeline
{
1214 struct radv_device
* device
;
1215 struct radv_dynamic_state dynamic_state
;
1217 struct radv_pipeline_layout
* layout
;
1219 bool needs_data_cache
;
1220 bool need_indirect_descriptor_sets
;
1221 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1222 struct radv_shader_variant
*gs_copy_shader
;
1223 VkShaderStageFlags active_stages
;
1225 struct radv_vertex_elements_info vertex_elements
;
1227 uint32_t binding_stride
[MAX_VBS
];
1229 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1232 struct radv_blend_state blend
;
1233 struct radv_depth_stencil_state ds
;
1234 struct radv_raster_state raster
;
1235 struct radv_multisample_state ms
;
1236 struct radv_tessellation_state tess
;
1237 struct radv_gs_state gs
;
1238 struct radv_vs_state vs
;
1239 struct radv_binning_state bin
;
1240 uint32_t db_shader_control
;
1241 uint32_t shader_z_format
;
1242 uint32_t spi_baryc_cntl
;
1245 uint32_t vgt_gs_mode
;
1246 bool vgt_primitiveid_en
;
1247 bool prim_restart_enable
;
1248 bool partial_es_wave
;
1249 uint8_t primgroup_size
;
1250 unsigned esgs_ring_size
;
1251 unsigned gsvs_ring_size
;
1252 uint32_t ps_input_cntl
[32];
1253 uint32_t ps_input_cntl_num
;
1254 uint32_t vgt_shader_stages_en
;
1255 uint32_t vtx_base_sgpr
;
1256 uint32_t base_ia_multi_vgt_param
;
1257 bool wd_switch_on_eop
;
1258 bool ia_switch_on_eoi
;
1259 bool partial_vs_wave
;
1260 uint8_t vtx_emit_num
;
1261 uint32_t vtx_reuse_depth
;
1262 struct radv_prim_vertex_count prim_vertex_count
;
1263 bool can_use_guardband
;
1264 uint32_t pa_sc_cliprect_rule
;
1265 uint32_t needed_dynamic_state
;
1270 unsigned scratch_bytes_per_wave
;
1273 static inline bool radv_pipeline_has_gs(struct radv_pipeline
*pipeline
)
1275 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1278 static inline bool radv_pipeline_has_tess(struct radv_pipeline
*pipeline
)
1280 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1283 struct ac_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1284 gl_shader_stage stage
,
1287 struct radv_shader_variant
*radv_get_vertex_shader(struct radv_pipeline
*pipeline
);
1289 struct radv_graphics_pipeline_create_info
{
1291 bool db_depth_clear
;
1292 bool db_stencil_clear
;
1293 bool db_depth_disable_expclear
;
1294 bool db_stencil_disable_expclear
;
1295 bool db_flush_depth_inplace
;
1296 bool db_flush_stencil_inplace
;
1297 bool db_resummarize
;
1298 uint32_t custom_blend_mode
;
1302 radv_graphics_pipeline_create(VkDevice device
,
1303 VkPipelineCache cache
,
1304 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1305 const struct radv_graphics_pipeline_create_info
*extra
,
1306 const VkAllocationCallbacks
*alloc
,
1307 VkPipeline
*pPipeline
);
1309 struct vk_format_description
;
1310 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1311 int first_non_void
);
1312 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1313 int first_non_void
);
1314 uint32_t radv_translate_colorformat(VkFormat format
);
1315 uint32_t radv_translate_color_numformat(VkFormat format
,
1316 const struct vk_format_description
*desc
,
1317 int first_non_void
);
1318 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1319 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1320 uint32_t radv_translate_dbformat(VkFormat format
);
1321 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1322 const struct vk_format_description
*desc
,
1323 int first_non_void
);
1324 uint32_t radv_translate_tex_numformat(VkFormat format
,
1325 const struct vk_format_description
*desc
,
1326 int first_non_void
);
1327 bool radv_format_pack_clear_color(VkFormat format
,
1328 uint32_t clear_vals
[2],
1329 VkClearColorValue
*value
);
1330 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1331 bool radv_dcc_formats_compatible(VkFormat format1
,
1334 struct radv_fmask_info
{
1338 unsigned pitch_in_pixels
;
1339 unsigned bank_height
;
1340 unsigned slice_tile_max
;
1341 unsigned tile_mode_index
;
1342 unsigned tile_swizzle
;
1345 struct radv_cmask_info
{
1349 unsigned slice_tile_max
;
1354 /* The original VkFormat provided by the client. This may not match any
1355 * of the actual surface formats.
1358 VkImageAspectFlags aspects
;
1359 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1360 struct ac_surf_info info
;
1361 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1362 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1367 unsigned queue_family_mask
;
1371 /* Set when bound */
1372 struct radeon_winsys_bo
*bo
;
1373 VkDeviceSize offset
;
1374 uint64_t dcc_offset
;
1375 uint64_t htile_offset
;
1376 bool tc_compatible_htile
;
1377 struct radeon_surf surface
;
1379 struct radv_fmask_info fmask
;
1380 struct radv_cmask_info cmask
;
1381 uint64_t clear_value_offset
;
1382 uint64_t dcc_pred_offset
;
1384 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1385 VkDeviceMemory owned_memory
;
1388 /* Whether the image has a htile that is known consistent with the contents of
1390 bool radv_layout_has_htile(const struct radv_image
*image
,
1391 VkImageLayout layout
,
1392 unsigned queue_mask
);
1394 /* Whether the image has a htile that is known consistent with the contents of
1395 * the image and is allowed to be in compressed form.
1397 * If this is false reads that don't use the htile should be able to return
1400 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1401 VkImageLayout layout
,
1402 unsigned queue_mask
);
1404 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1405 VkImageLayout layout
,
1406 unsigned queue_mask
);
1408 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1409 VkImageLayout layout
,
1410 unsigned queue_mask
);
1413 radv_vi_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1415 return image
->surface
.dcc_size
&& level
< image
->surface
.num_dcc_levels
;
1419 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1421 return image
->surface
.htile_size
&& level
== 0;
1424 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1426 static inline uint32_t
1427 radv_get_layerCount(const struct radv_image
*image
,
1428 const VkImageSubresourceRange
*range
)
1430 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1431 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1434 static inline uint32_t
1435 radv_get_levelCount(const struct radv_image
*image
,
1436 const VkImageSubresourceRange
*range
)
1438 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1439 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1442 struct radeon_bo_metadata
;
1444 radv_init_metadata(struct radv_device
*device
,
1445 struct radv_image
*image
,
1446 struct radeon_bo_metadata
*metadata
);
1448 struct radv_image_view
{
1449 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1450 struct radeon_winsys_bo
*bo
;
1452 VkImageViewType type
;
1453 VkImageAspectFlags aspect_mask
;
1455 uint32_t base_layer
;
1456 uint32_t layer_count
;
1458 uint32_t level_count
;
1459 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1461 uint32_t descriptor
[16];
1463 /* Descriptor for use as a storage image as opposed to a sampled image.
1464 * This has a few differences for cube maps (e.g. type).
1466 uint32_t storage_descriptor
[16];
1469 struct radv_image_create_info
{
1470 const VkImageCreateInfo
*vk_info
;
1472 bool no_metadata_planes
;
1475 VkResult
radv_image_create(VkDevice _device
,
1476 const struct radv_image_create_info
*info
,
1477 const VkAllocationCallbacks
* alloc
,
1481 radv_image_from_gralloc(VkDevice device_h
,
1482 const VkImageCreateInfo
*base_info
,
1483 const VkNativeBufferANDROID
*gralloc_info
,
1484 const VkAllocationCallbacks
*alloc
,
1485 VkImage
*out_image_h
);
1487 void radv_image_view_init(struct radv_image_view
*view
,
1488 struct radv_device
*device
,
1489 const VkImageViewCreateInfo
* pCreateInfo
);
1491 struct radv_buffer_view
{
1492 struct radeon_winsys_bo
*bo
;
1494 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1497 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1498 struct radv_device
*device
,
1499 const VkBufferViewCreateInfo
* pCreateInfo
);
1501 static inline struct VkExtent3D
1502 radv_sanitize_image_extent(const VkImageType imageType
,
1503 const struct VkExtent3D imageExtent
)
1505 switch (imageType
) {
1506 case VK_IMAGE_TYPE_1D
:
1507 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1508 case VK_IMAGE_TYPE_2D
:
1509 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1510 case VK_IMAGE_TYPE_3D
:
1513 unreachable("invalid image type");
1517 static inline struct VkOffset3D
1518 radv_sanitize_image_offset(const VkImageType imageType
,
1519 const struct VkOffset3D imageOffset
)
1521 switch (imageType
) {
1522 case VK_IMAGE_TYPE_1D
:
1523 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1524 case VK_IMAGE_TYPE_2D
:
1525 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1526 case VK_IMAGE_TYPE_3D
:
1529 unreachable("invalid image type");
1534 radv_image_extent_compare(const struct radv_image
*image
,
1535 const VkExtent3D
*extent
)
1537 if (extent
->width
!= image
->info
.width
||
1538 extent
->height
!= image
->info
.height
||
1539 extent
->depth
!= image
->info
.depth
)
1544 struct radv_sampler
{
1548 struct radv_color_buffer_info
{
1549 uint64_t cb_color_base
;
1550 uint64_t cb_color_cmask
;
1551 uint64_t cb_color_fmask
;
1552 uint64_t cb_dcc_base
;
1553 uint32_t cb_color_pitch
;
1554 uint32_t cb_color_slice
;
1555 uint32_t cb_color_view
;
1556 uint32_t cb_color_info
;
1557 uint32_t cb_color_attrib
;
1558 uint32_t cb_color_attrib2
;
1559 uint32_t cb_dcc_control
;
1560 uint32_t cb_color_cmask_slice
;
1561 uint32_t cb_color_fmask_slice
;
1564 struct radv_ds_buffer_info
{
1565 uint64_t db_z_read_base
;
1566 uint64_t db_stencil_read_base
;
1567 uint64_t db_z_write_base
;
1568 uint64_t db_stencil_write_base
;
1569 uint64_t db_htile_data_base
;
1570 uint32_t db_depth_info
;
1572 uint32_t db_stencil_info
;
1573 uint32_t db_depth_view
;
1574 uint32_t db_depth_size
;
1575 uint32_t db_depth_slice
;
1576 uint32_t db_htile_surface
;
1577 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1578 uint32_t db_z_info2
;
1579 uint32_t db_stencil_info2
;
1583 struct radv_attachment_info
{
1585 struct radv_color_buffer_info cb
;
1586 struct radv_ds_buffer_info ds
;
1588 struct radv_image_view
*attachment
;
1591 struct radv_framebuffer
{
1596 uint32_t attachment_count
;
1597 struct radv_attachment_info attachments
[0];
1600 struct radv_subpass_barrier
{
1601 VkPipelineStageFlags src_stage_mask
;
1602 VkAccessFlags src_access_mask
;
1603 VkAccessFlags dst_access_mask
;
1606 struct radv_subpass
{
1607 uint32_t input_count
;
1608 uint32_t color_count
;
1609 VkAttachmentReference
* input_attachments
;
1610 VkAttachmentReference
* color_attachments
;
1611 VkAttachmentReference
* resolve_attachments
;
1612 VkAttachmentReference depth_stencil_attachment
;
1614 /** Subpass has at least one resolve attachment */
1617 struct radv_subpass_barrier start_barrier
;
1622 struct radv_render_pass_attachment
{
1625 VkAttachmentLoadOp load_op
;
1626 VkAttachmentLoadOp stencil_load_op
;
1627 VkImageLayout initial_layout
;
1628 VkImageLayout final_layout
;
1632 struct radv_render_pass
{
1633 uint32_t attachment_count
;
1634 uint32_t subpass_count
;
1635 VkAttachmentReference
* subpass_attachments
;
1636 struct radv_render_pass_attachment
* attachments
;
1637 struct radv_subpass_barrier end_barrier
;
1638 struct radv_subpass subpasses
[0];
1641 VkResult
radv_device_init_meta(struct radv_device
*device
);
1642 void radv_device_finish_meta(struct radv_device
*device
);
1644 struct radv_query_pool
{
1645 struct radeon_winsys_bo
*bo
;
1647 uint32_t availability_offset
;
1650 uint32_t pipeline_stats_mask
;
1653 struct radv_semaphore
{
1654 /* use a winsys sem for non-exportable */
1655 struct radeon_winsys_sem
*sem
;
1657 uint32_t temp_syncobj
;
1660 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1662 const VkSemaphore
*wait_sems
,
1663 int num_signal_sems
,
1664 const VkSemaphore
*signal_sems
,
1666 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1668 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1669 struct radv_descriptor_set
*set
,
1673 radv_update_descriptor_sets(struct radv_device
*device
,
1674 struct radv_cmd_buffer
*cmd_buffer
,
1675 VkDescriptorSet overrideSet
,
1676 uint32_t descriptorWriteCount
,
1677 const VkWriteDescriptorSet
*pDescriptorWrites
,
1678 uint32_t descriptorCopyCount
,
1679 const VkCopyDescriptorSet
*pDescriptorCopies
);
1682 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1683 struct radv_cmd_buffer
*cmd_buffer
,
1684 struct radv_descriptor_set
*set
,
1685 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1688 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1689 VkPipelineBindPoint pipelineBindPoint
,
1690 VkPipelineLayout _layout
,
1692 uint32_t descriptorWriteCount
,
1693 const VkWriteDescriptorSet
*pDescriptorWrites
);
1695 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1696 struct radv_image
*image
, uint32_t value
);
1697 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1698 struct radv_image
*image
, uint32_t value
);
1701 struct radeon_winsys_fence
*fence
;
1706 uint32_t temp_syncobj
;
1709 struct radeon_winsys_sem
;
1711 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1713 static inline struct __radv_type * \
1714 __radv_type ## _from_handle(__VkType _handle) \
1716 return (struct __radv_type *) _handle; \
1719 static inline __VkType \
1720 __radv_type ## _to_handle(struct __radv_type *_obj) \
1722 return (__VkType) _obj; \
1725 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1727 static inline struct __radv_type * \
1728 __radv_type ## _from_handle(__VkType _handle) \
1730 return (struct __radv_type *)(uintptr_t) _handle; \
1733 static inline __VkType \
1734 __radv_type ## _to_handle(struct __radv_type *_obj) \
1736 return (__VkType)(uintptr_t) _obj; \
1739 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1740 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1742 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1743 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1744 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1745 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1746 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1748 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1749 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1750 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1751 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1752 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1753 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1754 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1755 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1756 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1757 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1758 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1759 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1760 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1761 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1762 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1763 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1764 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1765 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1766 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1767 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1768 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1770 #endif /* RADV_PRIVATE_H */